BMS STM32 V4.0.0.0
This commit is contained in:
File diff suppressed because one or more lines are too long
File diff suppressed because one or more lines are too long
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,715 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
|
||||
|
||||
<SchemaVersion>2.1</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Targets>
|
||||
<Target>
|
||||
<TargetName>Target 1</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
|
||||
<uAC6>0</uAC6>
|
||||
<TargetOption>
|
||||
<TargetCommonOption>
|
||||
<Device>STM32F103RC</Device>
|
||||
<Vendor>STMicroelectronics</Vendor>
|
||||
<PackID>Keil.STM32F1xx_DFP.2.3.0</PackID>
|
||||
<PackURL>http://www.keil.com/pack/</PackURL>
|
||||
<Cpu>IRAM(0x20000000,0xC000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE</Cpu>
|
||||
<FlashUtilSpec></FlashUtilSpec>
|
||||
<StartupFile></StartupFile>
|
||||
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_512 -FS08000000 -FL080000 -FP0($$Device:STM32F103RC$Flash\STM32F10x_512.FLM))</FlashDriverDll>
|
||||
<DeviceId>4230</DeviceId>
|
||||
<RegisterFile>$$Device:STM32F103RC$Device\Include\stm32f10x.h</RegisterFile>
|
||||
<MemoryEnv></MemoryEnv>
|
||||
<Cmp></Cmp>
|
||||
<Asm></Asm>
|
||||
<Linker></Linker>
|
||||
<OHString></OHString>
|
||||
<InfinionOptionDll></InfinionOptionDll>
|
||||
<SLE66CMisc></SLE66CMisc>
|
||||
<SLE66AMisc></SLE66AMisc>
|
||||
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||
<SFDFile>$$Device:STM32F103RC$SVD\STM32F103xx.svd</SFDFile>
|
||||
<bCustSvd>0</bCustSvd>
|
||||
<UseEnv>0</UseEnv>
|
||||
<BinPath></BinPath>
|
||||
<IncludePath></IncludePath>
|
||||
<LibPath></LibPath>
|
||||
<RegisterFilePath></RegisterFilePath>
|
||||
<DBRegisterFilePath></DBRegisterFilePath>
|
||||
<TargetStatus>
|
||||
<Error>0</Error>
|
||||
<ExitCodeStop>0</ExitCodeStop>
|
||||
<ButtonStop>0</ButtonStop>
|
||||
<NotGenerated>0</NotGenerated>
|
||||
<InvalidFlash>1</InvalidFlash>
|
||||
</TargetStatus>
|
||||
<OutputDirectory>..\OBJ\</OutputDirectory>
|
||||
<OutputName>BT_BMS_V3.0</OutputName>
|
||||
<CreateExecutable>1</CreateExecutable>
|
||||
<CreateLib>0</CreateLib>
|
||||
<CreateHexFile>0</CreateHexFile>
|
||||
<DebugInformation>1</DebugInformation>
|
||||
<BrowseInformation>1</BrowseInformation>
|
||||
<ListingPath>.\Listings\</ListingPath>
|
||||
<HexFormatSelection>1</HexFormatSelection>
|
||||
<Merge32K>0</Merge32K>
|
||||
<CreateBatchFile>0</CreateBatchFile>
|
||||
<BeforeCompile>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopU1X>0</nStopU1X>
|
||||
<nStopU2X>0</nStopU2X>
|
||||
</BeforeCompile>
|
||||
<BeforeMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopB1X>0</nStopB1X>
|
||||
<nStopB2X>0</nStopB2X>
|
||||
</BeforeMake>
|
||||
<AfterMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name>$K\ARM\ARMCC\bin\fromelf.exe --bin --output=Bin\@L.bin !L</UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopA1X>0</nStopA1X>
|
||||
<nStopA2X>0</nStopA2X>
|
||||
</AfterMake>
|
||||
<SelectedForBatchBuild>0</SelectedForBatchBuild>
|
||||
<SVCSIdString></SVCSIdString>
|
||||
</TargetCommonOption>
|
||||
<CommonProperty>
|
||||
<UseCPPCompiler>0</UseCPPCompiler>
|
||||
<RVCTCodeConst>0</RVCTCodeConst>
|
||||
<RVCTZI>0</RVCTZI>
|
||||
<RVCTOtherData>0</RVCTOtherData>
|
||||
<ModuleSelection>0</ModuleSelection>
|
||||
<IncludeInBuild>1</IncludeInBuild>
|
||||
<AlwaysBuild>0</AlwaysBuild>
|
||||
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||
<PublicsOnly>0</PublicsOnly>
|
||||
<StopOnExitCode>3</StopOnExitCode>
|
||||
<CustomArgument></CustomArgument>
|
||||
<IncludeLibraryModules></IncludeLibraryModules>
|
||||
<ComprImg>1</ComprImg>
|
||||
</CommonProperty>
|
||||
<DllOption>
|
||||
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||
<SimDllArguments>-REMAP</SimDllArguments>
|
||||
<SimDlgDll>DCM.DLL</SimDlgDll>
|
||||
<SimDlgDllArguments>-pCM3</SimDlgDllArguments>
|
||||
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||
<TargetDllArguments></TargetDllArguments>
|
||||
<TargetDlgDll>TCM.DLL</TargetDlgDll>
|
||||
<TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
|
||||
</DllOption>
|
||||
<DebugOption>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
<Oh166RecLen>16</Oh166RecLen>
|
||||
</OPTHX>
|
||||
</DebugOption>
|
||||
<Utilities>
|
||||
<Flash1>
|
||||
<UseTargetDll>1</UseTargetDll>
|
||||
<UseExternalTool>0</UseExternalTool>
|
||||
<RunIndependent>0</RunIndependent>
|
||||
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||
<Capability>1</Capability>
|
||||
<DriverSelection>4096</DriverSelection>
|
||||
</Flash1>
|
||||
<bUseTDR>1</bUseTDR>
|
||||
<Flash2>BIN\UL2CM3.DLL</Flash2>
|
||||
<Flash3>"" ()</Flash3>
|
||||
<Flash4></Flash4>
|
||||
<pFcarmOut></pFcarmOut>
|
||||
<pFcarmGrp></pFcarmGrp>
|
||||
<pFcArmRoot></pFcArmRoot>
|
||||
<FcArmLst>0</FcArmLst>
|
||||
</Utilities>
|
||||
<TargetArmAds>
|
||||
<ArmAdsMisc>
|
||||
<GenerateListings>0</GenerateListings>
|
||||
<asHll>1</asHll>
|
||||
<asAsm>1</asAsm>
|
||||
<asMacX>1</asMacX>
|
||||
<asSyms>1</asSyms>
|
||||
<asFals>1</asFals>
|
||||
<asDbgD>1</asDbgD>
|
||||
<asForm>1</asForm>
|
||||
<ldLst>0</ldLst>
|
||||
<ldmm>1</ldmm>
|
||||
<ldXref>1</ldXref>
|
||||
<BigEnd>0</BigEnd>
|
||||
<AdsALst>1</AdsALst>
|
||||
<AdsACrf>1</AdsACrf>
|
||||
<AdsANop>0</AdsANop>
|
||||
<AdsANot>0</AdsANot>
|
||||
<AdsLLst>1</AdsLLst>
|
||||
<AdsLmap>1</AdsLmap>
|
||||
<AdsLcgr>1</AdsLcgr>
|
||||
<AdsLsym>1</AdsLsym>
|
||||
<AdsLszi>1</AdsLszi>
|
||||
<AdsLtoi>1</AdsLtoi>
|
||||
<AdsLsun>1</AdsLsun>
|
||||
<AdsLven>1</AdsLven>
|
||||
<AdsLsxf>1</AdsLsxf>
|
||||
<RvctClst>0</RvctClst>
|
||||
<GenPPlst>0</GenPPlst>
|
||||
<AdsCpuType>"Cortex-M3"</AdsCpuType>
|
||||
<RvctDeviceName></RvctDeviceName>
|
||||
<mOS>0</mOS>
|
||||
<uocRom>0</uocRom>
|
||||
<uocRam>0</uocRam>
|
||||
<hadIROM>1</hadIROM>
|
||||
<hadIRAM>1</hadIRAM>
|
||||
<hadXRAM>0</hadXRAM>
|
||||
<uocXRam>0</uocXRam>
|
||||
<RvdsVP>0</RvdsVP>
|
||||
<hadIRAM2>0</hadIRAM2>
|
||||
<hadIROM2>0</hadIROM2>
|
||||
<StupSel>8</StupSel>
|
||||
<useUlib>0</useUlib>
|
||||
<EndSel>0</EndSel>
|
||||
<uLtcg>0</uLtcg>
|
||||
<nSecure>0</nSecure>
|
||||
<RoSelD>3</RoSelD>
|
||||
<RwSelD>3</RwSelD>
|
||||
<CodeSel>0</CodeSel>
|
||||
<OptFeed>0</OptFeed>
|
||||
<NoZi1>0</NoZi1>
|
||||
<NoZi2>0</NoZi2>
|
||||
<NoZi3>0</NoZi3>
|
||||
<NoZi4>0</NoZi4>
|
||||
<NoZi5>0</NoZi5>
|
||||
<Ro1Chk>0</Ro1Chk>
|
||||
<Ro2Chk>0</Ro2Chk>
|
||||
<Ro3Chk>0</Ro3Chk>
|
||||
<Ir1Chk>1</Ir1Chk>
|
||||
<Ir2Chk>0</Ir2Chk>
|
||||
<Ra1Chk>0</Ra1Chk>
|
||||
<Ra2Chk>0</Ra2Chk>
|
||||
<Ra3Chk>0</Ra3Chk>
|
||||
<Im1Chk>1</Im1Chk>
|
||||
<Im2Chk>0</Im2Chk>
|
||||
<OnChipMemories>
|
||||
<Ocm1>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm1>
|
||||
<Ocm2>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm2>
|
||||
<Ocm3>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm3>
|
||||
<Ocm4>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm4>
|
||||
<Ocm5>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm5>
|
||||
<Ocm6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm6>
|
||||
<IRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0xc000</Size>
|
||||
</IRAM>
|
||||
<IROM>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x8000000</StartAddress>
|
||||
<Size>0x40000</Size>
|
||||
</IROM>
|
||||
<XRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</XRAM>
|
||||
<OCR_RVCT1>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT1>
|
||||
<OCR_RVCT2>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT2>
|
||||
<OCR_RVCT3>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT3>
|
||||
<OCR_RVCT4>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x8000000</StartAddress>
|
||||
<Size>0x40000</Size>
|
||||
</OCR_RVCT4>
|
||||
<OCR_RVCT5>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT5>
|
||||
<OCR_RVCT6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT6>
|
||||
<OCR_RVCT7>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT7>
|
||||
<OCR_RVCT8>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT8>
|
||||
<OCR_RVCT9>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0xc000</Size>
|
||||
</OCR_RVCT9>
|
||||
<OCR_RVCT10>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT10>
|
||||
</OnChipMemories>
|
||||
<RvctStartVector></RvctStartVector>
|
||||
</ArmAdsMisc>
|
||||
<Cads>
|
||||
<interw>1</interw>
|
||||
<Optim>4</Optim>
|
||||
<oTime>0</oTime>
|
||||
<SplitLS>0</SplitLS>
|
||||
<OneElfS>1</OneElfS>
|
||||
<Strict>0</Strict>
|
||||
<EnumInt>0</EnumInt>
|
||||
<PlainCh>0</PlainCh>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<wLevel>2</wLevel>
|
||||
<uThumb>0</uThumb>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<uC99>1</uC99>
|
||||
<useXO>0</useXO>
|
||||
<v6Lang>1</v6Lang>
|
||||
<v6LangP>1</v6LangP>
|
||||
<vShortEn>1</vShortEn>
|
||||
<vShortWch>1</vShortWch>
|
||||
<v6Lto>0</v6Lto>
|
||||
<v6WtE>0</v6WtE>
|
||||
<v6Rtti>0</v6Rtti>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define>STM32F10X_HD,USE_STDPERIPH_DRIVER</Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath>..\USER;..\CORE;..\STM32F10x_FWLIB\inc;..\MOUDLE;..\BSP</IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
<Aads>
|
||||
<interw>1</interw>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<thumb>0</thumb>
|
||||
<SplitLS>0</SplitLS>
|
||||
<SwStkChk>0</SwStkChk>
|
||||
<NoWarn>0</NoWarn>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<useXO>0</useXO>
|
||||
<uClangAs>0</uClangAs>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Aads>
|
||||
<LDads>
|
||||
<umfTarg>1</umfTarg>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<noStLib>0</noStLib>
|
||||
<RepFail>1</RepFail>
|
||||
<useFile>0</useFile>
|
||||
<TextAddressRange>0x08000000</TextAddressRange>
|
||||
<DataAddressRange>0x20000000</DataAddressRange>
|
||||
<pXoBase></pXoBase>
|
||||
<ScatterFile></ScatterFile>
|
||||
<IncludeLibs></IncludeLibs>
|
||||
<IncludeLibsPath></IncludeLibsPath>
|
||||
<Misc></Misc>
|
||||
<LinkerInputFile></LinkerInputFile>
|
||||
<DisabledWarnings></DisabledWarnings>
|
||||
</LDads>
|
||||
</TargetArmAds>
|
||||
</TargetOption>
|
||||
<Groups>
|
||||
<Group>
|
||||
<GroupName>CORE</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>core_cm3.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\CORE\core_cm3.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>startup_stm32f10x_hd.s</FileName>
|
||||
<FileType>2</FileType>
|
||||
<FilePath>..\CORE\startup_stm32f10x_hd.s</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>USER</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>main.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\main.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>global.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\global.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_it.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\stm32f10x_it.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>system_stm32f10x.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\system_stm32f10x.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>BSP</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>gpio.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\BSP\gpio.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tim.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\BSP\tim.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>uart.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\BSP\uart.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>i2c.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\BSP\i2c.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>spi.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\BSP\spi.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>flash.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\BSP\flash.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>rtc.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\BSP\rtc.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>systick.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\BSP\systick.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>can.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\BSP\can.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>adc.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\BSP\adc.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>pwm.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\BSP\pwm.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>wdg.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\BSP\wdg.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>MOUDLE</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>AFE_SH3673520.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\MOUDLE\AFE_SH3673520.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>RS485_Modbus.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\MOUDLE\RS485_Modbus.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>RS485_Modbus_Inverter.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\MOUDLE\RS485_Modbus_Inverter.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>NTC.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\MOUDLE\NTC.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>Screen.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\MOUDLE\Screen.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>GasGauge.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\MOUDLE\GasGauge.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>SOE.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\MOUDLE\SOE.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>OCV.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\MOUDLE\OCV.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>Status.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\MOUDLE\Status.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>MBO26A.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\MOUDLE\MBO26A.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>YiBang.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\MOUDLE\YiBang.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>H7690C.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\MOUDLE\H7690C.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>LBS_Transmit.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\MOUDLE\LBS_Transmit.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>OTA.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\MOUDLE\OTA.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>STM32F103x_FWLIB</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>misc.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\STM32F10x_FWLIB\src\misc.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_adc.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\STM32F10x_FWLIB\src\stm32f10x_adc.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_bkp.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\STM32F10x_FWLIB\src\stm32f10x_bkp.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_can.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\STM32F10x_FWLIB\src\stm32f10x_can.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_cec.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\STM32F10x_FWLIB\src\stm32f10x_cec.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_crc.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\STM32F10x_FWLIB\src\stm32f10x_crc.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_dac.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\STM32F10x_FWLIB\src\stm32f10x_dac.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_dbgmcu.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\STM32F10x_FWLIB\src\stm32f10x_dbgmcu.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_dma.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\STM32F10x_FWLIB\src\stm32f10x_dma.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_exti.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\STM32F10x_FWLIB\src\stm32f10x_exti.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_flash.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\STM32F10x_FWLIB\src\stm32f10x_flash.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_fsmc.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\STM32F10x_FWLIB\src\stm32f10x_fsmc.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_gpio.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\STM32F10x_FWLIB\src\stm32f10x_gpio.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_i2c.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\STM32F10x_FWLIB\src\stm32f10x_i2c.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_iwdg.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\STM32F10x_FWLIB\src\stm32f10x_iwdg.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_pwr.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\STM32F10x_FWLIB\src\stm32f10x_pwr.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_rcc.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\STM32F10x_FWLIB\src\stm32f10x_rcc.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_rtc.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\STM32F10x_FWLIB\src\stm32f10x_rtc.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_sdio.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\STM32F10x_FWLIB\src\stm32f10x_sdio.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_spi.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\STM32F10x_FWLIB\src\stm32f10x_spi.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_tim.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\STM32F10x_FWLIB\src\stm32f10x_tim.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_usart.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\STM32F10x_FWLIB\src\stm32f10x_usart.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>stm32f10x_wwdg.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\STM32F10x_FWLIB\src\stm32f10x_wwdg.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>README</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>readme.txt</FileName>
|
||||
<FileType>5</FileType>
|
||||
<FilePath>..\README\readme.txt</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>InverterProtocol</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>ProtocolSwitch_P1.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\PROTOCOL\ProtocolSwitch_P1.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>ProtocolSwitch_P2.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\PROTOCOL\ProtocolSwitch_P2.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
</Groups>
|
||||
</Target>
|
||||
</Targets>
|
||||
|
||||
<RTE>
|
||||
<apis/>
|
||||
<components/>
|
||||
<files/>
|
||||
</RTE>
|
||||
|
||||
</Project>
|
||||
@@ -0,0 +1,97 @@
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
// <h> Debug MCU Configuration
|
||||
// <o0.0> DBG_SLEEP
|
||||
// <i> Debug Sleep Mode
|
||||
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||
// <o0.1> DBG_STOP
|
||||
// <i> Debug Stop Mode
|
||||
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||
// <o0.2> DBG_STANDBY
|
||||
// <i> Debug Standby Mode
|
||||
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||
// <o0.8> DBG_IWDG_STOP
|
||||
// <i> Debug independent watchdog stopped when core is halted
|
||||
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||
// <o0.9> DBG_WWDG_STOP
|
||||
// <i> Debug window watchdog stopped when core is halted
|
||||
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||
// <o0.10> DBG_TIM1_STOP
|
||||
// <i> Timer 1 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||
// <o0.11> DBG_TIM2_STOP
|
||||
// <i> Timer 2 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||
// <o0.12> DBG_TIM3_STOP
|
||||
// <i> Timer 3 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||
// <o0.13> DBG_TIM4_STOP
|
||||
// <i> Timer 4 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||
// <o0.14> DBG_CAN1_STOP
|
||||
// <i> Debug CAN1 stopped when Core is halted
|
||||
// <i> 0: Same behavior as in normal mode
|
||||
// <i> 1: CAN1 receive registers are frozen
|
||||
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||
// <i> 0: Same behavior as in normal mode
|
||||
// <i> 1: The SMBUS timeout is frozen
|
||||
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||
// <i> 0: Same behavior as in normal mode
|
||||
// <i> 1: The SMBUS timeout is frozen
|
||||
// <o0.17> DBG_TIM8_STOP
|
||||
// <i> Timer 8 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||
// <o0.18> DBG_TIM5_STOP
|
||||
// <i> Timer 5 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||
// <o0.19> DBG_TIM6_STOP
|
||||
// <i> Timer 6 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||
// <o0.20> DBG_TIM7_STOP
|
||||
// <i> Timer 7 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||
// <o0.21> DBG_CAN2_STOP
|
||||
// <i> Debug CAN2 stopped when Core is halted
|
||||
// <i> 0: Same behavior as in normal mode
|
||||
// <i> 1: CAN2 receive registers are frozen
|
||||
// <o0.25> DBG_TIM12_STOP
|
||||
// <i> Timer 12 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||
// <o0.26> DBG_TIM13_STOP
|
||||
// <i> Timer 13 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||
// <o0.27> DBG_TIM14_STOP
|
||||
// <i> Timer 14 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||
// <o0.28> DBG_TIM9_STOP
|
||||
// <i> Timer 9 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||
// <o0.29> DBG_TIM10_STOP
|
||||
// <i> Timer 10 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||
// <o0.30> DBG_TIM11_STOP
|
||||
// <i> Timer 11 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||
// </h>
|
||||
DbgMCU_CR = 0x00000007;
|
||||
// <<< end of configuration section >>>
|
||||
@@ -0,0 +1,36 @@
|
||||
// File: STM32F101_102_103_105_107.dbgconf
|
||||
// Version: 1.0.0
|
||||
// Note: refer to STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx Reference manual (RM0008)
|
||||
// STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx datasheets
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <h> Debug MCU configuration register (DBGMCU_CR)
|
||||
// <i> Reserved bits must be kept at reset value
|
||||
// <o.30> DBG_TIM11_STOP <i> TIM11 counter stopped when core is halted
|
||||
// <o.29> DBG_TIM10_STOP <i> TIM10 counter stopped when core is halted
|
||||
// <o.28> DBG_TIM9_STOP <i> TIM9 counter stopped when core is halted
|
||||
// <o.27> DBG_TIM14_STOP <i> TIM14 counter stopped when core is halted
|
||||
// <o.26> DBG_TIM13_STOP <i> TIM13 counter stopped when core is halted
|
||||
// <o.25> DBG_TIM12_STOP <i> TIM12 counter stopped when core is halted
|
||||
// <o.21> DBG_CAN2_STOP <i> Debug CAN2 stopped when core is halted
|
||||
// <o.20> DBG_TIM7_STOP <i> TIM7 counter stopped when core is halted
|
||||
// <o.19> DBG_TIM6_STOP <i> TIM6 counter stopped when core is halted
|
||||
// <o.18> DBG_TIM5_STOP <i> TIM5 counter stopped when core is halted
|
||||
// <o.17> DBG_TIM8_STOP <i> TIM8 counter stopped when core is halted
|
||||
// <o.16> DBG_I2C2_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
|
||||
// <o.15> DBG_I2C1_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
|
||||
// <o.14> DBG_CAN1_STOP <i> Debug CAN1 stopped when Core is halted
|
||||
// <o.13> DBG_TIM4_STOP <i> TIM4 counter stopped when core is halted
|
||||
// <o.12> DBG_TIM3_STOP <i> TIM3 counter stopped when core is halted
|
||||
// <o.11> DBG_TIM2_STOP <i> TIM2 counter stopped when core is halted
|
||||
// <o.10> DBG_TIM1_STOP <i> TIM1 counter stopped when core is halted
|
||||
// <o.9> DBG_WWDG_STOP <i> Debug window watchdog stopped when core is halted
|
||||
// <o.8> DBG_IWDG_STOP <i> Debug independent watchdog stopped when core is halted
|
||||
// <o.2> DBG_STANDBY <i> Debug standby mode
|
||||
// <o.1> DBG_STOP <i> Debug stop mode
|
||||
// <o.0> DBG_SLEEP <i> Debug sleep mode
|
||||
// </h>
|
||||
DbgMCU_CR = 0x00000007;
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
@@ -0,0 +1,97 @@
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
// <h> Debug MCU Configuration
|
||||
// <o0.0> DBG_SLEEP
|
||||
// <i> Debug Sleep Mode
|
||||
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||
// <o0.1> DBG_STOP
|
||||
// <i> Debug Stop Mode
|
||||
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||
// <o0.2> DBG_STANDBY
|
||||
// <i> Debug Standby Mode
|
||||
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||
// <o0.8> DBG_IWDG_STOP
|
||||
// <i> Debug independent watchdog stopped when core is halted
|
||||
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||
// <o0.9> DBG_WWDG_STOP
|
||||
// <i> Debug window watchdog stopped when core is halted
|
||||
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||
// <o0.10> DBG_TIM1_STOP
|
||||
// <i> Timer 1 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||
// <o0.11> DBG_TIM2_STOP
|
||||
// <i> Timer 2 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||
// <o0.12> DBG_TIM3_STOP
|
||||
// <i> Timer 3 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||
// <o0.13> DBG_TIM4_STOP
|
||||
// <i> Timer 4 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||
// <o0.14> DBG_CAN1_STOP
|
||||
// <i> Debug CAN1 stopped when Core is halted
|
||||
// <i> 0: Same behavior as in normal mode
|
||||
// <i> 1: CAN1 receive registers are frozen
|
||||
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||
// <i> 0: Same behavior as in normal mode
|
||||
// <i> 1: The SMBUS timeout is frozen
|
||||
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||
// <i> 0: Same behavior as in normal mode
|
||||
// <i> 1: The SMBUS timeout is frozen
|
||||
// <o0.17> DBG_TIM8_STOP
|
||||
// <i> Timer 8 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||
// <o0.18> DBG_TIM5_STOP
|
||||
// <i> Timer 5 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||
// <o0.19> DBG_TIM6_STOP
|
||||
// <i> Timer 6 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||
// <o0.20> DBG_TIM7_STOP
|
||||
// <i> Timer 7 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||
// <o0.21> DBG_CAN2_STOP
|
||||
// <i> Debug CAN2 stopped when Core is halted
|
||||
// <i> 0: Same behavior as in normal mode
|
||||
// <i> 1: CAN2 receive registers are frozen
|
||||
// <o0.25> DBG_TIM12_STOP
|
||||
// <i> Timer 12 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||
// <o0.26> DBG_TIM13_STOP
|
||||
// <i> Timer 13 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||
// <o0.27> DBG_TIM14_STOP
|
||||
// <i> Timer 14 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||
// <o0.28> DBG_TIM9_STOP
|
||||
// <i> Timer 9 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||
// <o0.29> DBG_TIM10_STOP
|
||||
// <i> Timer 10 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||
// <o0.30> DBG_TIM11_STOP
|
||||
// <i> Timer 11 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||
// </h>
|
||||
DbgMCU_CR = 0x00000007;
|
||||
// <<< end of configuration section >>>
|
||||
@@ -0,0 +1,97 @@
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
// <h> Debug MCU Configuration
|
||||
// <o0.0> DBG_SLEEP
|
||||
// <i> Debug Sleep Mode
|
||||
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
|
||||
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
|
||||
// <o0.1> DBG_STOP
|
||||
// <i> Debug Stop Mode
|
||||
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
|
||||
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||
// <o0.2> DBG_STANDBY
|
||||
// <i> Debug Standby Mode
|
||||
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
|
||||
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
|
||||
// <o0.8> DBG_IWDG_STOP
|
||||
// <i> Debug independent watchdog stopped when core is halted
|
||||
// <i> 0: The watchdog counter clock continues even if the core is halted
|
||||
// <i> 1: The watchdog counter clock is stopped when the core is halted
|
||||
// <o0.9> DBG_WWDG_STOP
|
||||
// <i> Debug window watchdog stopped when core is halted
|
||||
// <i> 0: The window watchdog counter clock continues even if the core is halted
|
||||
// <i> 1: The window watchdog counter clock is stopped when the core is halted
|
||||
// <o0.10> DBG_TIM1_STOP
|
||||
// <i> Timer 1 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||
// <o0.11> DBG_TIM2_STOP
|
||||
// <i> Timer 2 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||
// <o0.12> DBG_TIM3_STOP
|
||||
// <i> Timer 3 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||
// <o0.13> DBG_TIM4_STOP
|
||||
// <i> Timer 4 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
|
||||
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
|
||||
// <o0.14> DBG_CAN1_STOP
|
||||
// <i> Debug CAN1 stopped when Core is halted
|
||||
// <i> 0: Same behavior as in normal mode
|
||||
// <i> 1: CAN1 receive registers are frozen
|
||||
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
|
||||
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
|
||||
// <i> 0: Same behavior as in normal mode
|
||||
// <i> 1: The SMBUS timeout is frozen
|
||||
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
|
||||
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
|
||||
// <i> 0: Same behavior as in normal mode
|
||||
// <i> 1: The SMBUS timeout is frozen
|
||||
// <o0.17> DBG_TIM8_STOP
|
||||
// <i> Timer 8 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||
// <o0.18> DBG_TIM5_STOP
|
||||
// <i> Timer 5 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||
// <o0.19> DBG_TIM6_STOP
|
||||
// <i> Timer 6 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||
// <o0.20> DBG_TIM7_STOP
|
||||
// <i> Timer 7 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||
// <o0.21> DBG_CAN2_STOP
|
||||
// <i> Debug CAN2 stopped when Core is halted
|
||||
// <i> 0: Same behavior as in normal mode
|
||||
// <i> 1: CAN2 receive registers are frozen
|
||||
// <o0.25> DBG_TIM12_STOP
|
||||
// <i> Timer 12 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||
// <o0.26> DBG_TIM13_STOP
|
||||
// <i> Timer 13 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||
// <o0.27> DBG_TIM14_STOP
|
||||
// <i> Timer 14 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||
// <o0.28> DBG_TIM9_STOP
|
||||
// <i> Timer 9 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||
// <o0.29> DBG_TIM10_STOP
|
||||
// <i> Timer 10 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||
// <o0.30> DBG_TIM11_STOP
|
||||
// <i> Timer 11 counter stopped when core is halted
|
||||
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
|
||||
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
|
||||
// </h>
|
||||
DbgMCU_CR = 0x00000007;
|
||||
// <<< end of configuration section >>>
|
||||
@@ -0,0 +1,36 @@
|
||||
// File: STM32F101_102_103_105_107.dbgconf
|
||||
// Version: 1.0.0
|
||||
// Note: refer to STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx Reference manual (RM0008)
|
||||
// STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx datasheets
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <h> Debug MCU configuration register (DBGMCU_CR)
|
||||
// <i> Reserved bits must be kept at reset value
|
||||
// <o.30> DBG_TIM11_STOP <i> TIM11 counter stopped when core is halted
|
||||
// <o.29> DBG_TIM10_STOP <i> TIM10 counter stopped when core is halted
|
||||
// <o.28> DBG_TIM9_STOP <i> TIM9 counter stopped when core is halted
|
||||
// <o.27> DBG_TIM14_STOP <i> TIM14 counter stopped when core is halted
|
||||
// <o.26> DBG_TIM13_STOP <i> TIM13 counter stopped when core is halted
|
||||
// <o.25> DBG_TIM12_STOP <i> TIM12 counter stopped when core is halted
|
||||
// <o.21> DBG_CAN2_STOP <i> Debug CAN2 stopped when core is halted
|
||||
// <o.20> DBG_TIM7_STOP <i> TIM7 counter stopped when core is halted
|
||||
// <o.19> DBG_TIM6_STOP <i> TIM6 counter stopped when core is halted
|
||||
// <o.18> DBG_TIM5_STOP <i> TIM5 counter stopped when core is halted
|
||||
// <o.17> DBG_TIM8_STOP <i> TIM8 counter stopped when core is halted
|
||||
// <o.16> DBG_I2C2_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
|
||||
// <o.15> DBG_I2C1_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
|
||||
// <o.14> DBG_CAN1_STOP <i> Debug CAN1 stopped when Core is halted
|
||||
// <o.13> DBG_TIM4_STOP <i> TIM4 counter stopped when core is halted
|
||||
// <o.12> DBG_TIM3_STOP <i> TIM3 counter stopped when core is halted
|
||||
// <o.11> DBG_TIM2_STOP <i> TIM2 counter stopped when core is halted
|
||||
// <o.10> DBG_TIM1_STOP <i> TIM1 counter stopped when core is halted
|
||||
// <o.9> DBG_WWDG_STOP <i> Debug window watchdog stopped when core is halted
|
||||
// <o.8> DBG_IWDG_STOP <i> Debug independent watchdog stopped when core is halted
|
||||
// <o.2> DBG_STANDBY <i> Debug standby mode
|
||||
// <o.1> DBG_STOP <i> Debug stop mode
|
||||
// <o.0> DBG_SLEEP <i> Debug sleep mode
|
||||
// </h>
|
||||
DbgMCU_CR = 0x00000007;
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
@@ -0,0 +1,9 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
|
||||
<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
|
||||
|
||||
<component name="EventRecorderStub" version="1.0.0"/> <!--name and version of the component-->
|
||||
<events>
|
||||
</events>
|
||||
|
||||
</component_viewer>
|
||||
+3347
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,39 @@
|
||||
[BREAKPOINTS]
|
||||
ForceImpTypeAny = 0
|
||||
ShowInfoWin = 1
|
||||
EnableFlashBP = 2
|
||||
BPDuringExecution = 0
|
||||
[CFI]
|
||||
CFISize = 0x00
|
||||
CFIAddr = 0x00
|
||||
[CPU]
|
||||
MonModeVTableAddr = 0xFFFFFFFF
|
||||
MonModeDebug = 0
|
||||
MaxNumAPs = 0
|
||||
LowPowerHandlingMode = 0
|
||||
OverrideMemMap = 0
|
||||
AllowSimulation = 1
|
||||
ScriptFile=""
|
||||
[FLASH]
|
||||
CacheExcludeSize = 0x00
|
||||
CacheExcludeAddr = 0x00
|
||||
MinNumBytesFlashDL = 0
|
||||
SkipProgOnCRCMatch = 1
|
||||
VerifyDownload = 1
|
||||
AllowCaching = 1
|
||||
EnableFlashDL = 2
|
||||
Override = 0
|
||||
Device="ARM7"
|
||||
[GENERAL]
|
||||
WorkRAMSize = 0x00
|
||||
WorkRAMAddr = 0x00
|
||||
RAMUsageLimit = 0x00
|
||||
[SWO]
|
||||
SWOLogFile=""
|
||||
[MEM]
|
||||
RdOverrideOrMask = 0x00
|
||||
RdOverrideAndMask = 0xFFFFFFFF
|
||||
RdOverrideAddr = 0xFFFFFFFF
|
||||
WrOverrideOrMask = 0x00
|
||||
WrOverrideAndMask = 0xFFFFFFFF
|
||||
WrOverrideAddr = 0xFFFFFFFF
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,36 @@
|
||||
// File: STM32F101_102_103_105_107.dbgconf
|
||||
// Version: 1.0.0
|
||||
// Note: refer to STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx Reference manual (RM0008)
|
||||
// STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx datasheets
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <h> Debug MCU configuration register (DBGMCU_CR)
|
||||
// <i> Reserved bits must be kept at reset value
|
||||
// <o.30> DBG_TIM11_STOP <i> TIM11 counter stopped when core is halted
|
||||
// <o.29> DBG_TIM10_STOP <i> TIM10 counter stopped when core is halted
|
||||
// <o.28> DBG_TIM9_STOP <i> TIM9 counter stopped when core is halted
|
||||
// <o.27> DBG_TIM14_STOP <i> TIM14 counter stopped when core is halted
|
||||
// <o.26> DBG_TIM13_STOP <i> TIM13 counter stopped when core is halted
|
||||
// <o.25> DBG_TIM12_STOP <i> TIM12 counter stopped when core is halted
|
||||
// <o.21> DBG_CAN2_STOP <i> Debug CAN2 stopped when core is halted
|
||||
// <o.20> DBG_TIM7_STOP <i> TIM7 counter stopped when core is halted
|
||||
// <o.19> DBG_TIM6_STOP <i> TIM6 counter stopped when core is halted
|
||||
// <o.18> DBG_TIM5_STOP <i> TIM5 counter stopped when core is halted
|
||||
// <o.17> DBG_TIM8_STOP <i> TIM8 counter stopped when core is halted
|
||||
// <o.16> DBG_I2C2_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
|
||||
// <o.15> DBG_I2C1_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
|
||||
// <o.14> DBG_CAN1_STOP <i> Debug CAN1 stopped when Core is halted
|
||||
// <o.13> DBG_TIM4_STOP <i> TIM4 counter stopped when core is halted
|
||||
// <o.12> DBG_TIM3_STOP <i> TIM3 counter stopped when core is halted
|
||||
// <o.11> DBG_TIM2_STOP <i> TIM2 counter stopped when core is halted
|
||||
// <o.10> DBG_TIM1_STOP <i> TIM1 counter stopped when core is halted
|
||||
// <o.9> DBG_WWDG_STOP <i> Debug window watchdog stopped when core is halted
|
||||
// <o.8> DBG_IWDG_STOP <i> Debug independent watchdog stopped when core is halted
|
||||
// <o.2> DBG_STANDBY <i> Debug standby mode
|
||||
// <o.1> DBG_STOP <i> Debug stop mode
|
||||
// <o.0> DBG_SLEEP <i> Debug sleep mode
|
||||
// </h>
|
||||
DbgMCU_CR = 0x00000007;
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
@@ -0,0 +1,36 @@
|
||||
// File: STM32F101_102_103_105_107.dbgconf
|
||||
// Version: 1.0.0
|
||||
// Note: refer to STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx Reference manual (RM0008)
|
||||
// STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx datasheets
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
|
||||
// <h> Debug MCU configuration register (DBGMCU_CR)
|
||||
// <i> Reserved bits must be kept at reset value
|
||||
// <o.30> DBG_TIM11_STOP <i> TIM11 counter stopped when core is halted
|
||||
// <o.29> DBG_TIM10_STOP <i> TIM10 counter stopped when core is halted
|
||||
// <o.28> DBG_TIM9_STOP <i> TIM9 counter stopped when core is halted
|
||||
// <o.27> DBG_TIM14_STOP <i> TIM14 counter stopped when core is halted
|
||||
// <o.26> DBG_TIM13_STOP <i> TIM13 counter stopped when core is halted
|
||||
// <o.25> DBG_TIM12_STOP <i> TIM12 counter stopped when core is halted
|
||||
// <o.21> DBG_CAN2_STOP <i> Debug CAN2 stopped when core is halted
|
||||
// <o.20> DBG_TIM7_STOP <i> TIM7 counter stopped when core is halted
|
||||
// <o.19> DBG_TIM6_STOP <i> TIM6 counter stopped when core is halted
|
||||
// <o.18> DBG_TIM5_STOP <i> TIM5 counter stopped when core is halted
|
||||
// <o.17> DBG_TIM8_STOP <i> TIM8 counter stopped when core is halted
|
||||
// <o.16> DBG_I2C2_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
|
||||
// <o.15> DBG_I2C1_SMBUS_TIMEOUT <i> SMBUS timeout mode stopped when core is halted
|
||||
// <o.14> DBG_CAN1_STOP <i> Debug CAN1 stopped when Core is halted
|
||||
// <o.13> DBG_TIM4_STOP <i> TIM4 counter stopped when core is halted
|
||||
// <o.12> DBG_TIM3_STOP <i> TIM3 counter stopped when core is halted
|
||||
// <o.11> DBG_TIM2_STOP <i> TIM2 counter stopped when core is halted
|
||||
// <o.10> DBG_TIM1_STOP <i> TIM1 counter stopped when core is halted
|
||||
// <o.9> DBG_WWDG_STOP <i> Debug window watchdog stopped when core is halted
|
||||
// <o.8> DBG_IWDG_STOP <i> Debug independent watchdog stopped when core is halted
|
||||
// <o.2> DBG_STANDBY <i> Debug standby mode
|
||||
// <o.1> DBG_STOP <i> Debug stop mode
|
||||
// <o.0> DBG_SLEEP <i> Debug sleep mode
|
||||
// </h>
|
||||
DbgMCU_CR = 0x00000007;
|
||||
|
||||
// <<< end of configuration section >>>
|
||||
+1493
File diff suppressed because it is too large
Load Diff
+1699
File diff suppressed because it is too large
Load Diff
+545
@@ -0,0 +1,545 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file main.c
|
||||
* @author BMS
|
||||
* @version V1.0.0
|
||||
* @date 20-5-2022
|
||||
* @brief Main program body.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2011 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
#include "global.h"
|
||||
#include "rtc.h"
|
||||
#include "soe.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Examples
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO_IOToggle
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief Main program.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
int main(void)
|
||||
{
|
||||
#if Key_PressLong
|
||||
POWER_Check();
|
||||
#endif
|
||||
|
||||
delay_ms(1000); //上电之后加1S延时，防止WK唤醒误动
|
||||
|
||||
//SCB->VTOR = FLASH_BASE | 0x1800;
|
||||
|
||||
uf_GPIO_Init();
|
||||
uf_EXTI_Init();
|
||||
uf_TIM3_Init(); //10MS
|
||||
uf_I2C1_Init();
|
||||
uf_SPI2_Init();
|
||||
uf_CAN1_Init();
|
||||
|
||||
uf_ADC_Init();
|
||||
|
||||
uf_IWDG_Init(7,1250); //分频数=7,重载值=1250,溢出时间=((4*2^7)*1250)/40=16000ms=16s
|
||||
|
||||
#if Key_PressLong
|
||||
LED_ALL_ON(); //按钮长按模式，需要先灭再常亮
|
||||
#endif
|
||||
|
||||
uf_FLASH_Init();
|
||||
uf_GLOBAL_Init();
|
||||
|
||||
/*三选一模块*/
|
||||
#if BLE_Conn
|
||||
BLE_Init(); //蓝牙初始化
|
||||
BLE_IO_Init();
|
||||
BLE_Open();
|
||||
#endif
|
||||
#if WIFI_Conn
|
||||
WIFI_Init(); //WIFI初始化
|
||||
WIFI_IO_Init();
|
||||
WIFI_Open();
|
||||
#endif
|
||||
#if LTE_Conn
|
||||
LTE_4G_Init(); //4G初始化
|
||||
LTE_4G_IO_Init();
|
||||
LTE_4G_Open();
|
||||
#endif
|
||||
|
||||
// BAL_Off(); //默认关闭外置主动均衡(钰泰)
|
||||
|
||||
MODBUS_Init();
|
||||
MODBUS1_Init();
|
||||
|
||||
AFE_VoltageProcess();
|
||||
InitGasGauge();
|
||||
|
||||
MCU_TemperaProcess();
|
||||
MODBUS_Poll_Init();
|
||||
|
||||
Screen_Init(); //[陶晶驰]
|
||||
|
||||
if(uf_RTC_Init()==1) //RTC时钟初始化，超时说明晶振有问题
|
||||
{
|
||||
LSEErrFlag=1;
|
||||
sleep_Moni_Count=SLEEP_MON_CNT;
|
||||
}
|
||||
else
|
||||
{
|
||||
RTC_Get();
|
||||
}
|
||||
|
||||
while (1)
|
||||
{
|
||||
//5*10ms
|
||||
if(TIMER_IsOut(tmrTemp[0],5))
|
||||
{
|
||||
tmrTemp[0] = TIMER_Update();
|
||||
|
||||
/*三选一模块：蓝牙*/
|
||||
#if BLE_Conn
|
||||
BLE_IQ_Update(); //更新数据
|
||||
BLE_IQ_Transmit(); //发送数据，每0.05s执行一次
|
||||
#endif
|
||||
}
|
||||
|
||||
//10*10ms
|
||||
if(TIMER_IsOut(tmrTemp[1],10))
|
||||
{
|
||||
tmrTemp[1] = TIMER_Update();
|
||||
|
||||
/*三选一模块：WIFI*/
|
||||
#if WIFI_Conn
|
||||
WIFI_IQ_Update(); //更新数据
|
||||
WIFI_IQ_Transmit(); //发送数据，每0.1s执行一次
|
||||
#endif
|
||||
}
|
||||
|
||||
//25*10ms
|
||||
if(TIMER_IsOut(tmrTemp[2],25))
|
||||
{
|
||||
tmrTemp[2] = TIMER_Update();
|
||||
AFE_CurrentProcess(); //1s读4次电流后取平均值
|
||||
|
||||
#if Key_PressLong
|
||||
if(OFF_confirm_flg == 1) //若确认关机，此时把所有灯灭掉，提醒松开就会关机
|
||||
{
|
||||
LED_ALL_OFF();
|
||||
}
|
||||
else if(RST_confirm_flg == 1) //若按键摁下执行复位，灯被接管闪烁
|
||||
{
|
||||
LED_RST_Toggle();
|
||||
}
|
||||
else if(ON_confirm_flg != 0) //虚地址运行灯快速闪烁
|
||||
{
|
||||
if(sleep_flag == 0)
|
||||
{
|
||||
if(curLimitFlag == 0)
|
||||
{
|
||||
if(bmsMem.E2_485Addr > AddrMax)
|
||||
{
|
||||
LED_RUN_Toggle();
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/*三选一模块：4G*/
|
||||
#if LTE_Conn
|
||||
if((LTE_WarmDelay == 0) && (LTE_ResendDelay == 0) && (LTE_WaitRxDelay == 0) && (LTE_PinRST_Flag == 0) && (LTE_sleep_flag == 0)) //不在等候+不在引脚重启+不在休眠
|
||||
{
|
||||
if(MQTT_READY_flag == 0) //未通信MQTT
|
||||
{
|
||||
if(LTE_LINK_flag == 1)
|
||||
{
|
||||
LTE_4G_IQ_Update(); //更新数据
|
||||
LTE_4G_IQ_Transmit(); //发送数据，每0.25s执行一次
|
||||
}
|
||||
}
|
||||
else //已通信MQTT
|
||||
{
|
||||
if((pre_sleep_flag == 4) || (LTE_status == event_pub) || (LTE_status == srvc_pub) || (LTE_status == setPara_pub) || (LTE_status == getPara_pub))
|
||||
{
|
||||
LTE_4G_IQ_Update(); //更新数据
|
||||
LTE_4G_IQ_Transmit(); //发送数据，每0.25s执行一次
|
||||
}
|
||||
else if(LTE_OTA_Flag == 1)
|
||||
{
|
||||
LTE_OTA_IQ_Update(); //更新数据
|
||||
LTE_OTA_IQ_Transmit(); //发送数据，每0.25s执行一次
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
CALI_CurrentProcess(); //收到校准指令后进行更新，并回复
|
||||
|
||||
//50*10ms
|
||||
if(TIMER_IsOut(tmrTemp[3],50))
|
||||
{
|
||||
tmrTemp[3] = TIMER_Update();
|
||||
|
||||
//LED 运行灯
|
||||
#if Key_PressLong
|
||||
if((ON_confirm_flg != 0) && (RST_confirm_flg != 1) && (OFF_confirm_flg != 1))
|
||||
#endif
|
||||
{
|
||||
if(sleep_flag == 0)
|
||||
{
|
||||
if(curLimitFlag == 0)
|
||||
{
|
||||
if((bmsMem.E2_485Addr >= 1) && (bmsMem.E2_485Addr <= AddrMax))
|
||||
{
|
||||
LED_RUN_Toggle(); //正常地址运行灯正常闪烁
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
LED_RUN_On(); //限流常亮灯
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
LED_RUN_Off(); //休眠不亮灯
|
||||
}
|
||||
}
|
||||
|
||||
//LED报警灯
|
||||
#if Key_PressLong
|
||||
if((ON_confirm_flg != 0) && (RST_confirm_flg != 1) && (OFF_confirm_flg != 1))
|
||||
#endif
|
||||
{
|
||||
if((bAlarmFlag == 0) && (((bmsMem.bStatus2 & 0x00e0) ==0) && ((bmsMem.temperaStatus & 0x0040) ==0))) //无保护
|
||||
{
|
||||
if(((bmsMem.bStatus2 & 0xff00) != 0) || ((bmsMem.bStatus3 & 0x3A00) != 0) || ((bmsMem.temperaStatus & 0xf000) != 0)) //有报警(除了单体过压告警和总体过压告警)
|
||||
{
|
||||
if(sleep_flag == 0) LED_ALARM_Toggle();
|
||||
else LED_ALARM_Off();
|
||||
}
|
||||
else if((bmsMem.bStatus3 & 0x0500) != 0) //单体过压告警和总体过压告警
|
||||
{
|
||||
if(bmsMem.soc<99) //在正常工作时，发生[过压保护]，正常显示
|
||||
{
|
||||
if(sleep_flag == 0) LED_ALARM_Toggle();
|
||||
else LED_ALARM_Off();
|
||||
}
|
||||
else
|
||||
{
|
||||
LED_ALARM_Off();
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//主机轮询从机
|
||||
#if Key_PressLong
|
||||
if(OFF_confirm_flg != 1)
|
||||
#endif
|
||||
{
|
||||
if(sleep_flag == 0) //休眠时，主从通信禁用 //确认关机后，停止通信
|
||||
{
|
||||
//主机在3.4口向下通讯
|
||||
if((bmsMem.E2_485Addr == 1) && (paraMem.PACK_NUM >= 2) && (PollStop_flag == 0))
|
||||
{
|
||||
#if Addr_SetAuto
|
||||
//开机后地址可能从1变2，先等待2s
|
||||
if((paraMem.addr_FREE_Flg == 0) && (assignAddr_relay > 0))
|
||||
{
|
||||
assignAddr_relay--;
|
||||
}
|
||||
|
||||
else if((paraMem.addr_FREE_Flg == 0) && ((assignAddr_State == 0) || (assignAddr_State == 1)))
|
||||
{
|
||||
MODBUS_AddrAssign_Tx(); //(主机自动分配从机地址，结束了再进行下一操作)
|
||||
}
|
||||
else if((paraMem.addr_FREE_Flg == 0) && ((assignAddr_State == 2) && (assignAddr_WrIndex_Flg == 1)))
|
||||
{
|
||||
assignAddr_WrIndex_Flg = 0;
|
||||
MODBUS_WrIndex_Tx(); //主机广播队列标志数
|
||||
}
|
||||
|
||||
else
|
||||
#endif
|
||||
{
|
||||
if(sdwa_WrAddr_Flg == 1)//(主机屏幕写从机地址，结束了再进行下一操作)
|
||||
{
|
||||
MODBUS_Screen_WrSlaveAddr_Tx();
|
||||
}
|
||||
|
||||
else if((ConfigData_Index>=2) && (ConfigData_Index<=paraMem.PACK_NUM))
|
||||
{
|
||||
MODBUS_Config_RdSlave_Tx();//(上位机持续读单一从机，上位机比屏幕优先级高)
|
||||
}
|
||||
else if((scr_RdData_Index>=2) && (scr_RdData_Index<=paraMem.PACK_NUM))
|
||||
{
|
||||
MODBUS_Screen_RdSlave_Tx();//(屏幕持续读单一从机)
|
||||
}
|
||||
else
|
||||
{
|
||||
MODBUS_MASTER_Polling_Tx();//(轮询,是默认状态)
|
||||
}
|
||||
}
|
||||
}
|
||||
//主机暂停轮询在收不到之后的30s恢复
|
||||
else if(PollStop_flag == 1)
|
||||
{
|
||||
PollStop_count++;
|
||||
if(PollStop_count > 30)
|
||||
{
|
||||
PollStop_count = 0;
|
||||
PollStop_flag = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//100*10ms
|
||||
if(TIMER_IsOut(tmrTemp[4],100))
|
||||
{
|
||||
tmrTemp[4] = TIMER_Update();
|
||||
AFE_VoltageProcess();
|
||||
AFE_TemperaProcess();
|
||||
MCU_TemperaProcess();
|
||||
AFE_ProtectProcess();
|
||||
|
||||
IWDG_Feed(); //程序运行正常,进行喂狗
|
||||
|
||||
#if Key_PressLong
|
||||
POWER_Ctrl();
|
||||
#endif
|
||||
|
||||
#if Key_PressLong
|
||||
if(OFF_confirm_flg == 1)
|
||||
{
|
||||
CTRL_Off(); //关闭充放MOS
|
||||
delay_ms(2);
|
||||
|
||||
CHG_LIMIT_Off(); //关闭限流
|
||||
curLimitFlag = 0;
|
||||
delay_ms(2);
|
||||
|
||||
PCHG_Off(); //关闭预充
|
||||
TSC_detectFlag = 0;
|
||||
PCHG_startFlag = 0;
|
||||
PCHG_Flag = 0;
|
||||
delay_ms(2);
|
||||
|
||||
// BAL_Off(); //关闭均衡
|
||||
// balancing = 0;
|
||||
}
|
||||
else
|
||||
#endif
|
||||
{
|
||||
// MCU_BalanceProcess();
|
||||
CHG_LIMIT_Ctrl();
|
||||
|
||||
if(TSC_detectFlag == 1)
|
||||
{
|
||||
TSC_Detect(); //充接口开路或短路检测，开路检测
|
||||
}
|
||||
else if(PCHG_startFlag == 0)
|
||||
{
|
||||
PCHG_StartCtrl(); //启动预充(约1s检测开短路)
|
||||
}
|
||||
else if(MOS_Close_Flg == 0)
|
||||
{
|
||||
AFE_Ctrl(); //正常(开放电MOS前开预充，并检测真短路)
|
||||
}
|
||||
}
|
||||
|
||||
OCV_CaliSOC();
|
||||
ParaChange();
|
||||
|
||||
GaugeManage();
|
||||
|
||||
canMem_refresh();
|
||||
onlineMem_refresh();
|
||||
|
||||
#if Key_PressLong
|
||||
if(OFF_confirm_flg != 1)
|
||||
#endif
|
||||
{
|
||||
//当屏亮，而上位机在通过主机看从机，屏幕查看地址返回原值
|
||||
if(ConfigData_Index != 1)
|
||||
{
|
||||
scr_RdData_Index = bmsMem.E2_485Addr;
|
||||
}
|
||||
|
||||
//更新屏幕信息(息屏由[陶晶驰]自己做)
|
||||
if(sleep_flag == 0) Screen_IQ_Transmit(); //每1s更新1次屏幕数据
|
||||
}
|
||||
|
||||
//逆变器协议数据更新
|
||||
if(bmsMem.E2_485Addr == 1)
|
||||
{
|
||||
#if Key_PressLong
|
||||
if(OFF_confirm_flg != 1)
|
||||
#endif
|
||||
{
|
||||
if(sleep_flag == 0) CAN_UpdateData();
|
||||
if(sleep_flag == 0) MODBUS1_UpdateData();
|
||||
}
|
||||
}
|
||||
|
||||
if(LSEErrFlag!=1)
|
||||
{
|
||||
uf_RTC_Update(); //写时间或需要等待长时间，可能返回1，所以就不用这里来判断晶振了
|
||||
RTC_Get(); //时间更新每1s执行1次，若时钟持续10次都不走，可以认为晶振有问题
|
||||
}
|
||||
|
||||
/*三选一模块：4G*/
|
||||
#if LTE_Conn
|
||||
Check_eventChange(); //因为要加上时间，所以放在读时间后面
|
||||
|
||||
//开机等待or引脚重启等待
|
||||
if(LTE_WarmDelay > 0)
|
||||
{
|
||||
LTE_WarmDelay--;
|
||||
}
|
||||
//延迟下次发送等待
|
||||
else if(LTE_ResendDelay > 0)
|
||||
{
|
||||
LTE_ResendDelay--;
|
||||
}
|
||||
else if(LTE_WaitRxDelay > 0)
|
||||
{
|
||||
LTE_WaitRxDelay--;
|
||||
}
|
||||
//引脚重启
|
||||
else if(LTE_PinRST_Flag != 0)
|
||||
{
|
||||
if(LTE_PinRST_Flag == 1)
|
||||
{
|
||||
LTE_PinRST_Flag = 2;
|
||||
LTE_4G_Close();
|
||||
}
|
||||
else
|
||||
{
|
||||
LTE_PinRST_Flag = 0;
|
||||
LTE_4G_Init();
|
||||
LTE_4G_Open();
|
||||
}
|
||||
}
|
||||
//休眠
|
||||
else if(LTE_sleep_flag != 0)
|
||||
{
|
||||
if(LTE_sleep_flag == 1) //1:准备休眠
|
||||
{
|
||||
LTE_sleep_flag = 2; //2:正在休眠
|
||||
LTE_4G_Close(); //关闭4G模块
|
||||
}
|
||||
else if(LTE_sleep_flag == 0xAA) //0xAA:退出休眠，执行1次开机4G模块
|
||||
{
|
||||
LTE_sleep_flag = 0;
|
||||
LTE_4G_Init();
|
||||
LTE_4G_Open(); //启动4G模块
|
||||
|
||||
pre_sleep_flag = 0xA0; //上线后，上报退出休眠事件
|
||||
sleepOff_time=timecount;
|
||||
}
|
||||
}
|
||||
//正常通信or休眠前置步骤
|
||||
else
|
||||
{
|
||||
//休眠前置步骤执行倒计时
|
||||
if((pre_sleep_flag >=2) && (pre_sleep_flag <= 5))
|
||||
{
|
||||
pre_sleep_waitCnt++;
|
||||
if(pre_sleep_waitCnt > 60)
|
||||
{
|
||||
pre_sleep_waitCnt = 0;
|
||||
pre_sleep_flag = 0;
|
||||
LTE_sleep_flag = 1; //1min内前置一直卡住，直接执行休眠
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
pre_sleep_waitCnt = 0;
|
||||
}
|
||||
|
||||
if(MQTT_READY_flag == 0) //未通信MQTT
|
||||
{
|
||||
if(LTE_LINK_flag == 0)
|
||||
{
|
||||
LTE_4G_IQ_Update(); //更新数据
|
||||
LTE_4G_IQ_Transmit(); //发送数据，每1s执行一次
|
||||
}
|
||||
}
|
||||
else //已通信MQTT
|
||||
{
|
||||
if((pre_sleep_flag != 4) && (LTE_OTA_Flag != 1) && (LTE_status != event_pub) && (LTE_status != srvc_pub) && (LTE_status != setPara_pub) && (LTE_status != getPara_pub))
|
||||
{
|
||||
LTE_4G_IQ_Update(); //更新数据
|
||||
LTE_4G_IQ_Transmit(); //发送数据，每1s执行一次
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
//需要及时响应的动作，直接放入while主循环里
|
||||
Addr_Set(); //地址写入
|
||||
RTC_BackUp(); //因各种情况触发的时间备份
|
||||
|
||||
//屏幕接收
|
||||
#if Key_PressLong
|
||||
if(OFF_confirm_flg != 1)
|
||||
{
|
||||
if(Screen_RevHandlerFlg == 1)
|
||||
{
|
||||
Screen_RevHandlerFlg = 0;
|
||||
Screen_IT_Update();
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
SCR_KeepLight0(); //判断关机时收到数据屏幕也不能维持灯0
|
||||
}
|
||||
#else
|
||||
if(Screen_RevHandlerFlg == 1)
|
||||
{
|
||||
Screen_RevHandlerFlg = 0;
|
||||
Screen_IT_Update();
|
||||
}
|
||||
#endif
|
||||
|
||||
//485发送回复
|
||||
#if Key_PressLong
|
||||
if(OFF_confirm_flg != 1) MODBUS_IQ_Transmit();
|
||||
if(OFF_confirm_flg != 1) MODBUS1_IQ_Transmit();
|
||||
#else
|
||||
MODBUS_IQ_Transmit();
|
||||
MODBUS1_IQ_Transmit();
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
+8380
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,75 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file Project/STM32F10x_StdPeriph_Template/stm32f10x_conf.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.6.0
|
||||
* @date 20-September-2021
|
||||
* @brief Library configuration file.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2011 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_CONF_H
|
||||
#define __STM32F10x_CONF_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
|
||||
#include "stm32f10x_adc.h"
|
||||
#include "stm32f10x_bkp.h"
|
||||
#include "stm32f10x_can.h"
|
||||
#include "stm32f10x_cec.h"
|
||||
#include "stm32f10x_crc.h"
|
||||
#include "stm32f10x_dac.h"
|
||||
#include "stm32f10x_dbgmcu.h"
|
||||
#include "stm32f10x_dma.h"
|
||||
#include "stm32f10x_exti.h"
|
||||
#include "stm32f10x_flash.h"
|
||||
#include "stm32f10x_fsmc.h"
|
||||
#include "stm32f10x_gpio.h"
|
||||
#include "stm32f10x_i2c.h"
|
||||
#include "stm32f10x_iwdg.h"
|
||||
#include "stm32f10x_pwr.h"
|
||||
#include "stm32f10x_rcc.h"
|
||||
#include "stm32f10x_rtc.h"
|
||||
#include "stm32f10x_sdio.h"
|
||||
#include "stm32f10x_spi.h"
|
||||
#include "stm32f10x_tim.h"
|
||||
#include "stm32f10x_usart.h"
|
||||
#include "stm32f10x_wwdg.h"
|
||||
#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Uncomment the line below to expanse the "assert_param" macro in the
|
||||
Standard Peripheral Library drivers code */
|
||||
/* #define USE_FULL_ASSERT 1 */
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#ifdef USE_FULL_ASSERT
|
||||
|
||||
/**
|
||||
* @brief The assert_param macro is used for function's parameters check.
|
||||
* @param expr: If expr is false, it calls assert_failed function which reports
|
||||
* the name of the source file and the source line number of the call
|
||||
* that failed. If expr is true, it returns no value.
|
||||
* @retval None
|
||||
*/
|
||||
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
void assert_failed(uint8_t* file, uint32_t line);
|
||||
#else
|
||||
#define assert_param(expr) ((void)0)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
#endif /* __STM32F10x_CONF_H */
|
||||
|
||||
@@ -0,0 +1,166 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file Project/STM32F10x_StdPeriph_Template/stm32f10x_it.c
|
||||
* @author MCD Application Team
|
||||
* @version V3.6.0
|
||||
* @date 20-September-2021
|
||||
* @brief Main Interrupt Service Routines.
|
||||
* This file provides template for all exceptions handler and
|
||||
* peripherals interrupt service routine.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2011 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x_it.h"
|
||||
|
||||
/** @addtogroup STM32F10x_StdPeriph_Template
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/******************************************************************************/
|
||||
/* Cortex-M3 Processor Exceptions Handlers */
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @brief This function handles NMI exception.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void NMI_Handler(void)
|
||||
{
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles Hard Fault exception.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HardFault_Handler(void)
|
||||
{
|
||||
//执行软件重启
|
||||
NVIC_SystemReset();
|
||||
|
||||
//备用：软件复位失效时，触发IWDG复位
|
||||
IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable); // 解锁写访问
|
||||
IWDG_SetReload(1); // 重载值设为1
|
||||
IWDG_ReloadCounter(); // 喂狗，计数器重置为1
|
||||
|
||||
/* Go to infinite loop when Hard Fault exception occurs */
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles Memory Manage exception.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void MemManage_Handler(void)
|
||||
{
|
||||
/* Go to infinite loop when Memory Manage exception occurs */
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles Bus Fault exception.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void BusFault_Handler(void)
|
||||
{
|
||||
/* Go to infinite loop when Bus Fault exception occurs */
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles Usage Fault exception.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void UsageFault_Handler(void)
|
||||
{
|
||||
/* Go to infinite loop when Usage Fault exception occurs */
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles SVCall exception.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SVC_Handler(void)
|
||||
{
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles Debug Monitor exception.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void DebugMon_Handler(void)
|
||||
{
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles PendSVC exception.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void PendSV_Handler(void)
|
||||
{
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles SysTick Handler.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SysTick_Handler(void)
|
||||
{
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/* STM32F10x Peripherals Interrupt Handlers */
|
||||
/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */
|
||||
/* available peripheral interrupt handler's name please refer to the startup */
|
||||
/* file (startup_stm32f10x_xx.s). */
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @brief This function handles PPP interrupt request.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
/*void PPP_IRQHandler(void)
|
||||
{
|
||||
}*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
@@ -0,0 +1,52 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file Project/STM32F10x_StdPeriph_Template/stm32f10x_it.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.6.0
|
||||
* @date 20-September-2021
|
||||
* @brief This file contains the headers of the interrupt handlers.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2011 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F10x_IT_H
|
||||
#define __STM32F10x_IT_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f10x.h"
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
void NMI_Handler(void);
|
||||
void HardFault_Handler(void);
|
||||
void MemManage_Handler(void);
|
||||
void BusFault_Handler(void);
|
||||
void UsageFault_Handler(void);
|
||||
void SVC_Handler(void);
|
||||
void DebugMon_Handler(void);
|
||||
void PendSV_Handler(void);
|
||||
void SysTick_Handler(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F10x_IT_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,96 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32f10x.h
|
||||
* @author MCD Application Team
|
||||
* @version V3.5.1
|
||||
* @date 08-September-2021
|
||||
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2011 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32f10x_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Define to prevent recursive inclusion
|
||||
*/
|
||||
#ifndef __SYSTEM_STM32F10X_H
|
||||
#define __SYSTEM_STM32F10X_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @addtogroup STM32F10x_System_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup STM32F10x_System_Exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F10x_System_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F10x_System_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F10x_System_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
extern void SystemInit(void);
|
||||
extern void SystemCoreClockUpdate(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__SYSTEM_STM32F10X_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
Reference in New Issue
Block a user