commit 3ae7bcb054ae80534000c0038289ccb886f0511f Author: renshixing <2358401617@qq.com> Date: Tue Aug 25 17:30:40 2026 +0800 BMS STM32 V4.0.0.0 diff --git a/.vscode/extensions.json b/.vscode/extensions.json new file mode 100644 index 0000000..fc7a6d0 --- /dev/null +++ b/.vscode/extensions.json @@ -0,0 +1,5 @@ +{ + "recommendations": [ + "cl.keil-assistant" + ] +} \ No newline at end of file diff --git a/BSP/adc.c b/BSP/adc.c new file mode 100644 index 0000000..6c6d117 --- /dev/null +++ b/BSP/adc.c @@ -0,0 +1,242 @@ +/** + ****************************************************************************** + * @file gpio.c + * @author Jerry Cai + * @version V2.1 + * @date 19-April-2022 + * @brief gpio program body. + ****************************************************************************** + * @attention + * + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" +#include "global.h" + + +//【引脚】 +//GPIOA +#define PIN_T1 GPIO_Pin_5 +#define PIN_T2 GPIO_Pin_4 +#define PIN_T3 GPIO_Pin_1 +#define PIN_T4 GPIO_Pin_0 +//GPIOC +#define PIN_LOAD_VOL GPIO_Pin_4 + +//【ADC通道】 +#define CH_T1 ADC_Channel_5 +#define CH_T2 ADC_Channel_4 +#define CH_T3 ADC_Channel_1 +#define CH_T4 ADC_Channel_0 +#define CH_LOAD ADC_Channel_14 + + +int16_t TemperatureAverage; // 平均温度 +int16_t TemperatureMax; // 最高温度 +int16_t TemperatureMin; // 最低温度 +uint16_t TemperatureMaxIndex; // 最高温度序号 +uint16_t TemperatureMinIndex; // 最低温度序号 + +uint32_t loadvol; //负载检测的电压 + + +//ADC单通道单次转换 +void uf_ADC_Init(void) +{ + ADC_InitTypeDef ADC_InitStructure; + GPIO_InitTypeDef GPIO_InitStructure; + + //PC4 负载电压检测脚 + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE); + GPIO_InitStructure.GPIO_Pin = PIN_LOAD_VOL; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN; + GPIO_Init(GPIOC, &GPIO_InitStructure); + + //PA0.1.4.5 T1~T4输入引脚 + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA,ENABLE); + GPIO_InitStructure.GPIO_Pin = PIN_T1 | PIN_T2 | PIN_T3 | PIN_T4; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE ); //使能ADC1通道时钟 + RCC_ADCCLKConfig(RCC_PCLK2_Div6); //设置ADC分频因子6,ADC最大时间不能超过14M + + ADC_DeInit(ADC1); + ADC_InitStructure.ADC_Mode = ADC_Mode_Independent; + ADC_InitStructure.ADC_ScanConvMode = DISABLE; + ADC_InitStructure.ADC_ContinuousConvMode = DISABLE; + ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None; //转换由软件而不是外部触发启动 + ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right; //ADC数据右对齐 + ADC_InitStructure.ADC_NbrOfChannel = 1; //顺序进行规则转换的ADC通道的数目 + ADC_Init(ADC1, &ADC_InitStructure); + + ADC_Cmd(ADC1, ENABLE); //使能指定的ADC1 + ADC_ResetCalibration(ADC1); //使能复位校准 + while(ADC_GetResetCalibrationStatus(ADC1)); //等待复位校准结束 + ADC_StartCalibration(ADC1); //开启AD校准 + while(ADC_GetCalibrationStatus(ADC1)); //等待校准结束 +} + +//指定通道ADC值 +uint16_t ADC_GetVal(uint8_t ch) +{ + //设置指定ADC的规则组通道，一个序列，采样时间 + ADC_RegularChannelConfig(ADC1, ch, 1, ADC_SampleTime_239Cycles5 ); //ADC1,ADC通道,采样时间为239.5周期 + ADC_SoftwareStartConvCmd(ADC1, ENABLE); //使能指定的ADC1的软件转换启动功能 + while(!ADC_GetFlagStatus(ADC1, ADC_FLAG_EOC ));//等待转换结束 + return ADC_GetConversionValue(ADC1); //返回最近一次ADC1规则组的转换结果 +} + +//负载电压检测 +void LOAD_VOL(void) +{ + uint16_t adcvol; + + adcvol = ADC_GetVal(CH_LOAD); + + loadvol = adcvol * 40 * 3300 / 4095; //将AD值线性变换到0~3.3V的范围，表示电压 +} + +//温度处理 +void MCU_TemperaProcess(void) +{ + uint16_t adctmp[4]; //adc read value + uint16_t resntc[4]; //res calc value + uint16_t mcutmp[4]; + + uint16_t T[4]; //4路MCU + uint8_t i; + + + //获取ADC值 + adctmp[0] = ADC_GetVal(CH_T1); + adctmp[1] = ADC_GetVal(CH_T2); + adctmp[2] = ADC_GetVal(CH_T3); + adctmp[3] = ADC_GetVal(CH_T4); + + resntc[0] = (1000 * adctmp[0]) / (4096-adctmp[0]); + resntc[1] = (1000 * adctmp[1]) / (4096-adctmp[1]); + resntc[2] = (1000 * adctmp[2]) / (4096-adctmp[2]); + resntc[3] = (1000 * adctmp[3]) / (4096-adctmp[3]); + + mcutmp[0] = TEMP_Cal(resntc[0]); + mcutmp[1] = TEMP_Cal(resntc[1]); + mcutmp[2] = TEMP_Cal(resntc[2]); + mcutmp[3] = TEMP_Cal(resntc[3]); + + bmsMem.mcu_T1 = mcutmp[0]; + bmsMem.mcu_T2 = mcutmp[1]; + bmsMem.mcu_T3 = mcutmp[2]; + bmsMem.mcu_T4 = mcutmp[3]; + + + //当至少有1个温度可用时 + if((paraMem.temp_disable & 0x0F) != 0x0F) + { + uint8_t act_num = 0; //有效个数 + + if((paraMem.temp_disable & BIT0) == 0) + { + T[act_num] = bmsMem.mcu_T1; + act_num++; + } + if((paraMem.temp_disable & BIT1) == 0) + { + T[act_num] = bmsMem.mcu_T2; + act_num++; + } + if((paraMem.temp_disable & BIT2) == 0) + { + T[act_num] = bmsMem.mcu_T3; + act_num++; + } + if((paraMem.temp_disable & BIT3) == 0) + { + T[act_num] = bmsMem.mcu_T4; + act_num++; + } + + //平均温度 + TemperatureAverage = 0; + for(i=0;i T[i]) + { + TemperatureMin = T[i]; + TemperatureMinIndex = i; + } + } + } + //当4路温度都不可用时 + else + { + TemperatureAverage = 0; + TemperatureMin = 0; + TemperatureMax = 0; + TemperatureMinIndex = 0; + TemperatureMaxIndex = 0; + } + + //sum of all packs + bmsMem.can_temp = TemperatureAverage; + bmsMem.can_TempMax = TemperatureMax; + bmsMem.can_TempMaxIndex = TemperatureMaxIndex; + bmsMem.can_TempMin = TemperatureMin; + bmsMem.can_TempMinIndex = TemperatureMinIndex; + + + //当至少有1个温度可用时 + if((paraMem.temp_disable & 0x0F) != 0x0F) + { + //电芯温度告警和告警释放 + Trigger_mcuTAlarm(); //电芯温度告警 + Release_mcuTAlarm(); //电芯温度告警恢复 + //电芯温度保护和保护释放 + Trigger_mcuTProtect(); //电芯温度保护相关 + Release_mcuTProtect(); //电芯温度保护释放 + + #if DO2_Warm + //加热 + WARM_Ctrl(); //电芯低温启动加热，温度升高释放 + #endif + } + //当4路温度都不可用时 + else + { + bmsMem.bStatus2 &= ~0xF000; + bmsMem.temperaStatus &= ~0x000F; + } + + + //电流告警和告警释放 + Trigger_CurAlarm(); //电流告警 + Release_CurAlarm(); //电流告警恢复 + //电流保护和保护释放 + Trigger_CurProtect(); //电流保护 + Release_CurProtect(); //电流保护释放 + + /*电流保护连续出现的计算*/ + Trigger_CurProtectLock(); + +} + diff --git a/BSP/can.c b/BSP/can.c new file mode 100644 index 0000000..97267b0 --- /dev/null +++ b/BSP/can.c @@ -0,0 +1,213 @@ +/** + ****************************************************************************** + * @file tim.c + * @author Jerry + * @version V2.1 + * @date 19-April-2022 + * @brief tim program body. + ****************************************************************************** + * @attention + * + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" +#include "global.h" + + +#define CAN_MON_CNT 1000 //1000*10ms = 10s + +CanTxMsg TxMessage[20]; +CanRxMsg RxMessage; +uint8_t TxMailBox[20]; +uint8_t CAN_SendCount; +uint16_t CAN_MoniCount; + +CAN_MEMORY canMem[AddrMax+2]; + + +//HSE --> PLL倍频到72M --> APB1 2分频到36M +void uf_CAN1_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + CAN_InitTypeDef CAN_InitStructure; + CAN_FilterInitTypeDef CAN_FilterInitStructure; + NVIC_InitTypeDef NVIC_InitStructure; + + RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO | RCC_APB2Periph_GPIOA, ENABLE); + RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE); + + //Config CAN pin : RX + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + //GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + //Config CAN pin : TX + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + //NVIC + NVIC_InitStructure.NVIC_IRQChannel = USB_LP_CAN1_RX0_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1; //CAN通信 优先级：1,0 + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + //彻底复位CAN外设：先禁用，再重新使能，确保完全复位 + RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, DISABLE); + delay_ms(1); + RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE); + + //控制器配置 + CAN_DeInit(CAN1); + CAN_StructInit(&CAN_InitStructure); + CAN_InitStructure.CAN_TTCM = DISABLE; //时间触发通信模式 + CAN_InitStructure.CAN_ABOM = DISABLE; //自动离线管理 + CAN_InitStructure.CAN_AWUM = DISABLE; //自动唤醒 + CAN_InitStructure.CAN_NART = ENABLE; //自动重传 改启用 + CAN_InitStructure.CAN_RFLM = DISABLE; //FIFO锁定 + CAN_InitStructure.CAN_TXFP = DISABLE; //发送FIFO优先级 + CAN_InitStructure.CAN_Mode = CAN_Mode_Normal; //普通模式 + //波特率配置 + CAN_InitStructure.CAN_SJW = CAN_SJW_1tq; + CAN_InitStructure.CAN_BS1 = CAN_BS1_6tq; + CAN_InitStructure.CAN_BS2 = CAN_BS2_2tq; + if(protocol == 7) //MUST协议的波特率是100k + { + CAN_InitStructure.CAN_Prescaler = 40; //36MHz/40/(1+6+2)=100kbs + } + else //其他协议是500k + { + CAN_InitStructure.CAN_Prescaler = 8; //36MHz/8/(1+6+2)=500kbs + } + CAN_Init(CAN1, &CAN_InitStructure); + + //过滤器配置 + CAN_FilterInitStructure.CAN_FilterNumber = 0; //选择过滤器0 + CAN_FilterInitStructure.CAN_FilterMode = CAN_FilterMode_IdMask; //标识符屏蔽模式 + CAN_FilterInitStructure.CAN_FilterScale = CAN_FilterScale_32bit; //过滤器位宽32位 + CAN_FilterInitStructure.CAN_FilterIdHigh = 0; + CAN_FilterInitStructure.CAN_FilterIdLow = 0; + CAN_FilterInitStructure.CAN_FilterMaskIdHigh = 0; + CAN_FilterInitStructure.CAN_FilterMaskIdLow = 0; + CAN_FilterInitStructure.CAN_FilterFIFOAssignment = CAN_FilterFIFO0; + CAN_FilterInitStructure.CAN_FilterActivation = ENABLE; + CAN_FilterInit(&CAN_FilterInitStructure); + + //中断配置 + CAN_ITConfig(CAN1,CAN_IT_FMP0,ENABLE); //FIFO0中有消息允许中断 + + //清除所有可能的错误标志 + CAN1->ESR = 0; // 清除错误状态寄存器 + CAN1->MSR &= ~(CAN_MSR_ERRI); // 清除错误中断标志 + + //更新倒计时数 + CAN_MoniCount = CAN_MON_CNT; +} + +void USB_LP_CAN1_RX0_IRQHandler(void) +{ + //处理接收中断 + if(CAN_GetITStatus(CAN1, CAN_IT_FMP0) != RESET) + { + //接收报文 + CAN_Receive(CAN1,CAN_FIFO0,&RxMessage); + + if(RxMessage.StdId == 0x305) + { + RxMessage.StdId = 0; + CAN_MoniCount = CAN_MON_CNT; + + if(sleep_flag == 1) + { + //CAN网口收到数据，退出休眠且更新计时起点 + sleep_flag = 0; + SLEEP_Refresh(); + SLEEP2_Refresh(); + } + } + } +} + +void CAN_TIM_Moni(void) +{ + CAN_MoniCount--; + if(CAN_MoniCount == 0) + { + uf_CAN1_Init(); + } +} + +/* + 1."Sol-Ark", 2."GoodWe", 30."Megarevo", 12."Pylon", + 11."Deye", 7."MUST", 37."solis", 3."Growatt", + 4."Aiswei", 35."Afore", 27."Victron", 6."Sorotec", + + 5."SMA", 39."Sunways", 23."Luxpower", 24."Schneider", + 40."AlpSolarr", 13."SRNE", 14."Voltronic", 32."COSUPER", + 17."SMK", 31."SAKO", 18."SNADI", 21."invt", +*/ +void CAN_UpdateData(void) +{ + //第1页: + if(protocol == 1) CAN_Protocol_SolArk(); +// else if(protocol == 2) CAN_Protocol_GoodWe(); +// else if(protocol == 30) CAN_Protocol_Megarevo(); + else if(protocol == 12) CAN_Protocol_Pylon(); + else if(protocol == 11) CAN_Protocol_Deye(); +// else if(protocol == 7) CAN_Protocol_MUST(); + else if(protocol == 37) CAN_Protocol_solis(); + else if(protocol == 3) CAN_Protocol_Growatt(); +// else if(protocol == 4) CAN_Protocol_Aiswei(); +// else if(protocol == 35) CAN_Protocol_Afore(); +// else if(protocol == 27) CAN_Protocol_Victron(); +// else if(protocol == 6) CAN_Protocol_Sorotec(); + + //第2页: +// else if(protocol == 5) CAN_Protocol_SMA(); +// else if(protocol == 39) CAN_Protocol_Sunways(); +// else if(protocol == 23) CAN_Protocol_Luxpower(); +// else if(protocol == 24) CAN_Protocol_Schneider(); +// else if(protocol == 40) CAN_Protocol_AlpSolarr(); +} + +//CAN报文发送函数 +void CAN1_SendData(uint32_t Id, uint8_t *data) +{ + uint16_t can_timeout; + can_timeout = CAN_TIMEOUT_COUNT; + + if(Id < 0x1000) + { + TxMessage[CAN_SendCount].StdId = Id; //ID + TxMessage[CAN_SendCount].IDE = CAN_ID_STD; //标准ID + } + else + { + TxMessage[CAN_SendCount].ExtId = Id; //ID + TxMessage[CAN_SendCount].IDE = CAN_ID_EXT; //扩展ID + } + TxMessage[CAN_SendCount].RTR = CAN_RTR_DATA; //数据帧 + TxMessage[CAN_SendCount].DLC = 8; + TxMessage[CAN_SendCount].Data[0] = data[0]; + TxMessage[CAN_SendCount].Data[1] = data[1]; + TxMessage[CAN_SendCount].Data[2] = data[2]; + TxMessage[CAN_SendCount].Data[3] = data[3]; + TxMessage[CAN_SendCount].Data[4] = data[4]; + TxMessage[CAN_SendCount].Data[5] = data[5]; + TxMessage[CAN_SendCount].Data[6] = data[6]; + TxMessage[CAN_SendCount].Data[7] = data[7]; + TxMailBox[CAN_SendCount] = CAN_Transmit(CAN1, &TxMessage[CAN_SendCount]); //发送，返回当前邮箱号 + while(CAN_TransmitStatus(CAN1,TxMailBox[CAN_SendCount]) != CANTXOK) //等待发送完成 + { + if((can_timeout--) == 0) return; + } + + CAN_SendCount++; +} + diff --git a/BSP/flash.c b/BSP/flash.c new file mode 100644 index 0000000..f0ddb66 --- /dev/null +++ b/BSP/flash.c @@ -0,0 +1,1222 @@ +/** + ****************************************************************************** + * @file flash.c + * @author Jerry Cai + * @version + * @date + * @brief + ****************************************************************************** + * @attention + * + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" +#include "global.h" +#include "string.h" + +//将数组绝对定位到MCU内部FLASH地址 +//考虑兼容32K FLASH, +uint8_t const dataFlashA[2048] __attribute__((at(FLASH_DATA_A_BASE))) = +{ + /***** AFE设置参数 26Byte *****/ + 0x01, //5~16串存于此，其他串数(4/17~20串)存于paraMem.ee_sconf4 + 0x1E, //过放只关放电MOS,防止过放无法充电 + 0x6F, // + 0x20, //过压保护电压 0x320*5=4000mV + 0x63, // + 0x0C, //过压保护释放 0x30C*5=3900mV + 0x64, //欠压保护电压 0x64*20=2000mV + 0x69, //欠压保护释放 0x69*20=2100mV + 0xAF, //平衡开启电压 0xAF*20=3500mV + 0x78, //预充开启电压 0x78*20=2400mV + 0x4B, //低压禁止充电 0x4B*20=1500mV + 0xFA, //异常高压保护 0xFA*20=5000mV + 0x18, //放电过流1保护 30mV 4S + 0x1b, //放电过流2保护 40mV 2S + 0x10, //短路保护 40mV 0uS + 0x1A, //充电过流保护 30mV 1S + 0x50, // + 0x64, //充电过温保护 100 + 0x46, //充电过温释放 70 + 0xEC, //充电低温保护 -20 + 0xF6, //充电低温释放 -10 + 0x64, //放电过温保护 100 + 0x46, //放电过温释放 70 + 0xEC, //放电低温保护 -20 + 0xF6, //放电低温释放 -10 + 0xF4, //校验值(每次修改注意更新) + + /***** MCU保护参数 26Byte *****/ + //20230221 + 0x3C, //充电高温保护 60 + 0x37, //充电高温释放 55 + 0x00, //充电低温保护 0 + 0x05, //充电低温释放 5 + 0x41, //放电高温保护 65 + 0x3C, //放电高温释放 60 + 0xEC, //放电低温保护 -20 + 0xF1, //放电低温释放 -15 + + 0xCD, //充电过流保护 205A + 0xCD, //放电过流保护 205A + 0x01, //充电过流时间 1S + 0x01, //放电过流时间 1S + 0x1E, //过流恢复时间 30S + 0xB0, //校验值(每次修改注意更新) + + //20230614 + 0xC8, //限流启动电流 200A + 0x05, //限流延时时间 5S + 0x3C, //限流释放时间 0x003c=60S + 0x00, // + + //20230705 + 0x16, //逆变器充电电压限制 0x0316*0.1=79.0V + 0x03, // + 0x9A, //逆变器放电电压限制 0x019A*0.1=41.0V = 总体欠压告警41.0V + 0x01, // + 0x78, //逆变器充电电流限制 0x0578*0.1=140A = 充电过流告警150-10 + 0x05, // + 0xDC, //逆变器放电电流限制 0x05DC*0.1=150A = 放电过流告警160-10 + 0x05, // + + /***** Para过程参数 128Byte *****/ + //20240419 + 0x32, //主动均衡开启压差 50mV + 0x1E, //主动均衡释放压差 30mV + 0x58, //主动均衡释放延时 0x0258=600S + 0x02, // + + //20240821 + 0x5A, //累积容量转换比 90% + 0x46, //最低健康系数 70% + 0xC8, //100%对应的最大循环次数 0x00C8=200次 + 0x00, // + 0x70, //最大循环次数 6000次 + 0x17, // + + //20241024 + 0x3C, //浪涌短路消失且预充完成后，对下一次短路的等待时间 60s + 0x05, //浪涌短路的最大持续出现次数 5次 + + //20260402 + 0x01, //开机预充延时 1s + 0x02, //开放电MOS前预充延时 2s + 0x0A, //预充时的真短路判断电压 10V + 0x04, //浪涌短路时的真短路判断电压 4V + + //20250313 + 0xE0, //启用请求标志的标志 bit7充电允许 bit6放电允许 bit5强充 + 0x00, // + 0x64, //禁充开启SOC 100% + 0x63, //禁充释放SOC 99% + 0x0A, //禁放开启SOC 10% + 0x14, //禁放释放SOC 20% + 0x0A, //强充开启SOC 10% + 0x14, //强充释放SOC 20% + + //20250402 + 0x0F, //满充方式使能 单芯过压√ 总体过压√ 逆变器限压+2A小电流√ 满充电压+截止电流√ + 0x32, //截止电流 0x32=5.0A + 0x20, //满充电压 0x0320=80.0V + 0x03, // + + 0x00, //rsvd0[0] + 0x00, //rsvd0[1] + 0x00, //rsvd0[2] + 0x00, //rsvd0[3] + + //20240513 + 0xA0, //休眠时间(bit0~14) 0x05A0=1440min=24h + 0x05, //休眠启用(bit15) 0 + + //20240924 + 0x00, //地址手动控制不启用(bit0) 0 + 0x00, // + + //20241023 + 0x00, //充放启用控制 + 0x00, //bit0关放电MOS 0 bit1关充电MOS 0 bit2关预充 0 + + 0xD0, //满充容量校准时间(bit0~14) 0x02D0=720min=12h + 0x82, //充电校准满充容量不启用(bit15) 1 + + //20250402 + 0x01, //休眠2时间(bit0~14) 0x0001=1min + 0x00, //休眠2启用(bit15) 0 + 0x60, //休眠2电压(bit0~15) 0x960=2400mV + 0x09, // + + //20250410 + 0xF0, //定时校准soc时间(bit0-14) 0x00F0=240min=4h + 0x80, //开路电压定时校准soc禁用(bit15) 1 + 0x0A, //±10%范围外 + 0x0A, //±10℃范围内 + + //20260309 + 0x00, //bit0~4 温度只测不保护禁用 + 0x00, // + + 0x00, //rsvd1[0] + 0x00, //rsvd1[1] + 0x00, //rsvd1[2] + 0x00, //rsvd1[3] + 0x00, //rsvd1[4] + 0x00, //rsvd1[5] + 0x00, //rsvd1[6] + 0x00, //rsvd1[7] + 0x00, //rsvd1[8] + 0x00, //rsvd1[9] + 0x00, //rsvd1[10] + 0x00, //rsvd1[11] + 0x00, //rsvd1[12] + 0x00, //rsvd1[13] + + //20250404 + 0x20, //总体过压保护电压 0x0320*0.1=80.0V + 0x03, // + 0x0C, //总体过压保护释放电压 0x030C*0.1=78.0V + 0x03, // + 0x90, //总体欠压保护电压 0x0190*0.1=40.0V + 0x01, // + 0xA4, //总体欠压保护释放电压 0x01A4*0.1=42.0V + 0x01, // + 0x01, //总体过压保护延时 1s + 0x01, //总体欠压保护延时 1s + + 0x1C, //放电过流2 540A + 0x02, // + 0x04, //放电过流2延时 4*10ms + 0x00, // + + 0x46, //环境充电高温 70 + 0x41, //环境充电高温释放 65 + 0xEC, //环境充电低温 -20 + 0xF1, //环境充电低温释放 -15 + 0x46, //环境放电高温 70 + 0x41, //环境放电高温释放 65 + 0xEC, //环境放电低温 -20 + 0xF1, //环境放电低温释放 -15 + + 0x60, //单体过压释放SOC + 0x60, //总体过压释放SOC + + 0x10, //并机总数 16台 + + 0x00, //rsvd2[0] + 0x00, //rsvd2[1] + 0x00, //rsvd2[2] + 0x00, //rsvd2[3] + + //20260722 + 0x14, //SH36735XX系列SCONF4寄存器串数配置(20串) + + //20260716 + 0x12, //短路计算倍数 18 + 0x01, //1=SH36735xx系列 0=SH367309 + + //20250408 + 0x6E, //单体过压告警 0x0F6E=3950mV + 0x0F, // + 0x02, //单体欠压告警 0x0802=2050mV + 0x08, // + 0x16, //总体过压告警 0x0316=79.0V + 0x03, // + 0x9A, //总体欠压告警 0x019A=41.0V + 0x01, // + + 0x96, //充电过流告警 0x96=150A + 0xA0, //放电过流1告警 0xA0=160A + + 0x37, //电芯充电高温告警 55 + 0x05, //电芯充电低温告警 5 + 0x3C, //电芯放电高温告警 60 + 0xF1, //电芯放电低温告警 -15 + + 0x41, //环境充电高温告警 65 + 0xF1, //环境充电低温告警 -15 + 0x41, //环境放电高温告警 65 + 0xF1, //环境放电低温告警 -15 + + 0x5F, //MOS充电高温告警 95 + 0xF1, //MOS充电低温告警 -15 + 0x5F, //MOS放电高温告警 95 + 0xF1, //MOS放电低温告警 -15 + + 0x00, //rsvd3[0] + 0x00, //rsvd3[1] + 0x00, //rsvd3[2] + 0x00, //rsvd3[3] + 0x00, //rsvd3[4] + 0x00, //rsvd3[5] + 0x00, //rsvd3[6] + 0x00, //rsvd3[7] + 0x00, //rsvd3[8] + 0x00, //rsvd3[9] + + 0x49, //OCV放电曲线 2889 + 0x0B, // + 0x86, //3206 + 0x0C, // + 0x91, //3217 + 0x0C, // + 0xB1, //3249 + 0x0C, // + 0xC7, //3271 + 0x0C, // + 0xDA, //3290 + 0x0C, // + 0xDB, //3291 + 0x0C, // + 0xDE, //3294 + 0x0C, // + 0x02, //3330 + 0x0D, // + 0x03, //3331 + 0x0D, // + 0x03, //3331 + 0x0D, // + 0x04, //3332 + 0x0D, // + 0x05, //3333 + 0x0D, // + 0x07, //3335 + 0x0D, // + 0x47, //3399 + 0x0D, // + + 0x00, //rsvd4[0] + 0x00, //rsvd4[1] + + 0xF1, //OCV充电曲线 3057 + 0x0B, // + 0x95, //3221 + 0x0C, // + 0x9D, //3229 + 0x0C, // + 0xBE, //3262 + 0x0C, // + 0xD7, //3287 + 0x0C, // + 0xE7, //3303 + 0x0C, // + 0xE8, //3304 + 0x0C, // + 0xEA, //3306 + 0x0C, // + 0x0B, //3339 + 0x0D, // + 0x0C, //3340 + 0x0D, // + 0x0C, //3340 + 0x0D, // + 0x0B, //3339 + 0x0D, // + 0x0D, //3341 + 0x0D, // + 0x0C, //3340 + 0x0D, // + 0x47, //3399 + 0x0D, // + + 0x00, //rsvd5[0] + 0x00, //rsvd5[1] + + + #if LTE_Conn + /***** 4G平台设备参数 共42+2+42+42+23+1+8=160Byte *****/ + //域名 42Byte + 0x00, //0 + 0x00, //1 + 0x00, //2 + 0x00, //3 + + 0x00, //4 + 0x00, //5 + 0x00, //6 + 0x00, //7 + + 0x00, //8 + 0x00, //9 + 0x00, //10 + 0x00, //11 + + 0x00, //12 + 0x00, //13 + 0x00, //14 + 0x00, //15 + + 0x00, //16 + 0x00, //17 + 0x00, //18 + 0x00, //19 + + 0x00, //20 + 0x00, //21 + 0x00, //22 + 0x00, //23 + + 0x00, //24 + 0x00, //25 + 0x00, //26 + 0x00, //27 + + 0x00, //28 + 0x00, //29 + 0x00, //30 + 0x00, //31 + + 0x00, //32 + 0x00, //33 + 0x00, //34 + 0x00, //35 + + 0x00, //36 + 0x00, //37 + 0x00, //38 + 0x00, //39 + + 0x00, //40 + 0x00, //41 + + + //端口 2Byte + 0x00, // + 0x00, // + + + //用户名 42Byte + 0x00, //0 + 0x00, //1 + 0x00, //2 + 0x00, //3 + + 0x00, //4 + 0x00, //5 + 0x00, //6 + 0x00, //7 + + 0x00, //8 + 0x00, //9 + 0x00, //10 + 0x00, //11 + + 0x00, //12 + 0x00, //13 + 0x00, //14 + 0x00, //15 + + 0x00, //16 + 0x00, //17 + 0x00, //18 + 0x00, //19 + + 0x00, //20 + 0x00, //21 + 0x00, //22 + 0x00, //23 + + 0x00, //24 + 0x00, //25 + 0x00, //26 + 0x00, //27 + + 0x00, //28 + 0x00, //29 + 0x00, //30 + 0x00, //31 + + 0x00, //32 + 0x00, //33 + 0x00, //34 + 0x00, //35 + + 0x00, //36 + 0x00, //37 + 0x00, //38 + 0x00, //39 + + 0x00, //40 + 0x00, //41 + + + //密码 42Byte + 0x00, //0 + 0x00, //1 + 0x00, //2 + 0x00, //3 + + 0x00, //4 + 0x00, //5 + 0x00, //6 + 0x00, //7 + + 0x00, //8 + 0x00, //9 + 0x00, //10 + 0x00, //11 + + 0x00, //12 + 0x00, //13 + 0x00, //14 + 0x00, //15 + + 0x00, //16 + 0x00, //17 + 0x00, //18 + 0x00, //19 + + 0x00, //20 + 0x00, //21 + 0x00, //22 + 0x00, //23 + + 0x00, //24 + 0x00, //25 + 0x00, //26 + 0x00, //27 + + 0x00, //28 + 0x00, //29 + 0x00, //30 + 0x00, //31 + + 0x00, //32 + 0x00, //33 + 0x00, //34 + 0x00, //35 + + 0x00, //36 + 0x00, //37 + 0x00, //38 + 0x00, //39 + + 0x00, //40 + 0x00, //41 + + //ClientID 23Byte 和SN号同步，所以不填 + 0x00, //0 + 0x00, //1 + 0x00, //2 + + 0x00, //3 + 0x00, //4 + 0x00, //5 + 0x00, //6 + + 0x00, //7 + 0x00, //8 + 0x00, //9 + 0x00, //10 + + 0x00, //11 + 0x00, //12 + 0x00, //13 + 0x00, //14 + + 0x00, //15 + 0x00, //16 + 0x00, //17 + 0x00, //18 + + 0x00, //19 + 0x00, //20 + 0x00, //21 + 0x00, //22 + 0x00, //23 + 0x00, //24 + + 0x00, //CRC校验码(153个0x00的校验码是0) + + //(预留目前不用) + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + #endif + +}; + +uint8_t const dataFlashB[2048] __attribute__((at(FLASH_DATA_B_BASE))) = +{ + /***** AFE设置参数 26Byte *****/ + 0x01, //5~16串存于此，其他串数(4/17~20串)存于paraMem.ee_sconf4 + 0x1E, //过放只关放电MOS,防止过放无法充电 + 0x6F, // + 0x20, //过压保护电压 0x320*5=4000mV + 0x63, // + 0x0C, //过压保护释放 0x30C*5=3900mV + 0x64, //欠压保护电压 0x64*20=2000mV + 0x69, //欠压保护释放 0x69*20=2100mV + 0xAF, //平衡开启电压 0xAF*20=3500mV + 0x78, //预充开启电压 0x78*20=2400mV + 0x4B, //低压禁止充电 0x4B*20=1500mV + 0xFA, //异常高压保护 0xFA*20=5000mV + 0x18, //放电过流1保护 30mV 4S + 0x1b, //放电过流2保护 40mV 2S + 0x10, //短路保护 40mV 0uS + 0x1A, //充电过流保护 30mV 1S + 0x50, // + 0x64, //充电过温保护 100 + 0x46, //充电过温释放 70 + 0xEC, //充电低温保护 -20 + 0xF6, //充电低温释放 -10 + 0x64, //放电过温保护 100 + 0x46, //放电过温释放 70 + 0xEC, //放电低温保护 -20 + 0xF6, //放电低温释放 -10 + 0xF4, //校验值(每次修改注意更新) + + /***** MCU保护参数 26Byte *****/ + //20230221 + 0x3C, //充电高温保护 60 + 0x37, //充电高温释放 55 + 0x00, //充电低温保护 0 + 0x05, //充电低温释放 5 + 0x41, //放电高温保护 65 + 0x3C, //放电高温释放 60 + 0xEC, //放电低温保护 -20 + 0xF1, //放电低温释放 -15 + + 0xCD, //充电过流保护 205A + 0xCD, //放电过流保护 205A + 0x01, //充电过流时间 1S + 0x01, //放电过流时间 1S + 0x1E, //过流恢复时间 30S + 0xB0, //校验值(每次修改注意更新) + + //20230614 + 0xC8, //限流启动电流 200A + 0x05, //限流延时时间 5S + 0x3C, //限流释放时间 0x003c=60S + 0x00, // + + //20230705 + 0x16, //逆变器充电电压限制 0x0316*0.1=79.0V + 0x03, // + 0x9A, //逆变器放电电压限制 0x019A*0.1=41.0V = 总体欠压告警41.0V + 0x01, // + 0x78, //逆变器充电电流限制 0x0578*0.1=140A = 充电过流告警150-10 + 0x05, // + 0xDC, //逆变器放电电流限制 0x05DC*0.1=150A = 放电过流告警160-10 + 0x05, // + + /***** Para过程参数 128Byte *****/ + //20240419 + 0x32, //主动均衡开启压差 50mV + 0x1E, //主动均衡释放压差 30mV + 0x58, //主动均衡释放延时 0x0258=600S + 0x02, // + + //20240821 + 0x5A, //累积容量转换比 90% + 0x46, //最低健康系数 70% + 0xC8, //100%对应的最大循环次数 0x00C8=200次 + 0x00, // + 0x70, //最大循环次数 6000次 + 0x17, // + + //20241024 + 0x3C, //浪涌短路消失且预充完成后，对下一次短路的等待时间 60s + 0x05, //浪涌短路的最大持续出现次数 5次 + + //20260402 + 0x01, //开机预充延时 1s + 0x02, //开放电MOS前预充延时 2s + 0x0A, //预充时的真短路判断电压 10V + 0x04, //浪涌短路时的真短路判断电压 4V + + //20250313 + 0xE0, //启用请求标志的标志 bit7充电允许 bit6放电允许 bit5强充 + 0x00, // + 0x64, //禁充开启SOC 100% + 0x63, //禁充释放SOC 99% + 0x0A, //禁放开启SOC 10% + 0x14, //禁放释放SOC 20% + 0x0A, //强充开启SOC 10% + 0x14, //强充释放SOC 20% + + //20250402 + 0x0F, //满充方式使能 单芯过压√ 总体过压√ 逆变器限压+2A小电流√ 满充电压+截止电流√ + 0x32, //截止电流 0x32=5.0A + 0x20, //满充电压 0x0320=80.0V + 0x03, // + + 0x00, //rsvd0[0] + 0x00, //rsvd0[1] + 0x00, //rsvd0[2] + 0x00, //rsvd0[3] + + //20240513 + 0xA0, //休眠时间(bit0~14) 0x05A0=1440min=24h + 0x05, //休眠启用(bit15) 0 + + //20240924 + 0x00, //地址手动控制不启用(bit0) 0 + 0x00, // + + //20241023 + 0x00, //充放启用控制 + 0x00, //bit0关放电MOS 0 bit1关充电MOS 0 bit2关预充 0 + + 0xD0, //满充容量校准时间(bit0~14) 0x02D0=720min=12h + 0x82, //充电校准满充容量不启用(bit15) 1 + + //20250402 + 0x01, //休眠2时间(bit0~14) 0x0001=1min + 0x00, //休眠2启用(bit15) 0 + 0x60, //休眠2电压(bit0~15) 0x960=2400mV + 0x09, // + + //20250410 + 0xF0, //定时校准soc时间(bit0-14) 0x00F0=240min=4h + 0x80, //开路电压定时校准soc禁用(bit15) 1 + 0x0A, //±10%范围外 + 0x0A, //±10℃范围内 + + //20260309 + 0x00, //bit0~4 温度只测不保护禁用 + 0x00, // + + 0x00, //rsvd1[0] + 0x00, //rsvd1[1] + 0x00, //rsvd1[2] + 0x00, //rsvd1[3] + 0x00, //rsvd1[4] + 0x00, //rsvd1[5] + 0x00, //rsvd1[6] + 0x00, //rsvd1[7] + 0x00, //rsvd1[8] + 0x00, //rsvd1[9] + 0x00, //rsvd1[10] + 0x00, //rsvd1[11] + 0x00, //rsvd1[12] + 0x00, //rsvd1[13] + + //20250404 + 0x20, //总体过压保护电压 0x0320*0.1=80.0V + 0x03, // + 0x0C, //总体过压保护释放电压 0x030C*0.1=78.0V + 0x03, // + 0x90, //总体欠压保护电压 0x0190*0.1=40.0V + 0x01, // + 0xA4, //总体欠压保护释放电压 0x01A4*0.1=42.0V + 0x01, // + 0x01, //总体过压保护延时 1s + 0x01, //总体欠压保护延时 1s + + 0x1C, //放电过流2 540A + 0x02, // + 0x04, //放电过流2延时 4*10ms + 0x00, // + + 0x46, //环境充电高温 70 + 0x41, //环境充电高温释放 65 + 0xEC, //环境充电低温 -20 + 0xF1, //环境充电低温释放 -15 + 0x46, //环境放电高温 70 + 0x41, //环境放电高温释放 65 + 0xEC, //环境放电低温 -20 + 0xF1, //环境放电低温释放 -15 + + 0x60, //单体过压释放SOC + 0x60, //总体过压释放SOC + + 0x10, //并机总数 16台 + + 0x00, //rsvd2[0] + 0x00, //rsvd2[1] + 0x00, //rsvd2[2] + 0x00, //rsvd2[3] + + //20260722 + 0x14, //SH36735XX系列SCONF4寄存器串数配置(20串) + + //20260716 + 0x12, //短路计算倍数 18 + 0x01, //1=SH36735xx系列 0=SH367309 + + //20250408 + 0x6E, //单体过压告警 0x0F6E=3950mV + 0x0F, // + 0x02, //单体欠压告警 0x0802=2050mV + 0x08, // + 0x16, //总体过压告警 0x0316=79.0V + 0x03, // + 0x9A, //总体欠压告警 0x019A=41.0V + 0x01, // + + 0x96, //充电过流告警 0x96=150A + 0xA0, //放电过流1告警 0xA0=160A + + 0x37, //电芯充电高温告警 55 + 0x05, //电芯充电低温告警 5 + 0x3C, //电芯放电高温告警 60 + 0xF1, //电芯放电低温告警 -15 + + 0x41, //环境充电高温告警 65 + 0xF1, //环境充电低温告警 -15 + 0x41, //环境放电高温告警 65 + 0xF1, //环境放电低温告警 -15 + + 0x5F, //MOS充电高温告警 95 + 0xF1, //MOS充电低温告警 -15 + 0x5F, //MOS放电高温告警 95 + 0xF1, //MOS放电低温告警 -15 + + 0x00, //rsvd3[0] + 0x00, //rsvd3[1] + 0x00, //rsvd3[2] + 0x00, //rsvd3[3] + 0x00, //rsvd3[4] + 0x00, //rsvd3[5] + 0x00, //rsvd3[6] + 0x00, //rsvd3[7] + 0x00, //rsvd3[8] + 0x00, //rsvd3[9] + + 0x49, //OCV放电曲线 2889 + 0x0B, // + 0x86, //3206 + 0x0C, // + 0x91, //3217 + 0x0C, // + 0xB1, //3249 + 0x0C, // + 0xC7, //3271 + 0x0C, // + 0xDA, //3290 + 0x0C, // + 0xDB, //3291 + 0x0C, // + 0xDE, //3294 + 0x0C, // + 0x02, //3330 + 0x0D, // + 0x03, //3331 + 0x0D, // + 0x03, //3331 + 0x0D, // + 0x04, //3332 + 0x0D, // + 0x05, //3333 + 0x0D, // + 0x07, //3335 + 0x0D, // + 0x47, //3399 + 0x0D, // + + 0x00, //rsvd4[0] + 0x00, //rsvd4[1] + + 0xF1, //OCV充电曲线 3057 + 0x0B, // + 0x95, //3221 + 0x0C, // + 0x9D, //3229 + 0x0C, // + 0xBE, //3262 + 0x0C, // + 0xD7, //3287 + 0x0C, // + 0xE7, //3303 + 0x0C, // + 0xE8, //3304 + 0x0C, // + 0xEA, //3306 + 0x0C, // + 0x0B, //3339 + 0x0D, // + 0x0C, //3340 + 0x0D, // + 0x0C, //3340 + 0x0D, // + 0x0B, //3339 + 0x0D, // + 0x0D, //3341 + 0x0D, // + 0x0C, //3340 + 0x0D, // + 0x47, //3399 + 0x0D, // + + 0x00, //rsvd5[0] + 0x00, //rsvd5[1] + + + #if LTE_Conn + /***** 4G平台设备参数 共42+2+42+42+23+1+8=160Byte *****/ + //域名 42Byte + 0x00, //0 + 0x00, //1 + 0x00, //2 + 0x00, //3 + + 0x00, //4 + 0x00, //5 + 0x00, //6 + 0x00, //7 + + 0x00, //8 + 0x00, //9 + 0x00, //10 + 0x00, //11 + + 0x00, //12 + 0x00, //13 + 0x00, //14 + 0x00, //15 + + 0x00, //16 + 0x00, //17 + 0x00, //18 + 0x00, //19 + + 0x00, //20 + 0x00, //21 + 0x00, //22 + 0x00, //23 + + 0x00, //24 + 0x00, //25 + 0x00, //26 + 0x00, //27 + + 0x00, //28 + 0x00, //29 + 0x00, //30 + 0x00, //31 + + 0x00, //32 + 0x00, //33 + 0x00, //34 + 0x00, //35 + + 0x00, //36 + 0x00, //37 + 0x00, //38 + 0x00, //39 + + 0x00, //40 + 0x00, //41 + + + //端口 2Byte + 0x00, // + 0x00, // + + + //用户名 42Byte + 0x00, //0 + 0x00, //1 + 0x00, //2 + 0x00, //3 + + 0x00, //4 + 0x00, //5 + 0x00, //6 + 0x00, //7 + + 0x00, //8 + 0x00, //9 + 0x00, //10 + 0x00, //11 + + 0x00, //12 + 0x00, //13 + 0x00, //14 + 0x00, //15 + + 0x00, //16 + 0x00, //17 + 0x00, //18 + 0x00, //19 + + 0x00, //20 + 0x00, //21 + 0x00, //22 + 0x00, //23 + + 0x00, //24 + 0x00, //25 + 0x00, //26 + 0x00, //27 + + 0x00, //28 + 0x00, //29 + 0x00, //30 + 0x00, //31 + + 0x00, //32 + 0x00, //33 + 0x00, //34 + 0x00, //35 + + 0x00, //36 + 0x00, //37 + 0x00, //38 + 0x00, //39 + + 0x00, //40 + 0x00, //41 + + + //密码 42Byte + 0x00, //0 + 0x00, //1 + 0x00, //2 + 0x00, //3 + + 0x00, //4 + 0x00, //5 + 0x00, //6 + 0x00, //7 + + 0x00, //8 + 0x00, //9 + 0x00, //10 + 0x00, //11 + + 0x00, //12 + 0x00, //13 + 0x00, //14 + 0x00, //15 + + 0x00, //16 + 0x00, //17 + 0x00, //18 + 0x00, //19 + + 0x00, //20 + 0x00, //21 + 0x00, //22 + 0x00, //23 + + 0x00, //24 + 0x00, //25 + 0x00, //26 + 0x00, //27 + + 0x00, //28 + 0x00, //29 + 0x00, //30 + 0x00, //31 + + 0x00, //32 + 0x00, //33 + 0x00, //34 + 0x00, //35 + + 0x00, //36 + 0x00, //37 + 0x00, //38 + 0x00, //39 + + 0x00, //40 + 0x00, //41 + + //ClientID 23Byte 和SN号同步，所以不填 + 0x00, //0 + 0x00, //1 + 0x00, //2 + + 0x00, //3 + 0x00, //4 + 0x00, //5 + 0x00, //6 + + 0x00, //7 + 0x00, //8 + 0x00, //9 + 0x00, //10 + + 0x00, //11 + 0x00, //12 + 0x00, //13 + 0x00, //14 + + 0x00, //15 + 0x00, //16 + 0x00, //17 + 0x00, //18 + + 0x00, //19 + 0x00, //20 + 0x00, //21 + 0x00, //22 + 0x00, //23 + 0x00, //24 + + 0x00, //CRC校验码(153个0x00的校验码是0) + + //(预留目前不用) + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + #endif + +}; + +//FLASH指定地址连续写入num HALFWORD数据 +void FLASH_WrData(uint32_t addr, uint16_t *data, uint16_t num) +{ + uint16_t sign; + uint16_t i; + + FLASH_Unlock(); + FLASH_ClearFlag(FLASH_FLAG_BSY | FLASH_FLAG_EOP |FLASH_FLAG_PGERR | FLASH_FLAG_WRPRTERR); + sign = FLASH_ErasePage(addr); + if(sign == FLASH_COMPLETE) + { + for(i=0; i关闭充放MOS、预充] +uint8_t tscTimeCount; //AFE短路发生后，若第一时间检测的负载电压值<4V，显示“真短路” + + +uint8_t pchgTimeCount; //AFE短路结束后，单次预充时间，到点后会关闭预充检测负载电压 + +uint8_t TSC_detectFlag; //不开启预充时，AFE短路发生后，判断是否是真短路的标志 0;不执行 1:要执行 2:执行完成，回到正常 0xAA:检测到真短路 + +uint16_t ADDR_Moni_Count; //自动分配地址前，因为短接脚而该改变自身的地址 每次10ms + +uint8_t ClearArray_Flag; //在定时器函数中，执行清空队列标志的标志 + + +/*6.3.L非自锁按键-长按*/ +#define ON_WAIT 100 //100*10ms=1s +#define RST_WAIT 100 //100*10ms=1s +#define OFF_WAIT 300 //300*10ms=3s + +uint8_t ON_confirm_flg; //程序运行后，先确认开机 1:按键按下2s确认开机 2：确认开机后按键松开，可以监测下一次按键按下以判断复位和重启 +uint8_t RST_confirm_flg; //按钮按下后，通过时长判断执行复位 +uint8_t OFF_confirm_flg; //按钮按下后，通过时长判断确认断开电源维持，等按钮松开就关机 + +uint8_t key_state; //按键状态 0:未按下, 1:按下 +uint8_t power_state; //电源脚输出 0：应输出低，1：应输出高 + +uint8_t led_toggle_step; //执行复位时，LED灯同步闪烁 +/*6.3.L非自锁按键*/ + + +void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint32_t odr; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* get current Ouput Data Register value */ + odr = GPIOx->ODR; + + /* Set selected pins that were at low level, and reset ones that were high */ + GPIOx->BSRR = ((odr & GPIO_Pin) << 16u) | (~odr & GPIO_Pin); +} + +//LED +//--------------------------------------------- +void LED_RUN_On(void) +{ + GPIO_SetBits(GPIOA, PIN_LED_RUN); +} + +void LED_RUN_Off(void) +{ + GPIO_ResetBits(GPIOA, PIN_LED_RUN); +} + +void LED_ALARM_On(void) +{ + GPIO_SetBits(GPIOB, PIN_LED_ALARM); +} + +void LED_ALARM_Off(void) +{ + GPIO_ResetBits(GPIOB, PIN_LED_ALARM); +} + +void LED1_On(void) +{ + GPIO_SetBits(GPIOC, PIN_LED1); +} + +void LED1_Off(void) +{ + GPIO_ResetBits(GPIOC, PIN_LED1); +} + +void LED2_On(void) +{ + GPIO_SetBits(GPIOB, PIN_LED2); +} + +void LED2_Off(void) +{ + GPIO_ResetBits(GPIOB, PIN_LED2); +} + +void LED3_On(void) +{ + GPIO_SetBits(GPIOB, PIN_LED3); +} + +void LED3_Off(void) +{ + GPIO_ResetBits(GPIOB, PIN_LED3); +} + +void LED4_On(void) +{ + GPIO_SetBits(GPIOB, PIN_LED4); +} + +void LED4_Off(void) +{ + GPIO_ResetBits(GPIOB, PIN_LED4); +} + +void LED_RUN_Toggle(void) +{ + HAL_GPIO_TogglePin(GPIOA, PIN_LED_RUN); +} + +void LED_ALARM_Toggle(void) +{ + HAL_GPIO_TogglePin(GPIOB, PIN_LED_ALARM); +} + +void LED_ALL_ON(void) +{ + LED_RUN_On(); + LED_ALARM_On(); + LED1_On(); + LED2_On(); + LED3_On(); + LED4_On(); +} + +void LED_ALL_OFF(void) +{ + LED_RUN_Off(); + LED_ALARM_Off(); + LED1_Off(); + LED2_Off(); + LED3_Off(); + LED4_Off(); +} + +void LED_ALL_Toggle(void) +{ + HAL_GPIO_TogglePin(GPIOA, PIN_LED_RUN); + HAL_GPIO_TogglePin(GPIOB, PIN_LED_ALARM); + HAL_GPIO_TogglePin(GPIOC, PIN_LED1); + HAL_GPIO_TogglePin(GPIOB, PIN_LED2); + HAL_GPIO_TogglePin(GPIOB, PIN_LED3); + HAL_GPIO_TogglePin(GPIOB, PIN_LED4); +} + +void LED_RST_Toggle(void) +{ + led_toggle_step++; + + if(led_toggle_step == 1) //全亮 + { + LED_ALL_ON(); + } + else if(led_toggle_step <= 9) //闪烁:1亮-2灭-3亮-4灭-5亮-6灭-7亮-8灭-9亮 + { + LED_ALL_Toggle(); + } + + #if Key_PressRST + else if(led_toggle_step == 6) //执行复位，保持常亮 + { + uf_I2C1_Init(); //IIC复位 + uf_SPI2_Init(); //SPI复位 + uf_CAN1_Init(); //CAN复位 + MODBUS_Init(); //485通信复位 + MODBUS1_Init(); + + /*三选一模块*/ + #if BLE_Conn + BLE_Init(); //蓝牙通信复位 + BLE_Reset(); //蓝牙模块复位 + #endif + #if WIFI_Conn + WIFI_Init(); //WIFI通信复位 + WIFI_Reset(); //WIFI模块复位 + #endif + #if LTE_Conn + LTE_4G_Init(); //4G通信复位 + LTE_4G_Reset(); //4G模块复位 + #endif + + bmsMem.bStatus1 = 0; //保护/报警/故障标志复位 + bmsMem.bStatus2 = 0; + bmsMem.bStatus3 = 0; + bmsMem.temperaStatus = 0; + bmsMem.balanceStatus = 0; + bmsMem.packStatus = 0; + + uf_IWDG_Init(6,1250); //看门狗复位 + } + #endif + + else if(led_toggle_step >= 13) //结束 + { + led_toggle_step = 0; + RST_confirm_flg = 2; + } +} +//-------------------------------------------- + +//模块已开机，存于Flash +#define POWER_FLAG 0x08020800 +uint8_t power_old; //如果是正常工作时重启，保持开机 +void POWER_Check(void) +{ + uint32_t tmpRd; + + //读取标志位 + FLASH_RdWord(POWER_FLAG, &tmpRd, 1); //4/4=1 + if(tmpRd == 0x20260325) + { + power_old = 1; + } +} + +void POWER_On(void) +{ + GPIO_SetBits(GPIOC, PIN_POWER); + GPIO_SetBits(GPIOC, PIN_LED_POWER); //电源指示灯亮 +} + +void POWER_Off(void) +{ + GPIO_ResetBits(GPIOC, PIN_POWER); + GPIO_ResetBits(GPIOC, PIN_LED_POWER); //电源指示灯灭 +} + +void POWER_Ctrl(void) +{ + if(power_old == 1) //重启，所以直接维持输出高 + { + power_state = 1; + } + else if(power_old == 2) //检测到开机，记录到Flash + { + uint32_t tmpRd = 0x20260325; + + //写入标志位 + FLASH_WrData(POWER_FLAG, (uint16_t *)&tmpRd, 2); //4/2=2 + delay_ms(2); + + power_old = 3; + } + else if(power_old == 4) //检测到关机，记录到Flash + { + uint32_t tmpRd = 0xFFFFFFFF; + + //写入标志位 + FLASH_WrData(POWER_FLAG, (uint16_t *)&tmpRd, 2); //4/2=2 + delay_ms(2); + + power_old = 5; + } + + if(power_state == 1) //正常维持输出高 + { + POWER_On(); + } + else //判定按钮长按后，输出置低，等按钮松开就断电 + { + POWER_Off(); + } +} + +//输入电平检测 +uint8_t KEY_IN(void) +{ + uint8_t status; + status = GPIO_ReadInputDataBit(GPIOC,PIN_KEY); + + return status; +} + +//按键状态监测函数 +uint16_t KEY_INH_Count; +uint16_t KEY_INL_Count; +void KEY_TIM_Moni(void) +{ + key_state = KEY_IN(); + + if(power_old == 1) + { + ON_confirm_flg = 2; + } + + //开机后，延时2s确认保持开机 + if(ON_confirm_flg == 0) + { + if(key_state == 1) //输入高电平 + { + KEY_INH_Count++; + if(KEY_INH_Count > ON_WAIT) + { + KEY_INH_Count = 0; + ON_confirm_flg = 1; + + power_old = 2; //写入开机 + power_state = 1; + } + } + else + { + KEY_INH_Count = 0; + } + } + //确认开机后，要监测到按键松开才能进行对下一次按键摁下监测 + else if(ON_confirm_flg == 1) + { + if(key_state == 0) //输入低电平 + { + KEY_INL_Count++; + if(KEY_INL_Count > 3) //防抖动 + { + KEY_INL_Count = 0; + ON_confirm_flg = 2; + + RST_confirm_flg = 0; + OFF_confirm_flg = 0; + } + } + else + { + KEY_INL_Count = 0; + } + } + //确认保持开机后，监测按键下一次按下的时长 + else + { + if(OFF_confirm_flg == 0) + { + if(key_state == 1) //输入高电平 + { + KEY_INL_Count = 0; + + KEY_INH_Count++; + if((KEY_INH_Count > OFF_WAIT) && (OFF_confirm_flg == 0)) //按下3s，执行关机操作 + { + KEY_INH_Count = 0; + RST_confirm_flg = 0; + OFF_confirm_flg = 1; + + power_old = 4; //写入关机 + power_state = 0; + } + else if((KEY_INH_Count > RST_WAIT) && (RST_confirm_flg == 0)) //按下1s，执行复位操作 + { + RST_confirm_flg = 1; + led_toggle_step = 0; + } + } + else + { + KEY_INH_Count = 0; + + if(RST_confirm_flg == 2) //复位完成后，在按键松开后清零标志 + { + KEY_INL_Count++; + if(KEY_INL_Count > 3) //防抖动 + { + KEY_INL_Count = 0; + RST_confirm_flg = 0; + } + } + } + } + } +} + +////ON: ≥100uS +//void BAL_On(void) +//{ +// GPIO_ResetBits(GPIOC, PIN_BAL_OUT); +// delay_us(200); +// GPIO_SetBits(GPIOC, PIN_BAL_OUT); +// delay_us(200); +// GPIO_ResetBits(GPIOC, PIN_BAL_OUT); +// delay_us(200); +//} + +////OFF: 20-50uS +//void BAL_Off(void) +//{ +// GPIO_ResetBits(GPIOC, PIN_BAL_OUT); +// delay_us(20); +// GPIO_SetBits(GPIOC, PIN_BAL_OUT); +// delay_us(20); +// GPIO_ResetBits(GPIOC, PIN_BAL_OUT); +// delay_us(20); +//} + +//1S +void MCU_BalanceProcess(void) +{ + //高温关闭均衡 + if( ((bmsMem.bStatus2 & 0x0A) !=0) || ((bmsMem.temperaStatus & 0x03) !=0) ) + { + if((bmsMem.balanceStatus & 0x01) != 0) + { +// BAL_Off(); + bmsMem.balanceStatus &= 0xfffe; + } + + balancing = 0; + } + else + { + if( (cellVoltageMax - cellVoltageMin) > paraMem.act_bal_startV) + { + if((bmsMem.balanceStatus & 0x01) == 0) + { +// BAL_On(); +// bmsMem.balanceStatus |= 0x01; //BAL status set to 1 + } + + balancing = 1; + balCount = 0; + } + else if( (cellVoltageMax - cellVoltageMin) < paraMem.act_bal_stopV) + { + balCount++; + if(balCount >= paraMem.act_bal_stopT) + { + if((bmsMem.balanceStatus & 0x01) != 0) + { +// BAL_Off(); + bmsMem.balanceStatus &= 0xfffe; + } + + balancing = 0; + } + } + } +} + +void DO_On(void) //DO控制继电器开启 +{ + GPIO_SetBits(GPIOA, PIN_DO); +} + +void DO_Off(void) //DO控制继电器关闭 +{ + GPIO_ResetBits(GPIOA, PIN_DO); +} + +//void WARM_On(void) //加热开启 +//{ +// GPIO_SetBits(GPIOC, PIN_WARM); +//} + +//void WARM_Off(void) //加热关闭 +//{ +// GPIO_ResetBits(GPIOC, PIN_WARM); +//} + +////加热触发与控制 +//uint8_t warm_flag; //加热启动标志 +//uint8_t warm_count; +//uint8_t warmr_count; +//void WARM_Ctrl(void) +//{ +// uint16_t utc = bmsMem.mcu_utc * 10 + 2731; +// uint16_t utcr = bmsMem.mcu_utcr * 10 + 2731; +// +// //加热触发 +// if((bmsMem.bStatus1 & 0x0202) == 0) //触发总体/单体欠压，禁止加热 +// { +// if((warm_flag == 0) && (bCHGING == 1)) +// { +// if(TemperatureMin < utc) +// { +// warm_count++; +// if(warm_count > 3) +// { +// warm_flag = 1; +// warm_count = 0; +// } +// } +// else +// { +// warm_count = 0; +// } +// } +// } +// else +// { +// warm_flag = 0; +// warm_count = 0; +// warmr_count = 0; +// } +// +// //加热释放 +// if(warm_flag == 1) +// { +// if(TemperatureMin > utcr+20) //比释放值高2度 +// { +// warmr_count++; +// if(warmr_count > 3) +// { +// warm_flag = 0; +// warmr_count = 0; +// } +// } +// else +// { +// warmr_count = 0; +// } +// } +// +// //加热控制 +// if(warm_flag == 1) +// { +// WARM_On(); +// } +// else +// { +// WARM_Off(); +// } +//} + +void PCHG_On(void) //预充开启 +{ + GPIO_SetBits(GPIOC, PIN_PCHG_CTRL); +} + +void PCHG_Off(void) //预充关闭 +{ + GPIO_ResetBits(GPIOC, PIN_PCHG_CTRL); +} + +void PCHG_StartCtrl(void) //开机开启预充 +{ + //开始节点是1，结束是paraMem.pchg_startTime+1 + PCHG_startCnt++; + + //通过负载电压判断是否是真短路 + if(PCHG_startCnt == 2) //此时已充了1s + { + PCHG_Off(); + bmsMem.bStatus3 &= ~0x0004; //预充MOS关闭 + + delay_ms(2); + LOAD_VOL(); + if(loadvol < paraMem.pchg_scVol*1000) //负载电压小于10V说明短路；如果是空载则≈电池电压 + { + bmsMem.bStatus2 |= 0x0010; //显示“真短路保护”，不能继续预充 + return; + } + } + + //预充开启定时 + if(PCHG_startCnt <= paraMem.pchg_startTime) + { + PCHG_On(); + bmsMem.bStatus3 |= 0x0004; //预充MOS打开 + bmsMem.bStatus3 |= 0x0020; //预充状态开启 + } + else + { + PCHG_startFlag = 1; + PCHG_startCnt = 0; + + PCHG_Off(); + bmsMem.bStatus3 &= ~0x0004; //预充MOS关闭 + bmsMem.bStatus3 &= ~0x0020; //预充状态关闭 + + delay_ms(2); + CTRL_On(); + } +} + +void PCHG_Ctrl(void) //开放电MOS前开启预充 +{ + //开始节点是1，结束是paraMem.pchg_startTime+1 + PCHG_Cnt++; + + //通过负载电压判断是否是真短路 + if(PCHG_Cnt == 2) //此时已充了1s + { + PCHG_Off(); + bmsMem.bStatus3 &= ~0x0004; //预充MOS关闭 + + delay_ms(2); + LOAD_VOL(); + if(loadvol < paraMem.pchg_scVol*1000) //负载电压小于10V说明短路；如果是空载则≈电池电压 + { + CTRL_Off(); + bmsMem.bStatus2 |= 0x0010; //显示“真短路保护”，不能继续预充 + return; + } + } + + //预充开启定时 + if(PCHG_Cnt <= paraMem.pchg_Time) + { + PCHG_On(); + bmsMem.bStatus3 |= 0x0004; //预充MOS打开 + bmsMem.bStatus3 |= 0x0020; //预充状态开启 + } + else + { + PCHG_Flag = 2; + PCHG_Cnt = 0; + + PCHG_Off(); + bmsMem.bStatus3 &= ~0x0004; //预充MOS关闭 + bmsMem.bStatus3 &= ~0x0020; //预充状态关闭 + + delay_ms(2); + CTRL_On(); + } +} + +//在触发浪涌短路时，执行真短路判定 +void TSC_Detect(void) +{ + /**正常情况下**/ + if(TSC_detectFlag == 1) + { + CTRL_Off(); + + delay_ms(2); + + LOAD_VOL(); + if(loadvol < paraMem.sp_scVol*1000) //认为是短路情况，显示“真短路保护” + { + TSC_detectFlag = 0xAA; + } + else //检测正常后，回到正常控制 + { + CTRL_On(); + TSC_detectFlag = 2; + } + } + /**遇到[真短路]的情况，控制充放MOS关闭不变**/ + else if(TSC_detectFlag == 0xAA) + { + CTRL_Off(); + bmsMem.bStatus2 |= 0x0010; //显示“真短路保护” + } +} + +#if Addr_SetAuto +//输入电平检测 +uint8_t IO3_IN(void) +{ + uint8_t status; + status = GPIO_ReadInputDataBit(GPIOC,PIN_ADDR_RANK); + + return status; +} + +//输出置高，让下一个从机进入待分配状态 +void IO2_OUTSet(void) +{ + GPIO_SetBits(GPIOC, PIN_ADDR_OUT); +} + +//输出置低，转回正常状态 +void IO2_OUTReset(void) +{ + GPIO_ResetBits(GPIOC, PIN_ADDR_OUT); +} + +//输入电平检测 +uint8_t IO1_IN(void) +{ + uint8_t status; + status = GPIO_ReadInputDataBit(GPIOC,PIN_ADDR_IN); + + return status; +} + +//根据IO1的不同电平，进行地址修改操作 +uint8_t IO1_INH_Count; +uint8_t IO1_INL_Count; +void ADDR_Assign_Moni(void) +{ + if(((bmsMem.E2_485Addr >=2) && (bmsMem.E2_485Addr <= AddrMax+1))) //地址为实地址的从机 and 特定虚地址的从机(避免分配时出现意外) + { + if( IO1_IN() == 1 ) //输入高电平 + { + if(IO1_INH_Count < 10) + { + IO1_INH_Count++; //等待100ms + } + else + { + bmsMem.E2_485Addr = 99; //修改为虚地址 + } + } + else + { + IO1_INH_Count = 0; + } + } + else if(bmsMem.E2_485Addr > AddrMax+1)//地址本身就为虚地址的从机 + { + if( IO1_IN() == 0 ) //输入低电平 + { + if(IO1_INL_Count < 10) + { + IO1_INL_Count++; //等待100ms + } + else + { + bmsMem.E2_485Addr = AddrMax+1; //修改为特定的虚地址 + } + } + else + { + IO1_INL_Count = 0; + } + } +} + +//根据IO3的不同电平，确定自身是主机/从机 +void ADDR_Rank_Moni(void) +{ + //地址原来是1，过1s后设2 + if(bmsMem.E2_485Addr == 1) + { + if(assignAddr_State != 1) //进行分配时不动作 + { + if( IO3_IN() == 0 ) //短接 + { + ADDR_Moni_Count++; + if(ADDR_Moni_Count > 100) + { + bmsMem.E2_485Addr = 2; + bmsMem.write_Addr = bmsMem.E2_485Addr; //用于之后写入EEPROM + scr_RdData_Index = bmsMem.E2_485Addr; + + ADDR_Moni_Count = 0; + MODBUS_Init(); + + bmsMem.can_ArrayIndex = 0; + ClearArray_Flag = 1; //用于之后写入EEPROM + } + } + else + { + ADDR_Moni_Count = 0; + } + } + } + //地址原不是1，过5s后设1(可能只是调线子要有容错) + else + { + if( IO3_IN() != 0 ) //没有短接 + { + ADDR_Moni_Count++; + if(ADDR_Moni_Count > 500) + { + assignAddr_State = 0; + assignAddr_relay = 2;//变1后也有可能变回去 + + bmsMem.E2_485Addr = 1; + bmsMem.write_Addr = bmsMem.E2_485Addr; //用于之后写入EEPROM + scr_RdData_Index = bmsMem.E2_485Addr; + + ADDR_Moni_Count = 0; + MODBUS_Init(); + + bmsMem.can_ArrayIndex = 0; + ClearArray_Flag = 1; //用于之后写入EEPROM + } + } + else + { + ADDR_Moni_Count = 0; + } + } +} +#endif + +//IO初始化 +void uf_GPIO_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA , ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB , ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC , ENABLE); + + //PB3,PB4,PA15用作普通IO时需要禁用JTAG保留SWD, 并REMAP + RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO , ENABLE); + GPIO_PinRemapConfig(GPIO_Remap_SWJ_JTAGDisable, ENABLE); + + //LED + GPIO_InitStructure.GPIO_Pin = PIN_LED2 | PIN_LED3 | PIN_LED4 | PIN_LED_ALARM; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOB, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = PIN_LED1; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOC, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = PIN_LED_RUN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + #if Key_PressLong + //上电后灯全灭，之后全亮 + GPIO_ResetBits(GPIOA, PIN_LED_RUN); + GPIO_ResetBits(GPIOC, PIN_LED1); + GPIO_ResetBits(GPIOB, PIN_LED2); + GPIO_ResetBits(GPIOB, PIN_LED3); + GPIO_ResetBits(GPIOB, PIN_LED4); + GPIO_ResetBits(GPIOB, PIN_LED_ALARM); + #else + //上电后灯全亮 + GPIO_SetBits(GPIOA, PIN_LED_RUN); + GPIO_SetBits(GPIOC, PIN_LED1); + GPIO_SetBits(GPIOB, PIN_LED2); + GPIO_SetBits(GPIOB, PIN_LED3); + GPIO_SetBits(GPIOB, PIN_LED4); + GPIO_SetBits(GPIOB, PIN_LED_ALARM); + #endif + + + //PCHG预充控制 + GPIO_InitStructure.GPIO_Pin = PIN_PCHG_CTRL; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOC, &GPIO_InitStructure); + + //DO继电器控制 + GPIO_InitStructure.GPIO_Pin = PIN_DO; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOA, &GPIO_InitStructure); + +// //BAL主动均衡器控制 +// GPIO_InitStructure.GPIO_Pin = PIN_BAL_OUT; +// GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; +// GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; +// GPIO_Init(GPIOC, &GPIO_InitStructure); + + //控制引脚初始电平 + GPIO_ResetBits(GPIOC, PIN_PCHG_CTRL); //预充控制脚，默认关闭状态 + GPIO_ResetBits(GPIOA, PIN_DO); //DO继电器控制脚，默认关闭状态 +// GPIO_ResetBits(GPIOC, PIN_BAL_OUT); //主动均衡控制脚，默认关闭状态 + + + #if DO2_Warm + //加热控制 + GPIO_InitStructure.GPIO_Pin = PIN_WARM; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOC, &GPIO_InitStructure); + + GPIO_ResetBits(GPIOC, PIN_WARM); //加热控制脚，默认关闭状态 + #endif + + + #if Key_PressLong + //按键电平检测 + GPIO_InitStructure.GPIO_Pin = PIN_KEY; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOC, &GPIO_InitStructure); + + //电源维持控制 + GPIO_InitStructure.GPIO_Pin = PIN_POWER; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOC, &GPIO_InitStructure); + + //电源指示灯 + GPIO_InitStructure.GPIO_Pin = PIN_LED_POWER; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOC, &GPIO_InitStructure); + + if(power_old == 1) + { + GPIO_SetBits(GPIOC, PIN_POWER); //电源维持控制脚，置高 + GPIO_SetBits(GPIOC, PIN_LED_POWER); //电源指示灯亮 + } + else + { + GPIO_ResetBits(GPIOC, PIN_POWER); //电源维持控制脚，开机后默认置低 + GPIO_ResetBits(GPIOC, PIN_LED_POWER); //电源指示灯先不亮 + } + #else + //电源指示灯 + GPIO_InitStructure.GPIO_Pin = PIN_LED_POWER; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOC, &GPIO_InitStructure); + + GPIO_SetBits(GPIOC, PIN_LED_POWER); //电源指示灯直接亮 + #endif + + + #if Addr_SetAuto + //ADDR_IN IO1 + GPIO_InitStructure.GPIO_Pin = PIN_ADDR_IN; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOC, &GPIO_InitStructure); + + //ADDR_OUT IO2 + GPIO_InitStructure.GPIO_Pin = PIN_ADDR_OUT; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOC, &GPIO_InitStructure); + + //ADDR_RANK IO3 + GPIO_InitStructure.GPIO_Pin = PIN_ADDR_RANK; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOC, &GPIO_InitStructure); + + //地址分配引脚初始电平 + GPIO_ResetBits(GPIOC, PIN_ADDR_OUT); //初始化时所有OUT引脚置低 + #endif + + + //AFE-ALARM + GPIO_InitStructure.GPIO_Pin = PIN_AFE_ALARM; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOB, &GPIO_InitStructure); + + //AFE- VPRO/SHIP + GPIO_InitStructure.GPIO_Pin = PIN_SHIP; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + //AFE-CTL(急停控制) + GPIO_InitStructure.GPIO_Pin = PIN_CTLC; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOB, &GPIO_InitStructure); + + //AFE引脚初始电平 + GPIO_SetBits(GPIOA, PIN_SHIP); //初始置高，表示退出仓运模式 + + #if Key_PressLong + if(power_old == 1) + { + GPIO_SetBits(GPIOB, PIN_CTLC);//因为是重启，初始置高，不控制MOS + PCHG_startFlag = 1; //也不执行开机预充 + } + else + { + GPIO_ResetBits(GPIOB, PIN_CTLC);//初始置低，控制MOS全关 + } + #else + GPIO_ResetBits(GPIOB, PIN_CTLC);//初始置低，控制MOS全关 + #endif + + + CHG_LIMIT_Init(); +} + + +//AFE_ALARM 外部EXTI中断配置 +void uf_EXTI_Init(void) +{ +// EXTI_InitTypeDef EXTI_InitStructure; +// NVIC_InitTypeDef NVIC_InitStructure; + +// //BKP_TamperPinCmd(DISABLE); + +// RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO,ENABLE); //外部中断，需要使能AFIO时钟 + +// GPIO_EXTILineConfig(GPIO_PortSourceGPIOB,GPIO_PinSource9); +// EXTI_InitStructure.EXTI_Line=EXTI_Line9; +// EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; +// EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling; // 下降沿 触发 +// EXTI_InitStructure.EXTI_LineCmd = ENABLE; +// EXTI_Init(&EXTI_InitStructure); + + NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2); + +// NVIC_InitStructure.NVIC_IRQChannel = EXTI9_5_IRQn; +// NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; +// NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1; +// NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; +// NVIC_Init(&NVIC_InitStructure); +} + + +////用定时器还是用外部中断去读数据，纠结中... +////用外部中断考虑外部硬件连接有问题会导致读取不到数据 +//void EXTI9_5_IRQHandler(void) +//{ +// bAlarmFlag = 1; +// EXTI_ClearITPendingBit(EXTI_Line9); //清除EXTI0线路挂起位 +//} + diff --git a/BSP/i2c.c b/BSP/i2c.c new file mode 100644 index 0000000..0bbdf04 --- /dev/null +++ b/BSP/i2c.c @@ -0,0 +1,531 @@ +/** + ****************************************************************************** + * @file tim.c + * @author Jerry + * @version V2.1 + * @date 22-April-2022 + * @brief tim program body. + ****************************************************************************** + * @attention + * + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" +#include "global.h" +#include "string.h" +#include "sys.h" +#include "soe.h" + +//64-byte page write buffer +//1,000,000 program/erase cycles +//100 year data retention + +//AT24C256 32K Bytes = 128 * 256 bytes + +//0x0000 不可初始化数据 +//0x0200 厂内可初始化数据 +//0x0400 升级初始化数据 +//0x0800 报警记录数据 + +#define I2C_EEPROM I2C1 +#define I2C_AFE I2C1 +#define DEVICE_ID_EEPROM 0xA0 +#define DEVICE_ID_AFE 0x34 +#define I2C_TIMEOUT_COUNT 10000 + +#define FLASH_PAGE_ADDR 0x0800FC00 //要擦除的FLASH页地址 +#define JUMP_TO_USER 0X20230612 //用户固件更新标记 +#define JUMP_BUTNULL 0XFFFFFFFF //无更新标记 + + +uint8_t IAP_Run; //执行程序时是否正常的标志 + +uint8_t DL_Index; //跳转位置的标识 +uint32_t DL_Addr; //根据标识计算出的位置 +uint32_t DL_Jump; + + +void uf_I2C1_Init(void) +{ + uint8_t tmp[8]; + uint32_t ee_index; + uint16_t ee_pc; + uint16_t ee_num; + + /*初始化IIC*/ + GPIO_InitTypeDef GPIO_InitStructure; + I2C_InitTypeDef I2C_InitStructure; + + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB | RCC_APB2Periph_AFIO, ENABLE); + RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C1,ENABLE); + + /* Configure I2C1 pins: PB6->SCL and PB7->SDA */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6 | GPIO_Pin_7; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD; + GPIO_Init(GPIOB, &GPIO_InitStructure); + + I2C_DeInit(I2C1); + I2C_InitStructure.I2C_Mode = I2C_Mode_I2C; + I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2; + I2C_InitStructure.I2C_Ack = I2C_Ack_Enable; + I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; + I2C_InitStructure.I2C_ClockSpeed = 80000; + I2C_Init(I2C1, &I2C_InitStructure); + + I2C_Cmd(I2C1, ENABLE); + I2C_AcknowledgeConfig(I2C1, ENABLE); + + + /*IAP标志*/ + IAP_Run = 0x55; + EEPROM_WrMulByte(EE_IAP_NEW1,&IAP_Run); + delay_ms(10); + EEPROM_WrMulByte(EE_IAP_NEW2,&IAP_Run); + delay_ms(10); + + /*为兼容此前底层，写入标识*/ + EEPROM_RdMulByte(0,1,1,&DL_Index); + if((DL_Index != 0) && (DL_Index != 1)) //之前未刷过程序 + { + DL_Index = 1; //现在一般是1 + } + + //读出检查，确认是这个位置并且无用户数据/跳转标志，才进行写入 + DL_Addr = FLASH_PAGE_ADDR + 0x10000 * DL_Index; + FLASH_RdWord(DL_Addr, &DL_Jump, 1); + if(DL_Jump == JUMP_BUTNULL) + { + DL_Jump = JUMP_TO_USER; + FLASH_WrData(DL_Addr,(uint16_t *)&DL_Jump,8); + } + //若该位置有值，且不是跳转标志，跳转到另一个位置检查并写入 + else if(DL_Jump != JUMP_TO_USER) + { + DL_Index = (DL_Index==0) ? 1:0; //取另一个地址查询，若仍然不对，那该用户程序不依靠IAP底层 + DL_Addr = FLASH_PAGE_ADDR + 0x10000 * DL_Index; + FLASH_RdWord(DL_Addr, &DL_Jump, 1); + if(DL_Jump == JUMP_BUTNULL) + { + DL_Jump = JUMP_TO_USER; + FLASH_WrData(DL_Addr,(uint16_t *)&DL_Jump,8); + } + } + + + #if LTE_Conn + //上电读OTA升级回复标志 + EEPROM_RdMulByte(EE_OTA_FINE,&tmp[0]); + if((tmp[0] == 0xAA) || (tmp[0] == 0xBB)) + { + LTE_OTA_fineFlag = tmp[0]; + } + else + { + LTE_OTA_fineFlag = 0; + } + #endif + + + /*EEPROM无值，赋默认值，但不主动写入EEPROM*/ + //上电读485地址(先暂时获得一个值，之后根据paraMem参数来决定是否改变) + EEPROM_RdMulByte(EE_ADDR,&tmp[0]); + if((tmp[0]>=1) && (tmp[0]<=AddrMax)) + { + bmsMem.E2_485Addr = tmp[0]; + } + else + { + bmsMem.E2_485Addr = 2; + } + +// //上电读屏幕语言 +// EEPROM_RdMulByte(EE_LANG,&tmp[0]); +// if((tmp[0]==0) || (tmp[0]==1)) //0对应英文，1对应中文 +// { +// language = tmp[0]; +// } +// else +// { +// language = 0; //默认英文 +// } + + #if Addr_SetAuto + uint16_t random; + + //上电读自动分配地址的随机队列标志 + EEPROM_RdMulByte(EE_ASSIGN,&tmp[0]); + random = tmp[0]<<8 | tmp[1]; + if((random>AddrMax) && (random<0xffff)) //AddrMax+1~65534 + { + bmsMem.can_ArrayIndex = random; + } + else + { + bmsMem.can_ArrayIndex = 0; + } + #endif + + //上电读是否需要充电校准总容量 + EEPROM_RdMulByte(EE_FCC_TIME,&tmp[0]); + fcc_Calitimecount = tmp[0]<<24 | tmp[1]<<16 | tmp[2]<<8 | tmp[3]; + + if(fcc_Calitimecount <= timecount) //存的数据不算异常 + { + fcc_CaliStartFlag = 1; //记录了起始时间，说明正在计时等满充 + } + + #if LTE_Conn + //上电读取消绑定标志 + EEPROM_RdMulByte(EE_UNSUB,&tmp[0]); + if(tmp[0] <= 1) + { + LTE_UNSUB_Flag = tmp[0]; + } + else + { + LTE_UNSUB_Flag = 0; + } + #endif + + + /*上电读取记录相关信息*/ + EEPROM_RdMulByte(EE_SOE_INF,tmp); + ee_index = tmp[0]<<24 | tmp[1]<<16 | tmp[2]<<8 | tmp[3]; + ee_pc = tmp[4]<<8 | tmp[5]; + ee_num = tmp[6]<<8 | tmp[7]; + + //当前地址=0或0XFFFF或不为64倍数，初始化地址和记录序号 + if((ee_pc < 0x1000) || (ee_pc > 0x2940) || (ee_pc == 0xffff) || (ee_pc%64 !=0)) + { + soe.pc = RECORD_START_ADDR; + soe.index = 0; + soe.num = 0; + } + else + { + soe.index = ee_index; + soe.pc = ee_pc; + soe.num = ee_num; + } +} + +//EEPROM写多字节，注意写入时不要跨page +uint8_t EEPROM_WrMulByte(uint8_t addrH, uint8_t addrL, uint8_t lenth, uint8_t *data) +{ + uint8_t i; + uint16_t i2c_timeout; + + //I2C总线BUSY + i2c_timeout = I2C_TIMEOUT_COUNT; + while(I2C_GetFlagStatus(I2C_EEPROM,I2C_FLAG_BUSY) == SET) + { + if((i2c_timeout--) == 0) return 9; + } + + /*起始位*/ + I2C_GenerateSTART(I2C_EEPROM, ENABLE); + i2c_timeout = I2C_TIMEOUT_COUNT; + while(I2C_CheckEvent(I2C_EEPROM, I2C_EVENT_MASTER_MODE_SELECT) != SUCCESS) //EV5 + { + if((i2c_timeout--) == 0) return 1; + } + + /*EV5事件检测到，发送Device ID(写)*/ + I2C_Send7bitAddress(I2C_EEPROM, DEVICE_ID_EEPROM, I2C_Direction_Transmitter); + i2c_timeout = I2C_TIMEOUT_COUNT; + while(I2C_CheckEvent(I2C_EEPROM, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) != SUCCESS) //EV6 + { + if((i2c_timeout--) == 0) return 2; + } + + /*EV6事件检测到，发送EEPROM 存储单元地址*/ + //检测EV8,表示发送寄存器空了就可以继续填数据了，无需等待移位寄存器空 + I2C_SendData(I2C_EEPROM, addrH); + i2c_timeout = I2C_TIMEOUT_COUNT; + while(I2C_CheckEvent(I2C_EEPROM, I2C_EVENT_MASTER_BYTE_TRANSMITTING) != SUCCESS) + { + if((i2c_timeout--) == 0) return 3; + } + + /*发送EEPROM 存储单元地址*/ + I2C_SendData(I2C_EEPROM, addrL); + i2c_timeout = I2C_TIMEOUT_COUNT; + while(I2C_CheckEvent(I2C_EEPROM, I2C_EVENT_MASTER_BYTE_TRANSMITTING) != SUCCESS) + { + if((i2c_timeout--) == 0) return 4; + } + + /*发送写入EERPOM数据*/ + for(i=0;i>8) & 0xff; + tempW[1] = data & 0xff; + tempW[2] = tempW[0] ^ 0xff; + tempW[3] = tempW[1] ^ 0xff; + if(EEPROM_WrMulByte(EE_CALI_ZERO,tempW) !=0) + { + return 1; //iic write error + } + + delay_ms(20); //are there? + + if(EEPROM_RdMulByte(EE_CALI_ZERO,tempR) !=0) + { + return 2; //iic read error + } + + for(i=0;i<4;i++) + { + if(tempR[i] != tempW[i]) + { + return 3; //check error + } + } + + return 0; +} + +//write gain cali data to eeprom +uint8_t EEPROM_CALI_WrGain(int16_t data) +{ + uint8_t tempW[4]; + uint8_t tempR[4]; + uint8_t i; + + tempW[0] = (data >>8) & 0xff; + tempW[1] = data & 0xff; + tempW[2] = tempW[0] ^ 0xff; + tempW[3] = tempW[1] ^ 0xff; + if(EEPROM_WrMulByte(EE_CALI_GAIN,tempW) !=0) + { + return 1; + } + + delay_ms(20); + + if(EEPROM_RdMulByte(EE_CALI_GAIN,tempR) !=0) + { + return 2; //iic read error + } + + for(i=0;i<4;i++) + { + if(tempR[i] != tempW[i]) + { + return 3; //check error + } + } + + return 0; +} + +int16_t EEPROM_CALI_RdZero(void) +{ + uint8_t i; + uint8_t tempR[4]; + int16_t result; + + EEPROM_RdMulByte(EE_CALI_ZERO,tempR); + + if(((tempR[0] ^ 0xff) == tempR[2]) && ((tempR[1] ^ 0xff) == tempR[3])) + { + result = tempR[0] << 8 | tempR[1]; + return result; + } + else + { + EEPROM_RdMulByte(2,0,4,tempR); //读取旧地址的数据 + if(((tempR[0] ^ 0xff) == tempR[2]) && ((tempR[1] ^ 0xff) == tempR[3])) + { + //符合存储格式，说明之前校准值保存在旧地址,赋值到新地址，并清除 + EEPROM_WrMulByte(EE_CALI_ZERO,tempR); + delay_ms(5); + result = tempR[0] << 8 | tempR[1]; + + //为了不影响现在在旧地址的数据，将这部分清空 + for(i=0;i<4;i++) + { + tempR[i] = 0xff; + } + EEPROM_WrMulByte(2,0,4,tempR); + delay_ms(5); + EEPROM_WrMulByte(2,4,4,tempR); + delay_ms(5); + } + else + { + result = 0; + } + return result; + } +} + +int16_t EEPROM_CALI_RdGain(void) +{ + uint8_t i; + uint8_t tempR[4]; + int16_t result; + + EEPROM_RdMulByte(EE_CALI_GAIN,tempR); + + if(((tempR[0] ^ 0xff) == tempR[2]) && ((tempR[1] ^ 0xff) == tempR[3])) + { + result = tempR[0] << 8 | tempR[1]; + return result; + } + else + { + EEPROM_RdMulByte(3,0,4,tempR); //读取旧地址的数据 + if(((tempR[0] ^ 0xff) == tempR[2]) && ((tempR[1] ^ 0xff) == tempR[3])) + { + //符合存储格式，说明之前校准值保存在旧地址,赋值到新地址，并清除 + EEPROM_WrMulByte(EE_CALI_GAIN,tempR); + delay_ms(5); + result = tempR[0] << 8 | tempR[1]; + + //为了不影响现在在旧地址的数据，将这部分清空 + for(i=0;i<4;i++) + { + tempR[i] = 0xff; + } + EEPROM_WrMulByte(3,0,4,tempR); + delay_ms(5); + EEPROM_WrMulByte(3,4,4,tempR); + delay_ms(5); + } + else + { + result = 10000; + } + return result; + } +} + diff --git a/BSP/pwm.c b/BSP/pwm.c new file mode 100644 index 0000000..4ade67d --- /dev/null +++ b/BSP/pwm.c @@ -0,0 +1,269 @@ +/** + ****************************************************************************** + * @file pwm.c + * @author + * @version + * @date + * @brief + ****************************************************************************** + * @attention + * + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" +#include "global.h" + +//GPIOA +#define PIN_CHG_LIMIT_PON GPIO_Pin_8 //限流 电源控制管脚 + +//GPIOB +#define PIN_CHG_LIMIT_PWM GPIO_Pin_9 //限流 电流值控制 + +#define BIAS_VOLTAGE (200 * bmsMem.ucCellNum/16) //基准偏差电压值，单位1mV +#define BASE_VOLTAGE (60000 * bmsMem.ucCellNum/16) //基准电压值，单位1mV +#define BASE_CURRENT 10000 //基准/目标电流值10A，单位1mA + +#define MAX_DUTY 99.00f //最大占空比（百分比） +#define MIN_DUTY 50.00f //最小占空比（百分比） + +#define PWM_ARR 3599 //定时器自动重装值（对应0~100%占空比） +#define PWM_PSC 0 //预分频系数（PWM频率=72M/(0+1)/(3599+1) = 20kHz） + +uint8_t curLimit_ctrlFlag; //执行限流开/关的标志 0:关限流 1:开限流 + +float base_duty; //初始电流值偏小最好，对应假设充电器电压是最大值60V + +float old_duty; //有效的上一次调整的占空比 +float duty_cycle; //实时基准占空比 + + +//开限流 +void CHG_LIMIT_On(void) +{ + if(curLimit_ctrlFlag != 1) + { + curLimit_ctrlFlag = 1; + + delay_ms(10); //关充电MOS后，再延时开限流 + + //计算初始占空比 + base_duty = (float)(bmsMem.packVoltage + BIAS_VOLTAGE) / BASE_VOLTAGE * 100; + base_duty = (int)(base_duty * 100 + 0.5) / 100.0f; + if(base_duty < MIN_DUTY) + { + base_duty = MIN_DUTY; + } + else if(base_duty > MAX_DUTY) + { + base_duty = MAX_DUTY; + } + + //限流功能开启 + GPIO_SetBits(GPIOA, PIN_CHG_LIMIT_PON); + //PWM占空比为默认值 + duty_cycle = base_duty; + old_duty = duty_cycle; + PWM_Set_Duty_Percent(duty_cycle); + } +} + +//关限流 +void CHG_LIMIT_Off(void) +{ + if(curLimit_ctrlFlag != 0) + { + curLimit_ctrlFlag = 0; + + //限流功能关闭 + GPIO_ResetBits(GPIOA, PIN_CHG_LIMIT_PON); + //PWM占空比为0% + duty_cycle = 0.00f; + old_duty = duty_cycle; + PWM_Set_Duty_Percent(duty_cycle); + + delay_ms(10); //关限流后，延时开充电MOS + } +} + +//限流控制脚和PWM脚的初始化 +void CHG_LIMIT_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA , ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE); + + //限流充电控制 + GPIO_InitStructure.GPIO_Pin = PIN_CHG_LIMIT_PON; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + GPIO_ResetBits(GPIOA, PIN_CHG_LIMIT_PON); //限流控制脚，默认关闭状态 + + //限流PWM波初始化 + TIM4_PWM_Init(PWM_ARR, PWM_PSC); +} + +/************************************************************************** + ** 初始化TIM4_CH1（PA8）的PWM输出 + ** arr: 定时器自动重装值 + ** psc: 定时器预分频系数 +***************************************************************************/ +void TIM4_PWM_Init(uint16_t arr, uint16_t psc) +{ + GPIO_InitTypeDef GPIO_InitStructure; + TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; + TIM_OCInitTypeDef TIM_OCInitStructure; + + // 开启外设时钟 + RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE); // TIM4+GPIOB时钟 + RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO | RCC_APB2Periph_GPIOB, ENABLE); // 复用功能时钟（必要） + + // 配置PB9为复用推挽输出（PWM必须用复用模式） + GPIO_InitStructure.GPIO_Pin = PIN_CHG_LIMIT_PWM; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; // 复用推挽输出 + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOB, &GPIO_InitStructure); + + // 配置TIM4时基参数 + TIM_TimeBaseStructure.TIM_Period = arr; // 自动重装值 + TIM_TimeBaseStructure.TIM_Prescaler = psc; // 预分频系数 + TIM_TimeBaseStructure.TIM_ClockDivision = 0; // 时钟分割（无分频） + TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; // 向上计数 + TIM_TimeBaseInit(TIM4, &TIM_TimeBaseStructure); + + // 配置TIM4_CH1的PWM模式 + TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1; // PWM模式1：CNT 100.00f) duty_per = 100.00f; + + //转换为定时器CCR值（四舍五入，提升精度） + ccr_val = (u16)(duty_per / 100.00f * PWM_ARR + 0.50f); + + //设置CCR值 + TIM_SetCompare4(TIM4, ccr_val); +} + +/************************************************************************************************* +* 函数名: CHG_LIMIT_PWM_Adjust +* 参 数: 无 +* 返回值: 无 +* 描 述: pwm限流，根据电流来计算占空比，53.4V 10A时占空比为93.0 +*************************************************************************************************/ +void CHG_LIMIT_PWM_Adjust(void) +{ + int16_t cur_diff = bmsMem.packCurrent - BASE_CURRENT; + + //根据电流差值调整占空比，变化越大电流波动越大 + if(cur_diff >= 9000) + { + //电流超过目标9A以上，快速减小占空比（步长5.00，因为大电流有风险） + duty_cycle -= 5.00f; + } + else if(cur_diff >= 5000) + { + //电流超过目标5A以上，快速减小占空比（步长1.50，因为大电流有风险） + duty_cycle -= 1.50f; + } + else if(cur_diff >= 2000) + { + //电流超过目标2A以上，中速减小占空比（步长0.30） + duty_cycle -= 0.30f; + } + else if(cur_diff >= 1000) + { + //电流超过目标1A以上，中速减小占空比（步长0.20） + duty_cycle -= 0.20f; + } + else if(cur_diff >= 500) + { + //电流超过目标0.5A以上，慢速减小占空比（步长0.05） + duty_cycle -= 0.05f; + } + else if(cur_diff >= 100) + { + //电流超过目标0.5A以上，慢速减小占空比（步长0.01） + duty_cycle -= 0.01f; + } + else if(cur_diff <= -9000) + { + //电流低于目标9A以上，快速增大占空比（步长2.00） + duty_cycle += 2.00f; + } + else if(cur_diff <= -5000) + { + //电流低于目标5A以上，快速增大占空比（步长1.00） + duty_cycle += 1.00f; + } + else if(cur_diff <= -2000) + { + //电流低于目标3A以上，中速增大占空比（步长0.30） + duty_cycle += 0.30f; + } + else if(cur_diff <= -1000) + { + //电流低于目标1A以上，中速增大占空比（步长0.20） + duty_cycle += 0.20f; + } + else if(cur_diff <= -500) + { + //电流低于目标0.5A以上，慢速增大占空比（步长0.05） + duty_cycle += 0.05f; + } + else if(cur_diff <= -100) + { + //电流低于目标0.5A以上，慢速增大占空比（步长0.01） + duty_cycle += 0.01f; + } + else + { + //电流差在±500mA（0.5A）以内，占空比保持不变 + duty_cycle = old_duty; + } + + //限制占空比范围 + if(duty_cycle < MIN_DUTY) + { + duty_cycle = MIN_DUTY; + } + else if(duty_cycle > MAX_DUTY) + { + duty_cycle = MAX_DUTY; + } + + old_duty = duty_cycle; + + PWM_Set_Duty_Percent(duty_cycle); +} + diff --git a/BSP/rtc.c b/BSP/rtc.c new file mode 100644 index 0000000..45b79a8 --- /dev/null +++ b/BSP/rtc.c @@ -0,0 +1,793 @@ +/** + ****************************************************************************** + * @file gpio.c + * @author Jerry Cai + * @version V2.1 + * @date 19-April-2022 + * @brief gpio program body. + ****************************************************************************** + * @attention + * + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" +#include "rtc.h" +#include "global.h" + + +#define sleepEnd 60*(paraMem.sleep_min_disable&0x7FFF) //休眠1等待时长min，单位1s +#define sleep2End 60*(paraMem.sleep2_min_disable&0x7FFF) //休眠2等待时长min，单位1s +#define sleep2Vol paraMem.sleep2_vol //休眠方案2对应休眠电压，单位1mV +#define uvoffEnd 300 //强制欠压复位等待时长5min，单位1s +#define ocvEnd 60*(paraMem.ocv_min_disable&0x7FFF) //开路电压校准等待时长min，单位1s +#define fcccaliEnd 60*(paraMem.cali_min_disable&0x7FFF) //校准满充容量等待时长min，单位1s + +_calendar_obj calendar; //时钟结构体 +_calendar_obj calendar_WRITE; +_calendar_obj calendar_BACKUP; + +uint8_t const table_week[12]={0,3,3,6,1,4,6,2,5,0,3,5}; //平年的月修正数据表(基准是1900年1月1日)，闰年其他相同只是1.2月要-1 +const u8 mon_table[12]={31,28,31,30,31,30,31,31,30,31,30,31}; //平年的月份日期表.闰年的2月有29天 + +uint32_t timecount; //当前计时s +uint32_t oldtimecnt; //上一秒的计时s + +uint8_t LSEErrFlag; //外部低频晶振有问题的标志，需要让屏幕的时间不再显示 +uint8_t LSEErrCount;//时间不走的计数，满足了会把时间清零，标志置1 + +uint8_t sleep_flag; //休眠执行标志位 +uint8_t sleep_enableflag;//开启休眠功能标志位 + +uint32_t sleeptimecount; //休眠1的计时起点s +uint32_t sleeptime; //休眠启动的倒计时数 + +uint32_t sleep2timecount; //休眠2的计时起点s +uint32_t sleep2time; //休眠2启动的倒计时数 + +uint32_t uvofftimecount; //关闭欠压功能后的计时起点 +uint16_t uvofftime; //关闭欠压功能的倒计时数(会在屏幕显示故只设uint16) + +uint32_t ocvtimecount; //开路电压法的计时起点 +uint32_t ocvtime; //开路电压法的倒计时数 + +uint32_t fcc_Calitimecount; //校准满充容量的计时起点 +uint32_t fcc_Calitime; //校准满充容量的倒计时数，超过则不可更新 + +uint8_t RTC_UpdateFlag; //起始点刷新标志位，用以刷新休眠和欠压强制复位的时间 + + +/* + * 函数名：Is_Leap_Year + * 描述 ：判断是否为闰年 + 月份 1 2 3 4 5 6 7 8 9 10 11 12 + 闰年 31 29 31 30 31 30 31 31 30 31 30 31 + 非闰年 31 28 31 30 31 30 31 31 30 31 30 31 + * 输入 ：年份 + * 输出 ：该年份是不是闰年.1,是.0,不是 + * 调用 ： + */ +uint8_t Is_Leap_Year(uint8_t yed) +{ + uint8_t year; + + year=2000+yed; + if(year%4==0) //必须能被4整除 + { + if(year%100==0) + { + if(year%400==0) + return 1;//如果以00结尾,还要能被400整除 + else + return 0; + } + else + { + return 1; + } + } + else + { + return 0; + } +} + +/* + * 函数名：RTC_Get_Week + * 描述 ：输入公历日期得到星期 + * 输入 ：公历年月日 + * 输出 ：星期号 + * 调用 ： + */ +uint8_t RTC_Get_Week(uint8_t ye, uint8_t month, uint8_t day) +{ + uint16_t temp2; + uint16_t year; + uint8_t yearH,yearL; + + ye=ye/16*10+ye%16; //十六进制转十进制 + month=month/16*10+month%16; + day=day/16*10+day%16; + + year=2000+ye; //(输入格式决定了必定是21世纪) + yearH=year/100;//用于判断是21世纪 + yearL=year%100;//用于计算多的年数 + + //计算自1900年1月1日以来积累的多出来的天数 + temp2=yearL+yearL/4; //平年365%7=1 闰年366%7=2 (自动把可以略去的7的倍数略掉了)(不用计算/100和/400) + temp2=temp2%7; + temp2=temp2+day+table_week[month-1]; + + // 21世纪需要加6(因为1900年1月1日是星期一，2000年1月1日是星期六) + if(yearH == 20) + { + temp2+=6; + } + + //若日期是闰年的1.2月，星期修正要-1 + if(yearL%4==0&&month<3) + { + temp2--; + } + + return(temp2%7!=0)?temp2%7:7; //周一到周日=1~7 +} + +/* + * 函数名：RTC_Get + * 描述 ：根据RTC计算器值计算当前年/月/日/时/分/秒/星期放入calendar结构体 + * 输入 ：无 + * 输出 ：0，成功；其他：错误代码 + * 调用 ： + */ +uint8_t RTC_Get(void) +{ + static uint16_t daycnt=0; + uint32_t temp=0; + uint16_t temp1=0; + uint16_t tempppy; + + timecount=RTC_GetCounter(); + + /*时分秒的计算*/ + #if LTE_Conn + temp=(timecount+28800)/86400; //得到(总秒钟数对应的)天数 //在计算年月日时，中国时区-8h + #else + temp=timecount/86400; //得到(总秒钟数对应的)天数 + #endif + + if(daycnt!=temp)//超过一天了 + { + daycnt=temp; + + temp1=1970; //计算年份，从1970年开始 + while(temp>=365) + { + if(Is_Leap_Year(temp1))//闰年-366 + { + if(temp>=366)temp-=366; + else {temp1++;break;} + } + else temp-=365; //平年-365 + temp1++; + } + tempppy=temp1; + + temp1=0; //计算月份，最后的temp就是日期 + while(temp>=28) + { + if(Is_Leap_Year(tempppy)&&temp1==1)//闰年且是2月份-29 + { + if(temp>=29)temp-=29; + else break; + } + else + { + if(temp>=mon_table[temp1])temp-=mon_table[temp1];//其他都按表上来 + else break; + } + temp1++; + } + + tempppy=tempppy-2000;//得到年份 + calendar.w_year =(tempppy/10)*16+(tempppy%10); + + temp1=temp1+1; //得到月份 + calendar.w_month=(temp1/10)*16+(temp1%10); + + temp=temp+1; //得到日期 + calendar.w_date=(temp/10)*16+(temp%10); + } + + #if LTE_Conn + temp=(timecount+28800)%86400; //得到(去掉天数后 当天的)秒钟数 //在计算年月日时，中国时区-8h + #else + temp=timecount%86400; //得到(去掉天数后 当天的)秒钟数 + #endif + + tempppy=temp/3600; //得到小时 + calendar.hour=(tempppy/10)*16+(tempppy%10); + + tempppy=(temp%3600)/60;//得到分钟 + calendar.min=(tempppy/10)*16+(tempppy%10); + + tempppy=(temp%3600)%60;//得到秒钟 + calendar.sec=(tempppy/10)*16+(tempppy%10); + calendar.week=RTC_Get_Week(calendar.w_year,calendar.w_month,calendar.w_date);//获取星期 + + + /*判断合法*/ + //在初始化后的第一次调用时，oldtimecnt还未赋值，此时将合法的当前时间写入EEPROM + if(oldtimecnt==0) + { + oldtimecnt = timecount; + + if(calendar.w_month != 0) + { + uint8_t tmpRd[6]; + tmpRd[0] = calendar.w_year; + tmpRd[1] = calendar.w_month; + tmpRd[2] = calendar.w_date; + tmpRd[3] = calendar.hour; + tmpRd[4] = calendar.min; + tmpRd[5] = calendar.sec; + + EEPROM_WrMulByte(EE_TIME_BACKUP,tmpRd); + delay_ms(5); + } + } + + //当时钟一直不走，判定有问题 + if(timecount==oldtimecnt) + { + LSEErrCount++; + if(LSEErrCount>10) + { + LSEErrFlag=1; + sleep_Moni_Count=SLEEP_MON_CNT; + sleep2_Moni_Count = SLEEP2_MON_CNT; + + calendar.w_year = 0; //结构体清零，方便此时的报警记录计入的时间为全0无效值 + calendar.w_month = 0; + calendar.w_date = 0; + calendar.week = 0; + calendar.hour = 0; + calendar.min = 0; + calendar.sec = 0; + + return 1; //数据异常，返回1 + } + } + else + { + LSEErrCount=0; + oldtimecnt = timecount; + } + + + //休眠功能-RTC，比较当前秒与开始秒的差别来定时 + //方案1 + if((sleep_flag == 0) && ((sleep_enableflag & 0x01) != 0)) //未进入休眠+启用休眠方案1 + { + if(sleeptimecount != 0) + { + if(RTC_UpdateFlag == 1) + { + sleeptimecount = timecount - (sleepEnd - sleeptime); //更新起始点=当前时间-已消耗时间，此时剩余时间保持原值 + } + else + { + sleeptime = sleepEnd - (timecount - sleeptimecount); //更新剩余时间 + } + + if((sleeptime == 0) || (sleeptime > sleepEnd)) + { + sleep_flag = 1; + + #if LTE_Conn + pre_sleep_flag = 2; + pre_sleep_waitCnt = 0; + sleepOn_time=timecount; + #endif + } + } + else + { + sleeptimecount = timecount; + } + } + //方案2 + if((sleep_flag == 0) && ((sleep_enableflag & 0x02) != 0)) //未进入休眠+启用休眠方案2 + { + //满足休眠电压，无充电电流 + if((cellVoltageMin <= sleep2Vol) && (bmsMem.packCurrent < 500)) + { + if(sleep2timecount != 0) + { + if(RTC_UpdateFlag == 1) + { + sleep2timecount = timecount - (sleep2End - sleep2time); //更新起始点=当前时间-已消耗时间，此时剩余时间保持原值 + } + else + { + sleep2time = sleep2End - (timecount - sleep2timecount); //更新剩余时间 + } + + if((sleep2time == 0) || (sleep2time > sleep2End)) + { + #if Key_PressLong + power_old = 4; //写入关机 + power_state = 0; + #else + sleep_flag = 1; + + #if LTE_Conn + pre_sleep_flag = 2; + pre_sleep_waitCnt = 0; + sleepOn_time=timecount; + #endif + #endif + } + } + else + { + sleep2timecount = timecount; + } + } + //否则停止计时 + else + { + sleep2timecount = 0; + } + } + //不启用任何休眠方案 + if(sleep_enableflag == 0) + { + sleep_flag = 0; + } + + //屏幕手动关欠压启动了 + if((bmsMem.balanceStatus & 0x20) != 0) + { + if(RTC_UpdateFlag == 1) + { + uvofftimecount = timecount - (uvoffEnd - uvofftime); //更新起始点=当前时间-已消耗时间，此时剩余时间保持原值 + } + else + { + uvofftime = uvoffEnd - (timecount - uvofftimecount); + } + + if((uvofftime == 0) || (uvofftime > uvoffEnd)) //防止反向溢出 + { + bmsMem.balanceStatus &= 0xffdf; + } + } + + //开路电压法校准SOC启动了 + if(OCV_Wait_flag == 1) + { + if(RTC_UpdateFlag == 1) + { + ocvtimecount = timecount - (ocvEnd - ocvtime); //更新起始点=当前时间-已消耗时间，此时剩余时间保持原值 + } + else + { + ocvtime = ocvEnd - (timecount - ocvtimecount); + } + + if((ocvtime == 0) || (ocvtime > ocvEnd)) //防止反向溢出 + { + OCV_CaliSOC_flag = 1; + } + } + + //充电校准满充容量的倒计时启动了 + if(fcc_CaliStartFlag == 1) + { + if(RTC_UpdateFlag == 1) + { + fcc_Calitimecount = timecount - (fcccaliEnd - fcc_Calitime); //更新起始点=当前时间-已消耗时间，此时剩余时间保持原值 + } + else + { + fcc_Calitime = fcccaliEnd - (timecount - fcc_Calitimecount); + } + + if((fcc_Calitime == 0) || (fcc_Calitime > fcccaliEnd)) //防止反向溢出 + { + fcc_CaliStartFlag = 0; + + EEPROM_WrMulByte(EE_FCC_TIME,ClearEE); + delay_ms(5); + } + } + + //该刷新的都刷新后，标志置0 + if(RTC_UpdateFlag != 0) + { + RTC_UpdateFlag = 0; + } + + return 0; +} + +/* + * 函数名：RTC_Set + * 描述 ：把输入的年/月/日/时/分/秒转换为秒钟 写入RTC计数器 + 以1970年1月1日为基准 + * 输入 ：无 + * 输出 ：0，成功；1：错误代码 + * 调用 ： + */ +uint8_t RTC_Set(uint8_t ear,uint8_t smon,uint8_t sday,uint8_t hour,uint8_t min,uint8_t sec) +{ + uint16_t t,syear; + uint32_t seccount=0; + + ear=(ear/16)*10+ear%16; + smon=(smon/16)*10+smon%16; + sday=(sday/16)*10+sday%16; + hour=(hour/16)*10+hour%16; + min=(min/16)*10+min%16; + sec=(sec/16)*10+sec%16; + + syear=2000+ear; + if(syear<1970||syear>2099) //1970~2099年为合法年份 + { + return 1; + } + for(t=1970;tCRL &= (uint16_t)~RTC_FLAG_RSF; + /* Loop until RSF flag is set */ + while ((RTC->CRL & RTC_FLAG_RSF) == (uint16_t)RESET) + { + temp++; + if(temp>=2000) return 1; //初始化时钟失败,晶振有问题 + delay_ms(1); //1ms延时，总共2s + } + + return 0; +} + +/* + * 函数名：uf_RTC_Init + * 描述 ：RTC初始化配置.第一次配置时会写入2023-6-25 14:00:00. + * 输入 ：无 + * 输出 ：0，成功；1：错误代码 + * 调用 ： + */ +//开机执行一次 +//第一次配置写入2023-6-25 14:00:00，此后正常读RTC后备寄存器的存值。若RTC值意外丢失则读EEPROM存值使用 +uint8_t uf_RTC_Init(void) +{ + uint16_t temp=0; + uint8_t tmpRd[6]; + + //上电读备份的时间信息 + EEPROM_RdMulByte(EE_TIME_BACKUP,tmpRd); + if((tmpRd[0]!=0xff) && (tmpRd[1]!=0xff) && (tmpRd[2]!=0xff) && (tmpRd[3]!=0xff) && (tmpRd[4]!=0xff) && (tmpRd[5]!=0xff)) //时分秒格式存储，不可能存在0xff + { + calendar_BACKUP.w_year = tmpRd[0]; + calendar_BACKUP.w_month = tmpRd[1]; + calendar_BACKUP.w_date = tmpRd[2]; + calendar_BACKUP.hour = tmpRd[3]; + calendar_BACKUP.min = tmpRd[4]; + calendar_BACKUP.sec = tmpRd[5]; + } + else + { + //0x23,0x06,0x25,0x14,0x00,0x00 + calendar_BACKUP.w_year = 0x23; + calendar_BACKUP.w_month = 0x06; + calendar_BACKUP.w_date = 0x25; + calendar_BACKUP.hour = 0x14; + calendar_BACKUP.min = 0x00; + calendar_BACKUP.sec = 0x00; + } + + + RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE); //使能PWR和BKP外设时钟 + PWR_BackupAccessCmd(ENABLE); //使能后备寄存器访问 + + if(BKP_ReadBackupRegister(BKP_DR1) != 0x5050) //检查是不是第一次配置时钟 + { +// /*使用内部低速晶振*/ +// BKP_DeInit(); //复位备份区域 +// RCC_LSICmd(ENABLE); //使能LSI时钟 +// while (RCC_GetFlagStatus(RCC_FLAG_LSIRDY) == RESET) //等待LSI晶振就绪 +// { +// temp++; +// if(temp>=5000) return 1; //持续5s无法起振，初始化时钟失败,晶振有问题 +// delay_ms(1); // 1ms延时 +// } +// RCC_RTCCLKConfig(RCC_RTCCLKSource_LSI); //设置RTC时钟(RTCCLK),选择LSI作为RTC的时钟源 +// RCC_RTCCLKCmd(ENABLE); //使能RTC时钟 +// RTC_WaitForLastTask(); //等待最近一次对RTC寄存器的写操作完成 +// RTC_WaitForSynchro(); //等待RTC寄存器同步 +// RTC_ITConfig(RTC_IT_SEC, ENABLE); //使能RTC秒中断 +// RTC_WaitForLastTask(); //等待最近一次对RTC寄存器的写操作完成 +// RTC_EnterConfigMode(); //允许配置 +// RTC_SetPrescaler(40000 - 1); //设置RTC预分频的值40kHz +// RTC_WaitForLastTask(); //等待最近一次对RTC寄存器的写操作完成 +// /*使用内部低速晶振*/ + + /*使用外部低速晶振*/ + BKP_DeInit(); //复位备份区域 + RCC_LSEConfig(RCC_LSE_ON); //设置外部低速晶振(LSE),使用外设低速晶振 + while (RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET) //检查指定的RCC标志位设置与否,等待低速晶振就绪 + { + temp++; + if(temp>=5000) return 1; //持续5s无法起振，初始化时钟失败,晶振有问题 + delay_ms(1); // 1ms延时 + } + RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE); //设置RTC时钟(RTCCLK),选择LSE作为RTC时钟 + RCC_RTCCLKCmd(ENABLE); //使能RTC时钟 + RTC_WaitForLastTask(); //等待最近一次对RTC寄存器的写操作完成 + RTC_WaitForSynchro(); //等待RTC寄存器同步 + RTC_ITConfig(RTC_IT_SEC, ENABLE); //使能RTC秒中断 + RTC_WaitForLastTask(); //等待最近一次对RTC寄存器的写操作完成 + RTC_EnterConfigMode(); // 允许配置 + RTC_SetPrescaler(32767); //设置RTC预分频的值 + RTC_WaitForLastTask(); //等待最近一次对RTC寄存器的写操作完成 + /*使用外部低速晶振*/ + + + //RTC_Set(0x23,0x06,0x25,0x14,0x00,0x00); + RTC_Set(calendar_BACKUP.w_year,calendar_BACKUP.w_month,calendar_BACKUP.w_date,calendar_BACKUP.hour,calendar_BACKUP.min,calendar_BACKUP.sec); + + RTC_ExitConfigMode(); //退出配置模式 + BKP_WriteBackupRegister(BKP_DR1, 0x5050); //向指定的后备寄存器中写入指定数据 + } + else//系统继续计时 + { +// /*使用内部低速晶振*/ +// RCC_LSICmd(ENABLE); //使能LSI时钟 +// while (RCC_GetFlagStatus(RCC_FLAG_LSIRDY) == RESET) //等待LSI晶振就绪 +// { +// temp++; +// if(temp>=5000) return 1; //持续5s无法起振，初始化时钟失败,晶振有问题 +// delay_ms(1); // 1ms延时 +// } +// RCC_RTCCLKCmd(ENABLE); //使能RTC时钟 +// /*使用内部低速晶振*/ + + if(RTC_GetSynchro() == 1)return 1; //等待RTC寄存器同步 //10.8 晶振坏了这里会卡死，所以增加超时失败退出 + RTC_WaitForLastTask(); //等待最近一次对RTC寄存器的写操作完成 + } + + + /**更多功能**/ + //更新当前时间 + timecount=RTC_GetCounter(); + + //若启用休眠1，则以当前秒数为起始点 + if((paraMem.sleep_min_disable & 0x8000) == 0) //0代表启用休眠 + { + sleep_enableflag |= 0x01; + + sleeptimecount=timecount; + } + else + { + sleep_enableflag &= 0xfe; + } + //若启用休眠2，则判断此时最低电压是否满足条件，满足则以当前秒数为起始点 + if((paraMem.sleep2_min_disable & 0x8000) == 0) //0代表启用休眠 + { + sleep_enableflag |= 0x02; + + //满足休眠电压，无均衡，无电流 + if((cellVoltageMin <= sleep2Vol) && ((bmsMem.balanceStatus & 0x0001) == 0) && (bmsMem.packCurrent > (-200)) && (bmsMem.packCurrent < 200)) + { + //无除过压以外的保护 + if(((bmsMem.bStatus1 & 0x067e) == 0) && ((bmsMem.bStatus2 & 0x00ff) == 0) && ((bmsMem.bStatus3 & 0x0008) == 0) && ((bmsMem.temperaStatus & 0x0f7f) == 0)) + { + sleep2timecount=timecount; + } + } + } + else + { + sleep_enableflag &= 0xfd; + } + + return 0; //ok +} + +/* + * 函数名：uf_RTC_Update + * 描述 ：将calendar_WRITE结构体的值写入RTC时间 + * 输入 ：无 + * 输出 ：0，成功；1：错误代码 + * 调用 ： + */ +uint8_t uf_RTC_Update(void) +{ + if(calendar_WRITE.w_month != 0) //有写入的数组 + { + uint16_t temp=0; + uint8_t Wrtime[6]; + + RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE); //使能PWR和BKP外设时钟 + PWR_BackupAccessCmd(ENABLE); //使能后备寄存器访问 + + +// /*使用内部低速晶振*/ +// BKP_DeInit(); //复位备份区域 +// RCC_LSICmd(ENABLE); //使能LSI时钟 +// while (RCC_GetFlagStatus(RCC_FLAG_LSIRDY) == RESET) //等待LSI晶振就绪 +// { +// temp++; +// if(temp>=5000) return 1; //持续5s无法起振，初始化时钟失败,晶振有问题 +// delay_ms(1); // 1ms延时 +// } +// RCC_RTCCLKConfig(RCC_RTCCLKSource_LSI); //设置RTC时钟(RTCCLK),选择LSI作为RTC的时钟源 +// RCC_RTCCLKCmd(ENABLE); //使能RTC时钟 +// RTC_WaitForLastTask(); //等待最近一次对RTC寄存器的写操作完成 +// RTC_WaitForSynchro(); //等待RTC寄存器同步 +// RTC_ITConfig(RTC_IT_SEC, ENABLE); //使能RTC秒中断 +// RTC_WaitForLastTask(); //等待最近一次对RTC寄存器的写操作完成 +// RTC_EnterConfigMode(); //允许配置 +// RTC_SetPrescaler(40000 - 1); //设置RTC预分频的值40kHz +// RTC_WaitForLastTask(); //等待最近一次对RTC寄存器的写操作完成 +// /*使用内部低速晶振*/ + + /*使用外部低速晶振*/ + BKP_DeInit(); //复位备份区域 + RCC_LSEConfig(RCC_LSE_ON); //设置外部低速晶振(LSE),使用外设低速晶振 + while (RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET) //检查指定的RCC标志位设置与否,等待低速晶振就绪 + { + temp++; + if(temp>=5000) return 1; //持续5s无法起振，初始化时钟失败,晶振有问题 + delay_ms(1); // 1ms延时 + } + RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE); //设置RTC时钟(RTCCLK),选择LSE作为RTC时钟 + RCC_RTCCLKCmd(ENABLE); //使能RTC时钟 + RTC_WaitForLastTask(); //等待最近一次对RTC寄存器的写操作完成 + RTC_WaitForSynchro(); //等待RTC寄存器同步 + RTC_ITConfig(RTC_IT_SEC, ENABLE); //使能RTC秒中断 + RTC_WaitForLastTask(); //等待最近一次对RTC寄存器的写操作完成 + RTC_EnterConfigMode(); // 允许配置 + RTC_SetPrescaler(32767); //设置RTC预分频的值 + RTC_WaitForLastTask(); //等待最近一次对RTC寄存器的写操作完成 + /*使用外部低速晶振*/ + + + RTC_Set(calendar_WRITE.w_year,calendar_WRITE.w_month,calendar_WRITE.w_date,calendar_WRITE.hour,calendar_WRITE.min,calendar_WRITE.sec); + + RTC_ExitConfigMode(); //退出配置模式 + BKP_WriteBackupRegister(BKP_DR1, 0x5050); //向指定的后备寄存器中写入用户程序数据 + + //刷新休眠和欠压复位的时间 + RTC_UpdateFlag = 1; + //存储时间备份 + Wrtime[0] = calendar_WRITE.w_year; + Wrtime[1] = calendar_WRITE.w_month; + Wrtime[2] = calendar_WRITE.w_date; + Wrtime[3] = calendar_WRITE.hour; + Wrtime[4] = calendar_WRITE.min; + Wrtime[5] = calendar_WRITE.sec; + EEPROM_WrMulByte(EE_TIME_BACKUP,Wrtime); + delay_ms(5); + //清零 + calendar_WRITE.w_year = 0; + calendar_WRITE.w_month = 0; + calendar_WRITE.w_date = 0; + calendar_WRITE.week = 0; + calendar_WRITE.hour = 0; + calendar_WRITE.min = 0; + calendar_WRITE.sec = 0; + } + + return 0; //ok +} + +//用于处理因各种原因需要的时间备份 +int32_t oldCur; +void RTC_BackUp(void) +{ + uint8_t WrFlag=0; + + //当正在充放电，开始时记录一次，之后每5分钟记录一次 + if(bCHGING == 1) + { + if(oldCur <= 0) //原来在放电或待机 + { + WrFlag = 1; + oldCur = bmsMem.packCurrent; + } + + if((calendar.min%5 == 0x00) && (calendar.sec == 0x00)) + { + WrFlag = 1; + } + } + else if(bDSGING == 1) + { + if(oldCur >= 0) //原来在充电或待机 + { + WrFlag = 1; + oldCur = bmsMem.packCurrent; + } + + if((calendar.min%5 == 0x00) && (calendar.sec == 0x00)) + { + WrFlag = 1; + } + } + //在待机状态，每1h记录一次 + else + { + oldCur = 0; + + if((calendar.min == 0x00) && (calendar.sec == 0x00)) + { + WrFlag = 1; + } + } + + //需要写入备份时间，执行 + if(WrFlag == 1) + { + if(calendar.w_month != 0) + { + uint8_t tmpRd[6]; + tmpRd[0] = calendar.w_year; + tmpRd[1] = calendar.w_month; + tmpRd[2] = calendar.w_date; + tmpRd[3] = calendar.hour; + tmpRd[4] = calendar.min; + tmpRd[5] = calendar.sec; + + EEPROM_WrMulByte(EE_TIME_BACKUP,tmpRd); + delay_ms(5); + } + } +} + diff --git a/BSP/rtc.h b/BSP/rtc.h new file mode 100644 index 0000000..d92ceb7 --- /dev/null +++ b/BSP/rtc.h @@ -0,0 +1,28 @@ +#ifndef __RTC_H +#define __RTC_H +#include "stm32f10x.h" + +//时间结构体 +typedef struct +{ + vu8 sec; + vu8 min; + vu8 hour; + vu8 week; + vu8 w_date; + vu8 w_month; + vu8 w_year; +}_calendar_obj; + +extern _calendar_obj calendar; //日历结构体 +extern _calendar_obj calendar_WRITE; +extern _calendar_obj calendar_BACKUP; + +extern uint8_t uf_RTC_Init(void); +extern uint8_t uf_RTC_Update(void); //用于上位机修改时间 +extern uint8_t RTC_Set(uint8_t ear,uint8_t smon,uint8_t sday,uint8_t hour,uint8_t min,uint8_t sec); +extern uint8_t RTC_Get(void); +extern void RTC_BackUp(void); + + +#endif diff --git a/BSP/spi.c b/BSP/spi.c new file mode 100644 index 0000000..a2c58f3 --- /dev/null +++ b/BSP/spi.c @@ -0,0 +1,234 @@ +/** + ****************************************************************************** + * @file spi.c + * @author + * @version + * @date + * @brief SPI通信程序，用于与AFE芯片(SH3673520)通信 + ****************************************************************************** + * @attention + * + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" +#include "global.h" + +//SH3673517 SPI通信 +//PB12 = SPI1_CS (GPIO推挽输出，软件控制片选) +//PB13 = SPI1_SCK (AF1) - 时钟 +//PB14 = SPI1_MISO(AF1) - 主机输入从机输出 +//PB15 = SPI1_MOSI(AF0) - 主机输出从机输入 +#define PIN_SPI_NSS GPIO_Pin_12 +#define PIN_SPI_SCK GPIO_Pin_13 +#define PIN_SPI_MISO GPIO_Pin_14 +#define PIN_SPI_MOSI GPIO_Pin_15 + +#define SPI_Enable() GPIO_ResetBits(GPIOB, PIN_SPI_NSS) //使能通信 +#define SPI_Disable() GPIO_SetBits(GPIOB, PIN_SPI_NSS) //关闭通信 + + +/* + SPI_MOSI PB15 主设备输出，从设备输入 + SPI_MISO PB14 主设备输入，从设备输出 + SPI_SCK PB13 时钟 + SPI_CS PB12 片选信号 +*/ +void uf_SPI2_Init(void) +{ + /*定义SPI参数*/ + GPIO_InitTypeDef GPIO_InitStructure; + SPI_InitTypeDef SPI_InitStructure; + + // 使能SPI2和GPIOB时钟 + RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB | RCC_APB2Periph_AFIO, ENABLE); + + // PB13 (SCK), PB15 (MOSI) + GPIO_InitStructure.GPIO_Pin = PIN_SPI_SCK | PIN_SPI_MOSI; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; //复用推挽输出 + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOB, &GPIO_InitStructure); + // PB14 (MISO) + GPIO_InitStructure.GPIO_Pin = PIN_SPI_MISO; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; //浮空输入 + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOB, &GPIO_InitStructure); + // PB12 (CS) + GPIO_InitStructure.GPIO_Pin = PIN_SPI_NSS; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; //推挽输出 + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOB, &GPIO_InitStructure); + + GPIO_SetBits(GPIOB, PIN_SPI_NSS); //初始化拉高CS，关闭SPI通信 + + + /*配置SPI模式*/ + SPI_I2S_DeInit(SPI2); + + // 配置SPI2与AFE芯片的SPI3通信方式：4线通信，全双工，主模式，数据同边传输，MSB在前 + SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; //全双工模式 + SPI_InitStructure.SPI_Mode = SPI_Mode_Master; //主模式 + SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; //数据帧大小为 8 位 + // 配置SPI3极性参数CPOL和CPHA + SPI_InitStructure.SPI_CPOL = SPI_CPOL_High; //时钟极性为1，空闲时SCK电平状态为高电平 + SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge; //时钟相位为1，在第二个跳变沿开始采样数据(第一个跳变沿，失效) + SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; //软件控制 NSS 信号(PB12) + SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_64;//波特率预分频系数为 64 //36MHz/64 = 0.5625MHz < 1MHz + SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; //高位在前 + SPI_InitStructure.SPI_CRCPolynomial = 7; //CRC值的生成多项式=x^8+x^2+x+1，省略高位，可为任意值1，只用到低8位，生成二进制编码为0000111=7 + SPI_Init(SPI2, &SPI_InitStructure); + + // 使能SPI2 + SPI_Cmd(SPI2, ENABLE); +} + +//通信失败时，复位SPI +void SPI2_Error(void) +{ + //写也无法确有效，因为需要时序 + //这里重新初始化SPI + uf_SPI2_Init(); +} + +//AFE只支持单字节写操作 +//可写地址 40H~59H +//rtnval 0-true; other-false +uint8_t AFE_WriteOneByte(uint8_t addr, uint8_t *data) +{ + uint8_t tx_buffer[5], rx_buffer[5]; + uint8_t i; + uint8_t response; + + // 构造发送数据帧: [0x01][reg_addr][write_data][CRC][0x00] + tx_buffer[0] = 0x01; // 写命令 + tx_buffer[1] = addr; // 寄存器地址 + tx_buffer[2] = *data; // 写入数据 + tx_buffer[3] = CRC8_Cal(tx_buffer, 3); // CRC8 + tx_buffer[4] = 0x00; // 无效数据接收 + + // 拉低CS片选 + SPI_Enable(); + + for (i = 0; i < 5; i++) + { + while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_TXE) == RESET); + SPI_I2S_SendData(SPI2, tx_buffer[i]); + while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_RXNE) == RESET); + rx_buffer[i] = SPI_I2S_ReceiveData(SPI2); + } + + // 获取返回值 + response = rx_buffer[4]; + + SPI_Disable(); + delay_us(5); + + return (response == 0xA5) ? 0 : 1; +} + +//AFE可1次读取多个字节操作 +//可读取地址 40H~99H +//rtnval 0-success, other-fail +uint8_t AFE_ReadMulByte(uint8_t addr, uint8_t lenth, uint8_t *data) +{ + uint8_t tx_buffer[4]; // 发送缓冲区 + uint8_t rx_buffer[40]; // 接收缓冲区，最大可读取24字节，留有余量 + uint8_t crc_calculated, crc_received; + uint8_t i; + + // 构造发送数据帧: [0x02][reg_addr][data_length][0x00] + tx_buffer[0] = 0x02; // 读命令 + tx_buffer[1] = addr; // 寄存器地址 + tx_buffer[2] = lenth; // 数据长度 + tx_buffer[3] = 0x00; + + // 拉低CS片选 + SPI_Enable(); + + // 第一阶段：发送时钟和命令，发送(命令/地址/长度/0x00) 接收(0xFF/命令/地址/长度) + for( i=0; i<4; i++) + { + while(!SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_TXE)); // 等待发送缓冲区空 + SPI_I2S_SendData(SPI2, tx_buffer[i]); + while(!SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_RXNE)); // 等待接收完成 + rx_buffer[i] = SPI_I2S_ReceiveData(SPI2); + } + + // 第二阶段：接收有效数据(0x00)发送接收数据(需要提供接收时钟) + for( i=0; i>第五章(87页~92页). +#define BITBAND(addr, bitnum) ((addr & 0xF0000000)+0x2000000+((addr &0xFFFFF)<<5)+(bitnum<<2)) +#define MEM_ADDR(addr) *((volatile unsigned long *)(addr)) +#define BIT_ADDR(addr, bitnum) MEM_ADDR(BITBAND(addr, bitnum)) + +//IO口地址映射 +#define GPIOA_ODR_Addr (GPIOA_BASE+12) //0x4001080C +#define GPIOB_ODR_Addr (GPIOB_BASE+12) //0x40010C0C +#define GPIOC_ODR_Addr (GPIOC_BASE+12) //0x4001100C +#define GPIOD_ODR_Addr (GPIOD_BASE+12) //0x4001140C +#define GPIOE_ODR_Addr (GPIOE_BASE+12) //0x4001180C +#define GPIOF_ODR_Addr (GPIOF_BASE+12) //0x40011A0C +#define GPIOG_ODR_Addr (GPIOG_BASE+12) //0x40011E0C + +#define GPIOA_IDR_Addr (GPIOA_BASE+8) //0x40010808 +#define GPIOB_IDR_Addr (GPIOB_BASE+8) //0x40010C08 +#define GPIOC_IDR_Addr (GPIOC_BASE+8) //0x40011008 +#define GPIOD_IDR_Addr (GPIOD_BASE+8) //0x40011408 +#define GPIOE_IDR_Addr (GPIOE_BASE+8) //0x40011808 +#define GPIOF_IDR_Addr (GPIOF_BASE+8) //0x40011A08 +#define GPIOG_IDR_Addr (GPIOG_BASE+8) //0x40011E08 + +//确保n的值小于16! +//IO口操作,只对单一的IO口! +#define PAout(n) BIT_ADDR(GPIOA_ODR_Addr,n) //输出 +#define PAin(n) BIT_ADDR(GPIOA_IDR_Addr,n) //输入 + +#define PBout(n) BIT_ADDR(GPIOB_ODR_Addr,n) //输出 +#define PBin(n) BIT_ADDR(GPIOB_IDR_Addr,n) //输入 + +#define PCout(n) BIT_ADDR(GPIOC_ODR_Addr,n) //输出 +#define PCin(n) BIT_ADDR(GPIOC_IDR_Addr,n) //输入 + +#define PDout(n) BIT_ADDR(GPIOD_ODR_Addr,n) //输出 +#define PDin(n) BIT_ADDR(GPIOD_IDR_Addr,n) //输入 + +#define PEout(n) BIT_ADDR(GPIOE_ODR_Addr,n) //输出 +#define PEin(n) BIT_ADDR(GPIOE_IDR_Addr,n) //输入 + +#define PFout(n) BIT_ADDR(GPIOF_ODR_Addr,n) //输出 +#define PFin(n) BIT_ADDR(GPIOF_IDR_Addr,n) //输入 + +#define PGout(n) BIT_ADDR(GPIOG_ODR_Addr,n) //输出 +#define PGin(n) BIT_ADDR(GPIOG_IDR_Addr,n) //输入 + +#endif diff --git a/BSP/systick.c b/BSP/systick.c new file mode 100644 index 0000000..c721ba0 --- /dev/null +++ b/BSP/systick.c @@ -0,0 +1,78 @@ +/** + ****************************************************************************** + * @file tim.c + * @author Jerry + * @version V2.1 + * @date 19-April-2022 + * @brief tim program body. + ****************************************************************************** + * @attention + * + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" +#include "global.h" + +//相对精确的ms延时，不使用中断 +//优化：防止和其他中断冲突，导致卡死 +void delay_ms(uint16_t ms) +{ + uint16_t i; + volatile uint32_t tempreg; + + uint32_t timeout; //等待时间 + + for(i=0; iCTRL |= SysTick_CTRL_CLKSOURCE_Msk; + SysTick->LOAD = 72000 - 1; + SysTick->VAL = 0; + SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; + timeout = 72000; + do + { + tempreg = SysTick->CTRL; + + timeout--; + if(timeout == 0) + { + break; //超时退出 + } + } + while( (tempreg & SysTick_CTRL_COUNTFLAG_Msk) ==0); + + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + SysTick->VAL = 0; + } +} + +//相对精确的us延时，不使用中断 +//(没调用过) +void delay_us(uint16_t us) +{ + uint16_t i; + volatile uint32_t tempreg; + + for(i=0; iCTRL |= SysTick_CTRL_CLKSOURCE_Msk; + SysTick->LOAD = 72; + SysTick->VAL = 0; + SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; + do + { + tempreg = SysTick->CTRL; + } + while( (tempreg & SysTick_CTRL_COUNTFLAG_Msk) ==0); + + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + SysTick->VAL = 0; + } +} + + + + diff --git a/BSP/tim.c b/BSP/tim.c new file mode 100644 index 0000000..5a53696 --- /dev/null +++ b/BSP/tim.c @@ -0,0 +1,231 @@ +/** + ****************************************************************************** + * @file tim.c + * @author Jerry + * @version V2.1 + * @date 19-April-2022 + * @brief tim program body. + ****************************************************************************** + * @attention + * + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" +#include "global.h" + +uint32_t tmrSys = 0; +uint32_t tmrTemp[20]; + +//10MS +void uf_TIM3_Init(void) +{ + TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; + NVIC_InitTypeDef NVIC_InitStructure; + + RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE); + + TIM_TimeBaseStructure.TIM_Period = 10000-1; + TIM_TimeBaseStructure.TIM_Prescaler = 72-1; + TIM_TimeBaseStructure.TIM_ClockDivision = 0; + TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseInit(TIM3, &TIM_TimeBaseStructure); + + NVIC_InitStructure.NVIC_IRQChannel = TIM3_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; //主定时器 优先级：0,0 + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + TIM_ITConfig(TIM3, TIM_IT_Update,ENABLE ); + TIM_Cmd(TIM3, ENABLE); //使能TIMx外设 +} + +//10ms中断 +void TIM3_IRQHandler(void) //TIM3中断 +{ + if (TIM_GetITStatus(TIM3, TIM_IT_Update) != RESET) //检查指定的TIM中断发生与否:TIM 中断源 + { + TIM_ClearITPendingBit(TIM3, TIM_IT_Update); //清除TIMx的中断待处理位:TIM 中断源 + tmrSys++; + + KEY_TIM_Moni(); + + Cali_SOC_Moni(); + + Screen_TIM_Moni(); //[陶晶驰] + CAN_TIM_Moni(); + MODBUS_TIM_Moni(); + MODBUS1_TIM_Moni(); + +// DI_TIM_Moni(); +// DI_Ctrl(); + + OCC2_TIM_Moni(); + OCC2_Ctrl(); + + #if Addr_SetAuto + //休眠时，地址变动暂停 + if(sleep_flag == 0) + { + if(paraMem.addr_FREE_Flg == 0) ADDR_Rank_Moni(); + if(paraMem.addr_FREE_Flg == 0) ADDR_Assign_Moni(); + } + #endif + + //只有RTC时钟有问题时，才会启用下列函数 + if(LSEErrFlag==1) + { + SLEEP_TIM_Moni(); //休眠的倒计时 + SLEEP2_TIM_Moni(); //休眠2的倒计时 + UVOff_TIM_Moni(); //欠压强制复位的倒计时 + FCCCali_TIM_Moni(); //容量校准要在12h内的倒计时 + } + + + if(Screen_RevFlg == 1) //屏幕收到完整一帧去处理 + { + Screen_RevCount++; + if(Screen_RevCount > 1) + { + Screen_RevFlg = 0; + Screen_RevCount = 0; + + //Screen_IT_Update(); + Screen_RevHandlerFlg = 1; + } + } + + if(MODBUS_RevFlg == 1) //MODBUS收到完整一帧去处理 + { + MODBUS_RevCount++; + if(MODBUS_RevCount > 1) + { + MODBUS_RevFlg = 0; + MODBUS_RevCount = 0; + + MODBUS_IT_TIMUpdate(); + } + } + + if(MODBUS1_RevFlg == 1) //MODBUS1收到完整一帧去处理 + { + MODBUS1_RevCount++; + if(MODBUS1_RevCount > 1) + { + MODBUS1_RevFlg = 0; + MODBUS1_RevCount = 0; + + MODBUS1_IT_TIMUpdate(); + } + } + + + /*三选一模块*/ + #if BLE_Conn + BLE_TIM_Moni(); //BLE无通信定时初始化 + + if(BLE_RevFlg == 1) //BLE收到完整一帧去处理 + { + BLE_RevCount++; + if(BLE_RevCount > 3) + { + BLE_RevFlg = 0; + BLE_RevCount = 0; + + BLE_IT_Update(); + } + } + #endif + #if WIFI_Conn + WIFI_TIM_Moni(); //WIFI无通信定时初始化 + + if(WIFI_RevFlg == 1) //WIFI收到完整一帧去处理 + { + WIFI_RevCount++; + if(WIFI_RevCount > 3) + { + WIFI_RevFlg = 0; + WIFI_RevCount = 0; + + WIFI_IT_Update(); + } + } + #endif + #if LTE_Conn + LTE_TIM_Moni(); //LTE无通信定时初始化 + + if(LTE_RevFlg == 1) //LTE收到完整一帧去处理 + { + LTE_RevCount++; + if(LTE_RevCount > 3) + { + LTE_RevFlg = 0; + LTE_RevCount = 0; + + //有回复，清零等待倒计时 + LTE_WaitRxFlg = 0; + LTE_WaitRxDelay = 0; + + if(LTE_OTA_Flag == 0) + { + LTE_4G_IT_Update(); + } + else + { + LTE_OTA_IT_Update(); + } + } + } + #endif + } +} + +/************************************************************************** +** 函数名: TIMER_Update +** 输 入: nothing +** 输 出: tmrSys value +** 备 注：tmrSys do ++ in the SysTick_Handler function +***************************************************************************/ +uint32_t TIMER_Update(void) +{ + return tmrSys; +} + +/************************************************************************** +** 函数名: +** 输 入: +** 输 出: +** 备 注： +***************************************************************************/ +uint32_t TIMER_IsOut(uint32_t cnt, uint32_t tmr) +{ + uint32_t tmp = tmrSys; + + tmp = cnt > tmp ? ( (uint32_t)(-1) - cnt + tmp ) : ( tmp-cnt ); + + if(tmp>=tmr) + return 1; + else + return 0; +} + +/************************************************************************** +** 函数名: +** 输 入: +** 输 出: +** 备 注： +***************************************************************************/ +uint32_t TIMER_IsOther(uint32_t cnt, uint32_t tmr) +{ + uint32_t tmp = tmrSys; + uint32_t tmp1; + + tmp = cnt > tmp ? ( (uint32_t)(-1) - cnt + tmp ) : ( tmp-cnt ); + tmp1 = tmp>=tmr ? (tmp - tmr): (tmr-tmp); + + return tmp1; +} + diff --git a/BSP/uart.c b/BSP/uart.c new file mode 100644 index 0000000..183794d --- /dev/null +++ b/BSP/uart.c @@ -0,0 +1,316 @@ +/** + ****************************************************************************** + * @file tim.c + * @author Jerry + * @version V2.1 + * @date 19-April-2022 + * @brief tim program body. + ****************************************************************************** + * @attention + * + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" +#include "global.h" + + +uint8_t Screen_RevFlg; +uint8_t Screen_RevCount; +uint8_t Screen_RevHandlerFlg; //在主函数执行分析处理 + +uint8_t MODBUS_RevFlg; +uint8_t MODBUS_RevCount; + +uint8_t MODBUS1_RevFlg; +uint8_t MODBUS1_RevCount; + +/*三选一模块*/ +#if BLE_Conn +uint8_t BLE_RevFlg; +uint8_t BLE_RevCount; +#endif +#if WIFI_Conn +uint8_t WIFI_RevFlg; +uint8_t WIFI_RevCount; +#endif +#if LTE_Conn +uint8_t LTE_RevFlg; +uint8_t LTE_RevCount; +#endif + + +/**RS485 网口3.4**/ +//usart1 init +void uf_UART1_Init( u32 bound ) +{ + GPIO_InitTypeDef GPIO_InitStructure; + NVIC_InitTypeDef NVIC_InitStructure; + USART_InitTypeDef USART_InitStructure; + + /* Enable the USART1 Pins Software Remapping */ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA , ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE); + + USART_InitStructure.USART_BaudRate = bound; + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_Init(USART1, &USART_InitStructure); + + /* Configure USART1 Rx (PA.10) as input floating */ + /* Configure USART1 Tx (PA.09) as alternate function push-pull */ + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + /* Enable the USART1 Interrupt */ + NVIC_InitStructure.NVIC_IRQChannel = USART1_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 3; //485通信主从机 优先级：3,0 + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + if(bmsMem.E2_485Addr == 1) + { + USART_ITConfig(USART1, USART_IT_RXNE, DISABLE); //设备做主机时关闭接收中断 + } + else + { + USART_ITConfig(USART1, USART_IT_RXNE, ENABLE); //设备做从机时打开接收中断 + } + //USART_ITConfig(USART1, USART_IT_IDLE, ENABLE); + USART_Cmd(USART1, ENABLE); +} + + +//send multiple bytes +void USART1_SendMulByte(uint8_t *p, uint8_t size) +{ + uint8_t i; + + for(i=0;i + +/* define compiler specific symbols */ +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + + +/* ################### Compiler specific Intrinsics ########################### */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +__ASM uint32_t __get_PSP(void) +{ + mrs r0, psp + bx lr +} + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +__ASM void __set_PSP(uint32_t topOfProcStack) +{ + msr psp, r0 + bx lr +} + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +__ASM uint32_t __get_MSP(void) +{ + mrs r0, msp + bx lr +} + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +__ASM void __set_MSP(uint32_t mainStackPointer) +{ + msr msp, r0 + bx lr +} + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +__ASM uint32_t __REV16(uint16_t value) +{ + rev16 r0, r0 + bx lr +} + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +__ASM int32_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} + + +#if (__ARMCC_VERSION < 400000) + +/** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +__ASM void __CLREX(void) +{ + clrex +} + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +__ASM uint32_t __get_BASEPRI(void) +{ + mrs r0, basepri + bx lr +} + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +__ASM void __set_BASEPRI(uint32_t basePri) +{ + msr basepri, r0 + bx lr +} + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +__ASM uint32_t __get_PRIMASK(void) +{ + mrs r0, primask + bx lr +} + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +__ASM void __set_PRIMASK(uint32_t priMask) +{ + msr primask, r0 + bx lr +} + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +__ASM uint32_t __get_FAULTMASK(void) +{ + mrs r0, faultmask + bx lr +} + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +__ASM void __set_FAULTMASK(uint32_t faultMask) +{ + msr faultmask, r0 + bx lr +} + +/** + * @brief Return the Control Register value + * + * @return Control value + * + * Return the content of the control register + */ +__ASM uint32_t __get_CONTROL(void) +{ + mrs r0, control + bx lr +} + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +__ASM void __set_CONTROL(uint32_t control) +{ + msr control, r0 + bx lr +} + +#endif /* __ARMCC_VERSION */ + + + +#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#pragma diag_suppress=Pe940 + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +uint32_t __get_PSP(void) +{ + __ASM("mrs r0, psp"); + __ASM("bx lr"); +} + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +void __set_PSP(uint32_t topOfProcStack) +{ + __ASM("msr psp, r0"); + __ASM("bx lr"); +} + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +uint32_t __get_MSP(void) +{ + __ASM("mrs r0, msp"); + __ASM("bx lr"); +} + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +void __set_MSP(uint32_t topOfMainStack) +{ + __ASM("msr msp, r0"); + __ASM("bx lr"); +} + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +uint32_t __REV16(uint16_t value) +{ + __ASM("rev16 r0, r0"); + __ASM("bx lr"); +} + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +uint32_t __RBIT(uint32_t value) +{ + __ASM("rbit r0, r0"); + __ASM("bx lr"); +} + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit values) + */ +uint8_t __LDREXB(uint8_t *addr) +{ + __ASM("ldrexb r0, [r0]"); + __ASM("bx lr"); +} + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +uint16_t __LDREXH(uint16_t *addr) +{ + __ASM("ldrexh r0, [r0]"); + __ASM("bx lr"); +} + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +uint32_t __LDREXW(uint32_t *addr) +{ + __ASM("ldrex r0, [r0]"); + __ASM("bx lr"); +} + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +uint32_t __STREXB(uint8_t value, uint8_t *addr) +{ + __ASM("strexb r0, r0, [r1]"); + __ASM("bx lr"); +} + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +uint32_t __STREXH(uint16_t value, uint16_t *addr) +{ + __ASM("strexh r0, r0, [r1]"); + __ASM("bx lr"); +} + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +uint32_t __STREXW(uint32_t value, uint32_t *addr) +{ + __ASM("strex r0, r0, [r1]"); + __ASM("bx lr"); +} + +#pragma diag_default=Pe940 + + +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +uint32_t __get_PSP(void) __attribute__( ( naked ) ); +uint32_t __get_PSP(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, psp\n\t" + "MOV r0, %0 \n\t" + "BX lr \n\t" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) ); +void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n\t" + "BX lr \n\t" : : "r" (topOfProcStack) ); +} + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +uint32_t __get_MSP(void) __attribute__( ( naked ) ); +uint32_t __get_MSP(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, msp\n\t" + "MOV r0, %0 \n\t" + "BX lr \n\t" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) ); +void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n\t" + "BX lr \n\t" : : "r" (topOfMainStack) ); +} + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +uint32_t __get_BASEPRI(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) ); +} + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +uint32_t __get_PRIMASK(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); +} + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +uint32_t __get_FAULTMASK(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); +} + +/** + * @brief Return the Control Register value +* +* @return Control value + * + * Return the content of the control register + */ +uint32_t __get_CONTROL(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) ); +} + + +/** + * @brief Reverse byte order in integer value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in integer value + */ +uint32_t __REV(uint32_t value) +{ + uint32_t result=0; + + __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +uint32_t __REV16(uint16_t value) +{ + uint32_t result=0; + + __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +int32_t __REVSH(int16_t value) +{ + uint32_t result=0; + + __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +uint32_t __RBIT(uint32_t value) +{ + uint32_t result=0; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit value + */ +uint8_t __LDREXB(uint8_t *addr) +{ + uint8_t result=0; + + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +uint16_t __LDREXH(uint16_t *addr) +{ + uint16_t result=0; + + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +uint32_t __LDREXW(uint32_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +uint32_t __STREXB(uint8_t value, uint8_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +uint32_t __STREXH(uint16_t value, uint16_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +uint32_t __STREXW(uint32_t value, uint32_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif diff --git a/CORE/core_cm3.h b/CORE/core_cm3.h new file mode 100644 index 0000000..7ab7b4b --- /dev/null +++ b/CORE/core_cm3.h @@ -0,0 +1,1818 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V1.30 + * @date 30. October 2009 + * + * @note + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CM3_CORE_H__ +#define __CM3_CORE_H__ + +/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration + * + * List of Lint messages which will be suppressed and not shown: + * - Error 10: \n + * register uint32_t __regBasePri __asm("basepri"); \n + * Error 10: Expecting ';' + * . + * - Error 530: \n + * return(__regBasePri); \n + * Warning 530: Symbol '__regBasePri' (line 264) not initialized + * . + * - Error 550: \n + * __regBasePri = (basePri & 0x1ff); \n + * Warning 550: Symbol '__regBasePri' (line 271) not accessed + * . + * - Error 754: \n + * uint32_t RESERVED0[24]; \n + * Info 754: local structure member '' (line 109, file ./cm3_core.h) not referenced + * . + * - Error 750: \n + * #define __CM3_CORE_H__ \n + * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced + * . + * - Error 528: \n + * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n + * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced + * . + * - Error 751: \n + * } InterruptType_Type; \n + * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced + * . + * Note: To re-enable a Message, insert a space before 'lint' * + * + */ + +/*lint -save */ +/*lint -e10 */ +/*lint -e530 */ +/*lint -e550 */ +/*lint -e754 */ +/*lint -e750 */ +/*lint -e528 */ +/*lint -e751 */ + + +/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions + This file defines all structures and symbols for CMSIS core: + - CMSIS version number + - Cortex-M core registers and bitfields + - Cortex-M core peripheral base address + @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex core */ + +#include /* Include standard types */ + +#if defined (__ICCARM__) + #include /* IAR Intrinsics */ +#endif + + +#ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */ +#endif + + + + +/** + * IO definitions + * + * define access restrictions to peripheral registers + */ + +#ifdef __cplusplus + #define __I volatile /*!< defines 'read only' permissions */ +#else + #define __I volatile const /*!< defines 'read only' permissions */ +#endif +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ + + + +/******************************************************************************* + * Register Abstraction + ******************************************************************************/ +/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register + @{ +*/ + + +/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC + memory mapped structure for Nested Vectored Interrupt Controller (NVIC) + @{ + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */ +} NVIC_Type; +/*@}*/ /* end of group CMSIS_CM3_NVIC */ + + +/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB + memory mapped structure for System Control Block (SCB) + @{ + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ +/*@}*/ /* end of group CMSIS_CM3_SCB */ + + +/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick + memory mapped structure for SysTick + @{ + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ +/*@}*/ /* end of group CMSIS_CM3_SysTick */ + + +/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM + memory mapped structure for Instrumentation Trace Macrocell (ITM) + @{ + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */ + __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */ + __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ +/*@}*/ /* end of group CMSIS_CM3_ITM */ + + +/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type + memory mapped structure for Interrupt Type + @{ + */ +typedef struct +{ + uint32_t RESERVED0; + __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) + __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */ +#else + uint32_t RESERVED1; +#endif +} InterruptType_Type; + +/* Interrupt Controller Type Register Definitions */ +#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */ +#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */ +#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */ + +#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */ +#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */ + +#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */ +#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */ +/*@}*/ /* end of group CMSIS_CM3_InterruptType */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) +/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU + memory mapped structure for Memory Protection Unit (MPU) + @{ + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */ +#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */ +#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */ +#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */ +#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */ +#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */ +#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@}*/ /* end of group CMSIS_CM3_MPU */ +#endif + + +/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug + memory mapped structure for Core Debug Register + @{ + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ +/*@}*/ /* end of group CMSIS_CM3_CoreDebug */ + + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000) /*!< ITM Base Address */ +#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */ + +#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ +#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ +#endif + +/*@}*/ /* end of group CMSIS_CM3_core_register */ + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + + +/* ################### Compiler specific Intrinsics ########################### */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#define __enable_fault_irq __enable_fiq +#define __disable_fault_irq __disable_fiq + +#define __NOP __nop +#define __WFI __wfi +#define __WFE __wfe +#define __SEV __sev +#define __ISB() __isb(0) +#define __DSB() __dsb(0) +#define __DMB() __dmb(0) +#define __REV __rev +#define __RBIT __rbit +#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr)) +#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr)) +#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr)) +#define __STREXB(value, ptr) __strex(value, ptr) +#define __STREXH(value, ptr) __strex(value, ptr) +#define __STREXW(value, ptr) __strex(value, ptr) + + +/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */ +/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */ +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +extern uint32_t __get_PSP(void); + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +extern void __set_PSP(uint32_t topOfProcStack); + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +extern uint32_t __get_MSP(void); + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +extern void __set_MSP(uint32_t topOfMainStack); + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +extern uint32_t __REV16(uint16_t value); + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +extern int32_t __REVSH(int16_t value); + + +#if (__ARMCC_VERSION < 400000) + +/** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +extern void __CLREX(void); + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +extern uint32_t __get_BASEPRI(void); + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +extern void __set_BASEPRI(uint32_t basePri); + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +extern uint32_t __get_PRIMASK(void); + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +extern void __set_PRIMASK(uint32_t priMask); + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +extern uint32_t __get_FAULTMASK(void); + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +extern void __set_FAULTMASK(uint32_t faultMask); + +/** + * @brief Return the Control Register value + * + * @return Control value + * + * Return the content of the control register + */ +extern uint32_t __get_CONTROL(void); + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +extern void __set_CONTROL(uint32_t control); + +#else /* (__ARMCC_VERSION >= 400000) */ + +/** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +#define __CLREX __clrex + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +static __INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +static __INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +static __INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +static __INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +static __INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +static __INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & 1); +} + +/** + * @brief Return the Control Register value + * + * @return Control value + * + * Return the content of the control register + */ +static __INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +static __INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + +#endif /* __ARMCC_VERSION */ + + + +#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#define __enable_irq __enable_interrupt /*!< global Interrupt enable */ +#define __disable_irq __disable_interrupt /*!< global Interrupt disable */ + +static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); } +static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); } + +#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */ +static __INLINE void __WFI() { __ASM ("wfi"); } +static __INLINE void __WFE() { __ASM ("wfe"); } +static __INLINE void __SEV() { __ASM ("sev"); } +static __INLINE void __CLREX() { __ASM ("clrex"); } + +/* intrinsic void __ISB(void) */ +/* intrinsic void __DSB(void) */ +/* intrinsic void __DMB(void) */ +/* intrinsic void __set_PRIMASK(); */ +/* intrinsic void __get_PRIMASK(); */ +/* intrinsic void __set_FAULTMASK(); */ +/* intrinsic void __get_FAULTMASK(); */ +/* intrinsic uint32_t __REV(uint32_t value); */ +/* intrinsic uint32_t __REVSH(uint32_t value); */ +/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */ +/* intrinsic unsigned long __LDREX(unsigned long *); */ + + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +extern uint32_t __get_PSP(void); + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +extern void __set_PSP(uint32_t topOfProcStack); + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +extern uint32_t __get_MSP(void); + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +extern void __set_MSP(uint32_t topOfMainStack); + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +extern uint32_t __REV16(uint16_t value); + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +extern uint32_t __RBIT(uint32_t value); + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit values) + */ +extern uint8_t __LDREXB(uint8_t *addr); + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +extern uint16_t __LDREXH(uint16_t *addr); + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +extern uint32_t __LDREXW(uint32_t *addr); + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +extern uint32_t __STREXB(uint8_t value, uint8_t *addr); + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +extern uint32_t __STREXH(uint16_t value, uint16_t *addr); + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +extern uint32_t __STREXW(uint32_t value, uint32_t *addr); + + + +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); } +static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); } + +static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); } +static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); } + +static __INLINE void __NOP() { __ASM volatile ("nop"); } +static __INLINE void __WFI() { __ASM volatile ("wfi"); } +static __INLINE void __WFE() { __ASM volatile ("wfe"); } +static __INLINE void __SEV() { __ASM volatile ("sev"); } +static __INLINE void __ISB() { __ASM volatile ("isb"); } +static __INLINE void __DSB() { __ASM volatile ("dsb"); } +static __INLINE void __DMB() { __ASM volatile ("dmb"); } +static __INLINE void __CLREX() { __ASM volatile ("clrex"); } + + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +extern uint32_t __get_PSP(void); + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +extern void __set_PSP(uint32_t topOfProcStack); + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +extern uint32_t __get_MSP(void); + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +extern void __set_MSP(uint32_t topOfMainStack); + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +extern uint32_t __get_BASEPRI(void); + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +extern void __set_BASEPRI(uint32_t basePri); + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +extern uint32_t __get_PRIMASK(void); + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +extern void __set_PRIMASK(uint32_t priMask); + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +extern uint32_t __get_FAULTMASK(void); + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +extern void __set_FAULTMASK(uint32_t faultMask); + +/** + * @brief Return the Control Register value +* +* @return Control value + * + * Return the content of the control register + */ +extern uint32_t __get_CONTROL(void); + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +extern void __set_CONTROL(uint32_t control); + +/** + * @brief Reverse byte order in integer value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in integer value + */ +extern uint32_t __REV(uint32_t value); + +/** + * @brief Reverse byte order in unsigned short value + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +extern uint32_t __REV16(uint16_t value); + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +extern int32_t __REVSH(int16_t value); + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +extern uint32_t __RBIT(uint32_t value); + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit value + */ +extern uint8_t __LDREXB(uint8_t *addr); + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +extern uint16_t __LDREXH(uint16_t *addr); + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +extern uint32_t __LDREXW(uint32_t *addr); + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +extern uint32_t __STREXB(uint8_t value, uint8_t *addr); + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +extern uint32_t __STREXH(uint16_t value, uint16_t *addr); + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +extern uint32_t __STREXW(uint32_t value, uint32_t *addr); + + +#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + + +/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface + Core Function Interface containing: + - Core NVIC Functions + - Core SysTick Functions + - Core Reset Functions +*/ +/*@{*/ + +/* ########################## NVIC functions #################################### */ + +/** + * @brief Set the Priority Grouping in NVIC Interrupt Controller + * + * @param PriorityGroup is priority grouping field + * + * Set the priority grouping field using the required unlock sequence. + * The parameter priority_grouping is assigned to the field + * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + */ +static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + (0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + +/** + * @brief Get the Priority Grouping from NVIC Interrupt Controller + * + * @return priority grouping field + * + * Get the priority grouping from NVIC Interrupt Controller. + * priority grouping is SCB->AIRCR [10:8] PRIGROUP field. + */ +static __INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + +/** + * @brief Enable Interrupt in NVIC Interrupt Controller + * + * @param IRQn The positive number of the external interrupt to enable + * + * Enable a device specific interupt in the NVIC interrupt controller. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + +/** + * @brief Disable the interrupt line for external interrupt specified + * + * @param IRQn The positive number of the external interrupt to disable + * + * Disable a device specific interupt in the NVIC interrupt controller. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + +/** + * @brief Read the interrupt pending bit for a device specific interrupt source + * + * @param IRQn The number of the device specifc interrupt + * @return 1 = interrupt pending, 0 = interrupt not pending + * + * Read the pending register in NVIC and return 1 if its status is pending, + * otherwise it returns 0 + */ +static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + +/** + * @brief Set the pending bit for an external interrupt + * + * @param IRQn The number of the interrupt for set pending + * + * Set the pending bit for the specified interrupt. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + +/** + * @brief Clear the pending bit for an external interrupt + * + * @param IRQn The number of the interrupt for clear pending + * + * Clear the pending bit for the specified interrupt. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + +/** + * @brief Read the active bit for an external interrupt + * + * @param IRQn The number of the interrupt for read active bit + * @return 1 = interrupt active, 0 = interrupt not active + * + * Read the active register in NVIC and returns 1 if its status is active, + * otherwise it returns 0. + */ +static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + +/** + * @brief Set the priority for an interrupt + * + * @param IRQn The number of the interrupt for set priority + * @param priority The priority to set + * + * Set the priority for the specified interrupt. The interrupt + * number can be positive to specify an external (device specific) + * interrupt, or negative to specify an internal (core) interrupt. + * + * Note: The priority cannot be set for every core interrupt. + */ +static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + +/** + * @brief Read the priority for an interrupt + * + * @param IRQn The number of the interrupt for get priority + * @return The priority for the interrupt + * + * Read the priority for the specified interrupt. The interrupt + * number can be positive to specify an external (device specific) + * interrupt, or negative to specify an internal (core) interrupt. + * + * The returned priority value is automatically aligned to the implemented + * priority bits of the microcontroller. + * + * Note: The priority cannot be set for every core interrupt. + */ +static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** + * @brief Encode the priority for an interrupt + * + * @param PriorityGroup The used priority group + * @param PreemptPriority The preemptive priority value (starting from 0) + * @param SubPriority The sub priority value (starting from 0) + * @return The encoded priority for the interrupt + * + * Encode the priority for an interrupt with the given priority group, + * preemptive priority value and sub priority value. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + * + * The returned priority value can be used for NVIC_SetPriority(...) function + */ +static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** + * @brief Decode the priority of an interrupt + * + * @param Priority The priority for the interrupt + * @param PriorityGroup The used priority group + * @param pPreemptPriority The preemptive priority value (starting from 0) + * @param pSubPriority The sub priority value (starting from 0) + * + * Decode an interrupt priority value with the given priority group to + * preemptive priority value and sub priority value. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + * + * The priority value can be retrieved with NVIC_GetPriority(...) function + */ +static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + + +/* ################################## SysTick function ############################################ */ + +#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0) + +/** + * @brief Initialize and start the SysTick counter and its interrupt. + * + * @param ticks number of ticks between two interrupts + * @return 1 = failed, 0 = successful + * + * Initialise the system tick timer and its interrupt and start the + * system tick timer / counter in free running mode to generate + * periodical interrupts. + */ +static __INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + + + + +/* ################################## Reset function ############################################ */ + +/** + * @brief Initiate a system reset request. + * + * Initiate a system reset request to reset the MCU + */ +static __INLINE void NVIC_SystemReset(void) +{ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */ + + + +/* ##################################### Debug In/Output function ########################################### */ + +/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface + Core Debug Interface containing: + - Core Debug Receive / Transmit Functions + - Core Debug Defines + - Core Debug Variables +*/ +/*@{*/ + +extern volatile int ITM_RxBuffer; /*!< variable to receive characters */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ + + +/** + * @brief Outputs a character via the ITM channel 0 + * + * @param ch character to output + * @return character to output + * + * The function outputs a character via the ITM channel 0. + * The function returns when no debugger is connected that has booked the output. + * It is blocking when a debugger is connected, but the previous character send is not transmitted. + */ +static __INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ + (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** + * @brief Inputs a character via variable ITM_RxBuffer + * + * @return received character, -1 = no character received + * + * The function inputs a character via variable ITM_RxBuffer. + * The function returns when no debugger is connected that has booked the output. + * It is blocking when a debugger is connected, but the previous character send is not transmitted. + */ +static __INLINE int ITM_ReceiveChar (void) { + int ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + * @brief Check if a character via variable ITM_RxBuffer is available + * + * @return 1 = character available, 0 = no character available + * + * The function checks variable ITM_RxBuffer whether a character is available or not. + * The function returns '1' if a character is available and '0' if no character is available. + */ +static __INLINE int ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ /* end of group CMSIS_CM3_core_definitions */ + +#endif /* __CM3_CORE_H__ */ + +/*lint -restore */ diff --git a/CORE/startup_stm32f10x_cl.s b/CORE/startup_stm32f10x_cl.s new file mode 100644 index 0000000..e40f734 --- /dev/null +++ b/CORE/startup_stm32f10x_cl.s @@ -0,0 +1,369 @@ +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_cl.s +;* Author : MCD Application Team +;* Version : V3.5.1 +;* Date : 08-September-2021 +;* Description : STM32F10x Connectivity line devices vector table for MDK-ARM +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +;* +;* Copyright (c) 2011 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 and ADC2 + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C1 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC alarm through EXTI line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_IRQHandler +TIM7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_IRQHandler +DMA2_Channel5_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + diff --git a/CORE/startup_stm32f10x_hd.s b/CORE/startup_stm32f10x_hd.s new file mode 100644 index 0000000..1efbb07 --- /dev/null +++ b/CORE/startup_stm32f10x_hd.s @@ -0,0 +1,359 @@ +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_hd.s +;* Author : MCD Application Team +;* Version : V3.5.1 +;* Date : 08-September-2021 +;* Description : STM32F10x High Density Devices vector table for MDK-ARM +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system and also configure the external +;* SRAM mounted on STM3210E-EVAL board to be used as data +;* memory (optional, to be enabled by user) +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +;* +;* Copyright (c) 2011 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 & ADC2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend + DCD TIM8_BRK_IRQHandler ; TIM8 Break + DCD TIM8_UP_IRQHandler ; TIM8 Update + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD ADC3_IRQHandler ; ADC3 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 + DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5 +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] + EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + EXPORT TIM8_BRK_IRQHandler [WEAK] + EXPORT TIM8_UP_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT ADC3_IRQHandler [WEAK] + EXPORT FSMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_5_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USB_HP_CAN1_TX_IRQHandler +USB_LP_CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +USBWakeUp_IRQHandler +TIM8_BRK_IRQHandler +TIM8_UP_IRQHandler +TIM8_TRG_COM_IRQHandler +TIM8_CC_IRQHandler +ADC3_IRQHandler +FSMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_IRQHandler +TIM7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_5_IRQHandler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + diff --git a/CORE/startup_stm32f10x_hd_vl.s b/CORE/startup_stm32f10x_hd_vl.s new file mode 100644 index 0000000..93a3261 --- /dev/null +++ b/CORE/startup_stm32f10x_hd_vl.s @@ -0,0 +1,347 @@ +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_hd_vl.s +;* Author : MCD Application Team +;* Version : V3.5.1 +;* Date : 08-September-2021 +;* Description : STM32F10x High Density Value Line Devices vector table +;* for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system and also configure the external +;* SRAM mounted on STM32100E-EVAL board to be used as data +;* memory (optional, to be enabled by user) +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +;* +;* Copyright (c) 2011 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD CEC_IRQHandler ; HDMI-CEC + DCD TIM12_IRQHandler ; TIM12 + DCD TIM13_IRQHandler ; TIM13 + DCD TIM14_IRQHandler ; TIM14 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 + DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5 +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT TIM12_IRQHandler [WEAK] + EXPORT TIM13_IRQHandler [WEAK] + EXPORT TIM14_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_5_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM15_IRQHandler +TIM1_UP_TIM16_IRQHandler +TIM1_TRG_COM_TIM17_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +CEC_IRQHandler +TIM12_IRQHandler +TIM13_IRQHandler +TIM14_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_5_IRQHandler +DMA2_Channel5_IRQHandler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + diff --git a/CORE/startup_stm32f10x_ld.s b/CORE/startup_stm32f10x_ld.s new file mode 100644 index 0000000..2c5c976 --- /dev/null +++ b/CORE/startup_stm32f10x_ld.s @@ -0,0 +1,298 @@ +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_ld.s +;* Author : MCD Application Team +;* Version : V3.5.1 +;* Date : 08-September-2021 +;* Description : STM32F10x Low Density Devices vector table for MDK-ARM +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +;* +;* Copyright (c) 2011 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1_2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD 0 ; Reserved + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI1_IRQHandler ; SPI1 + DCD 0 ; Reserved + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] + EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USB_HP_CAN1_TX_IRQHandler +USB_LP_CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +SPI1_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +USBWakeUp_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + diff --git a/CORE/startup_stm32f10x_ld_vl.s b/CORE/startup_stm32f10x_ld_vl.s new file mode 100644 index 0000000..b38d7ea --- /dev/null +++ b/CORE/startup_stm32f10x_ld_vl.s @@ -0,0 +1,305 @@ +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_ld_vl.s +;* Author : MCD Application Team +;* Version : V3.5.1 +;* Date : 08-September-2021 +;* Description : STM32F10x Low Density Value Line Devices vector table +;* for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +;* +;* Copyright (c) 2011 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD 0 ; Reserved + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI1_IRQHandler ; SPI1 + DCD 0 ; Reserved + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD CEC_IRQHandler ; HDMI-CEC + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun + DCD TIM7_IRQHandler ; TIM7 +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM15_IRQHandler +TIM1_UP_TIM16_IRQHandler +TIM1_TRG_COM_TIM17_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +SPI1_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +CEC_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + diff --git a/CORE/startup_stm32f10x_md.s b/CORE/startup_stm32f10x_md.s new file mode 100644 index 0000000..1ab7096 --- /dev/null +++ b/CORE/startup_stm32f10x_md.s @@ -0,0 +1,308 @@ +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_md.s +;* Author : MCD Application Team +;* Version : V3.5.1 +;* Date : 08-September-2021 +;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +;* +;* Copyright (c) 2011 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1_2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] + EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USB_HP_CAN1_TX_IRQHandler +USB_LP_CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +USBWakeUp_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + diff --git a/CORE/startup_stm32f10x_md_vl.s b/CORE/startup_stm32f10x_md_vl.s new file mode 100644 index 0000000..8d7828a --- /dev/null +++ b/CORE/startup_stm32f10x_md_vl.s @@ -0,0 +1,316 @@ +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_md_vl.s +;* Author : MCD Application Team +;* Version : V3.5.1 +;* Date : 08-September-2021 +;* Description : STM32F10x Medium Density Value Line Devices vector table +;* for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +;* +;* Copyright (c) 2011 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD CEC_IRQHandler ; HDMI-CEC + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun + DCD TIM7_IRQHandler ; TIM7 +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM15_IRQHandler +TIM1_UP_TIM16_IRQHandler +TIM1_TRG_COM_TIM17_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +CEC_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + diff --git a/CORE/startup_stm32f10x_xl.s b/CORE/startup_stm32f10x_xl.s new file mode 100644 index 0000000..39f389b --- /dev/null +++ b/CORE/startup_stm32f10x_xl.s @@ -0,0 +1,359 @@ +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_xl.s +;* Author : MCD Application Team +;* Version : V3.5.1 +;* Date : 08-September-2021 +;* Description : STM32F10x XL-Density Devices vector table for MDK-ARM +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system and also configure the external +;* SRAM mounted on STM3210E-EVAL board to be used as data +;* memory (optional, to be enabled by user) +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +;* +;* Copyright (c) 2011 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 & ADC2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD ADC3_IRQHandler ; ADC3 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 + DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5 +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] + EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT ADC3_IRQHandler [WEAK] + EXPORT FSMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_5_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USB_HP_CAN1_TX_IRQHandler +USB_LP_CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +USBWakeUp_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +ADC3_IRQHandler +FSMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_IRQHandler +TIM7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_5_IRQHandler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + diff --git a/MOUDLE/AFE_SH3673520.c b/MOUDLE/AFE_SH3673520.c new file mode 100644 index 0000000..843db12 --- /dev/null +++ b/MOUDLE/AFE_SH3673520.c @@ -0,0 +1,1602 @@ +/** + ****************************************************************************** + * @file tim.c + * @author Jerry + * @version V2.1 + * @date 19-April-2022 + * @brief tim program body. + ****************************************************************************** + * @attention + * + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" +#include "global.h" +#include "string.h" +#include "soe.h" + +CALI_STRUCT cali; + +uint8_t bAlarmFlag; +uint8_t bAlarmFlagOld; + +AFE_RAM afeRam; +AFE_FLG afeFlg; + +int16_t siCurBuf[4]; //CADC以250ms周期采样4次 +uint8_t ucCadcTimeCnt; //CADC采样计数 +uint8_t bDSGING; //放电状态标记 +uint8_t bCHGING; //充电状态标记 +uint8_t bSTANDBY; //待机状态标记 +uint8_t bFC; //=1充满电 +uint8_t ucChgEndTimeCnt; //充电截止条件判断计数器 +uint8_t ucChgEndRTimeCnt;// +uint8_t E2ucChgEndDelay; //充电截止条件判断延时 +uint8_t E2uiChgEndVol; //充电截止电压 +uint8_t E2siChgEndCur; //充电截止电流 +uint8_t bCHGEnd; //充电结束关充电MOS标记 +uint8_t bCHGClosedFlg; //关闭充电标记 + +uint8_t curLimitFlag; +uint8_t curLimitCount; +uint16_t curLimitReleaseCount; +uint16_t curLimitCloseCount; + +uint8_t DSGcount; //小电流放电计数 +uint8_t DSGminiFlag; //小电流放电标志 +uint8_t CHGcount; +uint8_t CHGminiFlag; + +uint8_t ErrDSGcount; //放电MOS故障的延时计数 +uint8_t ErrCHGcount; //充电MOS故障的延时计数 +uint8_t ErrDSGRelaycount;//放电MOS故障恢复的延时计数 +uint8_t ErrCHGRelaycount;//充电MOS故障恢复的延时计数 + +uint8_t nullCurrent_Flag; //此时1s内的电流采样值无效标志 + +uint8_t sc_OccurFlag; //浪涌短路出现过的标志 +uint8_t tsc_OccurFlag; //真短路出现过的标志 +uint8_t pchgFail_OccurFlag; //预充超时失败出现过的标志 + +uint8_t sc_RepeatFlag; //浪涌短路持续出现的标志 +uint8_t sc_RepeatDelay; //等待浪涌短路倒计时，最大60s =>对应消失后60s内未再次出现，说明正常 +uint8_t sc_RepeatCount; //浪涌短路重复的计数，最大5次 =>对应连续5次出现短路 =>会在第五次短路时，MCU接管将标志位置1，控制MOS持续关闭 + +uint8_t tsc_RepeatFlag; //真短路持续出现的标志 +uint8_t tsc_RepeatDelay; //等待真短路倒计时，最大60s =>对应消失后60s内未再次出现，说明正常 +uint8_t tsc_RepeatCount; //真短路重复的计数，最大5次 =>对应连续5次出现短路 =>会在第五次短路时，MCU接管将标志位置1，控制MOS持续关闭 + +uint8_t pchgFail_RepeatFlag; //预充超时失败持续出现的标志 +uint8_t pchgFail_RepeatTime; //等待预充超时失败倒计时，最大60s =>对应消失后60s内未再次出现，说明正常 +uint8_t pchgFail_RepeatCount; //预充超时失败重复的计数，最大5次 =>对应连续5次出现预充超时失败 =>会在第五次预充超时失败时，锁定不可恢复标志位，控制MOS持续关闭 + +uint8_t fcc4_count; //满充条件4的延时计数 +uint8_t fcc4r_count; //满充条件4释放的延时计数 + +uint16_t CTRL_Order; //上位机[临时]控制MOS关闭指令 + +uint8_t OCC2_Flag; +uint16_t OCC2MoniCount; + +uint8_t sc_Often_Flag; //浪涌短路连续发生，执行锁定的标志 + +uint16_t tsc_relaycount; //真短路5min自动解除的延时计数 + +uint8_t dsgCtrl; //放电MOS控制状态 +uint8_t dsgCtrl_old; + +int16_t cellVol[20]; //20串电压 +int16_t cellVoltageMax; +int16_t cellVoltageMin; + +uint8_t MOS_Close_Flg; //需要控制MOS全关的标志 + +uint8_t sc_close_flag; //控制浪涌短路保护关闭的标志 + +//写AFE的寄存器 +uint8_t AFE_Write(uint8_t addr, uint8_t lenth, uint8_t *data) +{ + uint8_t i; + uint8_t result; + + result = 0; + + for(i=0; i MCU RAM -> AFE +#define afeReg_num 14 +uint8_t MEMORY_UpdateAFE(void) +{ + uint8_t i; + uint8_t WrBuf[14]; + uint8_t RdBuf[14]; + uint8_t afe_mode; + + //默认值 + WrBuf[0] = 0x00; //SCONF4 [bit0~4:10000-16串] + WrBuf[1] = 0x08; //SCONF5 bit3:1-开启CADC电流采集 + WrBuf[2] = 0x08; //SCONF6 bit3:1-开启短路保护 + WrBuf[3] = 0x00; //SCONF7 bit6:0-负载检测上拉电流(暂时默认60uA) + WrBuf[4] = 0x00; //OWV/ALARMH + WrBuf[5] = 0x04; //ALARML bit2:1-短路保护Alarm发送低电平脉冲 + WrBuf[6] = 0x00; //OVT/OVH + WrBuf[7] = 0x00; //OVL + WrBuf[8] = 0x00; //UVT/UVH + WrBuf[9] = 0x00; //UVL + WrBuf[10] = 0x00; //OCD1V/OCD1T + WrBuf[11] = 0x00; //OCD2V/OCD2T [bit0~3:放电过流2保护=2*10+10=30mV] + WrBuf[12] = 0x00; //SCV/SCT bit4~5:短路保护=2*VOCD2=60mV [bit0~3:延时0us] + WrBuf[13] = 0x00; //OCCV/OCCT + + //电池串数：先看ee_sconf1是否在5~16，是则用SCONF1路径；否则用ee_sconf4 + afe_mode = (paraMem.sc_mode >> 8) & 0xFF; + { + uint8_t cn1 = bmsMem.ee_sconf1 & 0x0F; //SCONF1低4位，5-15串，0表示16串 + if((cn1 >= 5 && cn1 <= 15) || cn1 == 0) //5~15串 或 16串(cn=0) + { + bmsMem.ucCellNum = (cn1 == 0) ? 16 : cn1; //cn=0是16串(4位字段存不下16) + WrBuf[0] |= bmsMem.ucCellNum & 0x0F; //309/35XX通用4位cn + } + else if(afe_mode == 1) //SH36735XX，支持4/17~20串 + { + bmsMem.ucCellNum = paraMem.ee_sconf4 & 0x1F; //SCONF4低5位，4-20串 + if(bmsMem.ucCellNum < 4 || bmsMem.ucCellNum > 20) + { + bmsMem.ucCellNum = 20; // 越界默认20串 + } + WrBuf[0] = bmsMem.ucCellNum & 0x1F; // 写入SCONF4 + } + else //SH367309，不支持4/17~20串 + { + bmsMem.ucCellNum = 16; // 越界默认16串 + WrBuf[0] |= bmsMem.ucCellNum & 0x0F; + } + } + + //短路电流=(OCD2V*10+10)*2 + WrBuf[11] |= (bmsMem.ee_scv_sct >> 4) & 0x0F; + //短路延时 + WrBuf[12] |= bmsMem.ee_scv_sct & 0x0F; + + + if(AFE_Write(REG_ADDR_SCONF4, 14, WrBuf) == 0) + { + if(AFE_Read(REG_ADDR_SCONF4, 14, RdBuf) == 0) + { + for(i=0;i<14;i++) + { + if(RdBuf[i] != WrBuf[i]) + { + return 1; //写入有误 + } + } + return 0; + } + else + { + return 2; //读取数据失败 + } + } + else + { + AFE_Reset(); + return 3; //写入数据失败 + } +} + +//电压获取 +//main->while 1s +void AFE_VoltageProcess(void) +{ + uint8_t i; + int16_t max,min,maxIndex,minIndex; //计算最高最低 + int32_t temp; //计算总压 + uint8_t afe_mode; + uint8_t rdLen; + + //先确定串数和读取长度：先看ee_sconf1是否在5~16，是则用SCONF1路径；否则用ee_sconf4 + afe_mode = (paraMem.sc_mode >> 8) & 0xFF; + { + uint8_t cn1 = bmsMem.ee_sconf1 & 0x0F; //SCONF1低4位，5-15串，0表示16串 + if((cn1 >= 5 && cn1 <= 15) || cn1 == 0) //5~15串 或 16串(cn=0) + { + bmsMem.ucCellNum = (cn1 == 0) ? 16 : cn1; //cn=0是16串(4位字段存不下16) + rdLen = 32; //16串 × 2字节 + } + else if(afe_mode == 1) //SH36735XX，支持4/17~20串 + { + bmsMem.ucCellNum = paraMem.ee_sconf4 & 0x1F; //SCONF4低5位，4-20串 + if(bmsMem.ucCellNum < 4 || bmsMem.ucCellNum > 20) + { + bmsMem.ucCellNum = 20; // 越界默认20串 + } + rdLen = 40; //20串 × 2字节 + } + else //SH367309，不支持4/17~20串 + { + bmsMem.ucCellNum = 16; // 越界默认16串 + rdLen = 32; //16串 × 2字节 + } + } + if(AFE_Read(REG_ADDR_CELL1H, rdLen, &afeRam.cell1h) != 0) + { + return; + } + + + //采集电芯电压(显示给上位机) + bmsMem.vCell[0] = ((uint16_t)afeRam.cell1h <<8 | afeRam.cell1l ) *5 >> 5; //=cell1*5/32 + bmsMem.vCell[1] = ((uint16_t)afeRam.cell2h <<8 | afeRam.cell2l ) *5 >> 5; + bmsMem.vCell[2] = ((uint16_t)afeRam.cell3h <<8 | afeRam.cell3l ) *5 >> 5; + bmsMem.vCell[3] = ((uint16_t)afeRam.cell4h <<8 | afeRam.cell4l ) *5 >> 5; + bmsMem.vCell[4] = ((uint16_t)afeRam.cell5h <<8 | afeRam.cell5l ) *5 >> 5; + bmsMem.vCell[5] = ((uint16_t)afeRam.cell6h <<8 | afeRam.cell6l ) *5 >> 5; + bmsMem.vCell[6] = ((uint16_t)afeRam.cell7h <<8 | afeRam.cell7l ) *5 >> 5; + bmsMem.vCell[7] = ((uint16_t)afeRam.cell8h <<8 | afeRam.cell8l ) *5 >> 5; + bmsMem.vCell[8] = ((uint16_t)afeRam.cell9h <<8 | afeRam.cell9l ) *5 >> 5; + bmsMem.vCell[9] = ((uint16_t)afeRam.cell10h <<8 | afeRam.cell10l) *5 >> 5; + bmsMem.vCell[10] = ((uint16_t)afeRam.cell11h <<8 | afeRam.cell11l) *5 >> 5; + bmsMem.vCell[11] = ((uint16_t)afeRam.cell12h <<8 | afeRam.cell12l) *5 >> 5; + bmsMem.vCell[12] = ((uint16_t)afeRam.cell13h <<8 | afeRam.cell13l) *5 >> 5; + bmsMem.vCell[13] = ((uint16_t)afeRam.cell14h <<8 | afeRam.cell14l) *5 >> 5; + bmsMem.vCell[14] = ((uint16_t)afeRam.cell15h <<8 | afeRam.cell15l) *5 >> 5; + bmsMem.vCell[15] = ((uint16_t)afeRam.cell16h <<8 | afeRam.cell16l) *5 >> 5; + + if(afe_mode == 1) + { + bmsMem.vCell2[0] = ((uint16_t)afeRam.cell17h<<8 | afeRam.cell17l)*5>>5; + bmsMem.vCell2[1] = ((uint16_t)afeRam.cell18h<<8 | afeRam.cell18l)*5>>5; + bmsMem.vCell2[2] = ((uint16_t)afeRam.cell19h<<8 | afeRam.cell19l)*5>>5; + bmsMem.vCell2[3] = ((uint16_t)afeRam.cell20h<<8 | afeRam.cell20l)*5>>5; + } + + //采集电芯电压(实际) + cellVol[0] = (int16_t)((uint16_t)afeRam.cell1h <<8 | afeRam.cell1l ) *5 >> 5; //=cell1*5/32 + cellVol[1] = (int16_t)((uint16_t)afeRam.cell2h <<8 | afeRam.cell2l ) *5 >> 5; + cellVol[2] = (int16_t)((uint16_t)afeRam.cell3h <<8 | afeRam.cell3l ) *5 >> 5; + cellVol[3] = (int16_t)((uint16_t)afeRam.cell4h <<8 | afeRam.cell4l ) *5 >> 5; + cellVol[4] = (int16_t)((uint16_t)afeRam.cell5h <<8 | afeRam.cell5l ) *5 >> 5; + cellVol[5] = (int16_t)((uint16_t)afeRam.cell6h <<8 | afeRam.cell6l ) *5 >> 5; + cellVol[6] = (int16_t)((uint16_t)afeRam.cell7h <<8 | afeRam.cell7l ) *5 >> 5; + cellVol[7] = (int16_t)((uint16_t)afeRam.cell8h <<8 | afeRam.cell8l ) *5 >> 5; + cellVol[8] = (int16_t)((uint16_t)afeRam.cell9h <<8 | afeRam.cell9l ) *5 >> 5; //=cell1*5/32 + cellVol[9] = (int16_t)((uint16_t)afeRam.cell10h <<8 | afeRam.cell10l) *5 >> 5; + cellVol[10] = (int16_t)((uint16_t)afeRam.cell11h <<8 | afeRam.cell11l) *5 >> 5; + cellVol[11] = (int16_t)((uint16_t)afeRam.cell12h <<8 | afeRam.cell12l) *5 >> 5; + cellVol[12] = (int16_t)((uint16_t)afeRam.cell13h <<8 | afeRam.cell13l) *5 >> 5; + cellVol[13] = (int16_t)((uint16_t)afeRam.cell14h <<8 | afeRam.cell14l) *5 >> 5; + cellVol[14] = (int16_t)((uint16_t)afeRam.cell15h <<8 | afeRam.cell15l) *5 >> 5; + cellVol[15] = (int16_t)((uint16_t)afeRam.cell16h <<8 | afeRam.cell16l) *5 >> 5; + + if(afe_mode == 1) + { + cellVol[16] = (int16_t)((uint16_t)afeRam.cell17h <<8 | afeRam.cell17l) *5 >> 5; + cellVol[17] = (int16_t)((uint16_t)afeRam.cell18h <<8 | afeRam.cell18l) *5 >> 5; + cellVol[18] = (int16_t)((uint16_t)afeRam.cell19h <<8 | afeRam.cell19l) *5 >> 5; + cellVol[19] = (int16_t)((uint16_t)afeRam.cell20h <<8 | afeRam.cell20l) *5 >> 5; + } + + //计算总电压 + temp = 0; + for(i=0;icellVol[i]) + { + min = cellVol[i]; + minIndex = i; + } + } + + cellVoltageMax = max; + cellVoltageMin = min; + if(maxIndex < 16) + { + bmsMem.cellVoltageMax = bmsMem.vCell[maxIndex]; + } + else + { + bmsMem.cellVoltageMax = bmsMem.vCell2[maxIndex - 16]; + } + if(minIndex < 16) + { + bmsMem.cellVoltageMin = bmsMem.vCell[minIndex]; + } + else + { + bmsMem.cellVoltageMin = bmsMem.vCell2[minIndex - 16]; + } + bmsMem.cellVoltageMaxIndex = maxIndex; + bmsMem.cellVoltageMinIndex = minIndex; + + //sum of all packs + bmsMem.can_VolMax = bmsMem.cellVoltageMax; + bmsMem.can_VolMaxIndex = bmsMem.cellVoltageMaxIndex; + bmsMem.can_VolMin = bmsMem.cellVoltageMin; + bmsMem.can_VolMinIndex = bmsMem.cellVoltageMinIndex; + + + //过压相关报警和保护 + Trigger_OVAlarm(); //报警 + Release_OVAlarm(); //报警恢复 + Trigger_OVProtect(); //保护 + Release_OVProtect(); //保护恢复 + //欠压相关 + if((bmsMem.balanceStatus & 0x0020) == 0) + { + Trigger_UVAlarm(); //报警 + Release_UVAlarm(); //报警恢复 + Trigger_UVProtect(); //保护 + Release_UVProtect(); //保护恢复 + } + else + { + bmsMem.bStatus1 &= ~0x0202; + bmsMem.bStatus3 &= ~0x0A00; + } +} + +//电流获取 +//read 4 times and average +void AFE_CurrentProcess(void) +{ + uint8_t temp[2]; + int16_t avecur; + + avecur = siCurBuf[ucCadcTimeCnt]; //4个CADC的值存放于数组中 + + if(AFE_Read(REG_ADDR_CADCDH, 2, temp) != 0) + { + siCurBuf[ucCadcTimeCnt] = avecur; //读失败了将上一组电流重赋值 + } + else + { + avecur =(int16_t) (temp[0]<<8 | temp[1]); //读成功赋值 + siCurBuf[ucCadcTimeCnt] = avecur; + } + + if(++ucCadcTimeCnt >= 4) //计算1s内电流的平均值 + { + ucCadcTimeCnt = 0; + avecur = ((int32_t)siCurBuf[0]+siCurBuf[1]+siCurBuf[2]+siCurBuf[3]) >> 2; + + cali.tempCur = avecur - cali.cadcZero; + bmsMem.cadcAveVal = avecur; //显示cadc寄存器电流 + + //对当前电流执行校准，计算校准参数 + if(cali.cmdZero != 0) + { + cali.flagWrZeroToEE = cali.cmdZero; + cali.cmdZero = 0; + + cali.cadcZero = avecur; + + bmsMem.cadcZero = cali.cadcZero; + } + else if(cali.cmdGain != 0) + { + cali.flagWrGainToEE = cali.cmdGain; + cali.cmdGain = 0; + + if(cali.tempCur<0) + { + cali.cadcGain = -cali.current* 100 / cali.tempCur; + } + else if(cali.tempCur>0) + { + cali.cadcGain = cali.current* 100 / cali.tempCur; + } + + bmsMem.cadcGain = cali.cadcGain; + } + + //更新电流值 + if(nullCurrent_Flag == 0) + { + bmsMem.packCurrent = (int32_t)cali.cadcGain * cali.tempCur /100; + } + else //这一秒的电流值无效，同时因为触发条件是写AFE芯片会关闭MOS，正常来说也是无电流的 + { + bmsMem.packCurrent = 0; + nullCurrent_Flag = 0; + } + + + //sum of all packs + bmsMem.can_cur = (int16_t) (bmsMem.packCurrent/10); //统一数值单位0.01A + + + //小电流延迟显示 + if((bmsMem.packCurrent > (-100)) && (bmsMem.packCurrent < 0)) //小电流放电 + { + if(DSGminiFlag == 0) + { + DSGcount++; + if(DSGcount >= 3) //延迟3s显示 + { + DSGminiFlag = 1; + DSGcount = 0; + } + else + { + bmsMem.packCurrent = 0; + } + } + } + else if((bmsMem.packCurrent > 0) && (bmsMem.packCurrent < 100)) //小电流充电 + { + if(CHGminiFlag == 0) + { + CHGcount++; + if(CHGcount >= 3) //延迟3s显示 + { + CHGminiFlag = 1; + CHGcount = 0; + } + else + { + bmsMem.packCurrent = 0; + } + } + } + else + { + DSGcount = 0; + CHGcount = 0; + DSGminiFlag = 0; + CHGminiFlag = 0; + } + + //判断充放电状态 + bDSGING = 0; + bCHGING = 0; + bSTANDBY = 0; + if(bmsMem.packCurrent <= (-100)) + { + bDSGING = 1; + } + else if(bmsMem.packCurrent >= 100) + { + bCHGING = 1; + } + else + { + //待机状态时，电流值存在(上位机可看) + //待机状态时，不参与容量计算，但参与电流校准 + bSTANDBY = 1; + } + + if(curLimit_ctrlFlag == 1) //开启限流后，根据电流值立刻改动限流的占空比 + { + //根据实时电流值调整占空比 + CHG_LIMIT_PWM_Adjust(); + } + } + + //充放电状态赋值 + bmsMem.bStatus3 &= 0xff3f; + if(bCHGING == 1) + { + bmsMem.bStatus3 |= 0x0080; + } + if(bDSGING == 1) + { + bmsMem.bStatus3 |= 0x0040; + } + + //存在充电或放电，休眠起始点更新 + if((bmsMem.packCurrent <= (-2000)) || (bmsMem.packCurrent >= 2000)) + { + if(((paraMem.sleep_min_disable & 0x8000) == 0) || ((paraMem.sleep2_min_disable & 0x8000) == 0)) //任意一项休眠都更新 + { + sleep_flag = 0; + SLEEP_Refresh(); + SLEEP2_Refresh(); + } + } +} + +//电流校准后保存 +void CALI_CurrentProcess(void) +{ + //收到零点校准指令 + if(cali.flagWrZeroToEE != 0) + { + if(scr_WrZero_Flg == 1) + { + scr_WrZero_Flg = 2; //表示完成 + } + else if(cali.flagWrZeroToEE == 1) //上位机执行的校准需要回复，云平台是另外的 + { + modbusFaaRxFlg = 1; + modbus1FaaRxFlg = 1; + } + + cali.flagWrZeroToEE = 0; + cali.flagZeroCaliFail = EEPROM_CALI_WrZero(cali.cadcZero); + } + + //收到增益校准指令 + if(cali.flagWrGainToEE != 0) + { + if(scr_WrGain_Flg == 1) + { + scr_WrGain_Flg = 2; //表示完成 + } + else if(cali.flagWrGainToEE == 1) //上位机执行的校准需要回复，云平台是另外的 + { + modbusFbbRxFlg = 1; + modbus1FbbRxFlg = 1; + } + + cali.flagWrGainToEE = 0; + cali.flagGainCaliFail = EEPROM_CALI_WrGain(cali.cadcGain); + } +} + +//获取MOS温度和环境温度 +//main->while 1s +void AFE_TemperaProcess(void) +{ + //获取afe温度 + if(AFE_Read(REG_ADDR_TEMP1H, 6, &afeRam.temp1h) != 0) + { + return; + } + + afeFlg.temp1 = ((uint16_t)afeRam.temp1h <<8 | afeRam.temp1l); + afeFlg.temp2 = ((uint16_t)afeRam.temp2h <<8 | afeRam.temp2l); + afeFlg.temp3 = ((uint16_t)afeRam.temp3h <<8 | afeRam.temp3l); + bmsMem.afe_T1 = TEMP_Cal_CMFA(afeFlg.temp1 * 1000 /(32768-afeFlg.temp1)); + bmsMem.afe_T2 = TEMP_Cal_CMFA(afeFlg.temp2 * 1000 /(32768-afeFlg.temp2)); + bmsMem.afe_T3 = TEMP_Cal_CMFA(afeFlg.temp3 * 1000 /(32768-afeFlg.temp3)); + + + //针对bmsMem.afe_T1+T2，进行MOS温度告警和告警释放 + Trigger_afeTAlarm(); + Release_afeTAlarm(); + //针对bmsMem.afe_T1+T2，进行MOS温度保护和保护释放 + Trigger_afeTProtect(); + Release_afeTProtect(); + + //针对bmsMem.afe_T3，进行环境温度告警和告警释放 + Trigger_amTAlarm(); + Release_amTAlarm(); + //针对bmsMem.afe_T3，进行环境温度保护和保护释放 + Trigger_amTProtect(); + Release_amTProtect(); +} + +//充电限流10A的控制标志位 +void CHG_LIMIT_Ctrl(void) +{ + //触发 + if(curLimitFlag == 0) + { + //常规大电流限流保护 + if(bmsMem.packCurrent >= (bmsMem.CHGLimit_Value * 1000)) + { + curLimitCount++; + if(curLimitCount >= bmsMem.CHGLimit_Count) + { + curLimitCount = 0; + curLimitFlag = 1; + } + } + } + //延时释放 + else + { + if(bCHGING == 1) //充电过程中，持续10min后释放 + { + curLimitReleaseCount++; + if(curLimitReleaseCount >= bmsMem.CHGLimit_ReleaseCount) + { + curLimitReleaseCount = 0; + curLimitFlag = 0; + } + } + else + { + curLimitCloseCount++; + if(curLimitCloseCount >= 8) + { + curLimitCloseCount = 0; + curLimitFlag = 0; + } + } + } + + //若之前有充电报警在，限流不能打开 + //包括AFE的充电报警 //但去掉充电过流 + if(((bmsMem.bStatus1 & 0x41) != 0) || ((bmsMem.bStatus2 & 0x0183) != 0) || ((bmsMem.bStatus3 & 0x0100) != 0) || ((bmsMem.temperaStatus & 0x05) != 0) || ((bmsMem.balanceStatus & 0x0500) != 0)) + { + curLimitReleaseCount = 0; + curLimitFlag = 0; + } + //若正在放电，限流板应当关闭 + if(bDSGING == 1) + { + curLimitReleaseCount = 0; + curLimitFlag = 0; + } + //进行充电MOS控制时，限流板也关闭 + if(((CTRL_Order & 0x02) != 0) || ((paraMem.ctrl_disable & 0x02) != 0)) + { + curLimitReleaseCount = 0; + curLimitFlag = 0; + } + + //限流标志 + if(curLimitFlag == 0) + { + bmsMem.balanceStatus &= 0xffef; + } + else + { + bmsMem.balanceStatus |= 0x0010; + } +} + +//放电过流2的判断 +void OCC2_TIM_Moni(void) +{ + //放电过流2 + if((bmsMem.bStatus1 & BIT10) ==0) + { + if(bmsMem.packCurrent < -paraMem.mcu_ocd2*1000) + { + OCC2MoniCount++; + if(OCC2MoniCount > paraMem.mcu_ocd2_t) //单位10ms + { + bmsMem.bStatus1 |= BIT10; + OCC2MoniCount = 0; + } + } + else + { + OCC2MoniCount = 0; + } + } +} + +//因预充使用了CTTRL引脚，所以放电过流2只是用中断来写RAM关闭放电MOS +void OCC2_Ctrl(void) +{ + uint8_t temp[1]; + + //触发后立刻关闭放电MOS + if((bmsMem.bStatus1 & BIT10) != 0) + { + //只在第一次执行 + if(OCC2_Flag == 0) + { + if(AFE_Read(REG_ADDR_SCONF2,1,temp) == 0) + { + temp[0] &= ~0x02; + AFE_Write(REG_ADDR_SCONF2,1,&temp[0]); + + OCC2_Flag = 1; + } + } + } + else + { + OCC2_Flag = 0; + } +} + +//统一写MOS控制到RAM，并控制限流。限流和充放MOS要有时间间隔 +void AFE_Ctrl(void) +{ + //默认正常[充放MOS全由硬件控制] + uint8_t temp = 0x83; + + //开放电MOS前开预充 + if(PCHG_Flag == 1) + { + temp &= ~0x02; //保持关闭放电MOS + PCHG_Ctrl(); //走预充流程 + } + + /*控制限流关闭在前*/ + if(curLimitFlag == 0) + { + CHG_LIMIT_Off(); + } + + //休眠模式[关闭放电MOS，不影响充电MOS和限流板状态] + if(sleep_flag == 1) + { + temp &= ~0x02; + } + //各种充电保护(不带afe的)+满充条件4[关闭充电MOS和限流板，不影响放电MOS状态] + if(((bmsMem.bStatus1 & 0x0901) != 0) || ((bmsMem.bStatus2 & 0x0083) != 0) || ((bmsMem.temperaStatus & 0x0515) != 0)) //关闭充电MOS + { + temp &= ~0x01; + + if(((bmsMem.bStatus1 & 0x0901) != 0) || ((bmsMem.bStatus2 & 0x0083) != 0) || ((bmsMem.temperaStatus & 0x0505) != 0)) //除了充电过流外，会同步关闭限流 + { + curLimitReleaseCount = 0; + curLimitFlag = 0; + } + } + //各种放电保护(带真短路和预充失败)[关闭放电MOS，不影响充电MOS和限流板状态] + if(((bmsMem.bStatus1 & 0x062E) != 0) || ((bmsMem.bStatus2 & 0x007C) != 0) || ((bmsMem.temperaStatus & 0x0A2A) != 0)) //关闭放电MOS + { + temp &= ~0x02; + } + //限流启用[关闭充电MOS，后续开启限流，不影响放电MOS状态] + if(curLimitFlag == 1) + { + temp &= ~0x01; + } + + /*因上位机写入指令而控制*/ + if(((CTRL_Order & 0x01) != 0) || ((paraMem.ctrl_disable & 0x01) != 0)) //强制关闭放电MOS + { + temp &= ~0x02; + } + if(((CTRL_Order & 0x02) != 0) || ((paraMem.ctrl_disable & 0x02) != 0)) //强制关闭充电MOS + { + temp &= ~0x01; + } + + /*当放电MOS被关闭，将要被打开，执行预充而不打开放电MOS*/ + if((temp & 0x02) != 0) //要开启放电MOS + { + dsgCtrl = 0xAA; + } + else //要关闭放电MOS + { + dsgCtrl = 0xBB; + } + + if(dsgCtrl_old == 0) //初始值0不参与判断 + { + dsgCtrl_old = dsgCtrl; + } + else + { + if((dsgCtrl == 0xAA) && (dsgCtrl_old != 0xAA)) //从关闭转变为打开 + { + if(PCHG_Flag == 0) + { + temp &= ~0x02; //保持关闭 + PCHG_Flag = 1;//启动预充 + } + else if(PCHG_Flag == 2) + { + PCHG_Flag = 0;//下次可以继续启动预充 + dsgCtrl_old = dsgCtrl; + } + } + else + { + dsgCtrl_old = dsgCtrl; + } + } + + + /*开关MOS控制*/ + AFE_Write(REG_ADDR_SCONF2,1,&temp); + + /*控制限流打开在后*/ + if(curLimitFlag == 1) + { + CHG_LIMIT_On(); + } +} + +//MOS控制开 +//预充流程结束/真短路检测结束/真短路释放 +void CTRL_On(void) +{ + //不需要控制，只要后续AFE_Ctrl正常控制 + MOS_Close_Flg = 0; +} + +//MOS控制关 +void CTRL_Off(void) +{ + uint8_t temp = 0x80; + AFE_Write(REG_ADDR_SCONF2,1,&temp); + + //控制全关时，正常控制MOS处也要同步 + MOS_Close_Flg = 1; +} + + +//获取AFE状态位 +//main->while 1s +void AFE_ProtectProcess(void) +{ + uint8_t temp[5]; + + //read flag1-3,bstatus1-2 + if(AFE_Read(REG_ADDR_FLAG1,5,temp) == 0) + { + //短路保护 + if((temp[0] & BIT4) != 0) + { + bmsMem.bStatus1 |= BIT5; + } + else + { + bmsMem.bStatus1 &= ~BIT5; + } + //充电MOS状态 + if((temp[3] & BIT0) != 0) + { + bmsMem.bStatus3 |= BIT1; + } + else + { + bmsMem.bStatus3 &= ~BIT1; + } + //放电MOS状态 + if((temp[3] & BIT1) != 0) + { + bmsMem.bStatus3 |= BIT0; + } + else + { + bmsMem.bStatus3 &= ~BIT0; + } + } + + //浪涌短路保护的释放 + if(sc_close_flag == 1) + { + uint8_t temp = 0x00; + if(AFE_Write(REG_ADDR_FLAG1,1,&temp) == 0) //清空AFE标志位 + { + temp = 0x80; + if(AFE_Write(REG_ADDR_SCONF2,1,&temp) == 0) //继续允许MCU清零标志位 + { + bmsMem.bStatus1 &= ~BIT5; //浪涌短路保护标志释放(只有2步都成功后才真正清除和释放) + sc_close_flag = 0; + } + } + } + //充放电MOS故障监测 + if((bmsMem.bStatus3 & 0x01) == 0) //放电MOS是关闭状态 + { + //当出现MOS故障，会主动关闭对应MOS，若此时还有电流，持续报警MOS故障 + if((bmsMem.bStatus2 & 0x40) == 0) //还没出现放电MOS故障 + { + if(bmsMem.packCurrent < (-2000)) //有放电电流 + { + ErrDSGcount++; + if(ErrDSGcount >= 30) + { + bmsMem.bStatus2 |= BIT6; //说明放电MOS故障 + } + } + else + { + ErrDSGcount = 0; + } + } + else //已经出现放电MOS故障 + { + //当因MOS故障关闭MOS后电流消失，那就消去MOS故障 + if(bmsMem.packCurrent > (-100)) //不再是放电电流 + { + ErrDSGRelaycount++; + if(ErrDSGRelaycount >= 3) + { + bmsMem.bStatus2 &= ~BIT6; //说明放电MOS正常 + } + } + else + { + ErrDSGRelaycount = 0; + } + } + } + else //放电MOS也是开启状态 + { + ErrDSGcount = 0; + ErrDSGRelaycount = 0; + bmsMem.bStatus2 &= ~BIT6; //不考虑放电MOS是否故障 + } + if(((bmsMem.bStatus3 & 0x02) == 0) && (curLimitFlag == 0)) //充电MOS是关闭状态 //11.7同时判断限流板没开启 + { + if((bmsMem.bStatus2 & 0x80) == 0) //还没出现充电MOS故障 + { + if(bmsMem.packCurrent > 2000) //有充电电流 + { + ErrCHGcount++; + if(ErrCHGcount >= 30) + { + bmsMem.bStatus2 |= BIT7; //说明充电MOS故障 + } + } + else + { + ErrCHGcount = 0; + } + } + else //已经出现放电MOS故障 + { + if(bmsMem.packCurrent < 100) //不再是充电电流 + { + ErrCHGRelaycount++; + if(ErrCHGRelaycount >= 3) + { + bmsMem.bStatus2 &= ~BIT7; //说明放电MOS正常 + } + } + else + { + ErrCHGRelaycount = 0; + } + } + } + else + { + ErrCHGcount = 0; + ErrCHGRelaycount = 0; + bmsMem.bStatus2 &= ~BIT7; //说明充电MOS正常 + } + + //DO执行条件：出现MOS故障 + if((bmsMem.bStatus2 & 0xC0) == 0) + { + DO_Off(); + bmsMem.temperaStatus &= 0xff7f; + } + else + { + DO_On(); //开启继电器让外部控制 + bmsMem.temperaStatus |= 0x0080; + } + + + /*浪涌短路保护连续出现的计算和锁定*/ + //浪涌短路保护释放——无法释放，只能等待自恢复时间8s + //连续出现5次后，直接MCU接管标志位并控制MOS全关 + //浪涌短路过程中检测是否真短路 + if((bmsMem.balanceStatus & BIT6) != 0) + { + bmsMem.bStatus1 |= 0x0020; + CTRL_Off(); + } + else + { + //浪涌短路出现 + if((bmsMem.bStatus1 & BIT5) != 0) + { + //刚出现时 + if(sc_OccurFlag == 0) + { + sc_OccurFlag = 1; + sc_RepeatDelay = 0; + + //分析是否满足锁定条件 + if(sc_RepeatFlag == 0) //此前60s内并未出现 (此时重复次数应=0) + { + sc_RepeatFlag = 1; //用于在消失后的计时判断 + } + else + { + sc_RepeatCount++; //浪涌短路持续60s不出现的话，sc_OccurFlag会置0，所以这时候存在值1，说明是在60s内出现的，计数次数+1 + + if(sc_RepeatCount+1 >= paraMem.scWaitNum) //当计数达到4时(即连续发生了五次浪涌短路)，直接锁定，"浪涌短路"持续显示，持续关闭MOS + { + sc_RepeatCount = 0; + bmsMem.balanceStatus |= BIT6; //浪涌短路锁定启用，只有重启可清零 + } + } + } + } + //浪涌短路消失后 + else + { + sc_OccurFlag = 0; + + if(TSC_detectFlag != 0xAA) + { + TSC_detectFlag = 0; + } + + //浪涌短路出现后又消失，若在60s内监测到浪涌短路不开启则计数恢复0，否则计数+1 + if(sc_RepeatFlag == 1) + { + sc_RepeatDelay++; + if(sc_RepeatDelay > paraMem.scWait_T) //持续60s + { + sc_RepeatFlag = 0; //标志置0 + sc_RepeatDelay = 0; //倒计时清零 + sc_RepeatCount = 0; //连续出现计数清零 + } + } + else + { + sc_RepeatDelay = 0; + } + } + } + + /*真短路保护连续出现的计算和锁定，和未锁定时的自动释放*/ + //真短路保护释放——5min自动解除 + //连续出现5次后，直接MCU接管标志位并控制MOS + if((bmsMem.balanceStatus & BIT7) != 0) + { + bmsMem.bStatus2 |= 0x0010; + CTRL_Off(); + } + else + { + //5min自动解除 + if((bmsMem.bStatus2 & BIT4) != 0) + { + tsc_relaycount++; + if(tsc_relaycount > 300) + { + tsc_relaycount = 0; + + TSC_Flag = 0; + TSC_detectFlag = 0; + + bmsMem.bStatus2 &= ~BIT4; + CTRL_On(); //释放充放MOS + } + } + + //真短路出现 + if((bmsMem.bStatus2 & BIT4) != 0) + { + //刚出现时 + if(tsc_OccurFlag == 0) + { + tsc_OccurFlag = 1; + tsc_RepeatDelay = 0; + + //分析是否满足锁定条件 + if(tsc_RepeatFlag == 0) //此前60s内并未出现 (此时重复次数应=0) + { + tsc_RepeatFlag = 1; //用于在消失后的计时判断 + } + else + { + tsc_RepeatCount++; //真短路持续60s不出现的话，tsc_OccurFlag会置0，所以这时候存在值1，说明是在60s内出现的，计数次数+1 + + if(tsc_RepeatCount+1 >= paraMem.scWaitNum) //当计数达到4时(即连续发生了五次真短路)，直接锁定，"真短路"持续显示，持续关闭MOS + { + tsc_RepeatCount = 0; + bmsMem.balanceStatus |= BIT7; //真短路锁定用[预充超时失败锁定]标志位启用，只有重启可清零 + } + } + } + } + //真短路消失 + else + { + tsc_OccurFlag = 0; + + //真短路出现后又消失，若在60s内监测到真短路不开启则计数恢复0，否则计数+1 + if(tsc_RepeatFlag == 1) + { + tsc_RepeatDelay++; + if(tsc_RepeatDelay > paraMem.scWait_T) //持续60s + { + tsc_RepeatFlag = 0; //标志置0 + tsc_RepeatDelay = 0; //倒计时清零 + tsc_RepeatCount = 0; //连续出现计数清零 + } + } + else + { + tsc_RepeatDelay = 0; + } + } + } + + + //满充条件4满足后，停止充电 + if((paraMem.soc100_methods & 0x08) != 0) + { + if((bmsMem.bStatus1 & 0x0800) == 0) //还没出现满充停充 + { + if((bmsMem.packVoltage >= paraMem.soc100_vol*100) && (bmsMem.packCurrent <= paraMem.soc100_cur*100) && (bCHGING == 1)) + { + fcc4_count++; + if(fcc4_count >= 3) + { + bmsMem.bStatus1 |= 0x0800; //置标志位，控制MOS关闭 + } + } + else + { + fcc4_count = 0; + } + } + else //出现后如果任一对应条件消失，标志释放 + { + if((bmsMem.packVoltage < paraMem.soc100_vol*100) || (bmsMem.soc < 96) || (bmsMem.packCurrent < -3000)) //特殊解除项：①SOC<96% ②放电电流>3A + { + fcc4r_count++; + if(fcc4r_count >= 3) + { + bmsMem.bStatus1 &= 0xf7ff; //标志位恢复 + } + } + else + { + fcc4r_count = 0; + } + } + } + else + { + bmsMem.bStatus1 &= 0xf7ff; + } + + + //sum of all packs + bmsMem.can_status_byte1 = bmsMem.bStatus1; + bmsMem.can_status_byte2 = bmsMem.bStatus2; + bmsMem.can_status_byte3 = bmsMem.bStatus3; + bmsMem.can_status_byte4 = bmsMem.temperaStatus; //温度报警判断已在此之前执行 + + + #if Key_PressLong + if((ON_confirm_flg != 0) && (RST_confirm_flg != 1) && (OFF_confirm_flg != 1)) + #endif + { + //(过压单独讨论，其他的都在这) + //报警灯亮与报警跳转 //浪涌短路加回来 + if(((bmsMem.bStatus1 & 0x067e) != 0) || ((bmsMem.bStatus2 & 0x001f) !=0) || ((bmsMem.bStatus3 & 0x0008) !=0) || ((bmsMem.temperaStatus & 0x0f3f) !=0)) + { + if(sleep_flag == 0) LED_ALARM_On(); + else LED_ALARM_Off(); + } + //只亮报警灯 + else if(((bmsMem.bStatus2 & 0x00e0) !=0) || ((bmsMem.temperaStatus & 0x0040) !=0) || ((bmsMem.balanceStatus & BIT6) != 0)) //BIT6.7-放电MOS故障、充电MOS故障、预充失败、急停 (不在屏幕上) //浪涌短路锁定亮灯 + { + if(sleep_flag == 0) LED_ALARM_On(); + else LED_ALARM_Off(); + } + //报警灯灭 + else + { + //若出现总体过压|单体过压,则不恢复原状，等待之后的判断 + if((bmsMem.bStatus1 & 0x0101) == 0) + { + LED_ALARM_Off(); + } + } + + //主机屏幕报警页跳转判断（所有保护） + if(((bmsMem.bStatus1 & 0x077f) != 0) || ((bmsMem.bStatus2 & 0x001f) !=0) || ((bmsMem.bStatus3 & 0x0008) !=0) || ((bmsMem.temperaStatus & 0x0f3f) !=0)) + { + bAlarmFlag = 1; + } + else + { + bAlarmFlag = 0; + bAlarmFlagOld = 0; + } + } + + + //soe记录判断 + soe.bsNew[0] = bmsMem.bStatus1 & 0xff; + soe.bsNew[1] = bmsMem.bStatus2 & 0xff; + soe.bsNew[2] = bmsMem.bStatus3 & 0xff; + soe.bsNew[3] = bmsMem.temperaStatus & 0xff; + soe.bsNew[4] = bmsMem.balanceStatus & 0xff; + soe.bsNew[5] = ((bmsMem.bStatus1>>4) & 0xf0) | ((bmsMem.temperaStatus>>8) & 0x0f); //占用原packStatus位置，保存新增保护 + + + //电压报警备份 //原来是正常状态 VS 已经出现报警 + //单体过压 + if((soe.bsOld[0] & 0x01) == 0) + { + if((soe.bsNew[0] & 0x01) != 0) //报警触发 + { + soe.bsOld[0] = soe.bsNew[0]; //如果已经执行记录，就不会再执行 + soe.bkType = BKTYPE_ALARM; + } + } + else + { + if((soe.bsNew[0] & 0x01) == 0) //没有报警，上次清除 + { + soe.bsOld[0] &= 0XFE; //~0X01 + } + } + //单体欠压 + if((soe.bsOld[0] & 0x02) == 0) + { + if((soe.bsNew[0] & 0x02) != 0) //报警触发 + { + soe.bsOld[0] = soe.bsNew[0]; //如果已经执行记录，就不会再执行 + soe.bkType = BKTYPE_ALARM; + } + } + else + { + if((soe.bsNew[0] & 0x02) == 0) //没有报警，上次清除 + { + soe.bsOld[0] &= 0XFD; //~0X02 + } + } + //总体过压 + if((soe.bsOld[5] & 0x10) == 0) + { + if((soe.bsNew[5] & 0x10) != 0) //报警触发 + { + soe.bsOld[5] = soe.bsNew[5]; //如果已经执行记录，就不会再执行 + soe.bkType = BKTYPE_ALARM; + } + } + else + { + if((soe.bsNew[5] & 0x10) == 0) //没有报警，上次清除 + { + soe.bsOld[5] &= 0XEF; //~0X10 + } + } + //总体欠压 + if((soe.bsOld[5] & 0x20) == 0) + { + if((soe.bsNew[5] & 0x20) != 0) //报警触发 + { + soe.bsOld[5] = soe.bsNew[5]; //如果已经执行记录，就不会再执行 + soe.bkType = BKTYPE_ALARM; + } + } + else + { + if((soe.bsNew[5] & 0x20) == 0) //没有报警，上次清除 + { + soe.bsOld[5] &= 0XDF; //~0X20 + } + } + //异常高压 + if((soe.bsOld[0] & 0x40) == 0) + { + if((soe.bsNew[0] & 0x40) != 0) //报警触发 + { + soe.bsOld[0] = soe.bsNew[0]; //如果已经执行记录，就不会再执行 + soe.bkType = BKTYPE_ALARM; + } + } + else + { + if((soe.bsNew[0] & 0x40) == 0) //没有报警，上次清除 + { + soe.bsOld[0] &= 0XBF; //~0X40 + } + } + //低电压禁止充电 + if((soe.bsOld[2] & 0x08) == 0) + { + if((soe.bsNew[2] & 0x08) != 0) //报警触发 + { + soe.bsOld[2] = soe.bsNew[2]; //如果已经执行记录，就不会再执行 + soe.bkType = BKTYPE_ALARM; + } + } + else + { + if((soe.bsNew[2] & 0x08) == 0) //没有报警，上次清除 + { + soe.bsOld[2] &= 0XF7; //~0X08 + } + } + + + //电流报警备份 + //充电过流 + if(((soe.bsOld[0] & 0x10) == 0) && ((soe.bsOld[3] & 0x10) == 0)) + { + if(((soe.bsNew[0] & 0x10) != 0) || ((soe.bsNew[3] & 0x10) != 0)) //报警触发 + { + soe.bsOld[0] = soe.bsNew[0]; //如果已经执行记录，就不会再执行 + soe.bsOld[3] = soe.bsNew[3]; + soe.bkType = BKTYPE_ALARM; + } + } + else + { + if(((soe.bsNew[0] & 0x10) == 0) && ((soe.bsNew[3] & 0x10) == 0)) //没有报警，上次清除 + { + soe.bsOld[0] &= 0XEF; //~0X10 + soe.bsOld[3] &= 0XEF; //~0X10 + } + } + //放电过流1 + if(((soe.bsOld[0] & 0x04) == 0) && ((soe.bsOld[3] & 0x20) == 0)) + { + if(((soe.bsNew[0] & 0x04) != 0) || ((soe.bsNew[3] & 0x20) != 0)) //报警触发 + { + soe.bsOld[0] = soe.bsNew[0]; //如果已经执行记录，就不会再执行 + soe.bsOld[3] = soe.bsNew[3]; + soe.bkType = BKTYPE_ALARM; + } + } + else + { + if(((soe.bsNew[0] & 0x04) == 0) && ((soe.bsNew[3] & 0x20) == 0)) //没有报警，上次清除 + { + soe.bsOld[0] &= 0XFB; //~0x04 + soe.bsOld[3] &= 0XDF; //~0x20 + } + } + //放电过流2 + if(((soe.bsOld[0] & 0x08) == 0) && ((soe.bsOld[5] & 0x40) == 0)) + { + if(((soe.bsNew[0] & 0x08) != 0) || ((soe.bsNew[5] & 0x40) != 0)) //报警触发 + { + soe.bsOld[0] = soe.bsNew[0]; //如果已经执行记录，就不会再执行 + soe.bsOld[5] = soe.bsNew[5]; + soe.bkType = BKTYPE_ALARM; + } + } + else + { + if(((soe.bsNew[0] & 0x08) == 0) && ((soe.bsNew[5] & 0x40) == 0)) //没有报警，上次清除 + { + soe.bsOld[0] &= 0XF7; //~0x08 + soe.bsOld[5] &= 0XBF; //~0x40 + } + } + //浪涌短路 + if((soe.bsOld[0] & 0x20) == 0) + { + if((soe.bsNew[0] & 0x20) != 0) //报警触发 + { + soe.bsOld[0] = soe.bsNew[0]; //如果已经执行记录，就不会再执行 + soe.bkType = BKTYPE_ALARM; + } + } + else + { + if((soe.bsNew[0] & 0x20) == 0) //没有报警，上次清除 + { + soe.bsOld[0] &= 0XDF; //~0X20 + } + } + //真短路 + if(((soe.bsOld[1] & 0x10) ==0)) + { + if((soe.bsNew[1] & 0x10) != 0) + { + soe.bsOld[1] = soe.bsNew[1]; + soe.bkType = BKTYPE_ALARM; + } + } + else + { + if((soe.bsNew[1] & 0x10) == 0) + { + soe.bsOld[1] &= 0XEF; //~0X10 + } + } + + + //温度报警备份 + //充电高温 + if(((soe.bsOld[1] & 0x02) == 0) && ((soe.bsOld[3] & 0x01) == 0) && ((soe.bsOld[5] & 0x01) == 0)) + { + if(((soe.bsNew[1] & 0x02) !=0) || ((soe.bsNew[3] & 0x01) !=0) || ((soe.bsNew[5] & 0x01) !=0)) + { + soe.bsOld[1] = soe.bsNew[1]; //如果已经执行记录，就不会再执行 + soe.bsOld[3] = soe.bsNew[3]; + soe.bsOld[5] = soe.bsNew[5]; + soe.bkType = BKTYPE_ALARM; + } + } + else + { + if(((soe.bsNew[1] & 0x02) ==0) && ((soe.bsNew[3] & 0x01) ==0) && ((soe.bsNew[5] & 0x01) ==0)) + { + soe.bsOld[1] &= 0XFD; //~0x02 + soe.bsOld[3] &= 0XFE; //~0x01 + soe.bsOld[5] &= 0XFE; //~0x01 + } + } + //放电高温 + if(((soe.bsOld[1] & 0x08) == 0) && ((soe.bsOld[3] & 0x02) == 0) && ((soe.bsOld[5] & 0x02) == 0)) + { + if(((soe.bsNew[1] & 0x08) !=0) || ((soe.bsNew[3] & 0x02) !=0) || ((soe.bsNew[5] & 0x02) !=0)) + { + soe.bsOld[1] = soe.bsNew[1]; //如果已经执行记录，就不会再执行 + soe.bsOld[3] = soe.bsNew[3]; + soe.bsOld[5] = soe.bsNew[5]; + soe.bkType = BKTYPE_ALARM; + } + } + else + { + if(((soe.bsNew[1] & 0x08) ==0) && ((soe.bsNew[3] & 0x02) ==0) && ((soe.bsNew[5] & 0x02) ==0)) + { + soe.bsOld[1] &= 0XF7; //~0x08 + soe.bsOld[3] &= 0XFD; //~0x02 + soe.bsOld[5] &= 0XFD; //~0x02 + } + } + //充电低温 + if(((soe.bsOld[1] & 0x01) == 0) && ((soe.bsOld[3] & 0x04) == 0) && ((soe.bsOld[5] & 0x04) == 0)) + { + if(((soe.bsNew[1] & 0x01) !=0) || ((soe.bsNew[3] & 0x04) !=0) || ((soe.bsNew[5] & 0x04) !=0)) + { + soe.bsOld[1] = soe.bsNew[1]; //如果已经执行记录，就不会再执行 + soe.bsOld[3] = soe.bsNew[3]; + soe.bsOld[5] = soe.bsNew[5]; + soe.bkType = BKTYPE_ALARM; + } + } + else + { + if(((soe.bsNew[1] & 0x01) ==0) && ((soe.bsNew[3] & 0x04) ==0) && ((soe.bsNew[5] & 0x04) ==0)) + { + soe.bsOld[1] &= 0XFE; //~0x01 + soe.bsOld[3] &= 0XFB; //~0x04 + soe.bsOld[5] &= 0XFB; //~0x04 + } + } + //放电低温 + if(((soe.bsOld[1] & 0x04) == 0) && ((soe.bsOld[3] & 0x08) == 0) && ((soe.bsOld[5] & 0x08) == 0)) + { + if(((soe.bsNew[1] & 0x04) !=0) || ((soe.bsNew[3] & 0x08) !=0) || ((soe.bsNew[5] & 0x08) !=0)) + { + soe.bsOld[1] = soe.bsNew[1]; //如果已经执行记录，就不会再执行 + soe.bsOld[3] = soe.bsNew[3]; + soe.bsOld[5] = soe.bsNew[5]; + soe.bkType = BKTYPE_ALARM; + } + } + else + { + if( ((soe.bsNew[1] & 0x04) ==0) && ((soe.bsNew[3] & 0x08) ==0) && ((soe.bsNew[5] & 0x08) ==0)) + { + soe.bsOld[1] &= 0XFB; //~0x04 + soe.bsOld[3] &= 0XF7; //~0x08 + soe.bsOld[5] &= 0XF7; //~0x08 + } + } + + //DI-急停 + if( ((soe.bsOld[3] & 0x40) ==0) ) + { + if((soe.bsNew[3] & 0x40) != 0) + { + soe.bsOld[3] = soe.bsNew[3]; + soe.bkType = BKTYPE_ALARM; + } + } + else + { + if((soe.bsNew[3] & 0x40) == 0) + { + soe.bsOld[3] &= 0XBF; //~0X40 + } + } + + //故障 + //放电MOS故障 + if( ((soe.bsOld[1] & 0x40) ==0) ) + { + if((soe.bsNew[1] & 0x40) != 0) + { + soe.bsOld[1] = soe.bsNew[1]; + soe.bkType = BKTYPE_ALARM; + } + } + else + { + if((soe.bsNew[1] & 0x40) == 0) + { + soe.bsOld[1] &= 0XBF; //~0X40 + } + } + //充电MOS故障 + if( ((soe.bsOld[1] & 0x80) ==0) ) + { + if((soe.bsNew[1] & 0x80) != 0) + { + soe.bsOld[1] = soe.bsNew[1]; + soe.bkType = BKTYPE_ALARM; + } + } + else + { + if((soe.bsNew[1] & 0x80) == 0) + { + soe.bsOld[1] &= 0X7F; //~0X80 + } + } + //预充失败 + if( ((soe.bsOld[1] & 0x20) ==0) ) + { + if((soe.bsNew[1] & 0x20) != 0) + { + soe.bsOld[1] = soe.bsNew[1]; + soe.bkType = BKTYPE_ALARM; + } + } + else + { + if((soe.bsNew[1] & 0x20) == 0) + { + soe.bsOld[1] &= 0XDF; //~0X20 + } + } + + + if(soe.bkType !=0) //当出现情况，进行记录 + { + SOE_BkData(soe.bkType); //函数内部清除BKTYPE标记 + } +} + + diff --git a/MOUDLE/AFE_SH3673520.h b/MOUDLE/AFE_SH3673520.h new file mode 100644 index 0000000..1725e4c --- /dev/null +++ b/MOUDLE/AFE_SH3673520.h @@ -0,0 +1,246 @@ +/** + ****************************************************************************** + * @file global.h + * @author Jerry Cai + * @version V2.1 + * @date 19-April-2022 + * @brief This file contains all the functions prototypes for the GPIO + * firmware library. + ****************************************************************************** + * @attention + * + + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __AFE_SH3673520_H +#define __AFE_SH3673520_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +//#define CALICUR 1000 +//#define CALICUR 30700 //16个4m欧电阻并联 +//#define CALICUR 28000 //16个5m欧电阻并联 + +#define REG_ADDR_SCONF1 0x40 +#define REG_ADDR_SCONF2 0x41 +#define REG_ADDR_SCONF3 0x42 +#define REG_ADDR_SCONF4 0x43 +#define REG_ADDR_SCONF5 0x44 +#define REG_ADDR_SCONF6 0x45 +#define REG_ADDR_SCONF7 0x46 +#define REG_ADDR_OWV_ALARMH 0x47 +#define REG_ADDR_ALARML 0x48 +#define REG_ADDR_OVT_OVH 0x49 +#define REG_ADDR_OVL 0x4A +#define REG_ADDR_UVT_UVL 0x4B +#define REG_ADDR_UVL 0x4C +#define REG_ADDR_OCD1V_OCD1T 0x4D +#define REG_ADDR_OCD2V_OCD2T 0x4E +#define REG_ADDR_SCV_SCT 0x4F +#define REG_ADDR_OCCV_OCCT 0x50 +#define REG_ADDR_OTC 0x51 +#define REG_ADDR_OTD 0x52 +#define REG_ADDR_UTC 0x53 +#define REG_ADDR_UTD 0x54 +#define REG_ADDR_BALANCEH 0x55 +#define REG_ADDR_BALANCEM 0x56 +#define REG_ADDR_BALANCEL 0x57 +#define REG_ADDR_FLAG1 0x58 +#define REG_ADDR_FLAG2 0x59 +#define REG_ADDR_FLAG3 0x5A +#define REG_ADDR_BSTATUS1 0x5B +#define REG_ADDR_BSTATUS2 0x5C +#define REG_ADDR_TEMP1H 0x5D +#define REG_ADDR_TEMP1L 0x5E +#define REG_ADDR_TEMP2H 0x5F +#define REG_ADDR_TEMP2L 0x60 +#define REG_ADDR_TEMP3H 0x61 +#define REG_ADDR_TEMP3L 0x62 +#define REG_ADDR_TEMP4H 0x63 +#define REG_ADDR_TEMP4L 0x64 +#define REG_ADDR_TEMPIH 0x65 +#define REG_ADDR_TEMPIL 0x66 +#define REG_ADDR_CURH 0x67 +#define REG_ADDR_CURL 0x68 +#define REG_ADDR_CELL1H 0x69 +#define REG_ADDR_CELL1L 0x6A +#define REG_ADDR_CELL2H 0x6B +#define REG_ADDR_CELL2L 0x6C +#define REG_ADDR_CELL3H 0x6D +#define REG_ADDR_CELL3L 0x6E +#define REG_ADDR_CELL4H 0x6F +#define REG_ADDR_CELL4L 0x70 +#define REG_ADDR_CELL5H 0x71 +#define REG_ADDR_CELL5L 0x72 +#define REG_ADDR_CELL6H 0x73 +#define REG_ADDR_CELL6L 0x74 +#define REG_ADDR_CELL7H 0x75 +#define REG_ADDR_CELL7L 0x76 +#define REG_ADDR_CELL8H 0x77 +#define REG_ADDR_CELL8L 0x78 +#define REG_ADDR_CELL9H 0x79 +#define REG_ADDR_CELL9L 0x7A +#define REG_ADDR_CELL10H 0X7B +#define REG_ADDR_CELL10L 0X7C +#define REG_ADDR_CELL11H 0X7D +#define REG_ADDR_CELL11L 0X7E +#define REG_ADDR_CELL12H 0X7F +#define REG_ADDR_CELL12L 0X80 +#define REG_ADDR_CELL13H 0X81 +#define REG_ADDR_CELL13L 0X82 +#define REG_ADDR_CELL14H 0X83 +#define REG_ADDR_CELL14L 0X84 +#define REG_ADDR_CELL15H 0X85 +#define REG_ADDR_CELL15L 0X86 +#define REG_ADDR_CELL16H 0X87 +#define REG_ADDR_CELL16L 0X88 +#define REG_ADDR_CELL17H 0X89 +#define REG_ADDR_CELL17L 0X8A +#define REG_ADDR_CELL18H 0X8B +#define REG_ADDR_CELL18L 0X8C +#define REG_ADDR_CELL19H 0X8D +#define REG_ADDR_CELL19L 0X8E +#define REG_ADDR_CELL20H 0X8F +#define REG_ADDR_CELL20L 0X90 +#define REG_ADDR_CADCDH 0x91 +#define REG_ADDR_CADCDL 0x92 +#define REG_ADDR_VTOPH 0x93 +#define REG_ADDR_VTOPL 0x94 +#define REG_ADDR_VCHGRH 0x95 +#define REG_ADDR_VCHGRL 0x96 +#define REG_ADDR_OWDH 0x97 +#define REG_ADDR_OWDM 0x98 +#define REG_ADDR_OWDL 0x99 + + +//AFE RAM Register +typedef struct +{ + uint8_t sconf1; + uint8_t sconf2; + uint8_t sconf3; + uint8_t sconf4; + uint8_t sconf5; + uint8_t sconf6; + uint8_t sconf7; + uint8_t owv_alarmh; + uint8_t alarml; + uint8_t ovt_ovh; + uint8_t ovl; + uint8_t uvt_uvh; + uint8_t uvl; + uint8_t ocd1v_ocd1t; + uint8_t ocd2v_ocd2t; + uint8_t scv_sct; + uint8_t occv_occt; + uint8_t otc; + uint8_t otd; + uint8_t utc; + uint8_t utd; + uint8_t balanceh; + uint8_t balancem; + uint8_t balancel; + uint8_t flag1; + uint8_t flag2; + uint8_t flag3; + uint8_t bstatus1; + uint8_t bstatus2; + uint8_t temp1h; + uint8_t temp1l; + uint8_t temp2h; + uint8_t temp2l; + uint8_t temp3h; + uint8_t temp3l; + uint8_t temp4h; + uint8_t temp4l; + uint8_t tempih; + uint8_t tempil; + uint8_t curh; + uint8_t curl; + uint8_t cell1h; + uint8_t cell1l; + uint8_t cell2h; + uint8_t cell2l; + uint8_t cell3h; + uint8_t cell3l; + uint8_t cell4h; + uint8_t cell4l; + uint8_t cell5h; + uint8_t cell5l; + uint8_t cell6h; + uint8_t cell6l; + uint8_t cell7h; + uint8_t cell7l; + uint8_t cell8h; + uint8_t cell8l; + uint8_t cell9h; + uint8_t cell9l; + uint8_t cell10h; + uint8_t cell10l; + uint8_t cell11h; + uint8_t cell11l; + uint8_t cell12h; + uint8_t cell12l; + uint8_t cell13h; + uint8_t cell13l; + uint8_t cell14h; + uint8_t cell14l; + uint8_t cell15h; + uint8_t cell15l; + uint8_t cell16h; + uint8_t cell16l; + uint8_t cell17h; + uint8_t cell17l; + uint8_t cell18h; + uint8_t cell18l; + uint8_t cell19h; + uint8_t cell19l; + uint8_t cell20h; + uint8_t cell20l; + uint8_t cadcdh; + uint8_t cadcdl; + uint8_t vtoph; + uint8_t vtopl; + uint8_t vchgrh; + uint8_t vchgrl; + uint8_t owdh; + uint8_t owdm; + uint8_t owdl; +} AFE_RAM; + +//AFE FLG Register +typedef struct +{ + uint16_t temp1; + uint16_t temp2; + uint16_t temp3; + uint16_t temp4; +} AFE_FLG; + +extern AFE_RAM afeRam; +extern AFE_FLG afeFlg; + + +extern void AFE_VoltageProcess(void); +extern void AFE_CurrentProcess(void); +extern void AFE_TemperaProcess(void); +extern void AFE_ProtectProcess(void); +extern uint8_t MEMORY_UpdateAFE(void); + +extern void InitGasGauge(void); + + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/MOUDLE/GasGauge.c b/MOUDLE/GasGauge.c new file mode 100644 index 0000000..d7c3ffa --- /dev/null +++ b/MOUDLE/GasGauge.c @@ -0,0 +1,656 @@ +/******************************************************************************** +Copyright (C), Sinowealth Electronic. Ltd. +Author: Sino +Version: V0.0 +Date: 2014/05/30 +History: + V0.0 2014/05/30 Preliminary +********************************************************************************/ +#include "stm32f10x.h" +#include "global.h" +#include "string.h" +#include "rtc.h" + +uint8_t oldsoc; +uint8_t newsoc; + +uint8_t fullToZeroStudyFlag; //婊″厖寮濮嬪涔犳爣璁 +uint8_t zeroToFullStudyFlag; //婊℃斁寮濮嬪涔犳爣璁 + +uint32_t packcheck_OV; //鍗曚綋杩囧帇鏍″噯SOC鐨勬诲帇鍒ゆ柇鍊 +uint32_t packcheck_UV; //鍗曚綋娆犲帇鏍″噯SOC鐨勬诲帇鍒ゆ柇鍊 + +uint16_t ncc_Ah; //棰濆畾瀹归噺锛岀敤浜庤绠椾紶缁欓嗗彉鍣ㄧ殑骞舵満鎬诲閲 鍗曚綅1Ah +uint16_t fcc_Ah; //婊″厖瀹归噺锛岀敤浜庡湪涓婁綅鏈轰慨鏀瑰閲忓拰SOC鍚庯紝璁＄畻姝ゆ椂鐨勫墿浣欏閲 鍗曚綅1Ah +uint16_t rcc_Ah; //鍓╀綑瀹归噺锛岀敤浜庤鍏ョ疮璁″閲忥紝鐒跺悗璁＄畻寰幆娆℃暟 +uint16_t oldrcc_Ah; //鏃х幇鏈夊閲忥紝鐢ㄤ簬姣旇緝璁″叆绱瀹归噺 +uint16_t cumuliCapacity; //绱Н瀹归噺锛屽崟浣0.1Ah + +uint8_t FullCharge_count; //婊″厖鍑忓閲忕殑寤惰繜璁℃暟 +uint8_t FullCharge_count2; //婊″厖鍑忓閲忕殑寤惰繜璁℃暟2 + +uint8_t Cali_Soc_Flag; //15%鏍″噯鎵ц鏍囧織 +uint16_t CaliSocMoniCount; //15%鏍″噯绛夊緟鏃堕棿 + +uint16_t oldcyc; + +uint8_t ClearEE[4] = {0xff,0xff,0xff,0xff}; +uint8_t tmpRdFCC[8]; //鐢ㄤ簬璇诲嚭鎬诲閲忓 +uint8_t tmpWrFCC[8]; //鐢ㄤ簬鍐欏叆鎬诲閲忓 +uint32_t RdFCC; + +uint32_t fcc; //婊″厖瀹归噺锛屽崟浣峬AS +uint8_t fcc_CaliStartFlag; //褰撳紑濮嬪厖鐢垫椂锛屽鏋滄鏃禨OC=0/1%锛屽紑濮嬭鏃 +uint8_t fcc_fullFlag; //杈惧埌浠讳竴婊″厖鏉′欢鐨勬爣蹇楋紝鏄渶缁堟墽琛屾弧鍏呭閲忔牎鍑嗙殑鏉′欢涔嬩竴 + + +/******************************************************************************* +Function:InitGasGauge() +Description: Calculate the remaining capacity according to pack voltage +Input: NULL +Output: NULL +Others: +*******************************************************************************/ +void InitGasGauge(void) +{ + uint8_t tmpRd[2],tmpWr[2]; + uint16_t capacity,cyctime; + + //涓婄數璇籈EPROM 棰濆畾瀹归噺鍊 + EEPROM_RdMulByte(EE_NCC,tmpRd); + capacity = tmpRd[0]<<8 | tmpRd[1]; + if(capacity>0 && capacity<=1000) //濡傛灉涔嬪墠鍐欒繃瀹归噺鍊,灏辨寜鐓т箣鍓嶇殑鍊兼樉绀猴紝鑼冨洿1~1000锛屽惁鍒欐樉绀100Ah + { + bmsMem.ncc = 3600 * 1000 * capacity; + ncc_Ah = capacity; + } + else + { + bmsMem.ncc = 3600 * 1000 * 100; //绯荤粺棰濆畾瀹归噺榛樿100AH = 100,000mAH = 360,000,000mAS + ncc_Ah = 100; + } + + //涓婄數璇籈EPROM 婊″厖瀹归噺鍊 + //鍓4浣嶆槸姝ｅ硷紝鍚庡洓浣嶆槸鍙嶅硷紝鐢ㄦ潵鏍￠獙鏁板兼纭 + EEPROM_RdMulByte(EE_FCC,tmpRdFCC); + if( ((tmpRdFCC[0]^0xff) == tmpRdFCC[4]) && ((tmpRdFCC[1]^0xff) == tmpRdFCC[5]) && ((tmpRdFCC[2]^0xff) == tmpRdFCC[6]) && ((tmpRdFCC[3]^0xff) == tmpRdFCC[7]) ) + { + RdFCC = tmpRdFCC[0]<<24 | tmpRdFCC[1]<<16 | tmpRdFCC[2]<<8 | tmpRdFCC[3]; + if((RdFCC>0) && (RdFCC <= 0xFFE00000)) //涓嶅嚭閿欑殑姝ｆ暟鑼冨洿涓1~4,292,870,144,澶х害1192Ah + { + fcc = RdFCC; + fcc_Ah = RdFCC / 3600000; + } + else + { + fcc = bmsMem.ncc; + fcc_Ah = bmsMem.ncc / 3600000; + } + } + else + { + fcc = bmsMem.ncc; + fcc_Ah = bmsMem.ncc / 3600000; + } + + //涓婄數璇籈EPROM 寰幆娆℃暟 + EEPROM_RdMulByte(EE_CYCLE,tmpRd); + cyctime = tmpRd[0]<<8 | tmpRd[1]; + if(cyctime > paraMem.sohcali_stopTime+10) //鍒濇璇诲彇 + { + oldcyc = 0; + bmsMem.cycleCount = 0; + } + else + { + oldcyc = cyctime; + bmsMem.cycleCount = cyctime; + } + + //涓婄數璇籈EPROM 绱Н瀹归噺鍊 //璁＄畻鏃讹紝浣跨敤棰濆畾瀹归噺鑰屼笉鏄弧鍏呭閲 + EEPROM_RdMulByte(EE_CUMULI,tmpRd); + capacity = tmpRd[0]<<8 | tmpRd[1]; + if((int)capacity>=0 && capacity<=10*ncc_Ah) //鍓╀綑瀹归噺鑼冨洿0~10000*0.1Ah锛岃秴鍑哄垯鏄剧ず0 + { + cumuliCapacity = capacity; + + //鑾峰緱杩涜寰幆娆℃暟璁＄畻鐨勫崟浣嶅閲(姝ゅ涓嶅彲涓0) + if(paraMem.sohcali_transCent != 0) + { + capacity = 10*ncc_Ah * paraMem.sohcali_transCent/100; + } + else + { + capacity = 10*ncc_Ah * 90/100; //榛樿90% + } + //璁＄畻寰幆娆℃暟 + if(cumuliCapacity >= capacity) //褰撶疮绉閲忚秴鍑烘诲閲忕殑90%,澧炲姞寰幆娆℃暟 + { + bmsMem.cycleCount += cumuliCapacity / capacity; + cumuliCapacity = cumuliCapacity % capacity; + + //淇濆瓨鍙備笌杩囧惊鐜鏁拌绠楀悗鐨勭疮绉閲 + tmpWr[0] = (cumuliCapacity >> 8) & 0xff; + tmpWr[1] = (cumuliCapacity >> 0) & 0xff; + EEPROM_WrMulByte(EE_CUMULI,tmpWr); + delay_ms(5); + } + } + else + { + cumuliCapacity = 0; + } + + + //涓婄數璇籈EPROM soc鍊 + EEPROM_RdMulByte(EE_SOC,&tmpRd[0]); + //姝ｅ父 + if(((int)tmpRd[0]>=0) && (tmpRd[0]<=100)) //鍦ㄦ瘮杈冩搷浣滀腑浣跨敤绫诲瀷杞崲涓嶄細鏀瑰彉鍙橀噺鏈韩鐨勭被鍨 + { + oldsoc = tmpRd[0]; + bmsMem.soc = tmpRd[0]; + + bmsMem.rcc = fcc/100 * bmsMem.soc; + rcc_Ah = fcc_Ah * bmsMem.soc /100; + oldrcc_Ah = rcc_Ah; + } + //棣栨涓婄數鏍规嵁鐢靛帇鏍″噯soc + else + { + OCV_CaliSOC_DataWr(); + bmsMem.soc = OCV_CaliSoc_dp(); + + bmsMem.rcc = fcc/100 * bmsMem.soc; + rcc_Ah = fcc_Ah * bmsMem.soc /100; + oldrcc_Ah = rcc_Ah; + } +} + + +//Manage the capacity of the pack +//interval 1s +void GaugeManage(void) +{ + uint8_t tempWr[2]; + uint16_t capacity; + + /*鍙備笌鍒ゆ柇鐨勬诲帇闄愬*/ + //妯″潡杩囧帇鍊 + packcheck_OV = cell_OV * bmsMem.ucCellNum -8000; + //妯″潡娆犲帇鍊 + packcheck_UV = cell_UV * bmsMem.ucCellNum +5000; + + + /*璁＄畻鍓╀綑瀹归噺*/ + //鐢垫祦绉垎娉曪細寰皬鐢垫祦璁や负鏄共鎵帮紝涓嶅弬涓庤绠 + if( (bmsMem.packCurrent <= (-100)) || (bmsMem.packCurrent >= 100) ) + { + bmsMem.rcc += bmsMem.packCurrent; + } + if(bmsMem.rcc > 0xFFE00000)//4.21娣诲姞锛岄槻姝㈣繃鏀炬暟鎹嚭閿 //鍥犳敼涓烘棤绗﹀彿锛岄渶娓呴浂鐨勮礋鏁拌寖鍥磋-1~-2,097,151锛岀數娴佸煎湪2000A鑼冨洿鍐呯殕鍙帴鍙楋紝涓嶅嚭閿欑殑姝ｆ暟鑼冨洿涓0~4,292,870,144,澶х害1192Ah + { + bmsMem.rcc = 0; + } + + if((paraMem.cali_min_disable & 0x8000) != 0) //涓嶅厑璁稿仛婊″厖瀹归噺鏍″噯 + { + //鍦ㄦ牎鍑嗗閲忓垽鏂墠锛屼繚璇佸弬鏁版纭 + if(fcc_CaliStartFlag != 0) + { + fcc_CaliStartFlag = 0; + + EEPROM_WrMulByte(EE_FCC_TIME,ClearEE); + delay_ms(5); + } + + if(fcc != bmsMem.ncc) //鏍″噯鎬诲閲=棰濆畾瀹归噺 + { + //璧嬪兼弧鍏呭閲=棰濆畾瀹归噺 + fcc = bmsMem.ncc; + fcc_Ah = ncc_Ah; + tmpWrFCC[0] = (fcc>>24) & 0xff; + tmpWrFCC[1] = (fcc>>16) & 0xff; + tmpWrFCC[2] = (fcc>> 8) & 0xff; + tmpWrFCC[3] = (fcc>> 0) & 0xff; + tmpWrFCC[4] = tmpWrFCC[0] ^ 0xff; + tmpWrFCC[5] = tmpWrFCC[1] ^ 0xff; + tmpWrFCC[6] = tmpWrFCC[2] ^ 0xff; + tmpWrFCC[7] = tmpWrFCC[3] ^ 0xff; + EEPROM_WrMulByte(EE_FCC,tmpWrFCC); + delay_ms(20); + + //璧嬪煎墿浣欏閲=鏂扮殑婊″厖瀹归噺*SOC + bmsMem.rcc = fcc/100 * bmsMem.soc; + rcc_Ah = fcc_Ah * bmsMem.soc / 100; + oldrcc_Ah = rcc_Ah; + } + } + + /*璁＄畻瀹炴椂SOC=鍓╀綑瀹归噺/婊″厖瀹归噺*/ + if(bmsMem.rcc > fcc/100 * 99) //>99% + { + //鑻OC宸茬粡鏄100%锛屼笉浼氫笅璋 + if(bmsMem.soc >= 100) + { + bmsMem.soc = 100; + } + //鑻OC姝ゅ墠<=99锛岄攣瀹99% + else + { + bmsMem.soc = 99; + } + } + else //0%~99% + { + //濡傛灉鍓╀綑瀹归噺鐨勫皬鏁伴儴鍒嗚嚦灏戞湁0.1Ah锛宻oc+1 + if( (bmsMem.rcc%(fcc/100)) /360000 != 0) //鍙栫簿搴0.1%浣滀负鍒ゆ柇鏍囧噯 360000mAS = 0.1*1000*3600 = 0.1Ah + { + bmsMem.soc = bmsMem.rcc/(fcc/100)+1; + } + else + { + bmsMem.soc = bmsMem.rcc/(fcc/100); + } + } + + /*鑻ユ弧瓒崇壒娈婃潯浠讹紝鐩存帴鏀瑰姩SOC鍊硷紝娉ㄦ剰鍓╀綑瀹归噺淇濇寔涓嶅彉*/ + //read bSTATUS1 ov bit 婊″厖鏍″噯 + //婊″厖鏉′欢1锛氬崟浣撹繃鍘 + if( ((paraMem.soc100_methods & 0x01) != 0) && ((bmsMem.bStatus1 & 0x0001) != 0) && (bmsMem.packVoltage > packcheck_OV)) //鍙戠敓杩囧帇淇濇姢(浼氬叧MOS)//甯︽诲帇鍒ゆ柇(鏍规嵁涓叉暟鍙樺寲) + { + bmsMem.soc = 100; + fcc_fullFlag = 1; + + //濡傛灉涓嶅湪绛夊緟鏍″噯婊″厖瀹归噺锛屽悓鏃舵洿鏂皉cc=fcc + if(fcc_CaliStartFlag == 0) + { + bmsMem.rcc = fcc; + } + } + //婊″厖鏉′欢2锛氭讳綋杩囧帇 + else if( ((paraMem.soc100_methods & 0x02) != 0) && ((bmsMem.bStatus1 & 0x0100) != 0)) //鍙戠敓鎬讳綋杩囧帇淇濇姢(浼氬叧MOS) + { + bmsMem.soc = 100; + fcc_fullFlag = 1; + + //濡傛灉涓嶅湪绛夊緟鏍″噯婊″厖瀹归噺锛屽悓鏃舵洿鏂皉cc=fcc + if(fcc_CaliStartFlag == 0) + { + bmsMem.rcc = fcc; + + //涓嶈鍏ュ惊鐜鏁 + rcc_Ah = bmsMem.rcc/3600/1000; + oldrcc_Ah = rcc_Ah; + } + } + //婊″厖鏉′欢3锛氶嗗彉鍣ㄩ檺鍘57.6V+2A灏忕數娴 + else if( ((paraMem.soc100_methods & 0x04) != 0) && (bmsMem.packVoltage >= bmsMem.inverter_chgVolLimit*100) && (bmsMem.packCurrent >= 100) && (bmsMem.packCurrent <= 2000)) //鐢靛帇澶т簬閫嗗彉鍣ㄥ厖鐢甸檺鍘嬪硷紝鐢垫祦灏忎簬2A(閫嗗彉鍣ㄤ細閫愭笎鍋滄鍏呯數锛屼絾BMS涓嶅叧闂璏OS) + { + bmsMem.soc = 100; + fcc_fullFlag = 1; + + //濡傛灉涓嶅湪绛夊緟鏍″噯婊″厖瀹归噺锛屽悓鏃舵洿鏂皉cc=fcc + if(fcc_CaliStartFlag == 0) + { + bmsMem.rcc = fcc; + + //涓嶈鍏ュ惊鐜鏁 + rcc_Ah = bmsMem.rcc/3600/1000; + oldrcc_Ah = rcc_Ah; + } + } + //婊″厖鏉′欢4锛氭弧鍏呯數鍘56V+5A鎴鐢垫祦 + else if( ((paraMem.soc100_methods & 0x08) != 0) && ((bmsMem.bStatus1 & 0x0800) != 0)) //鍙戠敓婊″厖鍋滄鍏呯數(浼氬叧MOS) + { + bmsMem.soc = 100; + fcc_fullFlag = 1; + + //濡傛灉涓嶅湪绛夊緟鏍″噯婊″厖瀹归噺锛屽悓鏃舵洿鏂皉cc=fcc + if(fcc_CaliStartFlag == 0) + { + bmsMem.rcc = fcc; + + //涓嶈鍏ュ惊鐜鏁 + rcc_Ah = bmsMem.rcc/3600/1000; + oldrcc_Ah = rcc_Ah; + } + } + else + { + fcc_fullFlag = 0; + } + + //read bFLAG1 ov bit 婊℃斁鏍″噯 + if((bmsMem.bStatus1 & 0x0002) !=0) //鍙戠敓鍗曚綋娆犲帇淇濇姢 + { + if(bmsMem.packVoltage < packcheck_UV) //鎬诲帇鍒ゆ柇(鏍规嵁涓叉暟鍙樺寲) + { + bmsMem.soc = 0; + bmsMem.rcc = 0; + } + } + else if((bmsMem.bStatus1 & 0x0200) !=0) //鍙戠敓鎬讳綋娆犲帇淇濇姢 + { + bmsMem.soc = 0; + bmsMem.rcc = 0; + } + else + { + if(bDSGING) //杩樻鍦ㄦ斁鐢典絾rcc宸茬粡涓0锛屼細涓婅皟涓鐐瑰閲忥紝鐩村埌婊¤冻婊℃斁鏉′欢 + { + if(bmsMem.soc == 0) //鑻OC鍘熸槸0%锛屾斁鐢典笉鐮村潖璇ュ + { + bmsMem.rcc = 0; + } + else if((bmsMem.rcc <= 360000) || (bmsMem.rcc > 0xFFE00000)) //鍥犳敼涓烘棤绗﹀彿锛岄渶娓呴浂鐨勮礋鏁拌寖鍥磋-1~-2,097,151锛岀數娴佸煎湪2000A鑼冨洿鍐呯殕鍙帴鍙楋紝涓嶅嚭閿欑殑姝ｆ暟鑼冨洿涓0~4,292,870,144,澶х害1192Ah + { + bmsMem.soc = 1; + bmsMem.rcc = 360000 * 5; //澧炲姞0.5Ah鐢ㄤ簬缁х画涓嬮檷 //鍦0.1Ah~0.5Ah涔嬮棿缁存寔(soc=1%) + } + } + } + + + //15%鏍″噯锛氬綋鎬荤數鍘嬪皬浜庣瓑浜50V鏃讹紝鑻OC澶т簬15%鍒欐牎鍑嗗埌15% //4.28澧炲姞鐢垫祦鏉′欢鏀剧數15A浠ヤ笅 + if((bmsMem.packVoltage <= (50000/16*bmsMem.ucCellNum)) && (bmsMem.soc > 15) && (bmsMem.packCurrent > (-15000)) && (bmsMem.packCurrent < 100)) + { + Cali_Soc_Flag = 1; + } + else + { + Cali_Soc_Flag = 0; + } + + + if((paraMem.cali_min_disable & 0x8000) == 0) //鍏佽鍋氭弧鍏呭閲忔牎鍑 + { + Cali_FCC_Moni(); //鐢垫祦鍜孲OC婊¤冻鏉′欢鍚庢墽琛 + } + else //涓嶅厑璁 + { + //鍦ㄤ互涓婃墍鏈夋墽琛屽畬鍚庯紝鏈夐棶棰樺啀绾犳涓 + if(bmsMem.soc == 100) //SOC宸茬粡鍒颁簡100%锛屾鏃秗cc鏈楂樹笉瓒呰繃fcc + { + if(bmsMem.rcc > fcc) + { + bmsMem.rcc = fcc; + } + } + else //SOC浣庝簬100%锛屾鏃秗cc鏈楂樹笉瓒呰繃fcc*99% + { + if(bmsMem.rcc > fcc/100 * 99) + { + if(bCHGING) //姝ｅ湪鍏呯數 + { + bmsMem.rcc = fcc - (fcc/1000*15); + } + else + { + bmsMem.rcc = fcc/100 * 99; + } + } + } + } + + + bmsMem.can_soc = bmsMem.soc; //sum of all packs + bmsMem.can_soh = bmsMem.soh; //sum of all packs + + + /*鏁版嵁瀛樺叆EEPROM*/ + //SOC write to eeprom + if(bmsMem.soc != oldsoc) + { + oldsoc = bmsMem.soc; + tempWr[0] = bmsMem.soc; + EEPROM_WrMulByte(EE_SOC,&tempWr[0]); + delay_ms(5); + } + + //绱Н瀹归噺 write to eeprom + rcc_Ah = bmsMem.rcc/3600/1000; + if(rcc_Ah > oldrcc_Ah) //褰撳閲忎笂娑ㄤ簡1Ah + { + cumuliCapacity += 10*(rcc_Ah - oldrcc_Ah); //灏嗗鍔犻儴鍒嗘斁鍏ョ疮绉閲忎腑 + oldrcc_Ah = rcc_Ah; + + //鑾峰緱杩涜寰幆娆℃暟璁＄畻鐨勫崟浣嶅閲(姝ゅ涓嶅彲涓0) + if(paraMem.sohcali_transCent != 0) + { + capacity = 10*ncc_Ah * paraMem.sohcali_transCent/100; + } + else + { + capacity = 10*ncc_Ah * 90/100; //榛樿90% + } + //璁＄畻寰幆娆℃暟 + if(cumuliCapacity >= capacity) //褰撶疮绉閲忚秴鍑烘诲閲忕殑90%,澧炲姞寰幆娆℃暟 + { + bmsMem.cycleCount += cumuliCapacity / capacity; + cumuliCapacity = cumuliCapacity % capacity; + } + //淇濆瓨褰撳墠(鎴栧弬涓庤繃寰幆娆℃暟璁＄畻鍚庣殑)绱Н瀹归噺 + tempWr[0] = (cumuliCapacity >> 8) & 0xff; + tempWr[1] = (cumuliCapacity >> 0) & 0xff; + EEPROM_WrMulByte(EE_CUMULI,tempWr); + delay_ms(5); + } + else + { + oldrcc_Ah = rcc_Ah; //瑕佸悓姝ュ鍑 + } + + //寰幆娆℃暟 write to eeprom + if(bmsMem.cycleCount != oldcyc) + { + oldcyc = bmsMem.cycleCount; + tempWr[0] = (bmsMem.cycleCount >> 8) & 0xff; + tempWr[1] = (bmsMem.cycleCount >> 0) & 0xff; + EEPROM_WrMulByte(EE_CYCLE,tempWr); + delay_ms(5); + + if(cumuliCapClear_flag == 1) + { + cumuliCapClear_flag = 0; + //淇濆瓨绱Н瀹归噺涓0 + cumuliCapacity = 0; + tempWr[0] = (cumuliCapacity >> 8) & 0xff; + tempWr[1] = (cumuliCapacity >> 0) & 0xff; + EEPROM_WrMulByte(EE_CUMULI,tempWr); + delay_ms(5); + } + } + + + /*閫氳繃寰幆娆℃暟璁＄畻SOH*/ + if(bmsMem.cycleCount <= paraMem.sohcali_stopTime) + { + if(bmsMem.cycleCount <= paraMem.sohcali_startTime) + { + bmsMem.soh = 100; //缁存寔100% + } + else + { + uint16_t cent = (paraMem.sohcali_stopTime-1 - paraMem.sohcali_startTime) / (99-paraMem.sohcali_minSOH); //姣1%瀵瑰簲鐨勫ぇ姒傛鏁 + + bmsMem.soh = 99 - (bmsMem.cycleCount - paraMem.sohcali_startTime) / cent; //浠99%寮濮嬩笅闄 + } + } + else //瓒呰繃灏辩淮鎸佹渶澶ф鏁 + { + bmsMem.cycleCount = paraMem.sohcali_stopTime; + bmsMem.soh = paraMem.sohcali_minSOH; + } + + //Wh鐗堝睆骞曢渶瑕 + bmsMem.can_cumuliCap = cumuliCapacity/10; //sum of all packs + bmsMem.can_cycleCnt = bmsMem.cycleCount; //sum of all packs + + + //杩囧帇鎶ヨ鐨勬樉绀哄垽鏂細鍦ㄦ帴杩戞弧鐢垫椂,鍙戠敓[杩囧帇淇濇姢],鍒欎笉浼氬洜姝や寒鐏睆骞曚篃涓嶆樉绀鸿繃鍘 + #if Key_PressLong + if((ON_confirm_flg != 0) && (RST_confirm_flg != 1) && (OFF_confirm_flg != 1)) + #endif + { + if(((bmsMem.bStatus1 & 0x0001) != 0) || ((bmsMem.bStatus1 & 0x0100) != 0)) //鍗曚綋杩囧帇+鎬讳綋杩囧帇 + { + if(bmsMem.soc<99) //鍦ㄦ甯稿伐浣滄椂锛屽彂鐢焄杩囧帇淇濇姢]锛屾甯告樉绀 + { + bAlarmFlag = 1; + if(sleep_flag == 0) LED_ALARM_On(); + else LED_ALARM_Off(); + } + else + { + //鑻ュ嚭鐜板叾浠栨姤璀︼紝灏变笉鎭㈠鍘熺姸(-鍗曚綋杩囧帇-鎬讳綋杩囧帇+鎬ュ仠) + if( ((bmsMem.bStatus1 & 0x067e) == 0) && ((bmsMem.bStatus2 & 0x00ff) == 0) && ((bmsMem.bStatus3 & 0x0008) == 0) && ((bmsMem.temperaStatus & 0x0f7f) == 0) ) + { + bAlarmFlag = 0; + bAlarmFlagOld = 0; + LED_ALARM_Off(); + } + } + } + } + + + //led鎸囩ず + #if Key_PressLong + if((ON_confirm_flg != 0) && (RST_confirm_flg != 1) && (OFF_confirm_flg != 1)) + #endif + { + if(sleep_flag == 0) + { + if(bmsMem.soc<5) + { + LED1_Off(); + LED2_Off(); + LED3_Off(); + LED4_Off(); + } + else if(bmsMem.soc>=5 && bmsMem.soc<30) + { + LED1_On(); + LED2_Off(); + LED3_Off(); + LED4_Off(); + } + else if(bmsMem.soc>=30 && bmsMem.soc<60) + { + LED1_On(); + LED2_On(); + LED3_Off(); + LED4_Off(); + } + else if(bmsMem.soc>=60 && bmsMem.soc<90) + { + LED1_On(); + LED2_On(); + LED3_On(); + LED4_Off(); + } + else + { + LED1_On(); + LED2_On(); + LED3_On(); + LED4_On(); + } + } + else //浼戠湢妯″紡涓嬬伅鍏ㄧ伃 + { + LED1_Off(); + LED2_Off(); + LED3_Off(); + LED4_Off(); + } + } +} + +#define CALI_SOC_CNT 12000 //2*60*100涓10ms=2鍒嗛挓 +void Cali_SOC_Moni(void) +{ + if(Cali_Soc_Flag == 1) + { + CaliSocMoniCount--; + if(CaliSocMoniCount == 0) + { + CaliSocMoniCount = CALI_SOC_CNT; + if(bmsMem.soc>15) + { + bmsMem.soc = 15; + bmsMem.rcc = fcc/100 * bmsMem.soc; + } + } + } + else + { + CaliSocMoniCount = CALI_SOC_CNT; + } +} + +//鏍″噯婊″厖瀹归噺鐨勬墽琛岃繃绋 +//鑻ュ垰寮濮嬪厖鐢垫椂锛孲OC=0/1%锛屽垯鍏佽鏍″噯婊″厖瀹归噺锛屽悓姝ヨ鏃12h瓒呰繃鍒欎笉鍐嶆牎鍑 +//鑻12h鍐咃紝婊¤冻浜嗘弧鍏呭垽瀹氱殑浠讳竴鏉′欢鑰屼娇SOC=100%锛屽湪鍩烘湰鍋滄鍏呯數(鐢垫祦<2A)鍚庢墽琛屽閲忔牎鍑嗭細璧嬪糩婊″厖瀹归噺]=姝ゆ椂鐨勫墿浣欏閲忓苟淇濆瓨銆 +//鑻12h澶栵紝婊¤冻浜嗘弧鍏呭垽瀹氱殑浠讳竴鏉′欢鑰屼娇SOC=100%锛屼笉浼氬彉鍔ㄦ弧鍏呭閲忋 +//鍓╀綑瀹归噺鍙互涓鐩村闀匡紝鑻ヨ秴杩囦簡鍘熸潵鐨勬弧鍏呭閲忥紝SOC淇濇寔100%涓嶅啀澧為暱銆 +void Cali_FCC_Moni(void) +{ + //娌℃湁鍦ㄨ鏃 + if(fcc_CaliStartFlag == 0) + { + if((bmsMem.packCurrent >= 2000) && (bmsMem.soc <= 1)) //鍏呯數(澶т簬2A)鏃讹紝鑻ユ鏃禨OC澶勪簬浣庣偣锛岃繘琛屾牎鍑嗘诲閲忕殑鍊掕鏃 + { + fcc_CaliStartFlag = 1; + + //鏇存柊璧峰鐐癸紝濡傛灉鏅舵尟姝ｅ父灏辨妸鏍囧織鍜岃捣濮嬬偣閮藉啓鍏EPROM + if(LSEErrFlag!=1) + { + uint8_t time[4]; + + fcc_Calitimecount=RTC_GetCounter(); + + //鍐欏叆璧峰鏃堕棿 + time[0] = fcc_Calitimecount>>24 & 0xff; + time[1] = fcc_Calitimecount>>16 & 0xff; + time[2] = fcc_Calitimecount>>8 & 0xff; + time[3] = fcc_Calitimecount>>0 & 0xff; + + EEPROM_WrMulByte(EE_FCC_TIME,time); + delay_ms(5); + } + else + { + fcc_Cali_Moni_Count = FCCCALI_MON_CNT; + } + } + } + //姝ゅ墠宸茬粡鍚姩璁℃椂 + else + { + if((bmsMem.packCurrent < 2000) && (fcc_fullFlag == 1)) //涓嶅湪鍏呯數鏃讹紝鑻ュ凡婊¤冻婊″厖鏉′欢锛岃鏄庢鏃剁殑鍓╀綑瀹归噺鏄綋鍓嶇殑婊″厖瀹归噺鍊 + { + //璧嬪兼弧鍏呭閲=鍓╀綑瀹归噺 + fcc = bmsMem.rcc; + fcc_Ah = bmsMem.rcc / 3600000; + tmpWrFCC[0] = (fcc>>24) & 0xff; + tmpWrFCC[1] = (fcc>>16) & 0xff; + tmpWrFCC[2] = (fcc>> 8) & 0xff; + tmpWrFCC[3] = (fcc>> 0) & 0xff; + tmpWrFCC[4] = tmpWrFCC[0] ^ 0xff; + tmpWrFCC[5] = tmpWrFCC[1] ^ 0xff; + tmpWrFCC[6] = tmpWrFCC[2] ^ 0xff; + tmpWrFCC[7] = tmpWrFCC[3] ^ 0xff; + EEPROM_WrMulByte(EE_FCC,tmpWrFCC); + delay_ms(20); + + fcc_CaliStartFlag = 0; //娓呴浂 + if(LSEErrFlag == 0) + { + EEPROM_WrMulByte(EE_FCC_TIME,ClearEE); + delay_ms(5); + } + } + } +} + diff --git a/MOUDLE/H7690C.c b/MOUDLE/H7690C.c new file mode 100644 index 0000000..2cd1e0e --- /dev/null +++ b/MOUDLE/H7690C.c @@ -0,0 +1,3646 @@ +/** + ****************************************************************************** + * @file H7690C.c + * @author + * @version + * @date + * @brief + ****************************************************************************** + * @attention + * + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" +#include "global.h" +#include "rtc.h" +#include "string.h" +#include +#include +#include + + +#if LTE_Conn +//延时 +#define ERR_timeEnd1 30/2 //持续ERR后重启计数，因遇到ERR会2s后再发报文，所以/2 30s +#define ERR_timeEnd2 60/2 //持续ERR后重启计数，因遇到ERR会2s后再发报文，所以/2 1min +#define RST_timeEnd 60*4 //指令持续无有效回复，执行4G重启 4min +#define RSSI13_timeEnd 60*4 //开机发现信号弱，等待恢复 4min +#define RSSI99_timeEnd 10 //开机可能出现rssi=99，等待恢复 10s +#define RSSI_timeEnd 30*4 //正常通信发现信号弱，等待恢复 4min +#define timed_Delay 51 //定时上报[属性]的延时 + +//通用定义 +#define PIN_LTE_RST GPIO_Pin_12 //PC12 4G复位 +#define PIN_LTE_CTRL GPIO_Pin_2 //PD2 输出几秒高电平，用以启动4G模块 + +#define LTE_UART UART4 +#define LTE_Send LTE_printf + +#define LTE_MON_CNT 6000 //6000*10ms = 60s +#define LTE_OTA_CNT 6000*3 //6000*3*10ms = 60*3s +#define LTE_ONLINE_CNT 6000*16 //持续未上线的倒计时数 +#define LTE_TIMEDPUB_CNT 6000*2 //持续未发送属性的倒计时数 + +#define LTE_RX_BUF_LEN 1000 //接收的最大长度 +#define LTE_TX_BUF_LEN 2000 //发送的最大长度 +#define LTEMEM_LEN 2000 //定时发送数据的缓存长度 + +char LTE_Rx_Buf[LTE_RX_BUF_LEN]; +char LTE_Tx_Buf[LTE_TX_BUF_LEN]; + +uint16_t LTE_Rx_BufIndex; +uint16_t LTE_Moni_Count; //无通信时重启4G +uint32_t LTE_Moni_Count2; //长时间不上线重启4G +uint32_t property_pub_count; //上线后长时间未上报属性重启MQTT服务 + +char LTEMem_Buf[LTEMEM_LEN]; //定时发送数据的缓冲区，也方便计算长度 +uint16_t LTEMem_len; //所存内容长度，在发送给4G模块前计算出 + + +//状态标志 +uint8_t LTE_Onflag; //4G模块开机成功标志 (暂无作用但保留) +uint8_t LTE_SIMflag; //4G模块识别到SIM卡标志 (暂无作用但保留) +uint8_t LTE_Networkflag; //4G模块联网功能开关状态 (暂无作用但保留) +uint8_t LTE_Onlineflag; //4G模块联网标志 0:未联网 1:已联网 0xAA:错误，尝试重新联网解决 + +uint8_t LTE_PinRST_Flag; //4G模块需通过引脚重启标志 1:关闭4G 2:开启4G +uint8_t LTE_NoMoni_Flag; //4G模块不应该继续定时监控的标志 在正常联网但SN号不存在时启用 + +//4G模块开机等待 +#define OpenTime 10 +#define CloseTime 5 +uint8_t LTE_WarmDelay; //4G模块开机等待时间 + +//4G模块回复ERR后发送等待 +#define ResendTime 2 +uint8_t LTE_ResendDelay; //4G模块对当前指令回复ERR，重新发送等待倒计时 + +//4G模块无回复后发送等待(实际时间要加上原有1s/0.25s) +#define WaitRxTime 2 +uint8_t LTE_WaitRxDelay; //4G模块对当前指令无回复，重新发送等待倒计时 +uint8_t LTE_WaitRxFlg; //有发送指令，需要在无回复时执行等待的标志 + + +//4G通信错误计数 +uint16_t LTE_ErrCnt; //未连接MQTT前发生的错误计数(持续发生就重启) +uint16_t MQTT_ErrCnt; //在连接/已连接MQTT后发生的错误计数(先尝试重启MQTT，还是不行就检查网络) +uint8_t Order_RevCount; //在接收MQTT下发指令的延时，用于防范“有头无尾”一直存在 +uint8_t CSQ_ErrCnt; //在正常流程中,发送CSQ或CGREG收到Err的错误计数(持续发送就重启) + +//4G异常状态:繁忙 +uint8_t LTE_BUSY_cnt; //当4G模块卡死，问什么都回复BUSY的计数(持续发送就重启) + + +//重置状态指令 +//1.重启模块 +uint8_t CRESET_flag; //重启 0xAA:多次重启失败 +uint8_t CRESET_step; //执行步骤 0~2:退出MQTT服务 3:重启 +uint8_t CRESET_count; //执行次数 连续5次后执行引脚重启并清零。成功连接云平台后释放 + +//2.重启MQTT +uint8_t MQTT_RST_flag; //重启MQTT服务 0xAA:多次重启失败 +uint8_t MQTT_RST_step; //执行步骤 0~2:退出MQTT服务 +uint8_t MQTT_RST_count; //执行次数 连续5次后执行CGREG。成功连接云平台后释放 + +//3.重新联网 +uint8_t CFUN_flag; //重新联网 0xAA:多次重启失败 +uint8_t CFUN_step; //执行步骤 0:断网 1:联网 2:查询联网状态 +uint8_t CFUN_count; //执行次数 连续5次后执行CGREG。联网正常后释放 +uint8_t searching_cnt; //当CGREG=2，说明正在找网，等待3s再次询问，持续30s无变化，再次尝试重联网 + + +//常规指令 +//1.查询信号质量 +uint8_t CSQ_flag; //执行查询信号质量指令的标志 +char str_rssi[5]; //信号强度对应字符串 +uint8_t LTE_rssi; //信号强度 +uint16_t rssiLow_count; //若信号强度过低，持续发生就重启 +uint16_t rssi99_count; //若信号值异常，给4G等待一点时间 + +//2.查询是否正常联网 +uint8_t CGREG_flag; //执行查询网络注册状态指令的标志 +uint16_t CGREG_count; //此时rssi正常，但网络注册状态有误，持续发生就重启 +uint8_t LTE_register;//联网状态 + +//3.连接MQTT服务器 +uint8_t MQTT_START_flag; //执行连接MQTT服务器的标志 +uint8_t MQTT_START_step; //执行步骤 +uint8_t MQTT_START_count;//出现"+MQTTSTART:1"，尝试重启MQTT解决。超过5次转为查询CGREG +uint8_t LTE_LINK_flag; //已连接到服务器的标志 + +//4.连接成功后，获取当前SIM卡的CICCID +uint8_t CICCID_flag; //执行获取CICCID的标志 +char ICCID[21]; //CICCID字符串 + +//5.连接成功后，订阅主题 +uint8_t SUBTOPIC_flag; //执行订阅主题的标志 +uint8_t SUBTOPIC_step; //执行步骤 +uint8_t LTE_UNSUB_Flag;//需要先取消绑定的标志 + +//6.连接并订阅成功后，请求[校时] +uint8_t CALITIME_flag; //执行请求[校时]的标志 +uint8_t CALITIME_step; //执行步骤 + +//final.已连上平台，走正常通信流程 +uint8_t MQTT_READY_flag; //MQTT执行正常通信流程的标志 +uint8_t MQTT_timed_count; //定时上报[属性]的倒计时 +uint8_t LTE_status; //执行内容 +uint8_t LTE_step; //执行步骤 + +//正常使用中.超时保护 +uint8_t check_sub_count; //查询订阅的超时保护 + + +// 【正常通信流程】 +// 0.询问LBS数据(1) +// 1.询问信号质量(1) +// 2.定时上报[属性](5) +// 3.等待60s定时(n) +// 4.检查是否正常订阅主题(1) +//0xA0.若存在事件，立即上报所有[事件](5) +//0xA1.立刻回复写[服务](5) +//0xA2.立刻回复写[属性](5) +//0xA3.立刻回复读[属性](5) +#define ask_lbs 0 +#define ask_rssi 1 +#define send_timed 2 +#define wait_timed 3 +#define check_sub 4 +#define event_pub 0xA0 +#define srvc_pub 0xA1 +#define setPara_pub 0xA2 +#define getPara_pub 0xA3 + +// 【具体步骤】 +// 0_0 [询问LBS数据] 0:获取4G基站数据 +// 1_1~2 [询问信号质量] 1:获取信号质量 2:获取联网状态 +// 2_6~10 [定时上报属性] 6:主题长度 7:主题内容 8:属性长度 9:属性内容 10:确认上传 +// 3_11 [60s定时] 11:定时等待 +// 4_12~22 [检查] 12:检查是否订阅主题 +// 13~14:重新订阅[校时]主题 +// 15~16:重新订阅[服务]主题 +// 17~18:重新订阅写[属性]主题 +// 19~20:重新订阅读[属性]主题 +// 21~22:重新订阅OTA升级信息主题 +//0xA0_101~105[立即上报事件] 101:主题长度 102:主题内容 103:属性长度 104:属性内容 105:确认上传 +//0xA1_106~110[立即回复写服务] 106:主题长度 107:主题内容 108:属性长度 109:属性内容 110:确认上传 +//0xA2_111~115[立即回复写属性] 111:主题长度 112:主题内容 113:属性长度 114:属性内容 115:确认上传 +//0xA3_116~120[立即回复读属性] 116:主题长度 117:主题内容 118:属性长度 119:属性内容 120:确认上传 +#define ask_lbs_step1 0 +#define ask_rssi_step1 1 +#define ask_rssi_step2 2 +#define send_timed_step1 6 +#define send_timed_step2 7 +#define send_timed_step3 8 +#define send_timed_step4 9 +#define send_timed_step5 10 +#define wait_timed_step1 11 +#define check_sub_step01 12 +#define check_sub_step11 13 +#define check_sub_step12 14 +#define check_sub_step21 15 +#define check_sub_step22 16 +#define check_sub_step31 17 +#define check_sub_step32 18 +#define check_sub_step41 19 +#define check_sub_step42 20 +#define check_sub_step51 21 +#define check_sub_step52 22 + +#define event_pub_step1 101 +#define event_pub_step2 102 +#define event_pub_step3 103 +#define event_pub_step4 104 +#define event_pub_step5 105 + +#define srvc_pub_step1 106 +#define srvc_pub_step2 107 +#define srvc_pub_step3 108 +#define srvc_pub_step4 109 +#define srvc_pub_step5 110 + +#define setPara_pub_step1 111 +#define setPara_pub_step2 112 +#define setPara_pub_step3 113 +#define setPara_pub_step4 114 +#define setPara_pub_step5 115 + +#define getPara_pub_step1 116 +#define getPara_pub_step2 117 +#define getPara_pub_step3 118 +#define getPara_pub_step4 119 +#define getPara_pub_step5 120 + + +//【OTA升级】 +//0xAA.OTA升级完成后，上线回复升级完成 +#define ota_fine_pub 0xAA + +#define ota_fine_pub_step1 221 +#define ota_fine_pub_step2 222 +#define ota_fine_pub_step3 223 +#define ota_fine_pub_step4 224 +#define ota_fine_pub_step5 225 + + +//功能参数 +char timestamp_str[10+2]; //时间校准值字符串 +uint32_t timestamp; //时间校准值 + +uint8_t LBS_Dataflag; //LBS数据标志 1:已获取到经纬度信息 0xAA:暂无数据 +char LBS_initial_str[60]; //原始数据字符串 +double LBS_lon,LBS_lat; //经纬度值(GCJ-02) +double WGS84_lon,WGS84_lat; //经纬度值(WGS84) + +//特殊：事件、服务、写属性、读属性 +#define INCIDENT_PUB_MAX 5 //一次性最多上传5条事件 +uint8_t incident_pub_count; +const char* incident_str; +uint8_t incident_len; +uint32_t incident_time; + +char ID_str[22]; //写[服务]/写[属性]/读[属性]时，操作设备的ID，最多20位 +uint8_t ID_len; + +uint8_t incident_reply_count; //回复操作计数 一共5步，若执行10次都没完成，可能是中间哪里卡住了，从头再开始发 +uint8_t putSrvc_reply_count; //回复操作计数 +uint8_t setPara_reply_count; //回复操作计数 +uint8_t getPara_reply_count; //回复操作计数 +uint8_t otaFine_reply_count; //回复操作计数【OTA升级】 + +char Str_Buf[30]; //在合并字符串和数据到一起的缓冲区 + +uint8_t putSrvc_reply_namelen; //写服务的名称长度 +uint8_t putSrvc_reply_strlen; //写服务的内容长度 + +uint16_t setPara_reply_sumlen; //写属性的内容长度，{}内的总长度(4G需提前计算) +uint16_t getPara_reply_sumlen; //读属性的内容长度，{}内的总长度(4G需提前计算) + +uint8_t LTE_sleep_flag; //4G也进入休眠标志 +uint8_t pre_sleep_flag; //休眠前置标志 1:收到休眠指令后回复(暂无) 2:准备上报启动休眠事件 3:正在上报启动休眠事件 4:上报属性 5:退出MQTT服务后跳转休眠 0xA0:退出休眠后要上报退出休眠事件 0xAA:执行上报退出休眠事件 +uint8_t pre_sleep_waitCnt; //休眠前置操作等待计数，若持续1min未执行结束，也直接跳到休眠最后一步：关闭4G + +uint32_t sleepOn_time; //启动休眠时间 +uint32_t sleepOff_time; //退出休眠时间 + +/**写服务变量名**/ +#define srvc_ForceOn "\"PutForceOn\"" +#define srvc_CurCali "\"PutCurCali\"" + +/**读写参数结构体**/ +//不需要写入Flash变量的序号 +#define Idx_WrFlash 4 //<4 +//type!=0 但写入需额外执行动作的序号 +#define Idx_Protocol 0 +#define Idx_CYC 2 +//type!=0 但读出需额外执行动作的序号 +#define Idx_Protocol 0 +//type!=0 但读出需另外赋值的序号 +#define Idx_SOC 1 +#define Idx_Capacity 3 +//type==0 需单独配置变量的序号 +#define Idx_COV_Vol 12 +#define Idx_COVR_Vol 13 +#define Idx_CUV_Vol 14 +#define Idx_CUVR_Vol 15 +#define Idx_SC_Cur 16 +#define Idx_SC_Delay 17 + +uint16_t Wr_Temp; + +//建立参数信息结构体 +typedef struct +{ + const char *name; //参数字符串，如 "Protocol" + void *data; //指向存储变量的指针，如 &protocol + int16_t min; //最小值（用于类型1~4的写范围判断，无符号的转int16_t存储）[不用时置0] + int16_t max; //最大值（用于类型1~4的写范围判断，无符号的转int16_t存储）[不用时置0] + uint8_t bitIdx;//位索引，如bit15（用于类型5）[不用时置0] + uint8_t type; //变量类型(0=不管 1=uint8_t 2=uint16_t 3=int8_t 4=int16_t 5=bool允许 6=bool禁止) + +} ParamInfo; + +//建立参数表，用于setPara和getPara +const ParamInfo paramTable[] = +{ + //系统参数 0~3 + {"\"Protocol\"", &protocol, 0, ProtocolSum, 0, 1}, //u8 //不写Flash //需写入EEPROM + {"\"SOC\"", &bmsMem.write_Soc, 0, 100, 0, 1}, //u8 //不写Flash //会在别处自动存EE //读出取bmsMem.soc + {"\"CYC\"", &bmsMem.cycleCount, 0, 0xFFFF, 0, 2}, //u16 //不写Flash //会在别处自动存EE //若超过paraMem.sohcali_stopTime，会在别处修正 //需置cumuliCapClear_flag=1 + {"\"Capacity\"", &bmsMem.write_Capacity, 1, 1000, 0, 2}, //u16 //不写Flash //会在别处自动存EE //读出取fcc_Ah + + //逆变器相关 4~7 + {"\"InverterChgVol\"", &bmsMem.inverter_chgVolLimit, 1, 600, 0, 2}, //u16 + {"\"InverterDsgVol\"", &bmsMem.inverter_dsgVolLimit, 1, 600, 0, 2}, //u16 + {"\"InverterChgCur\"", &bmsMem.inverter_chgCurLimit, 1, 6000, 0, 2}, //u16 + {"\"InverterDsgCur\"", &bmsMem.inverter_dsgCurLimit, 1, 6000, 0, 2}, //u16 + + //电压相关 8~15 + {"\"POV_Vol\"", ¶Mem.pack_ovv, 1, 600, 0, 2}, //u16 + {"\"POVR_Vol\"", ¶Mem.pack_ovrv, 1, 600, 0, 2}, //u16 + {"\"PUV_Vol\"", ¶Mem.pack_uvv, 1, 600, 0, 2}, //u16 + {"\"PUVR_Vol\"", ¶Mem.pack_uvrv, 1, 600, 0, 2}, //u16 + {"\"COV_Vol\"", &Wr_Temp, 20, 5000, 0, 0}, //更新后，在别处写入真正参数 //读出取cell_OV + {"\"COVR_Vol\"", &Wr_Temp, 20, 5000, 0, 0}, //更新后，在别处写入真正参数 //读出取cell_OVR + {"\"CUV_Vol\"", &Wr_Temp, 20, 5000, 0, 0}, //更新后，在别处写入真正参数 //读出取cell_UV + {"\"CUVR_Vol\"", &Wr_Temp, 20, 5000, 0, 0}, //更新后，在别处写入真正参数 //读出取cell_UVR + + //电流相关 16~21 + {"\"SC_Cur\"", &Wr_Temp, 0, 15, 0, 0}, //更新后，在别处写入真正参数 + {"\"SC_Delay\"", &Wr_Temp, 0, 15, 0, 0}, //更新后，在别处写入真正参数 + {"\"OCC_Cur\"", &bmsMem.mcu_occ, 1, 255, 0, 1}, //u8 + {"\"OCC_Delay\"", &bmsMem.mcu_occ_t, 1, 255, 0, 1}, //u8 + {"\"OCD1_Cur\"", &bmsMem.mcu_ocd, 1, 255, 0, 1}, //u8 + {"\"OCD1_Delay\"", &bmsMem.mcu_ocd_t, 1, 255, 0, 1}, //u8 + + //温度相关 22~29 + {"\"OTC_Temp\"", &bmsMem.mcu_otc, -45, 115, 0, 3}, //i8 + {"\"OTCR_Temp\"", &bmsMem.mcu_otcr, -45, 115, 0, 3}, //i8 + {"\"OTD_Temp\"", &bmsMem.mcu_otd, -45, 115, 0, 3}, //i8 + {"\"OTDR_Temp\"", &bmsMem.mcu_otdr, -45, 115, 0, 3}, //i8 + {"\"UTC_Temp\"", &bmsMem.mcu_utc, -45, 115, 0, 3}, //i8 + {"\"UTCR_Temp\"", &bmsMem.mcu_utcr, -45, 115, 0, 3}, //i8 + {"\"UTD_Temp\"", &bmsMem.mcu_utd, -45, 115, 0, 3}, //i8 + {"\"UTDR_Temp\"", &bmsMem.mcu_utdr, -45, 115, 0, 3}, //i8 +}; + +////用于填充写[属性]的数组 +////pm: 0表示正数，1表示负数 +//void Record_setPara(const char* name, uint16_t data, uint8_t pm) +//{ +// //if(setPara_reply_num >= SETPARA_SUM) return; +// +// setPara_reply_name[setPara_reply_num] = name; //名称 +// setPara_reply_temp[setPara_reply_num] = data; //数值 +// setPara_reply_pm[setPara_reply_num] = pm; //正负 +// +// setPara_reply_num++; +// setPara_reply_sumlen += strlen(name)+2+uint_str_len(data); //名称长度(包括"")+数值长度+外面固定长度 +// +// if(pm == 1) +// { +// setPara_reply_sumlen += 1; //负号 +// } +//} + +////用于填充读[属性]的数组 +////pm: 0表示正数，1表示负数 +//void Record_getPara(const char* name, uint16_t data, uint8_t pm) +//{ +// //if(getPara_reply_num >= GETPARA_SUM) return; +// +// getPara_reply_name[getPara_reply_num] = name; //名称 +// getPara_reply_temp[getPara_reply_num] = data; //数值 +// getPara_reply_pm[getPara_reply_num] = pm; //正负 +// +// getPara_reply_num++; +// getPara_reply_sumlen += strlen(name)+2+uint_str_len(data); //名称长度(包括"")+数值长度+外面固定长度 +// +// if(pm == 1) +// { +// getPara_reply_sumlen += 1; //负号 +// } +//} + + +//LTE专用的printf函数 +int LTE_printf(const char *fmt, ...) +{ + va_list args; + va_start(args, fmt); + int len = vsnprintf(LTE_Tx_Buf, sizeof(LTE_Tx_Buf), fmt, args); + va_end(args); + + for(int i = 0; i < len; i++) + { + while(!(UART4->SR & USART_SR_TXE)); // 等待发送完成 + UART4->DR = LTE_Tx_Buf[i]; + } + + LTE_WaitRxFlg = 1; //有发送，可延时等待接收 + + return len; +} + +//填充上报[属性]的缓冲区，并计算长度 +void LTE_CombineStr(const char *fmt, ...) +{ + //更新内容 + va_list args; + va_start(args, fmt); + int len = vsnprintf(LTEMem_Buf + LTEMem_len, sizeof(LTEMem_Buf) - LTEMem_len, fmt, args); + va_end(args); + + //更新长度 + if(len > 0) + { + LTEMem_len += len; + } +} + +//相关引脚初始化 +void LTE_4G_IO_Init(void) +{ + //初始化引脚 + GPIO_InitTypeDef GPIO_InitStructure; + + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC , ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD , ENABLE); + + GPIO_InitStructure.GPIO_Pin = PIN_LTE_RST; //4G复位控制引脚 + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOC, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = PIN_LTE_CTRL; //4G开机控制引脚 + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOD, &GPIO_InitStructure); + + GPIO_ResetBits(GPIOC, PIN_LTE_RST); //4G复位控制脚，默认置低，关闭状态 + GPIO_ResetBits(GPIOD, PIN_LTE_CTRL); //4G开机控制脚，默认置低，之后通过高电平脉冲开/关 +} + +//开机 +//脉冲宽度100ms(范围100ms~2s)，开机时间(UART)0.8s +void LTE_4G_Open(void) +{ + GPIO_ResetBits(GPIOD, PIN_LTE_CTRL); + delay_ms(50); + GPIO_SetBits(GPIOD, PIN_LTE_CTRL); + delay_ms(200); + GPIO_ResetBits(GPIOD, PIN_LTE_CTRL); + delay_ms(50); + + LTE_WarmDelay = OpenTime; //开机等待 +} + +//关机 +//脉冲宽度2s(范围>1.5s)，关机时间(UART)2.1s +void LTE_4G_Close(void) +{ + GPIO_ResetBits(GPIOD, PIN_LTE_CTRL); + delay_ms(50); + GPIO_SetBits(GPIOD, PIN_LTE_CTRL); + delay_ms(2000); + GPIO_ResetBits(GPIOD, PIN_LTE_CTRL); + delay_ms(50); + + LTE_WarmDelay = CloseTime; //关机等待 +} + +//复位 +//脉冲宽度100ms(范围100ms~2s)，建议仅在紧急情况使用 +void LTE_4G_Reset(void) +{ +// GPIO_ResetBits(GPIOC, PIN_LTE_RST); +// delay_ms(50); +// GPIO_SetBits(GPIOC, PIN_LTE_RST); +// delay_ms(200); +// GPIO_ResetBits(GPIOC, PIN_LTE_RST); +// delay_ms(50); +// +// LTE_WarmDelay = OpenTime; //开机等待 + + //采用更温和的手段，引脚重启 + LTE_PinRST_Flag = 1; +} + +//清空标志 +void LTE_4G_ClearFlg(void) +{ + //状态标志 + LTE_Onflag = 0; + LTE_SIMflag = 0; + LTE_Networkflag = 0; + LTE_Onlineflag = 0; + //LTE_PinRST_Flag = 0; + LTE_NoMoni_Flag = 0; + + //错误计数 + LTE_ErrCnt = 0; + MQTT_ErrCnt = 0; + + //重置状态标志 + CRESET_flag = 0; + CRESET_step = 0; + MQTT_RST_flag = 0; + MQTT_RST_step = 0; + CFUN_flag = 0; + CFUN_step = 0; + + //常规指令 + //1.信号质量 + CSQ_flag = 0; + LTE_rssi = 0; + + //2.联网 + CGREG_flag = 0; + + //3.连接MQTT + MQTT_START_flag = 0; + MQTT_START_step = 0; + LTE_LINK_flag = 0; + + //4.SIM卡的CICCID + CICCID_flag = 0; + + //5.订阅主题 + SUBTOPIC_flag = 0; + SUBTOPIC_step = 0; + + //6.请求[校时] + CALITIME_flag = 0; + CALITIME_step = 0; + + //final.正常通信流程 + MQTT_READY_flag = 0; + MQTT_timed_count = 0; + LTE_status = 0; + LTE_step = 0; + + //服务、写属性、读属性 + putSrvc_reply_flg = 0; + setPara_reply_flg = 0; + getPara_reply_flg = 0; + + //OTA升级 + LTE_OTA_Flag = 0; +} + +//清空接收缓冲区 +void LTE_4G_ClearBuf(void) +{ + LTE_Rx_BufIndex = 0; + memset(LTE_Rx_Buf, 0, LTE_RX_BUF_LEN); +} + +//初始化通讯 +void LTE_4G_Init(void) +{ + LTE_4G_ClearFlg(); + LTE_4G_ClearBuf(); + + LTE_Moni_Count = LTE_MON_CNT; + uf_UART4_Init(115200); +} + +//持续1min未收到任何数据，初始化串口和4G模块 +void LTE_TIM_Moni(void) +{ + if((LTE_WarmDelay == 0) && (LTE_sleep_flag == 0) && (LTE_NoMoni_Flag == 0)) //开机等待不算+休眠不算+联网正常但无SN号不算+等待上报不算 + { + LTE_Moni_Count--; + if(LTE_Moni_Count == 0) //持续无回复重启4G + { + LTE_4G_Init(); + LTE_PinRST_Flag = 1; + } + + if(MQTT_READY_flag == 0) + { + LTE_Moni_Count2++; + if(LTE_Moni_Count2 > LTE_ONLINE_CNT) //长期未上线重启4G + { + LTE_Moni_Count2 = 0; + + LTE_4G_Init(); + LTE_PinRST_Flag = 1; + } + } + else + { + LTE_Moni_Count2 = 0; + } + } + + if(((LTE_LINK_flag == 1) || (MQTT_READY_flag == 1)) && (LTE_OTA_Flag == 0)) //已连接/已上线，不在OTA，但一直未上报属性 + { + property_pub_count++; + if(property_pub_count > LTE_TIMEDPUB_CNT) + { + property_pub_count = 0; + + MQTT_RST_flag = 1; //重启MQTT + MQTT_RST_step = 0; + + LTE_LINK_flag = 0; //已连接标志清零 + MQTT_START_flag = 0; + MQTT_READY_flag = 0; + MQTT_timed_count = 0; + + LTE_OTA_Flag = 0; //OTA升级标志清零 + } + } + else + { + property_pub_count = 0; + } +} + +//下发[时钟同步]报文的处理 +void LTE_4G_SUB_NTP(void) +{ + if(strstr(LTE_Rx_Buf, "\"timestamp\"")) // + { + uint8_t len = 0; //字符串长度 + + //获取时间戳 + //{"timestamp":1753858296} + const char* timeKey = "\"timestamp\":"; + char* timeStart = strstr(LTE_Rx_Buf, timeKey); timeStart += strlen(timeKey); + char* timeEnd = strchr(timeStart, '}'); + len = timeEnd - timeStart; + strncpy(timestamp_str, timeStart, len); + timestamp_str[len] = '\0'; + sscanf(timestamp_str, "%u", ×tamp); + + if(LSEErrFlag == 0) //晶振正常时 + { + //刷新休眠时间 + RTC_UpdateFlag = 1; + + RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE); //使能PWR和BKP外设时钟 + PWR_BackupAccessCmd(ENABLE); //使能RTC和后备寄存器访问 + RTC_SetCounter(timestamp); //设置RTC计数器的值 + + RTC_WaitForLastTask(); //等待最近一次对RTC寄存器的写操作完成 + RTC_Get(); + } + } +} + +//分析4G基站定位 +void LTE_4G_GET_LBS(void) +{ + if(strstr(LTE_Rx_Buf, "+CLBS:")) + { + //获取原始数据字符串 + uint8_t len = 0; //字符串长度 + + //+CLBS: 0,31.191534,120.600830,550 + const char* dataKey = "+CLBS: "; + char* dataStart = strstr(LTE_Rx_Buf, dataKey); dataStart += strlen(dataKey); + char* dataEnd = strchr(dataStart, '\r'); + len = dataEnd - dataStart; + strncpy(LBS_initial_str, dataStart, len); + LBS_initial_str[len] = '\0'; + + //分析数据 + uint16_t temp1,temp2; + + //纬度格式：31.191534 (-180.000000~180.000000) + //经度格式：120.600830 (-90.000000~90.000000) + sscanf(LBS_initial_str, "%hu,%lf,%lf,%hu", &temp1, &LBS_lat, &LBS_lon, &temp2); + + //转换到国际通用坐标系 + gcj02_to_wgs84(LBS_lon, LBS_lat, &WGS84_lon, &WGS84_lat); + + //可以上传基站定位 + LBS_Dataflag = 1; + } +} + +//用于填充定时上报[属性]的数组 +void LTE_Record_pubData(void) +{ + //清空数组 + LTEMem_len = 0; + memset(LTEMem_Buf, 0, LTEMEM_LEN); + + //内容更新 + LTE_CombineStr("{"); //1 + LTE_CombineStr("\"BmsSN\":\"%s\",", BMS_SN); //5+4 + 9+2 + LTE_CombineStr("\"PackSN\":\"%s\",", PACK_SN); //6+4 + 15+2 + LTE_CombineStr("\"SysTime\":\"%u\",", timecount); //7+4 + 10+2 + if(ScreenVersion[0] == 0) + { + LTE_CombineStr("\"FirmwareVersion\":\"%s\",", FirmwareVersion); //15+4 + 11+2 + LTE_CombineStr("\"HardwareVersion\":\"%s\",", HardwareVersion); //15+4 + 5+2 + } + else + { + LTE_CombineStr("\"FirmwareVersion\":\"%s\",", FirmwareVersion); //15+4 + 11+2 + LTE_CombineStr("\"HardwareVersion\":\"%s\",", HardwareVersion); //15+4 + 5+2 + LTE_CombineStr("\"ScreenVersion\":\"%s\",", ScreenVersion); //13+4 + 5+2 + } + + //采集数据 + LTE_CombineStr("\"PackVol\":%u,", bmsMem.packVoltage); //7+4 + 10 + LTE_CombineStr("\"PackCur\":%d,", bmsMem.packCurrent); //7+4 + 10 + LTE_CombineStr("\"VolMax\":%d,", cellVoltageMax); //6+4 + 5 + LTE_CombineStr("\"VolMin\":%d,", cellVoltageMin); //6+4 + 5 + LTE_CombineStr("\"VolMaxIndex\":%u,", bmsMem.cellVoltageMaxIndex); //11+4 + 2 + LTE_CombineStr("\"VolMinIndex\":%u,", bmsMem.cellVoltageMinIndex); //11+4 + 2 + LTE_CombineStr("\"FCC\":%u,", bmsMem.ncc/3600); //3+4 + 7 + LTE_CombineStr("\"RCC\":%u,", bmsMem.rcc/3600); //3+4 + 7 + LTE_CombineStr("\"SOC\":%u,", bmsMem.soc); //3+4 + 3 + LTE_CombineStr("\"SOH\":%u,", bmsMem.soh); //3+4 + 3 + LTE_CombineStr("\"CYC\":%u,", bmsMem.cycleCount); //3+4 + 5 + //电压 + LTE_CombineStr("\"CellVol1\":%d,", cellVol[0]); //8+4 + 5 + LTE_CombineStr("\"CellVol2\":%d,", cellVol[1]); //8+4 + 5 + LTE_CombineStr("\"CellVol3\":%d,", cellVol[2]); //8+4 + 5 + LTE_CombineStr("\"CellVol4\":%d,", cellVol[3]); //8+4 + 5 + LTE_CombineStr("\"CellVol5\":%d,", cellVol[4]); //8+4 + 5 + LTE_CombineStr("\"CellVol6\":%d,", cellVol[5]); //8+4 + 5 + LTE_CombineStr("\"CellVol7\":%d,", cellVol[6]); //8+4 + 5 + LTE_CombineStr("\"CellVol8\":%d,", cellVol[7]); //8+4 + 5 + LTE_CombineStr("\"CellVol9\":%d,", cellVol[8]); //8+4 + 5 + LTE_CombineStr("\"CellVol10\":%d,", cellVol[9]); //9+4 + 5 + LTE_CombineStr("\"CellVol11\":%d,", cellVol[10]); //9+4 + 5 + LTE_CombineStr("\"CellVol12\":%d,", cellVol[11]); //9+4 + 5 + LTE_CombineStr("\"CellVol13\":%d,", cellVol[12]); //9+4 + 5 + LTE_CombineStr("\"CellVol14\":%d,", cellVol[13]); //9+4 + 5 + LTE_CombineStr("\"CellVol15\":%d,", cellVol[14]); //9+4 + 5 + LTE_CombineStr("\"CellVol16\":%d,", cellVol[15]); //9+4 + 5 + LTE_CombineStr("\"CellVol17\":%d,", cellVol[16]); //9+4 + 5 + LTE_CombineStr("\"CellVol18\":%d,", cellVol[17]); //9+4 + 5 + LTE_CombineStr("\"CellVol19\":%d,", cellVol[18]); //9+4 + 5 + LTE_CombineStr("\"CellVol20\":%d,", cellVol[19]); //9+4 + 5 + //温度 + LTE_CombineStr("\"MosT1\":%.1f,", (float)(bmsMem.afe_T1-2731)/10); //5+4 + 5 + LTE_CombineStr("\"MosT2\":%.1f,", (float)(bmsMem.afe_T2-2731)/10); //5+4 + 5 + LTE_CombineStr("\"AmbientT\":%.1f,", (float)(bmsMem.afe_T3-2731)/10); //8+4 + 5 + LTE_CombineStr("\"BatteryT1\":%.1f,", (float)(bmsMem.mcu_T1-2731)/10); //9+4 + 5 + LTE_CombineStr("\"BatteryT2\":%.1f,", (float)(bmsMem.mcu_T2-2731)/10); //9+4 + 5 + LTE_CombineStr("\"BatteryT3\":%.1f,", (float)(bmsMem.mcu_T3-2731)/10); //9+4 + 5 + LTE_CombineStr("\"BatteryT4\":%.1f,", (float)(bmsMem.mcu_T4-2731)/10); //9+4 + 5 + + //常见状态 + LTE_CombineStr("\"ChargeStatus\":%s,", Status[ChargeStatus]); //12+4 + 5 + LTE_CombineStr("\"DischargeStatus\":%s,", Status[DischargeStatus]); //15+4 + 5 + LTE_CombineStr("\"PreChargeStatus\":%s,", Status[PreChargeStatus]); //15+4 + 5 + LTE_CombineStr("\"ChgMosStatus\":%s,", Status[ChgMosStatus]); //12+4 + 5 + LTE_CombineStr("\"DsgMosStatus\":%s,", Status[DsgMosStatus]); //12+4 + 5 + LTE_CombineStr("\"PchgMosStatus\":%s,", Status[PchgMosStatus]); //13+4 + 5 + if(ChgLimitStatus) LTE_CombineStr("\"ChgLimitStatus\":true,"); //14+4 + 5 + //特殊状态 + if(LockOCC) LTE_CombineStr("\"LockOCC\":true,"); //7+4 + 5 + if(LockOCD1) LTE_CombineStr("\"LockOCD1\":true,"); //8+4 + 5 + if(LockOCD2) LTE_CombineStr("\"LockOCD2\":true,"); //8+4 + 5 + if(LockSP) LTE_CombineStr("\"LockSP\":true,"); //6+4 + 5 + if(LockSC) LTE_CombineStr("\"LockSC\":true,"); //6+4 + 5 + if(ChgMosFault) LTE_CombineStr("\"ChgMosFault\":true,"); //11+4 + 5 + if(DsgMosFault) LTE_CombineStr("\"DsgMosFault\":true,"); //11+4 + 5 + if(DOStatus) LTE_CombineStr("\"DOStatus\":true,"); //8+4 + 5 + if(ForceOffUV) LTE_CombineStr("\"ForceOffUV\":true,"); //10+4 + 5 + //保护 + if(PackOV) LTE_CombineStr("\"PackOV\":true,"); //6+4 + 5 + if(PackUV) LTE_CombineStr("\"PackUV\":true,"); //6+4 + 5 + if(CellOV) LTE_CombineStr("\"CellOV\":true,"); //6+4 + 5 + if(CellUV) LTE_CombineStr("\"CellUV\":true,"); //6+4 + 5 + if(PF) LTE_CombineStr("\"PF\":true,"); //2+4 + 5 + if(L0V) LTE_CombineStr("\"L0V\":true,"); //3+4 + 5 + if(OCC) LTE_CombineStr("\"OCC\":true,"); //3+4 + 5 + if(OCD1) LTE_CombineStr("\"OCD1\":true,"); //4+4 + 5 + if(OCD2) LTE_CombineStr("\"OCD2\":true,"); //4+4 + 5 + if(SP) LTE_CombineStr("\"SP\":true,"); //2+4 + 5 + if(SC) LTE_CombineStr("\"SC\":true,"); //2+4 + 5 + if(McuOTC) LTE_CombineStr("\"McuOTC\":true,"); //6+4 + 5 + if(McuOTD) LTE_CombineStr("\"McuOTD\":true,"); //6+4 + 5 + if(McuUTC) LTE_CombineStr("\"McuUTC\":true,"); //6+4 + 5 + if(McuUTD) LTE_CombineStr("\"McuUTD\":true,"); //6+4 + 5 + if(AmbientOTC) LTE_CombineStr("\"AmbientOTC\":true,"); //10+4 + 5 + if(AmbientOTD) LTE_CombineStr("\"AmbientOTD\":true,"); //10+4 + 5 + if(AmbientUTC) LTE_CombineStr("\"AmbientUTC\":true,"); //10+4 + 5 + if(AmbientUTD) LTE_CombineStr("\"AmbientUTD\":true,"); //10+4 + 5 + if(MosOTC) LTE_CombineStr("\"MosOTC\":true,"); //6+4 + 5 + if(MosOTD) LTE_CombineStr("\"MosOTD\":true,"); //6+4 + 5 + //if(MosUTC) LTE_CombineStr("\"MosUTC\":true,"); //6+4 + 5 + //if(MosUTD) LTE_CombineStr("\"MosUTD\":true,"); //6+4 + 5 + //报警 + if(PackOVWarning) LTE_CombineStr("\"PackOVWarning\":true,"); //6+4 + 5 + if(PackUVWarning) LTE_CombineStr("\"PackUVWarning\":true,"); //6+4 + 5 + if(CellOVWarning) LTE_CombineStr("\"CellOVWarning\":true,"); //6+4 + 5 + if(CellUVWarning) LTE_CombineStr("\"CellUVWarning\":true,"); //6+4 + 5 + if(OCCWarning) LTE_CombineStr("\"OCCWarning\":true,"); //3+4 + 5 + if(OCDWarning) LTE_CombineStr("\"OCDWarning\":true,"); //3+4 + 5 + if(McuOTCWarning) LTE_CombineStr("\"McuOTCWarning\":true,"); //6+7+4 + 5 + if(McuOTDWarning) LTE_CombineStr("\"McuOTDWarning\":true,"); //6+7+4 + 5 + if(McuUTCWarning) LTE_CombineStr("\"McuUTCWarning\":true,"); //6+7+4 + 5 + if(McuUTDWarning) LTE_CombineStr("\"McuUTDWarning\":true,"); //6+7+4 + 5 + if(AmbientOTCWarning) LTE_CombineStr("\"AmbientOTCWarning\":true,"); //10+7+4 + 5 + if(AmbientOTDWarning) LTE_CombineStr("\"AmbientOTDWarning\":true,"); //10+7+4 + 5 + if(AmbientUTCWarning) LTE_CombineStr("\"AmbientUTCWarning\":true,"); //10+7+4 + 5 + if(AmbientUTDWarning) LTE_CombineStr("\"AmbientUTDWarning\":true,"); //10+7+4 + 5 + if(MosOTCWarning) LTE_CombineStr("\"MosOTCWarning\":true,"); //6+7+4 + 5 + if(MosOTDWarning) LTE_CombineStr("\"MosOTDWarning\":true,"); //6+7+4 + 5 + //if(MosUTCWarning) LTE_CombineStr("\"MosUTCWarning\":true,"); //6+7+4 + 5 + //if(MosUTDWarning) LTE_CombineStr("\"MosUTDWarning\":true,"); //6+7+4 + 5 + + //4G信息 + LTE_CombineStr("\"ICCID\":\"%s\",", ICCID); //5+4 + 20+2 + if(LBS_Dataflag == 1) + { + LTE_CombineStr("\"rssi\":%u,", LTE_rssi); //4+4 + 2+2 + LTE_CombineStr("\"coords\":\"%.7f,%.7f\"}", WGS84_lon, WGS84_lat); //6+4 + 21+3 + } + else + { + LTE_CombineStr("\"rssi\":%u}", LTE_rssi); //4+4 + 2+2 + //LTE_CombineStr("\"coords\":null}"); //0 + } + + LTE_CombineStr("\r\n"); //+2 最后有换行 +} + +//下发[服务]报文的处理 +//(只填充回复相关不执行) +void LTE_4G_SUB_Service(void) +{ + if(strstr(LTE_Rx_Buf, "\"request_id\"")) //有ID格式 + { + //将ID内容拓印到数组 + //{"request_id":"123124sdf",…} + ID_len = GetID(LTE_Rx_Buf, ID_str); + if(ID_len == 0) + { + putSrvc_reply_flg = 0xBB; //设备拒绝执行 + return; + } + + //识别指令 + if(strstr(LTE_Rx_Buf, srvc_ForceOn)) //控制欠压强制复位 + { + putSrvc_reply_flg = 1; + putSrvc_reply_namestr = srvc_ForceOn; + putSrvc_reply_namelen = 10+2; + + //更新控制位 + if(strstr(LTE_Rx_Buf, "\"open\"")) + { + //当前总体和单体欠压的报警/保护位都置0 + bmsMem.bStatus1 &= ~0x0202; + bmsMem.bStatus3 &= ~0x0A00; + //状态置1，更新计时起点 + bmsMem.balanceStatus |= 0x0020; + if(LSEErrFlag!=1) + { + uvofftimecount = RTC_GetCounter(); + uvofftime = 300; + } + else + { + uvoff_Moni_Count = UVOff_MON_CNT; + } + + putSrvc_reply_str = "\"open\""; + putSrvc_reply_strlen = 4+2; + } + else if(strstr(LTE_Rx_Buf, "\"close\"")) + { + bmsMem.balanceStatus &= 0xffdf; + + putSrvc_reply_str = "\"close\""; + putSrvc_reply_strlen = 5+2; + } + else //未收到正确内容 + { + putSrvc_reply_flg = 0xBB; //设备拒绝执行 + } + } + else if(strstr(LTE_Rx_Buf, srvc_CurCali)) //控制执行电流校准 + { + putSrvc_reply_flg = 1; + putSrvc_reply_namestr = srvc_CurCali; + putSrvc_reply_namelen = 10+2; + + if(strstr(LTE_Rx_Buf, "\"zero\"")) + { + cali.cmdZero = 2; //执行零点校准标志置2，与上位机做区分 + + putSrvc_reply_str = "\"zero\""; + putSrvc_reply_strlen = 4+2; + } + else if(strstr(LTE_Rx_Buf, "\"gain\"") && strstr(LTE_Rx_Buf, "\"GainCur\"")) + { + char gain_str[10]; //1~2147483647 + uint8_t len = 0; //字符串长度 + uint32_t temp; //无符号过程量 + + //获取校准电流值 + len = GetStr("\"GainCur\":", '}', '}', LTE_Rx_Buf, gain_str); + sscanf(gain_str, "%u", &temp); + + //符合范围的放入 + if((temp>=1) && (temp<=0x7FFFFFFF) && (len > 0)) + { + //执行增益校准标志置2，与上位机做区分 + cali.cmdGain = 2; + cali.current = temp; + + memset(Str_Buf, 0, 30); //清空 + sprintf(Str_Buf, "\"gain\",\"GainCur\":%u", temp); //填充 + putSrvc_reply_str = Str_Buf; + putSrvc_reply_strlen = 17+len; + } + else + { + putSrvc_reply_flg = 0xBB; //设备拒绝执行 + } + } + else + { + putSrvc_reply_flg = 0xBB; //设备拒绝执行 + } + } + else + { + putSrvc_reply_flg = 0xAA; //设备无该属性 + } + } + else //无request_id + { + putSrvc_reply_flg = 0xBB; //设备拒绝执行 + } +} + +//用于填充写[属性]的数组 +//pm: 0表示正数，1表示负数 +void Record_setPara(const char* name, uint16_t data, uint8_t pm) +{ + //if(setPara_reply_num >= SETPARA_SUM) return; + + setPara_reply_name[setPara_reply_num] = name; //名称 + setPara_reply_temp[setPara_reply_num] = data; //数值 + setPara_reply_pm[setPara_reply_num] = pm; //正负 + + setPara_reply_num++; + setPara_reply_sumlen += strlen(name)+2+uint_str_len(data); //名称长度(包括"")+数值长度+外面固定长度 + + if(pm == 1) + { + setPara_reply_sumlen += 1; //负号 + } +} + +//下发写[属性]报文的处理 +//{"request_id":"123124sdf","Protocol":1} +void LTE_4G_SUB_SETPARA(void) +{ + if(strstr(LTE_Rx_Buf, "\"request_id\"")) //有ID格式 + { + //将ID内容拓印到数组 + //{"request_id":"123124sdf","POV_Vol":250} + ID_len = GetID(LTE_Rx_Buf, ID_str); + if(ID_len == 0) + { + setPara_reply_flg = 0xBB; //设备拒绝执行 + return; + } + + if(strstr(LTE_Rx_Buf, "\"data\":{") && strstr(LTE_Rx_Buf, "}}")) + { + uint8_t i; + + char para_str[6]; //0~65535 或 -32768~32767 + uint16_t len = 0; //字符串长度 + uint16_t temp; //无符号过程量 + int16_t temp_T; //有符号过程量 + uint8_t FlashStore_Flag = 0; //更新到Flash的标志 + + //获取原始数据，包括'{''}' + const char* paramsKey = "\"data\":"; + char* paramsStart = strstr(LTE_Rx_Buf, paramsKey); paramsStart += strlen(paramsKey); + char* paramsEnd = strchr(paramsStart, '}'); + len = paramsEnd - paramsStart; + if(len > sizeof(params_str)-2) //防溢出 + { + len = sizeof(params_str)-2; + } + strncpy(params_str, paramsStart, len); + params_str[len] = '}'; + params_str[len+1] = '\0'; + + + //识别存在的参数，并给予对应值 + setPara_reply_num = 0; + setPara_reply_sumlen = 0; + + //遍历参数表 + for(i=0; i= 3) && (paramTable[i].type <= 4)) //3.4 + { + sscanf(para_str, "%hd", &temp_T); + } + + //根据类型进行不同判断 + if(paramTable[i].type == 0) //需单独配置 + { + //符合范围的放入 + if((temp >= paramTable[i].min) && (temp <= paramTable[i].max) && (len > 0)) + { + if(i == Idx_COV_Vol) //"\"COV_Vol\"" + { + temp = temp/5; + bmsMem.ee_ovt_ldrt_ovh &= 0xfc;//~0x03 + bmsMem.ee_ovt_ldrt_ovh += (temp & 0x0300) >>8; + bmsMem.ee_ovl = temp & 0x00ff; + + temp = temp*5; + cell_OV = temp; + + //记录回复信息 + Record_setPara(paramTable[i].name, temp, 0); + } + else if(i == Idx_COVR_Vol) //"\"COVR_Vol\"" + { + temp = temp/5; + bmsMem.ee_uvt_ovrh &= 0xfc;//~0x03 + bmsMem.ee_uvt_ovrh += (temp & 0x0300) >>8; + bmsMem.ee_ovrl = temp & 0x00ff; + + temp = temp*5; + cell_OVR = temp; + + //记录回复信息 + Record_setPara(paramTable[i].name, temp, 0); + } + else if(i == Idx_CUV_Vol) //"\"CUV_Vol\"" + { + temp = temp/20; + bmsMem.ee_uv = temp; + + temp = temp*20; + cell_UV = temp; + + //记录回复信息 + Record_setPara(paramTable[i].name, temp, 0); + } + else if(i == Idx_CUVR_Vol) //"\"CUVR_Vol\"" + { + temp = temp/20; + bmsMem.ee_uvr = temp; + + temp = temp*20; + cell_UVR = temp; + + //记录回复信息 + Record_setPara(paramTable[i].name, temp, 0); + } + else if(i == Idx_SC_Cur) //"\"SC_Cur\"" + { + uint16_t scv,scc; + + bmsMem.ee_scv_sct &= 0x0F; + bmsMem.ee_scv_sct |= (temp & 0x0f)<<4; + + if(temp == 0x0B) + { + scv = 400; + } + else + { + scv = 50 + 30 * temp; + } + scc = scv * AFE_Multiple; + + //记录额外的回复信息 + Record_setPara(paramTable[i].name, temp, 0); + Record_setPara("\"SC_Current\"", scc, 0); + } + else if(i == Idx_SC_Delay) //"\"SC_Delay\"" + { + uint16_t sct; + + bmsMem.ee_scv_sct &= 0xF0; + bmsMem.ee_scv_sct |= (temp & 0x0f); + + sct = 0 + 64 * temp; + + //记录额外的回复信息 + Record_setPara(paramTable[i].name, temp, 0); + Record_setPara("\"SC_DelayTime\"", sct, 0); + } + } + else + { + setPara_reply_flg = 0xBB; //设备拒绝执行 + } + } + else if(paramTable[i].type == 1) //u8 + { + //符合范围的放入 + if((temp >= (uint8_t)paramTable[i].min) && (temp <= (uint8_t)paramTable[i].max) && (len > 0)) + { + //赋值 + *(uint8_t*)paramTable[i].data = (uint8_t)temp; + + //记录回复信息 + Record_setPara(paramTable[i].name, temp, 0); + + //额外操作 + if(i == Idx_Protocol) //"\"Protocol\"" + { + EEPROM_WrMulByte(EE_PROTOCOL,&protocol); + delay_ms(5); + uf_CAN1_Init();//CAN的波特率更新 + //SCR_DispProcotol(); //屏幕显示更新 + + protocol_reply_flg = 1; + protocol_reply_index = setPara_reply_num-1; //在记录回复信息时+1了 + if(protocol == 0) + { + //"ProtocolName":null + setPara_reply_sumlen += 12+4+4; + } + else + { + //"ProtocolName":"Sol-Ark" + setPara_reply_sumlen += 12+6+strlen(protocolStrings[protocol-1]); + } + } + } + else + { + setPara_reply_flg = 0xBB; //设备拒绝执行 + } + } + else if(paramTable[i].type == 2) //u16 + { + //符合范围的放入 + if((temp >= (uint16_t)paramTable[i].min) && (temp <= (uint16_t)paramTable[i].max) && (len > 0)) + { + //赋值 + *(uint16_t*)paramTable[i].data = temp; + + //记录回复信息 + Record_setPara(paramTable[i].name, temp, 0); + + //额外操作 + if(i == Idx_CYC) //"\"CYC\"" + { + cumuliCapClear_flag = 1; //保存时清空累积容量 + } + } + else + { + setPara_reply_flg = 0xBB; //设备拒绝执行 + } + } + else if(paramTable[i].type == 3) //i8 + { + //符合范围的放入 + if((temp_T >= paramTable[i].min) && (temp_T <= paramTable[i].max) && (len > 0)) + { + //记录回复信息 + if(temp_T >= 0) + { + //赋值 + *(int8_t*)paramTable[i].data = (int8_t)temp_T; + + //记录回复信息 + Record_setPara(paramTable[i].name, temp_T, 0); //正 + } + else + { + //赋值 + *(int8_t*)paramTable[i].data = (int8_t)temp_T; + + //记录回复信息 + Record_setPara(paramTable[i].name, -temp_T, 1); //负 + } + } + else + { + setPara_reply_flg = 0xBB; //设备拒绝执行 + } + } + + //除了个别参数外，都要执行写Flash更新 + if((i >= Idx_WrFlash) && (setPara_reply_flg < 0xAA)) + { + FlashStore_Flag = 1; + } + } + } + + if(setPara_reply_num > 0) + { + setPara_reply_flg = 1; //正常回复 + setPara_reply_sumlen -= 1; //最后不是逗号，长度去掉 + } + else if(setPara_reply_flg != 0xBB) //无任何符合的值&不是因为参数不符合范围 + { + setPara_reply_flg = 0xAA; //设备无所有属性 + } + + //某个参数更新，要同步更新Flash + if(FlashStore_Flag != 0) + { + //计算CRC校验值 + static uint8_t temp[AFE_MCU_LEN]; + memcpy(temp, &bmsMem.ee_sconf1, AFE_MCU_LEN); + + bmsMem.ee_tr = CRC8_Cal(&temp[0],25); + bmsMem.mcu_crc = CRC8_Cal(&temp[26], 13); + + //bmsMem中数据更新到FLASH A区和B区和AFE EEPORM + if((MEMORY_UpdateFlash(FLASH_DATA_A_BASE) == 0) && (MEMORY_UpdateFlash(FLASH_DATA_B_BASE) == 0)) + { + staPack.bits.flashUpdate= 0; + if(MEMORY_UpdateAFE() ==0) //更新AFE的EEPROM + { + staPack.bits.eepromUpdate = 0; + } + else + { + staPack.bits.eepromUpdate = 1; + } + } + else + { + staPack.bits.flashUpdate = 1; + } + bmsMem.packStatus = staPack.byte; + } + } + else + { + setPara_reply_flg = 0xBB; //设备拒绝执行 + } + } + else //无request_id + { + setPara_reply_flg = 0xBB; //设备拒绝执行 + } +} + +//用于填充读[属性]的数组 +//pm: 0表示正数，1表示负数 +void Record_getPara(const char* name, uint16_t data, uint8_t pm) +{ + //if(getPara_reply_num >= GETPARA_SUM) return; + + getPara_reply_name[getPara_reply_num] = name; //名称 + getPara_reply_temp[getPara_reply_num] = data; //数值 + getPara_reply_pm[getPara_reply_num] = pm; //正负 + + getPara_reply_num++; + getPara_reply_sumlen += strlen(name)+2+uint_str_len(data); //名称长度(包括"")+数值长度+外面固定长度 + + if(pm == 1) + { + getPara_reply_sumlen += 1; //负号 + } +} + +//下发读[属性]报文的处理 +//{"request_id":"123124sdf","params":{"Protocol"}} +void LTE_4G_SUB_GETPARA(void) +{ + if(strstr(LTE_Rx_Buf, "\"request_id\"")) //有ID格式 + { + //将ID内容拓印到数组 + //{"request_id":"123124sdf","params":{"POV_Vol","COV_Vol"}} + ID_len = GetID(LTE_Rx_Buf, ID_str); + if(ID_len == 0) + { + getPara_reply_flg = 0xBB; //设备拒绝执行 + return; + } + + if(strstr(LTE_Rx_Buf, "\"params\":[") && strstr(LTE_Rx_Buf, "]}")) + { + uint8_t i; + + uint16_t len = 0; //字符串长度 + uint16_t temp; //无符号过程量 + int16_t temp_T; //有符号过程量 + + //获取原始数据 + const char* paramsKey = "\"params\":["; + char* paramsStart = strstr(LTE_Rx_Buf, paramsKey); paramsStart += strlen(paramsKey); + char* paramsEnd = strchr(paramsStart, ']'); + len = paramsEnd - paramsStart; + if(len > sizeof(params_str)-1) //防溢出 + { + len = sizeof(params_str)-1; + } + strncpy(params_str, paramsStart, len); + params_str[len] = '\0'; + + //识别存在的参数，并给予对应值 + getPara_reply_num = 0; + getPara_reply_sumlen = 0; + + //遍历参数表 + for(i=0; i>4; + if(temp == 0x0B) + { + scv = 400; + } + else + { + scv = 50 + 30 * temp; + } + scc = scv * AFE_Multiple; + + //记录回复信息 + Record_getPara(paramTable[i].name, temp, 0); + Record_getPara("\"SC_Current\"", scc, 0); + } + else if(i == Idx_SC_Delay) + { + //赋值 + uint16_t sct; + + temp = bmsMem.ee_scv_sct & 0x0F; + sct = 0 + 64 * temp; + + //记录回复信息 + Record_getPara(paramTable[i].name, temp, 0); + Record_getPara("\"SC_DelayTime\"", sct, 0); + } + } + else if(paramTable[i].type == 1) //u8 + { + //赋值 + if(i == Idx_SOC) + { + temp = bmsMem.soc; + } + else + { + temp = *(uint8_t*)paramTable[i].data; + } + + //记录回复信息 + Record_getPara(paramTable[i].name, temp, 0); + + //额外回复 + if(i == Idx_Protocol) + { + protocol_reply_flg = 1; + protocol_reply_index = getPara_reply_num-1; //在记录回复信息时+1了 + if(protocol == 0) + { + //"ProtocolName":null + getPara_reply_sumlen += 12+4+4; + } + else + { + //"ProtocolName":"Sol-Ark" + getPara_reply_sumlen += 12+6+strlen(protocolStrings[protocol-1]); + } + } + } + else if(paramTable[i].type == 2) //u16 + { + //赋值 + if(i == Idx_Capacity) + { + temp = fcc_Ah; + } + else + { + temp = *(uint16_t*)paramTable[i].data; + } + + //记录回复信息 + Record_getPara(paramTable[i].name, temp, 0); + } + else if(paramTable[i].type == 3) //i8 + { + //赋值 + temp_T = *(int8_t*)paramTable[i].data; + + //记录回复信息 + if(temp_T >= 0) + { + Record_getPara(paramTable[i].name, temp_T, 0); //正 + } + else + { + Record_getPara(paramTable[i].name, -temp_T, 1); //负 + } + } + } + } + + if(getPara_reply_num > 0) + { + getPara_reply_flg = 1; //回复 + getPara_reply_sumlen -= 1; //最后不是逗号，长度去掉 + } + else //无任何符合的值 + { + getPara_reply_flg = 0xAA; //设备无所有属性 + } + } + else + { + getPara_reply_flg = 0xBB; //设备拒绝执行 + } + } + else //无request_id + { + getPara_reply_flg = 0xBB; //设备拒绝执行 + } +} + +//接收数据，在串口中断执行 +void LTE_4G_IT_Receive(void) +{ + //接收数据 + uint8_t received_byte = USART_ReceiveData(LTE_UART); + + //防止数组溢出 + if(LTE_Rx_BufIndex < LTE_RX_BUF_LEN - 1) + { + LTE_Rx_Buf[LTE_Rx_BufIndex] = received_byte; + LTE_Rx_BufIndex++; + } + else + { + LTE_4G_ClearBuf(); + } + + //更新计时 + if(LTE_OTA_Flag == 0) + { + LTE_Moni_Count = LTE_MON_CNT; + } + else + { + LTE_Moni_Count = LTE_OTA_CNT; + } +} + +//处理数据，接收报文识别后执行 +//波特率115200 +void LTE_4G_IT_Update(void) +{ + /*收到OK或>或ERROR，认为回复完整，开始分析*/ + if((LTE_Rx_BufIndex >= 2) && (strstr(LTE_Rx_Buf, "OK"))) + { + char tempStr[2]; //用于分析回复内容 + uint8_t len = 0; + uint16_t temp; + + if(LTE_Onlineflag == 0) LTE_ErrCnt = 0; + else MQTT_ErrCnt = 0; + + /** 重启状态指令的回复 **/ + //(重启4G模块，不考虑回复OK) + //(重启MQTT，不考虑回复OK) + //重新联网，尝试解决通信故障 + if(CFUN_flag == 1) + { + //0. + if(strstr(LTE_Rx_Buf, "AT+CFUN=0")) + { + CFUN_flag = 1; + CFUN_step = 1; //准备执行下一步 + LTE_Networkflag = 0; //已关闭联网 + } + //1. + else if(strstr(LTE_Rx_Buf, "AT+CFUN=1")) + { + CFUN_flag = 1; + CFUN_step = 2; //重启网络完成，执行下一步：等待3s后，获取当前网络状态 + LTE_Networkflag = 1; //已打开联网 + + CFUN_count++; + if(CFUN_count > 5) + { + CFUN_count = 0; + + CFUN_flag = 0xAA; //重新联网5次失败，跳转发CGREG，直到重启(因为本来下一步也是CGREG，所以放在这里计数也可以) + CFUN_step = 0; + } + } + //2.3.4.等待 + //5. + else if(strstr(LTE_Rx_Buf, "AT+CGREG?")) + { + CFUN_flag = 0; + CFUN_step = 0; //该次重联网流程完成 + + //+CGREG: 0,1\r\n\r\nOK + len = GetStr("+CGREG: 0,", 0x0d, 0x0d, LTE_Rx_Buf, tempStr); + sscanf(tempStr, "%hu", &temp); + + if(len > 0) + { + //获取联网状态 + LTE_register = temp; + + //显示在屏幕 + sprintf(LTEStatus_str + strlen(LTEStatus_str), " = %d", LTE_register); + + if(temp == 2) //正在搜索网络，需要等几秒再询问 + { + searching_cnt++; + if(searching_cnt <= 10) + { + CFUN_flag = 1; + CFUN_step = 2; //等待3s后，再次获取当前网络状态 + } + else + { + searching_cnt = 0; + LTE_Onlineflag = 0xAA; //联网错误 //若持续30s还没好，进入原有判断流程 + } + } + else + { + searching_cnt = 0; + + if((temp == 1) || (temp == 5)) + { + LTE_Onlineflag = 1; //联网正常 + + if(LTE_rssi == 99) //此前rssi异常，正常后需重新获取rssi + { + CSQ_flag = 1; + LTE_rssi = 0; + } + + MQTT_START_flag = 0; + MQTT_START_step = 0; //保证后续联网操作是从第1步走 + + CFUN_count = 0; //计数清零 + } + else //包括CGREG:0,11 + { + LTE_Onlineflag = 0xAA; //联网错误 + } + } + } + else + { + LTE_Onlineflag = 0xAA; //联网错误 + } + } + } + + /** 连接云平台之前指令的回复 **/ + //查询网络注册状态 + else if(CGREG_flag == 1) + { + if(strstr(LTE_Rx_Buf, "AT+CGREG?")) + { + //+CGREG: 0,1\r\n\r\nOK + len = GetStr("+CGREG: 0,", 0x0d, 0x0d, LTE_Rx_Buf, tempStr); + sscanf(tempStr, "%hu", &temp); + + if(len > 0) + { + //获取联网状态 + LTE_register = temp; + + //显示在屏幕 + sprintf(LTEStatus_str + strlen(LTEStatus_str), " = %d", LTE_register); + + if((temp == 1) || (temp == 5)) + { + LTE_Onlineflag = 1; //联网正常 + + if(LTE_rssi == 99) //此前rssi异常，正常后需重新获取rssi + { + CSQ_flag = 1; + LTE_rssi = 0; + } + + MQTT_START_flag = 0; + MQTT_START_step = 0; //保证后续联网操作是从第1步走 + + CGREG_flag = 0; //完成 + CGREG_count = 0; //计数清零 + + CFUN_flag = 0; //(若是在CFUN=0xAA后才恢复，也需要清零) + CFUN_count = 0; //计数清零 + } + else //包括CGREG:0,11 + { + LTE_Onlineflag = 0xAA; //联网错误 + + CGREG_count++; + if(CGREG_count > RST_timeEnd) //4min + { + CGREG_flag = 0; + CGREG_count = 0; + + CRESET_flag = 1; //重启 + CRESET_step = 0; + } + } + } + else + { + LTE_Onlineflag = 0xAA; //联网错误 + + CGREG_count++; + if(CGREG_count > RST_timeEnd) //8min + { + CGREG_flag = 0; + CGREG_count = 0; + + CRESET_flag = 1; //重启 + CRESET_step = 0; + } + } + } + else //测试发现在这里执行但有时不回复，这里也加上 + { + LTE_Onlineflag = 0xAA; //联网错误 + + CGREG_count++; + if(CGREG_count > RST_timeEnd) //8min + { + CGREG_flag = 0; + CGREG_count = 0; + + CRESET_flag = 1; //重启 + CRESET_step = 0; + } + } + } + //查询信号质量 + else if(CSQ_flag == 1) + { + if(strstr(LTE_Rx_Buf, "AT+CSQ")) + { + // +CSQ: 23,99\r\n\r\nOK + len = GetStr("+CSQ: ", ',', ',', LTE_Rx_Buf, tempStr); + sscanf(tempStr, "%hu", &temp); + + if(len > 0) + { + //获得信号强度 + LTE_rssi = temp; + + //显示在屏幕 + sprintf(LTEStatus_str + strlen(LTEStatus_str), " = %d", LTE_rssi); + } + } + } + //连接MQTT服务器 + else if(MQTT_START_flag == 1) + { + //0. + if(strstr(LTE_Rx_Buf, "AT+CMQTTSTART")) + { + if(strstr(LTE_Rx_Buf, "+CMQTTSTART: 1")) //异常 + { + MQTT_START_flag = 0; //执行连接标志清零(会在重启MQTT结束后可以再置1) + MQTT_START_step = 0; + + MQTT_START_count++; + if(MQTT_START_count <= 5) + { + MQTT_RST_flag = 1; //重启MQTT功能 + MQTT_RST_step = 0; + } + else if(MQTT_START_count <= 6) + { + //CGREG_flag = 1; //重启MQTT服务无用，或有可能是未被发现的联网异常，转检查CGREG + LTE_Onlineflag = 0; //重新检查联网情况 + + CSQ_flag = 1; //重新获取此时的rssi + LTE_rssi = 0; + } + else + { + MQTT_START_count = 0; + + CRESET_flag = 1; //联网无异常仍执行到这一步有问题，执行重启 + CRESET_step = 0; + } + } + else //"+CMQTTSTART: 0"，4G模块有时不会回复这句话(Bug)，所以不做判断 + { + MQTT_START_flag = 1; + MQTT_START_step = 1; //准备下一步 + } + } + //1. + else if(strstr(LTE_Rx_Buf, "AT+CMQTTACCQ")) + { + MQTT_START_flag = 1; + MQTT_START_step = 2; //准备下一步 + } + //2. + else if(strstr(LTE_Rx_Buf, "AT+CMQTTCONNECT")) + { + LTE_LINK_flag = 1; //连接服务器成功 + + MQTT_START_flag = 0; + MQTT_START_step = 0; //完成 + + CRESET_count = 0; //计数清零 + MQTT_RST_count = 0; //计数清零 + + CICCID_flag = 1; //跳转：获取CICCID + } + } + + /** 已连接云平台，正在基础配置指令的回复 **/ + //查询CICCID + else if(CICCID_flag == 1) + { + if(strstr(LTE_Rx_Buf, "AT+CICCID") && strstr(LTE_Rx_Buf, "+ICCID:")) + { + uint16_t i,j; + + // +ICCID: 89860869102570311585\r\n\r\nOK + for(i=0;i 0) + { + //获取信号质量 + LTE_rssi = temp; + + //显示在屏幕 + sprintf(LTEStatus_str + strlen(LTEStatus_str), " = %d", LTE_rssi); + + if((LTE_rssi > 13) && (LTE_rssi < 99)) //14~98 + { + rssiLow_count = 0; + + LTE_status = send_timed; + LTE_step = send_timed_step1; //完成，跳转：定时上报[属性] + } + else + { + rssiLow_count++; + if(rssiLow_count <= RSSI_timeEnd) //4min内一直质量差，保持询问CSQ和CGREG，等待信号质量变好 + { + LTE_status = ask_rssi; + LTE_step = ask_rssi_step2; //信号弱，跳转询问CGREG + } + else + { + rssiLow_count = 0; + + CRESET_flag = 1; //重启，再次连接MQTT + CRESET_step = 0; + } + } + } + } + //2.检查联网情况 + else if(strstr(LTE_Rx_Buf, "AT+CGREG?") && (LTE_step == ask_rssi_step2)) + { + //+CGREG: 0,1\r\n\r\nOK + len = GetStr("+CGREG: 0,", 0x0d, 0x0d, LTE_Rx_Buf, tempStr); + sscanf(tempStr, "%hu", &temp); + + if(len > 0) + { + //获取联网状态 + LTE_register = temp; + + //显示在屏幕 + sprintf(LTEStatus_str + strlen(LTEStatus_str), " = %d", LTE_register); + + if((temp == 1) || (temp == 5)) + { + LTE_status = ask_rssi; + LTE_step = ask_rssi_step1; //联网正常，跳转继续询问CSQ + } + else //包括CGREG:0,11 + { + LTE_Onlineflag = 0xAA; //联网错误 + + LTE_LINK_flag = 0; //清零连接状态，等待重联网 + MQTT_START_flag = 0; + MQTT_READY_flag = 0; + MQTT_timed_count = 0; + } + } + else + { + LTE_Onlineflag = 0xAA; //联网错误 + + LTE_LINK_flag = 0; //清零连接状态，等待重联网 + MQTT_START_flag = 0; + MQTT_READY_flag = 0; + MQTT_timed_count = 0; + } + } + } + //2.定时上报[属性] + else if(LTE_status == send_timed) + { + //2. + if(LTE_step == send_timed_step2) + { + LTE_status = send_timed; + LTE_step = send_timed_step3; //主题接收OK，准备下一步 + } + //4. + else if(LTE_step == send_timed_step4) + { + LTE_status = send_timed; + LTE_step = send_timed_step5; //内容接收OK，准备下一步 + } + //5. + else if(strstr(LTE_Rx_Buf, "AT+CMQTTPUB") && (LTE_step == send_timed_step5)) + { + property_pub_count = 0; //完成定时上报属性，定时检查计数清零 + incident_pub_count = 0; //完成定时上报属性，对上报事件个数的限制清零 + incident_DataFlg = 0; //完成定时上报属性，下次事件可以记录实时数据 + + if(pre_sleep_flag != 4) + { + LTE_status = wait_timed; + LTE_step = wait_timed_step1; //上报[属性]完成，跳转：等待定时 + } + else + { + pre_sleep_flag = 5; //退出MQTT后，执行休眠 + + LTE_LINK_flag = 0; + + MQTT_RST_flag = 1; + MQTT_RST_step = 0; + + MQTT_READY_flag = 0; + MQTT_timed_count = 0; + } + } + } + //3.等待30s定时(无) + //4.检查是否正常订阅主题，有缺就补 + else if(LTE_status == check_sub) + { + //0.检查订阅 + if(strstr(LTE_Rx_Buf, "AT+CMQTTSUB?") && (LTE_step == check_sub_step01)) + { + check_sub_count = 0; //检查订阅的超时计数清零 + + if(strstr(LTE_Rx_Buf, "/ext/ntp") == 0) //缺少了[校时]主题 + { + LTE_status = check_sub; + LTE_step = check_sub_step11; //无订阅，跳转：再次订阅[校时]的主题 + } + else if(strstr(LTE_Rx_Buf, "/thing/service/invoke") == 0) //缺少了[服务]主题 + { + LTE_status = check_sub; + LTE_step = check_sub_step21; //无订阅，跳转：再次订阅[服务]的主题 + } + else if(strstr(LTE_Rx_Buf, "/thing/property/set") == 0) //缺少了写[属性]主题 + { + LTE_status = check_sub; + LTE_step = check_sub_step31; //无订阅，跳转：再次订阅写[属性]的主题 + } + else if(strstr(LTE_Rx_Buf, "/thing/property/get") == 0) //缺少了读[属性]主题 + { + LTE_status = check_sub; + LTE_step = check_sub_step41; //无订阅，跳转：再次订阅写[属性]的主题 + } + else if(strstr(LTE_Rx_Buf, "/ota/device/upgrade/101") == 0) //缺少了OTA升级信息主题 + { + LTE_status = check_sub; + LTE_step = check_sub_step51; //无订阅，跳转：再次订阅写[属性]的主题 + } + + //都有正常订阅 + else + { + LTE_status = ask_lbs; + LTE_step = ask_lbs_step1; //跳转：正常流程第一步 + } + } + //1.订阅[校时]的主题 + else if(LTE_step == check_sub_step11) + { + check_sub_count = 0; //检查订阅的超时计数清零 + + LTE_status = ask_lbs; + LTE_step = ask_lbs_step1; //跳转：正常流程第一步 + + MQTT_timed_count += 2; + } + //2.订阅[服务]的主题 + else if(LTE_step == check_sub_step21) + { + check_sub_count = 0; //检查订阅的超时计数清零 + + LTE_status = ask_lbs; + LTE_step = ask_lbs_step1; //跳转：正常流程第一步 + + MQTT_timed_count += 2; + } + //3.订阅写[属性]的主题 + else if(LTE_step == check_sub_step31) + { + check_sub_count = 0; //检查订阅的超时计数清零 + + LTE_status = ask_lbs; + LTE_step = ask_lbs_step1; //跳转：正常流程第一步 + + MQTT_timed_count += 2; + } + //4.订阅读[属性]的主题 + else if(LTE_step == check_sub_step41) + { + check_sub_count = 0; //检查订阅的超时计数清零 + + LTE_status = ask_lbs; + LTE_step = ask_lbs_step1; //跳转：正常流程第一步 + + MQTT_timed_count += 2; + } + //5.订阅OTA升级信息的主题 + else if(LTE_step == check_sub_step51) + { + check_sub_count = 0; //检查订阅的超时计数清零 + + LTE_status = ask_lbs; + LTE_step = ask_lbs_step1; //跳转：正常流程第一步 + + MQTT_timed_count += 2; + } + } + + //0xA0.若存在事件，立即上报所有[事件] + else if(LTE_status == event_pub) + { + //2. + if(LTE_step == event_pub_step2) + { + LTE_status = event_pub; + LTE_step = event_pub_step3; //主题接收OK，准备下一步 + } + //4. + else if(LTE_step == event_pub_step4) + { + LTE_status = event_pub; + LTE_step = event_pub_step5; //内容接收OK，准备下一步 + } + //5. + else if(strstr(LTE_Rx_Buf, "AT+CMQTTPUB") && (LTE_step == event_pub_step5)) + { + incident_reply_count = 0; + + LTE_status = ask_lbs; + LTE_step = ask_lbs_step1; //跳转：正常流程第一步 + + incident_pub_count++; //记录上报数量，一次性不能超过5个 + incident_flag = 0; //当前事件上报完成，之后可检测下次[事件] + + if(pre_sleep_flag == 3) + { + pre_sleep_flag = 4; //启动休眠事件，上报完成，然后执行上报休眠前属性 + } + else if(pre_sleep_flag == 0xAA) + { + pre_sleep_flag = 0; //退出休眠事件，上报完成 + } + } + } + //0xA1.立即回复写[服务] + else if(LTE_status == srvc_pub) + { + //2. + if(LTE_step == srvc_pub_step2) + { + LTE_status = srvc_pub; + LTE_step = srvc_pub_step3; //主题接收OK，准备下一步 + } + //4. + else if(LTE_step == srvc_pub_step4) + { + LTE_status = srvc_pub; + LTE_step = srvc_pub_step5; //内容接收OK，准备下一步 + } + //5. + else if(strstr(LTE_Rx_Buf, "AT+CMQTTPUB") && (LTE_step == srvc_pub_step5)) + { + putSrvc_reply_count = 0; + + LTE_status = ask_lbs; + LTE_step = ask_lbs_step1; //跳转：正常流程第一步 + + putSrvc_reply_flg = 0; + putSrvc_reply_count = 0; + } + } + //0xA2.立即回复写[属性] + else if(LTE_status == setPara_pub) + { + //2. + if(LTE_step == setPara_pub_step2) + { + LTE_status = setPara_pub; + LTE_step = setPara_pub_step3; //主题接收OK，准备下一步 + } + //4. + else if(LTE_step == setPara_pub_step4) + { + LTE_status = setPara_pub; + LTE_step = setPara_pub_step5; //内容接收OK，准备下一步 + } + //5. + else if(strstr(LTE_Rx_Buf, "AT+CMQTTPUB") && (LTE_step == setPara_pub_step5)) + { + setPara_reply_count = 0; + + LTE_status = ask_lbs; + LTE_step = ask_lbs_step1; //跳转：正常流程第一步 + + setPara_reply_flg = 0; + setPara_reply_count = 0; + } + } + //0xA3.立即回复读[属性] + else if(LTE_status == getPara_pub) + { + //2. + if(LTE_step == getPara_pub_step2) + { + LTE_status = getPara_pub; + LTE_step = getPara_pub_step3; //主题接收OK，准备下一步 + } + //4. + else if(LTE_step == getPara_pub_step4) + { + LTE_status = getPara_pub; + LTE_step = getPara_pub_step5; //内容接收OK，准备下一步 + } + //5. + else if(strstr(LTE_Rx_Buf, "AT+CMQTTPUB") && (LTE_step == getPara_pub_step5)) + { + getPara_reply_count = 0; + + LTE_status = ask_lbs; + LTE_step = ask_lbs_step1; //跳转：正常流程第一步 + + getPara_reply_flg = 0; + getPara_reply_count = 0; + } + } + //0xAA.转存完成，设备上线后主动上报OTA升级完成 + else if(LTE_status == ota_fine_pub) + { + //2. + if(LTE_step == ota_fine_pub_step2) + { + LTE_status = ota_fine_pub; + LTE_step = ota_fine_pub_step3; //主题接收OK，准备下一步 + } + //4. + else if(LTE_step == ota_fine_pub_step4) + { + LTE_status = ota_fine_pub; + LTE_step = ota_fine_pub_step5; //内容接收OK，准备下一步 + } + //5. + else if(strstr(LTE_Rx_Buf, "AT+CMQTTPUB") && (LTE_step == ota_fine_pub_step5)) + { + otaFine_reply_count = 0; + + LTE_status = ask_lbs; + LTE_step = ask_lbs_step1; //跳转：正常流程第一步 + + //更新EE_OTA完成标志，为0 + LTE_OTA_fineFlag = 0; + OTAfine_WrFlg = 0xAA; + } + } + } + } + else if((LTE_Rx_BufIndex >= 1) && (strstr(LTE_Rx_Buf, ">"))) + { + if(LTE_Onlineflag == 0) LTE_ErrCnt = 0; + else MQTT_ErrCnt = 0; + + /** 已连接云平台，正在基础配置指令的回复 **/ + //订阅主题 + if(SUBTOPIC_flag == 1) + { + //0.订阅[校时]的主题 + if(strstr(LTE_Rx_Buf, "AT+CMQTTSUB=0,31,1") && (SUBTOPIC_step == 0)) + { + SUBTOPIC_step = 1; //准备下一步 + } + //2.订阅[服务]的主题 + else if(strstr(LTE_Rx_Buf, "AT+CMQTTSUB=0,39,1") && (SUBTOPIC_step == 2)) + { + SUBTOPIC_step = 3; //准备下一步 + } + //4.订阅写[属性]的主题 + else if(strstr(LTE_Rx_Buf, "AT+CMQTTSUB=0,37,1") && (SUBTOPIC_step == 4)) + { + SUBTOPIC_step = 5; //准备下一步 + } + //6.订阅读[属性]的主题 + else if(strstr(LTE_Rx_Buf, "AT+CMQTTSUB=0,37,1") && (SUBTOPIC_step == 6)) + { + SUBTOPIC_step = 7; //准备下一步 + } + //8.订阅OTA升级信息的主题 + else if(strstr(LTE_Rx_Buf, "AT+CMQTTSUB=0,33,1") && (SUBTOPIC_step == 8)) + { + SUBTOPIC_step = 9; //准备下一步 + } + } + //请求[校时] + else if(CALITIME_flag == 1) + { + //0.主题长度 + if(strstr(LTE_Rx_Buf, "AT+CMQTTTOPIC") && (CALITIME_step == 0)) + { + CALITIME_step = 1; //准备下一步 + } + } + + /** 已连接云平台且配置完成，正常通信指令的回复 **/ + else if(MQTT_READY_flag == 1) + { + //0.询问LBS数据(无) + //1.定时上报[属性] + if(LTE_status == send_timed) + { + //1. + if(strstr(LTE_Rx_Buf, "AT+CMQTTTOPIC") && (LTE_step == send_timed_step1)) + { + LTE_status = send_timed; + LTE_step = send_timed_step2; //准备下一步 + } + //3. + else if(strstr(LTE_Rx_Buf, "AT+CMQTTPAYLOAD") && (LTE_step == send_timed_step3)) + { + LTE_status = send_timed; + LTE_step = send_timed_step4; //准备下一步 + } + } + //3.等待30s定时(无) + //4.检查是否正常订阅主题，有缺就补 + else if(LTE_status == check_sub) + { + //1.补订阅[校时]的主题 + if(strstr(LTE_Rx_Buf, "AT+CMQTTSUB=0,31,1") && (LTE_step == check_sub_step11)) + { + check_sub_count = 0; //检查订阅的超时计数清零 + + LTE_step = check_sub_step12; //准备下一步 + } + //2.补订阅[服务]的主题 + else if(strstr(LTE_Rx_Buf, "AT+CMQTTSUB=0,39,1") && (LTE_step == check_sub_step21)) + { + check_sub_count = 0; //检查订阅的超时计数清零 + + LTE_step = check_sub_step22; //准备下一步 + } + //3.补订阅写[属性]的主题 + else if(strstr(LTE_Rx_Buf, "AT+CMQTTSUB=0,37,1") && (LTE_step == check_sub_step31)) + { + check_sub_count = 0; //检查订阅的超时计数清零 + + LTE_step = check_sub_step32; //准备下一步 + } + //4.补订阅读[属性]的主题 + else if(strstr(LTE_Rx_Buf, "AT+CMQTTSUB=0,37,1") && (LTE_step == check_sub_step41)) + { + check_sub_count = 0; //检查订阅的超时计数清零 + + LTE_step = check_sub_step42; //准备下一步 + } + //5.补订阅OTA升级信息的主题 + else if(strstr(LTE_Rx_Buf, "AT+CMQTTSUB=0,33,1") && (LTE_step == check_sub_step51)) + { + check_sub_count = 0; //检查订阅的超时计数清零 + + LTE_step = check_sub_step52; //准备下一步 + } + } + + //0xA0.若存在事件，立即上报所有[事件] + else if(LTE_status == event_pub) + { + //1. + if(strstr(LTE_Rx_Buf, "AT+CMQTTTOPIC") && (LTE_step == event_pub_step1)) + { + LTE_status = event_pub; + LTE_step = event_pub_step2; //准备下一步 + } + //3. + else if(strstr(LTE_Rx_Buf, "AT+CMQTTPAYLOAD") && (LTE_step == event_pub_step3)) + { + LTE_status = event_pub; + LTE_step = event_pub_step4; //准备下一步 + } + } + //0xA1.立即回复写[服务] + else if(LTE_status == srvc_pub) + { + //1. + if(strstr(LTE_Rx_Buf, "AT+CMQTTTOPIC") && (LTE_step == srvc_pub_step1)) + { + LTE_status = srvc_pub; + LTE_step = srvc_pub_step2; //准备下一步 + } + //3. + else if(strstr(LTE_Rx_Buf, "AT+CMQTTPAYLOAD") && (LTE_step == srvc_pub_step3)) + { + LTE_status = srvc_pub; + LTE_step = srvc_pub_step4; //准备下一步 + } + } + //0xA2.立即回复写[属性] + else if(LTE_status == setPara_pub) + { + //1. + if(strstr(LTE_Rx_Buf, "AT+CMQTTTOPIC") && (LTE_step == setPara_pub_step1)) + { + LTE_status = setPara_pub; + LTE_step = setPara_pub_step2; //准备下一步 + } + //3. + else if(strstr(LTE_Rx_Buf, "AT+CMQTTPAYLOAD") && (LTE_step == setPara_pub_step3)) + { + LTE_status = setPara_pub; + LTE_step = setPara_pub_step4; //准备下一步 + } + } + //0xA3.立即回复读[属性] + else if(LTE_status == getPara_pub) + { + //1. + if(strstr(LTE_Rx_Buf, "AT+CMQTTTOPIC") && (LTE_step == getPara_pub_step1)) + { + LTE_status = getPara_pub; + LTE_step = getPara_pub_step2; //准备下一步 + } + //3. + else if(strstr(LTE_Rx_Buf, "AT+CMQTTPAYLOAD") && (LTE_step == getPara_pub_step3)) + { + LTE_status = getPara_pub; + LTE_step = getPara_pub_step4; //准备下一步 + } + } + //0xAA.转存完成，设备上线后主动上报OTA升级完成 + else if(LTE_status == ota_fine_pub) + { + //1. + if(strstr(LTE_Rx_Buf, "AT+CMQTTTOPIC") && (LTE_step == ota_fine_pub_step1)) + { + LTE_status = ota_fine_pub; + LTE_step = ota_fine_pub_step2; //准备下一步 + } + //3. + else if(strstr(LTE_Rx_Buf, "AT+CMQTTPAYLOAD") && (LTE_step == ota_fine_pub_step3)) + { + LTE_status = ota_fine_pub; + LTE_step = ota_fine_pub_step4; //准备下一步 + } + } + } + } + else if((LTE_Rx_BufIndex >= 5) && (strstr(LTE_Rx_Buf, "ERROR"))) + { + if((CRESET_flag == 0) && (MQTT_RST_flag == 0) && (strstr(LTE_Rx_Buf, "AT+CMQTTSTOP") == 0)) //不考虑因重启的前置步骤而导致的ERROR + { + LTE_ResendDelay = ResendTime; + + if(LTEStatus_flg == 1) + { + strcat(LTEStatus_str, " ERR"); + } + + if(LTE_Onlineflag == 0) //未联网时 + { + LTE_ErrCnt++; + if(LTE_ErrCnt > ERR_timeEnd1) //最大：持续30s，重启4G模块 + { + LTE_ErrCnt = 0; + + CRESET_flag = 1; //重启 + CRESET_step = 0; + } + } + else //已联网时 + { + MQTT_ErrCnt++; + if(MQTT_ErrCnt > ERR_timeEnd2) //最大：持续1min，重启4G模块 + { + MQTT_ErrCnt = 0; + + CRESET_flag = 1; //重启 + CRESET_step = 0; + } + else if(((MQTT_ErrCnt > 3) && (MQTT_START_flag == 1)) || ((MQTT_ErrCnt > 15) && (LTE_LINK_flag == 1))) //连接MQTT时出现的ERROR等3次(6s)，后续出现的ERROR等15次(30s) + { + MQTT_RST_count++; + if(MQTT_RST_count <= 5) + { + MQTT_START_flag = 0; //退出连接 + MQTT_START_step = 0; + + MQTT_RST_flag = 1; //重启MQTT + MQTT_RST_step = 0; + + LTE_LINK_flag = 0; //已连接标志清零 + MQTT_START_flag = 0; + MQTT_READY_flag = 0; + MQTT_timed_count = 0; + + LTE_OTA_Flag = 0; //OTA升级标志清零 + } + else + { + MQTT_RST_count = 0; + + //CGREG_flag = 1; //重启MQTT服务无用，或有可能是未被发现的联网异常，转检查CGREG + LTE_Onlineflag = 0; //重新检查联网情况 + + CSQ_flag = 1; //重新获取此时的rssi + LTE_rssi = 0; + } + } + else if(LTE_status == ask_rssi) + { + CSQ_ErrCnt++; + if(CSQ_ErrCnt > 15) //对应30S左右 + { + CSQ_ErrCnt = 0; + + CRESET_flag = 1; //重启 + CRESET_step = 0; + } + } + } + } + } + + + /*特殊回复：状态*/ + //正常初始化 + if((LTE_Rx_BufIndex >= 10) && strstr(LTE_Rx_Buf, "ATREADY: 1")) + { + LTE_Onflag = 1; //4G模块已开机 + } + //SIM卡 + if((LTE_Rx_BufIndex >= 12) && strstr(LTE_Rx_Buf, "+CPIN: READY")) + { + LTE_SIMflag = 1; //SIM卡正常 + } + if((LTE_Rx_BufIndex >= 18) && strstr(LTE_Rx_Buf, "+CPIN: SIM REMOVED")) + { + LTE_SIMflag = 0; //未检测到SIM卡 + } + if((LTE_Rx_BufIndex >= 23) && strstr(LTE_Rx_Buf, "+SIMCARD: NOT AVAILABLE")) + { + LTE_SIMflag = 0; //未检测到SIM卡 + } + + /*特殊回复：4G模块异常*/ + if((LTE_Rx_BufIndex >= 4) && strstr(LTE_Rx_Buf, "BUSY")) + { + if(LTEStatus_flg == 1) + { + strcat(LTEStatus_str, " BUSY"); + } + + LTE_BUSY_cnt++; + if(LTE_BUSY_cnt > 30) + { + LTE_BUSY_cnt = 0; + LTE_PinRST_Flag = 1; //通过引脚重启4G模块 + } + } + else + { + LTE_BUSY_cnt = 0; + } +} + +//根据当前已知信息，选择接下来要执行的指令 +//可能同时赋值多个命令，但只会一个个执行 +void LTE_4G_IQ_Update(void) +{ + /** 通信云平台之前的状态改动 **/ + if(MQTT_READY_flag == 0) + { + if(LTE_Onlineflag == 0xAA) //信号异常或CGREG回复0,0 -> 都是驻网失败，执行5次找网，仍然失败就执行重启 + { + if(CFUN_flag == 0) //尝试断网重连，手动找网 + { + CFUN_flag = 1; + CFUN_step = 0; + } + else if(CFUN_flag == 0xAA) //5次失败，保持发CGREG指令，直到执行重启 + { + CGREG_flag = 1; + } + return; + } + + //1.采集信号质量(这里特指成功通信云平台前的) + if(LTE_rssi <= 13) //未询问或信号质量差 -> 持续询问信号质量直到信号变好，或者持续4min后执行重启 + { + rssiLow_count++; + if(rssiLow_count <= RSSI13_timeEnd) //4min + { + CSQ_flag = 1; + } + else + { + rssiLow_count = 0; + + CSQ_flag = 0; + + CRESET_flag = 1; //重启 + CRESET_step = 0; + } + } + else if(LTE_rssi == 99) + { + rssi99_count++; + if(rssi99_count <= RSSI99_timeEnd) //10s + { + CSQ_flag = 1; + } + else + { + rssi99_count = 0; + + LTE_Onlineflag = 0xAA; //尝试重新联网 + } + } + else //已获取到好的信号质量(14~98) -> 下一步检查联网状态 -> 联网成功且存在SN号时，尝试连到MQTT服务器 + { + rssiLow_count = 0; //计数清零 + rssi99_count = 0; //计数清零 + + CSQ_flag = 0; + + + //在通信质量好的前提下， + //2.询问是否联网 + if(LTE_Onlineflag == 0) //此前不知是否正常联网 -> 询问联网状态 + { + CGREG_flag = 1; + } + //3.网络正常，进行MQTT配置 + else if(LTE_Onlineflag == 1) //通信正常 -> 继续 + { + if((LTE_LINK_flag == 0) && (MQTT_RST_flag == 0)) //连接成功后&正重启MQTT时就不执行 + { + if((BMS_SN[0] != 0) && (BMS_SN[8] != 0)) //SN号头尾都有值说明存在，可以连接MQTT + { + LTE_NoMoni_Flag = 0; + + MQTT_START_flag = 1; + //MQTT_START_step = 0; + } + else + { + LTE_NoMoni_Flag = 1; + } + } + } + } + } + /** 通信云平台成功后的状态改动 **/ + else + { + /*监控平台下发报文，除了校准时间，其他收到1条并回复后才接收处理下一条*/ + if(strstr(LTE_Rx_Buf, "+CMQTTRXSTART") && strstr(LTE_Rx_Buf, "+CMQTTRXEND")) //有头有尾 + { + //校准系统时间 + if(strstr(LTE_Rx_Buf, "/ext/ntp")) + { + LTE_4G_SUB_NTP(); + } + else if((pre_sleep_flag < 2) && (putSrvc_reply_flg == 0) && (setPara_reply_flg == 0) && (getPara_reply_flg == 0)) + { + //下发[服务]指令 + if(strstr(LTE_Rx_Buf, "/thing/service/invoke")) + { + LTE_4G_SUB_Service(); + } + //写[属性] + else if(strstr(LTE_Rx_Buf, "/thing/property/set")) + { + LTE_4G_SUB_SETPARA(); + } + //读[属性] + else if(strstr(LTE_Rx_Buf, "/thing/property/get")) + { + LTE_4G_SUB_GETPARA(); + } + //OTA升级 + else if(strstr(LTE_Rx_Buf, "/ota/device/upgrade/101")) + { + LTE_NoMoni_Flag = 0; + + LTE_OTA_Info(); + } + } + } + + + /*正常通信中，持续检查是否有需要立即上报的内容*/ + if(LTE_step <= 105) //不在回复时，若需要回复则执行回复 + { + //上报启动休眠最优先 + if(pre_sleep_flag == 2) + { + pre_sleep_flag = 3; + + LTE_status = event_pub; + LTE_step = event_pub_step1; //跳转：立即上报[事件]：启动休眠 + MQTT_timed_count = 0; //清零定时上报倒计时 + } + //上报退出休眠最优先 + else if(pre_sleep_flag == 0xA0) + { + pre_sleep_flag = 0xAA; + + LTE_status = event_pub; + LTE_step = event_pub_step1; //跳转：立即上报[事件]：退出休眠 + MQTT_timed_count = 0; //清零定时上报倒计时 + } + //上报过启动休眠后，确保不会因其他打扰执行剩下的休眠前步骤 + else if(pre_sleep_flag < 2) + { + //回复写[服务]>回复写[属性]>回复读[属性]>立即上报[事件] + if(putSrvc_reply_flg != 0) + { + LTE_status = srvc_pub; + LTE_step = srvc_pub_step1; //跳转：立即回复写[服务]操作 + MQTT_timed_count = 0; //清零定时上报倒计时 + } + else if(setPara_reply_flg != 0) + { + LTE_status = setPara_pub; + LTE_step = setPara_pub_step1; //跳转：立即回复写[属性]操作 + MQTT_timed_count = 0; //清零定时上报倒计时 + } + else if(getPara_reply_flg != 0) + { + LTE_status = getPara_pub; + LTE_step = getPara_pub_step1; //跳转：立即回复写[属性]操作 + MQTT_timed_count = 0; //清零定时上报倒计时 + } + } + } + if(LTE_step <= 100) //若不在上报事件和回复时，判断是否要上报事件 + { + if(incident_pub_count < INCIDENT_PUB_MAX) + { + Transmit_incident(); //如果有报警/保护/加热提醒，立即准备上报 + if(incident_flag != 0) + { + LTE_status = event_pub; + LTE_step = event_pub_step1; //跳转：立即上报[事件] + MQTT_timed_count = 0; //清零定时上报倒计时 + } + } + } + + + /*定时上报[属性]的内容和长度更新*/ + if((LTE_status == send_timed) && (LTE_step == send_timed_step3)) + { + if(incident_DataFlg == 0) LTE_Record_pubData(); + } + } +} + +//该函数用于发送报文，1s执行1次 +//定时上报数据，每60s一次 +void LTE_4G_IQ_Transmit(void) +{ + if(LTE_NoMoni_Flag == 0) //不在发送AT指令的状态不算 + { + if((LTE_Rx_BufIndex == 0) && (LTE_WaitRxFlg == 1)) //有发送指令却没有回复 //只执行1次 + { + LTE_WaitRxFlg = 0; + LTE_WaitRxDelay = WaitRxTime; + + //若此时已上线，定时上报倒计时对应-3s //定时上报时序1s，等待共3s + if(MQTT_READY_flag == 1) + { + if(((int)LTE_status >= ask_lbs) && (LTE_status <= send_timed)) + { + MQTT_timed_count += WaitRxTime+1; + } + } + + return; + } + } + + LTE_Rx_BufIndex = 0; + memset(LTE_Rx_Buf, 0, LTE_RX_BUF_LEN); //填入前先清空 + memset(LTE_Tx_Buf, 0, LTE_TX_BUF_LEN); + + /** 重启状态 **/ + //1.重启4G模块 + if(CRESET_flag == 1) + { + if(CRESET_count < 5) //AT指令通信重启 + { + switch(CRESET_step) //0~2:失败也没关系 3:不考虑收到回复 + { + case 0: + LTEStatus_flg = 1; + strcpy(LTEStatus_str, "RST 4G step1"); + CRESET_step = 1; + LTE_Send("AT+CMQTTDISC=0\r\n"); //断开与服务器的连接 + break; + case 1: + LTEStatus_flg = 1; + strcpy(LTEStatus_str, "RST 4G step2"); + CRESET_step = 2; + LTE_Send("AT+CMQTTREL=0\r\n"); //解除客户关系 + break; + case 2: + LTEStatus_flg = 1; + strcpy(LTEStatus_str, "RST 4G step3"); + CRESET_step = 3; + LTE_Send("AT+CMQTTSTOP\r\n"); //停止MQTT服务 + break; + case 3: + LTEStatus_flg = 1; + strcpy(LTEStatus_str, "RST 4G step4"); + CRESET_flag = 0; + CRESET_step = 0; + CRESET_count++; + LTE_Send("AT+CRESET\r\n"); + + LTE_WarmDelay = OpenTime; //开机等待 + LTE_4G_Init(); //芯片也重启通信相关 + break; + default: + CRESET_step = 0; //非法值改为第一步 + break; + } + } + else //引脚重启 + { + CRESET_count = 0; //之后再经过5次后才会再做一次 + + LTE_PinRST_Flag = 1; //跳转执行引脚重启 + } + } + //2.重启MQTT服务 + else if(MQTT_RST_flag == 1) + { + switch(MQTT_RST_step) //0~3，失败也没关系 + { + case 0: + LTEStatus_flg = 1; + strcpy(LTEStatus_str, "RST MQTT step1"); + MQTT_RST_step = 1; + LTE_Send("AT+CMQTTDISC=0\r\n"); //断开与服务器的连接 + break; + case 1: + LTEStatus_flg = 1; + strcpy(LTEStatus_str, "RST MQTT step2"); + MQTT_RST_step = 2; + LTE_Send("AT+CMQTTREL=0\r\n"); //解除客户关系 + break; + case 2: + LTEStatus_flg = 1; + strcpy(LTEStatus_str, "RST MQTT step3"); + MQTT_RST_flag = 0; + MQTT_RST_step = 0; + LTE_Send("AT+CMQTTSTOP\r\n"); //停止MQTT服务 + + //MQTT停止，休眠前置步骤全部完成，进入休眠 + if(pre_sleep_flag == 5) + { + pre_sleep_flag = 0; + LTE_sleep_flag = 1; + } + //尝试再次连接 + else if((BMS_SN[0] != 0) && (BMS_SN[8] != 0)) //SN号头尾都有值说明存在，可以连接MQTT + { + MQTT_START_flag = 1; + MQTT_START_step = 0; //重新启动MQTT服务 + + LTE_LINK_flag = 0; //已连接标志清零 + } + break; + default: + MQTT_RST_step = 0; //非法值改为第一步 + break; + } + } + //3.重新联网 + else if(CFUN_flag == 1) + { + switch(CFUN_step) + { + case 0: + LTEStatus_flg = 1; + strcpy(LTEStatus_str, "RST NET step1"); + LTE_Send("AT+CFUN=0\r\n"); + break; + case 1: + LTEStatus_flg = 1; + strcpy(LTEStatus_str, "RST NET step2"); + LTE_Send("AT+CFUN=1\r\n"); + break; + case 2: + CFUN_step = 3; + break; + case 3: + CFUN_step = 4; + break; + case 4: + CFUN_step = 5; + break; + case 5: + LTEStatus_flg = 1; + strcpy(LTEStatus_str, "check network"); + LTE_Send("AT+CGREG?\r\n"); + break; + default: + CFUN_step = 0; //非法值改为第一步 + break; + } + } + + /** 连接云平台之前 **/ + //查询网络注册状态 + else if(CGREG_flag == 1) + { + LTEStatus_flg = 1; + strcpy(LTEStatus_str, "ask network"); + LTE_Send("AT+CGREG?\r\n"); + } + //查询信号质量 + else if(CSQ_flag == 1) + { + LTEStatus_flg = 1; + strcpy(LTEStatus_str, "ask rssi"); + LTE_Send("AT+CSQ\r\n"); + } + //连接MQTT服务器 + else if(MQTT_START_flag == 1) + { + switch(MQTT_START_step) + { + case 0: + LTEStatus_flg = 1; + strcpy(LTEStatus_str, "MQTT step1"); + LTE_Send("AT+CMQTTSTART\r\n"); //启动MQTT服务 + break; + case 1: + LTEStatus_flg = 1; + strcpy(LTEStatus_str, "MQTT step2"); + //LTE_Send("AT+CMQTTACCQ=0,\"jdg0bcu4RMG!rmt0ubv\"\r\n"); //38字节 + LTE_Send("AT+CMQTTACCQ=0,\"%.23s\"\r\n", VersionMem.ClientID); //输入服务器clientId + break; + case 2: + LTEStatus_flg = 1; + strcpy(LTEStatus_str, "MQTT step3"); + //LTE_Send("AT+CMQTTCONNECT=0,\"tcp://mqtt_zn.ricnsmart.com\",60,1,\"device\",\"E6Mk2Rj6uhFU4Zgy3kWCbghvaDYka8Dz\"\r\n"); //98字节 + LTE_Send("AT+CMQTTCONNECT=0,\"%.40s:%hu\",60,1,\"%.40s\",\"%.40s\"\r\n", VersionMem.host, VersionMem.port, VersionMem.UserName, VersionMem.PassWord); //输入host和密码 + break; + default: + MQTT_START_step = 0; //非法值改为第一步 + break; + } + } + + /** 已连接云平台，正在基础配置 **/ + //查询CICCID + else if(CICCID_flag == 1) + { + LTEStatus_flg = 1; + strcpy(LTEStatus_str, "ask ICCID"); + LTE_Send("AT+CICCID\r\n"); + } + //订阅主题 + else if(SUBTOPIC_flag == 1) + { + LTEStatus_flg = 1; + strcpy(LTEStatus_str, "sub topic"); + + if(LTE_UNSUB_Flag == 1) + { + LTE_UNSUB_Flag = 0; + EEPROM_WrMulByte(EE_UNSUB,<E_UNSUB_Flag); + delay_ms(5); + + LTE_Send("AT+CMQTTUNSUB=0,1\r\n"); + return; + } + + switch(SUBTOPIC_step) + { + /**订阅[校时]的主题**/ + case 0: + LTE_Send("AT+CMQTTSUB=0,31,1\r\n"); //订阅主题长度 "/ext/ntp/101/030200001/response"=31Byte + break; + case 1: + //LTE_Send("/ext/ntp/101/0000000030200001/response"); + LTE_Send("/ext/ntp/101/%s/response", BMS_SN); //订阅的主题 (只有这个不用换新行) + break; + + /**订阅[服务]的主题**/ + case 2: + LTE_Send("AT+CMQTTSUB=0,39,1\r\n"); //下发主题长度 "/sys/101/030200001/thing/"=25Byte "service/invoke"=14Byte + break; + case 3: + //LTE_Send("/sys/101/030200001/thing/service/invoke"); + LTE_Send("/sys/101/%s/thing/service/invoke", BMS_SN); //上报的主题 (只有这个不用换新行) + break; + + /**订阅写[属性]的主题**/ + case 4: + LTE_Send("AT+CMQTTSUB=0,37,1\r\n"); //订阅主题长度 "/sys/101/030200001/thing/"=25Byte "property/set"=12Byte + break; + case 5: + //LTE_Send("/sys/101/030200001/thing/property/set"); + LTE_Send("/sys/101/%s/thing/property/set", BMS_SN); //订阅的主题 (只有这个不用换新行) + break; + + /**订阅读[属性]的主题**/ + case 6: + LTE_Send("AT+CMQTTSUB=0,37,1\r\n"); //订阅主题长度 "/sys/101/030200001/thing/"=25Byte "property/get"=12Byte + break; + case 7: + //LTE_Send("/sys/101/030200001/thing/property/get"); + LTE_Send("/sys/101/%s/thing/property/get", BMS_SN); //订阅的主题 (只有这个不用换新行) + break; + + /**订阅OTA升级信息的主题**/ + case 8: + LTE_Send("AT+CMQTTSUB=0,33,1\r\n"); //订阅主题长度 "/ota/device/upgrade/101/030200001"=33Byte + break; + case 9: + //LTE_Send("/ota/device/upgrade/101/030200001"); + LTE_Send("/ota/device/upgrade/101/%s", BMS_SN); //订阅的主题 (只有这个不用换新行) + break; + + default: + SUBTOPIC_step = 0; //非法值改为第一步 + break; + } + } + //请求[校时] + else if(CALITIME_flag == 1) + { + LTEStatus_flg = 1; + strcpy(LTEStatus_str, "ask systime"); + + switch(CALITIME_step) + { + case 0: + LTE_Send("AT+CMQTTTOPIC=0,30\r\n"); //上报主题长度 "/ext/ntp/101/030200001/request"=30Byte + break; + case 1: + //LTE_Send("/ext/ntp/101/030200001/request"); + LTE_Send("/ext/ntp/101/%s/request", BMS_SN); //上报的主题 (只有这个不用换新行) + break; + case 2: + LTE_Send("AT+CMQTTPUB=0,1,30\r\n"); //至少上报1次+30s内等待服务器回复 + break; + default: + CALITIME_step = 0; //非法值改为第一步 + break; + } + } + + /** 已连接云平台且配置完成，正常通信 **/ + else if(MQTT_READY_flag == 1) + { + /*定时上报[属性]*/ + //0.询问LBS数据 + if(LTE_status == ask_lbs) + { + switch(LTE_step) + { + case ask_lbs_step1: + LTE_Send("AT+CLBS=1\r\n"); //获取4G基站定位信息 + break; + default: + LTE_step = ask_lbs_step1; //非法值改为第一步 + break; + } + } + //1.询问信号质量 + else if(LTE_status == ask_rssi) + { + switch(LTE_step) + { + case ask_rssi_step1: + LTEStatus_flg = 1; + strcpy(LTEStatus_str, "check rssi"); + LTE_Send("AT+CSQ\r\n"); //询问信号质量 + break; + case ask_rssi_step2: + LTEStatus_flg = 1; + strcpy(LTEStatus_str, "check network"); + LTE_Send("AT+CGREG?\r\n"); //询问联网情况 + break; + default: + LTE_step = ask_rssi_step1; //非法值改为第一步 + break; + } + } + //2.定时上报[属性] + else if(LTE_status == send_timed) + { + LTEStatus_flg = 1; + strcpy(LTEStatus_str, "send property"); + + switch(LTE_step) + { + case send_timed_step1: + LTE_Send("AT+CMQTTTOPIC=0,38\r\n"); //上报主题长度 "/sys/101/030200001/thing/"=25Byte "property/post"=13Byte + break; + case send_timed_step2: + //LTE_Send("/sys/101/030200001/thing/property/post"); + LTE_Send("/sys/101/%s/thing/property/post", BMS_SN); //上报的主题 (只有这个不用换新行) + break; + case send_timed_step3: + LTE_Send("AT+CMQTTPAYLOAD=0,%u\r\n", LTEMem_len); //上报内容长度 = 数据长度+固定字符长度+回车 + break; + case send_timed_step4: + LTE_Send(LTEMem_Buf); //发送缓存区内容 + break; + case send_timed_step5: + LTE_Send("AT+CMQTTPUB=0,1,30\r\n"); //至少上报1次+30s内等待服务器回复 + break; + default: + LTE_step = send_timed_step1; //非法值改为第一步 + break; + } + } + //3.等待60s定时 + else if(LTE_status == wait_timed) + { + switch(LTE_step) + { + case wait_timed_step1: + LTE_NoMoni_Flag = 1; + MQTT_timed_count++; //倒计时 + if(MQTT_timed_count > timed_Delay) + { + LTE_NoMoni_Flag = 0; + MQTT_timed_count = 0; + + LTE_status = check_sub; + LTE_step = check_sub_step01; //倒计时结束，跳转：检查订阅 + } + break; + default: + LTE_step = wait_timed_step1; //非法值改为第一步 + break; + } + } + //4.检查是否正常订阅主题 + else if(LTE_status == check_sub) + { + check_sub_count++; + if(check_sub_count > 2) //在这里连续2次(6s)无有效响应 + { + LTE_status = ask_lbs; + LTE_step = ask_lbs_step1; //跳转：正常流程第一步 + + check_sub_count = 0; + } + + switch(LTE_step) + { + //查询订阅 + case check_sub_step01: + LTE_Send("AT+CMQTTSUB?\r\n"); //查询订阅 + break; + + //重新订阅[校时] + case check_sub_step11: + LTE_Send("AT+CMQTTSUB=0,31,1\r\n"); //订阅主题长度 "/ext/ntp/101/030200001/response"=31Byte + break; + case check_sub_step12: + //LTE_Send("/ext/ntp/101/030200001/response"); + LTE_Send("/ext/ntp/101/%s/response", BMS_SN); //订阅的主题 (只有这个不用换新行) + break; + //重新订阅[服务] + case check_sub_step21: + LTE_Send("AT+CMQTTSUB=0,39,1\r\n"); //下发主题长度 "/sys/101/030200001/thing/"=25Byte "service/invoke"=14Byte + break; + case check_sub_step22: + //LTE_Send("/sys/101/030200001/thing/service/invoke"); + LTE_Send("/sys/101/%s/thing/service/invoke", BMS_SN); //上报的主题 (只有这个不用换新行) + break; + //重新订阅写[属性] + case check_sub_step31: + LTE_Send("AT+CMQTTSUB=0,37,1\r\n"); //订阅主题长度 "/sys/101/030200001/thing/property/set"=37Byte + break; + case check_sub_step32: + //LTE_Send("/sys/101/030200001/thing/property/set"); + LTE_Send("/sys/101/%s/thing/property/set", BMS_SN); //订阅的主题 (只有这个不用换新行) + break; + //重新订阅读[属性] + case check_sub_step41: + LTE_Send("AT+CMQTTSUB=0,37,1\r\n"); //订阅主题长度 "/sys/101/030200001/thing/property/get"=37Byte + break; + case check_sub_step42: + //LTE_Send("/sys/101/030200001/thing/property/get"); + LTE_Send("/sys/101/%s/thing/property/get", BMS_SN); //订阅的主题 (只有这个不用换新行) + break; + //重新订阅OTA升级信息 + case check_sub_step51: + LTE_Send("AT+CMQTTSUB=0,33,1\r\n"); //订阅主题长度 "/ota/device/upgrade/101/030200001"=33Byte + break; + case check_sub_step52: + //LTE_Send("/ota/device/upgrade/101/030200001"); + LTE_Send("/ota/device/upgrade/101/%s", BMS_SN); //订阅的主题 (只有这个不用换新行) + break; + default: + LTE_step = check_sub_step01; //非法值改为第一步 + break; + } + } + + /*突发立即上报*/ + //0xA0.若存在事件，立即上报所有[事件] + else if(LTE_status == event_pub) + { + LTEStatus_flg = 1; + strcpy(LTEStatus_str, "send event"); + + incident_reply_count++; + //尝试1次重新回复 + if(incident_reply_count == 10) + { + LTE_step = event_pub_step1; + } + //仍然失败退出回复 + else if(incident_reply_count >= 20) + { + LTE_status = ask_lbs; + LTE_step = ask_lbs_step1; //上报[事件]完成，跳转：正常流程第一步 + + incident_pub_count++; //记录上报数量，一次性不能超过5个 + incident_flag = 0; //当前事件上报完成，之后可检测下次[事件] + incident_reply_count = 0; + } + + switch(LTE_step) //event_pub_step11~event_pub_step5 + { + case event_pub_step1: + LTE_Send("AT+CMQTTTOPIC=0,35\r\n"); //上报主题长度 "/sys/101/030200001/thing/"=25Byte "event/post"=10Byte + break; + case event_pub_step2: + //LTE_Send("/sys/101/030200001/thing/event/post"); + LTE_Send("/sys/101/%s/thing/event/post", BMS_SN); //上报的主题 (只有这个不用换新行) + break; + case event_pub_step3: + if(pre_sleep_flag == 3) //启动休眠true HappenTimeLTESleeptrue 8+14 + { + LTE_Send("AT+CMQTTPAYLOAD=0,%u\r\n", uint_str_len(sleepOn_time)+4+10+8+9+2); //上报内容长度 = sleepOn_time长度+true长度4+时间名长度10+休眠名长度8+固定字符长度9+回车2 + } + else if(pre_sleep_flag == 0xAA) //退出休眠false + { + LTE_Send("AT+CMQTTPAYLOAD=0,%u\r\n", uint_str_len(sleepOff_time)+5+10+8+9+2); //上报内容长度 = sleepOff_time长度+false长度5+时间名长度10+休眠名长度8+固定字符长度9+回车2 + } + else if(incident_flag == 1) //上报true + { + LTE_Send("AT+CMQTTPAYLOAD=0,%u\r\n", incident_len+4+10+9+2); //上报内容长度 = [时间长度]+true长度4+时间名长度10+[事件名长度]+固定字符长度9+回车2 + } + else if(incident_flag == 2) //上报false + { + LTE_Send("AT+CMQTTPAYLOAD=0,%u\r\n", incident_len+5+10+9+2); //上报内容长度 = [时间长度]+false长度5+时间名长度10+[事件名长度]+固定字符长度9+回车2 + } + break; + case event_pub_step4: + if(pre_sleep_flag == 3) //启动休眠true + { + LTE_Send("{\"HappenTime\":%u,\"LTESleep\":true}\r\n", sleepOn_time); + } + else if(pre_sleep_flag == 0xAA) //退出休眠false + { + LTE_Send("{\"HappenTime\":%u,\"LTESleep\":false}\r\n", sleepOff_time); + } + else if(incident_flag == 1) //上报true + { + LTE_Send("{\"HappenTime\":%u,\"%s\":true}\r\n", incident_time, incident_str); + } + else if(incident_flag == 2) //上报false + { + LTE_Send("{\"HappenTime\":%u,\"%s\":false}\r\n", incident_time, incident_str); + } + break; + case event_pub_step5: + LTE_Send("AT+CMQTTPUB=0,1,30\r\n"); //至少上报1次+30s内等待服务器回复 + break; + default: + LTE_step = event_pub_step1; //非法值改为第一步 + break; + } + } + //0xA1.立即回复写[服务] + else if(LTE_status == srvc_pub) + { + LTEStatus_flg = 1; + strcpy(LTEStatus_str, "reply setService"); + + putSrvc_reply_count++; + //尝试1次重新回复 + if(putSrvc_reply_count == 10) + { + LTE_step = srvc_pub_step1; + } + //仍然失败退出回复 + else if(putSrvc_reply_count >= 20) + { + LTE_status = ask_lbs; + LTE_step = ask_lbs_step1; //回复写[属性]完成，跳转：正常流程第一步 + + putSrvc_reply_flg = 0; + putSrvc_reply_count = 0; + } + + switch(LTE_step) //srvc_pub_step1~srvc_pub_step5 + { + case srvc_pub_step1: + LTE_Send("AT+CMQTTTOPIC=0,52\r\n"); //上报主题长度 "/sys/101/2025071201000023/thing/"=32Byte "service/invoke_reply"=20Byte + break; + case srvc_pub_step2: + //LTE_Send("/sys/101/2025071201000023/thing/service/invoke_reply"); + LTE_Send("/sys/101/%s/thing/service/invoke_reply", BMS_SN); //上报的主题 (只有这个不用换新行) + break; + case srvc_pub_step3: + if(putSrvc_reply_flg == 1) + { + LTE_Send("AT+CMQTTPAYLOAD=0,%u\r\n", ID_len+putSrvc_reply_namelen+putSrvc_reply_strlen+28+2); //上报内容长度 = 数据长度+固定字符长度+回车 + } + else if(putSrvc_reply_flg == 0xAA) + { + LTE_Send("AT+CMQTTPAYLOAD=0,%u\r\n", ID_len+29+2); //上报内容长度 = 数据长度+固定字符长度+回车 + } + else if(putSrvc_reply_flg == 0xBB) + { + LTE_Send("AT+CMQTTPAYLOAD=0,%u\r\n", ID_len+29+2); //上报内容长度 = 数据长度+固定字符长度+回车 + } + break; + case srvc_pub_step4: + if(putSrvc_reply_flg == 1) //正确 + { + //{"request_id":"123124sdf","code":0,"PutForceOn":"close"} + LTE_Send("{\"request_id\":\"%s\",\"code\":0,%s:%s}\r\n", ID_str, putSrvc_reply_namestr, putSrvc_reply_str); + } + else if(putSrvc_reply_flg == 0xAA) //错误-设备无该属性 + { + //{"request_id":"123124sdf","code":6411} + LTE_Send("{\"request_id\":\"%s\",\"code\":6411}\r\n", ID_str); + } + else if(putSrvc_reply_flg == 0xBB) //错误-设备拒绝执行 + { + //{"request_id":"123124sdf","code":6405} + LTE_Send("{\"request_id\":\"%s\",\"code\":6405}\r\n", ID_str); + } + break; + case srvc_pub_step5: + LTE_Send("AT+CMQTTPUB=0,1,30\r\n"); //至少上报1次+30s内等待服务器回复 + break; + default: + LTE_step = srvc_pub_step1; //非法值改为第一步 + break; + } + } + //0xA2.立即回复写[属性] + else if(LTE_status == setPara_pub) + { + LTEStatus_flg = 1; + strcpy(LTEStatus_str, "reply setPara"); + + setPara_reply_count++; + //尝试1次重新回复 + if(setPara_reply_count == 10) + { + LTE_step = setPara_pub_step1; + } + //仍然失败退出回复 + else if(setPara_reply_count >= 20) + { + LTE_status = ask_lbs; + LTE_step = ask_lbs_step1; //回复写[属性]完成，跳转：正常流程第一步 + + setPara_reply_flg = 0; + setPara_reply_count = 0; + } + + switch(LTE_step) //setPara_pub_step1~setPara_pub_step5 + { + case setPara_pub_step1: + LTE_Send("AT+CMQTTTOPIC=0,43\r\n"); //上报主题长度 "/sys/101/030200001/thing/"=25Byte "property/set_reply"=18Byte + break; + case setPara_pub_step2: + //LTE_Send("/sys/101/030200001/thing/property/set_reply"); + LTE_Send("/sys/101/%s/thing/property/set_reply", BMS_SN); //上报的主题 (只有这个不用换新行) + break; + case setPara_pub_step3: + if(setPara_reply_flg == 1) //正确 + { + LTE_Send("AT+CMQTTPAYLOAD=0,%u\r\n", ID_len+uint_str_len(setPara_reply_num+protocol_reply_flg)+setPara_reply_sumlen+47+2); //上报内容长度 = ID长度+num长度+数据长度+固定字符长度+回车 + } + else if(setPara_reply_flg == 0xAA) + { + LTE_Send("AT+CMQTTPAYLOAD=0,%u\r\n", ID_len+29+2); //上报内容长度 = 数据长度+固定字符长度+回车 + } + else if(setPara_reply_flg == 0xBB) + { + LTE_Send("AT+CMQTTPAYLOAD=0,%u\r\n", ID_len+29+2); //上报内容长度 = 数据长度+固定字符长度+回车 + } + break; + case setPara_pub_step4: + if(setPara_reply_flg == 1) //正确 + { + uint8_t i; + + //{"request_id":"123124sdf","code":0,"get_num":2,"data":{"POV_Vol":250,"COV_Vol":3600}} + LTE_Send("{\"request_id\":\"%s\",\"code\":0,\"set_num\":%hu,\"data\":", ID_str, setPara_reply_num+protocol_reply_flg); + LTE_Send("{"); + for(i=0;i= 20) + { + LTE_status = ask_lbs; + LTE_step = ask_lbs_step1; //回复写[属性]完成，跳转：正常流程第一步 + + getPara_reply_flg = 0; + getPara_reply_count = 0; + } + + switch(LTE_step) //getPara_pub_step1~getPara_pub_step5 + { + case getPara_pub_step1: + LTE_Send("AT+CMQTTTOPIC=0,43\r\n"); //上报主题长度 "/sys/101/030200001/thing/"=25Byte "property/get_reply"=18Byte + break; + case getPara_pub_step2: + //LTE_Send("/sys/101/030200001/thing/property/get_reply"); + LTE_Send("/sys/101/%s/thing/property/get_reply", BMS_SN); //上报的主题 (只有这个不用换新行) + break; + case getPara_pub_step3: + if(getPara_reply_flg == 1) + { + LTE_Send("AT+CMQTTPAYLOAD=0,%u\r\n", ID_len+uint_str_len(getPara_reply_num+protocol_reply_flg)+getPara_reply_sumlen+47+2); //上报内容长度 = ID长度+num长度+数据长度+固定字符长度+回车 //数据长度是指{}内的长度 + } + else if(getPara_reply_flg == 0xAA) + { + LTE_Send("AT+CMQTTPAYLOAD=0,%u\r\n", ID_len+29+2); //上报内容长度 = 数据长度+固定字符长度+回车 + } + break; + case getPara_pub_step4: + if(getPara_reply_flg == 1) //正确 + { + uint8_t i; + + //{"request_id":"123124sdf","code":0,"get_num":2,"data":{"POV_Vol":250,"COV_Vol":3600}} + LTE_Send("{\"request_id\":\"%s\",\"code\":0,\"get_num\":%hu,\"data\":", ID_str, getPara_reply_num+protocol_reply_flg); + LTE_Send("{"); + for(i=0;i= 20) + { + LTE_status = ask_lbs; + LTE_step = ask_lbs_step1; //回复OTA升级完成，跳转：正常流程第一步 + + otaFine_reply_count = 0; + } + + switch(LTE_step) //ota_fine_pub_step1~ota_fine_pub_step5 + { + case ota_fine_pub_step1: + LTE_Send("AT+CMQTTTOPIC=0,32\r\n"); //上报主题长度 23+9=32Byte + break; + case ota_fine_pub_step2: + LTE_Send("/ota/device/inform/101/%s", BMS_SN); //上报的主题 (只有这个不用换新行) + break; + case ota_fine_pub_step3: + LTE_Send("AT+CMQTTPAYLOAD=0,12\r\n"); //上报内容长度 = 数据长度+固定字符长度+回车 + break; + case ota_fine_pub_step4: + if(LTE_OTA_fineFlag == 0xAA) + { + LTE_Send("{\"code\":0}\r\n"); //升级成功 + } + else + { + LTE_Send("{\"code\":6}\r\n"); //仍保持原程序 + } + break; + case ota_fine_pub_step5: + LTE_Send("AT+CMQTTPUB=0,1,30\r\n"); //至少上报1次+30s内等待服务器回复 + break; + default: + LTE_step = ota_fine_pub_step1; //非法值改为第一步 + break; + } + } + + } +} +#endif + diff --git a/MOUDLE/LBS_Transmit.c b/MOUDLE/LBS_Transmit.c new file mode 100644 index 0000000..fcff2df --- /dev/null +++ b/MOUDLE/LBS_Transmit.c @@ -0,0 +1,120 @@ +/** + ****************************************************************************** + * @file LBS_Transmit.c + * @author + * @version + * @date + * @brief + ****************************************************************************** + * @attention + * + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" +#include "global.h" +#include +#include + + +// PI定义 +#define M_PI 3.1415926535897932384626433832795 + +// 常量定义 +#define EARTH_RADIUS 6378245.0 // 地球长半径 +#define EE 0.00669342162296594323 // 偏心率平方 + + +/** + * @brief 检查坐标是否在中国大陆以外 + * @return 1:境外, 0:境内 + */ +static int is_out_of_china(double lon, double lat) +{ + if (lon < 72.004 || lon > 137.8347) + { + return 1; + } + if (lat < 0.8293 || lat > 55.8271) + { + return 1; + } + + return 0; +} + +/** + * @brief 纬度转换辅助函数 + */ +static double transform_lat(double x, double y) +{ + double ret = -100.0 + 2.0 * x + 3.0 * y + 0.2 * y * y + 0.1 * x * y + 0.2 * sqrt(fabs(x)); + ret += (20.0 * sin(6.0 * x * M_PI) + 20.0 * sin(2.0 * x * M_PI)) * 2.0 / 3.0; + ret += (20.0 * sin(y * M_PI) + 40.0 * sin(y / 3.0 * M_PI)) * 2.0 / 3.0; + ret += (160.0 * sin(y / 12.0 * M_PI) + 320 * sin(y * M_PI / 30.0)) * 2.0 / 3.0; + return ret; +} + +/** + * @brief 经度转换辅助函数 + */ +static double transform_lon(double x, double y) +{ + double ret = 300.0 + x + 2.0 * y + 0.1 * x * x + 0.1 * x * y + 0.1 * sqrt(fabs(x)); + ret += (20.0 * sin(6.0 * x * M_PI) + 20.0 * sin(2.0 * x * M_PI)) * 2.0 / 3.0; + ret += (20.0 * sin(x * M_PI) + 40.0 * sin(x / 3.0 * M_PI)) * 2.0 / 3.0; + ret += (150.0 * sin(x / 12.0 * M_PI) + 300.0 * sin(x / 30.0 * M_PI)) * 2.0 / 3.0; + return ret; +} + +/** + * @brief GCJ-02转WGS84坐标系 + * @param gcj_lon GCJ-02经度 + * @param gcj_lat GCJ-02纬度 + * @param wgs_lon WGS84经度输出指针 + * @param wgs_lat WGS84纬度输出指针 + * @note 迭代7次，精度约0.1-0.5米 + */ +void gcj02_to_wgs84(double gcj_lon, double gcj_lat, double *wgs_lon, double *wgs_lat) +{ + //如果坐标不在中国大陆，直接返回原坐标 + if(is_out_of_china(gcj_lon, gcj_lat)) + { + *wgs_lon = gcj_lon; + *wgs_lat = gcj_lat; + return; + } + + //使用迭代法进行转换（7次迭代足够精确） + double d_lon = 0.0, d_lat = 0.0; + double tmp_lon = gcj_lon, tmp_lat = gcj_lat; + + for(int i = 0; i < 7; i++) + { + //计算当前WGS84坐标转GCJ02的偏移 + double delta_lat = transform_lat(tmp_lon - 105.0, tmp_lat - 35.0); + double delta_lon = transform_lon(tmp_lon - 105.0, tmp_lat - 35.0); + + double rad_lat = tmp_lat * M_PI / 180.0; + double magic = sin(rad_lat); + magic = 1 - EE * magic * magic; + double sqrt_magic = sqrt(magic); + + delta_lat = (delta_lat * 180.0) / ((EARTH_RADIUS * (1 - EE)) / (magic * sqrt_magic) * M_PI); + delta_lon = (delta_lon * 180.0) / (EARTH_RADIUS / sqrt_magic * cos(rad_lat) * M_PI); + + // 计算与目标GCJ02坐标的差值 + d_lat = gcj_lat - (tmp_lat + delta_lat); + d_lon = gcj_lon - (tmp_lon + delta_lon); + + // 更新WGS84坐标估计 + tmp_lat += d_lat; + tmp_lon += d_lon; + } + + *wgs_lon = tmp_lon; + *wgs_lat = tmp_lat; +} + diff --git a/MOUDLE/MBO26A.c b/MOUDLE/MBO26A.c new file mode 100644 index 0000000..d3bad79 --- /dev/null +++ b/MOUDLE/MBO26A.c @@ -0,0 +1,1407 @@ +/** + ****************************************************************************** + * @file MBO26A.c + * @author + * @version + * @date + * @brief + ****************************************************************************** + * @attention + * + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" +#include "global.h" +#include "string.h" +#include +#include + + +//固定值 +const char* Status[2] = {"false", "true"}; //0对应false, 1对应true + +//在global.c赋值，或在被写入后更新 +char BMS_SN[10]; //9Byte +char PACK_SN[16]; //1~15Byte +char FirmwareVersion[11];//"4.00.00.00" 7~10Byte +char HardwareVersion[6]; //"6.3.L" 5Byte +char ScreenVersion[6]; //"03513" 5Byte + + +//读写参数功能相关 +char params_str[600]; //原始数据字符串 + +const char* putSrvc_reply_namestr; //写服务的名字字符串 +const char* putSrvc_reply_str; //写服务的字符串格式 +uint8_t putSrvc_reply_flg; //写服务回复标志 接收到ID号，就要以ID号的格式返回 + +const char* setPara_reply_name[SETPARA_SUM]; //写属性的名字字符串 +uint16_t setPara_reply_temp[SETPARA_SUM]; //写属性的数值 +uint8_t setPara_reply_pm[SETPARA_SUM]; //数值的正负 0：正数 1：负数 2：true 3：false +uint8_t setPara_reply_flg; //写属性回复标志 1:回复成功 0xAA:设备无所有要写的属性 0xBB:值不在范围，设备拒绝执行 +uint8_t setPara_reply_num; //写属性回复个数 + +const char* getPara_reply_name[GETPARA_SUM]; //读属性的名字字符串 +uint16_t getPara_reply_temp[GETPARA_SUM]; //读属性的数值 +uint8_t getPara_reply_pm[GETPARA_SUM]; //数值的正负 0：正数 1：负数 2：true 3：false +uint8_t getPara_reply_flg; //读属性回复标志 1:回复成功 0xAA:设备无所有要读的属性 +uint8_t getPara_reply_num; //读属性回复个数 + +uint8_t protocol_reply_flg; //协议在回复内容里的标志 +uint8_t protocol_reply_index; //协议在回复内容里的位置 + + +#if BLE_Conn +//通用定义 +#define PIN_BLE_RST GPIO_Pin_12 //PC12 0:不做处理 1:蓝牙复位 + +#define BLE_UART UART4 +#define BLE_Send BLE_printf + +#define BLE_MON_CNT 6000 //6000*10ms = 60s +#define BLE_RX_BUF_LEN 256 //接收的最大长度，实际244Byte +#define BLE_TX_BUF_LEN 256 //发送的最大长度，实际244Byte +#define BLE_ORDER_LEN 256 //回复指令的缓冲区的最大长度 + +#define SETPARA_SUM 34 //可写参数总个数 +#define GETPARA_SUM 34 //可读参数总个数 + +char BLE_Rx_Buf[BLE_RX_BUF_LEN]; +char BLE_Tx_Buf[BLE_TX_BUF_LEN]; +char BLE_buffer[BLE_ORDER_LEN]; + +uint16_t BLE_Rx_BufIndex; +uint16_t BLE_Moni_Count; + + +//状态/保护/报警的字符串：false/true +//固定发： +//状态 +const char* BLE_ChargeStatus_str; +const char* BLE_DischargeStatus_str; +const char* BLE_PreChargeStatus_str; +const char* BLE_ChgMosStatus_str; +const char* BLE_DsgMosStatus_str; +const char* BLE_PchgMosStatus_str; +const char* BLE_ChgLimitStatus_str; +const char* BLE_BalanceStatus_str; +//出现才发： +uint8_t BLE_SendFlag; //bit0:发特殊状态 bit1:发保护 bit2:发报警 +uint8_t BLE_SendFlag_old; //已发出则对应bit置1 +//特殊状态 +uint8_t BLE_SendStatus[9]; //出现则赋值1，否则赋值0 +//保护 +uint8_t BLE_SendProtect_Vol[6]; +uint8_t BLE_SendProtect_Cur[5]; +uint8_t BLE_SendProtect_Temp[12]; +//报警 +uint8_t BLE_SendWarning_Vol[4]; +uint8_t BLE_SendWarning_Cur[2]; +uint8_t BLE_SendWarning_Temp[12]; + + +uint8_t BLE_READYflag; //蓝牙模块准备就绪的标志 +uint8_t BLE_READYcount; //开机后最久等待3s，一直不收到也READY + +uint8_t BLE_Onflag; //蓝牙成功连接的标志 + +uint8_t BLE_status; //执行内容 0:持续上报[属性] +uint8_t BLE_step; //执行步骤 0:第一部分 1:第二部分 …… + +uint8_t BLE_Check_Flag; //蓝牙无设备连接时，在主程序里定时检查蓝牙 + +uint8_t BLE_RST_Flag; //蓝牙无响应的重启标志 +uint8_t BLE_RST_count; //重启的等待计数 + + +//BLE专用的printf函数 +int BLE_printf(const char *fmt, ...) +{ + va_list args; + va_start(args, fmt); + int len = vsnprintf(BLE_Tx_Buf, sizeof(BLE_Tx_Buf), fmt, args); + va_end(args); + + for(int i = 0; i < len; i++) + { + while(!(UART4->SR & USART_SR_TXE)); // 等待发送完成 + UART4->DR = BLE_Tx_Buf[i]; + } + + return len; +} + +//相关引脚初始化 +void BLE_IO_Init(void) +{ + //初始化引脚 + GPIO_InitTypeDef GPIO_InitStructure; + + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC , ENABLE); + + GPIO_InitStructure.GPIO_Pin = PIN_BLE_RST; //蓝牙复位控制引脚 + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOC, &GPIO_InitStructure); + + GPIO_ResetBits(GPIOC, PIN_BLE_RST); //蓝牙复位控制脚，默认关闭状态 +} + +//开机 +void BLE_Open(void) +{ + //预留 +} + +//关机 +void BLE_Close(void) +{ + //预留 +} + +//复位 +void BLE_Reset(void) +{ + //发软件重启AT指令 + BLE_Send("AT+REBOOT=1\r\n"); + + BLE_READYflag = 1; + BLE_READYcount = 0; +} + +//清空标志 +void BLE_ClearFlg(void) +{ + BLE_Onflag = 0; + + BLE_status = 0; + BLE_step = 0; + + setPara_reply_flg = 0; + getPara_reply_flg = 0; +} + +//清空接收缓冲区 +void BLE_ClearBuf(void) +{ + BLE_Rx_BufIndex = 0; + memset(BLE_Rx_Buf, 0, BLE_RX_BUF_LEN); +} + +//初始化通讯 +void BLE_Init(void) +{ + BLE_ClearFlg(); + BLE_ClearBuf(); + + BLE_Moni_Count = BLE_MON_CNT; + if(BLE_READYflag == 0) + { + uf_UART4_Init(9600); + } + else + { + uf_UART4_Init(115200); + } +} + +//一定时间没有连接任何设备，初始化通讯，并再次更新名称 +void BLE_TIM_Moni(void) +{ + if(BLE_Onflag == 0) //未连接蓝牙 + { + BLE_Moni_Count--; + if(BLE_Moni_Count == 0) + { + BLE_Init(); + BLE_Check_Flag = 1; + } + } + else + { + BLE_Moni_Count = BLE_MON_CNT; + } +} + +//设置蓝牙模块波特率 +void BLE_SetBaud( u32 bound ) +{ + BLE_Send("AT+UART=5\r\n"); + delay_ms(50); + uf_UART4_Init(115200); +} + +//检测蓝牙名称是否和SN号一致，不一致则修改 +void BLE_CheckName(void) +{ + BLE_ClearBuf(); + + //询问蓝牙名称 + BLE_Send("AT+NAME?\r\n"); + delay_ms(100); + + //收到回复 + if(strstr(BLE_Rx_Buf, "+NAME:")) + { + //名称有误，发送修改名称的AT指令 + if((strstr(BLE_Rx_Buf, "Ricn_") == 0) || (strstr(BLE_Rx_Buf, BMS_SN) == 0)) + { + BLE_ClearBuf(); + + //BLE_Send("AT+NAME=Ricn_052200021"); + BLE_Send("AT+NAME=Ricn_%s\r\n", BMS_SN); + delay_ms(50); + + BLE_Reset(); //重启以启用该名称 + } + } + else + { + BLE_RST_count++; + if(BLE_RST_count > 3) //3min + { + BLE_RST_Flag = 1; + } + } +} + +//写SN号时，直接同步修改蓝牙名称 +void BLE_WriteName(void) +{ + //检查一遍名称，不同就执行写入 + BLE_CheckName(); +} + +//蓝牙写指令 +void BLE_PUTSRVC(void) +{ + if(strstr(BLE_Rx_Buf, "\"data\":{") && strstr(BLE_Rx_Buf, "}}")) + { + uint8_t len = 0; //字符串长度 + + //获取原始数据，包括'{''}' + const char* paramsKey = "\"data\":"; + char* paramsStart = strstr(BLE_Rx_Buf, paramsKey); paramsStart += strlen(paramsKey); + char* paramsEnd = strchr(paramsStart, '}'); + len = paramsEnd - paramsStart; + if(len > sizeof(params_str)-2) //防溢出 + { + len = sizeof(params_str)-2; + } + strncpy(params_str, paramsStart, len); + params_str[len] = '}'; + params_str[len+1] = '\0'; + + + if(strstr(params_str, "\"PutForceOn\"")) + { + putSrvc_reply_flg = 1; + putSrvc_reply_namestr = "\"PutForceOn\""; + + if(strstr(params_str, "\"open\"")) + { + //当前总体和单体欠压的报警/保护位都置0 + bmsMem.bStatus1 &= ~0x0202; + bmsMem.bStatus3 &= ~0x0A00; + //状态置1，更新计时起点 + bmsMem.balanceStatus |= 0x0020; + if(LSEErrFlag!=1) + { + uvofftimecount = RTC_GetCounter(); + uvofftime = 300; + } + else + { + uvoff_Moni_Count = UVOff_MON_CNT; + } + + putSrvc_reply_str = "\"open\""; + } + else if(strstr(params_str, "\"close\"")) + { + bmsMem.balanceStatus &= 0xffdf; + + putSrvc_reply_str = "\"close\""; + } + else + { + putSrvc_reply_flg = 0xBB; //设备拒绝执行(内容有误) + } + } + else + { + putSrvc_reply_flg = 0xAA; //设备无该属性 + } + } + else + { + putSrvc_reply_flg = 0xBB; //设备拒绝执行 + } +} + +//蓝牙写参数 +void BLE_SETPARA(void) +{ + if(strstr(BLE_Rx_Buf, "\"data\":{") && strstr(BLE_Rx_Buf, "}}")) + { + char para_str[6]; //0~65535 或 -32768~32767 + uint8_t len = 0; //字符串长度 + uint16_t temp; //无符号过程量 + + //获取原始数据，包括'{''}' + const char* paramsKey = "\"data\":"; + char* paramsStart = strstr(BLE_Rx_Buf, paramsKey); paramsStart += strlen(paramsKey); + char* paramsEnd = strchr(paramsStart, '}'); + len = paramsEnd - paramsStart; + if(len > sizeof(params_str)-2) //防溢出 + { + len = sizeof(params_str)-2; + } + strncpy(params_str, paramsStart, len); + params_str[len] = '}'; + params_str[len+1] = '\0'; + + + //识别存在的参数，并给予对应值 + setPara_reply_num = 0; + + if(strstr(params_str, "\"Protocol\"")) //写协议 + { + //获取参数值 + len = GetStr("\"Protocol\":", ',', '}', params_str, para_str); + sscanf(para_str, "%hu", &temp); + + //符合范围的放入 + if(((int)temp >= 0) && (temp <= ProtocolSum) && (len > 0)) //0~38 + { + protocol = temp; + + EEPROM_WrMulByte(EE_PROTOCOL,&protocol); + delay_ms(5); + uf_CAN1_Init();//CAN的波特率更新 + //SCR_DispProcotol(); //屏幕显示更新 + + protocol_reply_flg = 1; + protocol_reply_index = setPara_reply_num; + + //准备回复 + setPara_reply_name[setPara_reply_num] = "Protocol"; + setPara_reply_temp[setPara_reply_num] = temp; + setPara_reply_num++; + } + else + { + setPara_reply_flg = 0xBB; //参数值超出范围，设备拒绝执行 + } + } + + if(setPara_reply_num > 0) + { + setPara_reply_flg = 1; //正常回复 + } + else if(setPara_reply_flg != 0xBB) //无任何符合的值&不是因为参数不符合范围 + { + setPara_reply_flg = 0xAA; //设备无该属性 + } + } + else + { + setPara_reply_flg = 0xBB; //设备拒绝执行 + } +} + +//蓝牙读参数 +void BLE_GETPARA(void) +{ + if(strstr(BLE_Rx_Buf, "\"params\":[") && strstr(BLE_Rx_Buf, "]}")) + { + uint16_t len = 0; //字符串长度 + + //获取原始数据 + const char* paramsKey = "\"params\":["; + char* paramsStart = strstr(BLE_Rx_Buf, paramsKey); paramsStart += strlen(paramsKey); + char* paramsEnd = strchr(paramsStart, ']'); + len = paramsEnd - paramsStart; + if(len > sizeof(params_str)-1) //防溢出 + { + len = sizeof(params_str)-1; + } + strncpy(params_str, paramsStart, len); + params_str[len] = '\0'; + + //识别存在的参数，并给予对应值 + getPara_reply_num = 0; + + if(strstr(params_str, "\"Protocol\"")) //读协议 + { + protocol_reply_flg = 1; + protocol_reply_index = getPara_reply_num; + + //准备回复 + getPara_reply_name[getPara_reply_num] = "Protocol"; + getPara_reply_temp[getPara_reply_num] = protocol; + getPara_reply_num++; + } + + if(getPara_reply_num > 0) + { + getPara_reply_flg = 1; //回复 + } + else //无任何符合的值 + { + getPara_reply_flg = 0xAA; //设备无该属性 + } + } + else + { + getPara_reply_flg = 0xBB; //设备拒绝执行 + } +} + +//接收数据，在串口中断执行 +void BLE_IT_Receive(void) +{ + uint8_t received_byte = USART_ReceiveData(BLE_UART); + + if(BLE_Rx_BufIndex < BLE_RX_BUF_LEN - 1) + { + BLE_Rx_Buf[BLE_Rx_BufIndex] = received_byte; + BLE_Rx_BufIndex++; + } + else + { + BLE_ClearBuf(); + } +} + +//处理数据，接收报文识别后执行 +//波特率115200 +void BLE_IT_Update(void) +{ + if(BLE_READYflag == 0) + { + if(strstr(BLE_Rx_Buf, "+READY")) //上电后，需收到+READY后才能执行指令 + { + BLE_READYcount = 0; + BLE_READYflag = 1; + + BLE_SetBaud(115200); //设置蓝牙模块波特率 + BLE_CheckName(); //检查蓝牙名称是否和SN号一致 + } + } + else + { + if(strstr(BLE_Rx_Buf, "+CONNECTED")) //连上蓝牙 + { + BLE_ClearBuf(); + + BLE_Onflag = 1; + BLE_status = 0; //从上报[属性]开始 + } + if(strstr(BLE_Rx_Buf, "+DISCONN")) //断开蓝牙 + { + BLE_ClearBuf(); + + BLE_Onflag = 0; + } + + if(BLE_Onflag == 1) + { + if(strstr(BLE_Rx_Buf,"\"dataType\":\"0x03\"")) //收到"0x03"开始解析数据 写指令 + { + BLE_status = 1; + BLE_PUTSRVC(); + + BLE_ClearBuf(); + } + else if(strstr(BLE_Rx_Buf,"\"dataType\":\"0x04\"")) //收到"0x04"开始解析数据 写参数 + { + BLE_status = 2; + BLE_SETPARA(); + + BLE_ClearBuf(); + } + else if(strstr(BLE_Rx_Buf,"\"dataType\":\"0x05\"")) //收到"0x05"开始解析数据 读参数 + { + BLE_status = 3; + BLE_GETPARA(); + + BLE_ClearBuf(); + } + } + } +} + +//根据当前已知信息，选择接下来要执行的指令，0.1s执行1次 +void BLE_IQ_Update(void) +{ + if(BLE_READYflag == 0) + { + BLE_READYcount++; + if(BLE_READYcount > 3*20) //延时判断3s + { + BLE_READYcount = 0; + BLE_READYflag = 1; + + BLE_SetBaud(115200); //设置蓝牙模块波特率 + BLE_CheckName(); //检查蓝牙名称是否和SN号一致 + } + } + else if(BLE_Onflag == 1) //已连接 + { + if(BLE_status == 0) //正常上报采集数据 + { + BLE_step++; + + if(BLE_step == 3) //状态：固定发送 + { + //更新true/false + BLE_ChargeStatus_str = Status[ChargeStatus]; + BLE_DischargeStatus_str = Status[DischargeStatus]; + BLE_PreChargeStatus_str = Status[PreChargeStatus]; + BLE_ChgMosStatus_str = Status[ChgMosStatus]; + BLE_DsgMosStatus_str = Status[DsgMosStatus]; + BLE_PchgMosStatus_str = Status[PchgMosStatus]; + BLE_ChgLimitStatus_str = Status[ChgLimitStatus]; + BLE_BalanceStatus_str = Status[BalanceStatus]; + } + else if(BLE_step == 8) //特殊状态：当前存在任一状态才发送 + { + if(((bmsMem.bStatus2 & 0x00C0) != 0) || ((bmsMem.temperaStatus & 0x0080) != 0) || ((bmsMem.balanceStatus & 0x07E0) != 0)) + { + BLE_SendFlag |= BIT0; + + //更新1:true/0:false + BLE_SendStatus[0] = LockOCC; + BLE_SendStatus[1] = LockOCD1; + BLE_SendStatus[2] = LockOCD2; + BLE_SendStatus[3] = LockSP; + BLE_SendStatus[4] = LockSC; + BLE_SendStatus[5] = ChgMosFault; + BLE_SendStatus[6] = DsgMosFault; + BLE_SendStatus[7] = DOStatus; + BLE_SendStatus[8] = ForceOffUV; + } + else + { + BLE_SendFlag &= ~BIT0; + } + + //if(((bmsMem.bStatus1 & 0x077f) != 0) || ((bmsMem.bStatus2 & 0x00ff) !=0) || ((bmsMem.bStatus3 & 0x0008) !=0) || ((bmsMem.temperaStatus & 0x0f7f) !=0)) + if(((bmsMem.bStatus1 & 0x077f) != 0) || ((bmsMem.bStatus2 & 0x00f0) !=0) || ((bmsMem.bStatus3 & 0x0008) !=0) || ((bmsMem.temperaStatus & 0x0070) !=0)) + { + BLE_SendFlag |= BIT1; + + //更新1:true/0:false + BLE_SendProtect_Vol[0] = PackOV; + BLE_SendProtect_Vol[1] = PackUV; + BLE_SendProtect_Vol[2] = CellOV; + BLE_SendProtect_Vol[3] = CellUV; + BLE_SendProtect_Vol[4] = PF; + BLE_SendProtect_Vol[5] = L0V; + + BLE_SendProtect_Cur[0] = OCC; + BLE_SendProtect_Cur[1] = OCD1; + BLE_SendProtect_Cur[2] = OCD2; + BLE_SendProtect_Cur[3] = SP; + BLE_SendProtect_Cur[4] = SC; + } + else + { + BLE_SendFlag &= ~BIT1; + } + + if(((bmsMem.bStatus2 & 0x000f) !=0) || ((bmsMem.temperaStatus & 0x0f0f) !=0)) + { + BLE_SendFlag |= BIT2; + + //更新1:true/0:false + BLE_SendProtect_Temp[0] = McuOTC; + BLE_SendProtect_Temp[1] = McuOTD; + BLE_SendProtect_Temp[2] = McuUTC; + BLE_SendProtect_Temp[3] = McuUTD; + BLE_SendProtect_Temp[4] = AmbientOTC; + BLE_SendProtect_Temp[5] = AmbientOTD; + BLE_SendProtect_Temp[6] = AmbientUTC; + BLE_SendProtect_Temp[7] = AmbientUTD; + BLE_SendProtect_Temp[8] = MosOTC; + BLE_SendProtect_Temp[9] = MosOTD; + BLE_SendProtect_Temp[10] = MosUTC; + BLE_SendProtect_Temp[11] = MosUTD; + } + else + { + BLE_SendFlag &= ~BIT2; + } + + //if(((bmsMem.bStatus2 & 0xff00) !=0) || ((bmsMem.bStatus3 & 0x3f00) !=0) || ((bmsMem.temperaStatus & 0xf000) !=0)) + if((bmsMem.bStatus3 & 0x3f00) !=0) + { + BLE_SendFlag |= BIT3; + + //更新1:true/0:false + BLE_SendWarning_Vol[0] = PackOVWarning; + BLE_SendWarning_Vol[1] = PackUVWarning; + BLE_SendWarning_Vol[2] = CellOVWarning; + BLE_SendWarning_Vol[3] = CellUVWarning; + + BLE_SendWarning_Cur[0] = OCCWarning; + BLE_SendWarning_Cur[1] = OCDWarning; + } + else + { + BLE_SendFlag &= ~BIT3; + } + + if(((bmsMem.bStatus2 & 0xff00) !=0) || ((bmsMem.temperaStatus & 0xf000) !=0)) + { + BLE_SendFlag |= BIT4; + + //更新1:true/0:false + BLE_SendWarning_Temp[0] = McuOTCWarning; + BLE_SendWarning_Temp[1] = McuOTDWarning; + BLE_SendWarning_Temp[2] = McuUTCWarning; + BLE_SendWarning_Temp[3] = McuUTDWarning; + BLE_SendWarning_Temp[4] = AmbientOTCWarning; + BLE_SendWarning_Temp[5] = AmbientOTDWarning; + BLE_SendWarning_Temp[6] = AmbientUTCWarning; + BLE_SendWarning_Temp[7] = AmbientUTDWarning; + BLE_SendWarning_Temp[8] = MosOTCWarning; + BLE_SendWarning_Temp[9] = MosOTDWarning; + BLE_SendWarning_Temp[10] = MosUTCWarning; + BLE_SendWarning_Temp[11] = MosUTDWarning; + } + else + { + BLE_SendFlag &= ~BIT4; + } + } + } + } +} + +//该函数用于发送报文，0.1s执行1次 +void BLE_IQ_Transmit(void) +{ +// BLE_Rx_BufIndex = 0; +// memset(BLE_Rx_Buf, 0, BLE_RX_BUF_LEN); //填入前先清空 +// memset(BLE_Tx_Buf, 0, BLE_TX_BUF_LEN); + + /*未连接，定时检查*/ + if(BLE_Onflag == 0) + { + //定时询问蓝牙名称 + if(BLE_Check_Flag == 1) + { + BLE_Check_Flag = 0; + BLE_CheckName(); + } + //询问持续无回复，尝试重启 + else if(BLE_RST_Flag == 1) + { + BLE_RST_Flag = 0; + BLE_Reset(); + } + } + /*连接上了才会传数据*/ + else + { + /*定时上报[属性],每段不超过512字节*/ + if(BLE_status == 0) + { + if(BLE_step == 1) + { + //上报内容 %u:unsigned int %d:int %s:char + //第一帧 + //开头 25 + BLE_Send("{"); + BLE_Send("\"dataType\":\"0x01\","); + BLE_Send("\"data\":"); + //内容 130 + BLE_Send("{"); //1 + BLE_Send("\"BmsSN\":\"%s\",", BMS_SN); //5+4 + 9+2 + BLE_Send("\"PackSN\":\"%s\",", PACK_SN); //6+4 + 15+2 + if(ScreenVersion[0] == 0) + { + BLE_Send("\"FirmwareVersion\":\"%s\",", FirmwareVersion); //15+4 + 11+2 + BLE_Send("\"HardwareVersion\":\"%s\"}", HardwareVersion); //15+4 + 5+2 + } + else + { + BLE_Send("\"FirmwareVersion\":\"%s\",", FirmwareVersion); //15+4 + 11+2 + BLE_Send("\"HardwareVersion\":\"%s\",", HardwareVersion); //15+4 + 5+2 + BLE_Send("\"ScreenVersion\":\"%s\"}", ScreenVersion); //13+4 + 5+2 + } + //结尾 1 + BLE_Send("}"); + } + else if(BLE_step == 2) + { + //上报内容 %u:unsigned int %d:int %s:char + //第二帧 + //开头 25 + BLE_Send("{"); + BLE_Send("\"dataType\":\"0x01\","); + BLE_Send("\"data\":"); + //内容 167 + BLE_Send("{"); //1 + BLE_Send("\"PackVol\":%u,", bmsMem.packVoltage); //7+4 + 10 + BLE_Send("\"PackCur\":%d,", bmsMem.packCurrent); //7+4 + 10 + BLE_Send("\"VolMax\":%d,", cellVoltageMax); //6+4 + 5 + BLE_Send("\"VolMin\":%d,", cellVoltageMin); //6+4 + 5 + BLE_Send("\"VolMaxIndex\":%u,", bmsMem.cellVoltageMaxIndex); //11+4 + 2 + BLE_Send("\"VolMinIndex\":%u,", bmsMem.cellVoltageMinIndex); //11+4 + 2 + BLE_Send("\"FCC\":%u,", bmsMem.ncc/3600); //3+4 + 7 + BLE_Send("\"RCC\":%u,", bmsMem.rcc/3600); //3+4 + 7 + BLE_Send("\"SOC\":%u,", bmsMem.soc); //3+4 + 3 + BLE_Send("\"SOH\":%u,", bmsMem.soh); //3+4 + 3 + BLE_Send("\"CYC\":%u}", bmsMem.cycleCount); //3+4 + 5 + //结尾 1 + BLE_Send("}"); + } + else if(BLE_step == 3) + { + //上报内容 %u:unsigned int %d:int %s:char + //第四帧 + //开头 25 + BLE_Send("{"); + BLE_Send("\"dataType\":\"0x01\","); + BLE_Send("\"data\":"); + //内容 137 + BLE_Send("{"); //1 + BLE_Send("\"CellVol1\":%d,", cellVol[0]); //8+4 + 5 + BLE_Send("\"CellVol2\":%d,", cellVol[1]); //8+4 + 5 + BLE_Send("\"CellVol3\":%d,", cellVol[2]); //8+4 + 5 + BLE_Send("\"CellVol4\":%d,", cellVol[3]); //8+4 + 5 + BLE_Send("\"CellVol5\":%d,", cellVol[4]); //8+4 + 5 + BLE_Send("\"CellVol6\":%d,", cellVol[5]); //8+4 + 5 + BLE_Send("\"CellVol7\":%d,", cellVol[6]); //8+4 + 5 + BLE_Send("\"CellVol8\":%d}", cellVol[7]); //8+4 + 5 + //结尾 1 + BLE_Send("}"); + } + else if(BLE_step == 4) + { + //上报内容 %u:unsigned int %d:int %s:char + //第五帧 + //开头 25 + BLE_Send("{"); + BLE_Send("\"dataType\":\"0x01\","); + BLE_Send("\"data\":"); + //内容 144 + BLE_Send("{"); //1 + BLE_Send("\"CellVol9\":%d,", cellVol[8]); //8+4 + 5 + BLE_Send("\"CellVol10\":%d,", cellVol[9]); //9+4 + 5 + BLE_Send("\"CellVol11\":%d,", cellVol[10]); //9+4 + 5 + BLE_Send("\"CellVol12\":%d,", cellVol[11]); //9+4 + 5 + BLE_Send("\"CellVol13\":%d,", cellVol[12]); //9+4 + 5 + BLE_Send("\"CellVol14\":%d,", cellVol[13]); //9+4 + 5 + BLE_Send("\"CellVol15\":%d,", cellVol[14]); //9+4 + 5 + BLE_Send("\"CellVol16\":%d}", cellVol[15]); //9+4 + 5 + //结尾 1 + BLE_Send("}"); + } + else if(BLE_step == 5) + { + //上报内容 %u:unsigned int %d:int %s:char + //第五帧 + //开头 25 + BLE_Send("{"); + BLE_Send("\"dataType\":\"0x01\","); + BLE_Send("\"data\":"); + //内容 73 + BLE_Send("{"); //1 + BLE_Send("\"CellVol17\":%d,", cellVol[16]); //9+4 + 5 + BLE_Send("\"CellVol18\":%d,", cellVol[17]); //9+4 + 5 + BLE_Send("\"CellVol19\":%d,", cellVol[18]); //9+4 + 5 + BLE_Send("\"CellVol20\":%d}", cellVol[19]); //9+4 + 5 + //结尾 1 + BLE_Send("}"); + } + else if(BLE_step == 6) + { + //上报内容 %u:unsigned int %d:int %s:char + //第六帧 + //开头 25 + BLE_Send("{"); + BLE_Send("\"dataType\":\"0x01\","); + BLE_Send("\"data\":"); + //内容 111 + BLE_Send("{"); //1 + BLE_Send("\"MosT1\":%.1f,", (float)(bmsMem.afe_T1-2731)/10); //5+4 + 5 + BLE_Send("\"MosT2\":%.1f,", (float)(bmsMem.afe_T2-2731)/10); //5+4 + 5 + BLE_Send("\"AmbientT\":%.1f,", (float)(bmsMem.afe_T3-2731)/10); //8+4 + 5 + BLE_Send("\"BatteryT1\":%.1f,", (float)(bmsMem.mcu_T1-2731)/10); //9+4 + 5 + BLE_Send("\"BatteryT2\":%.1f,", (float)(bmsMem.mcu_T2-2731)/10); //9+4 + 5 + BLE_Send("\"BatteryT3\":%.1f,", (float)(bmsMem.mcu_T3-2731)/10); //9+4 + 5 + BLE_Send("\"BatteryT4\":%.1f}", (float)(bmsMem.mcu_T4-2731)/10); //9+4 + 5 + //结尾 1 + BLE_Send("}"); + } + else if(BLE_step == 7) + { + //上报内容 %u:unsigned int %d:int %s:char + //第三帧 + //开头 25 + BLE_Send("{"); + BLE_Send("\"dataType\":\"0x01\","); + BLE_Send("\"data\":"); + //内容 179 + BLE_Send("{"); //1 + BLE_Send("\"ChargeStatus\":%s,", BLE_ChargeStatus_str); //12+4 + 5 + BLE_Send("\"DischargeStatus\":%s,", BLE_DischargeStatus_str); //15+4 + 5 + BLE_Send("\"PreChargeStatus\":%s,", BLE_PreChargeStatus_str); //15+4 + 5 + BLE_Send("\"ChgMosStatus\":%s,", BLE_ChgMosStatus_str); //12+4 + 5 + BLE_Send("\"DsgMosStatus\":%s,", BLE_DsgMosStatus_str); //12+4 + 5 + BLE_Send("\"PchgMosStatus\":%s,", BLE_PchgMosStatus_str); //13+4 + 5 + BLE_Send("\"ChgLimitStatus\":%s,", BLE_ChgLimitStatus_str); //14+4 + 5 + BLE_Send("\"BalanceStatus\":%s}", BLE_BalanceStatus_str); //13+4 + 5 + //结尾 1 + BLE_Send("}"); + } + else if((BLE_step >= 8) && (BLE_step <= 21)) + { + if(((BLE_SendFlag & BIT0) != 0) && ((BLE_SendFlag_old & BIT0) == 0)) + { + uint8_t firstflag = 0; //当出现过第1个上传状态后置1 + + BLE_SendFlag_old |= BIT0; + + //上报内容 %u:unsigned int %d:int %s:char + //存在才发，第一帧 + //开头 + BLE_Send("{"); + BLE_Send("\"dataType\":\"0x01\","); + BLE_Send("\"data\":"); + //内容 + BLE_Send("{"); + //特殊状态 + if(BLE_SendStatus[0] != 0) + { + BLE_Send("\"LockOCC\":true"); + firstflag = 1; + } + if(BLE_SendStatus[1] != 0) + { + if(firstflag == 1) BLE_Send(","); + BLE_Send("\"LockOCD1\":true"); + firstflag = 1; + } + if(BLE_SendStatus[2] != 0) + { + if(firstflag == 1) BLE_Send(","); + BLE_Send("\"LockOCD2\":true"); + firstflag = 1; + } + if(BLE_SendStatus[3] != 0) + { + if(firstflag == 1) BLE_Send(","); + BLE_Send("\"LockSP\":true"); + firstflag = 1; + } + if(BLE_SendStatus[4] != 0) + { + if(firstflag == 1) BLE_Send(","); + BLE_Send("\"LockSC\":true"); + firstflag = 1; + } + if(BLE_SendStatus[5] != 0) + { + if(firstflag == 1) BLE_Send(","); + BLE_Send("\"ChgMosFault\":true"); + firstflag = 1; + } + if(BLE_SendStatus[6] != 0) + { + if(firstflag == 1) BLE_Send(","); + BLE_Send("\"DsgMosFault\":true"); + firstflag = 1; + } + if(BLE_SendStatus[7] != 0) + { + if(firstflag == 1) BLE_Send(","); + BLE_Send("\"DOStatus\":true"); + firstflag = 1; + } + if(BLE_SendStatus[8] != 0) + { + if(firstflag == 1) BLE_Send(","); + BLE_Send("\"ForceOffUV\":true"); + firstflag = 1; + } + BLE_Send("}"); + //结尾 + BLE_Send("}"); + } + else if(((BLE_SendFlag & BIT1) != 0) && ((BLE_SendFlag_old & BIT1) == 0)) + { + uint8_t firstflag = 0; //当出现过第1个上传状态后置1 + + BLE_SendFlag_old |= BIT1; + + //上报内容 %u:unsigned int %d:int %s:char + //存在才发，第三帧 + //开头 + BLE_Send("{"); + BLE_Send("\"dataType\":\"0x01\","); + BLE_Send("\"data\":"); + //内容 + BLE_Send("{"); + //电压保护 + if(BLE_SendProtect_Vol[0] != 0) + { + BLE_Send("\"PackOV\":true"); + firstflag = 1; + } + if(BLE_SendProtect_Vol[1] != 0) + { + if(firstflag == 1) BLE_Send(","); + BLE_Send("\"PackUV\":true"); + firstflag = 1; + } + if(BLE_SendProtect_Vol[2] != 0) + { + if(firstflag == 1) BLE_Send(","); + BLE_Send("\"CellOV\":true"); + firstflag = 1; + } + if(BLE_SendProtect_Vol[3] != 0) + { + if(firstflag == 1) BLE_Send(","); + BLE_Send("\"CellUV\":true"); + firstflag = 1; + } + if(BLE_SendProtect_Vol[4] != 0) + { + if(firstflag == 1) BLE_Send(","); + BLE_Send("\"PF\":true"); + firstflag = 1; + } + if(BLE_SendProtect_Vol[5] != 0) + { + if(firstflag == 1) BLE_Send(","); + BLE_Send("\"L0V\":true"); + firstflag = 1; + } + //电流保护 + if(BLE_SendProtect_Cur[0] != 0) + { + if(firstflag == 1) BLE_Send(","); + BLE_Send("\"OCC\":true"); + firstflag = 1; + } + if(BLE_SendProtect_Cur[1] != 0) + { + if(firstflag == 1) BLE_Send(","); + BLE_Send("\"OCD1\":true"); + firstflag = 1; + } + if(BLE_SendProtect_Cur[2] != 0) + { + if(firstflag == 1) BLE_Send(","); + BLE_Send("\"OCD2\":true"); + firstflag = 1; + } + if(BLE_SendProtect_Cur[3] != 0) + { + if(firstflag == 1) BLE_Send(","); + BLE_Send("\"SP\":true"); + firstflag = 1; + } + if(BLE_SendProtect_Cur[4] != 0) + { + if(firstflag == 1) BLE_Send(","); + BLE_Send("\"SC\":true"); + firstflag = 1; + } + BLE_Send("}"); + //结尾 + BLE_Send("}"); + } + else if(((BLE_SendFlag & BIT2) != 0) && ((BLE_SendFlag_old & BIT2) == 0)) + { + uint8_t firstflag = 0; //当出现过第1个上传状态后置1 + + BLE_SendFlag_old |= BIT2; + + //上报内容 %u:unsigned int %d:int %s:char + //存在才发，第三帧 + //开头 + BLE_Send("{"); + BLE_Send("\"dataType\":\"0x01\","); + BLE_Send("\"data\":"); + //内容 + BLE_Send("{"); + //温度保护 + if(BLE_SendProtect_Temp[0] != 0) + { + BLE_Send("\"McuOTC\":true"); + firstflag = 1; + } + if(BLE_SendProtect_Temp[1] != 0) + { + if(firstflag == 1) BLE_Send(","); + BLE_Send("\"McuOTD\":true"); + firstflag = 1; + } + if(BLE_SendProtect_Temp[2] != 0) + { + if(firstflag == 1) BLE_Send(","); + BLE_Send("\"McuUTC\":true"); + firstflag = 1; + } + if(BLE_SendProtect_Temp[3] != 0) + { + if(firstflag == 1) BLE_Send(","); + BLE_Send("\"McuUTD\":true"); + firstflag = 1; + } + if(BLE_SendProtect_Temp[4] != 0) + { + if(firstflag == 1) BLE_Send(","); + BLE_Send("\"AmbientOTC\":true"); + firstflag = 1; + } + if(BLE_SendProtect_Temp[5] != 0) + { + if(firstflag == 1) BLE_Send(","); + BLE_Send("\"AmbientOTD\":true"); + firstflag = 1; + } + if(BLE_SendProtect_Temp[6] != 0) + { + if(firstflag == 1) BLE_Send(","); + BLE_Send("\"AmbientUTC\":true"); + firstflag = 1; + } + if(BLE_SendProtect_Temp[7] != 0) + { + if(firstflag == 1) BLE_Send(","); + BLE_Send("\"AmbientUTD\":true"); + firstflag = 1; + } + if(BLE_SendProtect_Temp[8] != 0) + { + if(firstflag == 1) BLE_Send(","); + BLE_Send("\"MosOTC\":true"); + firstflag = 1; + } + if(BLE_SendProtect_Temp[9] != 0) + { + if(firstflag == 1) BLE_Send(","); + BLE_Send("\"MosOTD\":true"); + firstflag = 1; + } + //if(BLE_SendProtect_Temp[10] != 0) + //{ + // if(firstflag == 1) BLE_Send(","); + // BLE_Send("\"MosUTC\":true"); + // firstflag = 1; + //} + //if(BLE_SendProtect_Temp[11] != 0) + //{ + // if(firstflag == 1) BLE_Send(","); + // BLE_Send("\"MosUTD\":true"); + // firstflag = 1; + //} + BLE_Send("}"); + //结尾 + BLE_Send("}"); + } + else if(((BLE_SendFlag & BIT3) != 0) && ((BLE_SendFlag_old & BIT3) == 0)) + { + uint8_t firstflag = 0; //当出现过第1个上传状态后置1 + + BLE_SendFlag_old |= BIT3; + + //上报内容 %u:unsigned int %d:int %s:char + //存在才发，第五帧 + //开头 + BLE_Send("{"); + BLE_Send("\"dataType\":\"0x01\","); + BLE_Send("\"data\":"); + //内容 + BLE_Send("{"); + //电压报警 + if(BLE_SendWarning_Vol[0] != 0) + { + BLE_Send("\"PackOVWarning\":true"); + firstflag = 1; + } + if(BLE_SendWarning_Vol[1] != 0) + { + if(firstflag == 1) BLE_Send(","); + BLE_Send("\"PackUVWarning\":true"); + firstflag = 1; + } + if(BLE_SendWarning_Vol[2] != 0) + { + if(firstflag == 1) BLE_Send(","); + BLE_Send("\"CellOVWarning\":true"); + firstflag = 1; + } + if(BLE_SendWarning_Vol[3] != 0) + { + if(firstflag == 1) BLE_Send(","); + BLE_Send("\"CellUVWarning\":true"); + firstflag = 1; + } + //电流报警 + if(BLE_SendWarning_Cur[0] != 0) + { + if(firstflag == 1) BLE_Send(","); + BLE_Send("\"OCCWarning\":true"); + firstflag = 1; + } + if(BLE_SendWarning_Cur[1] != 0) + { + if(firstflag == 1) BLE_Send(","); + BLE_Send("\"OCDWarning\":true"); + firstflag = 1; + } + BLE_Send("}"); + //结尾 + BLE_Send("}"); + } + else if(((BLE_SendFlag & BIT4) != 0) && ((BLE_SendFlag_old & BIT4) == 0)) + { + uint8_t firstflag = 0; //当出现过第1个上传状态后置1 + + BLE_SendFlag_old |= BIT4; + + //上报内容 %u:unsigned int %d:int %s:char + //存在才发，第五帧 + //开头 + BLE_Send("{"); + BLE_Send("\"dataType\":\"0x01\","); + BLE_Send("\"data\":"); + //内容 + BLE_Send("{"); + //温度报警 + if(BLE_SendWarning_Temp[0] != 0) + { + BLE_Send("\"McuOTCWarning\":true"); + firstflag = 1; + } + if(BLE_SendWarning_Temp[1] != 0) + { + if(firstflag == 1) BLE_Send(","); + BLE_Send("\"McuOTDWarning\":true"); + firstflag = 1; + } + if(BLE_SendWarning_Temp[2] != 0) + { + if(firstflag == 1) BLE_Send(","); + BLE_Send("\"McuUTCWarning\":true"); + firstflag = 1; + } + if(BLE_SendWarning_Temp[3] != 0) + { + if(firstflag == 1) BLE_Send(","); + BLE_Send("\"McuUTDWarning\":true"); + firstflag = 1; + } + if(BLE_SendWarning_Temp[4] != 0) + { + if(firstflag == 1) BLE_Send(","); + BLE_Send("\"AmbientOTCWarning\":true"); + firstflag = 1; + } + if(BLE_SendWarning_Temp[5] != 0) + { + if(firstflag == 1) BLE_Send(","); + BLE_Send("\"AmbientOTDWarning\":true"); + firstflag = 1; + } + if(BLE_SendWarning_Temp[6] != 0) + { + if(firstflag == 1) BLE_Send(","); + BLE_Send("\"AmbientUTCWarning\":true"); + firstflag = 1; + } + if(BLE_SendWarning_Temp[7] != 0) + { + if(firstflag == 1) BLE_Send(","); + BLE_Send("\"AmbientUTDWarning\":true"); + firstflag = 1; + } + if(BLE_SendWarning_Temp[8] != 0) + { + if(firstflag == 1) BLE_Send(","); + BLE_Send("\"MosOTCWarning\":true"); + firstflag = 1; + } + if(BLE_SendWarning_Temp[9] != 0) + { + if(firstflag == 1) BLE_Send(","); + BLE_Send("\"MosOTDWarning\":true"); + firstflag = 1; + } + //if(BLE_SendWarning_Temp[10] != 0) + //{ + // if(firstflag == 1) BLE_Send(","); + // BLE_Send("\"MosUTCWarning\":true"); + // firstflag = 1; + //} + //if(BLE_SendWarning_Temp[11] != 0) + //{ + // if(firstflag == 1) BLE_Send(","); + // BLE_Send("\"MosUTDWarning\":true"); + // firstflag = 1; + //} + BLE_Send("}"); + //结尾 + BLE_Send("}"); + } + } + + //每0.05s发送一次，1s后从头开始 + if(BLE_step >= 21) + { + BLE_step = 0; + BLE_SendFlag = 0; //可选输出项清零 + BLE_SendFlag_old = 0; //下一次继续输出 + } + } + else if(BLE_status == 1) //回复写指令操作 + { + BLE_status = 0; //回复后恢复正常状态 + + //上报内容 %u:unsigned int %d:int %s:char + //开头 + BLE_Send("{"); + BLE_Send("\"dataType\":\"0x03\","); + //内容 + if(putSrvc_reply_flg == 1) //正确 + { + BLE_Send("\"code\":0,"); + BLE_Send("\"data\":"); + + BLE_Send("{"); + BLE_Send("%s:%s", putSrvc_reply_namestr, putSrvc_reply_str); + BLE_Send("}"); + } + else if(putSrvc_reply_flg == 0xAA) //错误-设备无该属性 + { + BLE_Send("\"code\":6411"); + } + else if(putSrvc_reply_flg == 0xBB) //错误-设备拒绝执行 + { + BLE_Send("\"code\":6405"); + } + //结尾 + BLE_Send("}"); + } + else if(BLE_status == 2) //回复写数据操作 + { + BLE_status = 0; //回复后恢复正常状态 + + //上报内容 %u:unsigned int %d:int %s:char + //开头 + BLE_Send("{"); + BLE_Send("\"dataType\":\"0x04\","); + //内容 + if(setPara_reply_flg == 1) //正确 + { + uint8_t i; + uint8_t firstflag = 0; //当出现过第1个上传状态后置1 + + BLE_Send("\"code\":0,"); + BLE_Send("\"set_num\":%hu,", setPara_reply_num); + BLE_Send("\"data\":"); + + BLE_Send("{"); + for(i=0;i= NTC_103AT[0]) + { + temperature = 2731-550; //温度值小于-55度时 =-55度 + } + else if(tempcalcu <= NTC_103AT[180]) + { + temperature = 2731+1250; //温度值大于125度时 =125度 + } + else + { + i = ucTempeMiddle; + if(tempcalcu > NTC_103AT[i]) + { + for(i=ucTempeMiddle - 1; i>0; i--) + { + if(tempcalcu <= NTC_103AT[i]) //NTC103AT[i+1] NTC_103AT[i]) //NTC103AT[i-1]= NTC_103AT_CMFA[0]) + { + temperature = 2731-400; //温度值小于-40度时 =-40度 + } + else if(tempcalcu <= NTC_103AT_CMFA[165]) + { + temperature = 2731+1250; //温度值大于125度时 =125度 + } + else + { + i = ucTempeMiddle; + if(tempcalcu > NTC_103AT_CMFA[i]) + { + for(i=ucTempeMiddle - 1; i>0; i--) + { + if(tempcalcu <= NTC_103AT_CMFA[i]) //NTC103AT[i+1] NTC_103AT_CMFA[i]) //NTC103AT[i-1]= ocv_Media_dp[13]) //超过最大值认为是满电 + { + caliSoc = 100; + } + else if((bmsMem.packVoltage < ocv_Media_dp[13]) && (bmsMem.packVoltage >= ocv_Media_dp[12])) + { + caliSoc = 95; + } + else if((bmsMem.packVoltage < ocv_Media_dp[12]) && (bmsMem.packVoltage >= ocv_Media_dp[11])) + { + caliSoc = 90; + } + + else if((bmsMem.packVoltage < ocv_Media_dp[11]) && (bmsMem.packVoltage > ocv_Media_dp[7])) + { + //当电压在>50%、<90%的电压值内时，若实时SOC不在范围内，则校准到50%/90%，否则不校准 + if(bmsMem.soc > 90) + { + caliSoc = 90; + } + else if(bmsMem.soc < 50) + { + caliSoc = 50; + } + else + { + caliSoc = bmsMem.soc; //等于当前值，使不会校准 + } + } + + else if((bmsMem.packVoltage < ocv_Media_dp[7]) && (bmsMem.packVoltage >= ocv_Media_dp[6])) + { + caliSoc = 50; + } + else if((bmsMem.packVoltage < ocv_Media_dp[6]) && (bmsMem.packVoltage >= ocv_Media_dp[5])) + { + caliSoc = 40; + } + else if((bmsMem.packVoltage < ocv_Media_dp[5]) && (bmsMem.packVoltage >= ocv_Media_dp[4])) + { + caliSoc = 30; + } + else if((bmsMem.packVoltage < ocv_Media_dp[4]) && (bmsMem.packVoltage >= ocv_Media_dp[3])) + { + caliSoc = 20; + } + else if((bmsMem.packVoltage < ocv_Media_dp[3]) && (bmsMem.packVoltage >= ocv_Media_dp[2])) + { + caliSoc = 15; + } + else if((bmsMem.packVoltage < ocv_Media_dp[2]) && (bmsMem.packVoltage >= ocv_Media_dp[1])) + { + caliSoc = 10; + } + else if((bmsMem.packVoltage < ocv_Media_dp[1]) && (bmsMem.packVoltage >= ocv_Media_dp[0])) + { + caliSoc = 5; + } + else if(bmsMem.packVoltage <= ocv_Media_dp[0]) //小于最小值认为是空电 + { + caliSoc = 0; + } + + return caliSoc; +} + +//在RTC有效+允许执行校准倒计时+满足静置时间时，获取开路电压法对应soc +//在电芯温度合适+原SOC不靠谱时，将该soc写入 +//执行校准后，刷新计时起点，重新等待30min后再次执行校准 +void OCV_CaliSOC(void) +{ + uint8_t tempEE[4]; //用于保存计时起点 + + if((LSEErrFlag == 0) && ((paraMem.ocv_min_disable & 0x8000) == 0)) //RTC有效，且允许开路电压校准SOC + { + //静置状态，对应OCV_status为1 + if((bmsMem.packCurrent > (-500)) && (bmsMem.packCurrent < 500)) + { + //刚开机，读取存在EEPROM的时间 + if(OCV_status == 0) + { + OCV_status = 1; + OCV_Wait_flag = 1; //允许在rtc函数中进行时间判断 + + EEPROM_RdMulByte(EE_TIME_OCV, tempEE); + ocvtimecount = tempEE[0]<<24 | tempEE[1]<<16 | tempEE[2]<<8 | tempEE[3]; + + if(ocvtimecount > timecount) //存的数据异常 + { + //更新计时起点 + ocvtimecount = RTC_GetCounter(); + + //保存到EEPROM + tempEE[0] = (ocvtimecount >> 24) & 0xff; + tempEE[1] = (ocvtimecount >> 16) & 0xff; + tempEE[2] = (ocvtimecount >> 8) & 0xff; + tempEE[3] = (ocvtimecount >> 0) & 0xff; + EEPROM_WrMulByte(EE_TIME_OCV, tempEE); + delay_ms(10); + } + } + //从其他状态回来/从不允许改为允许，更新当前时间为计时起点 + else if(OCV_status != 1) + { + OCV_status = 1; + OCV_Wait_flag = 1; //允许在rtc函数中进行时间判断 + + //更新计时起点 + ocvtimecount = RTC_GetCounter(); + + //保存到EEPROM + tempEE[0] = (ocvtimecount >> 24) & 0xff; + tempEE[1] = (ocvtimecount >> 16) & 0xff; + tempEE[2] = (ocvtimecount >> 8) & 0xff; + tempEE[3] = (ocvtimecount >> 0) & 0xff; + EEPROM_WrMulByte(EE_TIME_OCV, tempEE); + delay_ms(10); + } + + //当倒计时结束，校准SOC并更新计时起点 + if((OCV_Wait_flag == 1) && (OCV_CaliSOC_flag == 1)) + { + //准备下一次计时 + OCV_CaliSOC_flag = 0; + ocvtimecount = RTC_GetCounter(); + + //保存到EEPROM + tempEE[0] = (ocvtimecount >> 24) & 0xff; + tempEE[1] = (ocvtimecount >> 16) & 0xff; + tempEE[2] = (ocvtimecount >> 8) & 0xff; + tempEE[3] = (ocvtimecount >> 0) & 0xff; + EEPROM_WrMulByte(EE_TIME_OCV, tempEE); + delay_ms(10); + + //更新OCV中值表 + OCV_CaliSOC_DataWr(); + + //获取校准SOC + OCV_soc = OCV_CaliSoc_dp(); + + if((OCV_soc == 0) && ((bmsMem.packVoltage == 0) || (bmsMem.packVoltage > ocv_data[0].ocv_dp))) //电压异常改0% or 电压正常但计算得0% = 不执行 + { + return; + } + else if(OCV_soc < bmsMem.soc-paraMem.ocv_soc_Range) //只减不增 + { + //若温度和原值差距过大则不替换 + if((TemperatureAverage > 250+2731-paraMem.ocv_T_Range*10) && (TemperatureAverage < 250+2731+paraMem.ocv_T_Range*10)) + { + bmsMem.soc = OCV_soc; + bmsMem.rcc = fcc/100 * bmsMem.soc; + + rcc_Ah = fcc_Ah * bmsMem.soc /100; + oldrcc_Ah = rcc_Ah; + } + } + } + + OCV_WrTime_count = 0; + } + //不在静置状态，对应OCV_status为2 + else + { + OCV_status = 2; + + //清除标志位 + OCV_Wait_flag = 0; + OCV_CaliSOC_flag = 0; + + //非静置状态，每隔30min记录一次计时起点，防止突然断电，导致倒计时偏差过大 + //此值在带电流重启后立刻静置的条件下启用 + OCV_WrTime_count++; + if(OCV_WrTime_count > 60*30) //等30min + { + OCV_WrTime_count = 0; + ocvtimecount = RTC_GetCounter(); + + //保存到EEPROM + tempEE[0] = (ocvtimecount >> 24) & 0xff; + tempEE[1] = (ocvtimecount >> 16) & 0xff; + tempEE[2] = (ocvtimecount >> 8) & 0xff; + tempEE[3] = (ocvtimecount >> 0) & 0xff; + EEPROM_WrMulByte(EE_TIME_OCV, tempEE); + delay_ms(10); + } + } + } + //关闭开路电压法，对应OCV_status为3 + else + { + OCV_status = 3; + + //清除倒计时和标志位 + ocvtimecount = 0; + OCV_Wait_flag = 0; + OCV_CaliSOC_flag = 0; + } +} + diff --git a/MOUDLE/OTA.c b/MOUDLE/OTA.c new file mode 100644 index 0000000..dc26be3 --- /dev/null +++ b/MOUDLE/OTA.c @@ -0,0 +1,698 @@ +/** + ****************************************************************************** + * @file OTA.c + * @author + * @version + * @date + * @brief + ****************************************************************************** + * @attention + * + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" +#include "global.h" +#include "string.h" +#include + + +#if LTE_Conn +//【OTA数据范围】 +#define DATA_BUF_LEN 256 //每包长度 +#define PAGE_LEN 120*(1024/DATA_BUF_LEN) //序号范围 +#define SIZE_LEN 120*1024 //总字节长度限制 120K以内 + +//【Flash存储】 +#define INFO_LEN 12 //存储信息限制，信息总长包括反向存储 +#define DATA_LEN 2048 //存储数据限制，每扇2K=256Byte*8 + +#define USER_FW_INFO 0X08020000 //新程序信息地址 +#define USER_FW_MIDD 0X08021800 //新程序数据地址 + + +//【云平台通信】 +uint8_t LTE_OTA_Flag; //4G升级标志 1：收到升级相关报文 +uint8_t LTE_OTA_fineFlag; //4G升级完成上报标志(上线后先上报升级完成) 0xAA:升级成功 0xBB:维持原程序 + +uint8_t ota_code; //回复标志 0:成功 1:内容有缺 6:升级失败仍运行原程序 + +uint16_t OTA_ErrCnt; //OTA过程的错误计数 + + +//【流程】 +//0xA8.回复OTA升级信息帧 +//0xA9.回复OTA升级数据帧 +//0xAA.转存完成，设备上线后主动上报OTA升级完成 +#define ota_check_sub 0xA7 +#define ota_info_pub 0xA8 +#define ota_data_pub 0xA9 + +//【步骤】 +//0xA8_201~205[回复OTA升级信息帧] 201:主题长度 202:主题内容 203:属性长度 204:属性内容 205:确认上传 +//0xA9_206~210[回复OTA升级数据帧] 206:主题长度 207:主题内容 208:属性长度 209:属性内容 210:确认上传 +//0xAA_211~215[主动上报OTA升级成功] 211:主题长度 212:主题内容 213:属性长度 214:属性内容 215:确认上传 +#define ota_check_sub_step1 201 +#define ota_check_sub_step2 202 +#define ota_check_sub_step3 203 + +#define ota_info_pub_step1 211 +#define ota_info_pub_step2 212 +#define ota_info_pub_step3 213 +#define ota_info_pub_step4 214 +#define ota_info_pub_step5 215 + +#define ota_data_pub_step1 216 +#define ota_data_pub_step2 217 +#define ota_data_pub_step3 218 +#define ota_data_pub_step4 219 +#define ota_data_pub_step5 220 + + +uint32_t firmware_size; //总包的大小 +uint16_t firmware_crc; //总包的CRC校验码 + +uint16_t rev_page; //OTA升级一共多少分包 +uint16_t rev_index; //当前包序号 0~rev_page-1，用于计算存入的地址 +uint16_t rev_crc; //当前包数据的CRC校验码 + +uint16_t ota_data_crc; //数据帧的CRC校验码 + +uint8_t ota_wr_info[INFO_LEN]; //存放信息让底层能判断读出 +uint8_t ota_wr_data[DATA_LEN]; //保存2K数据后再下载 + +uint8_t OTAfine_WrFlg; //更新OTA升级成功/失败标志的标志 0xAA:更新到0 0xBB:更新到0xBB + +uint8_t otaSub_reply_count; +uint8_t otaInfo_reply_count; +uint8_t otaData_reply_count; + +uint8_t ota_rx_Buf[2048]; + + +//下发[OTA升级信息]报文的处理 +void LTE_OTA_Info(void) +{ + //进入升级模式 + LTE_OTA_Flag = 1; + + //准备订阅主题和发送回复 + LTE_status = ota_check_sub; + LTE_step = ota_check_sub_step1; + + //收到并存储信息 + //{"page":100,"size":65535,"method":"crc16"} + if(strstr(LTE_Rx_Buf, "\"page\"") && strstr(LTE_Rx_Buf, "\"size\"") && strstr(LTE_Rx_Buf, "\"check\"")) + { + char str[6]; //字符串 0~102400 + uint8_t len = 0; //字符串长度 + uint32_t temp; //过程量 + uint8_t tmpWr[12]; + + ota_code = 0; + + //Bin文件最大120KB，对应Page最大PAGE_LEN + len = GetStr("\"page\":", ',', ',', LTE_Rx_Buf, str); + sscanf(str, "%u", &temp); + if((temp > 0) && (temp <= PAGE_LEN) && (len > 0)) + { + rev_page = temp; + } + else + { + ota_code = 2; //内容超出范围 + return; + } + + //Bin文件最大120KB，对应size最大120*1024 + len = GetStr("\"size\":", ',', ',', LTE_Rx_Buf, str); + sscanf(str, "%u", &temp); + if((temp > 0) && (temp <= SIZE_LEN) && (len > 0)) + { + firmware_size = temp; + } + else + { + ota_code = 2; //内容超出范围 + return; + } + + //整体CRC码 + len = GetStr("\"check\":\"", '\"', '\"', LTE_Rx_Buf, str); + if(len == 4) + { + sscanf(str, "%4hx", &firmware_crc); + } + else + { + ota_code = 2; //内容超出范围 + return; + } + + //序号清零，等待升级 + rev_index = 0; + + //赋值 + tmpWr[0] = (firmware_size>> 0) & 0xFF; + tmpWr[1] = (firmware_size>> 8) & 0xFF; + tmpWr[2] = (firmware_size>>16) & 0xFF; + tmpWr[3] = (firmware_size>>24) & 0xFF; + tmpWr[4] = (firmware_crc >> 0) & 0xFF; + tmpWr[5] = (firmware_crc >> 8) & 0xFF; + tmpWr[6] = tmpWr[0] ^ 0xff; + tmpWr[7] = tmpWr[1] ^ 0xff; + tmpWr[8] = tmpWr[2] ^ 0xff; + tmpWr[9] = tmpWr[3] ^ 0xff; + tmpWr[10] = tmpWr[4] ^ 0xff; + tmpWr[11] = tmpWr[5] ^ 0xff; + + //把OTA信息存储 + FLASH_WrData(USER_FW_INFO, (uint16_t *)&tmpWr[0], INFO_LEN/2); //12/2=6 + } + else + { + ota_code = 1; //内容有缺 + } +} + +//下发[OTA升级数据]报文的处理 +void LTE_OTA_Data(void) +{ + LTE_status = ota_data_pub; + LTE_step = ota_data_pub_step1; + + //收到并存储数据 + //{"index":0,"sign":"Hex","data":"HEX..."} + if(strstr(LTE_Rx_Buf, "\"index\"") && strstr(LTE_Rx_Buf, "\"data\"") && strstr(LTE_Rx_Buf, "\"check\"")) + { + char str[6] = {0}; //字符串 0~102400 + uint16_t len = 0; //字符串长度 + uint32_t temp = 0; //过程量 + + char data_str[DATA_BUF_LEN*2+4]; //字符串 + uint16_t dataLen = 0; //数据长度需要单独拿出参与最后一包的判断 + uint8_t dataIdx; //当前包对应2K数组中的位置 0~7 + + ota_code = 0; + + //Bin文件最大120KB，对应index最大PAGE_LEN + len = GetStr("\"index\":", ',', ',', LTE_Rx_Buf, str); + sscanf(str, "%u", &temp); + if(len > 0) + { + if(temp == 0) + { + rev_index = temp; + } + else if((temp > 0) && (temp <= PAGE_LEN)) + { + if(temp == rev_index+1) + { + rev_index = temp; + } + else + { + ota_code = 3; //内容不连续 + return; + } + } + else + { + ota_code = 2; //内容超出范围 + return; + } + } + else + { + ota_code = 1; //内容有缺 + } + + //该包的CRC码 + len = GetStr("\"check\":\"", '\"', '\"', LTE_Rx_Buf, str); + if(len == 4) + { + sscanf(str, "%4hx", &rev_crc); + } + else if(len > 0) + { + if(rev_index != 0) rev_index--; //该包接收错误，应回退等待下一次发当前包 + + ota_code = 2; //内容超出范围 + return; + } + else + { + ota_code = 1; //内容有缺 + } + + //该包的数据字符串放入str数组 + char* dataStart = strstr(LTE_Rx_Buf, "\"data\":\""); dataStart += strlen("\"data\":\""); + char* dataEnd = strchr(dataStart, '\"'); + dataLen = dataEnd - dataStart; + strncpy(data_str, dataStart, dataLen); + data_str[dataLen] = '\0'; + + dataIdx = rev_index%8; //2K数组中的位置0~7 (dataIdx=7)或(rev_index == rev_page-1)时执行写入Flash + + if((rev_index < rev_page-1) && (dataLen == DATA_BUF_LEN*2)) //正常包 + { + uint16_t i; + + //转换到ota_wr_data数组 + for(i=0;i 0)) //最后一包 + { + uint16_t i; + + //清空ota_wr_data的该包对应位置及以后的位置 + for(i=dataIdx;i<8;i++) + { + memset(&ota_wr_data[i*256], 0, DATA_BUF_LEN); + } + + //将最后一包也转换到ota_wr_data数组 + for(i=0;i 0) + { + if(rev_index != 0) rev_index--; //该包接收错误，应回退等待下一次发当前包 + + ota_code = 2; //内容超出范围 + return; + } + else + { + ota_code = 1; //内容有缺 + } + + //数据格式都正确，进行校验和写入 + //CRC校验码 + ota_data_crc = CRC16_FirmtoEE(&ota_wr_data[dataIdx*256], dataLen/2); + if(rev_crc == ota_data_crc) + { + if(rev_index == 0) //对第1包进行合法范围判断 + { + if((ota_wr_data[6] > 0x01) || (ota_wr_data[7] != 0x08)) //Flash 128KB 0x08000000~0x0801FFFF + { + if(rev_index != 0) rev_index--; //该包接收错误，应回退等待下一次发当前包 + + ota_code = 5; //内容不是正规升级文件 + return; + } + } + //执行写入Flash + else if((dataIdx == 7) || (rev_index == rev_page-1)) + { + FLASH_WrData(rev_index/8 * DATA_LEN + USER_FW_MIDD, (uint16_t *)&ota_wr_data[0], DATA_LEN/2); //2048/2=1024 + delay_ms(2); + } + } + else + { + if(rev_index != 0) rev_index--; //该包接收错误，应回退等待下一次发当前包 + + ota_code = 4; //CRC校验错误 + return; + } + } + else + { + ota_code = 1; //内容有缺 + } +} + +//处理数据，接收报文识别后执行 +void LTE_OTA_IT_Update(void) +{ + if(LTE_status != 0) //收到后，执行回复，才判断OK，>，ERROR + { + /*收到OK或>或ERROR，认为回复完整，开始分析*/ + if((LTE_Rx_BufIndex >= 2) && (strstr(LTE_Rx_Buf, "OK"))) + { + //0xA7.检查订阅主题 + if(LTE_status == ota_check_sub) + { + //1.检查订阅 + if(strstr(LTE_Rx_Buf, "AT+CMQTTSUB?") && (LTE_step == ota_check_sub_step1)) + { + if(strstr(LTE_Rx_Buf, "/ota/device/firmware/101") == 0) //缺少了OTA数据帧的主题 + { + LTE_status = ota_check_sub; + LTE_step = ota_check_sub_step2; //无订阅，跳转：订阅OTA数据帧的主题 + } + else + { + LTE_status = ota_info_pub; + LTE_step = ota_info_pub_step1; //有订阅，跳转：发送回复 + } + } + + //3.订阅OTA数据帧的主题 + else if(LTE_step == ota_check_sub_step3) + { + otaSub_reply_count = 0; + + LTE_status = ota_info_pub; + LTE_step = ota_info_pub_step1; //订阅成功，进行信息帧的回复 + } + } + //0xA8.回复OTA升级信息帧 + if(LTE_status == ota_info_pub) + { + //2. + if(LTE_step == ota_info_pub_step2) + { + LTE_status = ota_info_pub; + LTE_step = ota_info_pub_step3; //主题接收OK，准备下一步 + } + //4. + else if(LTE_step == ota_info_pub_step4) + { + LTE_status = ota_info_pub; + LTE_step = ota_info_pub_step5; //内容接收OK，准备下一步 + } + //5. + else if(strstr(LTE_Rx_Buf, "AT+CMQTTPUB") && (LTE_step == ota_info_pub_step5)) + { + otaInfo_reply_count = 0; + + if(ota_code == 0) + { + //等待数据内容，期间不主动发数据 + LTE_status = 0; + LTE_step = 0; + return; + } + else + { + //退出升级流程，正常上报 + LTE_OTA_Flag = 0; + + LTE_status = ask_lbs; + LTE_step = ask_lbs_step1; //跳转：正常流程第一步 + } + } + } + //0xA9.回复OTA升级数据帧 + else if(LTE_status == ota_data_pub) + { + //2. + if(LTE_step == ota_data_pub_step2) + { + LTE_status = ota_data_pub; + LTE_step = ota_data_pub_step3; //主题接收OK，准备下一步 + } + //4. + else if(LTE_step == ota_data_pub_step4) + { + LTE_status = ota_data_pub; + LTE_step = ota_data_pub_step5; //内容接收OK，准备下一步 + } + //5. + else if(strstr(LTE_Rx_Buf, "AT+CMQTTPUB") && (LTE_step == ota_data_pub_step5)) + { + otaData_reply_count = 0; + + //未收到全部数据时 + if(rev_index < rev_page-1) + { + //等待数据内容，期间不主动发数据 + LTE_status = 0; + LTE_step = 0; + return; + } + else + { + //更新EE_OTA完成标志，先更新失败标志，若底层完成，会改为成功标志 + LTE_OTA_fineFlag = 0xBB; + OTAfine_WrFlg = 0xBB; + } + } + } + } + else if((LTE_Rx_BufIndex >= 1) && (strstr(LTE_Rx_Buf, ">"))) + { + //0xA7.检查订阅 + if(LTE_status == ota_check_sub) + { + //1.订阅OTA数据帧的主题 + if(strstr(LTE_Rx_Buf, "AT+CMQTTSUB=0,39,1") && (LTE_step == ota_check_sub_step2)) + { + LTE_status = ota_check_sub; + LTE_step = ota_check_sub_step3; //准备下一步 + } + } + //0xA8.回复OTA升级数据帧 + else if(LTE_status == ota_info_pub) + { + //1. + if(strstr(LTE_Rx_Buf, "AT+CMQTTTOPIC") && (LTE_step == ota_info_pub_step1)) + { + LTE_status = ota_info_pub; + LTE_step = ota_info_pub_step2; //准备下一步 + } + //3. + else if(strstr(LTE_Rx_Buf, "AT+CMQTTPAYLOAD") && (LTE_step == ota_info_pub_step3)) + { + LTE_status = ota_info_pub; + LTE_step = ota_info_pub_step4; //准备下一步 + } + } + //0xA9.回复OTA升级信息帧 + else if(LTE_status == ota_data_pub) + { + //1. + if(strstr(LTE_Rx_Buf, "AT+CMQTTTOPIC") && (LTE_step == ota_data_pub_step1)) + { + LTE_status = ota_data_pub; + LTE_step = ota_data_pub_step2; //准备下一步 + } + //3. + else if(strstr(LTE_Rx_Buf, "AT+CMQTTPAYLOAD") && (LTE_step == ota_data_pub_step3)) + { + LTE_status = ota_data_pub; + LTE_step = ota_data_pub_step4; //准备下一步 + } + } + } + else if((LTE_Rx_BufIndex >= 5) && (strstr(LTE_Rx_Buf, "ERROR"))) + { + LTE_ResendDelay = ResendTime; + + OTA_ErrCnt++; + + if(OTA_ErrCnt > ERR_timeEnd2) //1min + { + OTA_ErrCnt = 0; + + //退出升级流程，在正常流程中检查问题 + LTE_OTA_Flag = 0; + + CRESET_flag = 1; //重启 + CRESET_step = 0; + } + } + } +} + +//收到下发报文后，在主循环进行处理 +void LTE_OTA_IQ_Update(void) +{ + if((LTE_status == 0) && (LTE_step == 0)) //OTA升级，重点是接收下发报文 + { + /*监控下发报文*/ + if(strstr(LTE_Rx_Buf, "+CMQTTRXSTART") && strstr(LTE_Rx_Buf, "+CMQTTRXEND")) //有头有尾 + { + //OTA信息帧 + if(strstr(LTE_Rx_Buf, "/ota/device/upgrade/101")) + { + LTE_OTA_Info(); + } + //OTA数据帧 + else if(strstr(LTE_Rx_Buf, "/ota/device/firmware/101")) + { + LTE_OTA_Data(); + + if(ota_code != 0) + { + uint16_t i; + for(i=0;i<2048;i++) + { + ota_rx_Buf[i] = LTE_Rx_Buf[i]; + } + } + } + } + } + + //更新升级标志归0 + if(OTAfine_WrFlg == 0xAA) + { + EEPROM_WrMulByte(EE_OTA_FINE,<E_OTA_fineFlag); + delay_ms(5); + + OTAfine_WrFlg = 0; + } + //更新升级标志为0xBB，IAP标志为0xBB (不需要兼容旧IAP，不用考虑擦除跳转标志) + else if(OTAfine_WrFlg == 0xBB) + { + EEPROM_WrMulByte(EE_OTA_FINE,<E_OTA_fineFlag); + delay_ms(5); + + OTAfine_WrFlg = 0; + + IAP_Run = 0xBB; //表示存在下一版程序 + EEPROM_WrMulByte(EE_IAP_NEW1,&IAP_Run); + delay_ms(10); + EEPROM_WrMulByte(EE_IAP_NEW2,&IAP_Run); + delay_ms(10); + + //执行软件重启 + NVIC_SystemReset(); + } +} + +//该函数用于发送报文 +void LTE_OTA_IQ_Transmit(void) +{ + if(LTE_status != 0) + { + if((LTE_Rx_BufIndex == 0) && (LTE_WaitRxFlg == 1)) //有发送指令却没有回复 //只执行1次 + { + LTE_WaitRxFlg = 0; + LTE_WaitRxDelay = WaitRxTime; + return; + } + + LTE_Rx_BufIndex = 0; + memset(LTE_Rx_Buf, 0, LTE_RX_BUF_LEN); //填入前先清空 + memset(LTE_Tx_Buf, 0, LTE_TX_BUF_LEN); + } + + //定期查询订阅并重新订阅主题 + if(LTE_status == ota_check_sub) + { + otaSub_reply_count++; + //尝试1次重新回复 + if(otaSub_reply_count == 10) + { + LTE_step = ota_check_sub_step1; + } + //仍然失败退出回复 + else if(otaSub_reply_count >= 20) + { + LTE_OTA_Flag = 0; + LTE_status = ask_lbs; + LTE_step = ask_lbs_step1; //回复OTA升级信息一直失败，跳转：正常流程第一步 + + otaSub_reply_count = 0; + } + + switch(LTE_step) //ota_info_pub_step1~ota_info_pub_step5 + { + case ota_check_sub_step1: + LTE_Send("AT+CMQTTSUB?\r\n"); //查询订阅 + break; + case ota_check_sub_step2: + LTE_Send("AT+CMQTTSUB=0,39,1\r\n"); //订阅主题长度 "/ota/device/firmware/101/030200001/post"=39Byte //订阅OTA升级数据 + break; + case ota_check_sub_step3: + LTE_Send("/ota/device/firmware/101/%s/post", BMS_SN); //订阅的主题 (只有这个不用换新行) + break; + default: + break; + } + } + //0xA8.回复OTA升级信息帧 + else if(LTE_status == ota_info_pub) + { + otaInfo_reply_count++; + //尝试1次重新回复 + if(otaInfo_reply_count == 10) + { + LTE_step = ota_info_pub_step1; + } + //仍然失败退出回复 + else if(otaInfo_reply_count >= 20) + { + LTE_OTA_Flag = 0; + LTE_status = ask_lbs; + LTE_step = ask_lbs_step1; //回复OTA升级信息一直失败，跳转：正常流程第一步 + + otaInfo_reply_count = 0; + } + + switch(LTE_step) //ota_info_pub_step1~ota_info_pub_step5 + { + case ota_info_pub_step1: + LTE_Send("AT+CMQTTTOPIC=0,39\r\n"); //上报主题长度 24+9+6=39Byte + break; + case ota_info_pub_step2: + LTE_Send("/ota/device/upgrade/101/%s/reply", BMS_SN); //上报的主题 (只有这个不用换新行) + break; + case ota_info_pub_step3: + LTE_Send("AT+CMQTTPAYLOAD=0,%hu\r\n", 11+uint_str_len(ota_code)); //上报内容长度 = 数据长度+固定字符长度+回车 + break; + case ota_info_pub_step4: + LTE_Send("{\"code\":%hu}\r\n", ota_code); + break; + case ota_info_pub_step5: + LTE_Send("AT+CMQTTPUB=0,1,30\r\n"); //至少上报1次+30s内等待服务器回复 + break; + default: + break; + } + } + //0xA9.回复OTA升级数据帧 + else if(LTE_status == ota_data_pub) + { + otaData_reply_count++; + //尝试1次重新回复(数据帧比较特殊，如果后续序号不对就失败了，故增加次数) + if(otaData_reply_count == 20) + { + LTE_step = ota_data_pub_step1; + } + //仍然失败退出回复 + else if(otaData_reply_count >= 30) + { + LTE_status = 0; + LTE_step = 0; + + otaData_reply_count = 0; + } + + switch(LTE_step) //ota_data_pub_step1~ota_data_pub_step5 + { + case ota_data_pub_step1: + LTE_Send("AT+CMQTTTOPIC=0,40\r\n"); //上报主题长度 25+9+6=40Byte + break; + case ota_data_pub_step2: + LTE_Send("/ota/device/firmware/101/%s/reply", BMS_SN); //上报的主题 (只有这个不用换新行) + break; + case ota_data_pub_step3: + LTE_Send("AT+CMQTTPAYLOAD=0,%hu\r\n", 11+uint_str_len(ota_code)); //上报内容长度 = 数据长度+固定字符长度+回车 + break; + case ota_data_pub_step4: + LTE_Send("{\"code\":%hu}\r\n", ota_code); + break; + case ota_data_pub_step5: + LTE_Send("AT+CMQTTPUB=0,1,30\r\n"); //至少上报1次+30s内等待服务器回复 + break; + default: + break; + } + } +} +#endif + diff --git a/MOUDLE/RS485_Modbus.c b/MOUDLE/RS485_Modbus.c new file mode 100644 index 0000000..8033b1c --- /dev/null +++ b/MOUDLE/RS485_Modbus.c @@ -0,0 +1,1937 @@ +/** + ****************************************************************************** + * @file RS485_Modbus.c + * @author + * @version + * @date + * @brief + ****************************************************************************** + * @attention + * + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" +#include "global.h" +#include "string.h" +#include "rtc.h" +#include "soe.h" + +#define MODBUS_UART USART1 +#define MODBUS_UART_SendMulByte USART1_SendMulByte //发送多字节 +#define MODBUS_UART_TIM TIM4 +#define MODBUS_UART_IT_RX_DISABLE USART_ITConfig(USART1, USART_IT_RXNE, DISABLE) +#define MODBUS_UART_IT_RX_ENABLE USART_ITConfig(USART1, USART_IT_RXNE, ENABLE) + +#define MODBUS_MEM_PT (uint8_t *)&bmsMem.vCell[0] //通讯内存开始地址 +#define MODBUS_VersionMEM_PT (uint8_t *)&VersionMem.Hardware[0]//上位机请求版本号通讯内存开始地址 +#define MODBUS_TimeMEM_PT (uint8_t *)&calendar_WRITE.sec +#define MODBUS_ParaMEM_PT (uint8_t *)¶Mem.act_bal_startV//上位机弹窗读写配置 +#define MODBUS_CtrlMEM_PT (uint8_t *)&CTRL_Order //上位机控制MOS关闭(一次性的，永久的在paraMem里) + +#define MODBUS_MON_CNT paraMem.PACK_NUM==1?MODBUS_MON_CNT1:MODBUS_MON_CNT2 +#define MODBUS_MON_CNT1 3000 //3000*10ms = 30s（因为轮询速度加快，该时间也加快） +#define MODBUS_MON_CNT2 paraMem.PACK_NUM*150+200 //最大20对应32s，最小2对应5s +#define MODBUS_BUF_LEN 220 + +#define MODBUS_ASSIGN_INADDR AddrMax+1 + +uint8_t modbusBuf[MODBUS_BUF_LEN]; +uint8_t modbusBufIndex; +uint16_t modbusMoniCount; + +uint8_t modbusF03RxFlg; //读数据接收正确标记 +uint8_t modbusF10RxFlg; //写数据接收正确标记 +uint8_t modbusFaaRxFlg; //CADC零点校准数据接收正确标记 +uint8_t modbusFbbRxFlg; //CADC增益校准数据接收正确标记 +uint8_t modbusFddRxFlg; //读取记录 接收正确标记 +uint8_t modbusFeeRxFlg; //清除记录 接收正确标记 +uint8_t modbusFf1RxFlg; //选择协议 接收正确标记 + +uint8_t modbusCurF03RxFlag;//主机收到03回复 接收正确标记 +uint8_t modbusCurF10RxFlag;//主机收到10回复 接收正确标记 + +uint8_t modbusCurStatus; //主机当前执行的功能——每当变化，会初始化收发状态 0:刚开机/刚初始化过 1:基础轮询 2:自动分配地址 3:屏幕持续读从机 4:屏幕写从机地址 5:上位机持续读从机 +uint8_t modbusCurDev; //主机当前的轮询对象 +uint8_t modbusCurSta; //主机当前的收发状态 + +uint8_t modbusCurLastAddr; //最后一个能通信到的并机地址 + +uint8_t chg_forbidFlg; //禁充标志，SOC大于100%的时候启用 +uint8_t dsg_forbidFlg; //禁放标志，SOC小于10%的时候启用 +uint8_t chg_forceFlg; //强充标志，SOC小于10%的时候启用 +uint16_t RequestFlag; //充放电允许位 + +uint8_t chg_curlimitFlg; //充电限流(固定40A)的标志，出现总体过压或单体过压的时候启用 + +uint8_t ReAskFlag; //主机轮询遇报警，再次询问的标志 + +uint8_t sleepOFFcount; //3.4网口的主从机轮询，可能有个时间差 + +uint8_t sdwa_WrAddr; //屏幕通过主机写从机地址的值 +uint8_t sdwa_WrAddr_Flg; //屏幕通过主机写从机地址的标志 0不在写 1尝试中 2成功 3失败 +uint8_t sdwa_WrAddr_Failcount; //连续写地址失败的计数 + +#if Addr_SetAuto +uint8_t assignAddr_relay; //主机开机后延时2s再开始通信，等待地址变化 +uint8_t assignAddr_State; //自动分配地址的状态 0未开始 1进行中 2结束 +uint8_t assignAddr_Step; //自动分配地址当前步骤 +uint8_t assignAddr_Failcount; //连续分配地址失败的计数 + +uint8_t assignAddr_485num; //分配地址后的在线个数，若存在从机(此值>2)才下发队列标志 +uint16_t assignAddr_random; //主机完成分配后生成的随机数(AddrMax+1~65535),用来识别队列 + +uint8_t assignAddr_WrIndex_Flg;//主机执行下发队列标志数的标志 + +uint8_t assign_ready_count1;//主机再次分配的启用条件计数，1.最后一个在线从机的序号不等于总在线个数，说明中间有地址缺失，发现2次就执行 +uint8_t assign_ready_count2;//主机再次分配的启用条件计数，2.始终找不到任何从机，发现3次就执行 +uint8_t assign_ready_count3;//主机再次分配的启用条件计数，3.从机的队列标志和主机的不同，发现2次就执行 +uint8_t assign_ready_count4;//主机再次分配的启用条件计数，4.在线总个数外的地址有不符合的乱码 +uint8_t assign_ready_count5;//主机再次分配的启用条件计数，5.在线总个数内的地址有回复但字节数超出 +#endif + +uint8_t AnswerFlag1; //轮询在线总个数外的地址有不符合的乱码 +uint8_t AnswerFlag2; //轮询在线总个数内的地址有回复但字节数超出 + +uint8_t PollStop_flag; //主机暂停发送轮询的标志位。在1口，除了7E/03/10/控制MOS的/升级的，其他报文都会恢复不再暂停。在3.4口， +uint8_t PollStop_count; //主机暂停发送轮询的倒计时，再次收到则清零，30s + + +const uint16_t CRC16Table[256]= +{ + 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241, + 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440, + 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40, + 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841, + 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40, + 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41, + 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641, + 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040, + 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240, + 0x3600, 0xF6C1, 0xF781, 0x3740, 0xF501, 0x35C0, 0x3480, 0xF441, + 0x3C00, 0xFCC1, 0xFD81, 0x3D40, 0xFF01, 0x3FC0, 0x3E80, 0xFE41, + 0xFA01, 0x3AC0, 0x3B80, 0xFB41, 0x3900, 0xF9C1, 0xF881, 0x3840, + 0x2800, 0xE8C1, 0xE981, 0x2940, 0xEB01, 0x2BC0, 0x2A80, 0xEA41, + 0xEE01, 0x2EC0, 0x2F80, 0xEF41, 0x2D00, 0xEDC1, 0xEC81, 0x2C40, + 0xE401, 0x24C0, 0x2580, 0xE541, 0x2700, 0xE7C1, 0xE681, 0x2640, + 0x2200, 0xE2C1, 0xE381, 0x2340, 0xE101, 0x21C0, 0x2080, 0xE041, + 0xA001, 0x60C0, 0x6180, 0xA141, 0x6300, 0xA3C1, 0xA281, 0x6240, + 0x6600, 0xA6C1, 0xA781, 0x6740, 0xA501, 0x65C0, 0x6480, 0xA441, + 0x6C00, 0xACC1, 0xAD81, 0x6D40, 0xAF01, 0x6FC0, 0x6E80, 0xAE41, + 0xAA01, 0x6AC0, 0x6B80, 0xAB41, 0x6900, 0xA9C1, 0xA881, 0x6840, + 0x7800, 0xB8C1, 0xB981, 0x7940, 0xBB01, 0x7BC0, 0x7A80, 0xBA41, + 0xBE01, 0x7EC0, 0x7F80, 0xBF41, 0x7D00, 0xBDC1, 0xBC81, 0x7C40, + 0xB401, 0x74C0, 0x7580, 0xB541, 0x7700, 0xB7C1, 0xB681, 0x7640, + 0x7200, 0xB2C1, 0xB381, 0x7340, 0xB101, 0x71C0, 0x7080, 0xB041, + 0x5000, 0x90C1, 0x9181, 0x5140, 0x9301, 0x53C0, 0x5280, 0x9241, + 0x9601, 0x56C0, 0x5780, 0x9741, 0x5500, 0x95C1, 0x9481, 0x5440, + 0x9C01, 0x5CC0, 0x5D80, 0x9D41, 0x5F00, 0x9FC1, 0x9E81, 0x5E40, + 0x5A00, 0x9AC1, 0x9B81, 0x5B40, 0x9901, 0x59C0, 0x5880, 0x9841, + 0x8801, 0x48C0, 0x4980, 0x8941, 0x4B00, 0x8BC1, 0x8A81, 0x4A40, + 0x4E00, 0x8EC1, 0x8F81, 0x4F40, 0x8D01, 0x4DC0, 0x4C80, 0x8C41, + 0x4400, 0x84C1, 0x8581, 0x4540, 0x8701, 0x47C0, 0x4680, 0x8641, + 0x8201, 0x42C0, 0x4380, 0x8341, 0x4100, 0x81C1, 0x8081, 0x4040 +}; + +// CRC 校验函数,返回CRC +BYTE2 CRC16_Cal(uint8_t *pdata, uint16_t len) +{ + uint16_t i; + BYTE2 CRCData; + + CRCData.b16=0XFFFF; + for(i=0;i=0 && num<=protocolNum) + { + if(num==0) //2026.2.10增加读协议 + { + num = protocol; + } + + protocolSwitchFail = 0; //存在该协议，选中，并返回协议名称 + protocol = num; + + //将选中的字符串复制到一个新的字符数组中,获取字符串的长度 + strcpy(name,protocolStrings[num-1]); + namelen = strlen(name); + + //生成输出报文 + modbusBuf[2] = namelen; + for(i=0;i= MODBUS_BUF_LEN ) + { + modbusBufIndex = 0; + } + + //每次接收数据中断清除定时器计数器并启动计数器 + //如定时器溢出中断，表示一帧数据接收完成 + TIM_SetCounter(MODBUS_UART_TIM, 0); + TIM_Cmd(MODBUS_UART_TIM, ENABLE); +} + +//查询发送数据 +void MODBUS_IQ_Transmit(void) +{ + BYTE2 crc16; + + if(modbusF03RxFlg == 1) + { + modbusF03RxFlg = 0; + modbusBufIndex = 0; + MODBUS_UART_SendMulByte(modbusBuf, (5 + modbusBuf[2]) ); + MODBUS_UART_IT_RX_ENABLE; + } + else if(modbusF10RxFlg == 1) + { + modbusF10RxFlg = 0; + modbusBufIndex = 0; + + if(modbusBuf[1] == 0x10) //写参数需要存入flash + { + //bmsMem中数据更新到FLASH A区和B区和AFE EEPORM + if((MEMORY_UpdateFlash(FLASH_DATA_A_BASE) == 0) && (MEMORY_UpdateFlash(FLASH_DATA_B_BASE) == 0)) + { + staPack.bits.flashUpdate= 0; + if(MEMORY_UpdateAFE() ==0) //更新AFE EEPROM内容 + { + staPack.bits.eepromUpdate = 0; + MODBUS_UART_SendMulByte(modbusBuf, 8); + } + else + { + staPack.bits.eepromUpdate = 1; + } + } + else + { + staPack.bits.flashUpdate= 1; + } + bmsMem.packStatus = staPack.byte; + } + else if(modbusBuf[1] == 0xf4) + { + if((MEMORY_UpdateFlash(FLASH_DATA_A_BASE) == 0) && (MEMORY_UpdateFlash(FLASH_DATA_B_BASE) == 0)) + { + staPack.bits.flashUpdate= 0; + if(MEMORY_UpdateAFE() ==0) + { + staPack.bits.eepromUpdate = 0; + MODBUS_UART_SendMulByte(modbusBuf, 8); + } + else + { + staPack.bits.eepromUpdate = 1; + } + } + else + { + staPack.bits.flashUpdate= 1; + } + bmsMem.packStatus = staPack.byte; + } + else if(modbusBuf[1] == 0x56) //写SN号需要写入EEPROM //写4G通信凭证需要存入flash + { + uint8_t i; + uint8_t *data; + uint8_t tmpWr[16]; + + if(modbusBuf[3] == 0x00) //对应硬件版本号的地址 + { + MODBUS_UART_SendMulByte(modbusBuf, 8); + EEPROM_WrMulByte(EE_Hardware,VersionMem.Hardware); + delay_ms(5); + + //填充HardwareVersion + Refresh_HardwareVersion(); + } + else if(modbusBuf[3] == 0x01) //对应屏幕号的地址 + { + MODBUS_UART_SendMulByte(modbusBuf, 8); + EEPROM_WrMulByte(EE_Screen,&VersionMem.Screen); + delay_ms(5); + + //填充ScreenVersion + Refresh_ScreenVersion(); + } + else if(modbusBuf[3] == 0x04) //对应BMS的SN号的地址 + { + data = (uint8_t *)&VersionMem.BMS_SN[0]; + for(i=0;i<9+1;i++) + { + tmpWr[i] = *data; + data++; + } + + MODBUS_UART_SendMulByte(modbusBuf, 8); + EEPROM_WrMulByte(EE_BMS_SN,tmpWr); + delay_ms(5); + + /*三选一模块*/ + #if BLE_Conn + BLE_WriteName(); //锟斤拷锟斤拷锟斤拷锟斤拷锟斤拷锟斤拷 + #endif + #if LTE_Conn + LTE_UNSUB_Flag = 1; //因为订阅主题变动，需要对此前的订阅进行取消绑定 + EEPROM_WrMulByte(EE_UNSUB,<E_UNSUB_Flag); + delay_ms(5); + + if(LTE_LINK_flag == 1) //若原来已连接4G服务器，断开并重新正确连接 + { + LTE_LINK_flag = 0; //已连接标志清零 + + MQTT_RST_flag = 1; //断开再连接MQTT服务器 + MQTT_RST_step = 0; + + MQTT_START_flag = 0; + MQTT_READY_flag = 0; + MQTT_timed_count = 0; //清零定时上报倒计时 + + LTE_OTA_Flag = 0; //OTA升级标志清零 + } + + LTE_4G_Domain_ChangeSN(); //更新4G通信凭证 + #endif + } + else if(modbusBuf[3] == 0x09) //对应PACK的SN号的地址 + { + data = (uint8_t *)&VersionMem.PACK_SN[0]; + for(i=0;i<15+1;i++) + { + tmpWr[i] = *data; + data++; + } + + MODBUS_UART_SendMulByte(modbusBuf, 8); + EEPROM_WrMulByte(EE_PACK_SN,tmpWr); + delay_ms(5); + + //填充PACK_SN + Refresh_PACK_SN(); + } + #if LTE_Conn + else if(modbusBuf[3] == 0x20) //对应4G通信凭证的起始地址 + { + if(LTE_LINK_flag == 1) + { + LTE_LINK_flag = 0; //已连接标志清零 + + MQTT_RST_flag = 1; //断开再连接MQTT服务器 + MQTT_RST_step = 0; + + MQTT_START_flag = 0; + MQTT_READY_flag = 0; + MQTT_timed_count = 0; //清零定时上报倒计时 + + LTE_OTA_Flag = 0; //OTA升级标志清零 + } + + //计算CRC校验值 + static uint8_t temp[HOSTMEM_LEN]; + memcpy(temp, &VersionMem.host[0], HOSTMEM_LEN); + + VersionMem.hostAll_crc = CRC8_Cal(&temp[0], 153); + + //更新Flash + if((MEMORY_UpdateFlash(FLASH_DATA_A_BASE) == 0) && (MEMORY_UpdateFlash(FLASH_DATA_B_BASE) == 0)) + { + staPack.bits.flashUpdate = 0; + } + else + { + staPack.bits.flashUpdate = 1; + } + bmsMem.packStatus = staPack.byte; + + MODBUS_UART_SendMulByte(modbusBuf, 8); + } + #endif + } + else + { + MODBUS_UART_SendMulByte(modbusBuf, 8); + } + + MODBUS_UART_IT_RX_ENABLE; + } + else if(modbusFaaRxFlg == 1) + { + modbusFaaRxFlg = 0; + modbusBufIndex = 0; + + if(cali.flagZeroCaliFail ==0) //ok + { + // 01 AA 5A A5 03 04 CRCL H + modbusBuf[0] = bmsMem.E2_485Addr; + modbusBuf[1] = 0xaa; + modbusBuf[2] = 0x5a; + modbusBuf[3] = 0xa5; + modbusBuf[4] = 0x03; + modbusBuf[5] = 0x04; + crc16 = CRC16_Cal(modbusBuf, 6); + modbusBuf[6] = crc16.b8[0]; + modbusBuf[7] = crc16.b8[1]; + MODBUS_UART_SendMulByte(modbusBuf, 8); + } + else //fail + { + // 01 AA 5A A5 05 06 CRCL H + modbusBuf[0] = bmsMem.E2_485Addr; + modbusBuf[1] = 0xaa; + modbusBuf[2] = 0x5a; + modbusBuf[3] = 0xa5; + modbusBuf[4] = 0x05; + modbusBuf[5] = 0x06; + crc16 = CRC16_Cal(modbusBuf, 6); + modbusBuf[6] = crc16.b8[0]; + modbusBuf[7] = crc16.b8[1]; + MODBUS_UART_SendMulByte(modbusBuf, 8); + } + + MODBUS_UART_IT_RX_ENABLE; + } + else if(modbusFbbRxFlg == 1) + { + modbusFbbRxFlg = 0; + modbusBufIndex = 0; + + if(cali.flagGainCaliFail ==0) //ok + { + // 01 AA 5A A5 03 04 CRCL H + modbusBuf[0] = bmsMem.E2_485Addr; + modbusBuf[1] = 0xbb; + modbusBuf[2] = 0x5b; + modbusBuf[3] = 0xb5; + modbusBuf[4] = 0x03; + modbusBuf[5] = 0x04; + crc16 = CRC16_Cal(modbusBuf, 6); + modbusBuf[6] = crc16.b8[0]; + modbusBuf[7] = crc16.b8[1]; + MODBUS_UART_SendMulByte(modbusBuf, 8); + } + else //fail + { + // 01 AA 5A A5 05 06 CRCL H + modbusBuf[0] = bmsMem.E2_485Addr; + modbusBuf[1] = 0xbb; + modbusBuf[2] = 0x5b; + modbusBuf[3] = 0xb5; + modbusBuf[4] = 0x05; + modbusBuf[5] = 0x06; + crc16 = CRC16_Cal(modbusBuf, 6); + modbusBuf[6] = crc16.b8[0]; + modbusBuf[7] = crc16.b8[1]; + MODBUS_UART_SendMulByte(modbusBuf, 8); + } + + MODBUS_UART_IT_RX_ENABLE; + } + else if(modbusFddRxFlg == 1) //按顺序读记录 + { + uint8_t adrh,adrl; + + modbusFddRxFlg = 0; + modbusBufIndex = 0; + + adrh = modbusBuf[2]; + adrl = modbusBuf[3]; + EEPROM_RdMulByte(EE_SOE, &modbusBuf[4]); + + //read extend cell17~20 if new format(0xA6) + if(modbusBuf[4+63] == 0xA6) + { + uint16_t rec_addr = ((uint16_t)modbusBuf[2] << 8) | modbusBuf[3]; + uint16_t ext_addr = 0x2900 + (rec_addr - 0x1000) * 6 / 64; + adrh = (ext_addr>>8) & 0xff; + adrl = ext_addr & 0xff; + EEPROM_RdMulByte(EE_SOE_EXT, &modbusBuf[4+64]); + } + else + { + memset(&modbusBuf[4+64], 0, 6); + } + + crc16 = CRC16_Cal(modbusBuf, 70+4); + modbusBuf[70+4] = crc16.b8[0]; + modbusBuf[70+5] = crc16.b8[1]; + + MODBUS_UART_SendMulByte(modbusBuf, 70+6); + MODBUS_UART_IT_RX_ENABLE; + } + else if(modbusFeeRxFlg == 1) //清除记录 + { + uint16_t i; + uint16_t pc; //待写入地址 + uint8_t adrh,adrl; + uint8_t wrBuf[64]; + + if(soe.num != 0) //存在记录，才去删除记录 + { + //先清空具体内容 + pc = 0x1000; + for(i=0;i<64;i++) + { + wrBuf[i] = 0xff; + } + for(i=0;i<100;i++) + { + adrh = (pc>>8) & 0xff; + adrl = pc & 0xff; + EEPROM_WrMulByte(EE_SOE,wrBuf); + delay_ms(10); + + pc += 0x40; + } + + //clear extend cell17~20 area + pc = 0x2900; + { + uint8_t extClear[6] = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF}; + for(i=0;i<100;i++) + { + adrh = (pc>>8) & 0xff; + adrl = pc & 0xff; + EEPROM_WrMulByte(EE_CLEAR_EXT,extClear); + delay_ms(10); + pc += 6; + } + } + + //再清空统计数据 + soe.index = 0; //起始序号0 + soe.pc = 0x1000; //起始地址0x1000 + soe.num = 0; //起始数量0 + + wrBuf[0] = (soe.index >> 24) & 0xff ; + wrBuf[1] = (soe.index >> 16) & 0xff ; + wrBuf[2] = (soe.index >> 8) & 0xff ; + wrBuf[3] = (soe.index >> 0) & 0xff ; + wrBuf[4] = (soe.pc >>8)&0XFF ; + wrBuf[5] = soe.pc & 0xff ; + wrBuf[6] = (soe.num >>8)&0XFF ; + wrBuf[7] = soe.num & 0xff ; + + EEPROM_WrMulByte(EE_SOE_INF,wrBuf); + delay_ms(10); + } + + modbusFeeRxFlg = 0; + modbusBufIndex = 0; + MODBUS_UART_SendMulByte(modbusBuf, 8 ); + MODBUS_UART_IT_RX_ENABLE; + + scr_RdRecord_Flg = 1; + } + else if(modbusFf1RxFlg == 1) //选择通信协议 + { + modbusFf1RxFlg = 0; + modbusBufIndex = 0; + + if(protocolSwitchFail == 0) //锟斤拷锟截讹拷应协锟斤拷 + { + MODBUS_UART_SendMulByte(modbusBuf, (5 + modbusBuf[2]) ); + + EEPROM_WrMulByte(EE_PROTOCOL,&protocol); + delay_ms(5); + uf_CAN1_Init();//CAN的波特率更新 + //SCR_DispProcotol(); //屏幕显示更新 + } + else + { + //失败的回复 + modbusBuf[0] = bmsMem.E2_485Addr; + modbusBuf[1] = 0xf1; + modbusBuf[2] = 0x00; + crc16 = CRC16_Cal(modbusBuf, 3); + modbusBuf[3] = crc16.b8[0]; + modbusBuf[4] = crc16.b8[1]; + MODBUS_UART_SendMulByte(modbusBuf, 5 ); + } + + MODBUS_UART_IT_RX_ENABLE; + } +} + +//接收一帧数据,帧间断小于x ms仍然认为是一帧 +//定时器中断里进行接收数据解析并准备回送数据 +void MODBUS_IT_TIMUpdate(void) +{ + if(bmsMem.E2_485Addr == 1 )//485主机模式 + { + if(modbusBufIndex > 2) + { + //要休眠，却还收到了通信，可能是有时间差，多确认几次再退出 + if(sleep_flag == 1) + { + sleepOFFcount++; + } + else + { + sleepOFFcount=0; + } + //网口3.4确定有通讯，退出休眠且更新计时起点 + if(sleepOFFcount >= 5) + { + sleep_flag = 0; + sleepOFFcount=0; + + SLEEP_Refresh(); + SLEEP2_Refresh(); + } + + if((modbusBuf[0] == bmsMem.E2_485Addr) && (modbusBuf[1] == 0x03) ) //读数据处理 + { + MODBUS_F03_Rx(MODBUS_MEM_PT); + } + else if((modbusBuf[0] == bmsMem.E2_485Addr) && (modbusBuf[1] == 0x10) ) //写数据处理 + { + MODBUS_F10_Rx(MODBUS_MEM_PT); + } + + /*V3上位机*/ + else if((modbusBuf[0] == bmsMem.E2_485Addr) && (modbusBuf[1] == 0x33) ) //上位机读数据处理 + { + PollStop_flag = 1; //3.4口兼容V3 + PollStop_count = 0; + + ConfigData_Index = 1; //主机看从机值更新回1 + scr_RdData_Index = 1; + + MODBUS_F03_Rx(MODBUS_MEM_PT); + } + + else if((modbusBuf[0] == bmsMem.E2_485Addr) && (modbusBuf[1] == 0x55) ) //上位机读取版本号 + { + MODBUS_F03_Rx(MODBUS_VersionMEM_PT); + } + else if((modbusBuf[0] == bmsMem.E2_485Addr) && (modbusBuf[1] == 0x56) ) //上位机写硬件版本号/屏幕号/SN号 + { + MODBUS_F10_Rx(MODBUS_VersionMEM_PT); + } + else if((modbusBuf[0] == bmsMem.E2_485Addr) && (modbusBuf[1] == 0x66) ) //上位机写时间 + { + if(LSEErrFlag!=1) MODBUS_F10_Rx(MODBUS_TimeMEM_PT); + } + else if((modbusBuf[0] == bmsMem.E2_485Addr) && (modbusBuf[1] == 0xaa) ) //CADC零点校准处理 + { + MODBUS_Faa_Rx(MODBUS_MEM_PT); + } + else if((modbusBuf[0] == bmsMem.E2_485Addr) && (modbusBuf[1] == 0xbb) ) //CADC增益校准处理 + { + MODBUS_Fbb_Rx(MODBUS_MEM_PT); + } + else if((modbusBuf[0] == bmsMem.E2_485Addr) && (modbusBuf[1] == 0Xdd) ) //读取记录 + { + UART1_ReadRecord(); + } + else if((modbusBuf[0] == bmsMem.E2_485Addr) && (modbusBuf[1] == 0xee) ) //清除记录 + { + UART1_ClearRecord(); + } + + else if((modbusBuf[0] == bmsMem.E2_485Addr) && (modbusBuf[1] == 0xf1) ) //F1 选择逆变器协议 + { + UART1_ProtocolSwitch(); + } + + else if((modbusBuf[0] == bmsMem.E2_485Addr) && (modbusBuf[1] == 0xf2) ) //F2 控制MOS强制关闭 + { + MODBUS_F10_Rx(MODBUS_CtrlMEM_PT); + } + else if((modbusBuf[0] == 0xff) && (modbusBuf[1] == 0xf2) ) // 广播控制MOS强制关闭 + { + MODBUS_CtrlMOS_Rx(MODBUS_CtrlMEM_PT); + } + + else if((modbusBuf[0] == bmsMem.E2_485Addr) && (modbusBuf[1] == 0xf3) ) //F3 弹窗读参数 + { + MODBUS_F03_Rx(MODBUS_ParaMEM_PT); + } + else if((modbusBuf[0] == bmsMem.E2_485Addr) && (modbusBuf[1] == 0xf4) ) //F4 弹窗写参数 + { + MODBUS_F10_Rx(MODBUS_ParaMEM_PT); + } + + + //上位机持续询问指定从机数据 + else if((ConfigData_Index>=2) && (ConfigData_Index<=paraMem.PACK_NUM)) + { + /*主机收集[上位机]指定从机数据*/ + if((modbusBuf[0] == ConfigData_Index) && (modbusBuf[1] == 0x03) ) //从机返回的读数据处理 + { + MODBUS_MASTER_F03_Rx(); + } + + #if Addr_SetAuto + /*自动分配地址 的回复*/ + else if((modbusBuf[0] == MODBUS_ASSIGN_INADDR) && (modbusBuf[1] == 0x10) ) //写数据回复的处理 + { + MODBUS_MASTER_F10_Rx(); + } + #endif + + else + { + MODBUS_Init(); //没加这个时，换地址通讯连接不上，待监控时间到重新初始化之后才恢复连接 + } + } + //屏幕查看指定从机数据 + else if((scr_RdData_Index>=2) && (scr_RdData_Index<=paraMem.PACK_NUM)) + { + /*主机收集[屏幕]指定从机数据*/ + if((modbusBuf[0] == scr_RdData_Index) && (modbusBuf[1] == 0x03) ) //单独请求从机，返回的读数据处理 + { + MODBUS_MASTER_F03_Rx(); + } + else if((modbusBuf[0] == scr_RdData_Index) && (modbusBuf[1] == 0x10) ) //从机对修改地址成功的回复 + { + MODBUS_MASTER_F10_Rx(); + } + + #if Addr_SetAuto + /*自动分配地址 的回复*/ + else if((modbusBuf[0] == MODBUS_ASSIGN_INADDR) && (modbusBuf[1] == 0x10) ) //写数据回复的处理 + { + MODBUS_MASTER_F10_Rx(); + } + #endif + + else + { + MODBUS_Init(); //没加这个时，换地址通讯连接不上，待监控时间到重新初始化之后才恢复连接 + } + } + //正常轮询 + else + { + /*主机轮询*/ + if((modbusBuf[0] == modbusCurDev) && (modbusBuf[1] == 0x03) ) //从机返回的读数据处理 + { + MODBUS_MASTER_F03_Rx(); + } + + #if Addr_SetAuto + /*自动分配地址 的回复*/ + else if((modbusBuf[0] == MODBUS_ASSIGN_INADDR) && (modbusBuf[1] == 0x10) ) //写数据回复的处理 + { + MODBUS_MASTER_F10_Rx(); + } + else + { + //轮询在询问但回复是乱码，作为自动分配启动条件 + if((paraMem.addr_FREE_Flg == 0) && (modbusCurStatus == 1) && (modbusCurDev >= 2) && (modbusCurDev <= bmsMem.E2_485Snum) && (modbusBufIndex > 10)) + { + AnswerFlag2 = 1; + } + + MODBUS_Init(); //没加这个时，换地址通讯连接不上，待监控时间到重新初始化之后才恢复连接 + } + #else + { + MODBUS_Init(); //没加这个时，换地址通讯连接不上，待监控时间到重新初始化之后才恢复连接 + } + #endif + } + } + } + else //485从机 + { + if(modbusBufIndex > 2) + { + //要休眠，却还收到了通信，可能是有时间差，多确认几次再退出 + if(sleep_flag == 1) + { + sleepOFFcount++; + } + else + { + sleepOFFcount=0; + } + //网口3.4确定有通讯，退出休眠且更新计时起点 + if(sleepOFFcount >= 5) + { + sleep_flag = 0; + sleepOFFcount=0; + + SLEEP_Refresh(); + SLEEP2_Refresh(); + } + + if((modbusBuf[0] == bmsMem.E2_485Addr) && (modbusBuf[1] == 0x03) ) //主机轮询从机 + { + MODBUS_F03_Rx(MODBUS_MEM_PT); + } + else if((modbusBuf[0] == bmsMem.E2_485Addr) && (modbusBuf[1] == 0x10) ) //写数据处理 + { + MODBUS_F10_Rx(MODBUS_MEM_PT); + } + + /*V3上位机*/ + else if((modbusBuf[0] == bmsMem.E2_485Addr) && (modbusBuf[1] == 0x33) ) //上位机读数据处理 + { + MODBUS_F03_Rx(MODBUS_MEM_PT); + } + + else if((modbusBuf[0] == bmsMem.E2_485Addr) && (modbusBuf[1] == 0x55) ) //上位机读取版本号 + { + MODBUS_F03_Rx(MODBUS_VersionMEM_PT); + } + else if((modbusBuf[0] == bmsMem.E2_485Addr) && (modbusBuf[1] == 0x56) ) //上位机写硬件版本号/屏幕号/SN号 + { + MODBUS_F10_Rx(MODBUS_VersionMEM_PT); + } + else if((modbusBuf[0] == bmsMem.E2_485Addr) && (modbusBuf[1] == 0x66) ) //上位机写时间 + { + if(LSEErrFlag!=1) MODBUS_F10_Rx(MODBUS_TimeMEM_PT); + } + else if((modbusBuf[0] == bmsMem.E2_485Addr) && (modbusBuf[1] == 0xaa) ) //CADC零点校准处理 + { + MODBUS_Faa_Rx(MODBUS_MEM_PT); + } + else if((modbusBuf[0] == bmsMem.E2_485Addr) && (modbusBuf[1] == 0xbb) ) //CADC增益校准处理 + { + MODBUS_Fbb_Rx(MODBUS_MEM_PT); + } + else if((modbusBuf[0] == bmsMem.E2_485Addr) && (modbusBuf[1] == 0Xdd) ) //读取记录 + { + UART1_ReadRecord(); + } + else if((modbusBuf[0] == bmsMem.E2_485Addr) && (modbusBuf[1] == 0xee) ) //清除记录 + { + UART1_ClearRecord(); + } + + else if((modbusBuf[0] == bmsMem.E2_485Addr) && (modbusBuf[1] == 0xf1) ) //F1 选择逆变器协议 + { + UART1_ProtocolSwitch(); + } + + else if((modbusBuf[0] == bmsMem.E2_485Addr) && (modbusBuf[1] == 0xf2) ) //F2 控制MOS强制关闭 + { + MODBUS_F10_Rx(MODBUS_CtrlMEM_PT); + } + else if((modbusBuf[0] == 0xff) && (modbusBuf[1] == 0xf2) ) // 广播控制MOS强制关闭 + { + MODBUS_CtrlMOS_Rx(MODBUS_CtrlMEM_PT); + } + + else if((modbusBuf[0] == bmsMem.E2_485Addr) && (modbusBuf[1] == 0xf3) ) //F3 弹窗读参数 + { + MODBUS_F03_Rx(MODBUS_ParaMEM_PT); + } + else if((modbusBuf[0] == bmsMem.E2_485Addr) && (modbusBuf[1] == 0xf4) ) //F4 弹窗写参数 + { + MODBUS_F10_Rx(MODBUS_ParaMEM_PT); + } + + #if Addr_SetAuto + else if((modbusBuf[0] == 0xff) && (modbusBuf[1] == 0x10) ) //主机广播写队列标志位 + { + MODBUS_WrIndex_Rx(); + } + #endif + + else + { + MODBUS_Init(); //没加这个时，换地址通讯连接不上，待监控时间到重新初始化之后才恢复连接 + } + } + } +} + +/**************************************** +**** MODBUS F03 读报文 ***** +** M: 01 03 00 addr 00 lenth CRCL H ** +** S: 01 03 2*lenth DATA0-N CRCL H ** +*****************************************/ +void MODBUS_F03_Rx(uint8_t *mem) +{ + uint8_t i; + BYTE2 crc16; + uint16_t adr; + uint8_t len; + uint8_t *data; + + //CRC判断 + crc16 = CRC16_Cal(modbusBuf, 6); + if( (modbusBuf[7] == crc16.b8[1]) && (modbusBuf[6] == crc16.b8[0]) ) + { + adr = (uint16_t)modbusBuf[3] <<1; + len = modbusBuf[5] <<1; + modbusBuf[2] = len; + + //高字节在前 + data = mem+adr; + for(i=0;i bmsMem.E2_485Snum) && (modbusBufIndex > 10)) + { + AnswerFlag1 = 1; + } + } + + /*若在CRC校验码之后还有报文，记录为启动自动分配条件*/ + if((paraMem.addr_FREE_Flg == 0) && (modbusCurStatus == 1) && (modbusBuf[len+5] != 0) && (modbusBuf[len+6] != 0)) + { + AnswerFlag2 = 1; + } + #endif +} + +/*********************************************** +**** MODBUS F10 写报文回复报文的解析 ***** +** M: 01 10 ADRH L 0 LENTH 2LETH DATAn CRCL H ** +** S: 01 10 ADRH L 0 LENTH CRCL CRCH ** +************************************************/ +void MODBUS_MASTER_F10_Rx(void) +{ + BYTE2 crc16; + + //CRC判断 + crc16 = CRC16_Cal(modbusBuf, 6); + if( (modbusBuf[7] == crc16.b8[1]) && (modbusBuf[6] == crc16.b8[0]) ) + { + modbusCurF10RxFlag = 1; + MODBUS_UART_IT_RX_DISABLE; + } +} + +//设为主机时，500MS调用1次 +void MODBUS_MASTER_Polling_Tx(void) +{ + uint8_t i; + uint16_t tmp; + + BYTE2 crc16; + + if(modbusCurStatus != 1) + { + modbusCurStatus = 1; + MODBUS_Init(); + } + + //主机接收上一帧的数据并处理 + if(modbusCurSta == 1) + { + modbusCurSta = 0; + + if(modbusCurF03RxFlag == 1) //收到数据且CRC校验正确 + { + modbusCurF03RxFlag = 0; + + canMem[modbusCurDev].status_byte1 = modbusBuf[3]<<8 | modbusBuf[4]; + canMem[modbusCurDev].status_byte2 = modbusBuf[5]<<8 | modbusBuf[6]; + canMem[modbusCurDev].status_byte3 = modbusBuf[7]<<8 | modbusBuf[8]; + canMem[modbusCurDev].status_byte4 = modbusBuf[9]<<8 | modbusBuf[10]; + canMem[modbusCurDev].soc = modbusBuf[12]; + canMem[modbusCurDev].soh = modbusBuf[11]; + canMem[modbusCurDev].cur = (int16_t)(modbusBuf[13]<<8 | modbusBuf[14]); + canMem[modbusCurDev].temp = (int16_t)(modbusBuf[15]<<8 | modbusBuf[16]); + + canMem[modbusCurDev].VolMax = modbusBuf[17]<<8 | modbusBuf[18]; + canMem[modbusCurDev].VolMin = modbusBuf[19]<<8 | modbusBuf[20]; + canMem[modbusCurDev].VolMaxIndex = modbusBuf[21]<<8 | modbusBuf[22]; + canMem[modbusCurDev].VolMinIndex = modbusBuf[23]<<8 | modbusBuf[24]; + canMem[modbusCurDev].TempMax = modbusBuf[25]<<8 | modbusBuf[26]; + canMem[modbusCurDev].TempMin = modbusBuf[27]<<8 | modbusBuf[28]; + canMem[modbusCurDev].TempMaxIndex = modbusBuf[29]<<8 | modbusBuf[30]; + canMem[modbusCurDev].TempMinIndex = modbusBuf[31]<<8 | modbusBuf[32]; + + //Wh版屏幕 + canMem[modbusCurDev].cumuliCap = modbusBuf[35]<<8 | modbusBuf[36]; + canMem[modbusCurDev].cycleCnt = modbusBuf[37]<<8 | modbusBuf[38]; + + //负值矫正 + canMem[modbusCurDev].cellVoltageMax = (int16_t)(canMem[modbusCurDev].VolMax*32/5)*5/32; + canMem[modbusCurDev].cellVoltageMin = (int16_t)(canMem[modbusCurDev].VolMin*32/5)*5/32; + + tmp = modbusBuf[33]<<8 | modbusBuf[34]; + if(tmp > AddrMax) //队列标志的取值范围在AddrMax+1~65535 + { + canMem[modbusCurDev].com = tmp; //赋值队列标志 + } + else + { + canMem[modbusCurDev].com = 1; //接收数据OK + } + } + else //未收到回复 + { + canMem[modbusCurDev].status_byte1 = 0; + canMem[modbusCurDev].status_byte2 = 0; + canMem[modbusCurDev].status_byte3 = 0; + canMem[modbusCurDev].status_byte4 = 0; + canMem[modbusCurDev].soc = 0; + canMem[modbusCurDev].soh = 0; + canMem[modbusCurDev].cur = 0; + canMem[modbusCurDev].temp = 0; + + canMem[modbusCurDev].VolMax = 0; + canMem[modbusCurDev].VolMin = 0; + canMem[modbusCurDev].VolMaxIndex = 0; + canMem[modbusCurDev].VolMinIndex = 0; + canMem[modbusCurDev].TempMax = 0; + canMem[modbusCurDev].TempMin = 0; + canMem[modbusCurDev].TempMaxIndex = 0; + canMem[modbusCurDev].TempMinIndex = 0; + + //Wh版屏幕 + canMem[modbusCurDev].cumuliCap = 0; + canMem[modbusCurDev].cycleCnt = 0; + + //负值矫正 + canMem[modbusCurDev].cellVoltageMax = 0; + canMem[modbusCurDev].cellVoltageMin = 0; + + canMem[modbusCurDev].com = 0;//接收数据FAIL + } + + //无报警正常轮询下一个，有报警的话再询问一遍(为简单，对满充时的充电过压不报警不做区分，这里不考虑) + if(((canMem[modbusCurDev].status_byte1 & 0x067e) != 0) || ((canMem[modbusCurDev].status_byte2 & 0x00ff) != 0) || ((canMem[modbusCurDev].status_byte3 & 0x0008) != 0) || ((canMem[modbusCurDev].status_byte4 & 0x0f7f) != 0)) + { + if(ReAskFlag == 0) + { + //再问一遍，此时modbusCurDev不变 + ReAskFlag = 1; + } + else + { + ReAskFlag = 0; + modbusCurDev++; + } + } + else + { + ReAskFlag = 0; + modbusCurDev++; + } + + //当轮询02~paraMem.PACK_NUM结束后，汇总数据、分析数据 + if(modbusCurDev > paraMem.PACK_NUM) + { + /*收集最后一个在线BMS的地址*/ + bmsMem.E2_485Snum = 1; + modbusCurLastAddr = 1; + for(i=2;i<=paraMem.PACK_NUM;i++) + { + if(canMem[i].com != 0) //引入队列标志位后的改动 + { + bmsMem.E2_485Snum++; + modbusCurLastAddr = i; + } + } + + #if Addr_SetAuto + /**** 分配地址启用条件判断 ****/ + if(paraMem.addr_FREE_Flg == 0) + { + //1.当在线个数和最后一个在线的通信地址的值不同，说明中间有地址不在，需要启动分配地址 + if(bmsMem.E2_485Snum != modbusCurLastAddr) + { + assign_ready_count1++; + if(assign_ready_count1 >= 2) //出现2次后触发，约20s + { + assignAddr_State = 1; + assign_ready_count1 = 0; + } + } + else + { + assign_ready_count1 = 0; + } + //2.当持续搜不到从机时，需要启动分配地址 + if(bmsMem.E2_485Snum == 1) + { + assign_ready_count2++; + if(assign_ready_count2 >= AddrMax-paraMem.PACK_NUM+2) //防止在并联数很少的情况时，因找不到从机而反复启动分配 + { + assignAddr_State = 1; + assign_ready_count2 = 0; + } + } + else + { + assign_ready_count2 = 0; + } + //3.当发现在线但 没有标志位/标志位和主机上次分配时不同时，需要启动分配地址 + uint8_t IndexFlag = 0;//用来遍历可能在线的从机，判断是否有队列标志不同的在线从机 + for(i=2;i<=paraMem.PACK_NUM;i++) + { + if((canMem[i].com != 0) && (canMem[i].com != canMem[1].com)) + { + IndexFlag = 1; + } + } + if(IndexFlag == 1) + { + assign_ready_count3++; + if(assign_ready_count3 >= 2) //出现2次后触发，约20s + { + assignAddr_State = 1; + assign_ready_count3 = 0; + } + } + else + { + assign_ready_count3 = 0; + } + //4.当发现对在线总个数以外的地址有回复但是乱码时，需要启动分配地址 + if(AnswerFlag1 == 1) + { + AnswerFlag1 = 0; + assign_ready_count4++; + if(assign_ready_count4 >= 2) //出现2次后触发，约20s + { + assignAddr_State = 1; + assign_ready_count4 = 0; + } + } + else + { + assign_ready_count4 = 0; + } + //5.当发现对在线总个数内的地址有回复但字节数超出时，需要启动分配地址 + if(AnswerFlag2 == 1) + { + AnswerFlag2 = 0; + assign_ready_count5++; + if(assign_ready_count5 >= 10) //出现10次后触发，约100s + { + assignAddr_State = 1; + assign_ready_count5 = 0; + } + } + else + { + assign_ready_count5 = 0; + } + } + #endif + + modbusCurDev = 2; + } + } + //主机发送对下一个从机的轮询 + if(modbusCurSta == 0) + { + modbusBufIndex = 0; + modbusBuf[0] = modbusCurDev; + modbusBuf[1] = 0x03; + modbusBuf[2] = 0x00; + modbusBuf[3] = 0x4B; + modbusBuf[4] = 0x00; + modbusBuf[5] = 0x12; //增加最大最小值相关 //增加队列标志 //标志位变u16 //Wh版屏幕，增加循环次数和累计容量 + crc16 = CRC16_Cal(modbusBuf, 6); + modbusBuf[6] = crc16.b8[0]; + modbusBuf[7] = crc16.b8[1]; + MODBUS_UART_SendMulByte(modbusBuf, 8); + + modbusCurSta = 1; + modbusCurF03RxFlag = 0; + MODBUS_UART_IT_RX_ENABLE; + } +} + +#if Addr_SetAuto +//主机先置高OUT初始化所有从机地址，再置低OUT让第一个从机为21，然后向地址21传正确地址 +void MODBUS_AddrAssign_Tx(void) +{ + uint8_t tmp[2]; + + BYTE2 crc16; + + if(assignAddr_Step == 0) + { + IO2_OUTSet(); //OUT引脚置高，让从机1地址99，输出置高 + assignAddr_Step = 1; + } + else if(assignAddr_Step == 1) + { + IO2_OUTReset(); //OUT引脚置低，让从机1地址AddrMax+1 + assignAddr_Step = 2; + } + else if((assignAddr_Step >= 2) && (assignAddr_Step <= paraMem.PACK_NUM)) //分配地址，和并机总数有关 + { + if(modbusCurStatus != 2) + { + modbusCurStatus = 2; + MODBUS_Init(); + } + + /*写地址时间稍长，真正时序是1s1次*/ + //主机接收上一帧的数据并处理 + if(modbusCurSta == 2) //主机接收数据处理 + { + modbusCurSta = 0; + + if(modbusCurF10RxFlag == 1) //收到数据且CRC校验正确，准备询问下一个 + { + modbusCurF10RxFlag = 0; + assignAddr_Failcount = 0; + + if(assignAddr_Step < paraMem.PACK_NUM) //非最后1个 + { + assignAddr_Step++; + } + else + { + //当可用地址的最后一个也分配成功，已经配置完所有在线从机 + assignAddr_State = 2;//已执行过分配 + + assignAddr_485num = assignAddr_Step; + assignAddr_Step = 0; //清空 + MODBUS_Init(); //初始化 + + assignAddr_random = get_random(); + assignAddr_WrIndex_Flg = 1; + + return; //退出，不执行发送 + } + } + else //未接收数据或数据错误，继续发送原写寄存器报文 + { + assignAddr_Failcount++; + + if(assignAddr_Failcount > 5) + { + assignAddr_Failcount = 0; + + //发送多次还未收到正确回复，认为已经配置完所有在线从机 + assignAddr_State = 2;//已执行过分配 + + assignAddr_485num = assignAddr_Step-1; + assignAddr_Step = 0; //清空 + MODBUS_Init(); //初始化 + + assignAddr_random = get_random(); + if(assignAddr_485num > 1) //存在从机才要下发队列标志 + { + assignAddr_WrIndex_Flg = 1; + } + + return; //退出，不执行发送 + } + } + } + //主机发送对下一个从机的分配地址 + if(modbusCurSta == 0) + { + tmp[0] = assignAddr_Step; + tmp[1] = CRC8_Cal(tmp,1); + + modbusBufIndex = 0; + modbusBuf[0] = MODBUS_ASSIGN_INADDR; + modbusBuf[1] = 0x10; + modbusBuf[2] = 0x00; + modbusBuf[3] = 0x48; + modbusBuf[4] = 0x00; + modbusBuf[5] = 0x01; + modbusBuf[6] = 0x02; + modbusBuf[7] = tmp[0]; + modbusBuf[8] = tmp[1]; + crc16 = CRC16_Cal(modbusBuf, 9); + modbusBuf[9] = crc16.b8[0]; + modbusBuf[10] = crc16.b8[1]; + MODBUS_UART_SendMulByte(modbusBuf, 11); + + modbusCurSta = 1; + modbusCurF10RxFlag = 0; + MODBUS_UART_IT_RX_ENABLE; + } + //1，给从机反应时间 + else + { + modbusCurSta++; + } + } +} + +//主机广播队列标志 +void MODBUS_WrIndex_Tx(void) +{ + BYTE2 crc16; + + modbusBufIndex = 0; + modbusBuf[0] = 0xff; + modbusBuf[1] = 0x10; + modbusBuf[2] = 0x00; + modbusBuf[3] = 0x00; + modbusBuf[4] = 0x00; + modbusBuf[5] = 0x01; + modbusBuf[6] = 0x02; + modbusBuf[7] = assignAddr_random & 0xff; + modbusBuf[8] = (assignAddr_random>>8) & 0xff; + crc16 = CRC16_Cal(modbusBuf, 9); + modbusBuf[9] = crc16.b8[0]; + modbusBuf[10] = crc16.b8[1]; + MODBUS_UART_SendMulByte(modbusBuf, 11); + + MODBUS_UART_IT_RX_ENABLE; +} + +//从机收到广播的队列标志 +void MODBUS_WrIndex_Rx(void) +{ + BYTE2 crc16; + + //CRC判断 + crc16 = CRC16_Cal(modbusBuf, 2+7); + if( (modbusBuf[2+8] == crc16.b8[1]) && (modbusBuf[2+7] == crc16.b8[0]) ) + { + if(assignAddr_State == 2) //经历过自动分配地址 + { + uint8_t tmp[2]; + bmsMem.can_ArrayIndex = modbusBuf[8]<<8 | modbusBuf[7]; + tmp[0] = modbusBuf[8]; + tmp[1] = modbusBuf[7]; + EEPROM_WrMulByte(EE_ASSIGN,tmp); + delay_ms(5); + } + + MODBUS_Init(); + } +} +#endif + +//主机因[屏幕]获取固定从机数据，并显示在屏幕上 +void MODBUS_Screen_RdSlave_Tx(void) +{ + uint8_t *data; + uint8_t len; + uint8_t i; + + BYTE2 crc16; + + if(modbusCurStatus != 3) + { + modbusCurStatus = 3; + MODBUS_Init(); + } + + //主机接收上一帧的数据并处理 + if(modbusCurSta == 1) + { + modbusCurSta = 0; + + if(modbusCurF03RxFlag == 1) //收到数据且CRC校验正确 + { + data = (uint8_t *)&bmsMem_slave.vCell[0]; + len = modbusBuf[2]; + + for(i=0;i3) + { + sdwa_WrAddr_Failcount = 0; + sdwa_WrAddr_Flg = 3; + } + } + } + //主机发送对固定从机的写地址 + if(modbusCurSta == 0) + { + tmp[0] = sdwa_WrAddr; + tmp[1] = CRC8_Cal(tmp,1); + + modbusBufIndex = 0; + modbusBuf[0] = scr_RdData_Index; + modbusBuf[1] = 0x10; + modbusBuf[2] = 0x00; + modbusBuf[3] = 0x48; + modbusBuf[4] = 0x00; + modbusBuf[5] = 0x01; + modbusBuf[6] = 0x02; + modbusBuf[7] = tmp[0]; + modbusBuf[8] = tmp[1]; + crc16 = CRC16_Cal(modbusBuf, 9); + modbusBuf[9] = crc16.b8[0]; + modbusBuf[10] = crc16.b8[1]; + MODBUS_UART_SendMulByte(modbusBuf, 11); + + modbusCurSta = 1; + modbusCurF10RxFlag = 0; + MODBUS_UART_IT_RX_ENABLE; + } +} + +//主机因[上位机]获取固定从机数据，并在下一次上位机询问时回复 +void MODBUS_Config_RdSlave_Tx(void) +{ + uint8_t *data; + uint8_t len; + uint8_t i; + + BYTE2 crc16; + + if(modbusCurStatus != 5) + { + modbusCurStatus = 5; + MODBUS_Init(); + } + + //主机接收上一帧的数据并处理 + if(modbusCurSta == 1) + { + modbusCurSta = 0; + + if(modbusCurF03RxFlag == 1) //收到数据且CRC校验正确 + { + Online_Flag = 1; //下次上位机询问，可以回复 + + data = (uint8_t *)&bmsMem_slave.vCell[0]; + len = modbusBuf[2]; + + for(i=0;i=0 && num<=ProtocolIdxSum) + { + if(num==0) //2026.2.10增加读协议 + { + num = protocol; + } + + if(protocol != 0) + { + protocolSwitchFail = 0; //存在该协议，选中，并返回协议名称 + protocol = num; + + //将选中的字符串复制到一个新的字符数组中,获取字符串的长度 + uint8_t ArrayIdx = protocolIdx[num-1]; + + if(ArrayIdx != 0) + { + strcpy(name,protocolStrings[ArrayIdx-1]); + namelen = strlen(name); + + //生成输出报文 + modbus1Buf[2] = namelen; + for(i=0;i= MODBUS1_BUF_LEN ) + { + modbus1BufIndex = 0; + } + + //每次接收数据中断清除定时器计数器并启动计数器 + //如定时器溢出中断，表示一帧数据接收完成 + TIM_SetCounter(MODBUS1_UART_TIM, 0); + TIM_Cmd(MODBUS1_UART_TIM, ENABLE); +} + +//查询发送数据 +void MODBUS1_IQ_Transmit(void) +{ + BYTE2 crc16; + + if(modbus1F03RxFlg == 1) + { + modbus1F03RxFlg = 0; + modbus1BufIndex = 0; + MODBUS1_UART_SendMulByte(modbus1Buf, (5 + modbus1Buf[2]) ); + MODBUS1_UART_IT_RX_ENABLE; + } + else if(modbus1VoltronicRxFlg == 1) + { + modbus1VoltronicRxFlg = 0; + modbus1BufIndex = 0; + MODBUS1_UART_SendMulByte(modbus1Buf, (6 + (modbus1Buf[3]<<1)) ); + MODBUS1_UART_IT_RX_ENABLE; + } + else if(ydn23RxFlg == 1) + { + ydn23RxFlg = 0; + modbus1BufIndex = 0; + MODBUS1_UART_SendMulByte(modbus1Buf, INFOlen+18); + MODBUS1_UART_IT_RX_ENABLE; + } + else if(modbus1F10RxFlg == 1) + { + modbus1F10RxFlg = 0; + modbus1BufIndex = 0; + + if(modbus1Buf[1] == 0x10) //写参数需要存入flash + { + //bmsMem中数据更新到FLASH A区和B区和AFE EEPORM + if((MEMORY_UpdateFlash(FLASH_DATA_A_BASE) == 0) && (MEMORY_UpdateFlash(FLASH_DATA_B_BASE) == 0)) + { + staPack.bits.flashUpdate= 0; + if(MEMORY_UpdateAFE() ==0) //更新AFE EEPROM内容 + { + staPack.bits.eepromUpdate = 0; + MODBUS1_UART_SendMulByte(modbus1Buf, 8); + } + else + { + staPack.bits.eepromUpdate = 1; + } + } + else + { + staPack.bits.flashUpdate= 1; + } + bmsMem.packStatus = staPack.byte; + } + else if(modbus1Buf[1] == 0xf4) + { + if((MEMORY_UpdateFlash(FLASH_DATA_A_BASE) == 0) && (MEMORY_UpdateFlash(FLASH_DATA_B_BASE) == 0)) + { + staPack.bits.flashUpdate= 0; + if(MEMORY_UpdateAFE() ==0) + { + staPack.bits.eepromUpdate = 0; + MODBUS1_UART_SendMulByte(modbus1Buf, 8); + } + else + { + staPack.bits.eepromUpdate = 1; + } + } + else + { + staPack.bits.flashUpdate= 1; + } + bmsMem.packStatus = staPack.byte; + } + else if(modbus1Buf[1] == 0x56) //写SN号需要写入EEPROM + { + uint8_t i; + uint8_t *data; + uint8_t tmpWr[16]; + + if(modbus1Buf[3] == 0x00) //对应硬件版本号的地址 + { + MODBUS1_UART_SendMulByte(modbus1Buf, 8); + EEPROM_WrMulByte(EE_Hardware,VersionMem.Hardware); + delay_ms(5); + + //填充HardwareVersion + Refresh_HardwareVersion(); + } + else if(modbus1Buf[3] == 0x01) //对应屏幕号的地址 + { + MODBUS1_UART_SendMulByte(modbus1Buf, 8); + EEPROM_WrMulByte(EE_Screen,&VersionMem.Screen); + delay_ms(5); + + //填充ScreenVersion + Refresh_ScreenVersion(); + } + else if(modbus1Buf[3] == 0x04) //对应BMS的SN号的地址 + { + data = (uint8_t *)&VersionMem.BMS_SN[0]; + for(i=0;i<9+1;i++) + { + tmpWr[i] = *data; + data++; + } + MODBUS1_UART_SendMulByte(modbus1Buf, 8); + + + EEPROM_WrMulByte(EE_BMS_SN,tmpWr); //写入EEPROM + delay_ms(5); + + Refresh_BMS_SN(); //更新BMS_SN字符串 + + /*三选一模块*/ + #if BLE_Conn + BLE_WriteName(); //更新蓝牙名称 + #endif + #if LTE_Conn + LTE_UNSUB_Flag = 1; //因为订阅主题变动，需要对此前的订阅进行取消绑定 + EEPROM_WrMulByte(EE_UNSUB,<E_UNSUB_Flag); + delay_ms(5); + + if(LTE_LINK_flag == 1) //若原来已连接4G服务器，断开并重新正确连接 + { + LTE_LINK_flag = 0; //已连接标志清零 + + MQTT_RST_flag = 1; //断开再连接MQTT服务器 + MQTT_RST_step = 0; + + MQTT_START_flag = 0; + MQTT_READY_flag = 0; + MQTT_timed_count = 0; //清零定时上报倒计时 + + LTE_OTA_Flag = 0; //OTA升级标志清零 + } + + LTE_4G_Domain_ChangeSN(); //更新4G通信凭证 + #endif + } + else if(modbus1Buf[3] == 0x09) //对应PACK的SN号的地址 + { + data = (uint8_t *)&VersionMem.PACK_SN[0]; + for(i=0;i<15+1;i++) + { + tmpWr[i] = *data; + data++; + } + + MODBUS1_UART_SendMulByte(modbus1Buf, 8); + EEPROM_WrMulByte(EE_PACK_SN,tmpWr); + delay_ms(5); + + //填充PACK_SN + Refresh_PACK_SN(); + } + #if LTE_Conn + else if(modbus1Buf[3] == 0x20) //对应4G通信凭证的起始地址 + { + if(LTE_LINK_flag == 1) + { + LTE_LINK_flag = 0; //已连接标志清零 + + MQTT_RST_flag = 1; //断开再连接MQTT服务器 + MQTT_RST_step = 0; + + MQTT_START_flag = 0; + MQTT_READY_flag = 0; + MQTT_timed_count = 0; //清零定时上报倒计时 + + LTE_OTA_Flag = 0; //OTA升级标志清零 + } + + //计算CRC校验值 + static uint8_t temp[HOSTMEM_LEN]; + memcpy(temp, &VersionMem.host[0], HOSTMEM_LEN); + + VersionMem.hostAll_crc = CRC8_Cal(&temp[0], 153); + + //更新Flash + if((MEMORY_UpdateFlash(FLASH_DATA_A_BASE) == 0) && (MEMORY_UpdateFlash(FLASH_DATA_B_BASE) == 0)) + { + staPack.bits.flashUpdate = 0; + } + else + { + staPack.bits.flashUpdate = 1; + } + bmsMem.packStatus = staPack.byte; + + MODBUS1_UART_SendMulByte(modbus1Buf, 8); + } + #endif + } + else + { + MODBUS1_UART_SendMulByte(modbus1Buf, 8); + } + + MODBUS1_UART_IT_RX_ENABLE; + } + else if(modbus1FaaRxFlg == 1) + { + modbus1FaaRxFlg = 0; + modbus1BufIndex = 0; + + if(cali.flagZeroCaliFail ==0) //ok + { + // 01 AA 5A A5 03 04 CRCL H + modbus1Buf[0] = bmsMem.E2_485Addr; + modbus1Buf[1] = 0xaa; + modbus1Buf[2] = 0x5a; + modbus1Buf[3] = 0xa5; + modbus1Buf[4] = 0x03; + modbus1Buf[5] = 0x04; + crc16 = CRC16_Cal(modbus1Buf, 6); + modbus1Buf[6] = crc16.b8[0]; + modbus1Buf[7] = crc16.b8[1]; + MODBUS1_UART_SendMulByte(modbus1Buf, 8); + } + else //fail + { + // 01 AA 5A A5 05 06 CRCL H + modbus1Buf[0] = bmsMem.E2_485Addr; + modbus1Buf[1] = 0xaa; + modbus1Buf[2] = 0x5a; + modbus1Buf[3] = 0xa5; + modbus1Buf[4] = 0x05; + modbus1Buf[5] = 0x06; + crc16 = CRC16_Cal(modbus1Buf, 6); + modbus1Buf[6] = crc16.b8[0]; + modbus1Buf[7] = crc16.b8[1]; + MODBUS1_UART_SendMulByte(modbus1Buf, 8); + } + + MODBUS1_UART_IT_RX_ENABLE; + } + else if(modbus1FbbRxFlg == 1) + { + modbus1FbbRxFlg = 0; + modbus1BufIndex = 0; + + if(cali.flagGainCaliFail ==0) //ok + { + // 01 AA 5A A5 03 04 CRCL H + modbus1Buf[0] = bmsMem.E2_485Addr; + modbus1Buf[1] = 0xbb; + modbus1Buf[2] = 0x5b; + modbus1Buf[3] = 0xb5; + modbus1Buf[4] = 0x03; + modbus1Buf[5] = 0x04; + crc16 = CRC16_Cal(modbus1Buf, 6); + modbus1Buf[6] = crc16.b8[0]; + modbus1Buf[7] = crc16.b8[1]; + MODBUS1_UART_SendMulByte(modbus1Buf, 8); + } + else //fail + { + // 01 AA 5A A5 05 06 CRCL H + modbus1Buf[0] = bmsMem.E2_485Addr; + modbus1Buf[1] = 0xbb; + modbus1Buf[2] = 0x5b; + modbus1Buf[3] = 0xb5; + modbus1Buf[4] = 0x05; + modbus1Buf[5] = 0x06; + crc16 = CRC16_Cal(modbus1Buf, 6); + modbus1Buf[6] = crc16.b8[0]; + modbus1Buf[7] = crc16.b8[1]; + MODBUS1_UART_SendMulByte(modbus1Buf, 8); + } + + MODBUS1_UART_IT_RX_ENABLE; + } + else if(modbus1FddRxFlg == 1) //按顺序读记录 + { + uint8_t adrh,adrl; + + modbus1FddRxFlg = 0; + modbus1BufIndex = 0; + + adrh = modbus1Buf[2]; + adrl = modbus1Buf[3]; + EEPROM_RdMulByte(EE_SOE, &modbus1Buf[4]); + + if(modbus1Buf[4+63] == 0xA6) + { + uint16_t rec_addr = ((uint16_t)modbus1Buf[2] << 8) | modbus1Buf[3]; + uint16_t ext_addr = 0x2900 + (rec_addr - 0x1000) * 6 / 64; + adrh = (ext_addr>>8) & 0xff; + adrl = ext_addr & 0xff; + EEPROM_RdMulByte(EE_SOE_EXT, &modbus1Buf[4+64]); + } + else + { + memset(&modbus1Buf[4+64], 0, 6); + } + + crc16 = CRC16_Cal(modbus1Buf, 70+4); + modbus1Buf[70+4] = crc16.b8[0]; + modbus1Buf[70+5] = crc16.b8[1]; + + MODBUS1_UART_SendMulByte(modbus1Buf, 70+6); + MODBUS1_UART_IT_RX_ENABLE; + } + else if(modbus1FeeRxFlg == 1) //清除记录 + { + uint16_t i; + uint16_t pc; //待写入地址 + uint8_t adrh,adrl; + uint8_t wrBuf[64]; + + if(soe.num != 0) //存在记录，才去删除记录 + { + //先清空具体内容 + pc = 0x1000; + for(i=0;i<64;i++) + { + wrBuf[i] = 0xff; + } + for(i=0;i<100;i++) + { + adrh = (pc>>8) & 0xff; + adrl = pc & 0xff; + EEPROM_WrMulByte(EE_SOE,wrBuf); + delay_ms(10); + + pc += 0x40; + } + + //clear extend cell17~20 area + pc = 0x2900; + { + uint8_t extClear[6] = {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF}; + for(i=0;i<100;i++) + { + adrh = (pc>>8) & 0xff; + adrl = pc & 0xff; + EEPROM_WrMulByte(EE_CLEAR_EXT,extClear); + delay_ms(10); + pc += 6; + } + } + + //再清空统计数据 + soe.index = 0; //起始序号0 + soe.pc = 0x1000; //起始地址0x1000 + soe.num = 0; //起始数量0 + + wrBuf[0] = (soe.index >> 24) & 0xff ; + wrBuf[1] = (soe.index >> 16) & 0xff ; + wrBuf[2] = (soe.index >> 8) & 0xff ; + wrBuf[3] = (soe.index >> 0) & 0xff ; + wrBuf[4] = (soe.pc >>8)&0XFF ; + wrBuf[5] = soe.pc & 0xff ; + wrBuf[6] = (soe.num >>8)&0XFF ; + wrBuf[7] = soe.num & 0xff ; + + EEPROM_WrMulByte(EE_SOE_INF,wrBuf); + delay_ms(10); + } + + modbus1FeeRxFlg = 0; + modbus1BufIndex = 0; + MODBUS1_UART_SendMulByte(modbus1Buf, 8 ); + MODBUS1_UART_IT_RX_ENABLE; + + scr_RdRecord_Flg = 1; + } + else if(modbus1Ff1RxFlg == 1) //选择通信协议 + { + modbus1Ff1RxFlg = 0; + modbus1BufIndex = 0; + + if(protocolSwitchFail == 0) //返回对应协议 + { + MODBUS1_UART_SendMulByte(modbus1Buf, (5 + modbus1Buf[2]) ); + + EEPROM_WrMulByte(EE_PROTOCOL,&protocol); + delay_ms(5); + uf_CAN1_Init();//CAN的波特率更新 + //SCR_DispProcotol(); //屏幕显示更新 + } + else + { + //失败的回复 + modbus1Buf[0] = bmsMem.E2_485Addr; + modbus1Buf[1] = 0xf1; + modbus1Buf[2] = 0x00; + crc16 = CRC16_Cal(modbus1Buf, 3); + modbus1Buf[3] = crc16.b8[0]; + modbus1Buf[4] = crc16.b8[1]; + MODBUS1_UART_SendMulByte(modbus1Buf, 5 ); + } + + MODBUS1_UART_IT_RX_ENABLE; + } + + else if(cmdRxIapFlg == 1) + { +// uint8_t Update_Index; //跳转位置的标识 +// uint32_t Update_Addr; //根据标识计算出的位置 +// uint32_t firmware_jump;//程序标志 +// +// /** 擦除FLash标志(不需要兼容旧IAP，不用考虑) **/ +// //根据EEPROM存放标志来决定擦除哪一位 +// EEPROM_RdMulByte(EE_IAP,&Update_Index); +// if((Update_Index != 0) && (Update_Index != 1)) //Update_Index范围是0~1 +// { +// Update_Index = 1; //一般是1 +// } +// +// //读出检查，确认是这个位置 +// Update_Addr = FLASH_PAGE_ADDR + 0x10000 * Update_Index; +// FLASH_RdWord(Update_Addr, &firmware_jump, 1); +// if(firmware_jump == JUMP_TO_USER) +// { +// FLASH_Unlock(); +// FLASH_ClearFlag(FLASH_FLAG_BSY | FLASH_FLAG_EOP |FLASH_FLAG_PGERR | FLASH_FLAG_WRPRTERR); +// FLASH_ErasePage(Update_Addr); //擦除标志位对应page,0x0800FC00-0x0800FFFF +// FLASH_Lock(); +// } +// else +// { +// Update_Index = (Update_Index==0) ? 1:0; //取另一个地址查询，若仍然不对，那该用户程序不依靠IAP底层 +// Update_Addr = FLASH_PAGE_ADDR + 0x10000 * Update_Index; +// FLASH_RdWord(Update_Addr, &firmware_jump, 1); +// if(firmware_jump == JUMP_TO_USER) +// { +// FLASH_Unlock(); +// FLASH_ClearFlag(FLASH_FLAG_BSY | FLASH_FLAG_EOP |FLASH_FLAG_PGERR | FLASH_FLAG_WRPRTERR); +// FLASH_ErasePage(Update_Addr); //擦除标志位对应page,0x0800FC00-0x0800FFFF +// FLASH_Lock(); +// } +// } + + /** 擦除EEPROM标志 **/ + IAP_Run = 0xAA; + EEPROM_WrMulByte(EE_IAP_NEW1,&IAP_Run); //第一时间写Run_Flag + delay_ms(10); + EEPROM_WrMulByte(EE_IAP_NEW2,&IAP_Run); + delay_ms(10); + + cmdRxIapFlg = 0; + modbus1BufIndex = 0; + MODBUS1_UART_SendMulByte(modbus1Buf, 8); + MODBUS1_UART_IT_RX_ENABLE; + + delay_ms(1000); + NVIC_SystemReset(); //软件复位 + } +} + +//接收一帧数据,帧间断小于x ms仍然认为是一帧 +//定时器中断里进行接收数据解析并准备回送数据 +void MODBUS1_IT_TIMUpdate(void) +{ + if(bmsMem.E2_485Addr == 1 ) //485主机 + { + if(modbus1BufIndex > 2) + { + if(sleep_flag == 1) + { + //网口1有通讯，退出休眠且更新计时起点 + sleep_flag = 0; + SLEEP_Refresh(); + SLEEP2_Refresh(); + } + + if(modbus1Buf[0] == 0x7E) //识别为电总协议 + { + if(protocol == 12) YDN_Protocol_Pylon(); //Pylon派能 电总协议 + } + else if((modbus1Buf[0] == bmsMem.E2_485Addr) && (modbus1Buf[1] == 0x03) ) //读数据处理 + { + if(protocol == 3) MODBUS1_F03_Rx(MODBUS1_GrowattMEM_PT); //Growatt古瑞瓦特 +// else if(protocol == 6) MODBUS1_F03_Rx(MODBUS1_GrowattMEM_PT); //Sorotec索瑞德(=古瑞瓦特) +// else if(protocol == 13) MODBUS1_F03_Rx(MODBUS1_SRNEMEM_PT); //SRNE硕日 + else if(protocol == 14) MODBUS1_F03_Rx(MODBUS1_VoltronicMEM_PT); //Voltronic日月元 +// else if(protocol == 32) MODBUS1_F03_Rx(MODBUS1_SRNEMEM_PT); //COSUPER(=硕日) +// else if(protocol == 17) MODBUS1_F03_Rx(MODBUS1_SMKMEM_PT); //SMK +// else if(protocol == 31) MODBUS1_F03_Rx(MODBUS1_VoltronicMEM_PT); //SAKO(=日月元) + else + { + MODBUS1_Init(); //没加这个时，换地址通讯连接不上，待监控时间到重新初始化之后才恢复连接 + } + } + + else if((modbus1Buf[0] == bmsMem.E2_485Addr) && (modbus1Buf[1] == 0x23) ) //上位机读主机的并机在线情况 + { + PollStop_flag = 0; //3.4口兼容V3 + + ConfigData_Index = modbus1Buf[0]; + + onlineMem.vol = bmsMem.packVoltage/10; + onlineMem.cur = canMem[0].cur; + onlineMem.temp = canMem[0].temp; + onlineMem.soc = canMem[0].soc; + onlineMem.soh = canMem[0].soh; + + onlineMem.status_byte1 = canMem[0].status_byte1; + onlineMem.status_byte2 = canMem[0].status_byte2; + onlineMem.status_byte3 = canMem[0].status_byte3; + onlineMem.status_byte4 = canMem[0].status_byte4; + + onlineMem.VolMax = canMem[0].VolMax; + onlineMem.VolMin = canMem[0].VolMin; + onlineMem.VolMaxIndex = canMem[0].VolMaxIndex; + onlineMem.VolMinIndex = canMem[0].VolMinIndex; + onlineMem.TempMax = canMem[0].TempMax; + onlineMem.TempMin = canMem[0].TempMin; + onlineMem.TempMaxIndex = canMem[0].TempMaxIndex; + onlineMem.TempMinIndex = canMem[0].TempMinIndex; + + MODBUS1_F03_Rx(MODBUS1_ONLINEMEM_PT); + } + else if((modbus1Buf[0] == bmsMem.E2_485Addr) && (modbus1Buf[1] == 0x33) ) //上位机读数据处理 + { + PollStop_flag = 0; //3.4口兼容V3 + + ConfigData_Index = modbus1Buf[0]; + MODBUS1_F03_Rx(MODBUS1_MEM_PT); + } + else if((modbus1Buf[0] != bmsMem.E2_485Addr) && (modbus1Buf[1] == 0x43) ) //上位机通过主机读从机数据处理 + { + PollStop_flag = 0; //3.4口兼容V3 + + if(ConfigData_Index != modbus1Buf[0]) + { + //第一次收到对这个从机的询问(此时要回复的话肯定不是该地址的数据) + Online_Flag = 0; + ConfigData_Index = modbus1Buf[0]; + } + else + { + //当3.4口轮询到了该从机的数据，将这一帧数据返回 + if(Online_Flag == 1) + { + MODBUS1_F03_Rx(MODBUS1_SLAVEMEM_PT); + } + } + } + + else if((modbus1Buf[0] == bmsMem.E2_485Addr) && (modbus1Buf[1] == 0x10) ) //写数据处理 + { + MODBUS1_F10_Rx(MODBUS1_MEM_PT); + } + else if((modbus1Buf[0] == bmsMem.E2_485Addr) && (modbus1Buf[1] == 0x55) ) //上位机读取版本号 + { + PollStop_flag = 0; //3.4口兼容V3 + + MODBUS1_F03_Rx(MODBUS1_VersionMEM_PT); + } + else if((modbus1Buf[0] == bmsMem.E2_485Addr) && (modbus1Buf[1] == 0x56) ) //上位机写硬件版本号/屏幕号/SN号 + { + PollStop_flag = 0; //3.4口兼容V3 + + MODBUS1_F10_Rx(MODBUS1_VersionMEM_PT); + } + else if((modbus1Buf[0] == bmsMem.E2_485Addr) && (modbus1Buf[1] == 0x66) ) //上位机写时间 + { + PollStop_flag = 0; //3.4口兼容V3 + + if(LSEErrFlag!=1) MODBUS1_F10_Rx(MODBUS1_TimeMEM_PT); + } + else if((modbus1Buf[0] == bmsMem.E2_485Addr) && (modbus1Buf[1] == 0xaa) ) //CADC零点校准处理 + { + PollStop_flag = 0; //3.4口兼容V3 + + MODBUS1_Faa_Rx(MODBUS1_MEM_PT); + } + else if((modbus1Buf[0] == bmsMem.E2_485Addr) && (modbus1Buf[1] == 0xbb) ) //CADC增益校准处理 + { + PollStop_flag = 0; //3.4口兼容V3 + + MODBUS1_Fbb_Rx(MODBUS1_MEM_PT); + } + else if((modbus1Buf[0] == bmsMem.E2_485Addr) && (modbus1Buf[1] == 0Xdd) ) //读取记录 + { + PollStop_flag = 0; //3.4口兼容V3 + + UART3_ReadRecord(); + } + else if((modbus1Buf[0] == bmsMem.E2_485Addr) && (modbus1Buf[1] == 0xee) ) //清除记录 + { + PollStop_flag = 0; //3.4口兼容V3 + + UART3_ClearRecord(); + } + + else if((modbus1Buf[0] == bmsMem.E2_485Addr) && (modbus1Buf[1] == 0xf1) ) //F1 选择逆变器协议 + { + PollStop_flag = 0; //3.4口兼容V3 + + UART3_ProtocolSwitch(); + } + + else if((modbus1Buf[0] == bmsMem.E2_485Addr) && (modbus1Buf[1] == 0xf2) ) //F2 控制MOS强制关闭 + { + MODBUS1_F10_Rx(MODBUS1_CtrlMEM_PT); + } + else if((modbus1Buf[0] == 0xff) && (modbus1Buf[1] == 0xf2) ) // 广播控制MOS强制关闭 + { + MODBUS1_CtrlMOS_Rx(MODBUS1_CtrlMEM_PT); + } + + else if((modbus1Buf[0] == bmsMem.E2_485Addr) && (modbus1Buf[1] == 0xf3) ) //F3 弹窗读参数 + { + PollStop_flag = 0; //3.4口兼容V3 + + MODBUS1_F03_Rx(MODBUS1_ParaMEM_PT); + } + else if((modbus1Buf[0] == bmsMem.E2_485Addr) && (modbus1Buf[1] == 0xf4) ) //F4 弹窗写参数 + { + PollStop_flag = 0; //3.4口兼容V3 + + MODBUS1_F10_Rx(MODBUS1_ParaMEM_PT); + } + + else if((modbus1Buf[0] == 0xA7) && (modbus1Buf[1] == 0x55)) + { + UART3_EraseIAP(); //485升级操作 + } + + else + { + MODBUS1_Init(); //没加这个时，换地址通讯连接不上，待监控时间到重新初始化之后才恢复连接 + } + } + } + else //485从机 + { + if(modbus1BufIndex > 2) + { + if(sleep_flag == 1) + { + //网口1有通讯，退出休眠且更新计时起点 + sleep_flag = 0; + SLEEP_Refresh(); + SLEEP2_Refresh(); + } + + if((modbus1Buf[0] == bmsMem.E2_485Addr) && (modbus1Buf[1] == 0x33) ) //读数据处理 + { + MODBUS1_F03_Rx(MODBUS1_MEM_PT); + } + else if((modbus1Buf[0] == bmsMem.E2_485Addr) && (modbus1Buf[1] == 0x10) ) //写数据处理 + { + MODBUS1_F10_Rx(MODBUS1_MEM_PT); + } + else if((modbus1Buf[0] == bmsMem.E2_485Addr) && (modbus1Buf[1] == 0x55) ) //上位机读取版本号 + { + MODBUS1_F03_Rx(MODBUS1_VersionMEM_PT); + } + else if((modbus1Buf[0] == bmsMem.E2_485Addr) && (modbus1Buf[1] == 0x56) ) //上位机写硬件版本号/屏幕号/SN号 + { + MODBUS1_F10_Rx(MODBUS1_VersionMEM_PT); + } + else if((modbus1Buf[0] == bmsMem.E2_485Addr) && (modbus1Buf[1] == 0x66) ) //上位机写时间 + { + if(LSEErrFlag!=1) MODBUS1_F10_Rx(MODBUS1_TimeMEM_PT); + } + else if((modbus1Buf[0] == bmsMem.E2_485Addr) && (modbus1Buf[1] == 0xaa) ) //CADC零点校准处理 + { + MODBUS1_Faa_Rx(MODBUS1_MEM_PT); + } + else if((modbus1Buf[0] == bmsMem.E2_485Addr) && (modbus1Buf[1] == 0xbb) ) //CADC增益校准处理 + { + MODBUS1_Fbb_Rx(MODBUS1_MEM_PT); + } + else if((modbus1Buf[0] == bmsMem.E2_485Addr) && (modbus1Buf[1] == 0Xdd) ) //读取记录 + { + UART3_ReadRecord(); + } + else if((modbus1Buf[0] == bmsMem.E2_485Addr) && (modbus1Buf[1] == 0xee) ) //清除记录 + { + UART3_ClearRecord(); + } + + else if((modbus1Buf[0] == bmsMem.E2_485Addr) && (modbus1Buf[1] == 0xf1) ) //F1 选择逆变器协议 + { + UART3_ProtocolSwitch(); + } + + else if((modbus1Buf[0] == bmsMem.E2_485Addr) && (modbus1Buf[1] == 0xf2) ) //F2 控制MOS强制关闭 + { + MODBUS1_F10_Rx(MODBUS1_CtrlMEM_PT); + } + else if((modbus1Buf[0] == 0xff) && (modbus1Buf[1] == 0xf2) ) // 广播控制MOS强制关闭 + { + MODBUS1_CtrlMOS_Rx(MODBUS1_CtrlMEM_PT); + } + + else if((modbus1Buf[0] == bmsMem.E2_485Addr) && (modbus1Buf[1] == 0xf3) ) //F3 弹窗读参数 + { + MODBUS1_F03_Rx(MODBUS1_ParaMEM_PT); + } + else if((modbus1Buf[0] == bmsMem.E2_485Addr) && (modbus1Buf[1] == 0xf4) ) //F4 弹窗写参数 + { + MODBUS1_F10_Rx(MODBUS1_ParaMEM_PT); + } + + else if((modbus1Buf[0] == 0xA7) && (modbus1Buf[1] == 0x55)) + { + UART3_EraseIAP(); //485升级操作 + } + + else + { + MODBUS1_Init(); //没加这个时，换地址通讯连接不上，待监控时间到重新初始化之后才恢复连接 + } + } + } +} + +/**************************************** +**** MODBUS1 F03 读报文 ***** +** M: 01 03 00 ADR 00 LEN/2 CRCL H ** +** S: 01 03 LEN DATA0-N CRCL H ** +*****************************************/ +void MODBUS1_F03_Rx(uint8_t *mem) +{ + uint8_t i; + BYTE2 crc16; + uint16_t adr; + uint8_t len; + uint8_t *data; + + //CRC判断 + crc16 = CRC16_Cal(modbus1Buf, 6); + if( (modbus1Buf[7] == crc16.b8[1]) && (modbus1Buf[6] == crc16.b8[0]) ) + { + adr = (uint16_t)modbus1Buf[3] <<1; + len = modbus1Buf[5] <<1; + + if(mem == MODBUS1_VoltronicMEM_PT) //日月元的数据长度占两字节，且是直接搬过来 + { + modbus1Buf[2] = modbus1Buf[4]; + modbus1Buf[3] = modbus1Buf[5]; + + //高字节在前 + data = mem+adr; + for(i=0;i> 12) & 0x0f); + modbus1Buf[INFOlen+14] = toASCII((CHKSUM >> 8 ) & 0x0f); + modbus1Buf[INFOlen+15] = toASCII((CHKSUM >> 4 ) & 0x0f); + modbus1Buf[INFOlen+16] = toASCII((CHKSUM >> 0 ) & 0x0f); + + //EOI + modbus1Buf[INFOlen+17] = 0x0D; + + ydn23RxFlg = 1; + MODBUS1_UART_IT_RX_DISABLE; + } + else if((modbus1Buf[7] == 0x36) && (modbus1Buf[8] == 0x30)) //60H 电池组系统基本信息 + { + //RTN + modbus1Buf[7] = 0x30; + modbus1Buf[8] = 0x30; + + //LENGTH 36 30 38 32 + INFOlen = 130; + modbus1Buf[9] = 0x36; + modbus1Buf[10] = 0x30; + modbus1Buf[11] = 0x38; + modbus1Buf[12] = 0x32; + + //INFO + //主机设备名称 Force_L + modbus1Buf[13] = 0x34; + modbus1Buf[14] = 0x36; + modbus1Buf[15] = 0x36; + modbus1Buf[16] = 0x46; + modbus1Buf[17] = 0x37; + modbus1Buf[18] = 0x32; + modbus1Buf[19] = 0x36; + modbus1Buf[20] = 0x33; + modbus1Buf[21] = 0x36; + modbus1Buf[22] = 0x35; + modbus1Buf[23] = 0x35; + modbus1Buf[24] = 0x46; + modbus1Buf[25] = 0x34; + modbus1Buf[26] = 0x43; + modbus1Buf[27] = 0x30; + modbus1Buf[28] = 0x30; + modbus1Buf[29] = 0x30; + modbus1Buf[30] = 0x30; + modbus1Buf[31] = 0x30; + modbus1Buf[32] = 0x30; + //主机厂商名称 Pylon + modbus1Buf[33] = 0x35; + modbus1Buf[34] = 0x30; + modbus1Buf[35] = 0x37; + modbus1Buf[36] = 0x39; + modbus1Buf[37] = 0x36; + modbus1Buf[38] = 0x43; + modbus1Buf[39] = 0x36; + modbus1Buf[40] = 0x46; + modbus1Buf[41] = 0x36; + modbus1Buf[42] = 0x45; + modbus1Buf[43] = 0x30; + modbus1Buf[44] = 0x30; + modbus1Buf[45] = 0x30; + modbus1Buf[46] = 0x30; + modbus1Buf[47] = 0x30; + modbus1Buf[48] = 0x30; + modbus1Buf[49] = 0x30; + modbus1Buf[50] = 0x30; + modbus1Buf[51] = 0x30; + modbus1Buf[52] = 0x30; + modbus1Buf[53] = 0x30; + modbus1Buf[54] = 0x30; + modbus1Buf[55] = 0x30; + modbus1Buf[56] = 0x30; + modbus1Buf[57] = 0x30; + modbus1Buf[58] = 0x30; + modbus1Buf[59] = 0x30; + modbus1Buf[60] = 0x30; + modbus1Buf[61] = 0x30; + modbus1Buf[62] = 0x30; + modbus1Buf[63] = 0x30; + modbus1Buf[64] = 0x30; + modbus1Buf[65] = 0x30; + modbus1Buf[66] = 0x30; + modbus1Buf[67] = 0x30; + modbus1Buf[68] = 0x30; + modbus1Buf[69] = 0x30; + modbus1Buf[70] = 0x30; + modbus1Buf[71] = 0x30; + modbus1Buf[72] = 0x30; + //主机软件版本 0x0009 + modbus1Buf[73] = 0x30; + modbus1Buf[74] = 0x30; + modbus1Buf[75] = 0x30; + modbus1Buf[76] = 0x39; + //电池数量 0x02 + modbus1Buf[77] = 0x30; + modbus1Buf[78] = 0x32; + //电池 1 的条形码 + modbus1Buf[79] = 0x33; + modbus1Buf[80] = 0x30; + modbus1Buf[81] = 0x33; + modbus1Buf[82] = 0x31; + modbus1Buf[83] = 0x33; + modbus1Buf[84] = 0x32; + modbus1Buf[85] = 0x33; + modbus1Buf[86] = 0x33; + modbus1Buf[87] = 0x33; + modbus1Buf[88] = 0x34; + modbus1Buf[89] = 0x33; + modbus1Buf[90] = 0x35; + modbus1Buf[91] = 0x33; + modbus1Buf[92] = 0x36; + modbus1Buf[93] = 0x33; + modbus1Buf[94] = 0x37; + modbus1Buf[95] = 0x33; + modbus1Buf[96] = 0x38; + modbus1Buf[97] = 0x33; + modbus1Buf[98] = 0x39; + modbus1Buf[99] = 0x36; + modbus1Buf[100] = 0x31; + modbus1Buf[101] = 0x36; + modbus1Buf[102] = 0x32; + modbus1Buf[103] = 0x36; + modbus1Buf[104] = 0x33; + modbus1Buf[105] = 0x36; + modbus1Buf[106] = 0x34; + modbus1Buf[107] = 0x36; + modbus1Buf[108] = 0x35; + modbus1Buf[109] = 0x36; + modbus1Buf[110] = 0x36; + //电池 2 的条形码 + modbus1Buf[111] = 0x33; + modbus1Buf[112] = 0x31; + modbus1Buf[113] = 0x33; + modbus1Buf[114] = 0x31; + modbus1Buf[115] = 0x33; + modbus1Buf[116] = 0x32; + modbus1Buf[117] = 0x33; + modbus1Buf[118] = 0x33; + modbus1Buf[119] = 0x33; + modbus1Buf[120] = 0x34; + modbus1Buf[121] = 0x33; + modbus1Buf[122] = 0x35; + modbus1Buf[123] = 0x33; + modbus1Buf[124] = 0x36; + modbus1Buf[125] = 0x33; + modbus1Buf[126] = 0x37; + modbus1Buf[127] = 0x33; + modbus1Buf[128] = 0x38; + modbus1Buf[129] = 0x33; + modbus1Buf[130] = 0x39; + modbus1Buf[131] = 0x36; + modbus1Buf[132] = 0x31; + modbus1Buf[133] = 0x36; + modbus1Buf[134] = 0x32; + modbus1Buf[135] = 0x36; + modbus1Buf[136] = 0x33; + modbus1Buf[137] = 0x36; + modbus1Buf[138] = 0x34; + modbus1Buf[139] = 0x36; + modbus1Buf[140] = 0x35; + modbus1Buf[141] = 0x36; + modbus1Buf[142] = 0x36; + + //CHKSUM + //除SOI、EOI和CHKSUM外，其他字符按ASCII码值累加求和，模65536余数，取反加1 + CHKSUM = 0; + for(i=1;i<=INFOlen+12;i++) + { + CHKSUM+=modbus1Buf[i]; + } + CHKSUM = CHKSUM%65536; + CHKSUM = -CHKSUM; + //以16进制-ASCII码传输 + modbus1Buf[INFOlen+13] = toASCII((CHKSUM >> 12) & 0x0f); + modbus1Buf[INFOlen+14] = toASCII((CHKSUM >> 8 ) & 0x0f); + modbus1Buf[INFOlen+15] = toASCII((CHKSUM >> 4 ) & 0x0f); + modbus1Buf[INFOlen+16] = toASCII((CHKSUM >> 0 ) & 0x0f); + + //EOI + modbus1Buf[INFOlen+17] = 0x0D; + + ydn23RxFlg = 1; + MODBUS1_UART_IT_RX_DISABLE; + } + else if((modbus1Buf[7] == 0x36) && (modbus1Buf[8] == 0x31)) //61H 系统模拟量 + { + uint16_t tempVol; + int16_t tempCur; + + + //RTN + modbus1Buf[7] = 0x30; + modbus1Buf[8] = 0x30; + + //LENGTH 38 30 36 32 + INFOlen = 98; + modbus1Buf[9] = 0x38; + modbus1Buf[10] = 0x30; + modbus1Buf[11] = 0x36; + modbus1Buf[12] = 0x32; + + //INFO + //平均电压 单位0.001V + tempVol = bmsMem.packVoltage; + modbus1Buf[13] = toASCII((tempVol >> 12) & 0x0f); + modbus1Buf[14] = toASCII((tempVol >> 8 ) & 0x0f); + modbus1Buf[15] = toASCII((tempVol >> 4 ) & 0x0f); + modbus1Buf[16] = toASCII((tempVol >> 0 ) & 0x0f); + //总电流 单位0.01A + tempCur = canMem[0].cur; + modbus1Buf[17] = toASCII((tempCur >> 12) & 0x0f); + modbus1Buf[18] = toASCII((tempCur >> 8 ) & 0x0f); + modbus1Buf[19] = toASCII((tempCur >> 4 ) & 0x0f); + modbus1Buf[20] = toASCII((tempCur >> 0 ) & 0x0f); + //平均SOC 单位1% + modbus1Buf[21] = toASCII((canMem[0].soc >> 4) & 0x0f); + modbus1Buf[22] = toASCII((canMem[0].soc >> 0 ) & 0x0f); + //平均循环次数 0xFFFF + modbus1Buf[23] = 0x46; + modbus1Buf[24] = 0x46; + modbus1Buf[25] = 0x46; + modbus1Buf[26] = 0x46; + //最大循环次数 0xFFFF + modbus1Buf[27] = 0x46; + modbus1Buf[28] = 0x46; + modbus1Buf[29] = 0x46; + modbus1Buf[30] = 0x46; + //平均SOH 固定99 单位1% + modbus1Buf[31] = 0x36; + modbus1Buf[32] = 0x33; + //最小SOH 固定99 单位1% + modbus1Buf[33] = 0x36; + modbus1Buf[34] = 0x33; + //单芯最高电压 单位1mV + modbus1Buf[35] = toASCII((canMem[0].cellVoltageMax >> 12) & 0x0f); + modbus1Buf[36] = toASCII((canMem[0].cellVoltageMax >> 8 ) & 0x0f); + modbus1Buf[37] = toASCII((canMem[0].cellVoltageMax >> 4 ) & 0x0f); + modbus1Buf[38] = toASCII((canMem[0].cellVoltageMax >> 0 ) & 0x0f); + //单芯最高电压的编号最小的模块 + modbus1Buf[39] = toASCII((canMem[0].VolMaxIndex >> 12) & 0x0f); + modbus1Buf[40] = toASCII((canMem[0].VolMaxIndex >> 8 ) & 0x0f); + modbus1Buf[41] = toASCII((canMem[0].VolMaxIndex >> 4 ) & 0x0f); + modbus1Buf[42] = toASCII((canMem[0].VolMaxIndex >> 0 ) & 0x0f); + //单芯最低电压 单位1mV + modbus1Buf[43] = toASCII((canMem[0].cellVoltageMin >> 12) & 0x0f); + modbus1Buf[44] = toASCII((canMem[0].cellVoltageMin >> 8 ) & 0x0f); + modbus1Buf[45] = toASCII((canMem[0].cellVoltageMin >> 4 ) & 0x0f); + modbus1Buf[46] = toASCII((canMem[0].cellVoltageMin >> 0 ) & 0x0f); + //单芯最低电压的编号最小的模块 + modbus1Buf[47] = toASCII((canMem[0].VolMinIndex >> 12) & 0x0f); + modbus1Buf[48] = toASCII((canMem[0].VolMinIndex >> 8 ) & 0x0f); + modbus1Buf[49] = toASCII((canMem[0].VolMinIndex >> 4 ) & 0x0f); + modbus1Buf[50] = toASCII((canMem[0].VolMinIndex >> 0 ) & 0x0f); + //单芯平均温度 单位0.1K + modbus1Buf[51] = toASCII((canMem[0].temp >> 12) & 0x0f); + modbus1Buf[52] = toASCII((canMem[0].temp >> 8 ) & 0x0f); + modbus1Buf[53] = toASCII((canMem[0].temp >> 4 ) & 0x0f); + modbus1Buf[54] = toASCII((canMem[0].temp >> 0 ) & 0x0f); + //单芯最高温度 单位0.1K + modbus1Buf[55] = toASCII((canMem[0].TempMax >> 12) & 0x0f); + modbus1Buf[56] = toASCII((canMem[0].TempMax >> 8 ) & 0x0f); + modbus1Buf[57] = toASCII((canMem[0].TempMax >> 4 ) & 0x0f); + modbus1Buf[58] = toASCII((canMem[0].TempMax >> 0 ) & 0x0f); + //单芯最高温度的编号最小的模块 + modbus1Buf[59] = toASCII((canMem[0].TempMaxIndex >> 12) & 0x0f); + modbus1Buf[60] = toASCII((canMem[0].TempMaxIndex >> 8 ) & 0x0f); + modbus1Buf[61] = toASCII((canMem[0].TempMaxIndex >> 4 ) & 0x0f); + modbus1Buf[62] = toASCII((canMem[0].TempMaxIndex >> 0 ) & 0x0f); + //单芯最低温度 单位0.1K + modbus1Buf[63] = toASCII((canMem[0].TempMin >> 12) & 0x0f); + modbus1Buf[64] = toASCII((canMem[0].TempMin >> 8 ) & 0x0f); + modbus1Buf[65] = toASCII((canMem[0].TempMin >> 4 ) & 0x0f); + modbus1Buf[66] = toASCII((canMem[0].TempMin >> 0 ) & 0x0f); + //单芯最低温度的编号最小的模块 + modbus1Buf[67] = toASCII((canMem[0].TempMinIndex >> 12) & 0x0f); + modbus1Buf[68] = toASCII((canMem[0].TempMinIndex >> 8 ) & 0x0f); + modbus1Buf[69] = toASCII((canMem[0].TempMinIndex >> 4 ) & 0x0f); + modbus1Buf[70] = toASCII((canMem[0].TempMinIndex >> 0 ) & 0x0f); + //MOSFET平均温度 0xFFFF + modbus1Buf[71] = 0x46; + modbus1Buf[72] = 0x46; + modbus1Buf[73] = 0x46; + modbus1Buf[74] = 0x46; + //MOSFET最高温度 0xFFFF + modbus1Buf[75] = 0x46; + modbus1Buf[76] = 0x46; + modbus1Buf[77] = 0x46; + modbus1Buf[78] = 0x46; + //MOSFET最高温度的编号最小的模块 0xFFFF + modbus1Buf[79] = 0x46; + modbus1Buf[80] = 0x46; + modbus1Buf[81] = 0x46; + modbus1Buf[82] = 0x46; + //MOSFET最低温度 0xFFFF + modbus1Buf[83] = 0x46; + modbus1Buf[84] = 0x46; + modbus1Buf[85] = 0x46; + modbus1Buf[86] = 0x46; + //MOSFET最低温度的编号最小的模块 0xFFFF + modbus1Buf[87] = 0x46; + modbus1Buf[88] = 0x46; + modbus1Buf[89] = 0x46; + modbus1Buf[90] = 0x46; + //BMS平均温度 + modbus1Buf[91] = toASCII((canMem[0].temp >> 12) & 0x0f); + modbus1Buf[92] = toASCII((canMem[0].temp >> 8) & 0x0f); + modbus1Buf[93] = toASCII((canMem[0].temp >> 4) & 0x0f); + modbus1Buf[94] = toASCII((canMem[0].temp >> 0) & 0x0f); + //BMS最高温度 + modbus1Buf[95] = toASCII((canMem[0].TempMax >> 12) & 0x0f); + modbus1Buf[96] = toASCII((canMem[0].TempMax >> 8) & 0x0f); + modbus1Buf[97] = toASCII((canMem[0].TempMax >> 4) & 0x0f); + modbus1Buf[98] = toASCII((canMem[0].TempMax >> 0) & 0x0f); + //BMS最高温度的编号最小的模块 0xFFFF + modbus1Buf[99] = toASCII((canMem[0].TempMaxIndex >> 12) & 0x0f); + modbus1Buf[100] = toASCII((canMem[0].TempMaxIndex >> 8) & 0x0f); + modbus1Buf[101] = toASCII((canMem[0].TempMaxIndex >> 4) & 0x0f); + modbus1Buf[102] = toASCII((canMem[0].TempMaxIndex >> 0) & 0x0f); + //BMS最低温度 + modbus1Buf[103] = toASCII((canMem[0].TempMin >> 12) & 0x0f); + modbus1Buf[104] = toASCII((canMem[0].TempMin >> 8) & 0x0f); + modbus1Buf[105] = toASCII((canMem[0].TempMin >> 4) & 0x0f); + modbus1Buf[106] = toASCII((canMem[0].TempMin >> 0) & 0x0f); + //BMS最低温度的编号最小的模块 0xFFFF + modbus1Buf[107] = toASCII((canMem[0].TempMinIndex >> 12) & 0x0f); + modbus1Buf[108] = toASCII((canMem[0].TempMinIndex >> 8) & 0x0f); + modbus1Buf[109] = toASCII((canMem[0].TempMinIndex >> 4) & 0x0f); + modbus1Buf[110] = toASCII((canMem[0].TempMinIndex >> 0) & 0x0f); + + //CHKSUM + //除SOI、EOI和CHKSUM外，其他字符按ASCII码值累加求和，模65536余数，取反加1 + CHKSUM = 0; + for(i=1;i<=INFOlen+12;i++) + { + CHKSUM+=modbus1Buf[i]; + } + CHKSUM = CHKSUM%65536; + CHKSUM = -CHKSUM; + //以16进制-ASCII码传输 + modbus1Buf[INFOlen+13] = toASCII((CHKSUM >> 12) & 0x0f); + modbus1Buf[INFOlen+14] = toASCII((CHKSUM >> 8 ) & 0x0f); + modbus1Buf[INFOlen+15] = toASCII((CHKSUM >> 4 ) & 0x0f); + modbus1Buf[INFOlen+16] = toASCII((CHKSUM >> 0 ) & 0x0f); + + //EOI + modbus1Buf[INFOlen+17] = 0x0D; + + ydn23RxFlg = 1; + MODBUS1_UART_IT_RX_DISABLE; + } + else if((modbus1Buf[7] == 0x36) && (modbus1Buf[8] == 0x32)) //62H 系统告警保护 + { + //保护 +// //过压保护 +// //cell_ov+pack_ov+pf +// if((canMem[0].status_byte1 & 0x0141) != 0) +// { +// if(canMem[0].soc < 99) +// { +// protectByte1 |= 0x20; +// } +// else +// { +// protectByte1 &= 0xDF; +// } +// } +// else +// { +// protectByte1 &= 0xDF; +// } + + //欠压保护 + //cell_uv+pack_uv+l0v + if(((canMem[0].status_byte1 & 0x0202) != 0) || ((canMem[0].status_byte3 & 0x0008) != 0)) + { + protectByte1 |= 0x10; + } + else + { + protectByte1 &= 0xEF; + } + + //过温保护 + //over temp at charging or discharging + if(((canMem[0].status_byte2 & 0x000A) != 0) || ((canMem[0].status_byte4 & 0x0303) != 0)) + { + protectByte1 |= 0x08; + } + else + { + protectByte1 &= 0xF7; + } + + //低温保护 + //under temp at charging or discharging + if(((canMem[0].status_byte2 & 0x0005) != 0) || ((canMem[0].status_byte4 & 0x0C0C) != 0)) + { + protectByte1 |= 0x04; + } + else + { + protectByte1 &= 0xFB; + } + + //BIT1 MOS高温 (未改) + if((canMem[0].status_byte2 & 0x0A) !=0) + { + protectByte1 |= 0x02; + } + else + { + protectByte1 &= 0xFD; + } + + //充电过流保护 + //charge over current + if( ((canMem[0].status_byte1 & 0x0010) != 0) || ((canMem[0].status_byte4 & 0x0010) != 0)) + { + protectByte2 |= 0x40; + } + else + { + protectByte2 &= 0xBF; + } + + //放电过流保护 + //discharge over current，SC, OCD1, OCD2 + if( ((canMem[0].status_byte1 & 0x042c) != 0) || ((canMem[0].status_byte2 & 0x0010) != 0) || ((canMem[0].status_byte4 & 0x0020) != 0)) + { + protectByte2 |= 0x20; + } + else + { + protectByte2 &= 0xDF; + } + + + //告警 +// //过压告警 +// if((canMem[0].status_byte3 & 0x0500) != 0) +// { +// if(canMem[0].soc < 99) +// { +// alarmByte1 |= 0x20; +// } +// else +// { +// alarmByte1 &= 0xDF; +// } +// } +// else +// { +// alarmByte1 &= 0xDF; +// } + + //欠压告警 + if((canMem[0].status_byte3 & 0x0A00) != 0) + { + alarmByte1 |= 0x10; + } + else + { + alarmByte1 &= 0xEF; + } + + //过温告警 + if(((canMem[0].status_byte2 & 0x3300) != 0) || ((canMem[0].status_byte4 & 0x3000) != 0)) + { + alarmByte1 |= 0x08; + } + else + { + alarmByte1 &= 0xF7; + } + + //低温告警 + if(((canMem[0].status_byte2 & 0xCC00) != 0) || ((canMem[0].status_byte4 & 0xC000) != 0)) + { + alarmByte1 |= 0x04; + } + else + { + alarmByte1 &= 0xFB; + } + + //BIT1 MOS高温告警 + if((canMem[0].status_byte2 & 0x0A) !=0) + { + alarmByte1 |= 0x02; + } + else + { + alarmByte1 &= 0xFD; + } + + //充电过流告警 + if((canMem[0].status_byte3 & 0x1000) != 0) + { + alarmByte2 |= 0x40; + } + else + { + alarmByte2 &= 0xBF; + } + + //放电过流告警 + if((canMem[0].status_byte3 & 0x2000) != 0) + { + alarmByte2 |= 0x20; + } + else + { + alarmByte2 &= 0xDF; + } + + //RTN + modbus1Buf[7] = 0x30; + modbus1Buf[8] = 0x30; + + //LENGTH 38 30 30 38 + INFOlen = 8; + modbus1Buf[9] = 0x38; + modbus1Buf[10] = 0x30; + modbus1Buf[11] = 0x30; + modbus1Buf[12] = 0x38; + + //INFO + //告警状态1 + modbus1Buf[13] = toASCII((alarmByte1 >> 4 ) & 0x0f); + modbus1Buf[14] = toASCII((alarmByte1 >> 0 ) & 0x0f); + //告警状态2 + modbus1Buf[15] = toASCII((alarmByte2 >> 4 ) & 0x0f); + modbus1Buf[16] = toASCII((alarmByte2 >> 0 ) & 0x0f); + //保护状态1 + modbus1Buf[17] = toASCII((protectByte1 >> 4 ) & 0x0f); + modbus1Buf[18] = toASCII((protectByte1 >> 0 ) & 0x0f); + //保护状态2 + modbus1Buf[19] = toASCII((protectByte2 >> 4 ) & 0x0f); + modbus1Buf[20] = toASCII((protectByte2 >> 0 ) & 0x0f); + + //CHKSUM + //除SOI、EOI和CHKSUM外，其他字符按ASCII码值累加求和，模65536余数，取反加1 + CHKSUM = 0; + for(i=1;i<=INFOlen+12;i++) + { + CHKSUM+=modbus1Buf[i]; + } + CHKSUM = CHKSUM%65536; + CHKSUM = -CHKSUM; + //以16进制-ASCII码传输 + modbus1Buf[INFOlen+13] = toASCII((CHKSUM >> 12) & 0x0f); + modbus1Buf[INFOlen+14] = toASCII((CHKSUM >> 8 ) & 0x0f); + modbus1Buf[INFOlen+15] = toASCII((CHKSUM >> 4 ) & 0x0f); + modbus1Buf[INFOlen+16] = toASCII((CHKSUM >> 0 ) & 0x0f); + + //EOI + modbus1Buf[INFOlen+17] = 0x0D; + + ydn23RxFlg = 1; + MODBUS1_UART_IT_RX_DISABLE; + } + else if((modbus1Buf[7] == 0x36) && (modbus1Buf[8] == 0x33)) //63H 系统交互信息 + { + uint16_t chgVolLimit; // 充电电压限制 + uint16_t dsgVolLimit; // 放电电压限制 + uint16_t chgCurLimit; // 充电电流限制 + uint16_t dsgCurLimit; // 放电电流限制 + //充放电电流限制需要有符号区别吗？ + + + //RTN + modbus1Buf[7] = 0x30; + modbus1Buf[8] = 0x30; + + //LENGTH 44 30 31 32 + INFOlen = 18; + modbus1Buf[9] = 0x44; + modbus1Buf[10] = 0x30; + modbus1Buf[11] = 0x31; + modbus1Buf[12] = 0x32; + + //INFO + //充电电压建议上限 单位0.001V + chgVolLimit = bmsMem.inverter_chgVolLimit*100; //充电电压限制，上位机配置，默认值57.6V + modbus1Buf[13] = toASCII((chgVolLimit >> 12) & 0x0f); + modbus1Buf[14] = toASCII((chgVolLimit >> 8 ) & 0x0f); + modbus1Buf[15] = toASCII((chgVolLimit >> 4 ) & 0x0f); + modbus1Buf[16] = toASCII((chgVolLimit >> 0 ) & 0x0f); + //放电电压建议下限 单位0.001V + dsgVolLimit = bmsMem.inverter_dsgVolLimit*100; //放电电压限制，上位机配置，默认值41.6V + modbus1Buf[17] = toASCII((dsgVolLimit >> 12) & 0x0f); + modbus1Buf[18] = toASCII((dsgVolLimit >> 8 ) & 0x0f); + modbus1Buf[19] = toASCII((dsgVolLimit >> 4 ) & 0x0f); + modbus1Buf[20] = toASCII((dsgVolLimit >> 0 ) & 0x0f); + //最大充电电流 单位0.1A + if(chg_forbidFlg == 1) + { + chgCurLimit = 0; //Pylon_电总禁充 + } + else if(chg_curlimitFlg == 1) + { + chgCurLimit = Inv_curlimit * (OnlineNum-chg_cur0Num); //限流40A*未保护个数 + } + else + { + chgCurLimit = bmsMem.inverter_chgCurLimit * (OnlineNum-chg_curLimitNum); //充电电流限制，上位机配置，默认值100A + } + modbus1Buf[21] = toASCII((chgCurLimit >> 12) & 0x0f); + modbus1Buf[22] = toASCII((chgCurLimit >> 8 ) & 0x0f); + modbus1Buf[23] = toASCII((chgCurLimit >> 4 ) & 0x0f); + modbus1Buf[24] = toASCII((chgCurLimit >> 0 ) & 0x0f); + //最大放电电流 单位0.1A + if(dsg_forbidFlg == 1) + { + dsgCurLimit = bmsMem.inverter_dsgCurLimit * (OnlineNum-dsg_curLimitNum); //放电电流限制，上位机配置，默认值100A + } + else + { + dsgCurLimit = 0; //Pylon_电总强充 + } + modbus1Buf[25] = toASCII((dsgCurLimit >> 12) & 0x0f); + modbus1Buf[26] = toASCII((dsgCurLimit >> 8 ) & 0x0f); + modbus1Buf[27] = toASCII((dsgCurLimit >> 4 ) & 0x0f); + modbus1Buf[28] = toASCII((dsgCurLimit >> 0 ) & 0x0f); + //充放电状态 + RequestFlag = 0xC0; //充电允许0x80，放电允许0x40，不强充~0x20 + if(chg_forbidFlg == 1)//Pylon_电总 + { + RequestFlag &= 0x7F; //禁充 + } + if(dsg_forbidFlg == 1)//Pylon_电总 + { + RequestFlag &= 0xBF; //禁放 + } + if(chg_forceFlg == 1)//Pylon_电总 + { + RequestFlag |= 0x20; //强充 + } + if(RequestFlag >= 0xA0) //转换为ASCII字符 + { + modbus1Buf[29] = (RequestFlag>>4) + (uint8_t)('A' - 10); + modbus1Buf[30] = 0x30; + } + else + { + modbus1Buf[29] = (RequestFlag>>4) + (uint8_t)'0'; + modbus1Buf[30] = 0x30; + } + + //CHKSUM + //除SOI、EOI和CHKSUM外，其他字符按ASCII码值累加求和，模65536余数，取反加1 + CHKSUM = 0; + for(i=1;i<=INFOlen+12;i++) + { + CHKSUM+=modbus1Buf[i]; + } + CHKSUM = CHKSUM%65536; + CHKSUM = -CHKSUM; + //以16进制-ASCII码传输 + modbus1Buf[INFOlen+13] = toASCII((CHKSUM >> 12) & 0x0f); + modbus1Buf[INFOlen+14] = toASCII((CHKSUM >> 8 ) & 0x0f); + modbus1Buf[INFOlen+15] = toASCII((CHKSUM >> 4 ) & 0x0f); + modbus1Buf[INFOlen+16] = toASCII((CHKSUM >> 0 ) & 0x0f); + + //EOI + modbus1Buf[INFOlen+17] = 0x0D; + + ydn23RxFlg = 1; + MODBUS1_UART_IT_RX_DISABLE; + } + + else + { + MODBUS1_Init(); //没加这个时，换地址通讯连接不上，待监控时间到重新初始化之后才恢复连接 + } + } + else + { + MODBUS1_Init(); //没加这个时，换地址通讯连接不上，待监控时间到重新初始化之后才恢复连接 + } + } + else + { + MODBUS1_Init(); //没加这个时，换地址通讯连接不上，待监控时间到重新初始化之后才恢复连接 + } +} + diff --git a/MOUDLE/SDWA.c b/MOUDLE/SDWA.c new file mode 100644 index 0000000..8aceacd --- /dev/null +++ b/MOUDLE/SDWA.c @@ -0,0 +1,4109 @@ +/** + ****************************************************************************** + * @file tim.c + * @author Jerry + * @version V2.1 + * @date 19-April-2022 + * @brief tim program body. + ****************************************************************************** + * @attention + * + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" +#include "global.h" +#include "rtc.h" +#include "soe.h" +#include "AFE_SH367309.h" +#include "string.h" + +#define VAR_CHARGE 0 +#define VAR_DISCHARGE 1 +#define VAR_FAULT 2 +#define VAR_ON 3 +#define VAR_OFF 4 + +//AFE过流保护对应采集电压值， +//单位mV，要转换为电流值 +//取x8，用MCU过流保护电流和其比较，选择稍大一点的值 +//const uint16_t OCD1V[16]= +//{ +// 20, 30, 40, 50, +// 60, 70, 80, 90, +// 100,110,120,130, +// 140,160,180,200 +//}; +//const uint16_t OCD2V[16]= +//{ +// 30, 40, 50, 60, +// 70, 80, 90,100, +// 120,140,160,180, +// 200,300,400,500 +//}; +//const uint16_t OCCV[16]= +//{ +// 20, 30, 40, 50, +// 60, 70, 80, 90, +// 100,110,120,130, +// 140,160,180,200 +//}; + +uint8_t protocol; //逆变器通信协议 + +//uint8_t language; //屏幕语言 + +uint8_t sdwaBuf[20]; +uint8_t sdwaBufIndex; +uint8_t sdwaMoniCount; +uint8_t sdwaRecvFlag; + +uint8_t read_index; +uint8_t recordBuf[64]; +char sendRecord[64]; + +uint8_t initFlag; //初始化配置参数 +uint8_t clearFlag; //清除报警记录 +uint8_t EE_clearFlag; //特殊按钮，点按清空EEPROM + +uint8_t sdwa_sleep_flag; //用于排除平时接收亮度的报文 + +uint8_t scr_WrZero_Flg; //屏幕写零点校准 +uint8_t scr_WrGain_Flg; //屏幕写增益校准 + +uint8_t scr_RdData_Index;//屏幕显示数据的地址，默认是自身地址，且只有addr=1可以变化该地址 +uint8_t scr_RdRecord_Flg;//屏幕只可以查看自身记录；当记录更新/清空/收到清空指令/进记录页面/上下翻动时，才会读EEPROM更新一次屏幕记录内容 + +uint8_t bAlarmFlagOld_slave; //主机屏幕显示从机报警的跳转 + +uint8_t sdwa_ExitTotal_Flg; //主机地址变化为从机，需要变化后退出总数据页 + + +//用于发送数据/显示图标 +//A5 5A 05 82 01 87 00 00 +void SDWA_Send_VAR(uint16_t addr, uint16_t data) +{ + USART_SendData(USART2, 0xA5); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + USART_SendData(USART2, 0x5A); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + USART_SendData(USART2, 0x05); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + USART_SendData(USART2, 0x82); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + USART_SendData(USART2, (addr&0xff00)>>8); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + USART_SendData(USART2, (addr&0x00ff)); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + USART_SendData(USART2, (data>>8) & 0xff); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + USART_SendData(USART2, (data & 0xff) ); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + __nop(); + __nop(); + __nop(); + __nop(); + __nop(); + __nop(); + __nop(); + __nop(); + __nop(); + __nop(); +} + +//页面跳转函数 +void SDWA_JumpToNumber(uint16_t number) +{ + USART_SendData(USART2, 0xA5); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + USART_SendData(USART2, 0x5A); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + USART_SendData(USART2, 0x04); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + USART_SendData(USART2, 0x80); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + USART_SendData(USART2, 0x03); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + USART_SendData(USART2, 0x00); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + USART_SendData(USART2, number); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + __nop(); + __nop(); + __nop(); + __nop(); + __nop(); + __nop(); + __nop(); + __nop(); + __nop(); + __nop(); +} + +//开机和息屏跳转时，根据语言跳转首页 +void SDWA_JumpToHome(void) +{ +// if(language == 0) +// { + SDWA_JumpToNumber(1); +// } +// else if(language == 1) +// { +// SDWA_JumpToNumber(29); +// } +} + +//改变屏幕背光亮度 +uint8_t LightChange_flg; +void SDWA_ChangeLight(uint8_t light) +{ + if(LightChange_flg == 0) + { + LightChange_flg = 1; + + USART_SendData(USART2, 0xA5); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + USART_SendData(USART2, 0x5A); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + USART_SendData(USART2, 0x03); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + USART_SendData(USART2, 0x80); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + USART_SendData(USART2, 0x01); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + USART_SendData(USART2, light); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + __nop(); + __nop(); + __nop(); + __nop(); + __nop(); + __nop(); + __nop(); + __nop(); + __nop(); + __nop(); + } +} + +//当关机时，若收到摁亮屏幕报文，控制灭 +void SDWA_KeepLight0(void) +{ + if(sdwaRecvFlag == 1) + { + sdwaRecvFlag = 0; + sdwaBufIndex = 0; + + if((sdwaBuf[0] == 0xA5) && (sdwaBuf[1] == 0x5A)) + { + if((sdwaBuf[2]==0x04) && (sdwaBuf[3]==0x81) && ( (sdwaBuf[6]>=0x20) && (sdwaBuf[6]<=0x40) )) + { + LightChange_flg = 0; + SDWA_ChangeLight(0); + } + } + } +} + + +/**4G状态的显示**/ +uint8_t LTEStatus_flg; //要传状态的标志 +char LTEStatus_str[41]; //4G状态文本 +void SDWA_Send_LTE(uint16_t addr) +{ + uint8_t i; + uint8_t len = strlen(LTEStatus_str); //最大长度20，对应ASCII码40个 + + + USART_SendData(USART2, 0xA5); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x5A); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, len+3); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x82); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, (addr&0xff00)>>8); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, (addr&0x00ff)); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + for(i=0;i>8); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, (addr&0x00ff)); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + if(data[0] < 10) + { + USART_SendData(USART2, 0x30+data[0]); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + } + else + { + USART_SendData(USART2, 0x30+data[0]/10); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x30+data[0]%10); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + } + + USART_SendData(USART2, '.'); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + if(data[1] < 10) + { + USART_SendData(USART2, 0x30+data[1]); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + } + else + { + USART_SendData(USART2, 0x30+data[1]/10); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x30+data[1]%10); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + } + + USART_SendData(USART2, '.'); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + if(data[2] < 10) + { + USART_SendData(USART2, 0x30+data[2]); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + } + else if(data[2] < 0xA0) //软件版本不是特殊版 + { + USART_SendData(USART2, 0x30+data[2]/10); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x30+data[2]%10); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + } + else + { + USART_SendData(USART2, 'A'+data[2]/16-0x0A); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x30+data[2]%16); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + } + + USART_SendData(USART2, '.'); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + if(data[3] < 10) + { + USART_SendData(USART2, 0x30+data[3]); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + } + else + { + USART_SendData(USART2, 0x30+data[3]/10); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x30+data[3]%10); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + } + + USART_SendData(USART2, 0xff ); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0xff ); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + __nop(); + __nop(); + __nop(); + __nop(); + __nop(); + + __nop(); + __nop(); + __nop(); + __nop(); + __nop(); + +} + +//显示硬件版本号 0x02D6 +void SDWA_Send_VER_HARD(uint16_t addr, uint8_t *data) +{ + USART_SendData(USART2, 0xA5); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x5A); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x0A); //5+5 + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x82); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, (addr&0xff00)>>8); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, (addr&0x00ff)); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x30+data[0]); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, '.'); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x30+data[1]); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, '.'); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + if(data[2] < 0x41) //硬件版本没有字母 + { + USART_SendData(USART2, 0x30+data[2]); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + } + else + { + USART_SendData(USART2, data[2]); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + } + + USART_SendData(USART2, 0xff ); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0xff ); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + __nop(); + __nop(); + __nop(); + __nop(); + __nop(); + + __nop(); + __nop(); + __nop(); + __nop(); + __nop(); + +} + +//显示屏幕号 0x02E9 +void SDWA_Send_VER_SCRN(uint16_t addr, uint8_t data) +{ + uint16_t list1,list2; + + //最高两位表示型号，00对应028，01对应035，10对应042，11对应070 + //剩下6位表示序号Index，范围0~63，显示为1~64 (028的要排除0/1/2/3为特殊项，从0x04开始) + if((data>>6 == 0x00) && (data >= 0x04)) + { + list1 = 28; + list2 = (data & 0x3f) +1-4; + } + else if(data>>6 == 0x01) + { + list1 = 35; + list2 = (data & 0x3f) +1; + } + else if(data>>6 == 0x02) + { + list1 = 43; + list2 = (data & 0x3f) +1; + } + else if(data>>6 == 0x03) + { + list1 = 70; + list2 = (data & 0x3f) +1; + } + else + { + return; //型号以外的(比如=0)，不显示 + } + + USART_SendData(USART2, 0xA5); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x5A); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x0A); //5+5 + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x82); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, (addr&0xff00)>>8); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, (addr&0x00ff)); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x30+list1/100); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x30+list1/10%10); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x30+list1%10); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x30+list2/10); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x30+list2%10); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0xff ); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0xff ); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + __nop(); + __nop(); + __nop(); + __nop(); + __nop(); + + __nop(); + __nop(); + __nop(); + __nop(); + __nop(); + +} + +//显示BMS的SN号 +//0x02CD +void SDWA_Send_VER_BMSSN(uint16_t addr, uint8_t *data) +{ + uint8_t i; + + USART_SendData(USART2, 0xA5); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x5A); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x0E); //9+5 + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x82); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, (addr&0xff00)>>8); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, (addr&0x00ff)); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + for(i=0;i<9;i++) + { + USART_SendData(USART2, data[i]); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + } + + USART_SendData(USART2, 0xff ); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0xff ); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + __nop(); + __nop(); + __nop(); + __nop(); + __nop(); + + __nop(); + __nop(); + __nop(); + __nop(); + __nop(); + +} + +//显示PACK的SN号 +//0x02C0 +void SDWA_Send_VER_PACKSN(uint16_t addr, uint8_t *data) +{ + uint8_t i; + uint8_t n=0; //有几个有效字符 + + for(i=0;i<15;i++) + { + if(data[i]!=0xff) + { + n++; + } + } + + USART_SendData(USART2, 0xA5); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x5A); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, n+5); //length + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x82); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, (addr&0xff00)>>8); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, (addr&0x00ff)); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + for(i=0;i0:00 +void SDWA_Send_TimeCount(uint16_t addr,uint16_t countdown) +{ + uint8_t min=countdown/60; + uint8_t sec=countdown%60; + + USART_SendData(USART2, 0xA5); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x5A); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x0A); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x82); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, (addr&0xff00)>>8); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, (addr&0x00ff)); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x30+min/10); //min + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x30+min%10); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, ':'); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x30+sec/10); //sec + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x30+sec%10); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0xff ); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0xff ); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + __nop(); + __nop(); + __nop(); + __nop(); + __nop(); + + __nop(); + __nop(); + __nop(); + __nop(); + __nop(); + +} + +//0x0020,文本传输：2023-08-07 14:00:00 +//A5 5A 0A 82 00 20 year month date week hour min sec +void SDWA_Send_Time(uint16_t addr) +{ + USART_SendData(USART2, 0xA5); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x5A); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x18); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x82); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, (addr&0xff00)>>8); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, (addr&0x00ff)); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x30+calendar.w_date/16); //day + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x30+calendar.w_date%16); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, '/'); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x30+calendar.w_month/16); //month + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x30+calendar.w_month%16); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, '/'); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, '2'); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, '0'); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x30+calendar.w_year/16); //year + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x30+calendar.w_year%16); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, ' '); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x30+calendar.hour/16); //hour + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x30+calendar.hour%16); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, ':'); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x30+calendar.min/16); //min + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x30+calendar.min%16); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, ':'); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x30+calendar.sec/16); //sec + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x30+calendar.sec%16); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0xff ); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0xff ); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + __nop(); + __nop(); + __nop(); + __nop(); + __nop(); + + __nop(); + __nop(); + __nop(); + __nop(); + __nop(); + +} + + +/**报警记录的显示**/ +//0x0040,0x0080,0x00C0 +void SDWA_Send_RecordTime(uint16_t addr) +{ + uint8_t time[6]; + + time[0] = recordBuf[4]; //year + time[1] = recordBuf[5]; //month + time[2] = recordBuf[6]; //date + time[3] = recordBuf[7]; //hour + time[4] = recordBuf[8]; //min + time[5] = recordBuf[9]; //sec + + USART_SendData(USART2, 0xA5); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x5A); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x18); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x82); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, (addr&0xff00)>>8); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, (addr&0x00ff)); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x30+time[2]/16); //day + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x30+time[2]%16); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, '/'); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x30+time[1]/16); //month + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x30+time[1]%16); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, '/'); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, '2'); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, '0'); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x30+time[0]/16); //year + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x30+time[0]%16); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, ' '); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x30+time[3]/16); //hour + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x30+time[3]%16); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, ':'); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x30+time[4]/16); //min + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x30+time[4]%16); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, ':'); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x30+time[5]/16); //sec + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x30+time[5]%16); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0xff ); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0xff ); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + __nop(); + __nop(); + __nop(); + __nop(); + __nop(); + + __nop(); + __nop(); + __nop(); + __nop(); + __nop(); + +} + +//0x0060,0x00A0,0x00E0 +void SDWA_Send_Record(uint16_t addr) +{ + uint16_t bStatus1; + uint16_t bStatus2; + uint16_t bStatus3; + uint16_t temperaStatus; + + uint8_t i; + uint8_t sendcount; + char *p = &sendRecord[0]; + + if((recordBuf[50] == 0x05) && (recordBuf[51] == 0xA5)) //旧报警记录格式 + { + bStatus1 = recordBuf[44]; + bStatus2 = recordBuf[45]; + bStatus3 = recordBuf[46]; + temperaStatus = recordBuf[47]; + } + else //新报警记录格式 //宁化时代新增保护，把recordBuf[15]拆分到原来的位置 + { + bStatus1 = (recordBuf[15] & 0xf0) <<4 | recordBuf[10]; + bStatus2 = recordBuf[11]; + bStatus3 = recordBuf[12]; + temperaStatus = (recordBuf[15] & 0x0f) <<8 | recordBuf[13]; + } + + sendcount = 0; + for(i=0;i<64;i++) + { + sendRecord[i]=0; + } + + /*电压*/ + if((bStatus1 & 0x0100) != 0) //总体过压 + { + sendcount +=8; + *p = 'P'; p++; + *p = 'a'; p++; + *p = 'c'; p++; + *p = 'k'; p++; + *p = '_'; p++; + *p = 'O'; p++; + *p = 'V'; p++; + *p = ' '; p++; + } + if((bStatus1 & 0x0200) != 0) //总体欠压 + { + sendcount +=8; + *p = 'P'; p++; + *p = 'a'; p++; + *p = 'c'; p++; + *p = 'k'; p++; + *p = '_'; p++; + *p = 'U'; p++; + *p = 'V'; p++; + *p = ' '; p++; + } + if((bStatus1 & 0x0001) != 0) //单体过压 + { + sendcount +=3; + *p = 'O'; p++; + *p = 'V'; p++; + *p = ' '; p++; + } + if((bStatus1 & 0x0002) != 0) //单体欠压 + { + sendcount +=3; + *p = 'U'; p++; + *p = 'V'; p++; + *p = ' '; p++; + } + if((bStatus1 & 0x0040) !=0) //异常高压保护 + { + sendcount +=3; + *p = 'P'; p++; + *p = 'F'; p++; + *p = ' '; p++; + } + if((bStatus3 & 0x0008) !=0) //低电压禁止充电 + { + sendcount +=4; + *p = 'L'; p++; + *p = '0'; p++; + *p = 'V'; p++; + *p = ' '; p++; + } + /**电流**/ + if(((bStatus1 & 0x0010) != 0) || ((temperaStatus & 0x0010) != 0)) //充电过流 + { + sendcount +=4; + *p = 'O'; p++; + *p = 'C'; p++; + *p = 'C'; p++; + *p = ' '; p++; + } + if(((bStatus1 & 0x042C) != 0) || ((temperaStatus & 0x0020) != 0)) //放电过流1/2 + { + sendcount +=4; + *p = 'O'; p++; + *p = 'C'; p++; + *p = 'D'; p++; + *p = ' '; p++; + } + if((bStatus1 & 0x0020) !=0) //浪涌短路 + { + sendcount +=3; + *p = 'S'; p++; + *p = 'C'; p++; + *p = ' '; p++; + } + if((bStatus2 & 0x0010) !=0) //真短路保护 + { + sendcount +=8; + *p = 'S'; p++; + *p = 'C'; p++; + *p = '_'; p++; + *p = 'L'; p++; + *p = 'o'; p++; + *p = 'c'; p++; + *p = 'k'; p++; + *p = ' '; p++; + } + /**温度**/ + if(((bStatus2 & 0x0001) !=0) || ((temperaStatus & 0x0404) !=0)) //充电低温 + { + sendcount +=4; + *p = 'U'; p++; + *p = 'T'; p++; + *p = 'C'; p++; + *p = ' '; p++; + } + if(((bStatus2 & 0x0002) !=0) || ((temperaStatus & 0x0101) !=0)) //充电高温 + { + sendcount +=4; + *p = 'O'; p++; + *p = 'T'; p++; + *p = 'C'; p++; + *p = ' '; p++; + } + if(((bStatus2 & 0x0004) !=0) || ((temperaStatus & 0x0808) !=0)) //放电低温 + { + sendcount +=4; + *p = 'U'; p++; + *p = 'T'; p++; + *p = 'D'; p++; + *p = ' '; p++; + } + if(((bStatus2 & 0x0008) !=0) || ((temperaStatus & 0x0202) !=0)) //放电高温 + { + sendcount +=4; + *p = 'O'; p++; + *p = 'T'; p++; + *p = 'D'; p++; + *p = ' '; p++; + } + /**故障**/ + if((temperaStatus & 0x0040) !=0) //急停 RPSD_Activated + { + sendcount +=15; + *p = 'R'; p++; + *p = 'P'; p++; + *p = 'S'; p++; + *p = 'D'; p++; + *p = '_'; p++; + *p = 'A'; p++; + *p = 'c'; p++; + *p = 't'; p++; + *p = 'i'; p++; + *p = 'v'; p++; + *p = 'a'; p++; + *p = 't'; p++; + *p = 'e'; p++; + *p = 'd'; p++; + *p = ' '; p++; + } + if((bStatus2 & 0x0040) !=0) //放电MOS故障 + { + sendcount +=11; + *p = 'D'; p++; + *p = '-'; p++; + *p = 'M'; p++; + *p = 'O'; p++; + *p = 'S'; p++; + *p = 'f'; p++; + *p = 'a'; p++; + *p = 'u'; p++; + *p = 'l'; p++; + *p = 't'; p++; + *p = ' '; p++; + } + if((bStatus2 & 0x0080) !=0) //充电MOS故障 + { + sendcount +=11; + *p = 'C'; p++; + *p = '-'; p++; + *p = 'M'; p++; + *p = 'O'; p++; + *p = 'S'; p++; + *p = 'f'; p++; + *p = 'a'; p++; + *p = 'u'; p++; + *p = 'l'; p++; + *p = 't'; p++; + *p = ' '; p++; + } + if((bStatus2 & 0x0020) !=0) //预充失败 + { + sendcount +=10; + *p = 'P'; p++; + *p = 'C'; p++; + *p = 'H'; p++; + *p = 'G'; p++; + *p = '_'; p++; + *p = 'F'; p++; + *p = 'a'; p++; + *p = 'i'; p++; + *p = 'l'; p++; + *p = ' '; p++; + } + + + USART_SendData(USART2, 0xA5); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x5A); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, sendcount+3); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, 0x82); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, (addr&0xff00)>>8); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, (addr&0x00ff)); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + for(i=0;i>8); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + USART_SendData(USART2, (addr&0x00ff)); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + + for(i=0;i<64;i++) + { + USART_SendData(USART2, sendRecord[i]); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + } + +__nop(); +__nop(); +__nop(); +__nop(); +__nop(); + +__nop(); +__nop(); +__nop(); +__nop(); +__nop(); + +} + + +/**报警页面的显示**/ +void SDWA_ClearAlarm(void) +{ + //报警内容显示 + //单体过压 + SDWA_Send_VAR(0x0187, 0); + + //单体欠压 + SDWA_Send_VAR(0x0193, 0); + + //充电过流 + SDWA_Send_VAR(0x0188, 0); + + //放电过流 + SDWA_Send_VAR(0x0194, 0); + + //充电高温 + SDWA_Send_VAR(0x0189, 0); + + //充电低温 + SDWA_Send_VAR(0x0195, 0); + + //放电高温 + SDWA_Send_VAR(0x0190, 0); + + //放电低温 + SDWA_Send_VAR(0x0196, 0); + + //异常高压 + SDWA_Send_VAR(0x0191, 0); + + //低压禁止充电 + SDWA_Send_VAR(0x0197, 0); + + //短路保护 + SDWA_Send_VAR(0x0192, 0); +} + +void SDWA_ShowAlarm(void) +{ + //报警内容显示 + //单体过压&总体过压 + if(((bmsMem.bStatus1 & 0x0001) != 0) || ((bmsMem.bStatus1 & 0x0100) != 0)) + { + if(bmsMem.soc<99) + { + SDWA_Send_VAR(0x0187, 1); + } + else //当SOC大于99%，此时触发过压报警，不会跳转屏幕，也不会亮报警灯 + { + SDWA_Send_VAR(0x0187, 0); + } + } + else + { + SDWA_Send_VAR(0x0187, 0); + } + //单体欠压&总体欠压 + if(((bmsMem.bStatus1 & 0x0002) != 0) || ((bmsMem.bStatus1 & 0x0200) != 0)) + { + SDWA_Send_VAR(0x0193, 1); + } + else + { + SDWA_Send_VAR(0x0193, 0); + } + //afe充电过流&充电过流 + if(((bmsMem.bStatus1 & 0x0010) != 0) || ((bmsMem.temperaStatus & 0x0010) != 0)) + { + SDWA_Send_VAR(0x0188, 1); + } + else + { + SDWA_Send_VAR(0x0188, 0); + } + //afe放电过流&放电过流1&放电过流2 + if(((bmsMem.bStatus1 & 0x000c) != 0) || ((bmsMem.temperaStatus & 0x0020) != 0) || ((bmsMem.bStatus1 & 0x0400) != 0)) + { + SDWA_Send_VAR(0x0194, 1); + } + else + { + SDWA_Send_VAR(0x0194, 0); + } + //afe充电高温&环境充电高温&电芯充电高温 + if(((bmsMem.bStatus2 & 0x0002) != 0) || ((bmsMem.temperaStatus & 0x0100) != 0) || ((bmsMem.temperaStatus & 0x0001) != 0)) + { + SDWA_Send_VAR(0x0189, 1); + } + else + { + SDWA_Send_VAR(0x0189, 0); + } + //afe放电高温&环境放电高温&电芯放电高温 + if(((bmsMem.bStatus2 & 0x0008) != 0) || ((bmsMem.temperaStatus & 0x0200) != 0) || ((bmsMem.temperaStatus & 0x0002) != 0)) + { + SDWA_Send_VAR(0x0190, 1); + } + else + { + SDWA_Send_VAR(0x0190, 0); + } + //afe充电低温&环境充电低温&电芯充电低温 + if(((bmsMem.bStatus2 & 0x0001) != 0) || ((bmsMem.temperaStatus & 0x0400) != 0) || ((bmsMem.temperaStatus & 0x0004) != 0)) + { + SDWA_Send_VAR(0x0195, 1); + } + else + { + SDWA_Send_VAR(0x0195, 0); + } + //afe放电低温&环境放电低温&电芯放电低温 + if(((bmsMem.bStatus2 & 0x0004) != 0) || ((bmsMem.temperaStatus & 0x0800) != 0) || ((bmsMem.temperaStatus & 0x0008) != 0)) + { + SDWA_Send_VAR(0x0196, 1); + } + else + { + SDWA_Send_VAR(0x0196, 0); + } + //异常高压 + if((bmsMem.bStatus1 & 0x0040) != 0) + { + SDWA_Send_VAR(0x0191, 1); + } + else + { + SDWA_Send_VAR(0x0191, 0); + } + //低压禁止充电 + if((bmsMem.bStatus3 & 0x0008) != 0) + { + SDWA_Send_VAR(0x0197, 1); + } + else + { + SDWA_Send_VAR(0x0197, 0); + } + //真短路保护 + if((bmsMem.bStatus2 & 0x0010) != 0) //只有预充情况才会出现短路锁定，出现则一直保持，这里也一直显示 + { + SDWA_Send_VAR(0x0192, 1); + } + //浪涌短路保护 + else if((bmsMem.bStatus1 & 0x0020) != 0) + { + SDWA_Send_VAR(0x0192, 1); + } + else + { + SDWA_Send_VAR(0x0192, 0); + } +} + +void SDWA_ShowAlarm_Slave(void) //读取的从机报警数据的显示 +{ + //报警内容显示 + //单体过压&总体过压 + if(((bmsMem_slave.bStatus1 & 0x0001) != 0) || ((bmsMem_slave.bStatus1 & 0x0100) != 0)) + { + if(bmsMem_slave.soc<99) + { + SDWA_Send_VAR(0x0187, 1); + } + else //当SOC大于99%，此时触发过压报警，不会跳转屏幕，也不会亮报警灯 + { + SDWA_Send_VAR(0x0187, 0); + } + } + else + { + SDWA_Send_VAR(0x0187, 0); + } + //单体欠压&总体欠压 + if(((bmsMem_slave.bStatus1 & 0x0002) != 0) || ((bmsMem_slave.bStatus1 & 0x0200) != 0)) + { + SDWA_Send_VAR(0x0193, 1); + } + else + { + SDWA_Send_VAR(0x0193, 0); + } + //afe充电过流&充电过流 + if(((bmsMem_slave.bStatus1 & 0x0010) != 0) || ((bmsMem_slave.temperaStatus & 0x0010) != 0)) + { + SDWA_Send_VAR(0x0188, 1); + } + else + { + SDWA_Send_VAR(0x0188, 0); + } + //afe放电过流&放电过流1&放电过流2 + if(((bmsMem_slave.bStatus1 & 0x000c) != 0) || ((bmsMem_slave.temperaStatus & 0x0020) != 0) || ((bmsMem_slave.bStatus1 & 0x0400) != 0)) + { + SDWA_Send_VAR(0x0194, 1); + } + else + { + SDWA_Send_VAR(0x0194, 0); + } + //afe充电高温&环境充电高温&电芯充电高温 + if(((bmsMem_slave.bStatus2 & 0x0002) != 0) || ((bmsMem_slave.temperaStatus & 0x0100) != 0) || ((bmsMem_slave.temperaStatus & 0x0001) != 0)) + { + SDWA_Send_VAR(0x0189, 1); + } + else + { + SDWA_Send_VAR(0x0189, 0); + } + //afe放电高温&环境放电高温&电芯放电高温 + if(((bmsMem_slave.bStatus2 & 0x0008) != 0) || ((bmsMem_slave.temperaStatus & 0x0200) != 0) || ((bmsMem_slave.temperaStatus & 0x0002) != 0)) + { + SDWA_Send_VAR(0x0190, 1); + } + else + { + SDWA_Send_VAR(0x0190, 0); + } + //afe充电低温&环境充电低温&电芯充电低温 + if(((bmsMem_slave.bStatus2 & 0x0001) != 0) || ((bmsMem_slave.temperaStatus & 0x0400) != 0) || ((bmsMem_slave.temperaStatus & 0x0004) != 0)) + { + SDWA_Send_VAR(0x0195, 1); + } + else + { + SDWA_Send_VAR(0x0195, 0); + } + //afe放电低温&环境放电低温&电芯放电低温 + if(((bmsMem_slave.bStatus2 & 0x0004) != 0) || ((bmsMem_slave.temperaStatus & 0x0800) != 0) || ((bmsMem_slave.temperaStatus & 0x0008) != 0)) + { + SDWA_Send_VAR(0x0196, 1); + } + else + { + SDWA_Send_VAR(0x0196, 0); + } + //异常高压 + if((bmsMem_slave.bStatus1 & 0x0040) != 0) + { + SDWA_Send_VAR(0x0191, 1); + } + else + { + SDWA_Send_VAR(0x0191, 0); + } + //低压禁止充电 + if((bmsMem_slave.bStatus3 & 0x0008) != 0) + { + SDWA_Send_VAR(0x0197, 1); + } + else + { + SDWA_Send_VAR(0x0197, 0); + } + //真短路保护 + if((bmsMem_slave.bStatus2 & 0x0010) != 0) //只有预充情况才会出现短路锁定，出现则一直保持，这里也一直显示 + { + SDWA_Send_VAR(0x0192, 1); + } + //浪涌短路保护 + else if((bmsMem_slave.bStatus1 & 0x0020) != 0) + { + SDWA_Send_VAR(0x0192, 1); + } + else + { + SDWA_Send_VAR(0x0192, 0); + } +} + +void SDWA_JumpToAlarm(void) +{ +// if(language == 0) +// { + SDWA_JumpToNumber(4); +// } +// else if(language == 1) +// { +// SDWA_JumpToNumber(32); +// } +} + + +/**报警记录显示**/ +//被SDWA_Init()调用，用于自身报警记录和信息显示 +void SDWA_Send_RecordInfo(void) +{ + uint8_t i; + uint8_t adrh,adrl; + uint32_t ee_index[3]; + uint16_t ee_pc[3]; + + //报警记录序号,初始默认0，1，2 + ee_index[0] = read_index; + ee_pc[0] = 0x1000 + 0x0040 * ee_index[0]; + ee_index[1] = read_index+1; + ee_pc[1] = 0x1000 + 0x0040 * ee_index[1]; + ee_index[2] = read_index+2; + ee_pc[2] = 0x1000 + 0x0040 * ee_index[2]; + + SDWA_Send_VAR(0x0132, ee_index[0]+1); + if(ee_index[2] != 101) //对应序号101.102不显示 + { + SDWA_Send_VAR(0x0144, 0); + SDWA_Send_VAR(0x0133, ee_index[1]+1); + SDWA_Send_VAR(0x0134, ee_index[2]+1); + } + else + { + SDWA_Send_VAR(0x0144, 1); + } + + //报警记录序号对应的报警内容 + if(read_index < soe.num)//为减少读写EEPROM次数，只当序号在soe.num范围内时可用 //read_index+1 <= soe.num的简写 + { + for(i=0;i<3;i++) + { + adrh = (ee_pc[i]>>8) & 0xff; + adrl = ee_pc[i] & 0xff; + EEPROM_RdMulByte(adrh,adrl,52,recordBuf); + delay_ms(10); + + if(recordBuf[0]==0xff && recordBuf[1]==0xff && recordBuf[2]==0xff && recordBuf[3]==0xff)//序号数据全是0xff,表示无数据 + { + SDWA_Send_Blank(0x0040 + 0x0040*i); + SDWA_Send_Blank(0x0060 + 0x0040*i); + + SDWA_Send_VAR(0x0140 + 0x0001*i,1); + } + else + { + SDWA_Send_VAR(0x0140 + 0x0001*i,0); + + if(recordBuf[4]!=0 || recordBuf[5]!=0 || recordBuf[6]!=0 || recordBuf[7]!=0 || recordBuf[8]!=0 || recordBuf[9]!=0) + { + SDWA_Send_RecordTime(0x0040 + 0x0040*i); + } + else + { + SDWA_Send_Blank(0x0040 + 0x0040*i); + } + SDWA_Send_Blank(0x0060 + 0x0040*i); //防止上次的记录比这次长 + SDWA_Send_Record(0x0060 + 0x0040*i); + } + } + } + else + { + for(i=0;i<3;i++) + { + SDWA_Send_Blank(0x0040 + 0x0040*i); + SDWA_Send_Blank(0x0060 + 0x0040*i); + + SDWA_Send_VAR(0x0140 + 0x0001*i,1); + } + } + + //报警记录个数和最新记录对应序号(更新) + SDWA_Send_VAR(0x0130, soe.num ); //记录个数的显示 + if((soe.index == 0) || (soe.index%100 != 0)) //最新记录所在 + { + SDWA_Send_VAR(0x0131, soe.index%100 ); + } + else + { + SDWA_Send_VAR(0x0131, 100 ); + } +} + +//被SDWA_Init()调用，用于主机查看从机的报警记录(暂直接显示空白和数据0) +void SDWA_Send_Slave_RecordBank(void) +{ + uint8_t i; + + //报警记录序号 + SDWA_Send_VAR(0x0132, 1); + SDWA_Send_VAR(0x0133, 2); + SDWA_Send_VAR(0x0144, 0); + SDWA_Send_VAR(0x0134, 3); + + //报警记录序号对应的报警内容 + for(i=0;i<3;i++) + { + SDWA_Send_VAR(0x0140 + 0x0001*i,1); + } + + //报警记录个数和最新记录对应序号 + SDWA_Send_VAR(0x0130, 0 ); + SDWA_Send_VAR(0x0131, 0 ); +} + + +/**协议选择的显示**/ + //A5 5A 06 83 03 10 01 00 01 勾选 + //A5 5A 06 83 03 10 01 00 00 取消勾选 + //A5 5A 05 82 03 00 00 01 显示勾选 + //A5 5A 05 82 03 00 00 00 显示取消勾选 +void SDWA_DispProcotol(uint8_t addrH, uint8_t addrL, uint8_t data) +{ + USART_SendData(USART2, 0xA5); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + USART_SendData(USART2, 0x5A); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + USART_SendData(USART2, 0x05); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + USART_SendData(USART2, 0x82); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + USART_SendData(USART2, addrH); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + USART_SendData(USART2, addrL); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + USART_SendData(USART2, 0x00); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + USART_SendData(USART2, data); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); +} + +void SDWA_DispProtocol_P1Null(void) +{ + //P1 + SDWA_DispProcotol(0x03,0x00,0x00); + SDWA_DispProcotol(0x03,0x01,0x00); + SDWA_DispProcotol(0x03,0x02,0x00); + SDWA_DispProcotol(0x03,0x03,0x00); + SDWA_DispProcotol(0x03,0x04,0x00); + SDWA_DispProcotol(0x03,0x05,0x00); +} +void SDWA_DispProtocol_P2Null(void) +{ + //P2 + SDWA_DispProcotol(0x03,0x06,0x00); + SDWA_DispProcotol(0x03,0x07,0x00); + SDWA_DispProcotol(0x03,0x08,0x00); + SDWA_DispProcotol(0x03,0x09,0x00); + SDWA_DispProcotol(0x03,0x0A,0x00); + SDWA_DispProcotol(0x03,0x0B,0x00); + SDWA_DispProcotol(0x03,0x0C,0x00); + SDWA_DispProcotol(0x03,0x0D,0x00); + SDWA_DispProcotol(0x03,0x0E,0x00); +} +void SDWA_DispProtocol_P3Null(void) +{ + //P3 + SDWA_DispProcotol(0x03,0x0F,0x00); + SDWA_DispProcotol(0x03,0x20,0x00); + SDWA_DispProcotol(0x03,0x21,0x00); + SDWA_DispProcotol(0x03,0x22,0x00); + SDWA_DispProcotol(0x03,0x23,0x00); + SDWA_DispProcotol(0x03,0x24,0x00); + SDWA_DispProcotol(0x03,0x25,0x00); + SDWA_DispProcotol(0x03,0x26,0x00); + SDWA_DispProcotol(0x03,0x27,0x00); +} +void SDWA_DispProtocol_P4Null(void) +{ + //P4 + SDWA_DispProcotol(0x03,0x28,0x00); + SDWA_DispProcotol(0x03,0x29,0x00); + SDWA_DispProcotol(0x03,0x2A,0x00); + SDWA_DispProcotol(0x03,0x2B,0x00); + SDWA_DispProcotol(0x03,0x2C,0x00); + SDWA_DispProcotol(0x03,0x2D,0x00); + SDWA_DispProcotol(0x03,0x2E,0x00); + SDWA_DispProcotol(0x03,0x2F,0x00); + SDWA_DispProcotol(0x03,0x40,0x00); +} +void SDWA_DispProtocol_P5Null(void) +{ + //P5 + SDWA_DispProcotol(0x03,0x41,0x00); + SDWA_DispProcotol(0x03,0x42,0x00); + SDWA_DispProcotol(0x03,0x43,0x00); + SDWA_DispProcotol(0x03,0x44,0x00); + SDWA_DispProcotol(0x03,0x47,0x00); //在这里跳过2个地址 + SDWA_DispProcotol(0x03,0x48,0x00); + SDWA_DispProcotol(0x03,0x49,0x00); + SDWA_DispProcotol(0x03,0x4A,0x00); + SDWA_DispProcotol(0x03,0x4B,0x00); +} + + +/**屏幕数据更新的显示**/ +//被SDWA_UpdateData()调用，用于显示总数据 +void SDWA_Send_TotalInfo(void) +{ + uint16_t voltage; + int16_t current; + uint16_t temperature; //【不删兼容其他屏幕】 + + uint16_t totalCapacity; + uint16_t capacity; + uint8_t soc; + + /**Wh版屏幕相关**/ + int32_t export_P; + uint16_t total_W,remain_W,cumuli_W; + + uint8_t OV_bAlarmFlag = 0; //过压报警标志位 + + int16_t Progress; //充放电进度条 + uint16_t remain_T; //充放电剩余时间 + /**Wh版屏幕相关**/ + + voltage = bmsMem.packVoltage /100; //总电压，单位0.1V + current = canMem[0].cur /10; //总电流，单位0.1A + temperature = canMem[0].temp; //温度 //【不删兼容其他屏幕】 + totalCapacity = 10 * ncc_Ah * OnlineNum; //总额定容量，单位0.1Ah + capacity = totalCapacity * canMem[0].soc /100; //总当前容量，单位0.1Ah + soc = canMem[0].soc; //平均soc + + SDWA_Send_VAR(0x0241, voltage); //总电压 + SDWA_Send_VAR(0x0242, current); //总电流 + SDWA_Send_VAR(0x0245, temperature - 2731);//平均温度 //【不删兼容其他屏幕】 + + SDWA_Send_VAR(0x0243, totalCapacity); //总额定容量 //【不删兼容其他屏幕】 + SDWA_Send_VAR(0x0244, capacity); //总当前容量 //【不删兼容其他屏幕】 + SDWA_Send_VAR(0x0246, soc); //平均soc + + /**Wh版屏幕相关**/ + export_P = voltage*current/10; //当前消耗功率=总电压x总电流，单位0.1W=10*(0.1V*0.1A) + total_W = totalCapacity*(3.2*bmsMem.ucCellNum)/1000; //额定能量=额定总容量x额定电压，单位0.1kWh=1000*(0.1Ah*1V) + remain_W = capacity*(3.2*bmsMem.ucCellNum)/1000; //剩余能量=当前总容量x额定电压，单位0.1kWh=1000*(0.1Ah*1V) + cumuli_W = (canMem[0].cycleCnt*fcc_Ah+canMem[0].cumuliCap)*(3.2*bmsMem.ucCellNum)/100/1000; //累积消耗能量=(总循环次数1x单PACK额定容量Ah+总累积消耗容量Ah)x额定电压V，单位0.1MWh=100000*1Wh + + SDWA_Send_VAR(0x0378,(export_P>>16) & 0xFFFF); //当前消耗功率，高16位 + SDWA_Send_VAR(0x0379, export_P & 0xFFFF); //当前消耗功率，低16位 + SDWA_Send_VAR(0x0372, total_W); //额定能量 + SDWA_Send_VAR(0x0371, remain_W); //剩余能量 + SDWA_Send_VAR(0x0373, cumuli_W); //总累积消耗功率Mwh + Progress = (voltage*current)/18000; //充放电进度条，100%对应18kW，1%对应0.18kW=18000*0.1V*0.1A + if(Progress>112) + { + Progress = 112; + } + else if(Progress<(-112)) + { + Progress = -112; + } + + if(((canMem[0].status_byte1 & 0x7e)==0) && ((canMem[0].status_byte2 & 0xef) ==0) && ((canMem[0].status_byte3 & 0x18) ==0) && ((canMem[0].status_byte4 & 0x3f) ==0)) //9.27 除了过压报警，其他报警都没有 + { + if(((bmsMem.bStatus1 & 0x7e)==0) && ((bmsMem.bStatus2 & 0xef) ==0) && ((bmsMem.bStatus3 & 0x18) ==0) && ((bmsMem.temperaStatus & 0x3f) ==0)) //9.27 除了过压报警，其他报警都没有【主机自身】 + { + if(((bmsMem.bStatus1 & 0x01) != 0) && (bmsMem.soc<99)) //过压报警的判断：满电时发生[过压保护],屏幕不显示过压【主机自身】 + { + OV_bAlarmFlag = 1; + } + else if((canMem[0].status_byte1 & 0x01) != 0) //若并机线上有过压报警，需判断是否需要报警 + { + //轮询每个收集到的数据，若有未满压且发生过压报警的从机，则总数据显示报警 + uint8_t i; + for(i=1;i<=paraMem.PACK_NUM;i++) + { + if(canMem[i].com != 0) //该从机在线 + { + if(((canMem[i].status_byte1 & 0x01) != 0) && (canMem[i].soc<99)) //该从机正在过压报警 + { + OV_bAlarmFlag = 1; + break; + } + } + } + } + + if(OV_bAlarmFlag == 1) //过压报警 + { + SDWA_Send_VAR(0x0374, 2); //“Fault” + } + else + { + if(current>100) //充电状态 + { + SDWA_Send_VAR(0x0374, 0); //“Charge” + } + else if(current<(-100)) //放电状态 + { + SDWA_Send_VAR(0x0374, 1); //“Discharge” + } + else //待机状态 + { + SDWA_Send_VAR(0x0374, 6); //“Standby” + } + } + } + else + { + SDWA_Send_VAR(0x0374, 2); //“Fault” + } + } + else + { + SDWA_Send_VAR(0x0374, 2); //“Fault” + } + + if(current>100) //充电状态 + { + SDWA_Send_VAR(0x05B6, 0); //放电进度条隐去 + SDWA_Send_VAR(0x05B5, Progress); //充电进度条 + + remain_T = (totalCapacity - capacity)*10/current; //充电剩余时间=(额定总容量-当前总容量)0.1Ah/总电流0.1A，单位0.1h=0.1*0.1Ah/0.1A + SDWA_Send_VAR(0x0375, remain_T); //充电剩余时间 + SDWA_Send_VAR(0x0376, 0); //充放电剩余时间挡条不显示 + } + else if(current<(-100)) //放电状态 + { + SDWA_Send_VAR(0x05B5, 0); //充电进度条隐去 + SDWA_Send_VAR(0x05B6, -Progress); //放电进度条 + + remain_T = capacity*10/(-current); //放电剩余时间=当前总容量0.1Ah/总电流0.1A，单位0.1h=0.1*0.1Ah/0.1A + SDWA_Send_VAR(0x0375, remain_T); //放电剩余时间 + SDWA_Send_VAR(0x0376, 0); //充放剩余电时间挡条不显示 + } + else //待机状态 + { + SDWA_Send_VAR(0x05B5, 0); //充电进度条隐去 + SDWA_Send_VAR(0x05B6, 0); //放电进度条隐去 + + SDWA_Send_VAR(0x0375, 0); //充放电剩余时间都为0 + SDWA_Send_VAR(0x0376, 1); //充放电剩余时间挡条显示 + } + /**Wh版屏幕相关**/ +} + +//被SDWA_UpdateData()调用，用于显示自身基本信息 +void SDWA_Send_Self_BasicInfo(void) +{ + uint8_t i; + + uint16_t voltage; + int16_t current; + uint16_t capacity; + uint8_t soc; + + /**Wh版屏幕相关**/ + int32_t export_P; + uint16_t remain_W; + + uint16_t Ave_Temp; //平均温度 + + int16_t Progress; //充放电进度条 + uint16_t remain_T; //充放电剩余时间 + /**Wh版屏幕相关**/ + + voltage = bmsMem.packVoltage /100; //电压，单位0.1V + current = bmsMem.packCurrent /100; //电流，单位0.1A + capacity = bmsMem.rcc/360000; //当前容量，单位0.1Ah + soc = bmsMem.soc; //平均SOC + + //发送数据到串口显示屏，已经调试成功 + SDWA_Send_VAR(0x0000, voltage); //TOTAL VOLTAGE + SDWA_Send_VAR(0x0002, current); //CURRENT + SDWA_Send_VAR(0x0004, capacity); //CAPACITY //【不删兼容其他屏幕】 + SDWA_Send_VAR(0x0230, soc); //SOC + + for(i=0;i<16;i++) + { + if(cellVol[i] >= 0) + { + SDWA_Send_VAR(0x0010+i, bmsMem.vCell[i]); + } + else + { + SDWA_Send_VAR(0x0010+i, 0); + } + } +// SDWA_Send_VAR(0x0010, bmsMem.vCell[0]); //CELL1 +// SDWA_Send_VAR(0x0011, bmsMem.vCell[1]); //CELL2 +// SDWA_Send_VAR(0x0012, bmsMem.vCell[2]); //CELL3 +// SDWA_Send_VAR(0x0013, bmsMem.vCell[3]); //CELL4 +// SDWA_Send_VAR(0x0014, bmsMem.vCell[4]); //CELL5 +// SDWA_Send_VAR(0x0015, bmsMem.vCell[5]); //CELL6 +// SDWA_Send_VAR(0x0016, bmsMem.vCell[6]); //CELL7 +// SDWA_Send_VAR(0x0017, bmsMem.vCell[7]); //CELL8 +// SDWA_Send_VAR(0x0018, bmsMem.vCell[8]); //CELL9 +// SDWA_Send_VAR(0x0019, bmsMem.vCell[9]); //CELL10 +// SDWA_Send_VAR(0x001A, bmsMem.vCell[10]); //CELL11 +// SDWA_Send_VAR(0x001B, bmsMem.vCell[11]); //CELL12 +// SDWA_Send_VAR(0x001C, bmsMem.vCell[12]); //CELL13 +// SDWA_Send_VAR(0x001D, bmsMem.vCell[13]); //CELL14 +// SDWA_Send_VAR(0x001E, bmsMem.vCell[14]); //CELL15 +// SDWA_Send_VAR(0x001F, bmsMem.vCell[15]); //CELL16 + + SDWA_Send_VAR(0x0201, bmsMem.mcu_T1 - 2731); //MCU T1 + SDWA_Send_VAR(0x0204, bmsMem.mcu_T2 - 2731); //MCU T2 + SDWA_Send_VAR(0x0202, bmsMem.mcu_T3 - 2731); //MCU T3 + SDWA_Send_VAR(0x0205, bmsMem.mcu_T4 - 2731); //MCU T4 + SDWA_Send_VAR(0x0200, bmsMem.afe_T1 - 2731); //AFE T1 + SDWA_Send_VAR(0x0203, bmsMem.afe_T2 - 2731); //AFE T2 + SDWA_Send_VAR(0x0206, bmsMem.afe_T3 - 2731); //AFE T3 + + SDWA_Send_VAR(0x0287, bmsMem.cellVoltageMaxIndex+1); //最高电压电芯序号 + SDWA_Send_VAR(0x028B, bmsMem.cellVoltageMinIndex+1); //最低电压电芯序号 + + //首页的状态显示and报警跳转 + if(bAlarmFlag == 0) //无屏幕上的报警 + { + if( (bmsMem.temperaStatus & 0x40) !=0) //急停 + { + SDWA_Send_VAR(0x0100, 5); //“RPSD_Activated”(急停) + } + else if((bmsMem.bStatus2 & 0xe0) !=0) + { + SDWA_Send_VAR(0x0100, 2); //“Fault”(其他报警：放电MOS故障、充电MOS故障、预充失败) + } + else + { + if(bSTANDBY == 1) + { + SDWA_Send_VAR(0x0100, 6); //“Standby”(待机) + } + else if(bCHGING ==1) + { + if((bmsMem.balanceStatus & 0x10) != 0) + { + SDWA_Send_VAR(0x0100, 7); //“CL-start”(限流) + } + else + { + SDWA_Send_VAR(0x0100, 0); //“Charge”(充电) + } + } + else + { + SDWA_Send_VAR(0x0100, 1); //“Discharge”(放电) + } + } + + SDWA_ClearAlarm(); + } + else + { + SDWA_Send_VAR(0x0100, 2); //“Fault”(屏幕上的报警) + + if(bAlarmFlagOld ==0) + { + bAlarmFlagOld = 1; + SDWA_JumpToAlarm(); + } + + SDWA_ShowAlarm(); + } + + //平衡状态 + if(balancing ==1) + { + SDWA_Send_VAR(0x0110, 0); //"On"(开启) + } + else + { + SDWA_Send_VAR(0x0110, 1); //"Off"(关闭) + } + + /**Wh版屏幕相关**/ + export_P = voltage*current/100; //当前消耗功率=总电压x总电流，单位1W=100*(0.1V*0.1A) + remain_W = capacity*(3.2*bmsMem.ucCellNum)/1000; //剩余能量=当前总容量x额定电压，单位0.1kWh=1000*(0.1Ah*1V) + Ave_Temp = TemperatureAverage; + + SDWA_Send_VAR(0x0366,(export_P>>16) & 0xFFFF); //当前消耗功率，高16位 + SDWA_Send_VAR(0x0367, export_P & 0xFFFF); //当前消耗功率，低16位 + SDWA_Send_VAR(0x0361, remain_W); //剩余能量 + + SDWA_Send_VAR(0x0364, Ave_Temp - 2731); //平均温度 + SDWA_Send_VAR(0x0365, bmsMem.cycleCount); //循环次数 + + Progress = (voltage*current)/6000; //充放电进度条，100%对应6kW，1%对应0.06kW=6000*0.1V*0.1A + if(Progress>100) + { + Progress = 100; + } + else if(Progress<(-100)) + { + Progress = -100; + } + + if(bCHGING ==1) //充电状态 + { + remain_T = (fcc - bmsMem.rcc)/36000/current; //充电剩余时间=((额定总容量-当前总容量mAS)/36000)/总电流，单位0.1h=0.01Ah/0.1A + } + else //放电状态 + { + remain_T = bmsMem.rcc/36000/(-current); //放电剩余时间=当前总容量mAS/36000/总电流，单位0.1h=0.01Ah/0.1A + } + + if(bSTANDBY == 1) //待机状态 + { + SDWA_Send_VAR(0x05A9, 0); //充电进度条隐去 + SDWA_Send_VAR(0x05AA, 0); //放电进度条隐去 + + SDWA_Send_VAR(0x0362, 0); //充放电剩余时间都为0 + SDWA_Send_VAR(0x0377, 1); //充放电剩余时间挡条显示 + } + else if(bCHGING ==1) //充电状态 + { + SDWA_Send_VAR(0x05AA, 0); //放电进度条隐去 + SDWA_Send_VAR(0x05A9, Progress); //充电进度条 + + SDWA_Send_VAR(0x0362, remain_T); //充电剩余时间 + SDWA_Send_VAR(0x0377, 0); //充放电剩余时间挡条不显示 + } + else //放电状态 + { + SDWA_Send_VAR(0x05A9, 0); //充电进度条隐去 + SDWA_Send_VAR(0x05AA, -Progress); //放电进度条 + + SDWA_Send_VAR(0x0362, remain_T); //放电剩余时间 + SDWA_Send_VAR(0x0377, 0); //充放电剩余时间挡条不显示 + } + /**Wh版屏幕相关**/ +} + +//被SDWA_UpdateData()调用，用于显示从机基本信息 +void SDWA_Send_Slave_BasicInfo(void) +{ + uint8_t i; + + uint16_t voltage; + int16_t current; + uint16_t capacity; + uint8_t soc; + + /**Wh版屏幕相关**/ + int32_t export_P; + uint16_t remain_W; + + uint16_t Ave_Temp; //平均温度 + + int16_t Progress; //充放电进度条 + uint16_t remain_T; //充放电剩余时间 + /**Wh版屏幕相关**/ + + voltage = bmsMem_slave.packVoltage /100; //电压，单位0.1V + current = bmsMem_slave.packCurrent /100; //电流，单位0.1A + capacity = bmsMem_slave.rcc/360000; //当前容量，单位0.1Ah + soc = bmsMem_slave.soc; //平均SOC + + //发送数据到串口显示屏，已经调试成功 + SDWA_Send_VAR(0x0000, voltage); //TOTAL VOLTAGE + SDWA_Send_VAR(0x0002, current); //CURRENT + SDWA_Send_VAR(0x0004, capacity); //CAPACITY //【不删兼容其他屏幕】 + SDWA_Send_VAR(0x0230, soc); //SOC + + for(i=0;i<16;i++) + { + int16_t vol = (int16_t)(bmsMem_slave.vCell[i]*32/5)*5/32; + if(vol >= 0) + { + SDWA_Send_VAR(0x0010+i, bmsMem_slave.vCell[i]); + } + else + { + SDWA_Send_VAR(0x0010+i, 0); + } + } +// SDWA_Send_VAR(0x0010, bmsMem_slave.vCell[0]); //CELL1 +// SDWA_Send_VAR(0x0011, bmsMem_slave.vCell[1]); //CELL2 +// SDWA_Send_VAR(0x0012, bmsMem_slave.vCell[2]); //CELL3 +// SDWA_Send_VAR(0x0013, bmsMem_slave.vCell[3]); //CELL4 +// SDWA_Send_VAR(0x0014, bmsMem_slave.vCell[4]); //CELL5 +// SDWA_Send_VAR(0x0015, bmsMem_slave.vCell[5]); //CELL6 +// SDWA_Send_VAR(0x0016, bmsMem_slave.vCell[6]); //CELL7 +// SDWA_Send_VAR(0x0017, bmsMem_slave.vCell[7]); //CELL8 +// SDWA_Send_VAR(0x0018, bmsMem_slave.vCell[8]); //CELL9 +// SDWA_Send_VAR(0x0019, bmsMem_slave.vCell[9]); //CELL10 +// SDWA_Send_VAR(0x001A, bmsMem_slave.vCell[10]); //CELL11 +// SDWA_Send_VAR(0x001B, bmsMem_slave.vCell[11]); //CELL12 +// SDWA_Send_VAR(0x001C, bmsMem_slave.vCell[12]); //CELL13 +// SDWA_Send_VAR(0x001D, bmsMem_slave.vCell[13]); //CELL14 +// SDWA_Send_VAR(0x001E, bmsMem_slave.vCell[14]); //CELL15 +// SDWA_Send_VAR(0x001F, bmsMem_slave.vCell[15]); //CELL16 + + SDWA_Send_VAR(0x0201, bmsMem_slave.mcu_T1 - 2731); //MCU T1 + SDWA_Send_VAR(0x0204, bmsMem_slave.mcu_T2 - 2731); //MCU T2 + SDWA_Send_VAR(0x0202, bmsMem_slave.mcu_T3 - 2731); //MCU T3 + SDWA_Send_VAR(0x0205, bmsMem_slave.mcu_T4 - 2731); //MCU T4 + SDWA_Send_VAR(0x0200, bmsMem_slave.afe_T1 - 2731); //AFE T1 + SDWA_Send_VAR(0x0203, bmsMem_slave.afe_T2 - 2731); //AFE T2 + SDWA_Send_VAR(0x0206, bmsMem_slave.afe_T3 - 2731); //AFE T3 + + SDWA_Send_VAR(0x0287, bmsMem_slave.cellVoltageMaxIndex+1); //最高电压电芯序号 + SDWA_Send_VAR(0x028B, bmsMem_slave.cellVoltageMinIndex+1); //最低电压电芯序号 + + //首页的状态显示and报警跳转 + if( ((bmsMem_slave.bStatus1 & 0x7e)==0) && ((bmsMem_slave.bStatus2 & 0x0f) ==0) && ((bmsMem_slave.bStatus3 & 0x18) ==0) && ((bmsMem_slave.temperaStatus & 0x3f) ==0) ) //无屏幕上的报警 + { + if( ((bmsMem_slave.bStatus1 & 0x01) != 0) && (bmsMem_slave.soc<99) ) //过压报警的判断：满电时发生[过压保护],屏幕不显示过压 + { + SDWA_Send_VAR(0x0100, 2); //“Fault”(过压报警) + + //从机报警的跳转 + if(bAlarmFlagOld_slave ==0) + { + bAlarmFlagOld_slave = 1; + SDWA_JumpToAlarm(); + } + + SDWA_ShowAlarm_Slave(); + } + else + { + if((bmsMem_slave.temperaStatus & 0x40) !=0) + { + SDWA_Send_VAR(0x0100, 5); //“RPSD_Activated”(急停) + } + else if((bmsMem_slave.bStatus2 & 0xe0) !=0) + { + SDWA_Send_VAR(0x0100, 2); //“Fault”(其他报警：放电MOS故障、充电MOS故障、预充失败) + } + else + { + if(bmsMem_slave.packCurrent > 100) + { + if((bmsMem.balanceStatus & 0x10) != 0) + { + SDWA_Send_VAR(0x0100, 7); //“CL-start”(限流) + } + else + { + SDWA_Send_VAR(0x0100, 0); //“Charge”(充电) + } + } + else if(bmsMem_slave.packCurrent < (-100)) + { + SDWA_Send_VAR(0x0100, 1); //“Discharge”(放电) + } + else + { + SDWA_Send_VAR(0x0100, 6); //“Standby”(待机) + } + } + + bAlarmFlagOld_slave = 0; + SDWA_ClearAlarm(); + } + } + else + { + SDWA_Send_VAR(0x0100, 2); //“Fault”(屏幕上的报警) + + //从机报警的跳转 + if(bAlarmFlagOld_slave ==0) + { + bAlarmFlagOld_slave = 1; + SDWA_JumpToAlarm(); + } + + SDWA_ShowAlarm_Slave(); + } + + //平衡状态 + if((bmsMem_slave.balanceStatus & 0x01) !=0) + { + SDWA_Send_VAR(0x0110, 0); //"On"(开启) + } + else + { + SDWA_Send_VAR(0x0110, 1); //"Off"(关闭) + } + + /**Wh版屏幕相关**/ + export_P = voltage*current/100; //当前消耗功率=总电压x总电流，单位1W=100*(0.1V*0.1A) + + remain_W = capacity*(3.2*bmsMem.ucCellNum)/1000; //剩余能量=当前总容量x额定电压，单位0.1kWh=1000*(0.1Ah*1V) + Ave_Temp = (bmsMem_slave.mcu_T1 + bmsMem_slave.mcu_T2 + bmsMem_slave.mcu_T3 + bmsMem_slave.mcu_T4)/4; + + SDWA_Send_VAR(0x0366,(export_P>>16) & 0xFFFF); //当前消耗功率，高16位 + SDWA_Send_VAR(0x0367, export_P & 0xFFFF); //当前消耗功率，低16位 + SDWA_Send_VAR(0x0361, remain_W); //剩余能量 + SDWA_Send_VAR(0x0364, Ave_Temp - 2731); //平均温度 + SDWA_Send_VAR(0x0365, bmsMem_slave.cycleCount); //循环次数 + + Progress = (voltage*current)/6000; //充放电进度条，100%对应6kW，1%对应0.06kW=6000*0.1V*0.1A + if(Progress>100) + { + Progress = 100; + } + else if(Progress<(-100)) + { + Progress = -100; + } + + if(bmsMem_slave.packCurrent > 100) //充电状态 + { + remain_T = (fcc - bmsMem_slave.rcc)/36000/current; //充电剩余时间=((额定总容量-当前总容量mAS)/36000)/总电流，单位0.1h=0.01Ah/0.1A + } + else if(bmsMem_slave.packCurrent < (-100)) //放电状态 + { + remain_T = bmsMem_slave.rcc/36000/(-current); //放电剩余时间=当前总容量mAS/36000/总电流，单位0.1h=0.01Ah/0.1A + } + + if(bmsMem_slave.packCurrent > 100) //充电状态 + { + SDWA_Send_VAR(0x05AA, 0); //放电进度条隐去 + SDWA_Send_VAR(0x05A9, Progress); //充电进度条 + + SDWA_Send_VAR(0x0362, remain_T); //充电剩余时间 + SDWA_Send_VAR(0x0377, 0); //充放电剩余时间挡条不显示 + } + else if(bmsMem_slave.packCurrent < (-100)) //放电状态 + { + SDWA_Send_VAR(0x05A9, 0); //充电进度条隐去 + SDWA_Send_VAR(0x05AA, -Progress); //放电进度条 + + SDWA_Send_VAR(0x0362, remain_T); //放电剩余时间 + SDWA_Send_VAR(0x0377, 0); //充放电剩余时间挡条不显示 + } + else //待机状态 + { + SDWA_Send_VAR(0x05A9, 0); //充电进度条隐去 + SDWA_Send_VAR(0x05AA, 0); //放电进度条隐去 + + SDWA_Send_VAR(0x0362, 0); //充放电剩余时间都为0 + SDWA_Send_VAR(0x0377, 1); //充放电剩余时间挡条显示 + } + /**Wh版屏幕相关**/ +} + +//更新屏幕数据，1s执行一次 +void SDWA_UpdateData(void) +{ + uint16_t scv,sct; //用于显示短路参数 + + /**** 时间显示 ****/ + if(LSEErrFlag==1) SDWA_Send_Blank(0x0020); + else SDWA_Send_Time(0x0020); //Time + + + /**** 汇总信息 ****/ + if(bmsMem.E2_485Addr == 1) + { + SDWA_Send_TotalInfo(); //无论并机还是单机，都对应canMem[0]的数据 + } + + + /**** 基本信息 ****/ + if((bmsMem.E2_485Addr != 1) || (scr_RdData_Index == 1)) //当前是从机或主机自身，一直显示自身数据 + { + SDWA_Send_Self_BasicInfo(); + } + else //当前是主机，可显示自身数据或所选从机数据 + { + SDWA_Send_Slave_BasicInfo(); + } + + + /**** 可显示图标的控制 ****/ + //报警记录的跳转按钮 + if((bmsMem.E2_485Addr != 1) || (scr_RdData_Index == 1)) + { + SDWA_Send_VAR(0x0346, 1); //图标显示 + } + else + { + SDWA_Send_VAR(0x0346, 0); //图标隐藏 + } + //主页返回总数据页的跳转按钮 + if(bmsMem.E2_485Addr == 1) + { + SDWA_Send_VAR(0x0345, 1); //图标显示 + } + else + { + SDWA_Send_VAR(0x0345, 0); //图标隐藏 + } + + + /**** 轮询在线从机页面 ****/ + if(scr_RdData_Index == 1) + { + uint8_t i; + + if(bAlarmFlag == 1) + { + SDWA_Send_VAR(0x0250, 2); //主机报警 + } + else + { + SDWA_Send_VAR(0x0250, 1); //主机一定在线 + } + + //从机 + for(i=2;i<=paraMem.PACK_NUM;i++) + { + if(canMem[i].com != 0) + { + //根据汇总的标志位来显示报警(任何保护都算，急停、MOS故障不在屏上也算报警) + if(canMem[i].soc<99) //在正常工作时，发生[总体/单体过压保护]，正常显示 + { + if( ((canMem[i].status_byte1 & 0x077f)!=0) || ((canMem[i].status_byte2 & 0x00ff) !=0) || ((canMem[i].status_byte3 & 0x0008) !=0) || ((canMem[i].status_byte4 & 0x0f7f) !=0) ) + { + SDWA_Send_VAR(0x0250+i-1, 2); + } + else + { + SDWA_Send_VAR(0x0250+i-1, 1); + } + } + else //在接近满电时,发生[总体/单体过压保护],则不会因此亮灯屏幕也不显示过压 + { + if( ((canMem[i].status_byte1 & 0x067e)!=0) || ((canMem[i].status_byte2 & 0x00ff) !=0) || ((canMem[i].status_byte3 & 0x0008) !=0) || ((canMem[i].status_byte4 & 0x0f7f) !=0) ) + { + SDWA_Send_VAR(0x0250+i-1, 2); + } + else + { + SDWA_Send_VAR(0x0250+i-1, 1); + } + } + } + else + { + SDWA_Send_VAR(0x0250+i-1, 0); + } + } + + //显示当前正在轮询还是正在分配 + #if Addr_SetAuto + if((assignAddr_State == 0) || (assignAddr_State == 1)) + { + SDWA_Send_VAR(0x01B3, 2 ); //分配 + } + else + #endif + if(ConfigData_Index == 1) //除了上位机读数据的其他时候 + { + SDWA_Send_VAR(0x01B3, 1 ); //轮询 + } + else + { + SDWA_Send_VAR(0x01B3, 0 ); //其他状态不显示 + } + } + + + /**** 参数显示 ****/ + //SN号，可上位机更新 + SDWA_Send_VER_PACKSN(0x02C0, &VersionMem.PACK_SN[0]);//数字和字母的组合，不含符号，最大15位 + SDWA_Send_VER_BMSSN(0x02CD, &VersionMem.BMS_SN[0]); //纯数字显示，只可9位 + //版本号，不可修改 + SDWA_Send_VER_SOFT(0x02DE, VersionMem.Software); //按照x.x.x.x来排布 + SDWA_Send_VER_HARD(0x02D6, VersionMem.Hardware); //按照x.x.x来排布 + SDWA_Send_VER_SCRN(0x02E9, VersionMem.Screen); //一共5位数，存放在1个字节里 + + //一屏多显，当前显示地址 + SDWA_Send_VAR(0x0240, scr_RdData_Index ); //当前显示数据地址 + + //报警记录个数和最新记录对应序号 + SDWA_Send_VAR(0x0130, soe.num ); //记录个数的显示 + if((soe.index == 0) || (soe.index%100 != 0)) //最新记录所在 + { + SDWA_Send_VAR(0x0131, soe.index%100 ); + } + else + { + SDWA_Send_VAR(0x0131, 100 ); + } + + //其他参数页面 +// SDWA_Send_VAR(0x01A0, language); //语言 + SDWA_Send_VAR(0x0209, paraMem.PACK_NUM ); //宁化时代4.16 增加显示并机总数 + + //系统校准页面 + SDWA_Send_VAR(0x0126, bmsMem.soc); //电量 + SDWA_Send_VAR(0x01AA, ncc_Ah); //额定容量 + + SDWA_Send_VAR(0x01A8, (bmsMem.packCurrent>>16) & 0xFFFF); + SDWA_Send_VAR(0x01A9, bmsMem.packCurrent & 0xFFFF); + SDWA_Send_VAR(0x01A1, (cali.current>>16) & 0xFFFF); + SDWA_Send_VAR(0x01A2, cali.current & 0xFFFF); + + //配置参数页面 + SDWA_Send_VAR(0x0145, 0); //参数修改成功 + SDWA_Send_VAR(0x0124, bmsMem.inverter_chgVolLimit ); + SDWA_Send_VAR(0x0212, bmsMem.inverter_dsgVolLimit ); + SDWA_Send_VAR(0x0213, bmsMem.inverter_chgCurLimit ); + SDWA_Send_VAR(0x0214, bmsMem.inverter_dsgCurLimit ); + + SDWA_Send_VAR(0x0215, bmsMem.mcu_occ ); + SDWA_Send_VAR(0x0216, bmsMem.mcu_ocd ); + SDWA_Send_VAR(0x0217, 5* (((bmsMem.ee_ovt_ldrt_ovh & 0x03)<<8) + bmsMem.ee_ovl) ); + SDWA_Send_VAR(0x0218, 20* bmsMem.ee_uv ); + SDWA_Send_VAR(0x0219, bmsMem.mcu_otc ); + SDWA_Send_VAR(0x021A, bmsMem.mcu_utc ); + SDWA_Send_VAR(0x021B, bmsMem.mcu_otd ); + SDWA_Send_VAR(0x021C, bmsMem.mcu_utd ); + + SDWA_Send_VAR(0x0227, 5* (((bmsMem.ee_uvt_ovrh & 0x03)<<8) + bmsMem.ee_ovrl) ); + SDWA_Send_VAR(0x0228, 20* bmsMem.ee_uvr ); + SDWA_Send_VAR(0x0229, bmsMem.mcu_otcr ); + SDWA_Send_VAR(0x022A, bmsMem.mcu_utcr ); + SDWA_Send_VAR(0x022B, bmsMem.mcu_otdr ); + SDWA_Send_VAR(0x022C, bmsMem.mcu_utdr ); + + SDWA_Send_VAR(0x0400, (paraMem.temp_disable & BIT0)>>0 ); //电池温度1失效 + SDWA_Send_VAR(0x0401, (paraMem.temp_disable & BIT1)>>1 ); //电池温度2失效 + SDWA_Send_VAR(0x0402, (paraMem.temp_disable & BIT2)>>2 ); //电池温度3失效 + SDWA_Send_VAR(0x0403, (paraMem.temp_disable & BIT3)>>3 ); //电池温度4失效 + + //短路参数 + scv = (bmsMem.ee_scv_sct & 0xF0)>>4; + if(scv == 0x0B) + { + scv = 400; + } + else + { + scv = 50 + 30 * scv; + } + sct = 0 + 64*(bmsMem.ee_scv_sct & 0x0F); + SDWA_Send_VAR(0x021D, scv); //短路保护电压 + SDWA_Send_VAR(0x021E, sct); //短路保护延时 + + + /**** 若之前在总数据页，而地址变化，跳回数据页 ****/ + if(bmsMem.E2_485Addr != 1) + { + if(sdwa_ExitTotal_Flg == 1) + { + sdwa_ExitTotal_Flg = 0; + SDWA_JumpToHome(); + } + } + + + /**** 屏幕修改地址的显示 ****/ + if(sdwa_WrAddr_Flg == 1) //主机改从机地址的显示 + { + //显示0，正在修改 + SDWA_Send_VAR(0x0210, 0 ); + } + else if(sdwa_WrAddr_Flg == 2) + { + //成功 + sdwa_WrAddr_Flg = 0; + canMem[scr_RdData_Index].com = 0; + canMem[sdwa_WrAddr].com = 1; + scr_RdData_Index = sdwa_WrAddr; + SDWA_Send_VAR(0x0210, scr_RdData_Index ); + } + else if(sdwa_WrAddr_Flg == 3) + { + //失败,显示原地址 + sdwa_WrAddr_Flg = 0; + SDWA_Send_VAR(0x0210, scr_RdData_Index ); + } + else + { + //正常 + if((bmsMem.E2_485Addr != 1) || (scr_RdData_Index == 1)) + { + SDWA_Send_VAR(0x0210, bmsMem.E2_485Addr ); + } + else + { + SDWA_Send_VAR(0x0210, scr_RdData_Index ); + } + } + + /**** 地址释放控制的打勾显示 ****/ + if(paraMem.addr_FREE_Flg == 1) + { + SDWA_Send_VAR(0x0294, 1); + } + else + { + SDWA_Send_VAR(0x0294, 0); + } + + + /**** 欠压保护恢复倒计时的显示 ****/ + if((bmsMem.balanceStatus & 0x20) != 0) + { + //正常情况下，在RTC时钟里计算 + if(LSEErrFlag == 0) + SDWA_Send_TimeCount(0x02A0,uvofftime); + //若RTC遇到问题，在定时器里计算 + else + SDWA_Send_TimeCount(0x02A0,uvoff_Moni_Count/100); + } + else + { + SDWA_Send_VAR(0x0290, 0); //按钮变黑 + + #if LTE_Conn + //4G常见状态 + if(LTEStatus_flg == 0) + { + if(LTE_WarmDelay > 0) + { + LTEStatus_flg = 1; + strcpy(LTEStatus_str, "wait 4G warm"); + } + else if(LTE_OTA_Flag == 1) //4G等待OTA升级 + { + LTEStatus_flg = 1; + strcpy(LTEStatus_str, "upgrade loading"); + } + else if(MQTT_READY_flag == 1) //4G已在正常工作流程 + { + LTEStatus_flg = 1; + strcpy(LTEStatus_str, "working"); + } + else if((LTE_rssi > 0) && (LTE_rssi <= 13)) //出现问题：弱网环境 + { + LTEStatus_flg = 1; + strcpy(LTEStatus_str, "weak grid"); + } + else if(LTE_Onlineflag == 0xAA) //出现问题：4G联网错误 + { + LTEStatus_flg = 1; + strcpy(LTEStatus_str, "network fault"); + } + } + else + { + if((LTE_Rx_BufIndex == 0) && (CRESET_flag == 0) && (MQTT_RST_flag == 0)) + { + strcat(LTEStatus_str, " Null"); + } + } + + if(LTEStatus_flg == 1) + { + LTEStatus_flg = 0; + SDWA_Send_Blank(0x02A0); //清除原有显示 + SDWA_Send_LTE(0x02A0); //船用带4G版，用屏幕显示当前4G在什么阶段 + } + else + { + SDWA_Send_Blank(0x02A0); //清除显示 + } + #else + SDWA_Send_Blank(0x02A0); //倒计时消失 + #endif + } + + + /**** 延时显示完成操作 ****/ + //初始化参数的显示 + if(initFlag != 0) + { + SDWA_Send_VAR(0x01A4, 2); //初始化成功 + initFlag++; + if(initFlag > 3) + { + initFlag = 0; + SDWA_Send_VAR(0x01A4, 0); //初始化按钮恢复正常 + } + } + + //零点校准按钮的显示 + if(scr_WrZero_Flg == 2) + { + scr_WrZero_Flg = 0; + SDWA_Send_VAR(0x012A, 0); + } + //增益校准按钮的显示 + if(scr_WrGain_Flg == 2) + { + scr_WrGain_Flg = 0; + SDWA_Send_VAR(0x012C, 0); + } + + //删除记录的显示 + if(clearFlag != 0) + { + SDWA_Send_VAR(0x0160, 0); + SDWA_Send_VAR(0x0143, 1); + clearFlag++; + + if(clearFlag > 3) + { + clearFlag = 0; + SDWA_Send_VAR(0x0143, 0); + + scr_RdRecord_Flg = 1;//因为会展示成功标识，需要刷新屏幕并重新读记录 + SCR_DispProcotol();//以更新报警页面 + } + } + + //清空EEPROM的显示 + if(EE_clearFlag != 0) + { + EE_clearFlag++; + if(EE_clearFlag > 3) //等待3s后按钮变白并执行软件复位 + { + EE_clearFlag = 0; + SDWA_Send_VAR(0x0152, 0); + + delay_ms(1000); + NVIC_SystemReset(); //软件复位，参数恢复默认 + } + } +} + + +/**接收屏幕报文的函数**/ +//USART2中断接收 +//如果在向外发送时，接收数据会怎么样？ +void SDWA_IT_Receive(void) +{ + //接收数据 + sdwaBuf[sdwaBufIndex] = USART_ReceiveData(USART2); + sdwaBufIndex++; + + //防止数组溢出 + if(sdwaBufIndex >= 19 ) + { + sdwaBufIndex = 0; + } + + sdwaMoniCount = 10; +} + +//一定时间没有接收到数据，初始化MODBUS通讯 +void SDWA_TIM_Moni(void) +{ + if(sdwaMoniCount!= 0xff) + { + sdwaMoniCount--; + } + + if(sdwaMoniCount == 0) + { + sdwaMoniCount = 0xff; + sdwaRecvFlag = 1; + } +} + +//SDWA写入数据：485地址、密码、协议选择、报警记录删除 +void SDWA_RecvData(void) +{ + uint8_t tmpWr[2]; + uint8_t tmpRd[2]; + + uint16_t tmp; //屏幕参数相关 + int16_t tmp_T;//温度是有符号型 + uint8_t flashUpdateFlag = 0; //1:不需要算校验位 2:需要算校验位 3:初始化参数，也要算校验位 + + uint8_t protocol_Index; //屏幕写入增多，加一层判断以减少写入协议选择的次数 + protocol_Index = protocol; + + + if(sdwaRecvFlag == 1) + { + sdwaRecvFlag = 0; + + if((sdwaBuf[0] == 0xA5) && (sdwaBuf[1] == 0x5A)) + { + /**语言和地址设置**/ +// //语言 +// //A5 5A 06 83 01 27 01 00 00/01[中文/英文] +// if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x01) && (sdwaBuf[5]==0x27)) +// { +// tmpWr[0] = sdwaBuf[8]; +// EEPROM_WrMulByte(EE_LANG,&tmpWr[0]); +// delay_ms(5); +// EEPROM_RdMulByte(EE_LANG,&tmpRd[0]); +// language = tmpRd[0]; +// SDWA_Send_VAR(0x01A0, language); +// +// if((bmsMem.E2_485Addr != 1) || (scr_RdData_Index == 1)) //主机的地址和语言设置页 +// { +// if(language == 0) +// { +// SDWA_JumpToNumber(27); +// } +// else if(language == 1) +// { +// SDWA_JumpToNumber(51); +// } +// } +// else //从机的地址和语言设置页 +// { +// if(language == 0) +// { +// SDWA_JumpToNumber(15); +// } +// else if(language == 1) +// { +// SDWA_JumpToNumber(36); +// } +// } +// } + + //地址 + //A5 5A 06 83 02 10 01 00 addr + if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x02) && (sdwaBuf[5]==0x10)) + { + if((sdwaBuf[8]>=1) && (sdwaBuf[8]<=AddrMax)) //范围判断 + { + if(bmsMem.E2_485Addr == 1) //作为主机 + { + if((scr_RdData_Index>=2) && (scr_RdData_Index<=paraMem.PACK_NUM)) //想修改从机地址 + { + if((sdwaBuf[8] != 1) && (sdwaBuf[8] <= paraMem.PACK_NUM)) //（不能修改成1） //宁化时代.不能修改到高于并机总数 + { + sdwa_WrAddr = sdwaBuf[8]; + + SDWA_Send_VAR(0x0210, 0 ); //正在修改，显示0 + sdwa_WrAddr_Flg = 1; + } + } + else //修改主机地址 + { + if(paraMem.addr_FREE_Flg != 0) + { + tmpWr[0] = sdwaBuf[8]; + EEPROM_WrMulByte(EE_ADDR,&tmpWr[0]); + delay_ms(5); + EEPROM_RdMulByte(EE_ADDR,&tmpRd[0]); + bmsMem.E2_485Addr = tmpRd[0]; + SDWA_Send_VAR(0x0210, bmsMem.E2_485Addr ); + + tmpWr[0] = 0; + tmpWr[1] = 0; + bmsMem.can_ArrayIndex = 0; + EEPROM_WrMulByte(EE_ASSIGN,tmpWr); + delay_ms(5); + + scr_RdData_Index = bmsMem.E2_485Addr; + } + } + } + else //作为从机 + { + if(paraMem.addr_FREE_Flg != 0) + { + tmpWr[0] = sdwaBuf[8]; + EEPROM_WrMulByte(EE_ADDR,&tmpWr[0]); + delay_ms(5); + EEPROM_RdMulByte(EE_ADDR,&tmpRd[0]); + bmsMem.E2_485Addr = tmpRd[0]; + SDWA_Send_VAR(0x0210, bmsMem.E2_485Addr ); + + tmpWr[0] = 0; + tmpWr[1] = 0; + bmsMem.can_ArrayIndex = 0; + EEPROM_WrMulByte(EE_ASSIGN,tmpWr); + delay_ms(5); + + scr_RdData_Index = bmsMem.E2_485Addr; + } + else + { + if(sdwaBuf[8] != 1) //（不能修改成1） + { + bmsMem.E2_485Addr = sdwaBuf[8]; + SDWA_Send_VAR(0x0210, bmsMem.E2_485Addr ); + + scr_RdData_Index = bmsMem.E2_485Addr; + } + } + } + } + } + + //并机总个数 + //A5 5A 06 83 02 09 01 00 num + if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x02) && (sdwaBuf[5]==0x09)) + { + if((sdwaBuf[8]>=1) && (sdwaBuf[8]<=AddrMax)) //范围判断 + { + //更新并机总个数 + paraMem.PACK_NUM = sdwaBuf[8]; + SDWA_Send_VAR(0x0209, paraMem.PACK_NUM ); + + flashUpdateFlag = 1; + + //地址若溢出，变为1，初始化自动分配状态 //宁化时代.原则上应该只有主机能通过屏幕修改此值，所以该判断暂时保留 + if(bmsMem.E2_485Addr > paraMem.PACK_NUM) + { + #if Addr_SetAuto + assignAddr_State = 0; + assignAddr_relay = 2;//变1后也有可能变回去 + + bmsMem.can_ArrayIndex = 0; + tmpWr[0] = 0; + tmpWr[1] = 0; + EEPROM_WrMulByte(EE_ASSIGN,tmpWr); + delay_ms(5); + #endif + + bmsMem.E2_485Addr = 1; + scr_RdData_Index = bmsMem.E2_485Addr; + + tmpWr[0] = bmsMem.E2_485Addr; + EEPROM_WrMulByte(EE_ADDR,&tmpWr[0]); + delay_ms(5); + + MODBUS_Init(); + } + } + } + + + /**页面跳转**/ + //密码跳转设置页[0x07BD=1981] + //接收界面密码指令: A5 5A 06 83 01 20 01 07 BD + //跳转设置界面指令: A5 5A 04 80 03 00 05 + if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x01) && (sdwaBuf[5]==0x20) && (sdwaBuf[7]==0x07) && (sdwaBuf[8]==0xBD)) + { + if((bmsMem.E2_485Addr != 1) || (scr_RdData_Index == 1)) //进入设置菜单 + { +// if(language == 0) +// { + SDWA_JumpToNumber(5); +// } +// else if(language == 1) +// { +// SDWA_JumpToNumber(42); +// } + } + else //主机看从机时，只能进入地址和语言设置页 + { +// if(language == 0) +// { + SDWA_JumpToNumber(15); +// } +// else if(language == 1) +// { +// SDWA_JumpToNumber(36); +// } + } + } + //密码跳转限制参数页[0x07C3=1987] + //接收界面密码指令: A5 5A 06 83 01 AD 01 07 C3 + //跳转参数界面指令: A5 5A 04 80 03 00 0A + if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x01) && (sdwaBuf[5]==0xAD) && (sdwaBuf[7]==0x07) && (sdwaBuf[8]==0xC3)) + { +// if(language == 0) +// { + SDWA_JumpToNumber(10); +// } +// else if(language == 1) +// { +// SDWA_JumpToNumber(45); +// } + } + //密码跳转保护参数页[0x07C3=1987] + //接收界面密码指令: A5 5A 06 83 01 AE 01 07 C3 + //跳转参数界面指令: A5 5A 04 80 03 00 0A + if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x01) && (sdwaBuf[5]==0xAE) && (sdwaBuf[7]==0x07) && (sdwaBuf[8]==0xC3)) + { +// if(language == 0) +// { + SDWA_JumpToNumber(12); +// } +// else if(language == 1) +// { +// SDWA_JumpToNumber(31); +// } + } + + //息屏跳转首页 + //进入睡眠模式，此时不能有任何数据传来: A5 5A 04 81 01 01 00 + //退出睡眠模式会自动发送：A5 5A 04 81 01 01 40 + //跳转主页界面指令: A5 5A 04 80 03 00 01 + if((sdwaBuf[2]==0x04) && (sdwaBuf[3]==0x81) && (sdwaBuf[6]==0x00)) //屏幕息屏，数据停止发送 + { + sdwa_sleep_flag = 1; + + sdwa_ExitTotal_Flg = 0; //不需要主动退出总数据页，因为亮屏自会跳转 + scr_RdData_Index = bmsMem.E2_485Addr; //为了不影响轮询，地址返回原值 + } + else if((sdwaBuf[2]==0x04) && (sdwaBuf[3]==0x81) && ( (sdwaBuf[6]>=0x20) && (sdwaBuf[6]<=0x40) )) //摁亮退出息屏，数据正常发送 + { + sdwa_sleep_flag = 0; + + SDWA_JumpToHome(); + } + + //主页跳转报警记录页面——只能看自身的报警记录，主机看从机不显示 + if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x02) && (sdwaBuf[5]==0x71)) + { + if((bmsMem.E2_485Addr != 1) || (scr_RdData_Index == 1)) + { + scr_RdRecord_Flg = 1; +// if(language == 0) +// { + SDWA_JumpToNumber(28); +// } +// else if(language == 1) +// { +// SDWA_JumpToNumber(35); +// } + } + } + + //主页跳转轮询页——只有主机可用；先将显示序号置1恢复轮询，然后跳转 + if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x02) && (sdwaBuf[5]==0x70)) + { + if(bmsMem.E2_485Addr == 1) + { + scr_RdData_Index = 1; + sdwa_ExitTotal_Flg = 1;//可能要进行跳转 + + //不论语言，轮询页都是这一页 + SDWA_JumpToNumber(13); + } + } + + //轮询页跳转总数据页——根据语言选择不同跳转页 + if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x01) && (sdwaBuf[5]==0xA6)) + { +// if(language == 0) +// { + SDWA_JumpToNumber(23); +// } +// else if(language == 1) +// { +// SDWA_JumpToNumber(48); +// } + } + + //自身/主看从机的设置页跳转返回——自身都是返回上级菜单，主机看从机是返回主页 + if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x01) && (sdwaBuf[5]==0xAC)) + { + if((bmsMem.E2_485Addr != 1) || (scr_RdData_Index == 1)) //进入设置菜单 + { +// if(language == 0) +// { + SDWA_JumpToNumber(5); +// } +// else if(language == 1) +// { +// SDWA_JumpToNumber(42); +// } + } + else //主机看从机时，直接返回主页 + { + SDWA_JumpToHome(); + } + } + + + /**参数改动**/ + //系统值修改 + //SOC：A5 5A 06 83 01 26 01 00 soc + if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x01) && (sdwaBuf[5]==0x26)) + { + if(((int)sdwaBuf[8]>=0) && (sdwaBuf[8]<=100)) //范围判断 + { + tmpWr[0] = sdwaBuf[8]; + + EEPROM_WrMulByte(EE_SOC,&tmpWr[0]); + delay_ms(5); + + //赋值SOC + EEPROM_RdMulByte(EE_SOC,&tmpRd[0]); + bmsMem.soc = tmpRd[0]; + SDWA_Send_VAR(0x0126, bmsMem.soc); + + //赋值剩余容量=满充容量*新的SOC + bmsMem.rcc = fcc/100 * bmsMem.soc; + rcc_Ah = fcc_Ah * bmsMem.soc / 100; + oldrcc_Ah = rcc_Ah; + + //在满放满充过程中，修改SOC会影响效果，不再执行 + if(fcc_CaliStartFlag == 1) + { + fcc_CaliStartFlag = 0; + if(LSEErrFlag == 0) + { + EEPROM_WrMulByte(EE_FCC_TIME,ClearEE); + delay_ms(5); + } + } + } + } + //额定容量：A5 5A 06 83 01 AA 01 00 capacity + if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x01) && (sdwaBuf[5]==0xAA)) + { + tmp = sdwaBuf[7]<<8 | sdwaBuf[8]; + + if((tmp>0) && (tmp<=1000)) //范围判断 + { + tmpWr[0] = sdwaBuf[7]; + tmpWr[1] = sdwaBuf[8]; + EEPROM_WrMulByte(EE_NCC,tmpWr); + delay_ms(5); + + //赋值额定容量 + EEPROM_RdMulByte(EE_NCC,tmpRd); + ncc_Ah = tmpRd[0]<<8 | tmpRd[1]; + bmsMem.ncc = 3600 * 1000 * ncc_Ah; + SDWA_Send_VAR(0x01AA, ncc_Ah); + + //赋值满充容量=额定容量 + fcc = bmsMem.ncc; + fcc_Ah = ncc_Ah; + tmpWrFCC[0] = (fcc>>24) & 0xff; + tmpWrFCC[1] = (fcc>>16) & 0xff; + tmpWrFCC[2] = (fcc>> 8) & 0xff; + tmpWrFCC[3] = (fcc>> 0) & 0xff; + tmpWrFCC[4] = tmpWrFCC[0] ^ 0xff; + tmpWrFCC[5] = tmpWrFCC[1] ^ 0xff; + tmpWrFCC[6] = tmpWrFCC[2] ^ 0xff; + tmpWrFCC[7] = tmpWrFCC[3] ^ 0xff; + EEPROM_WrMulByte(EE_FCC,tmpWrFCC); + delay_ms(20); + + //赋值剩余容量=新的满充容量*SOC + bmsMem.rcc = fcc/100 * bmsMem.soc; + rcc_Ah = fcc_Ah * bmsMem.soc / 100; + oldrcc_Ah = rcc_Ah; + + //改额定容量不影响此前的满放满充过程 + } + } + //增益校准系数：A5 5A 08 83 01 A1 02 dataHH dataHL dataLH dataLL + if((sdwaBuf[2]==0x08) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x01) && (sdwaBuf[5]==0xA1)) + { + cali.current = sdwaBuf[7]<<24 | sdwaBuf[8]<<16 | sdwaBuf[9]<<8 | sdwaBuf[10]; + } + //零点校准：A5 5A 06 83 01 2B 01 00 01 + if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x01) && (sdwaBuf[5]==0x2B)) + { + scr_WrZero_Flg = 1; + cali.cmdZero = 1; + SDWA_Send_VAR(0x012A, 1); + } + //增益校准：A5 5A 06 83 01 2D 01 00 01 + if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x01) && (sdwaBuf[5]==0x2D)) + { + scr_WrGain_Flg = 1; + cali.cmdGain = 1; + SDWA_Send_VAR(0x012C, 1); + } + + //配置参数修改 + //恢复默认参数——150A参数 + //Default按钮：A5 5A 06 83 01 A5 01 00 01 + if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x01) && (sdwaBuf[5]==0xA5)) + { + //P1 + bmsMem.ee_scv_sct = 0x10; //80mV 0us + bmsMem.inverter_chgVolLimit = 576; //57.6V + bmsMem.inverter_dsgVolLimit = 480; //48.0V + bmsMem.inverter_chgCurLimit = paraMem.alarm_occ * 10 - 100; //充电过流告警-10A + bmsMem.inverter_dsgCurLimit = paraMem.alarm_ocd1 * 10 - 100; //放电过流告警-10A + //P2 + bmsMem.ee_ocd1v_ocd1t = (bmsMem.ee_ocd1v_ocd1t & 0x0F) | 0x10; //30mV + bmsMem.ee_ocd2v_ocd2t = (bmsMem.ee_ocd2v_ocd2t & 0x0F) | 0x10; //40mV + bmsMem.ee_occv_occt = (bmsMem.ee_occv_occt & 0x0F) | 0x10; //30mV + bmsMem.mcu_occ = 0x9B; //充电过流 155A + bmsMem.mcu_ocd = 0x9B; //放电过流 155A + bmsMem.ee_ovt_ldrt_ovh = (bmsMem.ee_ovt_ldrt_ovh & 0xFC) | 0x02; + bmsMem.ee_ovl = 0xD0; //过压保护电压 0x2D0*5=3600mV + bmsMem.ee_uvt_ovrh = (bmsMem.ee_uvt_ovrh & 0xFC) | 0x02; + bmsMem.ee_ovrl = 0xA8; //过压保护释放 0x2A8*5=3400mV + bmsMem.ee_uv = 0x87; //欠压保护电压 0x87*20=2700mV + bmsMem.ee_uvr = 0x91; //欠压保护释放 0x91*20=2900mV + //P3 + bmsMem.mcu_otc = 0x3C; //充电高温 60 + bmsMem.mcu_otcr = 0x37; //充电高温释放 55 + bmsMem.mcu_utc = 0x00; //充电低温 0 + bmsMem.mcu_utcr = 0x05; //充电低温释放 5 + bmsMem.mcu_otd = 0x41; //放电高温 65 + bmsMem.mcu_otdr = 0x3C; //放电高温释放 60 + bmsMem.mcu_utd = 0xEC; //放电低温 -20 + bmsMem.mcu_utdr = 0xF1; //放电低温释放 -15 + + SDWA_Send_VAR(0x01A4, 1); //初始化按钮变化颜色 + flashUpdateFlag = 3; + } + //单个参数作用的 + //修改短路电压：A5 5A 06 83 03 50 01 00 data + if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x01) && (sdwaBuf[5]==0x22)) + { + tmp = sdwaBuf[8]; + + if(tmp <= 0x0F) //范围：0x00~0x0F + { + bmsMem.ee_scv_sct = (bmsMem.ee_scv_sct & 0x0F) + (tmp<<4); + flashUpdateFlag = 2; + } + } + //修改短路延时：A5 5A 06 83 03 60 01 00 data + if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x01) && (sdwaBuf[5]==0x23)) + { + tmp = sdwaBuf[8]; + + if(tmp <= 0x0F) //范围：0x00~0x0F + { + bmsMem.ee_scv_sct = (bmsMem.ee_scv_sct & 0xF0) + tmp; + flashUpdateFlag = 2; + } + } + //修改逆变器充电限压：A5 5A 06 83 02 11 01 dataH dataL + if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x01) && (sdwaBuf[5]==0x24)) + { + tmp = sdwaBuf[7]<<8 | sdwaBuf[8]; + + if((tmp>=540) && (tmp<=580)) //范围：54~58V，单位0.1V + { + bmsMem.inverter_chgVolLimit = tmp; + flashUpdateFlag = 1; + } + } + //修改逆变器放电限压：A5 5A 06 83 02 12 11 dataH dataL + if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x02) && (sdwaBuf[5]==0x12)) + { + tmp = sdwaBuf[7]<<8 | sdwaBuf[8]; + bmsMem.inverter_dsgVolLimit = tmp; //(暂无范围) + flashUpdateFlag = 1; + } + //修改逆变器充电限流：A5 5A 06 83 02 13 01 dataH dataL + if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x02) && (sdwaBuf[5]==0x13)) + { + tmp = sdwaBuf[7]<<8 | sdwaBuf[8]; + bmsMem.inverter_chgCurLimit = tmp; //(暂无范围) + flashUpdateFlag = 1; + } + //修改逆变器放电限流：A5 5A 06 83 02 14 01 dataH dataL + if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x02) && (sdwaBuf[5]==0x14)) + { + tmp = sdwaBuf[7]<<8 | sdwaBuf[8]; + bmsMem.inverter_dsgCurLimit = tmp; //(暂无范围) + flashUpdateFlag = 1; + } + //修改充电过流值：A5 5A 06 83 02 15 01 dataH dataL + if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x02) && (sdwaBuf[5]==0x15)) + { + tmp = sdwaBuf[7]<<8 | sdwaBuf[8]; + + if(tmp <= 0xFF) //范围：0x00~0xFF + { + bmsMem.mcu_occ = tmp; + flashUpdateFlag = 2; + } + } + //修改放电过流值：A5 5A 06 83 02 16 01 dataH dataL + if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x02) && (sdwaBuf[5]==0x16)) + { + tmp = sdwaBuf[7]<<8 | sdwaBuf[8]; + + if(tmp <= 0xFF) //范围：0x00~0xFF + { + bmsMem.mcu_ocd = tmp; + flashUpdateFlag = 2; + } + } + //保护和释放参数一起作用的 + //修改单体过压值：A5 5A 06 83 02 17 01 dataH dataL + if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x02) && (sdwaBuf[5]==0x17)) + { + //单体过压 + tmp = sdwaBuf[7]<<8 | sdwaBuf[8]; + tmp = tmp/5; + + if((tmp <= 0x03FF) && (tmp >= 0x0029)) //范围：0x0029~0x03FF(考虑到释放值最小1，这里最小1+200/5) + { + bmsMem.ee_ovt_ldrt_ovh &= 0xfc;//~0x03 + bmsMem.ee_ovt_ldrt_ovh += (tmp & 0x0300) >>8; + bmsMem.ee_ovl = tmp & 0x00ff; + + //单体过压释放=-200mV + tmp = tmp-200/5; + bmsMem.ee_uvt_ovrh &= 0xfc;//~0x03 + bmsMem.ee_uvt_ovrh += (tmp & 0x0300) >>8; + bmsMem.ee_ovrl = tmp & 0x00ff; + + flashUpdateFlag = 2; + } + } + //修改单体过压释放值：A5 5A 06 83 02 17 01 dataH dataL + if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x02) && (sdwaBuf[5]==0x27)) + { + tmp = sdwaBuf[7]<<8 | sdwaBuf[8]; + tmp = tmp/5; + + if((tmp < ((bmsMem.ee_ovt_ldrt_ovh & 0x03)<<8 | bmsMem.ee_ovl)) && (tmp > 0)) //不超过保护值才能写入，范围：0x0001~0x03FF(如果是0会有问题) + { + bmsMem.ee_uvt_ovrh &= 0xfc;//~0x03 + bmsMem.ee_uvt_ovrh += (tmp & 0x0300) >>8; + bmsMem.ee_ovrl = tmp & 0x00ff; + + flashUpdateFlag = 2; + } + } + //修改单体欠压值：A5 5A 06 83 02 18 01 dataH dataL + if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x02) && (sdwaBuf[5]==0x18)) + { + //单体欠压 + tmp = sdwaBuf[7]<<8 | sdwaBuf[8]; + tmp = tmp/20; + + if(tmp <= 0xF4) //范围：0x00~0xF4(考虑到释放值最大0xFE，这里0xFE-200/20) + { + bmsMem.ee_uv = tmp; + + //单体欠压释放=+200mV + tmp = tmp+200/20; + bmsMem.ee_uvr = tmp; + + flashUpdateFlag = 2; + } + } + //修改单体欠压释放值：A5 5A 06 83 02 18 01 dataH dataL + if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x02) && (sdwaBuf[5]==0x28)) + { + tmp = sdwaBuf[7]<<8 | sdwaBuf[8]; + tmp = tmp/20; + + if((tmp > bmsMem.ee_uv) && (tmp < 0xFF)) //不超过保护值才能写入，范围：0x00~0xFE(如果是0xff会有问题) + { + bmsMem.ee_uvr = tmp; + flashUpdateFlag = 2; + } + } + //修改充电高温保护值：A5 5A 06 83 02 19 01 dataH dataL + if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x02) && (sdwaBuf[5]==0x19)) + { + //充电高温 + tmp_T = sdwaBuf[7]<<8 | sdwaBuf[8]; + + if((tmp_T >= -118) && (tmp_T <= 127)) //范围：-118~127(考虑到释放值最小-128，这里-128+10) + { + bmsMem.mcu_otc = tmp_T; + + //充电高温释放=-10℃ + tmp_T = tmp_T-10; + bmsMem.mcu_otcr = tmp_T; + + flashUpdateFlag = 2; + } + } + //修改充电高温保护释放值：A5 5A 06 83 02 19 01 dataH dataL + if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x02) && (sdwaBuf[5]==0x29)) + { + tmp_T = sdwaBuf[7]<<8 | sdwaBuf[8]; + + if((tmp_T >= -128) && (tmp_T < bmsMem.mcu_otc)) //不超过保护值才能写入，范围：-128~127 + { + bmsMem.mcu_otcr = tmp_T; + flashUpdateFlag = 2; + } + } + //修改充电低温保护值：A5 5A 06 83 02 1A 01 dataH dataL + if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x02) && (sdwaBuf[5]==0x1A)) + { + //充电低温 + tmp_T = sdwaBuf[7]<<8 | sdwaBuf[8]; + + if((tmp_T >= -128) && (tmp_T <= 124)) //范围：-128~124(考虑到释放值最大127，这里127-3) + { + bmsMem.mcu_utc = tmp_T; + + //充电低温释放=+3℃ + tmp_T = tmp_T+3; + bmsMem.mcu_utcr = tmp_T; + + flashUpdateFlag = 2; + } + } + //修改充电低温保护释放值：A5 5A 06 83 02 1A 01 dataH dataL + if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x02) && (sdwaBuf[5]==0x2A)) + { + tmp_T = sdwaBuf[7]<<8 | sdwaBuf[8]; + + if((tmp_T > bmsMem.mcu_utc) && (tmp_T <= 127)) //不超过保护值才能写入，范围：-128~127 + { + bmsMem.mcu_utcr = tmp_T; + flashUpdateFlag = 2; + } + } + //修改放电高温保护值：A5 5A 06 83 02 1B 01 dataH dataL + if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x02) && (sdwaBuf[5]==0x1B)) + { + //放电高温 + tmp_T = sdwaBuf[7]<<8 | sdwaBuf[8]; + + if((tmp_T >= -118) && (tmp_T <= 127)) //范围：-118~127(考虑到释放值最小-128，这里-128+10) + { + bmsMem.mcu_otd = tmp_T; + + //放电高温释放=-10℃ + tmp_T = tmp_T-10; + bmsMem.mcu_otdr = tmp_T; + + flashUpdateFlag = 2; + } + } + //修改放电高温保护释放值：A5 5A 06 83 02 1B 01 dataH dataL + if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x02) && (sdwaBuf[5]==0x2B)) + { + tmp_T = sdwaBuf[7]<<8 | sdwaBuf[8]; + + if((tmp_T >= -128) && (tmp_T < bmsMem.mcu_otd)) //不超过保护值才能写入，范围：-128~127 + { + bmsMem.mcu_otdr = tmp_T; + flashUpdateFlag = 2; + } + } + //修改放电低温保护值：A5 5A 06 83 02 1C 01 dataH dataL + if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x02) && (sdwaBuf[5]==0x1C)) + { + //放电低温 + tmp_T = sdwaBuf[7]<<8 | sdwaBuf[8]; + + if((tmp_T >= -128) && (tmp_T <= 124)) //范围：-128~124(考虑到释放值最大127，这里127-3) + { + bmsMem.mcu_utd = tmp_T; + + //放电低温释放=+3℃ + tmp_T = tmp_T+3; + bmsMem.mcu_utdr = tmp_T; + + flashUpdateFlag = 2; + } + } + //修改放电低温保护释放值：A5 5A 06 83 02 1C 01 dataH dataL + if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x02) && (sdwaBuf[5]==0x2C)) + { + tmp_T = sdwaBuf[7]<<8 | sdwaBuf[8]; + + if((tmp_T > bmsMem.mcu_utd) && (tmp_T <= 127)) //不超过保护值才能写入，范围：-128~127 + { + bmsMem.mcu_utdr = tmp_T; + flashUpdateFlag = 2; + } + } + + + /**功能按钮**/ + //释放地址限制的按钮 + if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x02) && (sdwaBuf[5]==0x95)) + { + if(paraMem.addr_FREE_Flg != 1) + { + paraMem.addr_FREE_Flg = 1; + SDWA_Send_VAR(0x0294, 1); + + //若改为手动控制，则及时将当前地址写入EEPROM + tmpWr[0] = bmsMem.E2_485Addr; + EEPROM_WrMulByte(EE_ADDR,&tmpWr[0]); + delay_ms(5); + } + else + { + paraMem.addr_FREE_Flg = 0; + SDWA_Send_VAR(0x0294, 0); + } + + flashUpdateFlag = 1; + } + + //欠压强制复位按钮 + if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x02) && (sdwaBuf[5]==0x91)) + { + SDWA_Send_VAR(0x0290, 1); //按钮变黄 + + //当前总体和单体欠压的报警/保护位都置0 + bmsMem.bStatus1 &= ~0x0202; + bmsMem.bStatus3 &= ~0x0A00; + //状态位置1，更新计时起点 + bmsMem.balanceStatus |= 0x0020; + if(LSEErrFlag!=1) + { + uvofftimecount = RTC_GetCounter(); + uvofftime = 300; + } + else + { + uvoff_Moni_Count = UVOff_MON_CNT; + } + + SDWA_Send_VAR(0x0290, 2); //按钮变红 + } + + //温度失效开关_T1 + if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x04) && (sdwaBuf[5]==0x10)) + { + if((paraMem.temp_disable & BIT0) == 0) + { + paraMem.temp_disable |= BIT0; + } + else + { + paraMem.temp_disable &= ~BIT0; + } + flashUpdateFlag = 1; + } + //温度失效开关_T2 + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x04) && (sdwaBuf[5]==0x11)) + { + if((paraMem.temp_disable & BIT1) == 0) + { + paraMem.temp_disable |= BIT1; + } + else + { + paraMem.temp_disable &= ~BIT1; + } + flashUpdateFlag = 1; + } + //温度失效开关_T3 + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x04) && (sdwaBuf[5]==0x12)) + { + if((paraMem.temp_disable & BIT2) == 0) + { + paraMem.temp_disable |= BIT2; + } + else + { + paraMem.temp_disable &= ~BIT2; + } + flashUpdateFlag = 1; + } + //温度失效开关_T4 + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x04) && (sdwaBuf[5]==0x13)) + { + if((paraMem.temp_disable & BIT3) == 0) + { + paraMem.temp_disable |= BIT3; + } + else + { + paraMem.temp_disable &= ~BIT3; + } + flashUpdateFlag = 1; + } + + //删除记录按钮 + if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x01) && (sdwaBuf[5]==0x70)) //当按钮按下 + { + uint16_t i; + uint16_t pc; //待写入地址 + uint8_t adrh,adrl; + uint8_t wrBuf[64]; + + SDWA_Send_VAR(0x0160, 1); + + if(soe.num != 0) //存在记录，才去删除记录 + { + //先清空具体内容 + pc = 0x1000; + for(i=0;i<64;i++) + { + wrBuf[i] = 0xff; + } + for(i=0;i<100;i++) + { + adrh = (pc>>8) & 0xff; + adrl = pc & 0xff; + EEPROM_WrMulByte(EE_SOE,wrBuf); + delay_ms(10); + + pc += 0x40; + } + + //再清空统计数据 + soe.index = 0; //起始序号0 + soe.pc = 0x1000; //起始地址0x1000 + soe.num = 0; //起始数量0 + + wrBuf[0] = (soe.index >> 24) & 0xff ; + wrBuf[1] = (soe.index >> 16) & 0xff ; + wrBuf[2] = (soe.index >> 8) & 0xff ; + wrBuf[3] = (soe.index >> 0) & 0xff ; + wrBuf[4] = (soe.pc >>8)&0xFF ; + wrBuf[5] = soe.pc & 0xff ; + wrBuf[6] = (soe.num >>8)&0xFF ; + wrBuf[7] = soe.num & 0xff ; + + EEPROM_WrMulByte(EE_SOE_INF,wrBuf); + delay_ms(10); + } + + read_index = 0; + clearFlag = 1; + } + + //读取记录按钮——上下按键选择读取的地址 + if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x01) && (sdwaBuf[5]==0x50) && (sdwaBuf[6]==0x01)) + { + if(read_index > 0) + { + scr_RdRecord_Flg = 1; + read_index -= 3; //对应序号 + } + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x01) && (sdwaBuf[5]==0x51) && (sdwaBuf[6]==0x01)) + { + if(read_index < 99) + { + scr_RdRecord_Flg = 1; + read_index += 3; //对应序号 + } + } + + //初始化EEPROM按钮——地址范围0x0200~0x03FF(出厂前刷新内容) + if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x01) && (sdwaBuf[5]==0x53)) //当按钮按下 + { + uint16_t i; + uint16_t pc; //待写入地址 + uint8_t adrh,adrl; + uint8_t wrBuf[64]; + + SDWA_Send_VAR(0x0152, 1); //按钮变黄，正在执行 + + //485地址、IAP标志存在0x0000~0x01FF中，不更改 + //电流校准值，已在初始化时进行判断转移，不再操作 + + //清空EEPROM地址0x0200-0x03FF，存放如容量和SOC一类参数 + pc = 0x0200; + for(i=0;i<64;i++) + { + wrBuf[i] = 0xff; + } + for(i=0;i<8;i++) + { + adrh = (pc>>8) & 0xff; + adrl = pc & 0xff; + EEPROM_WrMulByte(EE_CLEAR,wrBuf); + delay_ms(10); + + pc += 0x40; + } + + EE_clearFlag = 1; // + } + + + /**轮询页的选择——主机1肯定可选，其他要看是否在线**/ + if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x02) && (sdwaBuf[5]==0x60)) + { + scr_RdData_Index = 1; + sdwa_ExitTotal_Flg = 0; //自己跳回了首页，那就不需要再跳转 + SDWA_Send_VAR(0x0240, scr_RdData_Index ); + + SDWA_JumpToHome(); + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x02) && (sdwaBuf[5]==0x61)) + { + if((canMem[2].com != 0) && (ConfigData_Index == 1)) //对应从机在线且上位机不在询问从机 + { + scr_RdData_Index = 2; + SDWA_Send_VAR(0x0240, scr_RdData_Index ); + + SDWA_JumpToHome(); + } + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x02) && (sdwaBuf[5]==0x62)) + { + if((canMem[3].com != 0) && (ConfigData_Index == 1)) //对应从机在线且上位机不在询问从机 + { + scr_RdData_Index = 3; + SDWA_Send_VAR(0x0240, scr_RdData_Index ); + + SDWA_JumpToHome(); + } + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x02) && (sdwaBuf[5]==0x63)) + { + if((canMem[4].com != 0) && (ConfigData_Index == 1)) //对应从机在线且上位机不在询问从机 + { + scr_RdData_Index = 4; + SDWA_Send_VAR(0x0240, scr_RdData_Index ); + + SDWA_JumpToHome(); + } + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x02) && (sdwaBuf[5]==0x64)) + { + if((canMem[5].com != 0) && (ConfigData_Index == 1)) //对应从机在线且上位机不在询问从机 + { + scr_RdData_Index = 5; + SDWA_Send_VAR(0x0240, scr_RdData_Index ); + + SDWA_JumpToHome(); + } + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x02) && (sdwaBuf[5]==0x65)) + { + if((canMem[6].com != 0) && (ConfigData_Index == 1)) //对应从机在线且上位机不在询问从机 + { + scr_RdData_Index = 6; + SDWA_Send_VAR(0x0240, scr_RdData_Index ); + + SDWA_JumpToHome(); + } + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x02) && (sdwaBuf[5]==0x66)) + { + if((canMem[7].com != 0) && (ConfigData_Index == 1)) //对应从机在线且上位机不在询问从机 + { + scr_RdData_Index = 7; + SDWA_Send_VAR(0x0240, scr_RdData_Index ); + + SDWA_JumpToHome(); + } + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x02) && (sdwaBuf[5]==0x67)) + { + if((canMem[8].com != 0) && (ConfigData_Index == 1)) //对应从机在线且上位机不在询问从机 + { + scr_RdData_Index = 8; + SDWA_Send_VAR(0x0240, scr_RdData_Index ); + + SDWA_JumpToHome(); + } + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x02) && (sdwaBuf[5]==0x68)) + { + if((canMem[9].com != 0) && (ConfigData_Index == 1)) //对应从机在线且上位机不在询问从机 + { + scr_RdData_Index = 9; + SDWA_Send_VAR(0x0240, scr_RdData_Index ); + + SDWA_JumpToHome(); + } + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x02) && (sdwaBuf[5]==0x69)) + { + if((canMem[10].com != 0) && (ConfigData_Index == 1)) //对应从机在线且上位机不在询问从机 + { + scr_RdData_Index = 10; + SDWA_Send_VAR(0x0240, scr_RdData_Index ); + + SDWA_JumpToHome(); + } + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x02) && (sdwaBuf[5]==0x6A)) + { + if((canMem[11].com != 0) && (ConfigData_Index == 1)) //对应从机在线且上位机不在询问从机 + { + scr_RdData_Index = 11; + SDWA_Send_VAR(0x0240, scr_RdData_Index ); + + SDWA_JumpToHome(); + } + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x02) && (sdwaBuf[5]==0x6B)) + { + if((canMem[12].com != 0) && (ConfigData_Index == 1)) //对应从机在线且上位机不在询问从机 + { + scr_RdData_Index = 12; + SDWA_Send_VAR(0x0240, scr_RdData_Index ); + + SDWA_JumpToHome(); + } + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x02) && (sdwaBuf[5]==0x6C)) + { + if((canMem[13].com != 0) && (ConfigData_Index == 1)) //对应从机在线且上位机不在询问从机 + { + scr_RdData_Index = 13; + SDWA_Send_VAR(0x0240, scr_RdData_Index ); + + SDWA_JumpToHome(); + } + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x02) && (sdwaBuf[5]==0x6D)) + { + if((canMem[14].com != 0) && (ConfigData_Index == 1)) //对应从机在线且上位机不在询问从机 + { + scr_RdData_Index = 14; + SDWA_Send_VAR(0x0240, scr_RdData_Index ); + + SDWA_JumpToHome(); + } + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x02) && (sdwaBuf[5]==0x06E)) + { + if((canMem[15].com != 0) && (ConfigData_Index == 1)) //对应从机在线且上位机不在询问从机 + { + scr_RdData_Index = 15; + SDWA_Send_VAR(0x0240, scr_RdData_Index ); + + SDWA_JumpToHome(); + } + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x02) && (sdwaBuf[5]==0x6F)) + { + if((canMem[16].com != 0) && (ConfigData_Index == 1)) //对应从机在线且上位机不在询问从机 + { + scr_RdData_Index = 16; + SDWA_Send_VAR(0x0240, scr_RdData_Index ); + + SDWA_JumpToHome(); + } + } + + + /**协议选择——共42项**/ + //A5 5A 06 83 03 10 01 00 01 勾选 + //A5 5A 06 83 03 10 01 00 00 取消勾选 + //A5 5A 05 82 03 00 00 01 显示勾选 + //A5 5A 05 82 03 00 00 00 显示取消勾选 + if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x03) && (sdwaBuf[5]==0x10)) + { + if(protocol_Index !=1) + protocol_Index = 1; + else + protocol_Index = 0; + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x03) && (sdwaBuf[5]==0x11)) + { + if(protocol_Index !=2) + protocol_Index = 2; + else + protocol_Index = 0; + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x03) && (sdwaBuf[5]==0x12)) + { + if(protocol_Index !=3) + protocol_Index = 3; + else + protocol_Index = 0; + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x03) && (sdwaBuf[5]==0x13)) + { + if(protocol_Index !=4) + protocol_Index = 4; + else + protocol_Index = 0; + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x03) && (sdwaBuf[5]==0x14)) + { + if(protocol_Index !=5) + protocol_Index = 5; + else + protocol_Index = 0; + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x03) && (sdwaBuf[5]==0x15)) + { + if(protocol_Index !=6) + protocol_Index = 6; + else + protocol_Index = 0; + } + + //第2页相关 + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x03) && (sdwaBuf[5]==0x16)) + { + if(protocol_Index !=7) + protocol_Index = 7; + else + protocol_Index = 0; + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x03) && (sdwaBuf[5]==0x17)) + { + if(protocol_Index !=8) + protocol_Index = 8; + else + protocol_Index = 0; + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x03) && (sdwaBuf[5]==0x18)) + { + if(protocol_Index !=9) + protocol_Index = 9; + else + protocol_Index = 0; + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x03) && (sdwaBuf[5]==0x19)) + { + if(protocol_Index !=10) + protocol_Index = 10; + else + protocol_Index = 0; + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x03) && (sdwaBuf[5]==0x1A)) + { + if(protocol_Index !=11) + protocol_Index = 11; + else + protocol_Index = 0; + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x03) && (sdwaBuf[5]==0x1B)) + { + if(protocol_Index !=12) + protocol_Index = 12; + else + protocol_Index = 0; + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x03) && (sdwaBuf[5]==0x1C)) + { + if(protocol_Index !=13) + protocol_Index = 13; + else + protocol_Index = 0; + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x03) && (sdwaBuf[5]==0x1D)) + { + if(protocol_Index !=14) + protocol_Index = 14; + else + protocol_Index = 0; + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x03) && (sdwaBuf[5]==0x1E)) + { + if(protocol_Index !=15) + protocol_Index = 15; + else + protocol_Index = 0; + } + + //第3页相关 + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x03) && (sdwaBuf[5]==0x1F)) + { + if(protocol_Index !=16) + protocol_Index = 16; + else + protocol_Index = 0; + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x03) && (sdwaBuf[5]==0x30)) + { + if(protocol_Index !=17) + protocol_Index = 17; + else + protocol_Index = 0; + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x03) && (sdwaBuf[5]==0x31)) + { + if(protocol_Index !=18) + protocol_Index = 18; + else + protocol_Index = 0; + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x03) && (sdwaBuf[5]==0x32)) + { + if(protocol_Index !=19) + protocol_Index = 19; + else + protocol_Index = 0; + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x03) && (sdwaBuf[5]==0x33)) + { + if(protocol_Index !=20) + protocol_Index = 20; + else + protocol_Index = 0; + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x03) && (sdwaBuf[5]==0x34)) + { + if(protocol_Index !=21) + protocol_Index = 21; + else + protocol_Index = 0; + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x03) && (sdwaBuf[5]==0x35)) + { + if(protocol_Index !=22) + protocol_Index = 22; + else + protocol_Index = 0; + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x03) && (sdwaBuf[5]==0x36)) + { + if(protocol_Index !=23) + protocol_Index = 23; + else + protocol_Index = 0; + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x03) && (sdwaBuf[5]==0x37)) + { + if(protocol_Index !=24) + protocol_Index = 24; + else + protocol_Index = 0; + } + + //第4页相关 + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x03) && (sdwaBuf[5]==0x38)) + { + if(protocol_Index !=25) + protocol_Index = 25; + else + protocol_Index = 0; + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x03) && (sdwaBuf[5]==0x39)) + { + if(protocol_Index !=26) + protocol_Index = 26; + else + protocol_Index = 0; + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x03) && (sdwaBuf[5]==0x3A)) + { + if(protocol_Index !=27) + protocol_Index = 27; + else + protocol_Index = 0; + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x03) && (sdwaBuf[5]==0x3B)) + { + if(protocol_Index !=28) + protocol_Index = 28; + else + protocol_Index = 0; + } + + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x03) && (sdwaBuf[5]==0x3C)) + { + if(protocol_Index !=29) + protocol_Index = 29; + else + protocol_Index = 0; + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x03) && (sdwaBuf[5]==0x3D)) + { + if(protocol_Index !=30) + protocol_Index = 30; + else + protocol_Index = 0; + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x03) && (sdwaBuf[5]==0x3E)) + { + if(protocol_Index !=31) + protocol_Index = 31; + else + protocol_Index = 0; + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x03) && (sdwaBuf[5]==0x3F)) + { + if(protocol_Index !=32) + protocol_Index = 32; + else + protocol_Index = 0; + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x03) && (sdwaBuf[5]==0x50)) + { + if(protocol_Index !=33) + protocol_Index = 33; + else + protocol_Index = 0; + } + + //第5页相关 + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x03) && (sdwaBuf[5]==0x51)) + { + if(protocol_Index !=34) + protocol_Index = 34; + else + protocol_Index = 0; + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x03) && (sdwaBuf[5]==0x52)) + { + if(protocol_Index !=35) + protocol_Index = 35; + else + protocol_Index = 0; + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x03) && (sdwaBuf[5]==0x53)) + { + if(protocol_Index !=36) + protocol_Index = 36; + else + protocol_Index = 0; + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x03) && (sdwaBuf[5]==0x54)) + { + if(protocol_Index !=37) + protocol_Index = 37; + else + protocol_Index = 0; + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x03) && (sdwaBuf[5]==0x57)) //在这里跳过2个地址 + { + if(protocol_Index !=38) + protocol_Index = 38; + else + protocol_Index = 0; + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x03) && (sdwaBuf[5]==0x58)) + { + if(protocol_Index !=39) + protocol_Index = 39; + else + protocol_Index = 0; + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x03) && (sdwaBuf[5]==0x59)) + { + if(protocol_Index !=40) + protocol_Index = 40; + else + protocol_Index = 0; + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x03) && (sdwaBuf[5]==0x5A)) + { + if(protocol_Index !=41) + protocol_Index = 41; + else + protocol_Index = 0; + } + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x03) && (sdwaBuf[5]==0x5B)) + { + if(protocol_Index !=42) + protocol_Index = 42; + else + protocol_Index = 0; + } + + uf_CAN1_Init(); + + if(protocol != protocol_Index) + { + protocol = protocol_Index; + + EEPROM_WrMulByte(EE_PROTOCOL,&protocol); + delay_ms(5); + } + } + + + /**屏幕配置参数的写入**/ + if(flashUpdateFlag != 0) //配置参数的CRC校验码计算和写入 + { + uint8_t i; + uint8_t* data; + uint8_t temp[26]; //要计算校验码 + + if(flashUpdateFlag >= 2) //2代表修改单个参数，3代表初始化所有参数 》》但都需要计算CRC值 + { + SDWA_Send_VAR(0x0145, 1); //显示请等待 + + data = (uint8_t *)&bmsMem.ee_sconf1; + for(i=0;i<25;i++) + { + temp[i] = *data; + data++; + } + temp[25] = CRC8_Cal(&temp[0],25); //更改对应校验值 + bmsMem.ee_tr = temp[25]; + + data = (uint8_t *)&bmsMem.mcu_otc; + for(i=0;i<13;i++) + { + temp[i] = *data; + data++; + } + temp[13] = CRC8_Cal(&temp[0],13); //更改对应校验值 + bmsMem.mcu_crc = temp[13]; + } + + //bmsMem中数据更新到FLASH A区和B区和AFE EEPORM + if((MEMORY_UpdateFlash(FLASH_DATA_A_BASE) == 0) && (MEMORY_UpdateFlash(FLASH_DATA_B_BASE) == 0)) + { + staPack.bits.flashUpdate= 0; + if(MEMORY_UpdateAFE() ==0) //更新AFE EEPROM内容 + { + staPack.bits.eepromUpdate = 0; + } + else + { + staPack.bits.eepromUpdate = 1; + } + } + else + { + staPack.bits.flashUpdate= 1; + } + bmsMem.packStatus = staPack.byte; + + //初始化参数成功后，要显示一段时间后恢复正常 + if(flashUpdateFlag == 3) + { + initFlag = 1; + SDWA_Send_VAR(0x01A4, 2); //初始化成功 + } + + //清空值 + flashUpdateFlag = 0; + } + + /**除了屏幕亮度的程序外，其他默认都会初始化**/ + if(sdwa_sleep_flag != 1) + { + SCR_DispProcotol(); + + if(sleep_flag == 1) + { + //有屏幕操作/摁亮屏幕，退出休眠且更新计时起点 + sleep_flag = 0; + SLEEP_Refresh(); + SLEEP2_Refresh(); + } + } + else + { + sdwaBufIndex = 0; + } + } +} + diff --git a/MOUDLE/SOE.c b/MOUDLE/SOE.c new file mode 100644 index 0000000..b732afa --- /dev/null +++ b/MOUDLE/SOE.c @@ -0,0 +1,253 @@ +/** + ****************************************************************************** + * @file tim.c + * @author Jerry + * @version V2.1 + * @date 19-April-2022 + * @brief tim program body. + ****************************************************************************** + * @attention + * + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" +#include "global.h" +#include "string.h" +#include "rtc.h" +#include "soe.h" + +_soe_obj soe; +uint8_t rdd[64]; + + +/******************************************************************************* +Function: +Description: 发生SOE事件时，将事件写入EEPROM +Input: +Output: +Others: +*******************************************************************************/ +void SOE_BkData(uint8_t type) +{ + uint8_t wrBuf[64]; + uint8_t extBuf[6]; + uint8_t adrh,adrl; + uint16_t ee_vol,ee_fcc,ee_rcc; + int16_t ee_cur; + uint8_t afe_mode; + uint16_t ext_addr; + + uint8_t i; + uint16_t ee_cellVol[20]; //用于转换存储单芯电压 + + ee_vol = (uint16_t)(bmsMem.packVoltage/10); //电压保存 单位0.01V + ee_cur = (int16_t) (bmsMem.packCurrent/100); //电流保存 单位0.1A + ee_fcc = (uint16_t)(fcc/3600/100); //满充容量 单位0.1Ah //5.16增加满充容量自适应逻辑后修改 + ee_rcc = (uint16_t)(bmsMem.rcc/3600/100); //剩余容量 单位0.1Ah + + /*记录序号,便于上位机排序和查看*/ + wrBuf[0] = (soe.index >> 24) & 0xff ; + wrBuf[1] = (soe.index >> 16) & 0xff ; + wrBuf[2] = (soe.index >> 8) & 0xff ; + wrBuf[3] = (soe.index >> 0) & 0xff ; + + /*记录时间*/ + wrBuf[4] = calendar.w_year ; + wrBuf[5] = calendar.w_month ; + wrBuf[6] = calendar.w_date ; + wrBuf[7] = calendar.hour ; + wrBuf[8] = calendar.min ; + wrBuf[9] = calendar.sec ; + + /*记录BMS参数*/ + wrBuf[10] = bmsMem.bStatus1 & 0xff; + wrBuf[11] = bmsMem.bStatus2 & 0xff; + wrBuf[12] = bmsMem.bStatus3 & 0xff; + wrBuf[13] = bmsMem.temperaStatus & 0xff; + wrBuf[14] = bmsMem.balanceStatus & 0xff; + //wrBuf[15] = bmsMem.packStatus & 0xff; + wrBuf[15] = ((bmsMem.bStatus1>>4) & 0xf0) | ((bmsMem.temperaStatus>>8) & 0x0f); //占用原packStatus位置，保存新增保护 + + wrBuf[16] = (ee_vol >> 8) & 0xff; + wrBuf[17] = (ee_vol >> 0) & 0xff; + wrBuf[18] = (ee_cur >> 8) & 0xff; + wrBuf[19] = (ee_cur >> 0) & 0xff; + + wrBuf[20] = (ee_fcc >> 8) & 0xff; + wrBuf[21] = (ee_fcc >> 0) & 0xff; + wrBuf[22] = (ee_rcc >> 8) & 0xff; + wrBuf[23] = (ee_rcc >> 0) & 0xff; + + wrBuf[24] = (bmsMem.cycleCount >> 8) & 0xff; + wrBuf[25] = (bmsMem.cycleCount >> 0) & 0xff; + + wrBuf[26] = bmsMem.soh & 0xff; + + //afe_T1~T3 + wrBuf[27] = (bmsMem.afe_T1>>8) & 0x0f; + wrBuf[28] = (bmsMem.afe_T1>>0) & 0xff; + wrBuf[29] = (bmsMem.afe_T2>>4) & 0xff; + wrBuf[30] = ((bmsMem.afe_T2<<4) & 0xf0) | ((bmsMem.afe_T3>>8) & 0x0f); + wrBuf[31] = (bmsMem.afe_T3>>0) & 0xff; + //mcu_T1~T4 + wrBuf[32] = (bmsMem.mcu_T1>>4) & 0xff; + wrBuf[33] = ((bmsMem.mcu_T1<<4) & 0xf0) | ((bmsMem.mcu_T2>>8) & 0x0f); + wrBuf[34] = (bmsMem.mcu_T2>>0) & 0xff; + wrBuf[35] = (bmsMem.mcu_T3>>4) & 0xff; + wrBuf[36] = ((bmsMem.mcu_T3<<4) & 0xf0) | ((bmsMem.mcu_T4>>8) & 0x0f); + wrBuf[37] = (bmsMem.mcu_T4>>0) & 0xff; + + afe_mode = (paraMem.sc_mode >> 8) & 0xFF; + + for(i=0;i<20;i++) + { + if(i < 16) + { + if(bmsMem.vCell[i] > 5119) + { + ee_cellVol[i] = 0; + } + else if(bmsMem.vCell[i] > 4095) + { + ee_cellVol[i] = 4095; + } + else + { + ee_cellVol[i] = bmsMem.vCell[i]; + } + } + else + { + if(afe_mode == 1) + { + if(bmsMem.vCell2[i-16] > 5119) + { + ee_cellVol[i] = 0; + } + else if(bmsMem.vCell2[i-16] > 4095) + { + ee_cellVol[i] = 4095; + } + else + { + ee_cellVol[i] = bmsMem.vCell2[i-16]; + } + } + else + { + ee_cellVol[i] = 0; + } + } + } + + wrBuf[38] = (ee_cellVol[0]>>4) & 0xff; + wrBuf[39] = ((ee_cellVol[0]<<4) & 0xf0) | ((ee_cellVol[1]>>8) & 0x0f); + wrBuf[40] = (ee_cellVol[1]>>0) & 0xff; + wrBuf[41] = (ee_cellVol[2]>>4) & 0xff; + wrBuf[42] = ((ee_cellVol[2]<<4) & 0xf0) | ((ee_cellVol[3]>>8) & 0x0f); + wrBuf[43] = (ee_cellVol[3]>>0) & 0xff; + wrBuf[44] = (ee_cellVol[4]>>4) & 0xff; + wrBuf[45] = ((ee_cellVol[4]<<4) & 0xf0) | ((ee_cellVol[5]>>8) & 0x0f); + wrBuf[46] = (ee_cellVol[5]>>0) & 0xff; + wrBuf[47] = (ee_cellVol[6]>>4) & 0xff; + wrBuf[48] = ((ee_cellVol[6]<<4) & 0xf0) | ((ee_cellVol[7]>>8) & 0x0f); + wrBuf[49] = (ee_cellVol[7]>>0) & 0xff; + wrBuf[50] = (ee_cellVol[8]>>4) & 0xff; + wrBuf[51] = ((ee_cellVol[8]<<4) & 0xf0) | ((ee_cellVol[9]>>8) & 0x0f); + wrBuf[52] = (ee_cellVol[9]>>0) & 0xff; + wrBuf[53] = (ee_cellVol[10]>>4) & 0xff; + wrBuf[54] = ((ee_cellVol[10]<<4) & 0xf0) | ((ee_cellVol[11]>>8) & 0x0f); + wrBuf[55] = (ee_cellVol[11]>>0) & 0xff; + wrBuf[56] = (ee_cellVol[12]>>4) & 0xff; + wrBuf[57] = ((ee_cellVol[12]<<4) & 0xf0) | ((ee_cellVol[13]>>8) & 0x0f); + wrBuf[58] = (ee_cellVol[13]>>0) & 0xff; + wrBuf[59] = (ee_cellVol[14]>>4) & 0xff; + wrBuf[60] = ((ee_cellVol[14]<<4) & 0xf0) | ((ee_cellVol[15]>>8) & 0x0f); + wrBuf[61] = (ee_cellVol[15]>>0) & 0xff; + + wrBuf[62] = type; + if(afe_mode == 1) //SH36735XX, 20 cells + { + wrBuf[63] = 0xA6; //new format flag + //pack cell17~20 into extBuf[0~5] + extBuf[0] = (ee_cellVol[16]>>4) & 0xff; + extBuf[1] = ((ee_cellVol[16]<<4) & 0xf0) | ((ee_cellVol[17]>>8) & 0x0f); + extBuf[2] = (ee_cellVol[17]>>0) & 0xff; + extBuf[3] = (ee_cellVol[18]>>4) & 0xff; + extBuf[4] = ((ee_cellVol[18]<<4) & 0xf0) | ((ee_cellVol[19]>>8) & 0x0f); + extBuf[5] = (ee_cellVol[19]>>0) & 0xff; + } + else + { + wrBuf[63] = 0xA5; //old format flag + } + + + /*写入前检查是否合法*/ + //当前地址=0或0XFFFF或不为64倍数，初始化地址和记录序号 + if((soe.pc < 0x1000) || (soe.pc > 0x2940) || (soe.pc == 0xffff) || (soe.pc%64 !=0)) + { + soe.pc = RECORD_START_ADDR; + soe.index = 0; + soe.num = 0; + } + + + /*记录写入EEPROM*/ + adrh = (soe.pc>>8) & 0xff; + adrl = soe.pc & 0xff; + EEPROM_WrMulByte(EE_SOE,wrBuf); + delay_ms(10); + EEPROM_RdMulByte(EE_SOE,rdd); + + //write extend cell17~20 for SH36735XX + if(afe_mode == 1) + { + ext_addr = 0x2900 + (soe.pc - 0x1000) * 6 / 64; + adrh = (ext_addr>>8) & 0xff; + adrl = ext_addr & 0xff; + EEPROM_WrMulByte(EE_SOE_EXT,extBuf); + delay_ms(10); + EEPROM_RdMulByte(EE_SOE_EXT,rdd); + } + + /*清除记录写入标记*/ + soe.bkType = 0; + + /*暂定400条记录*/ + soe.index+=1; + soe.pc +=0x40; + soe.num +=1; + +// if(soe.pc == 0x7400) //0x1000-0x7400共400条 +// if(soe.pc == 0x1C80) //0x1000-0x1C80共50条 + if(soe.pc == 0x2900) //0x1000-0x2900共100条 + { + soe.pc = RECORD_START_ADDR; + } + + if(soe.num >= 100) + { + soe.num = 100; + } + + wrBuf[0] = (soe.index >> 24) & 0xff ; + wrBuf[1] = (soe.index >> 16) & 0xff ; + wrBuf[2] = (soe.index >> 8) & 0xff ; + wrBuf[3] = (soe.index >> 0) & 0xff ; + wrBuf[4] = (soe.pc >>8)&0XFF ; + wrBuf[5] = soe.pc & 0xff ; + wrBuf[6] = (soe.num >>8)&0XFF ; + wrBuf[7] = soe.num & 0xff ; + + EEPROM_WrMulByte(EE_SOE_INF,wrBuf); + delay_ms(10); + EEPROM_RdMulByte(EE_SOE_INF,rdd); + + scr_RdRecord_Flg = 1; + //SCR_DispProcotol(); +} + diff --git a/MOUDLE/Screen.c b/MOUDLE/Screen.c new file mode 100644 index 0000000..523c54e --- /dev/null +++ b/MOUDLE/Screen.c @@ -0,0 +1,3129 @@ +/** + ****************************************************************************** + * @file Screen.c + * @author + * @version + * @date + * @brief + ****************************************************************************** + * @attention + * + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" +#include "global.h" +#include "rtc.h" +#include "soe.h" +#include "string.h" +#include +#include + + +//通用定义 +#define SCR_UART USART2 +#define SCR_Send USART2_printf + +#define SCR_MON_CNT 6000 //6000*10ms = 60s +#define SCR_RX_BUF_LEN 128 //接收的最大长度 +#define SCR_TX_BUF_LEN 128 //发送的最大长度 + +char SCR_Rx_Buf[SCR_RX_BUF_LEN]; +char SCR_Tx_Buf[SCR_TX_BUF_LEN]; + +uint16_t SCR_Rx_BufIndex; +uint16_t SCR_Moni_Count; + +uint8_t read_index; +uint8_t recordBuf[64]; +char sendRecord[64]; + +uint8_t scrBufIndex; +uint8_t scrMoniCount; +uint8_t scrRecvFlag; + +uint8_t initFlag; //初始化配置参数 +uint8_t clearFlag; //删除记录成功标志（已存在） +uint8_t clearFlag_timer; //成功图标保持计时（秒） +uint8_t EE_clearFlag; //特殊按钮，点按清空EEPROM + +//休眠(屏幕自己做) +char SCR_sleepOn[] = {0x86,0xFF,0xFF,0xFF}; //屏幕休眠 +char SCR_sleepOff[] = {0x87,0xFF,0xFF,0xFF}; //屏幕退出休眠 + +//分配地址勾选 +char SCR_setADDR[] = {0x65,0x0E,0x07,0x01,0xFF,0xFF,0xFF}; + +//强制开启放电 +char SCR_ForceDischarge[] = {0x65, 0x0C, 0x01, 0x01, 0xFF, 0xFF, 0xFF}; + +// 出厂设置键值 +char SCR_FactoryReset[] = {0x65, 0x0D, 0x01, 0x01, 0xFF, 0xFF, 0xFF}; + +//遮挡历史 +char SCR_Hide_History[] = {0x65,0x01,0x10,0x01,0xFF,0xFF,0xFF};//按下历史按键 +char SCR_up_History[] = {0x65,0x11,0x0A,0x01,0xFF,0xFF,0xFF};//上翻页 +char SCR_down_History[] = {0x65,0x11,0x0B,0x01,0xFF,0xFF,0xFF};//下翻页 +char SCR_clean_History[]= {0x65,0x11,0x0C,0x01,0xFF,0xFF,0xFF};//删除历史记录 + +//并机按键键值 +char SCR_Parallel[] = {0x65,0x01,0x11,0x01,0xFF,0xFF,0xFF}; + +//电池页跳转汇总数据页图标键值 +char SCR_Allpack[] = {0x65,0x13,0x0A,0x01,0xFF,0xFF,0xFF}; +//汇总数据页返回电池页图标键值 +char SCR_Allcell[] = {0x65,0x12,0x11,0x01,0xFF,0xFF,0xFF}; +//告警页返回键值 +char SCR_Protect[] = {0x65,0x04,0x0C,0x01,0xFF,0xFF,0xFF}; + +//屏幕休眠唤醒键值 +char SCR_Sleep[] = {0x87,0xFF,0xFF,0xFF}; + +//PACK页-单个电池图标 +char SCR_PACK1[] = {0x65,0x12,0x01,0x01,0xFF,0xFF,0xFF}; +char SCR_PACK2[] = {0x65,0x12,0x02,0x01,0xFF,0xFF,0xFF}; +char SCR_PACK3[] = {0x65,0x12,0x03,0x01,0xFF,0xFF,0xFF}; +char SCR_PACK4[] = {0x65,0x12,0x04,0x01,0xFF,0xFF,0xFF}; +char SCR_PACK5[] = {0x65,0x12,0x05,0x01,0xFF,0xFF,0xFF}; +char SCR_PACK6[] = {0x65,0x12,0x06,0x01,0xFF,0xFF,0xFF}; +char SCR_PACK7[] = {0x65,0x12,0x07,0x01,0xFF,0xFF,0xFF}; +char SCR_PACK8[] = {0x65,0x12,0x08,0x01,0xFF,0xFF,0xFF}; +char SCR_PACK9[] = {0x65,0x12,0x09,0x01,0xFF,0xFF,0xFF}; +char SCR_PACK10[] = {0x65,0x12,0x0A,0x01,0xFF,0xFF,0xFF}; +char SCR_PACK11[] = {0x65,0x12,0x0B,0x01,0xFF,0xFF,0xFF}; +char SCR_PACK12[] = {0x65,0x12,0x0C,0x01,0xFF,0xFF,0xFF}; +char SCR_PACK13[] = {0x65,0x12,0x0D,0x01,0xFF,0xFF,0xFF}; +char SCR_PACK14[] = {0x65,0x12,0x0E,0x01,0xFF,0xFF,0xFF}; +char SCR_PACK15[] = {0x65,0x12,0x0F,0x01,0xFF,0xFF,0xFF}; +char SCR_PACK16[] = {0x65,0x12,0x10,0x01,0xFF,0xFF,0xFF}; + +//选择协议 +char SCR_setProtocol_SolArk[] = {0x65,0x06,0x0D,0x01,0xFF,0xFF,0xFF}; +char SCR_setProtocol_GoodWe[] = {0x65,0x06,0x0E,0x01,0xFF,0xFF,0xFF}; +char SCR_setProtocol_Megarevo[] = {0x65,0x06,0x0F,0x01,0xFF,0xFF,0xFF}; +char SCR_setProtocol_Pylon[] = {0x65,0x06,0x10,0x01,0xFF,0xFF,0xFF}; +char SCR_setProtocol_Deye[] = {0x65,0x06,0x11,0x01,0xFF,0xFF,0xFF}; +char SCR_setProtocol_MUST[] = {0x65,0x06,0x12,0x01,0xFF,0xFF,0xFF}; +char SCR_setProtocol_Solis[] = {0x65,0x06,0x13,0x01,0xFF,0xFF,0xFF}; +char SCR_setProtocol_Growatt[] = {0x65,0x06,0x14,0x01,0xFF,0xFF,0xFF}; +char SCR_setProtocol_Aiswei[] = {0x65,0x06,0x15,0x01,0xFF,0xFF,0xFF}; +char SCR_setProtocol_Afore[] = {0x65,0x06,0x16,0x01,0xFF,0xFF,0xFF}; +char SCR_setProtocol_Victron[] = {0x65,0x06,0x17,0x01,0xFF,0xFF,0xFF}; +char SCR_setProtocol_Sorotec[] = {0x65,0x06,0x18,0x01,0xFF,0xFF,0xFF}; + +char SCR_setProtocol_SMA[] = {0x65,0x07,0x0D,0x01,0xFF,0xFF,0xFF}; +char SCR_setProtocol_Sunways[] = {0x65,0x07,0x0E,0x01,0xFF,0xFF,0xFF}; +char SCR_setProtocol_Luxpower[] = {0x65,0x07,0x0F,0x01,0xFF,0xFF,0xFF}; +char SCR_setProtocol_Schneider[] = {0x65,0x07,0x10,0x01,0xFF,0xFF,0xFF}; +char SCR_setProtocol_AlpSolarr[] = {0x65,0x07,0x11,0x01,0xFF,0xFF,0xFF}; +char SCR_setProtocol_SRNE[] = {0x65,0x07,0x12,0x01,0xFF,0xFF,0xFF}; +char SCR_setProtocol_Voltronic[] = {0x65,0x07,0x13,0x01,0xFF,0xFF,0xFF}; +char SCR_setProtocol_COSUPER[] = {0x65,0x07,0x14,0x01,0xFF,0xFF,0xFF}; +char SCR_setProtocol_SMK[] = {0x65,0x07,0x15,0x01,0xFF,0xFF,0xFF}; +char SCR_setProtocol_SAKO[] = {0x65,0x07,0x16,0x01,0xFF,0xFF,0xFF}; +char SCR_setProtocol_SNADI[] = {0x65,0x07,0x17,0x01,0xFF,0xFF,0xFF}; +char SCR_setProtocol_invt[] = {0x65,0x07,0x18,0x01,0xFF,0xFF,0xFF}; + +char SCR_altProtocol_1[] = {0x65,0x08,0x03,0x01,0xFF,0xFF,0xFF}; +char SCR_altProtocol_2[] = {0x65,0x08,0x04,0x01,0xFF,0xFF,0xFF}; + +//短路保护电压 +char SCR_setSCVol_0[] = {0x65,0x15,0x02,0x01,0xFF,0xFF,0xFF}; //设短路电压 page21 b1 50mV +char SCR_setSCVol_1[] = {0x65,0x15,0x03,0x01,0xFF,0xFF,0xFF}; //设短路电压 page21 b2 80mV +char SCR_setSCVol_2[] = {0x65,0x15,0x04,0x01,0xFF,0xFF,0xFF}; //设短路电压 page21 b3 110mV +char SCR_setSCVol_3[] = {0x65,0x15,0x05,0x01,0xFF,0xFF,0xFF}; //设短路电压 page21 b4 140mV +char SCR_setSCVol_4[] = {0x65,0x15,0x06,0x01,0xFF,0xFF,0xFF}; //设短路电压 page21 b5 170mV +char SCR_setSCVol_5[] = {0x65,0x15,0x07,0x01,0xFF,0xFF,0xFF}; //设短路电压 page21 b6 200mV +char SCR_setSCVol_6[] = {0x65,0x15,0x08,0x01,0xFF,0xFF,0xFF}; //设短路电压 page21 b7 230mV +char SCR_setSCVol_7[] = {0x65,0x15,0x09,0x01,0xFF,0xFF,0xFF}; //设短路电压 page21 b8 260mV +char SCR_setSCVol_8[] = {0x65,0x15,0x0A,0x01,0xFF,0xFF,0xFF}; //设短路电压 page21 b9 290mV +char SCR_setSCVol_9[] = {0x65,0x15,0x0B,0x01,0xFF,0xFF,0xFF}; //设短路电压 page21 b10 320mV +char SCR_setSCVol_10[] = {0x65,0x15,0x0C,0x01,0xFF,0xFF,0xFF}; //设短路电压 page21 b11 350mV +char SCR_setSCVol_11[] = {0x65,0x15,0x0D,0x01,0xFF,0xFF,0xFF}; //设短路电压 page21 b12 400mV + +//短路保护延时 +char SCR_setSCTim_0[] = {0x65,0x16,0x02,0x01,0xFF,0xFF,0xFF}; //设短路延时 page22 b1 0uS +char SCR_setSCTim_1[] = {0x65,0x16,0x03,0x01,0xFF,0xFF,0xFF}; //设短路延时 page22 b2 64uS +char SCR_setSCTim_2[] = {0x65,0x16,0x04,0x01,0xFF,0xFF,0xFF}; //设短路延时 page22 b3 128uS +char SCR_setSCTim_3[] = {0x65,0x16,0x05,0x01,0xFF,0xFF,0xFF}; //设短路延时 page22 b4 192uS +char SCR_setSCTim_4[] = {0x65,0x16,0x06,0x01,0xFF,0xFF,0xFF}; //设短路延时 page22 b5 256uS +char SCR_setSCTim_5[] = {0x65,0x16,0x07,0x01,0xFF,0xFF,0xFF}; //设短路延时 page22 b6 320uS +char SCR_setSCTim_6[] = {0x65,0x16,0x08,0x01,0xFF,0xFF,0xFF}; //设短路延时 page22 b7 348uS +char SCR_setSCTim_7[] = {0x65,0x16,0x09,0x01,0xFF,0xFF,0xFF}; //设短路延时 page22 b8 448uS +char SCR_setSCTim_8[] = {0x65,0x16,0x0A,0x01,0xFF,0xFF,0xFF}; //设短路延时 page22 b9 512uS +char SCR_setSCTim_9[] = {0x65,0x16,0x0B,0x01,0xFF,0xFF,0xFF}; //设短路延时 page22 b10 576uS +char SCR_setSCTim_10[] = {0x65,0x16,0x0C,0x01,0xFF,0xFF,0xFF}; //设短路延时 page22 b11 640uS +char SCR_setSCTim_11[] = {0x65,0x16,0x0D,0x01,0xFF,0xFF,0xFF}; //设短路延时 page22 b12 704uS + +//参数(字符串) +//逆变器设置 +//逆变器充电限流 page9 t1 id1 (输入100后会发送39 2C 31 2C 31 30 30 04 FF FF FF //9,1,100页面9，ID1，100) +//逆变器充电限压 page9 t2 id2 +//逆变器放电限流 page9 t3 id3 +//逆变器放电限压 page9 t4 id4 + +//BMS设置 +//充电过流保护值 page9 t5 id5 +//放电过流保护值 page9 t6 id6 + +//充电高温保护值 page10 t1 id1 +//充电高温释放值 page10 t2 id2 +//充电低温保护值 page10 t3 id3 +//充电低温保护值 page10 t4 id4 + +//放电高温保护值 page10 t5 id5 +//放电高温释放值 page10 t6 id6 +//放电低温保护值 page10 t7 id7 +//放电低温保护值 page10 t8 id8 + +//充电过压保护值 page11 t1 id1 +//充电过压释放值 page11 t2 id2 +//充电欠压保护值 page11 t3 id3 +//充电欠压释放值 page11 t4 id4 + +uint8_t flashUpdateFlag; //按钮反馈，会显示1秒的正在设置 1:只显示 2:显示并且将配置写入Flash +uint8_t SCR_setProFlag; //协议按钮反馈，1：按下，0：未按下 + +uint8_t SCR_setADDRFlag; //分配地址按下标志 + +uint8_t SCR_HistoryFlag; //遮挡历史按下标志 +uint8_t SCR_ParallelFlag;//并机按键按下标志 + +uint8_t SCR_PACKFlag; //并机页电池图标按下标志 + +// 强制放电状态 +uint8_t force_discharge_flag; // 0=空闲, 1=启动中, 2=倒计时中 + +//出厂设置标志 +uint8_t factory_reset_flag; // 0=空闲, 1=执行中, 2=完成 + +uint8_t SCR_show[2]; //出现多个保护，轮流显示 1.欠压保护 2.低SOC保护 +uint8_t SCR_showIdx; //当前要显示保护的序号 +uint8_t SCR_showNum; //总个数 +uint8_t SCR_showNum_old; //比较总个数，不同时清零序号 + +uint8_t protocol; //逆变器通信协议 + +//屏幕显示数据的地址，默认是自身地址，且只有addr=1可以变化该地址 +uint8_t scr_RdData_Index;//屏幕显示数据的地址，默认是自身地址，且只有addr=1可以变化该地址 +uint8_t scr_RdRecord_Flg;//屏幕只可以查看自身记录；当记录更新/清空/收到清空指令/进记录页面/上下翻动时，才会读EEPROM更新一次屏幕记录内容 + +uint8_t bAlarmFlagOld_slave; //主机屏幕显示从机报警的跳转 + +uint8_t scr_WrZero_Flg; //屏幕写零点校准 +uint8_t scr_WrGain_Flg; //屏幕写增益校准 + +uint8_t LTEStatus_flg; //要传状态的标志 +char LTEStatus_str[41]; //4G状态文本 + + +//USART2专用的printf函数(疑问：LW发送内容较多，未使用中断发送，是否影响系统实时性？) +int USART2_printf(const char *fmt, ...) +{ + va_list args; + va_start(args, fmt); + int len = vsnprintf(SCR_Tx_Buf, sizeof(SCR_Tx_Buf), fmt, args); + va_end(args); + + for(int i = 0; i < len; i++) + { + while(!(USART2->SR & USART_SR_TXE)); // 等待发送完成 + USART2->DR = SCR_Tx_Buf[i]; + } + + return len; +} + +//清空标志 +void Screen_ClearFlg(void) +{ + +} + +//清空接收缓冲区 +void Screen_ClearBuf(void) +{ + SCR_Rx_BufIndex = 0; + memset(SCR_Rx_Buf, 0, SCR_RX_BUF_LEN); +} + +//初始化屏幕通讯 +void Screen_Init(void) +{ + Screen_ClearFlg(); + Screen_ClearBuf(); + + SCR_Moni_Count = SCR_MON_CNT; + uf_UART2_Init(115200); + + //SCR_DispProcotol(); +} + +//一定时间没有接收到数据，初始化屏幕通讯 +void Screen_TIM_Moni(void) +{ + SCR_Moni_Count--; + if(SCR_Moni_Count == 0) + { + Screen_Init(); + } +} + +//UART中断接收数据 +void Screen_IT_Receive(void) +{ + //接收数据 + uint8_t received_byte = USART_ReceiveData(SCR_UART); + + //防止数组溢出 + if(SCR_Rx_BufIndex < SCR_RX_BUF_LEN - 1) + { + SCR_Rx_Buf[SCR_Rx_BufIndex] = received_byte; + SCR_Rx_BufIndex++; + } + else + { + Screen_ClearBuf(); + } + + //更新计时 + SCR_Moni_Count = SCR_MON_CNT; +} + +//寻找指令对应的接收内容，可用二进制格式 +//可能出现在任意位置 +uint8_t findHexStr(const char *buf, uint16_t buf_len, const char *cmd, uint16_t cmd_len) +{ + uint16_t i; + + for(i=0;i0:00 +void SCR_Send_TimeCount(uint16_t countdown) +{ + uint8_t min = countdown / 60; + uint8_t sec = countdown % 60; + SCR_Send("page12.t1.txt=\"%02d:%02d\"\xff\xff\xff", min, sec); +} + +//文本传输：2023-08-07 14:00:00 +void SCR_Send_Time(void) +{ + char time_str[20]; + sprintf(time_str, "20%02x/%02x/%02x %02x:%02x:%02x", + calendar.w_year, calendar.w_month, calendar.w_date, + calendar.hour, calendar.min, calendar.sec); + SCR_Send("page19.t9.txt=\"%s\"\xff\xff\xff", time_str); +} + +/**报警记录的显示**/ +void SCR_Send_RecordTime(uint8_t row) +{ + char time_str[20]; + sprintf(time_str, "20%02x/%02x/%02x %02x:%02x:%02x", + recordBuf[4], recordBuf[5], recordBuf[6], + recordBuf[7], recordBuf[8], recordBuf[9]); + if(row == 0) + { + SCR_Send("page17.t6.txt=\"%s\"\xff\xff\xff", time_str); + } + else if(row == 1) + { + SCR_Send("page17.t8.txt=\"%s\"\xff\xff\xff", time_str); + } + else if(row == 2) + { + SCR_Send("page17.t10.txt=\"%s\"\xff\xff\xff", time_str); + } +} + +void Set_Row_Hide(uint8_t row, uint8_t hide) +{ + if(row == 0) SCR_Send("page17.p2.pic=%d\xff\xff\xff", hide ? 151 : 154); + else if(row == 1) SCR_Send("page17.p3.pic=%d\xff\xff\xff", hide ? 151 : 154); + else if(row == 2) SCR_Send("page17.p4.pic=%d\xff\xff\xff", hide ? 151 : 154); +} + +void Send_Record_Blank(uint8_t row) +{ + // 设置遮挡 (1=遮挡) + Set_Row_Hide(row, 1); + + // 清空时间和报警文本 + if(row == 0) + { + SCR_Send("page17.t6.txt=\" \"\xff\xff\xff"); + SCR_Send("page17.t7.txt=\" \"\xff\xff\xff"); + SCR_Send("page17.t3.txt=\" \"\xff\xff\xff"); // 序号也清空 + } + else if(row == 1) + { + SCR_Send("page17.t8.txt=\" \"\xff\xff\xff"); + SCR_Send("page17.t9.txt=\" \"\xff\xff\xff"); + SCR_Send("page17.t4.txt=\" \"\xff\xff\xff"); + } + else if(row == 2) + { + SCR_Send("page17.t10.txt=\" \"\xff\xff\xff"); + SCR_Send("page17.t11.txt=\" \"\xff\xff\xff"); + SCR_Send("page17.t5.txt=\" \"\xff\xff\xff"); + } +} + +void SCR_Send_Record(uint8_t row) +{ + uint16_t bStatus1; + uint16_t bStatus2; + uint16_t bStatus3; + uint16_t temperaStatus; + char *p = sendRecord; + uint8_t cnt = 0; + + // 清空发送缓冲区 + memset(sendRecord, 0, sizeof(sendRecord)); + + // 判断新旧格式 + if((recordBuf[50] == 0x05) && (recordBuf[51] == 0xA5)) + { + // 旧格式 + bStatus1 = recordBuf[44]; + bStatus2 = recordBuf[45]; + bStatus3 = recordBuf[46]; + temperaStatus = recordBuf[47]; + } + else + { + // 新格式 + bStatus1 = (recordBuf[15] & 0xf0) << 4 | recordBuf[10]; + bStatus2 = recordBuf[11]; + bStatus3 = recordBuf[12]; + temperaStatus = (recordBuf[15] & 0x0f) << 8 | recordBuf[13]; + } + + //电压 + if(bStatus1 & 0x0100) { memcpy(p, "Pack_OV ", 8); p += 8; cnt += 8; } + if(bStatus1 & 0x0200) { memcpy(p, "Pack_UV ", 8); p += 8; cnt += 8; } + if(bStatus1 & 0x0001) { memcpy(p, "OV ", 3); p += 3; cnt += 3; } + if(bStatus1 & 0x0002) { memcpy(p, "UV ", 3); p += 3; cnt += 3; } + if(bStatus1 & 0x0040) { memcpy(p, "PF ", 3); p += 3; cnt += 3; } + if(bStatus3 & 0x0008) { memcpy(p, "L0V ", 4); p += 4; cnt += 4; } + + //电流 + if((bStatus1 & 0x0010) || (temperaStatus & 0x0010)) + { memcpy(p, "OCC ", 4); p += 4; cnt += 4; } + if((bStatus1 & 0x042C) || (temperaStatus & 0x0020)) + { memcpy(p, "OCD ", 4); p += 4; cnt += 4; } + if(bStatus1 & 0x0020) { memcpy(p, "SC ", 3); p += 3; cnt += 3; } + if(bStatus2 & 0x0010) { memcpy(p, "SC_Lock ", 8); p += 8; cnt += 8; } + + //温度 + if((bStatus2 & 0x0001) || (temperaStatus & 0x0404)) + { memcpy(p, "UTC ", 4); p += 4; cnt += 4; } + if((bStatus2 & 0x0002) || (temperaStatus & 0x0101)) + { memcpy(p, "OTC ", 4); p += 4; cnt += 4; } + if((bStatus2 & 0x0004) || (temperaStatus & 0x0808)) + { memcpy(p, "UTD ", 4); p += 4; cnt += 4; } + if((bStatus2 & 0x0008) || (temperaStatus & 0x0202)) + { memcpy(p, "OTD ", 4); p += 4; cnt += 4; } + + //故障 + if(temperaStatus & 0x0040) { memcpy(p, "RPSD_Activated ", 15); p += 15; cnt += 15; } + if(bStatus2 & 0x0040) { memcpy(p, "D-MOSfault ", 11); p += 11; cnt += 11; } + if(bStatus2 & 0x0080) { memcpy(p, "C-MOSfault ", 11); p += 11; cnt += 11; } + if(bStatus2 & 0x0020) { memcpy(p, "PCHG_Fail ", 10); p += 10; cnt += 10; } + + // 保证字符串以空字符结尾 + sendRecord[cnt] = '\0'; + + // 发送到对应的列 + if(row == 0) + SCR_Send("page17.t7.txt=\"%s\"\xff\xff\xff", sendRecord); + else if(row == 1) + SCR_Send("page17.t9.txt=\"%s\"\xff\xff\xff", sendRecord); + else if(row == 2) + SCR_Send("page17.t11.txt=\"%s\"\xff\xff\xff", sendRecord); + +} + +/**报警页面的显示**/ +//清空报警数据的显示 +void SCR_ClearAlarm(void) +{ + SCR_Send("page4.t0.txt=\"%d\"\xff\xff\xff", bmsMem.E2_485Addr); + //报警内容显示 + //单体过压 + SCR_Send("page4.p1.pic=31\xff\xff\xff"); //31为正常 + + //单体欠压 + SCR_Send("page4.p6.pic=41\xff\xff\xff"); //41为正常 + + //充电过流 + SCR_Send("page4.p2.pic=33\xff\xff\xff"); //33为正常 + + //放电过流 + SCR_Send("page4.p7.pic=43\xff\xff\xff"); //43为正常 + + //充电高温 + SCR_Send("page4.p3.pic=35\xff\xff\xff"); //35为正常 + + //充电低温 + SCR_Send("page4.p8.pic=45\xff\xff\xff"); //45为正常 + + //放电高温 + SCR_Send("page4.p4.pic=37\xff\xff\xff"); //37为正常 + + //放电低温 + SCR_Send("page4.p9.pic=47\xff\xff\xff"); //47为正常 + + //异常高压 + SCR_Send("page4.p5.pic=39\xff\xff\xff"); //39为正常 + + //低压禁止充电 + SCR_Send("page4.p10.pic=49\xff\xff\xff"); //49为正常 + + //短路保护 + SCR_Send("page4.p11.pic=51\xff\xff\xff"); //51为正常 +} + +//读取主机的报警数据的显示 +void SCR_ShowAlarm(void) +{ + SCR_Send("page4.t0.txt=\"%d\"\xff\xff\xff", bmsMem.E2_485Addr); + //报警内容显示 + //单体过压 + if((bmsMem.bStatus1 & 0x0001) != 0) + { + if(bmsMem.soc<99) + { + SCR_Send("page4.p1.pic=32\xff\xff\xff"); //32为触发 + } + else //当SOC大于99%，此时触发过压报警，不会跳转屏幕，也不会亮报警灯 + { + SCR_Send("page4.p1.pic=31\xff\xff\xff"); //31为正常 + } + } + //总体过压 + else if((bmsMem.bStatus1 & 0x0100) != 0) + { + if(bmsMem.soc<99) + { + SCR_Send("page4.p1.pic=158\xff\xff\xff"); //158为触发 + } + else //当SOC大于99%，此时触发过压报警，不会跳转屏幕，也不会亮报警灯 + { + SCR_Send("page4.p1.pic=31\xff\xff\xff"); //31为正常 + } + } + else + { + SCR_Send("page4.p1.pic=31\xff\xff\xff"); //31为正常 + } + //afe充电过流&充电过流 + if(((bmsMem.bStatus1 & 0x0010) != 0) || ((bmsMem.temperaStatus & 0x0010) != 0)) + { + SCR_Send("page4.p2.pic=34\xff\xff\xff"); //34为触发 + } + else + { + SCR_Send("page4.p2.pic=33\xff\xff\xff"); //33为正常 + } + //afe充电高温&环境充电高温&电芯充电高温 + if(((bmsMem.bStatus2 & 0x0002) != 0) || ((bmsMem.temperaStatus & 0x0100) != 0) || ((bmsMem.temperaStatus & 0x0001) != 0)) + { + SCR_Send("page4.p3.pic=36\xff\xff\xff"); //36为触发 + } + else + { + SCR_Send("page4.p3.pic=35\xff\xff\xff"); //35为正常 + } + //afe放电高温&环境放电高温&电芯放电高温 + if(((bmsMem.bStatus2 & 0x0008) != 0) || ((bmsMem.temperaStatus & 0x0200) != 0) || ((bmsMem.temperaStatus & 0x0002) != 0)) + { + SCR_Send("page4.p4.pic=38\xff\xff\xff"); //38为触发 + } + else + { + SCR_Send("page4.p4.pic=37\xff\xff\xff"); //37为正常 + } + //异常高压 + if((bmsMem.bStatus1 & 0x0040) != 0) + { + SCR_Send("page4.p5.pic=40\xff\xff\xff"); //40为触发 + } + else + { + SCR_Send("page4.p5.pic=39\xff\xff\xff"); //39为正常 + } + //单体欠压 + if((bmsMem.bStatus1 & 0x0002) != 0) + { + SCR_Send("page4.p6.pic=42\xff\xff\xff"); //42为触发 + } + //总体欠压 + else if((bmsMem.bStatus1 & 0x0200) != 0) + { + SCR_Send("page4.p6.pic=159\xff\xff\xff"); //159为触发 + } + else + { + SCR_Send("page4.p6.pic=41\xff\xff\xff"); //41为正常 + } + //afe放电过流&放电过流1&放电过流2 + if(((bmsMem.bStatus1 & 0x000c) != 0) || ((bmsMem.temperaStatus & 0x0020) != 0) || ((bmsMem.bStatus1 & 0x0400) != 0)) + { + SCR_Send("page4.p7.pic=44\xff\xff\xff"); //44为触发 + } + else + { + SCR_Send("page4.p7.pic=43\xff\xff\xff"); //43为正常 + } + //afe充电低温&环境充电低温&电芯充电低温 + if(((bmsMem.bStatus2 & 0x0001) != 0) || ((bmsMem.temperaStatus & 0x0400) != 0) || ((bmsMem.temperaStatus & 0x0004) != 0)) + { + SCR_Send("page4.p8.pic=46\xff\xff\xff"); //46为触发 + } + else + { + SCR_Send("page4.p8.pic=45\xff\xff\xff"); //45为正常 + } + //afe放电低温&环境放电低温&电芯放电低温 + if(((bmsMem.bStatus2 & 0x0004) != 0) || ((bmsMem.temperaStatus & 0x0800) != 0) || ((bmsMem.temperaStatus & 0x0008) != 0)) + { + SCR_Send("page4.p9.pic=48\xff\xff\xff"); //48为触发 + } + else + { + SCR_Send("page4.p9.pic=47\xff\xff\xff"); //47为正常 + } + //低压禁止充电 + if((bmsMem.bStatus3 & 0x0008) != 0) + { + SCR_Send("page4.p10.pic=50\xff\xff\xff"); //50为触发 + } + else + { + SCR_Send("page4.p10.pic=49\xff\xff\xff"); //49为正常 + } + //真短路保护 + if((bmsMem.bStatus2 & 0x0010) != 0) //只有预充情况才会出现短路锁定，出现则一直保持，这里也一直显示 + { + SCR_Send("page4.p11.pic=52\xff\xff\xff"); //52为触发 + } + //浪涌短路保护 + else if((bmsMem.bStatus1 & 0x0020) != 0) + { + SCR_Send("page4.p11.pic=52\xff\xff\xff"); //52为触发 + } + else + { + SCR_Send("page4.p11.pic=51\xff\xff\xff"); //51为正常 + } +} + +//读取从机的报警数据的显示 +void SCR_ShowAlarm_Slave(void) +{ + //报警内容显示 + //单体过压 + if((bmsMem_slave.bStatus1 & 0x0001) != 0) + { + if(bmsMem_slave.soc<99) + { + SCR_Send("page4.p1.pic=32\xff\xff\xff"); //32为触发 + } + else //当SOC大于99%，此时触发过压报警，不会跳转屏幕，也不会亮报警灯 + { + SCR_Send("page4.p1.pic=31\xff\xff\xff"); //31为正常 + } + } + //总体过压 + else if((bmsMem_slave.bStatus1 & 0x0100) != 0) + { + if(bmsMem_slave.soc<99) + { + SCR_Send("page4.p1.pic=158\xff\xff\xff"); //158为触发 + } + else //当SOC大于99%，此时触发过压报警，不会跳转屏幕，也不会亮报警灯 + { + SCR_Send("page4.p1.pic=31\xff\xff\xff"); //31为正常 + } + } + else + { + SCR_Send("page4.p1.pic=31\xff\xff\xff"); //31为正常 + } + //afe充电过流&充电过流 + if(((bmsMem_slave.bStatus1 & 0x0010) != 0) || ((bmsMem_slave.temperaStatus & 0x0010) != 0)) + { + SCR_Send("page4.p2.pic=34\xff\xff\xff"); //34为触发 + } + else + { + SCR_Send("page4.p2.pic=33\xff\xff\xff"); //33为正常 + } + //afe充电高温&环境充电高温&电芯充电高温 + if(((bmsMem_slave.bStatus2 & 0x0002) != 0) || ((bmsMem_slave.temperaStatus & 0x0100) != 0) || ((bmsMem_slave.temperaStatus & 0x0001) != 0)) + { + SCR_Send("page4.p3.pic=36\xff\xff\xff"); //36为触发 + } + else + { + SCR_Send("page4.p3.pic=35\xff\xff\xff"); //35为正常 + } + //afe放电高温&环境放电高温&电芯放电高温 + if(((bmsMem_slave.bStatus2 & 0x0008) != 0) || ((bmsMem_slave.temperaStatus & 0x0200) != 0) || ((bmsMem_slave.temperaStatus & 0x0002) != 0)) + { + SCR_Send("page4.p4.pic=38\xff\xff\xff"); //38为触发 + } + else + { + SCR_Send("page4.p4.pic=37\xff\xff\xff"); //37为正常 + } + //异常高压 + if((bmsMem_slave.bStatus1 & 0x0040) != 0) + { + SCR_Send("page4.p5.pic=40\xff\xff\xff"); //40为触发 + } + else + { + SCR_Send("page4.p5.pic=39\xff\xff\xff"); //39为正常 + } + //单体欠压 + if((bmsMem_slave.bStatus1 & 0x0002) != 0) + { + SCR_Send("page4.p6.pic=42\xff\xff\xff"); //42为触发 + } + //总体欠压 + else if((bmsMem_slave.bStatus1 & 0x0200) != 0) + { + SCR_Send("page4.p6.pic=159\xff\xff\xff"); //159为触发 + } + else + { + SCR_Send("page4.p6.pic=41\xff\xff\xff"); //41为正常 + } + //afe放电过流&放电过流1&放电过流2 + if(((bmsMem_slave.bStatus1 & 0x000c) != 0) || ((bmsMem_slave.temperaStatus & 0x0020) != 0) || ((bmsMem_slave.bStatus1 & 0x0400) != 0)) + { + SCR_Send("page4.p7.pic=44\xff\xff\xff"); //44为触发 + } + else + { + SCR_Send("page4.p7.pic=43\xff\xff\xff"); //43为正常 + } + //afe充电低温&环境充电低温&电芯充电低温 + if(((bmsMem_slave.bStatus2 & 0x0001) != 0) || ((bmsMem_slave.temperaStatus & 0x0400) != 0) || ((bmsMem_slave.temperaStatus & 0x0004) != 0)) + { + SCR_Send("page4.p8.pic=46\xff\xff\xff"); //46为触发 + } + else + { + SCR_Send("page4.p8.pic=45\xff\xff\xff"); //45为正常 + } + //afe放电低温&环境放电低温&电芯放电低温 + if(((bmsMem_slave.bStatus2 & 0x0004) != 0) || ((bmsMem_slave.temperaStatus & 0x0800) != 0) || ((bmsMem_slave.temperaStatus & 0x0008) != 0)) + { + SCR_Send("page4.p9.pic=48\xff\xff\xff"); //48为触发 + } + else + { + SCR_Send("page4.p9.pic=47\xff\xff\xff"); //47为正常 + } + //低压禁止充电 + if((bmsMem_slave.bStatus3 & 0x0008) != 0) + { + SCR_Send("page4.p10.pic=50\xff\xff\xff"); //50为触发 + } + else + { + SCR_Send("page4.p10.pic=49\xff\xff\xff"); //49为正常 + } + //真短路保护 + if((bmsMem_slave.bStatus2 & 0x0010) != 0) //只有预充情况才会出现短路锁定，出现则一直保持，这里也一直显示 + { + SCR_Send("page4.p11.pic=52\xff\xff\xff"); //52为触发 + } + //浪涌短路保护 + else if((bmsMem_slave.bStatus1 & 0x0020) != 0) + { + SCR_Send("page4.p11.pic=52\xff\xff\xff"); //52为触发 + } + else + { + SCR_Send("page4.p11.pic=51\xff\xff\xff"); //51为正常 + } +} + +//报警记录显示 +void SCR_Send_RecordInfo(void) +{ + uint8_t i; + uint8_t adrh, adrl; + uint32_t ee_index[3]; + uint16_t ee_pc[3]; + + ee_index[0] = read_index; + ee_index[1] = read_index + 1; + ee_index[2] = read_index + 2; + for(i=0; i<3; i++) ee_pc[i] = 0x1000 + 0x40 * ee_index[i]; + + // 发送最新索引 (t1) 和总数 (t2) + uint16_t latest; + if (soe.num == 0) + { + latest = 0; + } + else + { + latest = (soe.index % 100 == 0) ? 100 : soe.index % 100; + } + SCR_Send("page17.t1.txt=\"%d\"\xff\xff\xff", latest); + SCR_Send("page17.t2.txt=\"%d\"\xff\xff\xff", soe.num); + + for(i=0; i<3; i++) + { + uint8_t row = i; // 0=第一列, 1=第二列, 2=第三列 + uint16_t seq = ee_index[i] + 1; // 序号从1显示 + + if(ee_index[i] < soe.num) + { + // 读EEPROM + adrh = (ee_pc[i] >> 8) & 0xFF; + adrl = ee_pc[i] & 0xFF; + EEPROM_RdMulByte(adrh, adrl, 52, recordBuf); + delay_ms(5); + + if(recordBuf[0]==0xFF && recordBuf[1]==0xFF && + recordBuf[2]==0xFF && recordBuf[3]==0xFF) + { + // 无数据，清空+遮挡 + Set_Row_Hide(row, 1); + Send_Record_Blank(row); + } + else + { + Set_Row_Hide(row, 0); + // 发送序号 + if(row==0) SCR_Send("page17.t3.txt=\"%d\"\xff\xff\xff", seq); + if(row==1) SCR_Send("page17.t4.txt=\"%d\"\xff\xff\xff", seq); + if(row==2) SCR_Send("page17.t5.txt=\"%d\"\xff\xff\xff", seq); + + // 发送时间 (BCD转字符串) + char time_str[20]; + sprintf(time_str, "20%02x-%02x-%02x %02x:%02x:%02x", + recordBuf[4], recordBuf[5], recordBuf[6], + recordBuf[7], recordBuf[8], recordBuf[9]); + if(row==0) SCR_Send("page17.t6.txt=\"%s\"\xff\xff\xff", time_str); + if(row==1) SCR_Send("page17.t8.txt=\"%s\"\xff\xff\xff", time_str); + if(row==2) SCR_Send("page17.t10.txt=\"%s\"\xff\xff\xff", time_str); + + // 发送报警描述 + SCR_Send_Record(row); // 改造该函数为写入 sendRecord 后通过 SCR_Send 发送 + } + } + else + { + // 超出总记录数，清空+遮挡 + Set_Row_Hide(row, 1); + Send_Record_Blank(row); + } + } + + // 遮挡序号2/3图标 + SCR_Send("page17.p0.pic=%d\xff\xff\xff", (ee_index[1] < soe.num) ? 154 : 153); + SCR_Send("page17.p1.pic=%d\xff\xff\xff", (ee_index[2] < soe.num) ? 154 : 153); +} + +//用于主机查看从机的报警记录(暂直接显示空白和数据0) +void SCR_Send_Slave_RecordBank(void) +{ + // t1, t2 显示 0 + SCR_Send("page17.t1.txt=\"0\"\xff\xff\xff"); + SCR_Send("page17.t2.txt=\"0\"\xff\xff\xff"); + // 三行全遮挡 + for(uint8_t row = 0; row < 3; row++) + { + Set_Row_Hide(row, 1); + Send_Record_Blank(row); + } + // 遮挡序号2/3图标 + SCR_Send("page17.p0.pic=153\xff\xff\xff"); + SCR_Send("page17.p1.pic=153\xff\xff\xff"); + // 删除成功图标隐藏 + SCR_Send("page17.p5.pic=154\xff\xff\xff"); + +} + +//协议选择 OK +void SCR_DispProcotol(void) +{ + uint8_t tmpRd; + + EEPROM_RdMulByte(EE_PROTOCOL,&tmpRd); + protocol = tmpRd; + + //Sol-Ark + if(protocol == 1) + { + SCR_Send("page6.p1.pic=54\xff\xff\xff"); + } + else + { + SCR_Send("page6.p1.pic=53\xff\xff\xff"); + } + //GoodWe + if(protocol == 2) + { + SCR_Send("page6.p2.pic=56\xff\xff\xff"); + } + else + { + SCR_Send("page6.p2.pic=55\xff\xff\xff"); + } + //Megarevo + if(protocol == 30) + { + SCR_Send("page6.p3.pic=58\xff\xff\xff"); + } + else + { + SCR_Send("page6.p3.pic=57\xff\xff\xff"); + } + //Pylon + if(protocol == 12) + { + SCR_Send("page6.p4.pic=60\xff\xff\xff"); + } + else + { + SCR_Send("page6.p4.pic=59\xff\xff\xff"); + } + //Deye + if(protocol == 11) + { + SCR_Send("page6.p5.pic=62\xff\xff\xff"); + } + else + { + SCR_Send("page6.p5.pic=61\xff\xff\xff"); + } + //MUST + if(protocol == 7) + { + SCR_Send("page6.p6.pic=64\xff\xff\xff"); + } + else + { + SCR_Send("page6.p6.pic=63\xff\xff\xff"); + } + //solis + if(protocol == 37) + { + SCR_Send("page6.p7.pic=66\xff\xff\xff"); + } + else + { + SCR_Send("page6.p7.pic=65\xff\xff\xff"); + } + //Growatt + if(protocol == 3) + { + SCR_Send("page6.p8.pic=68\xff\xff\xff"); + } + else + { + SCR_Send("page6.p8.pic=67\xff\xff\xff"); + } + //Aiswei + if(protocol == 4) + { + SCR_Send("page6.p9.pic=70\xff\xff\xff"); + } + else + { + SCR_Send("page6.p9.pic=69\xff\xff\xff"); + } + //Afore + if(protocol == 35) + { + SCR_Send("page6.p10.pic=72\xff\xff\xff"); + } + else + { + SCR_Send("page6.p10.pic=71\xff\xff\xff"); + } + //Victron + if(protocol == 27) + { + SCR_Send("page6.p11.pic=74\xff\xff\xff"); + } + else + { + SCR_Send("page6.p11.pic=73\xff\xff\xff"); + } + //Sorotec + if(protocol == 6) + { + SCR_Send("page6.p12.pic=76\xff\xff\xff"); + } + else + { + SCR_Send("page6.p12.pic=75\xff\xff\xff"); + } + //SMA + if(protocol == 5) + { + SCR_Send("page7.p1.pic=78\xff\xff\xff"); + } + else + { + SCR_Send("page7.p1.pic=77\xff\xff\xff"); + } + //Sunways + if(protocol == 39) + { + SCR_Send("page7.p2.pic=80\xff\xff\xff"); + } + else + { + SCR_Send("page7.p2.pic=79\xff\xff\xff"); + } + //Luxpower + if(protocol == 23) + { + SCR_Send("page7.p3.pic=82\xff\xff\xff"); + } + else + { + SCR_Send("page7.p3.pic=81\xff\xff\xff"); + } + //Schneider + if(protocol == 24) + { + SCR_Send("page7.p4.pic=84\xff\xff\xff"); + } + else + { + SCR_Send("page7.p4.pic=83\xff\xff\xff"); + } + //AlpSolarr + if(protocol == 40) + { + SCR_Send("page7.p5.pic=86\xff\xff\xff"); + } + else + { + SCR_Send("page7.p5.pic=85\xff\xff\xff"); + } + //SRNE + if(protocol == 13) + { + SCR_Send("page7.p6.pic=88\xff\xff\xff"); + } + else + { + SCR_Send("page7.p6.pic=87\xff\xff\xff"); + } + //Voltronic + if(protocol == 14) + { + SCR_Send("page7.p7.pic=90\xff\xff\xff"); + } + else + { + SCR_Send("page7.p7.pic=89\xff\xff\xff"); + } + //COSUPER + if(protocol == 32) + { + SCR_Send("page7.p8.pic=92\xff\xff\xff"); + } + else + { + SCR_Send("page7.p8.pic=91\xff\xff\xff"); + } + //SMK + if(protocol == 17) + { + SCR_Send("page7.p9.pic=94\xff\xff\xff"); + } + else + { + SCR_Send("page7.p9.pic=93\xff\xff\xff"); + } + //SAKO + if(protocol == 31) + { + SCR_Send("page7.p10.pic=96\xff\xff\xff"); + } + else + { + SCR_Send("page7.p10.pic=95\xff\xff\xff"); + } + //SNADI + if(protocol == 18) + { + SCR_Send("page7.p11.pic=98\xff\xff\xff"); + } + else + { + SCR_Send("page7.p11.pic=97\xff\xff\xff"); + } + //invt + if(protocol == 21) + { + SCR_Send("page7.p12.pic=100\xff\xff\xff"); + } + else + { + SCR_Send("page7.p12.pic=99\xff\xff\xff"); + } +// //备选 +// if(protocol == 25) +// { +// SCR_Send("page8.p1.pic=102\xff\xff\xff"); +// } +// else +// { +// SCR_Send("page8.p1.pic=101\xff\xff\xff"); +// } +// //备选2 +// if(protocol == 26) +// { +// SCR_Send("page8.p2.pic=104\xff\xff\xff"); +// } +// else +// { +// SCR_Send("page8.p2.pic=103\xff\xff\xff"); +// } + + if((protocol <= 0) || (protocol > 50)) + { + //默认Sol-Ark + protocol = 1; + } +} + +//显示总数据 OK +void SCR_Send_TotalInfo(void) +{ + uint16_t voltage; + int16_t current; + + uint16_t totalCapacity; + uint16_t capacity; + uint8_t soc; + + int32_t export_P; + uint16_t total_W,remain_W,cumuli_W; + + uint16_t remain_T; //充放电剩余时间 + + voltage = bmsMem.packVoltage /100; //总电压，单位0.1V + current = canMem[0].cur /10; //总电流，单位0.1A + totalCapacity = 10 * ncc_Ah * OnlineNum; //总额定容量，单位0.1Ah + capacity = totalCapacity * canMem[0].soc /100; //总当前容量，单位0.1Ah + soc = canMem[0].soc; //平均soc + + export_P = voltage*current/10; //当前消耗功率=总电压x总电流，单位0.1W=10*(0.1V*0.1A) + total_W = totalCapacity*(3.2*bmsMem.ucCellNum)/1000; //额定能量=额定总容量x额定电压，单位0.1kWh=1000*(0.1Ah*1V) + remain_W = capacity*(3.2*bmsMem.ucCellNum)/1000; //剩余能量=当前总容量x额定电压，单位0.1kWh=1000*(0.1Ah*1V) + cumuli_W = (canMem[0].cycleCnt*fcc_Ah+canMem[0].cumuliCap)*(3.2*bmsMem.ucCellNum)/100/1000; //累积消耗能量=(总循环次数1x单PACK额定容量Ah+总累积消耗容量Ah)x额定电压V，单位0.1MWh=100000*1Wh + + //Page19 总数据页 + SCR_Send("page19.t1.txt=\"%.1f\"\xff\xff\xff", (float)voltage/10); //总电压 0.1V + SCR_Send("page19.t2.txt=\"%.1f\"\xff\xff\xff", (float)export_P/10); //总功率 0.1W + SCR_Send("page19.t3.txt=\"%.1f\"\xff\xff\xff", (float)current/10); //总电流 0.1A + SCR_Send("page19.t4.txt=\"%.1f\"\xff\xff\xff", (float)remain_W/10); //剩余容量 0.1kWh + SCR_Send("page19.t5.txt=\"%.1f\"\xff\xff\xff", (float)total_W/10); //额定容量 0.1kWh + SCR_Send("page19.t6.txt=\"%.1f\"\xff\xff\xff", (float)cumuli_W/10); //功率总耗 0.1Mwh + SCR_Send("page19.t8.txt=\"%d\"\xff\xff\xff", soc);//总SOC + + if(current >= 5) //充电0.5A + { + remain_T = (totalCapacity - capacity)*10/current; //充电剩余时间=(额定总容量-当前总容量)0.1Ah/总电流0.1A，单位0.1h=0.1*0.1Ah/0.1A + SCR_Send("page19.t7.txt=\"%.1f\"\xff\xff\xff", (float)remain_T);//剩余时间 0.1h + } + else if(current <= (-5)) //放电0.5A + { + remain_T = capacity*10/(-current); //放电剩余时间=当前总容量0.1Ah/总电流0.1A，单位0.1h=0.1*0.1Ah/0.1A + SCR_Send("page19.t7.txt=\"%.1f\"\xff\xff\xff", (float)remain_T);//剩余时间 0.1h + } + else //待机状态 + { + SCR_Send("page19.t7.txt=\"%d\"\xff\xff\xff", 0);//剩余时间 0 + } +} + +//显示自身基本信息 OK +void SCR_Send_Self_BasicInfo(void) +{ + static uint8_t last_alarm_stat = 0; + + uint16_t voltage; + int16_t current; + int32_t power; + uint16_t capacity; + uint16_t remain_T; + + voltage = bmsMem.packVoltage /100; //电压，1位小数 + current = bmsMem.packCurrent /100; //电流，1位小数 + power = voltage * current /10; //功率，1位小数 + capacity = bmsMem.rcc/3600 /100; //容量，1位小数 + + //发送数据到屏幕 + SCR_Send("page1.t0.txt=\"%d\"\xff\xff\xff", bmsMem.E2_485Addr); + SCR_Send("page1.t1.txt=\"%.1f\"\xff\xff\xff", (float)voltage/10); + SCR_Send("page1.t2.txt=\"%.1f\"\xff\xff\xff", (float)power/10); + SCR_Send("page1.t3.txt=\"%.1f\"\xff\xff\xff", (float)current/10); + SCR_Send("page1.t4.txt=\"%.1f\"\xff\xff\xff", (float)capacity/10); + SCR_Send("page1.t5.txt=\"%.1f\"\xff\xff\xff", (float)(TemperatureAverage - 2731)/10); + SCR_Send("page1.t6.txt=\"%d\"\xff\xff\xff", bmsMem.soc); + SCR_Send("page1.t7.txt=\"%d\"\xff\xff\xff", bmsMem.can_cycleCnt); + + SCR_Send("page2.t0.txt=\"%d\"\xff\xff\xff", bmsMem.E2_485Addr); + SCR_Send("page2.t1.txt=\"%d\"\xff\xff\xff", cellVol[0]); + SCR_Send("page2.t2.txt=\"%d\"\xff\xff\xff", cellVol[1]); + SCR_Send("page2.t3.txt=\"%d\"\xff\xff\xff", cellVol[2]); + SCR_Send("page2.t4.txt=\"%d\"\xff\xff\xff", cellVol[3]); + SCR_Send("page2.t5.txt=\"%d\"\xff\xff\xff", cellVol[4]); + SCR_Send("page2.t6.txt=\"%d\"\xff\xff\xff", cellVol[5]); + SCR_Send("page2.t7.txt=\"%d\"\xff\xff\xff", cellVol[6]); + SCR_Send("page2.t8.txt=\"%d\"\xff\xff\xff", cellVol[7]); + SCR_Send("page2.t9.txt=\"%d\"\xff\xff\xff", cellVol[8]); + SCR_Send("page2.t10.txt=\"%d\"\xff\xff\xff", cellVol[9]); + SCR_Send("page2.t11.txt=\"%d\"\xff\xff\xff", cellVol[10]); + SCR_Send("page2.t12.txt=\"%d\"\xff\xff\xff", cellVol[11]); + SCR_Send("page2.t13.txt=\"%d\"\xff\xff\xff", cellVol[12]); + SCR_Send("page2.t14.txt=\"%d\"\xff\xff\xff", cellVol[13]); + SCR_Send("page2.t15.txt=\"%d\"\xff\xff\xff", cellVol[14]); + SCR_Send("page2.t16.txt=\"%d\"\xff\xff\xff", cellVol[15]); + + SCR_Send("page3.t0.txt=\"%d\"\xff\xff\xff", bmsMem.E2_485Addr); + SCR_Send("page3.t1.txt=\"%.1f\"\xff\xff\xff", (float)(bmsMem.mcu_T1 - 2731)/10); + SCR_Send("page3.t2.txt=\"%.1f\"\xff\xff\xff", (float)(bmsMem.mcu_T2 - 2731)/10); + SCR_Send("page3.t3.txt=\"%.1f\"\xff\xff\xff", (float)(bmsMem.mcu_T3 - 2731)/10); + SCR_Send("page3.t4.txt=\"%.1f\"\xff\xff\xff", (float)(bmsMem.mcu_T4 - 2731)/10); + SCR_Send("page3.t5.txt=\"%.1f\"\xff\xff\xff", (float)(bmsMem.afe_T3 - 2731)/10); //环境温度 + SCR_Send("page3.t6.txt=\"%.1f\"\xff\xff\xff", (float)(bmsMem.afe_T1 - 2731)/10); //接线柱温度1 + SCR_Send("page3.t7.txt=\"%.1f\"\xff\xff\xff", (float)(bmsMem.afe_T2 - 2731)/10); //接线柱温度2 + + if(bAlarmFlag == 0) //无屏幕上的报警 + { + // 仅在从报警状态恢复时，才清除报警页图标 + if(last_alarm_stat != 0) + { + SCR_ClearAlarm(); + } + last_alarm_stat = 0; + + if((bmsMem.temperaStatus & 0x40) !=0) //急停 + { + SCR_Send("page1.p1.pic=27\xff\xff\xff"); //27为急停 + } + else if((bmsMem.bStatus2 & 0xe0) !=0) + { + SCR_Send("page1.p1.pic=26\xff\xff\xff"); //26为报警 + } + else + { + if(bSTANDBY == 1) + { + SCR_Send("page1.p1.pic=25\xff\xff\xff"); //25为待机 + } + else if(bCHGING ==1) + { + if((bmsMem.balanceStatus & 0x10) != 0) + { + SCR_Send("page1.p1.pic=28\xff\xff\xff"); //28为限流 + } + else + { + SCR_Send("page1.p1.pic=23\xff\xff\xff"); //23为充电 + } + } + else + { + SCR_Send("page1.p1.pic=24\xff\xff\xff"); //24为放电 + } + } + SCR_ClearAlarm(); + } + else + { + last_alarm_stat = 1; // 记录本次有报警 + SCR_Send("page1.p1.pic=26\xff\xff\xff"); //“Fault”(屏幕上的报警) + + if(bAlarmFlagOld ==0) + { + bAlarmFlagOld = 1; + SCR_JumpToAlarm(); + } + SCR_ShowAlarm(); + } + + if(current >= 5) //充电0.5A + { + remain_T = (fcc - bmsMem.rcc)/36000/current; //充电剩余时间=((额定总容量-当前总容量mAS)/36000)/总电流，单位0.1h=0.01Ah/0.1A + SCR_Send("page1.t8.txt=\"%.1f\"\xff\xff\xff", (float)remain_T);//剩余时间 0.1h + } + else if(current <= (-5)) //放电0.5A + { + remain_T = bmsMem.rcc/36000/(-current); //放电剩余时间=当前总容量mAS/36000/总电流，单位0.1h=0.01Ah/0.1A + SCR_Send("page1.t8.txt=\"%.1f\"\xff\xff\xff", (float)remain_T);//剩余时间 0.1h + } + else//待机状态 + { + SCR_Send("page1.t8.txt=\"%d\"\xff\xff\xff", 0);//剩余时间 0 + } + + //均衡状态 + if(balancing ==1) + { + SCR_Send("page1.p2.pic=29\xff\xff\xff"); //29为开启 + } + else + { + SCR_Send("page1.p2.pic=30\xff\xff\xff"); //30为关闭 + } +} + +void SCR_Send_Slave_BasicInfo(void) +{ + uint16_t voltage; + int16_t current; + int32_t power; + uint16_t capacity; + uint8_t soc; + + uint16_t Ave_Temp; //平均温度 + + uint16_t remain_T; //充放电剩余时间 + + voltage = bmsMem_slave.packVoltage /100; //电压，单位0.1V + current = bmsMem_slave.packCurrent /100; //电流，单位0.1A + power = voltage * current /10; //功率，1位小数 + capacity = bmsMem_slave.rcc/360000; //当前容量，单位0.1Ah + Ave_Temp = (bmsMem_slave.mcu_T1 + bmsMem_slave.mcu_T2 + bmsMem_slave.mcu_T3 + bmsMem_slave.mcu_T4)/4; + soc = bmsMem_slave.soc; //平均SOC + + //发送数据到屏幕 + SCR_Send("page1.t1.txt=\"%.1f\"\xff\xff\xff", (float)voltage/10); + SCR_Send("page1.t2.txt=\"%.1f\"\xff\xff\xff", (float)power/10); + SCR_Send("page1.t3.txt=\"%.1f\"\xff\xff\xff", (float)current/10); + SCR_Send("page1.t4.txt=\"%.1f\"\xff\xff\xff", (float)capacity/10); + SCR_Send("page1.t5.txt=\"%.1f\"\xff\xff\xff", (float)(Ave_Temp - 2731)/10); + SCR_Send("page1.t6.txt=\"%d\"\xff\xff\xff", soc); + SCR_Send("page1.t7.txt=\"%d\"\xff\xff\xff", bmsMem.can_cycleCnt); + + SCR_Send("page2.t1.txt=\"%d\"\xff\xff\xff", (int16_t)(bmsMem_slave.vCell[0]*32/5)*5/32); + SCR_Send("page2.t2.txt=\"%d\"\xff\xff\xff", (int16_t)(bmsMem_slave.vCell[1]*32/5)*5/32); + SCR_Send("page2.t3.txt=\"%d\"\xff\xff\xff", (int16_t)(bmsMem_slave.vCell[2]*32/5)*5/32); + SCR_Send("page2.t4.txt=\"%d\"\xff\xff\xff", (int16_t)(bmsMem_slave.vCell[3]*32/5)*5/32); + SCR_Send("page2.t5.txt=\"%d\"\xff\xff\xff", (int16_t)(bmsMem_slave.vCell[4]*32/5)*5/32); + SCR_Send("page2.t6.txt=\"%d\"\xff\xff\xff", (int16_t)(bmsMem_slave.vCell[5]*32/5)*5/32); + SCR_Send("page2.t7.txt=\"%d\"\xff\xff\xff", (int16_t)(bmsMem_slave.vCell[6]*32/5)*5/32); + SCR_Send("page2.t8.txt=\"%d\"\xff\xff\xff", (int16_t)(bmsMem_slave.vCell[7]*32/5)*5/32); + SCR_Send("page2.t9.txt=\"%d\"\xff\xff\xff", (int16_t)(bmsMem_slave.vCell[8]*32/5)*5/32); + SCR_Send("page2.t10.txt=\"%d\"\xff\xff\xff", (int16_t)(bmsMem_slave.vCell[9]*32/5)*5/32); + SCR_Send("page2.t11.txt=\"%d\"\xff\xff\xff", (int16_t)(bmsMem_slave.vCell[10]*32/5)*5/32); + SCR_Send("page2.t12.txt=\"%d\"\xff\xff\xff", (int16_t)(bmsMem_slave.vCell[11]*32/5)*5/32); + SCR_Send("page2.t13.txt=\"%d\"\xff\xff\xff", (int16_t)(bmsMem_slave.vCell[12]*32/5)*5/32); + SCR_Send("page2.t14.txt=\"%d\"\xff\xff\xff", (int16_t)(bmsMem_slave.vCell[13]*32/5)*5/32); + SCR_Send("page2.t15.txt=\"%d\"\xff\xff\xff", (int16_t)(bmsMem_slave.vCell[14]*32/5)*5/32); + SCR_Send("page2.t16.txt=\"%d\"\xff\xff\xff", (int16_t)(bmsMem_slave.vCell[15]*32/5)*5/32); + + SCR_Send("page3.t1.txt=\"%.1f\"\xff\xff\xff", (float)(bmsMem_slave.mcu_T1 - 2731)/10); + SCR_Send("page3.t2.txt=\"%.1f\"\xff\xff\xff", (float)(bmsMem_slave.mcu_T2 - 2731)/10); + SCR_Send("page3.t3.txt=\"%.1f\"\xff\xff\xff", (float)(bmsMem_slave.mcu_T3 - 2731)/10); + SCR_Send("page3.t4.txt=\"%.1f\"\xff\xff\xff", (float)(bmsMem_slave.mcu_T4 - 2731)/10); + SCR_Send("page3.t5.txt=\"%.1f\"\xff\xff\xff", (float)(bmsMem_slave.afe_T3 - 2731)/10); //环境温度 + SCR_Send("page3.t6.txt=\"%.1f\"\xff\xff\xff", (float)(bmsMem_slave.afe_T1 - 2731)/10); //接线柱温度1 + SCR_Send("page3.t7.txt=\"%.1f\"\xff\xff\xff", (float)(bmsMem_slave.afe_T2 - 2731)/10); //接线柱温度2 + + //首页的状态显示and报警跳转 + if(((bmsMem_slave.bStatus1 & 0x7e)==0) && ((bmsMem_slave.bStatus2 & 0x0f) ==0) && ((bmsMem_slave.bStatus3 & 0x18) ==0) && ((bmsMem_slave.temperaStatus & 0x3f) ==0) ) //无屏幕上的报警 + { + if(((bmsMem_slave.bStatus1 & 0x01) != 0) && (bmsMem_slave.soc<99) ) //过压报警的判断：满电时发生[过压保护],屏幕不显示过压 + { + SCR_Send("page1.p1.pic=26\xff\xff\xff"); //“Fault”(屏幕上的报警) + + //从机报警的跳转 + if(bAlarmFlagOld_slave == 0) + { + bAlarmFlagOld_slave = 1; + SCR_JumpToAlarm(); + } + SCR_ShowAlarm_Slave(); + } + else + { + if((bmsMem_slave.temperaStatus & 0x40) !=0) + { + SCR_Send("page1.p1.pic=27\xff\xff\xff"); //27为急停 + } + else if((bmsMem_slave.bStatus2 & 0xe0) !=0) + { + SCR_Send("page1.p1.pic=26\xff\xff\xff"); //“Fault”(屏幕上的报警) + } + else + { + if(bmsMem_slave.packCurrent > 100) + { + if((bmsMem.balanceStatus & 0x10) != 0) + { + SCR_Send("page1.p1.pic=28\xff\xff\xff"); //28为限流 + } + else + { + SCR_Send("page1.p1.pic=23\xff\xff\xff"); //23为充电 + } + } + else if(bmsMem_slave.packCurrent < (-100)) + { + SCR_Send("page1.p1.pic=24\xff\xff\xff"); //24为放电 + } + else + { + SCR_Send("page1.p1.pic=25\xff\xff\xff"); //25为待机 + } + } + bAlarmFlagOld_slave = 0; + SCR_ClearAlarm(); + } + } + else + { + SCR_Send("page1.p1.pic=26\xff\xff\xff"); //“Fault”(屏幕上的报警) + //从机报警的跳转 + if(bAlarmFlagOld_slave ==0) + { + bAlarmFlagOld_slave = 1; + SCR_JumpToAlarm(); + } + SCR_ShowAlarm_Slave(); + } + + //均衡状态 + if((bmsMem_slave.balanceStatus & 0x01) !=0) + { + SCR_Send("page1.p2.pic=29\xff\xff\xff"); //29为开启 + } + else + { + SCR_Send("page1.p2.pic=30\xff\xff\xff"); //30为关闭 + } + + + if(current >= 5) //充电0.5A + { + remain_T = (fcc - bmsMem_slave.rcc)/36000/current; //充电剩余时间=((额定总容量-当前总容量mAS)/36000)/总电流，单位0.1h=0.01Ah/0.1A + SCR_Send("page1.t8.txt=\"%.1f\"\xff\xff\xff", (float)remain_T);//剩余时间 0.1h + } + else if(current <= (-5)) //放电0.5A + { + remain_T = bmsMem_slave.rcc/36000/(-current); //放电剩余时间=当前总容量mAS/36000/总电流，单位0.1h=0.01Ah/0.1A + SCR_Send("page1.t8.txt=\"%.1f\"\xff\xff\xff", (float)remain_T);//剩余时间 0.1h + } + else//待机状态 + { + SCR_Send("page1.t8.txt=\"%d\"\xff\xff\xff", 0);//剩余时间 0 + } +} + +//定时发送数据，1s1次 +void Screen_IQ_Transmit(void) +{ + uint16_t scv,sct; //用于显示短路参数 + + /**** 时间显示 ****/ + SCR_Send_Time(); //系统时间 + + + /**** 汇总信息 ****/ + if(bmsMem.E2_485Addr == 1) + { + SCR_Send_TotalInfo(); //显示总数据 + } + /**** 基本信息 ****/ + if((bmsMem.E2_485Addr != 1) || (scr_RdData_Index == 1)) //当前是从机或主机自身，一直显示自身数据 + { + SCR_Send_Self_BasicInfo(); + } + else //当前是主机，可显示自身数据或所选从机数据 + { + SCR_Send_Slave_BasicInfo(); + } + + + /**** 删除记录的显示 ****/ + if((SCR_HistoryFlag == 1) && (clearFlag == 1)) + { + if(clearFlag_timer > 0) + { + SCR_Send("page17.p5.pic=152\xff\xff\xff"); // 显示删除成功图标 + clearFlag_timer--; + } + else + { + SCR_Send("page17.p5.pic=154\xff\xff\xff"); // 隐藏成功图标 + clearFlag = 0; // 标志复位 + SCR_HistoryFlag = 0; + } + } + + + /**** 欠压保护恢复倒计时的显示 ****/ + if((bmsMem.balanceStatus & 0x20) != 0) + { + uint16_t time; + + //正常情况下，在RTC时钟里计算 + if(LSEErrFlag == 0) + time = uvofftime; + //若RTC遇到问题，在定时器里计算 + else + time = uvoff_Moni_Count/100; + + uint8_t min = time / 60; + uint8_t sec = time % 60; + SCR_Send("page12.t1.txt=\"%02d:%02d\"\xff\xff\xff", min, sec); + } + else + { + SCR_Send("page12.b0.pic=105\xff\xff\xff"); // 恢复默认图标 + SCR_Send("page12.t1.txt=\" \"\xff\xff\xff"); + } + + + /**** 并机图标根据地址显示 ****/ + if(bmsMem.E2_485Addr == 1) + { + SCR_Send("page1.p3.pic=150\xff\xff\xff"); //150为并机 + } + else + { + SCR_Send("page1.p3.pic=149\xff\xff\xff"); //149不并机 + } + /**** 电池并机页显示 ****/ + //显示当前正在轮询还是正在分配 + if(SCR_ParallelFlag == 1) + { + #if Addr_SetAuto + if((paraMem.addr_FREE_Flg == 0) && ((assignAddr_State == 0) || (assignAddr_State == 1))) + { + SCR_Send("page18.p0.pic=146\xff\xff\xff"); //146为分配 + } + else + #endif + if(ConfigData_Index == 1) //除了上位机读数据的其他时候 + { + SCR_Send("page18.p0.pic=145\xff\xff\xff"); //145为轮询 + } + else + { + SCR_Send("page18.p0.pic=144\xff\xff\xff"); //144为空 + } + + for(int i = 1; i <= 16; i++) + { + int picId; + if(onlineMem.Online[i] == 0xAA) + { + picId = 110 + i * 2; // 在线 + } + else if(onlineMem.Online[i] == 0xBB) + { + picId = 111 + i * 2; // 报警 + } + else + { + picId = 111; // 空 + } + char cmd[32]; + sprintf(cmd, "page18.p%d.pic=%d\xff\xff\xff", i, picId); + SCR_Send(cmd); + } + if(SCR_PACKFlag == 1) + { + SCR_ParallelFlag = 0; + SCR_PACKFlag = 0; + SCR_Send("page page1\xff\xff\xff"); //跳转到page1数据页 + } + } + + + /**** 历史记录显示 ****/ + //在首页，历史记录按钮只有主机1显示 + if(bmsMem.E2_485Addr == 1) + { + SCR_Send("page1.p0.pic=147\xff\xff\xff"); //147为不遮挡历史 + } + else + { + SCR_Send("page1.p0.pic=148\xff\xff\xff"); //148为遮挡历史 + } + //历史记录页显示 + if(SCR_HistoryFlag == 1) + { + if((bmsMem.E2_485Addr != 1) || (scr_RdData_Index == 1)) //看自身数据 + { + SCR_Send_RecordInfo(); + } + else + { + SCR_Send_Slave_RecordBank(); + } + } + + + /**** 地址释放控制的打勾显示 ****/ + if(paraMem.addr_FREE_Flg == 1) + { + SCR_Send("page14.p1.pic=157\xff\xff\xff");//勾选 + } + else + { + SCR_Send("page14.p1.pic=156\xff\xff\xff");//取消 + } + /**** 地址与从机地址修改状态显示 ****/ + if(sdwa_WrAddr_Flg == 1) + { + SCR_Send("page14.t1.txt=\"%d\"\xff\xff\xff", 0); // 正在修改 + } + else if(sdwa_WrAddr_Flg == 2) + { + sdwa_WrAddr_Flg = 0; + canMem[scr_RdData_Index].com = 0; + canMem[sdwa_WrAddr].com = 1; + scr_RdData_Index = sdwa_WrAddr; // 切换查看 + SCR_Send("page14.t1.txt=\"%d\"\xff\xff\xff", sdwa_WrAddr); + } + else if(sdwa_WrAddr_Flg == 3) + { + sdwa_WrAddr_Flg = 0; + SCR_Send("page14.t1.txt=\"%d\"\xff\xff\xff", scr_RdData_Index); // 恢复 + } + else + { + if((bmsMem.E2_485Addr != 1) || (scr_RdData_Index == 1)) + { + SCR_Send("page14.t1.txt=\"%d\"\xff\xff\xff", bmsMem.E2_485Addr); + } + else + { + SCR_Send("page14.t1.txt=\"%d\"\xff\xff\xff", scr_RdData_Index); + } + } + + + #if LTE_Conn + /**** 4G状态显示 ****/ + if(LTEStatus_flg == 0) + { + if(LTE_WarmDelay > 0) + { + LTEStatus_flg = 1; + strcpy(LTEStatus_str, "wait 4G warm"); + } + else if(LTE_OTA_Flag == 1) //4G等待OTA升级 + { + LTEStatus_flg = 1; + strcpy(LTEStatus_str, "Upgrade loading"); + } + else if(MQTT_READY_flag == 1) //4G已在正常工作流程 + { + LTEStatus_flg = 1; + strcpy(LTEStatus_str, "working"); + } + else if((LTE_rssi > 0) && (LTE_rssi <= 13)) //出现问题：弱网环境 + { + LTEStatus_flg = 1; + strcpy(LTEStatus_str, "weak grid"); + } + else if(LTE_Onlineflag == 0xAA) //出现问题：4G联网错误 + { + LTEStatus_flg = 1; + strcpy(LTEStatus_str, "network exist fault"); + } + } + else + { + if((LTE_Rx_BufIndex == 0) && (CRESET_flag == 0) && (MQTT_RST_flag == 0)) + { + strcat(LTEStatus_str, " Null"); + } + } + + if(LTEStatus_flg == 1) + { + LTEStatus_flg = 0; + SCR_Send("page14.t3.txt=\"%s\"\xff\xff\xff", LTEStatus_str); + } + else + { + SCR_Send("page14.t3.txt=\" \"\xff\xff\xff"); + } + #endif + + + /**** 恢复出厂设置功能+完成图标显示 ****/ + if(factory_reset_flag == 1) + { + // 执行恢复默认参数 + //P1 + bmsMem.ee_scv_sct = 0x10; //80mV 0uS + bmsMem.inverter_chgVolLimit = 640; //60.4V + bmsMem.inverter_dsgVolLimit = 480; //48.0V + bmsMem.inverter_chgCurLimit = paraMem.alarm_occ * 10 - 100; //充电过流告警-10A + bmsMem.inverter_dsgCurLimit = paraMem.alarm_ocd1 * 10 - 100; //放电过流告警-10A + //P2 + bmsMem.ee_ocd1v_ocd1t = (bmsMem.ee_ocd1v_ocd1t & 0x0F) | 0x10; //30mV + bmsMem.ee_ocd2v_ocd2t = (bmsMem.ee_ocd2v_ocd2t & 0x0F) | 0x10; //40mV + bmsMem.ee_occv_occt = (bmsMem.ee_occv_occt & 0x0F) | 0x10; //30mV + bmsMem.mcu_occ = 0xCD; //充电过流 205A + bmsMem.mcu_ocd = 0xCD; //放电过流 205A + bmsMem.ee_ovt_ldrt_ovh = (bmsMem.ee_ovt_ldrt_ovh & 0xFC) | 0x02; + bmsMem.ee_ovl = 0xD0; //过压保护电压 0x2D0*5=3600mV + bmsMem.ee_uvt_ovrh = (bmsMem.ee_uvt_ovrh & 0xFC) | 0x02; + bmsMem.ee_ovrl = 0xA8; //过压保护释放 0x2A8*5=3400mV + bmsMem.ee_uv = 0x87; //欠压保护电压 0x87*20=2700mV + bmsMem.ee_uvr = 0x91; //欠压保护释放 0x91*20=2900mV + //P3 + bmsMem.mcu_otc = 0x3C; //充电高温 60 + bmsMem.mcu_otcr = 0x37; //充电高温释放 55 + bmsMem.mcu_utc = 0x00; //充电低温 0 + bmsMem.mcu_utcr = 0x05; //充电低温释放 5 + bmsMem.mcu_otd = 0x41; //放电高温 65 + bmsMem.mcu_otdr = 0x3C; //放电高温释放 60 + bmsMem.mcu_utd = 0xEC; //放电低温 -20 + bmsMem.mcu_utdr = 0xF1; //放电低温释放 -15 + + // 更新 Flash 和 AFE + if((MEMORY_UpdateFlash(FLASH_DATA_A_BASE) == 0) && (MEMORY_UpdateFlash(FLASH_DATA_B_BASE) == 0)) + { + bmsMem.packStatus &= ~BIT0; + if(MEMORY_UpdateAFE() == 0) + bmsMem.packStatus &= ~BIT1; + else + bmsMem.packStatus |= BIT1; + } + else + { + bmsMem.packStatus |= BIT0; + } + + factory_reset_flag = 2; + SCR_Send("page13.b0.pic=109\xff\xff\xff"); // 配置中 + } + else if(factory_reset_flag == 2) + { + // 延时一定时间后恢复默认图标（例如通过计数器） + static uint8_t reset_timer = 0; + reset_timer++; + if(reset_timer >= 3) // 3秒后恢复 + { + reset_timer = 0; + factory_reset_flag = 0; + SCR_Send("page13.b0.pic=108\xff\xff\xff");//默认 + } + else + { + SCR_Send("page13.b0.pic=110\xff\xff\xff"); // 成功图标 + } + } + + + /**** 参数显示 ****/ + SCR_Send_VER(); //地址、SN号、版本号 + SCR_DispProcotol(); //逆变器协议 + + //一屏多显，当前显示地址 + uint8_t dispAddr = (scr_RdData_Index == 1) ? bmsMem.E2_485Addr : scr_RdData_Index; + for (int p = 1; p <= 17; p++) + { + SCR_Send("page%d.t0.txt=\"%d\"\xff\xff\xff", p, dispAddr); + } + //额定容量 + SCR_Send("page14.t2.txt=\"%d\"\xff\xff\xff", bmsMem.ncc/3600/1000); + + + /**** 可设参数显示+正在设置图标 ****/ + if(flashUpdateFlag != 0) + { + uint8_t i; + uint8_t* data; + uint8_t temp[26]; //要计算校验码 + + if(flashUpdateFlag >= 2) //2代表修改单个参数，3代表初始化所有参数 》》但都需要计算CRC值 + { + data = (uint8_t *)&bmsMem.ee_sconf1; + for(i=0;i<25;i++) + { + temp[i] = *data; + data++; + } + temp[25] = CRC8_Cal(&temp[0],25); //更改对应校验值 + bmsMem.ee_tr = temp[25]; + + data = (uint8_t *)&bmsMem.mcu_otc; + for(i=0;i<13;i++) + { + temp[i] = *data; + data++; + } + temp[13] = CRC8_Cal(&temp[0],13); //更改对应校验值 + bmsMem.mcu_crc = temp[13]; + } + + //bmsMem中数据更新到FLASH A区和B区和AFE EEPORM + if((MEMORY_UpdateFlash(FLASH_DATA_A_BASE) == 0) && (MEMORY_UpdateFlash(FLASH_DATA_B_BASE) == 0)) + { + staPack.bits.flashUpdate= 0; + if(MEMORY_UpdateAFE() ==0) //更新AFE EEPROM内容 + { + staPack.bits.eepromUpdate = 0; + } + else + { + staPack.bits.eepromUpdate = 1; + } + } + else + { + staPack.bits.flashUpdate= 1; + } + bmsMem.packStatus = staPack.byte; + + //清空值 + flashUpdateFlag = 0; + } + else + { + //短路参数 + scv = (bmsMem.ee_scv_sct & 0xF0)>>4; + if(scv == 0x0B) + { + scv = 400; + } + else + { + scv = 50 + 30 * scv; + } + sct = 0 + 64*(bmsMem.ee_scv_sct & 0x0F); + + //Page9 + SCR_Send("page9.t1.txt=\"%.1f\"\xff\xff\xff", (float)bmsMem.inverter_chgCurLimit / 10); + SCR_Send("page9.t2.txt=\"%.1f\"\xff\xff\xff", (float)bmsMem.inverter_chgVolLimit / 10); + SCR_Send("page9.t3.txt=\"%.1f\"\xff\xff\xff", (float)bmsMem.inverter_dsgCurLimit / 10); + SCR_Send("page9.t4.txt=\"%.1f\"\xff\xff\xff", (float)bmsMem.inverter_dsgVolLimit / 10); + SCR_Send("page9.t5.txt=\"%d\"\xff\xff\xff", bmsMem.mcu_occ); + SCR_Send("page9.t6.txt=\"%d\"\xff\xff\xff", bmsMem.mcu_ocd); + + //Page10 + SCR_Send("page10.t1.txt=\"%d\"\xff\xff\xff", bmsMem.mcu_otc); + SCR_Send("page10.t2.txt=\"%d\"\xff\xff\xff", bmsMem.mcu_otcr); + SCR_Send("page10.t3.txt=\"%d\"\xff\xff\xff", bmsMem.mcu_utc); + SCR_Send("page10.t4.txt=\"%d\"\xff\xff\xff", bmsMem.mcu_utcr); + SCR_Send("page10.t5.txt=\"%d\"\xff\xff\xff", bmsMem.mcu_otd); + SCR_Send("page10.t6.txt=\"%d\"\xff\xff\xff", bmsMem.mcu_otdr); + SCR_Send("page10.t7.txt=\"%d\"\xff\xff\xff", bmsMem.mcu_utd); + SCR_Send("page10.t8.txt=\"%d\"\xff\xff\xff", bmsMem.mcu_utdr); + + //Page11 + SCR_Send("page11.t1.txt=\"%d\"\xff\xff\xff", 5* (((bmsMem.ee_ovt_ldrt_ovh & 0x03)<<8) + bmsMem.ee_ovl)); + SCR_Send("page11.t2.txt=\"%d\"\xff\xff\xff", 5* (((bmsMem.ee_uvt_ovrh & 0x03)<<8) + bmsMem.ee_ovrl)); + SCR_Send("page11.t3.txt=\"%d\"\xff\xff\xff", bmsMem.ee_uv *20); + SCR_Send("page11.t4.txt=\"%d\"\xff\xff\xff", bmsMem.ee_uvr * 20); + SCR_Send("page11.t5.txt=\"%d\"\xff\xff\xff", scv);//短路保护电压 + SCR_Send("page11.t6.txt=\"%d\"\xff\xff\xff", sct);//短路保护延时 + } +} + +//接收一帧数据,帧间断小于x ms仍然认为是一帧 +//定时器中断里进行接收数据解析并准备回送数据 +void Screen_IT_Update(void) +{ + uint8_t protocol_Index; //屏幕写入增多，加一层判断以减少写入协议选择的次数 + protocol_Index = protocol; + uint8_t tmpWr[2]; + + if(SCR_Rx_BufIndex >= 4) //按钮指令都是7字节，写参数指令至少5字节，休眠/退出休眠指令是4字节 + { + uint8_t i; + uint32_t temp = 0; //过程量(绝对值) + + //屏幕休眠唤醒 + if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_Sleep, 4)) + { + SCR_Send("page page1\xff\xff\xff"); // 唤醒跳转至首页 + if(sleep_flag == 1) + { + sleep_flag = 0; + SLEEP_Refresh(); + SLEEP2_Refresh(); + } + } + + //手动分配地址勾选 + if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_setADDR, 7)) + { + SCR_setADDRFlag = 1; + } + + //历史记录界面 + if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_Hide_History, 7)) + { + SCR_HistoryFlag = 1; + SCR_Send("page page17\xff\xff\xff"); // 只发一次跳转 + } + if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_up_History, 7)) //上翻页 + { + if(read_index >= 3) read_index -= 3; + else read_index = 0; + } + if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_down_History, 7)) //下翻页 + { + if(read_index + 3 < soe.num) read_index += 3; + } + if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_clean_History, 7)) + { + if(soe.num != 0) // 有记录才删除 + { + uint16_t i; + uint16_t pc; + uint8_t adrh, adrl; + uint8_t wrBuf[64]; + + //清空所有记录内容（填充0xFF） + memset(wrBuf, 0xFF, sizeof(wrBuf)); + pc = 0x1000; + for(i=0; i<100; i++) + { + adrh = (pc >> 8) & 0xFF; + adrl = pc & 0xFF; + EEPROM_WrMulByte(EE_SOE, wrBuf); // 使用EE_SOE宏，传入adrh,adrl + delay_ms(10); + pc += 0x40; + } + + //重置 soe 统计信息 + soe.index = 0; + soe.pc = 0x1000; + soe.num = 0; + wrBuf[0] = (soe.index >> 24) & 0xFF; + wrBuf[1] = (soe.index >> 16) & 0xFF; + wrBuf[2] = (soe.index >> 8) & 0xFF; + wrBuf[3] = soe.index & 0xFF; + wrBuf[4] = (soe.pc >> 8) & 0xFF; + wrBuf[5] = soe.pc & 0xFF; + wrBuf[6] = (soe.num >> 8) & 0xFF; + wrBuf[7] = soe.num & 0xFF; + EEPROM_WrMulByte(EE_SOE_INF, wrBuf); + delay_ms(10); + + //重置显示起始索引 + read_index = 0; + + //设置删除成功标志 + clearFlag = 1; // 已存在 + clearFlag_timer = 3; // 显示3秒 + } + } + + // 分配地址勾选 + if(SCR_setADDRFlag == 1) + { + SCR_setADDRFlag = 0; // 保证单次执行 + + if(paraMem.addr_FREE_Flg != 1) + { + paraMem.addr_FREE_Flg = 1; + + //若改为手动控制，则及时将当前地址写入EEPROM + tmpWr[0] = bmsMem.E2_485Addr; + EEPROM_WrMulByte(EE_ADDR,&tmpWr[0]); + delay_ms(5); + } + else + { + paraMem.addr_FREE_Flg = 0; + } + } + + // 欠压强制复位按钮 + if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_ForceDischarge, 7)) + { + SCR_Send("page12.b0.pic=106\xff\xff\xff"); // 配置中 + force_discharge_flag = 1; + + //当前总体和单体欠压的报警/保护位都置0 + bmsMem.bStatus1 &= ~0x0202; + bmsMem.bStatus3 &= ~0x0A00; + //状态位置1，更新计时起点 + bmsMem.balanceStatus |= 0x0020; + if(LSEErrFlag!=1) + { + uvofftimecount = RTC_GetCounter(); + uvofftime = 300; + } + else + { + uvoff_Moni_Count = UVOff_MON_CNT; + } + + SCR_Send("page12.b0.pic=107\xff\xff\xff"); // 成功启动，显示成功图标 + } + + // 恢复默认参数按钮 + if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_FactoryReset, 7)) + { + factory_reset_flag = 1; + } + + + //并机界面 + if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_Parallel, 7)) + { + SCR_ParallelFlag = 1; + SCR_PACKFlag = 0; + if(bmsMem.E2_485Addr == 1) + { + SCR_Send("page page18\xff\xff\xff"); // 只发一次跳转 + } + } + //汇总数据页跳转至电池页(跳转屏幕做，置1标志位) + if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_Allpack, 7)) + { + SCR_ParallelFlag = 1; + } + //电池页跳转至汇总数据页(跳转屏幕做，清0标志位) + if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_Allcell, 7)) + { + SCR_ParallelFlag = 0; + } + + //跳转到单个电池页 + if(SCR_ParallelFlag == 1) + { + if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_PACK1, 7)) + { + scr_RdData_Index = 1; + SCR_PACKFlag = 1; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_PACK2, 7)) + { + scr_RdData_Index = 2; + SCR_PACKFlag = 1; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_PACK3, 7)) + { + scr_RdData_Index = 3; + SCR_PACKFlag = 1; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_PACK4, 7)) + { + scr_RdData_Index = 4; + SCR_PACKFlag = 1; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_PACK5, 7)) + { + scr_RdData_Index = 5; + SCR_PACKFlag = 1; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_PACK6, 7)) + { + scr_RdData_Index = 6; + SCR_PACKFlag = 1; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_PACK7, 7)) + { + scr_RdData_Index = 7; + SCR_PACKFlag = 1; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_PACK8, 7)) + { + scr_RdData_Index = 8; + SCR_PACKFlag = 1; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_PACK9, 7)) + { + scr_RdData_Index = 9; + SCR_PACKFlag = 1; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_PACK10, 7)) + { + scr_RdData_Index = 10; + SCR_PACKFlag = 1; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_PACK11, 7)) + { + scr_RdData_Index = 11; + SCR_PACKFlag = 1; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_PACK12, 7)) + { + scr_RdData_Index = 12; + SCR_PACKFlag = 1; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_PACK13, 7)) + { + scr_RdData_Index = 13; + SCR_PACKFlag = 1; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_PACK14, 7)) + { + scr_RdData_Index = 14; + SCR_PACKFlag = 1; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_PACK15, 7)) + { + scr_RdData_Index = 15; + SCR_PACKFlag = 1; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_PACK16, 7)) + { + scr_RdData_Index = 16; + SCR_PACKFlag = 1; + } + } + + //短路保护电压 + if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_setSCVol_0, 7)) + { + flashUpdateFlag = 2; + temp = 0; + bmsMem.ee_scv_sct &= ~0xF0; + bmsMem.ee_scv_sct |= temp<<4; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_setSCVol_1, 7)) + { + flashUpdateFlag = 2; + temp = 1; + bmsMem.ee_scv_sct &= ~0xF0; + bmsMem.ee_scv_sct |= temp<<4; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_setSCVol_2, 7)) + { + flashUpdateFlag = 2; + temp = 2; + bmsMem.ee_scv_sct &= ~0xF0; + bmsMem.ee_scv_sct |= temp<<4; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_setSCVol_3, 7)) + { + flashUpdateFlag = 2; + temp = 3; + bmsMem.ee_scv_sct &= ~0xF0; + bmsMem.ee_scv_sct |= temp<<4; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_setSCVol_4, 7)) + { + flashUpdateFlag = 2; + temp = 4; + bmsMem.ee_scv_sct &= ~0xF0; + bmsMem.ee_scv_sct |= temp<<4; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_setSCVol_5, 7)) + { + flashUpdateFlag = 2; + temp = 5; + bmsMem.ee_scv_sct &= ~0xF0; + bmsMem.ee_scv_sct |= temp<<4; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_setSCVol_6, 7)) + { + flashUpdateFlag = 2; + temp = 6; + bmsMem.ee_scv_sct &= ~0xF0; + bmsMem.ee_scv_sct |= temp<<4; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_setSCVol_7, 7)) + { + flashUpdateFlag = 2; + temp = 7; + bmsMem.ee_scv_sct &= ~0xF0; + bmsMem.ee_scv_sct |= temp<<4; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_setSCVol_8, 7)) + { + flashUpdateFlag = 2; + temp = 8; + bmsMem.ee_scv_sct &= ~0xF0; + bmsMem.ee_scv_sct |= temp<<4; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_setSCVol_9, 7)) + { + flashUpdateFlag = 2; + temp = 9; + bmsMem.ee_scv_sct &= ~0xF0; + bmsMem.ee_scv_sct |= temp<<4; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_setSCVol_10, 7)) + { + flashUpdateFlag = 2; + temp = 10; + bmsMem.ee_scv_sct &= ~0xF0; + bmsMem.ee_scv_sct |= temp<<4; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_setSCVol_11, 7)) + { + flashUpdateFlag = 2; + temp = 11; + bmsMem.ee_scv_sct &= ~0xF0; + bmsMem.ee_scv_sct |= temp<<4; + } + + //短路保护延时 + if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_setSCTim_0, 7)) + { + flashUpdateFlag = 2; + temp = 0; + bmsMem.ee_scv_sct &= ~0x0F; + bmsMem.ee_scv_sct |= temp; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_setSCTim_1, 7)) + { + flashUpdateFlag = 2; + temp = 1; + bmsMem.ee_scv_sct &= ~0x0F; + bmsMem.ee_scv_sct |= temp; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_setSCTim_2, 7)) + { + flashUpdateFlag = 2; + temp = 2; + bmsMem.ee_scv_sct &= ~0x0F; + bmsMem.ee_scv_sct |= temp; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_setSCTim_3, 7)) + { + flashUpdateFlag = 2; + temp = 3; + bmsMem.ee_scv_sct &= ~0x0F; + bmsMem.ee_scv_sct |= temp; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_setSCTim_4, 7)) + { + flashUpdateFlag = 2; + temp = 4; + bmsMem.ee_scv_sct &= ~0x0F; + bmsMem.ee_scv_sct |= temp; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_setSCTim_5, 7)) + { + flashUpdateFlag = 2; + temp = 5; + bmsMem.ee_scv_sct &= ~0x0F; + bmsMem.ee_scv_sct |= temp; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_setSCTim_6, 7)) + { + flashUpdateFlag = 2; + temp = 6; + bmsMem.ee_scv_sct &= ~0x0F; + bmsMem.ee_scv_sct |= temp; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_setSCTim_7, 7)) + { + flashUpdateFlag = 2; + temp = 7; + bmsMem.ee_scv_sct &= ~0x0F; + bmsMem.ee_scv_sct |= temp; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_setSCTim_8, 7)) + { + flashUpdateFlag = 2; + temp = 8; + bmsMem.ee_scv_sct &= ~0x0F; + bmsMem.ee_scv_sct |= temp; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_setSCTim_9, 7)) + { + flashUpdateFlag = 2; + temp = 9; + bmsMem.ee_scv_sct &= ~0x0F; + bmsMem.ee_scv_sct |= temp; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_setSCTim_10, 7)) + { + flashUpdateFlag = 2; + temp = 10; + bmsMem.ee_scv_sct &= ~0x0F; + bmsMem.ee_scv_sct |= temp; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_setSCTim_11, 7)) + { + flashUpdateFlag = 2; + temp = 11; + bmsMem.ee_scv_sct &= ~0x0F; + bmsMem.ee_scv_sct |= temp; + } + + //设置逆变器协议 + if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_setProtocol_SolArk, 7)) + { + if(protocol_Index != 1) protocol_Index = 1; + else protocol_Index = 0; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_setProtocol_GoodWe, 7)) + { + if(protocol_Index != 2) protocol_Index = 2; + else protocol_Index = 0; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_setProtocol_Megarevo, 7)) + { + if(protocol_Index != 30) protocol_Index = 30; + else protocol_Index = 0; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_setProtocol_Pylon, 7)) + { + if(protocol_Index != 12) protocol_Index = 12; + else protocol_Index = 0; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_setProtocol_Deye, 7)) + { + if(protocol_Index != 11) protocol_Index = 11; + else protocol_Index = 0; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_setProtocol_MUST, 7)) + { + if(protocol_Index != 7) protocol_Index = 7; + else protocol_Index = 0; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_setProtocol_Solis, 7)) + { + if(protocol_Index != 37) protocol_Index = 37; + else protocol_Index = 0; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_setProtocol_Growatt, 7)) + { + if(protocol_Index != 3) protocol_Index = 3; + else protocol_Index = 0; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_setProtocol_Aiswei, 7)) + { + if(protocol_Index != 4) protocol_Index = 4; + else protocol_Index = 0; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_setProtocol_Afore, 7)) + { + if(protocol_Index != 35) protocol_Index = 35; + else protocol_Index = 0; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_setProtocol_Victron, 7)) + { + if(protocol_Index != 27) protocol_Index = 27; + else protocol_Index = 0; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_setProtocol_Sorotec, 7)) + { + if(protocol_Index != 6) protocol_Index = 6; + else protocol_Index = 0; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_setProtocol_SMA, 7)) + { + if(protocol_Index != 5) protocol_Index = 5; + else protocol_Index = 0; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_setProtocol_Sunways, 7)) + { + if(protocol_Index != 39) protocol_Index = 39; + else protocol_Index = 0; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_setProtocol_Luxpower, 7)) + { + if(protocol_Index != 23) protocol_Index = 23; + else protocol_Index = 0; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_setProtocol_Schneider, 7)) + { + if(protocol_Index != 24) protocol_Index = 24; + else protocol_Index = 0; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_setProtocol_AlpSolarr, 7)) + { + if(protocol_Index != 40) protocol_Index = 40; + else protocol_Index = 0; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_setProtocol_SRNE, 7)) + { + if(protocol_Index != 13) protocol_Index = 13; + else protocol_Index = 0; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_setProtocol_Voltronic, 7)) + { + if(protocol_Index != 14) protocol_Index = 14; + else protocol_Index = 0; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_setProtocol_COSUPER, 7)) + { + if(protocol_Index != 32) protocol_Index = 32; + else protocol_Index = 0; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_setProtocol_SMK, 7)) + { + if(protocol_Index != 17) protocol_Index = 17; + else protocol_Index = 0; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_setProtocol_SAKO, 7)) + { + if(protocol_Index != 31) protocol_Index = 31; + else protocol_Index = 0; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_setProtocol_SNADI, 7)) + { + if(protocol_Index != 18) protocol_Index = 18; + else protocol_Index = 0; + } + else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_setProtocol_invt, 7)) + { + if(protocol_Index != 21) protocol_Index = 21; + else protocol_Index = 0; + } +// else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_altProtocol_1, 7)) +// { +// //预留 +// } +// else if(findHexStr(SCR_Rx_Buf, SCR_RX_BUF_LEN, SCR_altProtocol_2, 7)) +// { +// //预留 +// } + if(protocol != protocol_Index) //协议更新才写入，减少访问次数 + { + protocol = protocol_Index; + + EEPROM_WrMulByte(EE_PROTOCOL,&protocol); + delay_ms(5); + + uf_CAN1_Init(); + //SCR_DispProcotol(); + } + + + char para_str[6]; //无符号整数0~65535 或 有符号整数-32768~32767 或小数 //最长6位 + uint8_t len = 0; //字符串长度 + uint8_t pmFlg = 0; //是负数的标志 + uint8_t cotFlg = 0; //出现小数点的标志 + uint8_t tmpWr[2]; + uint8_t tmpRd[2]; + + // ===== 逆变器设置 (page9 id1~id4) ===== + if(strstr(SCR_Rx_Buf, "9,1,")) // 逆变器充电限流 + { + len = GetStr("9,1,", '\xff', '\xff', SCR_Rx_Buf, para_str); + if(len > 0) + { + for(i=0; i= '0' && para_str[i] <= '9') + { + temp = temp * 10 + (para_str[i] - '0'); + } + else if(para_str[i] == '.') + { + if((para_str[i+1] >= '0') && (para_str[i+1] <= '9')) + { + cotFlg = 1; + temp = temp * 10 + (para_str[i+1] - '0'); + } + + break; //遇到小数点，取后1位，剩下不算 + } + } + if(cotFlg == 0) //没有小数点，值*10 + { + temp = temp * 10; + } + + if((temp > 0) && (temp <= 20000)) //0.1~2000.0A + { + flashUpdateFlag = 1; + bmsMem.inverter_chgCurLimit = temp; + } + } + } + else if(strstr(SCR_Rx_Buf, "9,2,")) // 逆变器充电限压 + { + len = GetStr("9,2,", '\xff', '\xff', SCR_Rx_Buf, para_str); + if(len > 0) + { + for(i=0; i= '0' && para_str[i] <= '9') + { + temp = temp * 10 + (para_str[i] - '0'); + } + else if(para_str[i] == '.') + { + if((para_str[i+1] >= '0') && (para_str[i+1] <= '9')) + { + cotFlg = 1; + temp = temp * 10 + (para_str[i+1] - '0'); + } + + break; //遇到小数点，取后1位，剩下不算 + } + } + if(cotFlg == 0) //没有小数点，值*10 + { + temp = temp * 10; + } + + if((temp > 0) && (temp <= 1000)) //0.1~100.0V + { + flashUpdateFlag = 1; + bmsMem.inverter_chgVolLimit = temp; + } + } + } + else if(strstr(SCR_Rx_Buf, "9,3,")) // 逆变器放电限流 + { + len = GetStr("9,3,", '\xff', '\xff', SCR_Rx_Buf, para_str); + if(len > 0) + { + for(i=0; i= '0' && para_str[i] <= '9') + { + temp = temp * 10 + (para_str[i] - '0'); + } + else if(para_str[i] == '.') + { + if((para_str[i+1] >= '0') && (para_str[i+1] <= '9')) + { + cotFlg = 1; + temp = temp * 10 + (para_str[i+1] - '0'); + } + + break; //遇到小数点，取后1位，剩下不算 + } + } + if(cotFlg == 0) //没有小数点，值*10 + { + temp = temp * 10; + } + + if((temp > 0) && (temp <= 20000)) //0.1~2000.0A + { + flashUpdateFlag = 1; + bmsMem.inverter_dsgCurLimit = temp; + } + } + } + else if(strstr(SCR_Rx_Buf, "9,4,")) // 逆变器放电限压 + { + len = GetStr("9,4,", '\xff', '\xff', SCR_Rx_Buf, para_str); + if(len > 0) + { + for(i=0; i= '0' && para_str[i] <= '9') + { + temp = temp * 10 + (para_str[i] - '0'); + } + else if(para_str[i] == '.') + { + if((para_str[i+1] >= '0') && (para_str[i+1] <= '9')) + { + cotFlg = 1; + temp = temp * 10 + (para_str[i+1] - '0'); + } + + break; //遇到小数点，取后1位，剩下不算 + } + } + if(cotFlg == 0) //没有小数点，值*10 + { + temp = temp * 10; + } + + if((temp > 0) && (temp <= 1000)) //0.1~100.0V + { + flashUpdateFlag = 1; + bmsMem.inverter_dsgVolLimit = temp; + } + } + } + + // ===== BMS过流保护 (page9 id5~id6) ===== + else if(strstr(SCR_Rx_Buf, "9,5,")) // 充电过流保护值 + { + len = GetStr("9,5,", '\xff', '\xff', SCR_Rx_Buf, para_str); + if(len > 0) + { + temp = 0; + for(i=0; i= '0' && para_str[i] <= '9') + temp = temp * 10 + (para_str[i] - '0'); + else break; // 遇到非数字停止 + } + if(temp <= 255) // uint8_t 范围 + { + flashUpdateFlag = 2; + bmsMem.mcu_occ = (uint8_t)temp; + } + } + } + else if(strstr(SCR_Rx_Buf, "9,6,")) // 放电过流保护值 + { + len = GetStr("9,6,", '\xff', '\xff', SCR_Rx_Buf, para_str); + if(len > 0) + { + temp = 0; + for(i=0; i= '0' && para_str[i] <= '9') + temp = temp * 10 + (para_str[i] - '0'); + else break; + } + if(temp <= 255) + { + flashUpdateFlag = 2; + bmsMem.mcu_ocd = (uint8_t)temp; + } + } + } + + // ===== 充电温度保护 (page10 id1~id4) ===== + else if(strstr(SCR_Rx_Buf, "10,1,")) // 充电高温保护值 + { + len = GetStr("10,1,", '\xff', '\xff', SCR_Rx_Buf, para_str); + if(len > 0) + { + for(i=0;i= '0') && (para_str[i] <= '9')) + { + temp = temp * 10 + (para_str[i] - '0'); + } + else if(para_str[i] == '.') + { + break; //遇到小数点，剩下不算 + } + } + + if((pmFlg == 0) && (temp <= 115)) //-45~115℃ + { + flashUpdateFlag = 2; + bmsMem.mcu_otc = temp; + } + else if((pmFlg == 1) && (temp <= 45)) //-45~115℃ + { + flashUpdateFlag = 2; + bmsMem.mcu_otc = -temp; + } + } + } + else if(strstr(SCR_Rx_Buf, "10,2,")) // 充电高温释放值 + { + len = GetStr("10,2,", '\xff', '\xff', SCR_Rx_Buf, para_str); + if(len > 0) + { + for(i=0;i= '0') && (para_str[i] <= '9')) + { + temp = temp * 10 + (para_str[i] - '0'); + } + else if(para_str[i] == '.') + { + break; //遇到小数点，剩下不算 + } + } + + if((pmFlg == 0) && (temp <= 115)) //-45~115℃ + { + flashUpdateFlag = 2; + bmsMem.mcu_otcr = temp; + } + else if((pmFlg == 1) && (temp <= 45)) //-45~115℃ + { + flashUpdateFlag = 2; + bmsMem.mcu_otcr = -temp; + } + } + } + else if(strstr(SCR_Rx_Buf, "10,3,")) // 充电低温保护值 + { + len = GetStr("10,3,", '\xff', '\xff', SCR_Rx_Buf, para_str); + if(len > 0) + { + for(i=0;i= '0') && (para_str[i] <= '9')) + { + temp = temp * 10 + (para_str[i] - '0'); + } + else if(para_str[i] == '.') + { + break; //遇到小数点，剩下不算 + } + } + + if((pmFlg == 0) && (temp <= 115)) //-45~115℃ + { + flashUpdateFlag = 2; + bmsMem.mcu_utc = temp; + } + else if((pmFlg == 1) && (temp <= 45)) //-45~115℃ + { + flashUpdateFlag = 2; + bmsMem.mcu_utc = -temp; + } + } + } + else if(strstr(SCR_Rx_Buf, "10,4,")) // 充电低温释放值 + { + len = GetStr("10,4,", '\xff', '\xff', SCR_Rx_Buf, para_str); + if(len > 0) + { + for(i=0;i= '0') && (para_str[i] <= '9')) + { + temp = temp * 10 + (para_str[i] - '0'); + } + else if(para_str[i] == '.') + { + break; //遇到小数点，剩下不算 + } + } + + if((pmFlg == 0) && (temp <= 115)) //-45~115℃ + { + flashUpdateFlag = 2; + bmsMem.mcu_utcr = temp; + } + else if((pmFlg == 1) && (temp <= 45)) //-45~115℃ + { + flashUpdateFlag = 2; + bmsMem.mcu_utcr = -temp; + } + } + } + + // ===== 放电温度保护 (page10 id5~id8) ===== + else if(strstr(SCR_Rx_Buf, "10,5,")) // 放电高温保护值 + { + len = GetStr("10,5,", '\xff', '\xff', SCR_Rx_Buf, para_str); + if(len > 0) + { + for(i=0;i= '0') && (para_str[i] <= '9')) + { + temp = temp * 10 + (para_str[i] - '0'); + } + else if(para_str[i] == '.') + { + break; //遇到小数点，剩下不算 + } + } + + if((pmFlg == 0) && (temp <= 115)) //-45~115℃ + { + flashUpdateFlag = 2; + bmsMem.mcu_otd = temp; + } + else if((pmFlg == 1) && (temp <= 45)) //-45~115℃ + { + flashUpdateFlag = 2; + bmsMem.mcu_otd = -temp; + } + } + } + else if(strstr(SCR_Rx_Buf, "10,6,")) // 放电高温释放值 + { + len = GetStr("10,6,", '\xff', '\xff', SCR_Rx_Buf, para_str); + if(len > 0) + { + for(i=0;i= '0') && (para_str[i] <= '9')) + { + temp = temp * 10 + (para_str[i] - '0'); + } + else if(para_str[i] == '.') + { + break; //遇到小数点，剩下不算 + } + } + + if((pmFlg == 0) && (temp <= 115)) //-45~115℃ + { + flashUpdateFlag = 2; + bmsMem.mcu_otdr = temp; + } + else if((pmFlg == 1) && (temp <= 45)) //-45~115℃ + { + flashUpdateFlag = 2; + bmsMem.mcu_otdr = -temp; + } + } + } + else if(strstr(SCR_Rx_Buf, "10,7,")) // 放电低温保护值 + { + len = GetStr("10,7,", '\xff', '\xff', SCR_Rx_Buf, para_str); + if(len > 0) + { + for(i=0;i= '0') && (para_str[i] <= '9')) + { + temp = temp * 10 + (para_str[i] - '0'); + } + else if(para_str[i] == '.') + { + break; //遇到小数点，剩下不算 + } + } + + if((pmFlg == 0) && (temp <= 115)) //-45~115℃ + { + flashUpdateFlag = 2; + bmsMem.mcu_utd = temp; + } + else if((pmFlg == 1) && (temp <= 45)) //-45~115℃ + { + flashUpdateFlag = 2; + bmsMem.mcu_utd = -temp; + } + } + } + else if(strstr(SCR_Rx_Buf, "10,8,")) // 放电低温释放值 + { + len = GetStr("10,8,", '\xff', '\xff', SCR_Rx_Buf, para_str); + if(len > 0) + { + for(i=0;i= '0') && (para_str[i] <= '9')) + { + temp = temp * 10 + (para_str[i] - '0'); + } + else if(para_str[i] == '.') + { + break; //遇到小数点，剩下不算 + } + } + + if((pmFlg == 0) && (temp <= 115)) //-45~115℃ + { + flashUpdateFlag = 2; + bmsMem.mcu_utdr = temp; + } + else if((pmFlg == 1) && (temp <= 45)) //-45~115℃ + { + flashUpdateFlag = 2; + bmsMem.mcu_utdr = -temp; + } + } + } + + // ===== 电压保护 (page11 id1~id4) ===== + else if(strstr(SCR_Rx_Buf, "11,1,")) // 充电过压保护值 (单体) + { + len = GetStr("11,1,", '\xff', '\xff', SCR_Rx_Buf, para_str); + if(len > 0) + { + for(i=0;i= '0') && (para_str[i] <= '9')) + { + temp = temp * 10 + (para_str[i] - '0'); + } + else if(para_str[i] == '.') + { + break; //遇到小数点，剩下不算 + } + } + + if((temp >= 3500) && (temp <= 3750)) //3500mV~3750mV + { + flashUpdateFlag = 2; + temp = temp/5; + bmsMem.ee_ovt_ldrt_ovh &= 0xfc;//~0x03 + bmsMem.ee_ovt_ldrt_ovh += (temp & 0x0300) >>8; + bmsMem.ee_ovl = temp & 0x00ff; + } + } + } + else if(strstr(SCR_Rx_Buf, "11,2,")) // 充电过压释放值 + { + len = GetStr("11,2,", '\xff', '\xff', SCR_Rx_Buf, para_str); + if(len > 0) + { + for(i=0; i= '0') && (para_str[i] <= '9')) + { + temp = temp * 10 + (para_str[i] - '0'); + } + else if(para_str[i] == '.') + { + break; //遇到小数点，剩下不算 + } + } + + if(temp >= 3300 && temp <= 3700) + { + flashUpdateFlag = 2; + temp = temp / 5; + bmsMem.ee_uvt_ovrh = (bmsMem.ee_uvt_ovrh & 0xfc) | ((temp >> 8) & 0x03); + bmsMem.ee_ovrl = temp & 0xff; + } + } + } + else if(strstr(SCR_Rx_Buf, "11,3,")) // 充电欠压保护值 (单体) + { + len = GetStr("11,3,", '\xff', '\xff', SCR_Rx_Buf, para_str); + if(len > 0) + { + for(i=0;i= '0') && (para_str[i] <= '9')) + { + temp = temp * 10 + (para_str[i] - '0'); + } + else if(para_str[i] == '.') + { + break; //遇到小数点，剩下不算 + } + } + + if((temp >= 2000) && (temp <= 3500)) //2000mV~3500mV + { + flashUpdateFlag = 2; + temp = temp/20; + bmsMem.ee_uv = temp; + } + } + } + else if(strstr(SCR_Rx_Buf, "11,4,")) // 充电欠压释放值 + { + len = GetStr("11,4,", '\xff', '\xff', SCR_Rx_Buf, para_str); + if(len > 0) + { + temp = 0; + for(int i=0; i= '0') && (para_str[i] <= '9')) + { + temp = temp * 10 + (para_str[i] - '0'); + } + else if(para_str[i] == '.') + { + break; //遇到小数点，剩下不算 + } + } + if(temp >= 2000 && temp <= 3500) + { + flashUpdateFlag = 2; + temp = temp / 20; + bmsMem.ee_uvr = temp; + } + } + } + + // ===== 其他 (page14 id1~id2) ===== + //写地址 + else if(strstr(SCR_Rx_Buf, "14,1,")) + { + len = GetStr("14,1,", '\xff', '\xff', SCR_Rx_Buf, para_str); + if(len > 0) + { + temp = 0; + for(i = 0; i < len; i++) + { + if(para_str[i] >= '0' && para_str[i] <= '9') + temp = temp * 10 + (para_str[i] - '0'); + else break; + } + if((temp >= 1) && (temp <= AddrMax)) + { + if(bmsMem.E2_485Addr == 1) //作为主机 + { + if((scr_RdData_Index>=2) && (scr_RdData_Index<=paraMem.PACK_NUM)) //想通过主机修改从机地址 + { + if((temp != 1) && (temp <= paraMem.PACK_NUM)) + { + sdwa_WrAddr = temp; + sdwa_WrAddr_Flg = 1; + } + } + else //修改主机地址 + { + if(paraMem.addr_FREE_Flg != 0) //只有允许手动改地址，才能改主机 + { + tmpWr[0] = temp; + EEPROM_WrMulByte(EE_ADDR,&tmpWr[0]); + delay_ms(5); + EEPROM_RdMulByte(EE_ADDR,&tmpRd[0]); + bmsMem.E2_485Addr = tmpRd[0]; + + tmpWr[0] = 0; + tmpWr[1] = 0; + bmsMem.can_ArrayIndex = 0; + EEPROM_WrMulByte(EE_ASSIGN,tmpWr); + delay_ms(5); + + scr_RdData_Index = bmsMem.E2_485Addr; + } + } + } + else //作为从机 + { + if((temp != 1) || (paraMem.addr_FREE_Flg != 0)) //只有允许手动改地址，才能改1 + { + tmpWr[0] = temp; + EEPROM_WrMulByte(EE_ADDR,&tmpWr[0]); + delay_ms(5); + EEPROM_RdMulByte(EE_ADDR,&tmpRd[0]); + bmsMem.E2_485Addr = tmpRd[0]; + + tmpWr[0] = 0; + tmpWr[1] = 0; + bmsMem.can_ArrayIndex = 0; + EEPROM_WrMulByte(EE_ASSIGN,tmpWr); + delay_ms(5); + + scr_RdData_Index = bmsMem.E2_485Addr; + } + } + } + } + } + + //写容量 + else if(strstr(SCR_Rx_Buf, "14,2,")) + { + len = GetStr("14,2,", '\xff', '\xff', SCR_Rx_Buf, para_str); + if(len > 0) + { + for(int i=0;i= '0') && (para_str[i] <= '9')) + { + temp = temp * 10 + (para_str[i] - '0'); + } + else if(para_str[i] == '.') + { + break; //遇到小数点，剩下不算 + } + } + + if((temp >= 1) && (temp <= 1000)) //1~1000Ah + { + //写入额定容量到 EEPROM + uint8_t tmpWr[2]; + tmpWr[0] = (temp >> 8) & 0xFF; + tmpWr[1] = temp & 0xFF; + EEPROM_WrMulByte(EE_NCC, tmpWr); + delay_ms(5); + + //重新读取 ncc_Ah + uint8_t tmpRd[2]; + EEPROM_RdMulByte(EE_NCC, tmpRd); + ncc_Ah = (tmpRd[0] << 8) | tmpRd[1]; + bmsMem.ncc = 3600 * 1000 * ncc_Ah; + + //满充容量设为额定容量 + fcc = bmsMem.ncc; + fcc_Ah = ncc_Ah; + uint8_t tmpFCC[8]; + tmpFCC[0] = (fcc >> 24) & 0xFF; + tmpFCC[1] = (fcc >> 16) & 0xFF; + tmpFCC[2] = (fcc >> 8) & 0xFF; + tmpFCC[3] = fcc & 0xFF; + tmpFCC[4] = tmpFCC[0] ^ 0xFF; + tmpFCC[5] = tmpFCC[1] ^ 0xFF; + tmpFCC[6] = tmpFCC[2] ^ 0xFF; + tmpFCC[7] = tmpFCC[3] ^ 0xFF; + EEPROM_WrMulByte(EE_FCC, tmpFCC); + delay_ms(20); + + //更新剩余容量 + bmsMem.rcc = fcc / 100 * bmsMem.soc; + rcc_Ah = fcc_Ah * bmsMem.soc / 100; + oldrcc_Ah = rcc_Ah; + } + } + } + + Screen_ClearBuf(); + } +} + diff --git a/MOUDLE/Status.c b/MOUDLE/Status.c new file mode 100644 index 0000000..8eab63f --- /dev/null +++ b/MOUDLE/Status.c @@ -0,0 +1,2647 @@ +/** + ****************************************************************************** + * @file Status.c + * @author + * @version + * @date + * @brief + ****************************************************************************** + * @attention + * + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" +#include "global.h" +#include "string.h" + +/*电压*/ +uint8_t cellov_alarmcount; //单体过压告警的延时计数 +uint8_t celluv_alarmcount; //单体欠压告警的延时计数 +uint8_t packov_alarmcount; //总体过压告警的延时计数 +uint8_t packuv_alarmcount; //总体欠压告警的延时计数 +uint8_t cellovr_alarmcount; //单体过压告警释放的延时计数 +uint8_t celluvr_alarmcount; //单体欠压告警释放的延时计数 +uint8_t packovr_alarmcount; //总体过压告警释放的延时计数 +uint8_t packuvr_alarmcount; //总体欠压告警释放的延时计数 + +uint8_t cellov_count; //单体过压保护的延时计数 +uint8_t celluv_count; //单体欠压保护的延时计数 +uint8_t packov_count; //总体过压保护的延时计数 +uint8_t packuv_count; //总体欠压保护的延时计数 +uint8_t cellovr_count; //单体过压保护释放的延时计数 +uint8_t celluvr_count; //单体欠压保护释放的延时计数 +uint8_t packovr_count; //总体过压保护释放的延时计数 +uint8_t packuvr_count; //总体欠压保护释放的延时计数 + +uint16_t cell_OV; //单体过压值 +uint16_t cell_UV; //单体欠压值 +uint16_t cell_OVT; //单体过压延时参数，对应表格1s~40s +uint16_t cell_UVT; //单体欠压延时参数，对应表格1s~40s +uint16_t cell_OVR; //单体过压释放值 +uint16_t cell_UVR; //单体欠压释放值 + +uint8_t cellovr_alarmcount2; //单体过压告警特殊释放的延时计数 +uint8_t celluvr_alarmcount2; //单体欠压告警特殊释放的延时计数 +uint8_t packovr_alarmcount2; //总体过压告警特殊释放的延时计数 +uint8_t packuvr_alarmcount2; //总体欠压告警特殊释放的延时计数 + +uint8_t cellovr_alarmcount3; //单体过压告警特殊释放的延时计数 +uint8_t celluvr_alarmcount3; //单体欠压告警特殊释放的延时计数 +uint8_t packovr_alarmcount3; //总体过压告警特殊释放的延时计数 +uint8_t packuvr_alarmcount3; //总体欠压告警特殊释放的延时计数 + +uint8_t cellovr_count2; //单体过压保护特殊释放的延时计数 +uint8_t celluvr_count2; //单体欠压保护特殊释放的延时计数 +uint8_t packovr_count2; //总体过压保护特殊释放的延时计数 +uint8_t packuvr_count2; //总体欠压保护特殊释放的延时计数 + +uint8_t cellovr_count3; //单体过压保护特殊释放的延时计数 +uint8_t celluvr_count3; //单体欠压保护特殊释放的延时计数 +uint8_t packovr_count3; //总体过压保护特殊释放的延时计数 +uint8_t packuvr_count3; //总体欠压保护特殊释放的延时计数 + +uint8_t cellovr_alarmflag; //单体过压告警特殊释放的标志(因为过压会校准SOC，不考虑SOC<96%条件) +uint8_t packovr_alarmflag; //总体过压告警特殊释放的标志(因为过压会校准SOC，不考虑SOC<96%条件) +uint8_t celluvr_alarmflag; //单体欠压告警特殊释放的标志 +uint8_t packuvr_alarmflag; //总体欠压告警特殊释放的标志 + +uint8_t cellovr_flag; //单体过压保护特殊释放的标志(因为过压会校准SOC，不考虑SOC<96%条件) +uint8_t packovr_flag; //总体过压保护特殊释放的标志(因为过压会校准SOC，不考虑SOC<96%条件) +uint8_t celluvr_flag; //单体欠压保护特殊释放的标志 +uint8_t packuvr_flag; //总体欠压保护特殊释放的标志 + +/*电流*/ +uint8_t occ_alarmcount; //充电过流告警的延时计数 +uint8_t ocd1_alarmcount; //放电过流1告警的延时计数 +uint8_t occr_alarmcount; //充电过流告警恢复的延时计数 +uint8_t occr_alarmcount2; +uint8_t ocd1r_alarmcount; //放电过流1告警恢复的延时计数 +uint8_t ocd1r_alarmcount2; + +uint8_t scr_count; //浪涌短路保护释放的延时计数 + +uint8_t occ_count; //充电过流保护的延时计数 +uint8_t ocd_count; //放电过流1保护的延时计数 +uint8_t ocr_count; //电流保护释放的延时计数 + +uint8_t occ_OccurFlag; //充电过流出现过的标志 +uint8_t ocd1_OccurFlag; //放电过流1出现过的标志 +uint8_t ocd2_OccurFlag; //放电过流1出现过的标志 + +uint8_t occ_RepeatFlag; //持续出现的标志 +uint8_t occ_RepeatTime; //等待倒计时，最大60s =>消失后60s内未再次出现，说明正常 +uint8_t occ_RepeatCount; //重复的计数，最大5次 =>连续5次出现，会在第五次短路将标志位置1，控制MOS关闭 + +uint8_t ocd1_RepeatFlag; //持续出现的标志 +uint8_t ocd1_RepeatTime; //等待倒计时，最大60s =>消失后60s内未再次出现，说明正常 +uint8_t ocd1_RepeatCount; //重复的计数，最大5次 =>连续5次出现，会在第五次短路将标志位置1，控制MOS关闭 + +uint8_t ocd2_RepeatFlag; //持续出现的标志 +uint8_t ocd2_RepeatTime; //等待倒计时，最大60s =>消失后60s内未再次出现，说明正常 +uint8_t ocd2_RepeatCount; //重复的计数，最大5次 =>连续5次出现，会在第五次短路将标志位置1，控制MOS关闭 + +/*温度*/ +uint8_t mcuotc_alarmcount; //电芯充电高温告警的延时计数 +uint8_t mcuutc_alarmcount; //电芯充电低温告警的延时计数 +uint8_t mcuotd_alarmcount; //电芯放电高温告警的延时计数 +uint8_t mcuutd_alarmcount; //电芯放电低温告警的延时计数 +uint8_t mcuotcr_alarmcount; //电芯充电高温告警释放的延时计数 +uint8_t mcuutcr_alarmcount; //电芯充电低温告警释放的延时计数 +uint8_t mcuotdr_alarmcount; //电芯放电高温告警释放的延时计数 +uint8_t mcuutdr_alarmcount; //电芯放电低温告警释放的延时计数 + +uint8_t dsg_htp_count; +uint8_t dsg_ltp_count; +uint8_t chg_htp_count; +uint8_t chg_ltp_count; +uint8_t dsg_htpr_count; +uint8_t dsg_ltpr_count; +uint8_t chg_htpr_count; +uint8_t chg_ltpr_count; + +uint8_t am_otc_alarmcount; +uint8_t am_utc_alarmcount; +uint8_t am_otd_alarmcount; +uint8_t am_utd_alarmcount; +uint8_t am_otcr_alarmcount; +uint8_t am_utcr_alarmcount; +uint8_t am_otdr_alarmcount; +uint8_t am_utdr_alarmcount; + +uint8_t am_otc_count; +uint8_t am_otcr_count; +uint8_t am_otd_count; +uint8_t am_otdr_count; +uint8_t am_utc_count; +uint8_t am_utcr_count; +uint8_t am_utd_count; +uint8_t am_utdr_count; + +uint8_t afeotc_alarmcount; //MOS温度告警的延时计数 +//uint8_t afeutc_alarmcount; +uint8_t afeotd_alarmcount; +//uint8_t afeutd_alarmcount; +uint8_t afeotcr_alarmcount; +//uint8_t afeutcr_alarmcount; +uint8_t afeotdr_alarmcount; +//uint8_t afeutdr_alarmcount; + +uint8_t afeotc_count; //MOS温度保护的延时计数 +//uint8_t afeutc_count; +uint8_t afeotd_count; +//uint8_t afeutd_count; +uint8_t afeotcr_count; +//uint8_t afeutcr_count; +uint8_t afeotdr_count; +//uint8_t afeutdr_count; + +/****出现告警/保护/故障/状态事件的上传****/ +#define MaxSaveNum 50 + +uint8_t incident_flag; //4G上报_要执行上报事件的标志 +uint8_t incident_DataInf; //4G上报_要上报发生事件的类型 +uint8_t incident_DataFlg; //4G上报_要上报发生事件时的数据的标志 2:保护 1:其他 0:不用记录 + +uint8_t staChange[MaxSaveNum+5]; //4G上报_最多同时存储50条 +uint32_t staChange_time[MaxSaveNum+5]; //4G上报_发生时间，最多同时存储50条 +uint8_t staChange_num; //4G上报_当前存储待上报状态的总个数 若总个数到达最大，就不再放入，直到全部发送后才清零重新计数 +uint8_t staChange_index; //4G上报_目前上报对应的序号 + +/*状态改变*/ +//常见状态 +uint16_t NomalStatus; //1~8bit -> 有0x01~0x08 无不算事件 (这个从0x01开始表示) +//特殊状态 +uint16_t SpecialStatus; //0~8bit -> 有0x10~0x19 无+0x80 +//保护 +uint16_t Protect_Vol; //0~5bit -> 有0x20~0x25 无+0x80 +uint16_t Protect_Cur; //0~4bit -> 有0x30~0x34 无+0x80 +uint16_t Protect_Temp; //0~11bit -> 有0x40~0x4B 无+0x80 +//报警 +uint16_t Warning_Vol; //0~3bit -> 有0x50~0x53 无+0x80 +uint16_t Warning_Cur; //0~1bit -> 有0x60~0x61 无+0x80 +uint16_t Warning_Temp; //0~11bit -> 有0x70~0x7B 无+0x80 + +uint16_t status_New[8]; //当前状态拷贝 +uint16_t status_Old[8]; //当上报过出现的报警/保护后，置位对应位 + + +const uint8_t VP_Time[16-6]= +{ + 1, 2, 3, 4, 6, 8, 10, 20, 30, 40 +}; + + +//过压的告警 +void Trigger_OVAlarm(void) +{ + //单体过压告警判断 + if((bmsMem.bStatus3 & 0x0100) == 0) + { + if(cellVoltageMax >= paraMem.alarm_cov) + { + if(cellovr_alarmflag == 0) //特殊释放不会因为电压重复触发 + { + cellov_alarmcount++; + if(cellov_alarmcount > 3) + { + bmsMem.bStatus3 |= 0x0100; + cellov_alarmcount = 0; + } + } + } + else + { + cellovr_alarmflag = 0; + + cellov_alarmcount = 0; + } + + if(bDSGING == 0) + { + cellovr_alarmflag = 0; + } + } + + //总体过压告警判断 + if((bmsMem.bStatus3 & 0x0400) == 0) + { + if(bmsMem.packVoltage >= paraMem.alarm_pov * 100) + { + if(packovr_alarmflag == 0) + { + packov_alarmcount++; + if(packov_alarmcount > 3) + { + bmsMem.bStatus3 |= 0x0400; + packov_alarmcount = 0; + } + } + } + else + { + packovr_alarmflag = 0; + packov_alarmcount = 0; + } + + if(bDSGING == 0) + { + packovr_alarmflag = 0; + } + } +} + +//欠压的告警 +void Trigger_UVAlarm(void) +{ + //单体欠压告警判断 + if((bmsMem.bStatus3 & 0x0200) == 0) + { + if(cellVoltageMin <= paraMem.alarm_cuv) + { + if(celluvr_alarmflag == 0) + { + celluv_alarmcount++; + if(celluv_alarmcount > 3) + { + bmsMem.bStatus3 |= 0x0200; + celluv_alarmcount = 0; + } + } + } + else + { + celluvr_alarmflag = 0; + celluv_alarmcount = 0; + } + + if(bCHGING == 0) + { + celluvr_alarmflag = 0; + } + } + + //总体欠压告警判断 + if((bmsMem.bStatus3 & 0x0800) == 0) + { + if(bmsMem.packVoltage <= paraMem.alarm_puv * 100) + { + if(packuvr_alarmflag == 0) + { + packuv_alarmcount++; + if(packuv_alarmcount > 3) + { + bmsMem.bStatus3 |= 0x0800; + packuv_alarmcount = 0; + } + } + } + else + { + packuvr_alarmflag = 0; + packuv_alarmcount = 0; + } + + if(bCHGING == 0) + { + packuvr_alarmflag = 0; + } + } +} + +//过压的告警释放 +void Release_OVAlarm(void) +{ + //单体过压恢复值 + cell_OVR = ( (bmsMem.ee_uvt_ovrh & 0x03) <<8 | bmsMem.ee_ovrl ) * 5; + + //单体过压告警恢复判断 + if((bmsMem.bStatus3 & 0x0100) != 0) + { + if(cellVoltageMax < cell_OVR) + { + cellovr_alarmcount++; + if(cellovr_alarmcount > 1) + { + bmsMem.bStatus3 &= ~0x0100; + cellovr_alarmcount = 0; + } + } + else + { + cellovr_alarmcount = 0; + } + + if(bmsMem.soc < paraMem.cellovr_soc) //特殊解除项：①SOC<96% + { + cellovr_alarmcount2++; + if(cellovr_alarmcount2 > 1) + { + bmsMem.bStatus3 &= ~0x0100; + cellovr_alarmcount2 = 0; + } + } + else + { + cellovr_alarmcount2 = 0; + } + + if(bmsMem.packCurrent < -3000) //特殊解除项：②放电电流>3A + { + cellovr_alarmcount3++; + if(cellovr_alarmcount3 > 1) + { + cellovr_alarmflag = 1; + + bmsMem.bStatus3 &= ~0x0100; + cellovr_alarmcount3 = 0; + } + } + else + { + cellovr_alarmcount3 = 0; + } + } + + //总体过压告警恢复判断 + if((bmsMem.bStatus3 & 0x0400) != 0) + { + if(bmsMem.packVoltage < paraMem.pack_ovrv * 100) + { + packovr_alarmcount++; + if(packovr_alarmcount > 1) + { + bmsMem.bStatus3 &= ~0x0400; + packovr_alarmcount = 0; + } + } + else + { + packovr_alarmcount = 0; + } + + if(bmsMem.soc < paraMem.packovr_soc) //特殊解除项：①SOC<96% + { + packovr_alarmcount2++; + if(packovr_alarmcount2 > 1) + { + bmsMem.bStatus3 &= ~0x0400; + packovr_alarmcount2 = 0; + } + } + else + { + packovr_alarmcount2 = 0; + } + + if(bmsMem.packCurrent < -3000) //特殊解除项：②放电电流>3A + { + packovr_alarmcount3++; + if(packovr_alarmcount3 > 1) + { + packovr_alarmflag = 1; + + bmsMem.bStatus3 &= ~0x0400; + packovr_alarmcount3 = 0; + } + } + else + { + packovr_alarmcount3 = 0; + } + } +} + +//欠压的告警释放 +void Release_UVAlarm(void) +{ + //单体欠压恢复值 + cell_UVR = bmsMem.ee_uvr * 20; + + //单体欠压告警恢复判断 + if((bmsMem.bStatus3 & 0x0200) != 0) + { + if(cellVoltageMin > cell_UVR) + { + celluvr_alarmcount++; + if(celluvr_alarmcount > 1) + { + bmsMem.bStatus3 &= ~0x0200; + celluvr_alarmcount = 0; + } + } + else + { + celluvr_alarmcount = 0; + } + + if(bmsMem.packCurrent > 200) //特殊解除项：接入充电器 0.2A + { + celluvr_alarmcount2++; + if(celluvr_alarmcount2 > 1) + { + celluvr_alarmflag = 1; + + bmsMem.bStatus3 &= ~0x0200; + celluvr_alarmcount2 = 0; + } + } + else + { + celluvr_alarmcount2 = 0; + } + } + + //总体欠压告警恢复判断 + if((bmsMem.bStatus3 & 0x0800) != 0) + { + if(bmsMem.packVoltage > paraMem.pack_uvrv * 100) + { + packuvr_alarmcount++; + if(packuvr_alarmcount > 1) + { + bmsMem.bStatus3 &= ~0x0800; + packuvr_alarmcount = 0; + } + } + else + { + packuvr_alarmcount = 0; + } + + if(bmsMem.packCurrent > 200) //特殊解除项：接入充电器 0.2A + { + packuvr_alarmcount2++; + if(packuvr_alarmcount2 > 1) + { + packuvr_alarmflag = 1; + + bmsMem.bStatus3 &= ~0x0800; + packuvr_alarmcount2 = 0; + } + } + else + { + packuvr_alarmcount2 = 0; + } + } +} + +//过压的保护 +void Trigger_OVProtect(void) +{ + uint8_t temp; + + //单体过压值 + cell_OV = ( (bmsMem.ee_ovt_ldrt_ovh & 0x03) <<8 | bmsMem.ee_ovl ) * 5; + + //单体过压的延时，单位1s + temp = bmsMem.ee_ovt_ldrt_ovh >> 4; + temp = temp>=6?(temp-6):0; + cell_OVT = VP_Time[temp]; + + //单体过压判断 + if((bmsMem.bStatus1 & 0x0001) == 0) + { + if(cellVoltageMax >= cell_OV) + { + if(cellovr_flag == 0) + { + cellov_count++; + if(cellov_count > cell_OVT) + { + bmsMem.bStatus1 |= 0x0001; + cellov_count = 0; + } + } + } + else + { + cellovr_flag = 0; + cellov_count = 0; + } + + if(bDSGING == 0) + { + cellovr_flag = 0; + } + } + + //总体过压判断 + if((bmsMem.bStatus1 & 0x0100) == 0) + { + if(bmsMem.packVoltage >= paraMem.pack_ovv * 100) + { + if(packovr_flag == 0) + { + packov_count++; + if(packov_count > paraMem.pack_ovt) + { + bmsMem.bStatus1 |= 0x0100; + packov_count = 0; + } + } + } + else + { + packovr_flag = 0; + packov_count = 0; + } + + if(bDSGING == 0) + { + packovr_flag = 0; + } + } +} + +//欠压的保护 +void Trigger_UVProtect(void) +{ + uint8_t temp; + + //单体欠压值 + cell_UV = bmsMem.ee_uv * 20; + + //单体欠压的延时，单位1s + temp = bmsMem.ee_uvt_ovrh >> 4; + temp = temp>=6?(temp-6):0; + cell_UVT = VP_Time[temp]; + + //单体欠压判断 + if((bmsMem.bStatus1 & 0x0002) == 0) + { + if(cellVoltageMin <= cell_UV) + { + if(celluvr_flag == 0) + { + celluv_count++; + if(celluv_count > cell_UVT) + { + bmsMem.bStatus1 |= 0x0002; + celluv_count = 0; + } + } + } + else + { + celluvr_flag = 0; + celluv_count = 0; + } + + if(bCHGING == 0) + { + celluvr_flag = 0; + } + } + + //总体欠压判断 + if((bmsMem.bStatus1 & 0x0200) == 0) + { + if(bmsMem.packVoltage <= paraMem.pack_uvv * 100) + { + if(packuvr_flag == 0) + { + packuv_count++; + if(packuv_count > paraMem.pack_uvt) + { + bmsMem.bStatus1 |= 0x0200; + packuv_count = 0; + } + } + } + else + { + packuvr_flag = 0; + packuv_count = 0; + } + + if(bCHGING == 0) + { + packuvr_flag = 0; + } + } +} + +//过压的保护释放 +void Release_OVProtect(void) +{ + //单体过压恢复判断 + if((bmsMem.bStatus1 & 0x0001) != 0) + { + if(cellVoltageMax < cell_OVR) + { + cellovr_count++; + if(cellovr_count > 1) + { + bmsMem.bStatus1 &= ~0x0001; + cellovr_count = 0; + } + } + else + { + cellovr_count = 0; + } + + if(bmsMem.soc < paraMem.cellovr_soc) //特殊解除项：①SOC<96% + { + cellovr_count2++; + if(cellovr_count2 > 1) + { + bmsMem.bStatus1 &= ~0x0001; + cellovr_count2 = 0; + } + } + else + { + cellovr_count2 = 0; + } + if(bmsMem.packCurrent < -3000) //特殊解除项：②放电电流>3A + { + cellovr_count3++; + if(cellovr_count3 > 1) + { + cellovr_flag = 1; + + bmsMem.bStatus1 &= ~0x0001; + cellovr_count3 = 0; + } + } + else + { + cellovr_count3 = 0; + } + } + + //总体过压恢复判断 + if((bmsMem.bStatus1 & 0x0100) != 0) + { + if(bmsMem.packVoltage < paraMem.pack_ovrv * 100) + { + packovr_count++; + if(packovr_count > 1) + { + bmsMem.bStatus1 &= ~0x0100; + packovr_count = 0; + } + } + else + { + packovr_count = 0; + } + + if(bmsMem.soc < paraMem.packovr_soc) //特殊解除项：①SOC<96% + { + packovr_count2++; + if(packovr_count2 > 1) + { + bmsMem.bStatus1 &= ~0x0100; + packovr_count2 = 0; + } + } + else + { + packovr_count2 = 0; + } + if(bmsMem.packCurrent < -3000) //特殊解除项：②放电电流>3A + { + packovr_count3++; + if(packovr_count3 > 1) + { + packovr_flag = 1; + + bmsMem.bStatus1 &= ~0x0100; + packovr_count3 = 0; + } + } + else + { + packovr_count3 = 0; + } + } +} + +//欠压的保护释放 +void Release_UVProtect(void) +{ + //单体欠压恢复判断 + if((bmsMem.bStatus1 & 0x0002) != 0) + { + if(cellVoltageMin > cell_UVR) + { + celluvr_count++; + if(celluvr_count > 1) + { + bmsMem.bStatus1 &= ~0x0002; + celluvr_count = 0; + } + } + else + { + celluvr_count = 0; + } + + if(bmsMem.packCurrent > 200) //特殊解除项：接入充电器 0.2A + { + celluvr_count2++; + if(celluvr_count2 > 1) + { + celluvr_flag = 1; + + bmsMem.bStatus1 &= ~0x0002; + celluvr_count2 = 0; + } + } + else + { + celluvr_count2 = 0; + } + } + + //总体欠压恢复判断 + if((bmsMem.bStatus1 & 0x0200) != 0) + { + if(bmsMem.packVoltage > paraMem.pack_uvrv * 100) + { + packuvr_count++; + if(packuvr_count > 1) + { + bmsMem.bStatus1 &= ~0x0200; + packuvr_count = 0; + } + } + else + { + packuvr_count = 0; + } + + if(bmsMem.packCurrent > 200) //特殊解除项：接入充电器 0.2A + { + packuvr_count2++; + if(packuvr_count2 > 1) + { + packuvr_flag = 1; + + bmsMem.bStatus1 &= ~0x0200; + packuvr_count2 = 0; + } + } + else + { + packuvr_count2 = 0; + } + } +} + +//电流的告警 +void Trigger_CurAlarm(void) +{ + uint32_t current; + uint32_t alarm_occ,alarm_ocd1; + + if(bmsMem.packCurrent >=0) + { + current = bmsMem.packCurrent; + } + else + { + current = -bmsMem.packCurrent; + } + alarm_occ = paraMem.alarm_occ * 1000; + alarm_ocd1 = paraMem.alarm_ocd1 * 1000; + + + //充电过流告警 + if((bmsMem.bStatus3 & BIT12) == 0) + { + if((current > alarm_occ) && (bCHGING==1)) //充电状态 + { + occ_alarmcount++; + if(occ_alarmcount > 3) + { + bmsMem.bStatus3 |= BIT12; + occ_alarmcount = 0; + } + } + else + { + occ_alarmcount = 0; + } + } + //放电过流1告警 + if((bmsMem.bStatus3 & BIT13) == 0) + { + if((current > alarm_ocd1) && (bDSGING==1)) //放电状态 + { + ocd1_alarmcount++; + if(ocd1_alarmcount > 3) + { + bmsMem.bStatus3 |= BIT13; + ocd1_alarmcount = 0; + } + } + else + { + ocd1_alarmcount = 0; + } + } +} + +//电流的告警释放 +void Release_CurAlarm(void) +{ + uint32_t current; + uint32_t alarm_occ,alarm_ocd1; + + if(bmsMem.packCurrent >=0) + { + current = bmsMem.packCurrent; + } + else + { + current = -bmsMem.packCurrent; + } + alarm_occ = paraMem.alarm_occ * 1000; + alarm_ocd1 = paraMem.alarm_ocd1 * 1000; + + + //充电过流告警释放 + if((bmsMem.bStatus3 & BIT12) != 0) + { + if(current <= alarm_occ) + { + if(((current <= alarm_occ) && (bCHGING == 1)) || (bmsMem.packCurrent < -2000)) //特殊解除项：放电电流>2A + { + occr_alarmcount++; + if(occr_alarmcount > 3) + { + bmsMem.bStatus3 &= ~BIT12; + occr_alarmcount = 0; + } + } + else + { + occr_alarmcount = 0; + } + + //[定时恢复] + if(bmsMem.mcu_ocr_t != 0xFF) // 255 - 不自动恢复 + { + occr_alarmcount2++; + if(occr_alarmcount2 > bmsMem.mcu_ocr_t) + { + bmsMem.bStatus3 &= ~BIT12; + occr_alarmcount2 = 0; + } + } + } + } + //放电过流1告警释放 + if((bmsMem.bStatus3 & BIT13) != 0) + { + if(current <= alarm_ocd1) + { + if(((current <= alarm_ocd1) && (bDSGING == 1)) || (bmsMem.packCurrent > 2000)) //特殊解除项：充电电流>2A + { + ocd1r_alarmcount++; + if(ocd1r_alarmcount > 3) + { + bmsMem.bStatus3 &= ~BIT13; + ocd1r_alarmcount = 0; + } + } + else + { + ocd1r_alarmcount = 0; + } + + //[定时恢复] + if(bmsMem.mcu_ocr_t != 0xFF) // 255 - 不自动恢复 + { + ocd1r_alarmcount2++; + if(ocd1r_alarmcount2 > bmsMem.mcu_ocr_t) + { + bmsMem.bStatus3 &= ~BIT13; + ocd1r_alarmcount2 = 0; + } + } + } + } +} + +//电流的保护 +void Trigger_CurProtect(void) +{ + uint32_t current; + uint32_t occ,ocd; + + if(bmsMem.packCurrent >=0) + { + current = bmsMem.packCurrent; + } + else + { + current = -bmsMem.packCurrent; + } + + occ = bmsMem.mcu_occ * 1000; + ocd = bmsMem.mcu_ocd * 1000; + + + //充电过流 + if((bmsMem.temperaStatus & BIT4) == 0) + { + if((current > occ) && (bCHGING==1)) + { + occ_count++; + if(occ_count > bmsMem.mcu_occ_t) + { + bmsMem.temperaStatus |= BIT4; + occ_count = 0; + } + } + else + { + occ_count = 0; + } + } + //放电过流1 + if((bmsMem.temperaStatus & BIT5) == 0) + { + if((current > ocd) && (bDSGING==1)) + { + ocd_count++; + if(ocd_count > bmsMem.mcu_ocd_t) + { + bmsMem.temperaStatus |= BIT5; + ocd_count = 0; + } + } + else + { + ocd_count = 0; + } + } +} + +//电流的保护释放 +void Release_CurProtect(void) +{ + uint8_t scr_t = (bmsMem.ee_most_ocrt_pft >> 2) & 0x03; //取bit2-3 + if(scr_t == 0) scr_t = 8; + else if(scr_t == 1) scr_t = 16; + else if(scr_t == 2) scr_t = 32; + else if(scr_t == 3) scr_t = 64; + + //短路保护自恢复 + if(((bmsMem.bStatus1 & BIT5) != 0) && (sc_close_flag == 0)) + { + scr_count++; + if(scr_count > scr_t) + { + sc_close_flag = 1; + scr_count = 0; + } + } + //充电过流/放电过流1/放电过流2保护释放[定时恢复] + if(((bmsMem.temperaStatus & BIT4) != 0) || ((bmsMem.temperaStatus & BIT5) != 0) || ((bmsMem.bStatus1 & BIT10) != 0)) + { + if(bmsMem.mcu_ocr_t != 0xFF) // 255 - 不自动恢复 + { + ocr_count++; + if(ocr_count > bmsMem.mcu_ocr_t) + { + //充电过流释放 + bmsMem.temperaStatus &= ~BIT4; + //放电过流1释放 + bmsMem.temperaStatus &= ~BIT5; + //放电过流2释放 + bmsMem.bStatus1 &= ~BIT10; + + ocr_count = 0; + } + } + } + + //充电过流保护释放[放电解除] + if((bmsMem.temperaStatus & BIT4) != 0) + { + if(bmsMem.packCurrent < -2000) //特殊解除项：充电电流>2A + { + //充电过流释放 + bmsMem.temperaStatus &= ~BIT4; + } + } + //放电过流1保护释放[充电解除] + if((bmsMem.temperaStatus & BIT5) != 0) + { + if(bmsMem.packCurrent > 2000) //特殊解除项：充电电流>2A + { + //放电过流1释放 + bmsMem.temperaStatus &= ~BIT5; + } + } + //放电过流2保护释放[充电解除] + if((bmsMem.bStatus1 & BIT10) != 0) + { + if(bmsMem.packCurrent > 2000) //特殊解除项：充电电流>2A + { + //放电过流2释放 + bmsMem.bStatus1 &= ~BIT10; + } + } +} + +//电流保护的次数超限锁定 +void Trigger_CurProtectLock(void) +{ +// //充电过流保护出现 +// if((bmsMem.temperaStatus & BIT4) != 0) +// { +// //刚出现时 +// if(occ_OccurFlag == 0) +// { +// occ_OccurFlag = 1; +// +// //分析是否满足锁定条件 +// if(occ_RepeatFlag == 0) //此前并未连续出现 +// { +// occ_RepeatFlag = 1; //“充电过流保护60s内出现过”的标志，用于在消失后的计时判断 +// } +// else +// { +// occ_RepeatCount++; //充电过流保护持续60s不出现的话，occ_OccurFlag会置0，所以这时候存在值1，说明是在60s内出现的，计数次数+1 +// } +// +// if(occ_RepeatCount+1 >= 10) //当计数达到9时(即连续发生了十次充电过流保护)，直接锁定，“充电过流保护”持续显示，持续关闭MOS +// { +// occ_RepeatCount = 0; +// bmsMem.balanceStatus |= BIT10; //充电过流保护锁定启用，只有重启和写MOS控制可清零 +// } +// } +// } +// //充电过流保护消失 +// else +// { +// occ_OccurFlag = 0; +// +// //充电过流保护出现后又消失，若在60s内监测到充电过流保护不开启则计数恢复0，否则计数+1 +// if(occ_RepeatFlag == 1) +// { +// occ_RepeatTime++; +// if(occ_RepeatTime > 60) //持续60s +// { +// occ_RepeatFlag = 0; //“充电过流保护60s内出现过”的标志置0 +// occ_RepeatCount = 0; //连续出现计数清零 +// occ_RepeatTime = 0; //倒计时清零 +// } +// } +// else +// { +// occ_RepeatTime = 0; +// } +// } +// +// //放电过流1保护出现 +// if((bmsMem.temperaStatus & BIT5) != 0) +// { +// //刚出现时 +// if(ocd1_OccurFlag == 0) +// { +// ocd1_OccurFlag = 1; +// +// //分析是否满足锁定条件 +// if(ocd1_RepeatFlag == 0) //此前并未连续出现 +// { +// ocd1_RepeatFlag = 1; //“放电过流1保护60s内出现过”的标志，用于在消失后的计时判断 +// } +// else +// { +// ocd1_RepeatCount++; //放电过流1保护持续60s不出现的话，ocd1_OccurFlag会置0，所以这时候存在值1，说明是在60s内出现的，计数次数+1 +// } +// +// if(ocd1_RepeatCount+1 >= 10) //当计数达到9时(即连续发生了十次放电过流1保护)，直接锁定，“放电过流1保护”持续显示，持续关闭MOS +// { +// ocd1_RepeatCount = 0; +// bmsMem.balanceStatus |= BIT9; //放电过流1保护锁定启用，只有重启和写MOS控制可清零 +// } +// } +// } +// //放电过流1保护消失 +// else +// { +// ocd1_OccurFlag = 0; +// +// //放电过流1保护出现后又消失，若在60s内监测到放电过流1保护不开启则计数恢复0，否则计数+1 +// if(ocd1_RepeatFlag == 1) +// { +// ocd1_RepeatTime++; +// if(ocd1_RepeatTime > 60) //持续60s +// { +// ocd1_RepeatFlag = 0; //“放电过流1保护60s内出现过”的标志置0 +// ocd1_RepeatCount = 0; //连续出现计数清零 +// ocd1_RepeatTime = 0; //倒计时清零 +// } +// } +// else +// { +// ocd1_RepeatTime = 0; +// } +// } +// +// //放电过流2保护出现 +// if((bmsMem.bStatus1 & BIT10) != 0) +// { +// //刚出现时 +// if(ocd2_OccurFlag == 0) +// { +// ocd2_OccurFlag = 1; +// +// //分析是否满足锁定条件 +// if(ocd2_RepeatFlag == 0) //此前并未连续出现 +// { +// ocd2_RepeatFlag = 1; //“放电过流2保护60s内出现过”的标志，用于在消失后的计时判断 +// } +// else +// { +// ocd2_RepeatCount++; //放电过流2保护持续60s不出现的话，ocd2_OccurFlag会置0，所以这时候存在值1，说明是在60s内出现的，计数次数+1 +// } +// +// if(ocd2_RepeatCount+1 >= 3) //当计数达到2时(即连续发生了三次放电过流2保护)，直接锁定，“放电过流2保护”持续显示，持续关闭MOS +// { +// ocd2_RepeatCount = 0; +// bmsMem.balanceStatus |= BIT8; //放电过流2保护锁定启用，只有重启和写MOS控制可清零 +// } +// } +// } +// //放电过流2保护消失 +// else +// { +// ocd2_OccurFlag = 0; +// +// //放电过流2保护出现后又消失，若在60s内监测到放电过流2保护不开启则计数恢复0，否则计数+1 +// if(ocd2_RepeatFlag == 1) +// { +// ocd2_RepeatTime++; +// if(ocd2_RepeatTime > 60) //持续60s +// { +// ocd2_RepeatFlag = 0; //“放电过流2保护60s内出现过”的标志置0 +// ocd2_RepeatCount = 0; //连续出现计数清零 +// ocd2_RepeatTime = 0; //倒计时清零 +// } +// } +// else +// { +// ocd2_RepeatTime = 0; +// } +// } + + //浪涌短路和真短路，与预充相关，次数计算在别处执行 +} + +//电芯温度的告警 +void Trigger_mcuTAlarm(void) +{ + uint16_t alarm_otc,alarm_utc,alarm_otd,alarm_utd; + + alarm_otc = paraMem.alarm_mcu_otc * 10 + 2731; + alarm_utc = paraMem.alarm_mcu_utc * 10 + 2731; + alarm_otd = paraMem.alarm_mcu_otd * 10 + 2731; + alarm_utd = paraMem.alarm_mcu_utd * 10 + 2731; + + if(bmsMem.packCurrent > (-500)) //非放电状态下 + { + //电芯充电高温告警 + if((bmsMem.bStatus2 & BIT12) == 0) + { + if(TemperatureMax > alarm_otc) + { + mcuotc_alarmcount++; + if(mcuotc_alarmcount > 3) + { + bmsMem.bStatus2 |= BIT12; + mcuotc_alarmcount = 0; + } + } + else + { + mcuotc_alarmcount = 0; + } + } + + //电芯充电低温告警 + if((bmsMem.bStatus2 & BIT14) == 0) + { + if(TemperatureMin < alarm_utc) + { + mcuutc_alarmcount++; + if(mcuutc_alarmcount > 3) + { + bmsMem.bStatus2 |= BIT14; + mcuutc_alarmcount = 0; + } + } + else + { + mcuutc_alarmcount = 0; + } + } + } + else + { + bmsMem.bStatus2 &= ~BIT12; + bmsMem.bStatus2 &= ~BIT14; + } + + if(bmsMem.packCurrent < 500) //非充电状态下 + { + //电芯放电高温告警 + if((bmsMem.bStatus2 & BIT13) == 0) + { + if(TemperatureMax > alarm_otd) + { + mcuotd_alarmcount++; + if(mcuotd_alarmcount > 3) + { + bmsMem.bStatus2 |= BIT13; + mcuotd_alarmcount = 0; + } + } + else + { + mcuotd_alarmcount = 0; + } + } + + //电芯放电低温告警 + if((bmsMem.bStatus2 & BIT15) == 0) + { + if(TemperatureMin < alarm_utd) + { + mcuutd_alarmcount++; + if(mcuutd_alarmcount > 3) + { + bmsMem.bStatus2 |= BIT15; + mcuutd_alarmcount = 0; + } + } + else + { + mcuutd_alarmcount = 0; + } + } + } + else + { + bmsMem.bStatus2 &= ~BIT13; + bmsMem.bStatus2 &= ~BIT15; + } +} + +//电芯温度的告警释放 +void Release_mcuTAlarm(void) +{ + uint16_t otcr,utcr,otdr,utdr; + + otcr = bmsMem.mcu_otcr * 10 + 2731; + utcr = bmsMem.mcu_utcr * 10 + 2731; + otdr = bmsMem.mcu_otdr * 10 + 2731; + utdr = bmsMem.mcu_utdr * 10 + 2731; + + + //电芯充电高温告警恢复判断 + if((bmsMem.bStatus2 & BIT12) != 0) + { + if(TemperatureMax <= otcr) + { + mcuotcr_alarmcount++; + if(mcuotcr_alarmcount > 3) + { + bmsMem.bStatus2 &= ~BIT12; + mcuotcr_alarmcount = 0; + } + } + else + { + mcuotcr_alarmcount = 0; + } + } + + //电芯充电低温告警恢复判断 + if((bmsMem.bStatus2 & BIT14) != 0) + { + if(TemperatureMin >= utcr) + { + mcuutcr_alarmcount++; + if(mcuutcr_alarmcount > 3) + { + bmsMem.bStatus2 &= ~BIT14; + mcuutcr_alarmcount = 0; + } + } + else + { + mcuutcr_alarmcount = 0; + } + } + + //电芯放电高温告警恢复判断 + if((bmsMem.bStatus2 & BIT13) != 0) + { + if(TemperatureMax <= otdr) + { + mcuotdr_alarmcount++; + if(mcuotdr_alarmcount > 3) + { + bmsMem.bStatus2 &= ~BIT13; + mcuotdr_alarmcount = 0; + } + } + else + { + mcuotdr_alarmcount = 0; + } + } + + //电芯放电低温告警恢复判断 + if((bmsMem.bStatus2 & BIT15) != 0) + { + if(TemperatureMin >= utdr) + { + mcuutdr_alarmcount++; + if(mcuutdr_alarmcount > 3) + { + bmsMem.bStatus2 &= ~BIT15; + mcuutdr_alarmcount = 0; + } + } + else + { + mcuutdr_alarmcount = 0; + } + } +} + +//电芯温度的保护 +void Trigger_mcuTProtect(void) +{ + uint16_t otc,utc,otd,utd; + + otc = bmsMem.mcu_otc * 10 + 2731; + utc = bmsMem.mcu_utc * 10 + 2731; + otd = bmsMem.mcu_otd * 10 + 2731; + utd = bmsMem.mcu_utd * 10 + 2731; + + + if(bmsMem.packCurrent > (-500)) //非放电状态下 + { + //充电高温保护 + if((bmsMem.temperaStatus & BIT0) == 0) // 没有发生充电高温保护 + { + if(TemperatureMax > otc) + { + chg_htp_count++; + if(chg_htp_count > 3) + { + bmsMem.temperaStatus |= BIT0; //连续发生过温，保护 + chg_htp_count = 0; + } + } + else + { + chg_htp_count = 0; + } + } + + //充电低温保护 + if((bmsMem.temperaStatus & BIT2) == 0) // 没有发生充电低温保护 + { + #if DO2_Warm + if((TemperatureMin < utc) && (bCHGING == 1)) + #else + if(TemperatureMin < utc) + #endif + { + chg_ltp_count++; + if(chg_ltp_count > 3) + { + bmsMem.temperaStatus |= BIT2; //连续发生低温，保护 + chg_ltp_count = 0; + } + } + else + { + chg_ltp_count = 0; + } + } + } + else + { + bmsMem.temperaStatus &= ~BIT0; + bmsMem.temperaStatus &= ~BIT2; + } + + if(bmsMem.packCurrent < 500) //非充电状态下 + { + //放电高温保护 + if((bmsMem.temperaStatus & BIT1) == 0) // 没有发生放电高温保护 + { + if(TemperatureMax > otd) + { + dsg_htp_count++; + if(dsg_htp_count > 3) + { + bmsMem.temperaStatus |= BIT1; //连续发生过温，保护 + dsg_htp_count = 0; + } + } + else + { + dsg_htp_count = 0; + } + } + + //放电低温保护 + if((bmsMem.temperaStatus & BIT3) == 0) // 没有发生放电低温保护 + { + if(TemperatureMin < utd) + { + dsg_ltp_count++; + if(dsg_ltp_count > 3) + { + bmsMem.temperaStatus |= BIT3; //连续发生低温，保护 + dsg_ltp_count = 0; + } + } + else + { + dsg_ltp_count = 0; + } + } + } + else + { + bmsMem.temperaStatus &= ~BIT1; + bmsMem.temperaStatus &= ~BIT3; + } +} + +//电芯温度的保护释放 +void Release_mcuTProtect(void) +{ + uint16_t otcr,utcr,otdr,utdr; + + otcr = bmsMem.mcu_otcr * 10 + 2731; + utcr = bmsMem.mcu_utcr * 10 + 2731; + otdr = bmsMem.mcu_otdr * 10 + 2731; + utdr = bmsMem.mcu_utdr * 10 + 2731; + + + //充电高温保护释放 + if((bmsMem.temperaStatus & BIT0) != 0) // 发生充电高温保护 + { + if(TemperatureMax < otcr) + { + chg_htpr_count++; + if(chg_htpr_count > 3) + { + bmsMem.temperaStatus &= ~BIT0; + chg_htpr_count = 0; + } + } + else + { + chg_htpr_count = 0; + } + } + + //充电低温保护释放 + if((bmsMem.temperaStatus & BIT2) != 0) // 发生充电低温保护 + { + if(TemperatureMin > utcr) + { + chg_ltpr_count++; + if(chg_ltpr_count > 3) + { + bmsMem.temperaStatus &= ~BIT2; + chg_ltpr_count = 0; + } + } + else + { + chg_ltpr_count = 0; + } + } + + //放电高温保护释放 + if((bmsMem.temperaStatus & BIT1) != 0) // 发生放电高温保护 + { + if(TemperatureMax < otdr) + { + dsg_htpr_count++; + if(dsg_htpr_count > 3) + { + bmsMem.temperaStatus &= ~BIT1; //连续发生过温，保护 + dsg_htpr_count = 0; + } + } + else + { + dsg_htpr_count = 0; + } + } + + //放电低温保护释放 + if((bmsMem.temperaStatus & BIT3) != 0) // 发生放电低温保护 + { + if(TemperatureMin > utdr) + { + dsg_ltpr_count++; + if(dsg_ltpr_count > 3) + { + bmsMem.temperaStatus &= ~BIT3; + dsg_ltpr_count = 0; + } + } + else + { + dsg_ltpr_count = 0; + } + } +} + +//环境温度的告警 +void Trigger_amTAlarm(void) +{ + uint16_t alarm_otc,alarm_utc,alarm_otd,alarm_utd; + + //针对bmsMem.afe_T3，进行环境温度告警和告警释放 + alarm_otc = paraMem.alarm_am_otc * 10 + 2731; + alarm_utc = paraMem.alarm_am_utc * 10 + 2731; + alarm_otd = paraMem.alarm_am_otd * 10 + 2731; + alarm_utd = paraMem.alarm_am_utd * 10 + 2731; + + if(bmsMem.packCurrent > (-500)) //非放电状态下 + { + //环境充电高温告警 + if((bmsMem.temperaStatus & BIT12) == 0) + { + if(bmsMem.afe_T3 > alarm_otc) + { + am_otc_alarmcount++; + if(am_otc_alarmcount > 3) + { + bmsMem.temperaStatus |= BIT12; + am_otc_alarmcount = 0; + } + } + else + { + am_otc_alarmcount = 0; + } + } + + //环境充电低温告警 + if((bmsMem.temperaStatus & BIT14) == 0) + { + if(bmsMem.afe_T3 < alarm_utc) + { + am_utc_alarmcount++; + if(am_utc_alarmcount > 3) + { + bmsMem.temperaStatus |= BIT14; + am_utc_alarmcount = 0; + } + } + else + { + am_utc_alarmcount = 0; + } + } + } + else + { + bmsMem.temperaStatus &= ~BIT12; + bmsMem.temperaStatus &= ~BIT14; + } + + if(bmsMem.packCurrent < 500) //非充电状态下 + { + //环境放电高温告警 + if((bmsMem.temperaStatus & BIT13) == 0) // 没有发生放电高温保护 + { + if(bmsMem.afe_T3 > alarm_otd) + { + am_otd_alarmcount++; + if(am_otd_alarmcount > 3) + { + bmsMem.temperaStatus |= BIT13; //连续发生过温，保护 + am_otd_alarmcount = 0; + } + } + else + { + am_otd_alarmcount = 0; + } + } + + //环境放电低温告警 + if((bmsMem.temperaStatus & BIT15) == 0) // 没有发生放电低温保护 + { + if(bmsMem.afe_T3 < alarm_utd) + { + am_utd_alarmcount++; + if(am_utd_alarmcount > 3) + { + bmsMem.temperaStatus |= BIT15; //连续发生低温，保护 + am_utd_alarmcount = 0; + } + } + else + { + am_utd_alarmcount = 0; + } + } + } + else + { + bmsMem.temperaStatus &= ~BIT13; + bmsMem.temperaStatus &= ~BIT15; + } +} + +//环境温度的告警释放 +void Release_amTAlarm(void) +{ + uint16_t otcr,utcr,otdr,utdr; + + otcr = paraMem.am_otcr * 10 + 2731; + utcr = paraMem.am_utcr * 10 + 2731; + otdr = paraMem.am_otdr * 10 + 2731; + utdr = paraMem.am_utdr * 10 + 2731; + + + //环境充电高温告警 + if((bmsMem.temperaStatus & BIT12) !=0) + { + if(bmsMem.afe_T3 <= otcr) + { + am_otcr_alarmcount++; + if(am_otcr_alarmcount > 3) + { + bmsMem.temperaStatus &= ~BIT12; + am_otcr_alarmcount = 0; + } + } + else + { + am_otcr_alarmcount = 0; + } + } + + //环境充电低温告警 + if((bmsMem.temperaStatus & BIT14) !=0) + { + if(bmsMem.afe_T3 >= utcr) + { + am_utcr_alarmcount++; + if(am_utcr_alarmcount > 3) + { + bmsMem.temperaStatus &= ~BIT14; + am_utcr_alarmcount = 0; + } + } + else + { + am_utcr_alarmcount = 0; + } + } + + //环境放电高温告警 + if((bmsMem.temperaStatus & BIT13) !=0) // 没有发生放电高温保护 + { + if(bmsMem.afe_T3 <= otdr) + { + am_otdr_alarmcount++; + if(am_otdr_alarmcount > 3) + { + bmsMem.temperaStatus &= ~BIT13; //连续发生过温，保护 + am_otdr_alarmcount = 0; + } + } + else + { + am_otdr_alarmcount = 0; + } + } + + //环境放电低温告警 + if((bmsMem.temperaStatus & BIT15) !=0) // 没有发生放电低温保护 + { + if(bmsMem.afe_T3 >= utdr) + { + am_utdr_alarmcount++; + if(am_utdr_alarmcount > 3) + { + bmsMem.temperaStatus &= ~BIT15; //连续发生低温，保护 + am_utdr_alarmcount = 0; + } + } + else + { + am_utdr_alarmcount = 0; + } + } +} + +//环境温度的保护 +void Trigger_amTProtect(void) +{ + uint16_t otc,utc,otd,utd; + + otc = paraMem.am_otc * 10 + 2731; + utc = paraMem.am_utc * 10 + 2731; + otd = paraMem.am_otd * 10 + 2731; + utd = paraMem.am_utd * 10 + 2731; + + if(bmsMem.packCurrent > (-500)) //非放电状态下 + { + //充电高温保护 + if((bmsMem.temperaStatus & BIT8) == 0) // 没有发生充电高温保护 + { + if(bmsMem.afe_T3 > otc) + { + am_otc_count++; + if(am_otc_count > 3) + { + bmsMem.temperaStatus |= BIT8; + am_otc_count = 0; + } + } + else + { + am_otc_count = 0; + } + } + + //充电低温保护 + if((bmsMem.temperaStatus & BIT10) == 0) // 没有发生充电低温保护 + { + if(bmsMem.afe_T3 < utc) + { + am_utc_count++; + if(am_utc_count > 3) + { + bmsMem.temperaStatus |= BIT10; + am_utc_count = 0; + } + } + else + { + am_utc_count = 0; + } + } + } + else + { + bmsMem.temperaStatus &= ~BIT8; + bmsMem.temperaStatus &= ~BIT10; + } + + if(bmsMem.packCurrent < 500) //非充电状态下 + { + //放电高温保护 + if((bmsMem.temperaStatus & BIT9) == 0) // 没有发生放电高温保护 + { + if(bmsMem.afe_T3 > otd) + { + am_otd_count++; + if(am_otd_count > 3) + { + bmsMem.temperaStatus |= BIT9; + am_otd_count = 0; + } + } + else + { + am_otd_count = 0; + } + } + + //放电低温保护 + if((bmsMem.temperaStatus & BIT11) == 0) // 没有发生放电低温保护 + { + if(bmsMem.afe_T3 < utd) + { + am_utd_count++; + if(am_utd_count > 3) + { + bmsMem.temperaStatus |= BIT11; + am_utd_count = 0; + } + } + else + { + am_utd_count = 0; + } + } + } + else + { + bmsMem.temperaStatus &= ~BIT9; + bmsMem.temperaStatus &= ~BIT11; + } +} + +//环境温度的保护释放 +void Release_amTProtect(void) +{ + uint16_t otcr,utcr,otdr,utdr; + + otcr = paraMem.am_otcr * 10 + 2731; + utcr = paraMem.am_utcr * 10 + 2731; + otdr = paraMem.am_otdr * 10 + 2731; + utdr = paraMem.am_utdr * 10 + 2731; + + + //充电高温保护释放 + if((bmsMem.temperaStatus & BIT8) != 0) // 发生充电高温保护 + { + if(bmsMem.afe_T3 < otcr) + { + am_otcr_count++; + if(am_otcr_count > 3) + { + bmsMem.temperaStatus &= ~BIT8; + am_otcr_count = 0; + } + } + else + { + am_otcr_count = 0; + } + } + + //充电低温保护释放 + if((bmsMem.temperaStatus & BIT10) != 0) // 发生充电低温保护 + { + if(bmsMem.afe_T3 > utcr) + { + am_utcr_count++; + if(am_utcr_count > 3) + { + bmsMem.temperaStatus &= ~BIT10; + am_utcr_count = 0; + } + } + else + { + am_utcr_count = 0; + } + } + + //放电高温保护释放 + if((bmsMem.temperaStatus & BIT9) != 0) // 发生放电高温保护 + { + if(bmsMem.afe_T3 < otdr) + { + am_otdr_count++; + if(am_otdr_count > 3) + { + bmsMem.temperaStatus &= ~BIT9; + am_otdr_count = 0; + } + } + else + { + am_otdr_count = 0; + } + } + + //放电低温保护释放 + if((bmsMem.temperaStatus & BIT11) != 0) // 发生放电低温保护 + { + if(bmsMem.afe_T3 > utdr) + { + am_utdr_count++; + if(am_utdr_count > 3) + { + bmsMem.temperaStatus &= ~BIT11; + am_utdr_count = 0; + } + } + else + { + am_utdr_count = 0; + } + } +} + +//MOS温度的告警 +void Trigger_afeTAlarm(void) +{ + uint16_t alarm_afe_otc; //,alarm_afe_utc; + uint16_t alarm_afe_otd; //,alarm_afe_utd; + + alarm_afe_otc = paraMem.alarm_afe_otc * 10 + 2731; + //alarm_afe_utc = paraMem.alarm_afe_utc * 10 + 2731; + alarm_afe_otd = paraMem.alarm_afe_otd * 10 + 2731; + //alarm_afe_utd = paraMem.alarm_afe_utd * 10 + 2731; + + if(bmsMem.packCurrent > (-500)) //非放电状态下 + { + //MOS充电高温告警 + if((bmsMem.bStatus2 & BIT8) == 0) + { + if((bmsMem.afe_T1 > alarm_afe_otc) || (bmsMem.afe_T2 > alarm_afe_otc)) + { + afeotc_alarmcount++; + if(afeotc_alarmcount > 3) + { + bmsMem.bStatus2 |= BIT8; + afeotc_alarmcount = 0; + } + } + else + { + afeotc_alarmcount = 0; + } + } + + // //MOS充电低温告警 + // if((bmsMem.bStatus2 & BIT10) == 0) + // { + // if((bmsMem.afe_T1 < alarm_afe_utc) || (bmsMem.afe_T2 < alarm_afe_utc)) + // { + // afeutc_alarmcount++; + // if(afeutc_alarmcount > 3) + // { + // bmsMem.bStatus2 |= BIT10; + // afeutc_alarmcount = 0; + // } + // } + // else + // { + // afeutc_alarmcount = 0; + // } + // } + } + else + { + bmsMem.bStatus2 &= ~BIT8; +// bmsMem.bStatus2 &= ~BIT10; + } + + if(bmsMem.packCurrent < 500) //非充电状态下 + { + //MOS放电高温告警 + if((bmsMem.bStatus2 & BIT9) == 0) // 没有发生放电高温保护 + { + if((bmsMem.afe_T1 > alarm_afe_otd) || (bmsMem.afe_T2 > alarm_afe_otd)) + { + afeotd_alarmcount++; + if(afeotd_alarmcount > 3) + { + bmsMem.bStatus2 |= BIT9; //连续发生过温，保护 + afeotd_alarmcount = 0; + } + } + else + { + afeotd_alarmcount = 0; + } + } + + // //MOS放电低温告警 + // if((bmsMem.bStatus2 & BIT11) == 0) // 没有发生放电低温保护 + // { + // if((bmsMem.afe_T1 < alarm_afe_utd) || (bmsMem.afe_T2 < alarm_afe_utd)) + // { + // afeutd_alarmcount++; + // if(afeutd_alarmcount > 3) + // { + // bmsMem.bStatus2 |= BIT11; //连续发生低温，保护 + // afeutd_alarmcount = 0; + // } + // } + // else + // { + // afeutd_alarmcount = 0; + // } + // } + } + else + { + bmsMem.bStatus2 &= ~BIT9; +// bmsMem.bStatus2 &= ~BIT11; + } +} + +//MOS温度的告警释放 +void Release_afeTAlarm(void) +{ + uint16_t afe_otcr; //,afe_utcr; + uint16_t afe_otdr; //,afe_utdr; + + afe_otcr = bmsMem.otcr * 10 + 2731; + //afe_utcr = bmsMem.utcr * 10 + 2731; + afe_otdr = bmsMem.otdr * 10 + 2731; + //afe_utdr = bmsMem.utdr * 10 + 2731; + + + //MOS充电高温告警恢复 + if((bmsMem.bStatus2 & BIT8) != 0) + { + if((bmsMem.afe_T1 <= afe_otcr) && (bmsMem.afe_T2 <= afe_otcr)) + { + afeotcr_alarmcount++; + if(afeotcr_alarmcount > 3) + { + bmsMem.bStatus2 &= ~BIT8; + afeotcr_alarmcount = 0; + } + } + else + { + afeotcr_alarmcount = 0; + } + } + +// //MOS充电低温告警恢复 +// if((bmsMem.bStatus2 & BIT10) != 0) +// { +// if((bmsMem.afe_T1 >= afe_utcr) && (bmsMem.afe_T2 >= afe_utcr)) +// { +// afeutcr_alarmcount++; +// if(afeutcr_alarmcount > 3) +// { +// bmsMem.bStatus2 &= ~BIT10; +// afeutcr_alarmcount = 0; +// } +// } +// else +// { +// afeutcr_alarmcount = 0; +// } +// } + + //MOS放电高温告警恢复 + if((bmsMem.bStatus2 & BIT9) != 0) // 没有发生放电高温保护 + { + if((bmsMem.afe_T1 <= afe_otdr) && (bmsMem.afe_T2 <= afe_otdr)) + { + afeotdr_alarmcount++; + if(afeotdr_alarmcount > 3) + { + bmsMem.bStatus2 &= ~BIT9; //连续发生过温，保护 + afeotdr_alarmcount = 0; + } + } + else + { + afeotdr_alarmcount = 0; + } + } + +// //MOS放电低温告警恢复 +// if((bmsMem.bStatus2 & BIT11) != 0) // 没有发生放电低温保护 +// { +// if((bmsMem.afe_T1 >= afe_utdr) && (bmsMem.afe_T2 >= afe_utdr)) +// { +// afeutdr_alarmcount++; +// if(afeutdr_alarmcount > 3) +// { +// bmsMem.bStatus2 &= ~BIT11; //连续发生低温，保护 +// afeutdr_alarmcount = 0; +// } +// } +// else +// { +// afeutdr_alarmcount = 0; +// } +// } +} + +//MOS温度的保护 +void Trigger_afeTProtect(void) +{ + uint16_t afe_otc; + uint16_t afe_otd; + + afe_otc = bmsMem.otc * 10 + 2731; + afe_otd = bmsMem.otd * 10 + 2731; + + if(bmsMem.packCurrent > (-500)) //非放电状态下 + { + //MOS充电高温保护 + if((bmsMem.bStatus2 & BIT1) == 0) + { + if((bmsMem.afe_T1 > afe_otc) || (bmsMem.afe_T2 > afe_otc)) + { + afeotc_count++; + if(afeotc_count > 3) + { + bmsMem.bStatus2 |= BIT1; + afeotc_count = 0; + } + } + else + { + afeotc_count = 0; + } + } +// //MOS充电低温保护 +// if((bmsMem.bStatus2 & BIT0) == 0) +// { +// if((bmsMem.afe_T1 < afe_utc) || (bmsMem.afe_T2 < afe_utc)) +// { +// afeutc_count++; +// if(afeutc_count > 3) +// { +// bmsMem.bStatus2 |= BIT0; +// afeutc_count = 0; +// } +// } +// else +// { +// afeutc_count = 0; +// } +// } + } + else + { + bmsMem.bStatus2 &= ~BIT1; +// bmsMem.bStatus2 &= ~BIT0; + } + + if(bmsMem.packCurrent < 500) //非充电状态下 + { + //MOS放电高温保护 + if((bmsMem.bStatus2 & BIT3) == 0) // 没有发生放电高温保护 + { + if((bmsMem.afe_T1 > afe_otd) || (bmsMem.afe_T2 > afe_otd)) + { + afeotd_count++; + if(afeotd_count > 3) + { + bmsMem.bStatus2 |= BIT3; //连续发生过温，保护 + afeotd_count = 0; + } + } + else + { + afeotd_count = 0; + } + } +// //MOS放电低温保护 +// if((bmsMem.bStatus2 & BIT2) == 0) // 没有发生放电低温保护 +// { +// if((bmsMem.afe_T1 < afe_utd) || (bmsMem.afe_T2 < afe_utd)) +// { +// afeutd_count++; +// if(afeutd_count > 3) +// { +// bmsMem.bStatus2 |= BIT2; //连续发生低温，保护 +// afeutd_count = 0; +// } +// } +// else +// { +// afeutd_count = 0; +// } +// } + } + else + { + bmsMem.bStatus2 &= ~BIT3; +// bmsMem.bStatus2 &= ~BIT2; + } +} + +//MOS温度的保护释放 +void Release_afeTProtect(void) +{ + uint16_t afe_otcr; + uint16_t afe_otdr; + + afe_otcr = bmsMem.otcr * 10 + 2731; + afe_otdr = bmsMem.otdr * 10 + 2731; + + + //MOS充电高温保护恢复 + if((bmsMem.bStatus2 & BIT1) != 0) + { + if((bmsMem.afe_T1 <= afe_otcr) && (bmsMem.afe_T2 <= afe_otcr)) + { + afeotcr_count++; + if(afeotcr_count > 3) + { + bmsMem.bStatus2 &= ~BIT1; + afeotcr_count = 0; + } + } + else + { + afeotcr_count = 0; + } + } + + //MOS放电高温保护恢复 + if((bmsMem.bStatus2 & BIT3) != 0) // 没有发生放电高温保护 + { + if((bmsMem.afe_T1 <= afe_otdr) && (bmsMem.afe_T2 <= afe_otdr)) + { + afeotdr_count++; + if(afeotdr_count > 3) + { + bmsMem.bStatus2 &= ~BIT3; //连续发生过温，保护 + afeotdr_count = 0; + } + } + else + { + afeotdr_count = 0; + } + } +} + +#if LTE_Conn +//存放事件记录：广泛可用，又防止意外写错 +uint8_t Protect[21] = +{ + 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, + 0x30, 0x31, 0x32, 0x33, 0x34, + 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49 +}; + +void Write_Change(uint8_t code) +{ + uint8_t i; + + staChange_time[staChange_num] = timecount; + staChange[staChange_num] = code; + staChange_num++; + + //确认该次事件的优先级 + incident_DataInf = 1; + for(i=0;i<21;i++) + { + if(code == Protect[i]) //遍历保护 + { + incident_DataInf = 2; + } + } + + //保存此时的属性，若连续发生多个，只能记住第1个 + //优先级：保护触发>其他 + if((incident_DataFlg < 2) && (incident_DataInf == 2)) + { + incident_DataFlg = 2; + LTE_Record_pubData(); + } + else if((incident_DataFlg < 1) && (incident_DataInf == 1)) + { + incident_DataFlg = 1; + LTE_Record_pubData(); + } +} + +//事件[发生和释放]的判断与记录 +//code: 记录事件的对应码 +void Check_Change(uint8_t STA_i, uint16_t BIT_n, uint8_t code) +{ + if((status_Old[STA_i] & BIT_n) == 0) + { + if((status_New[STA_i] & BIT_n) != 0) //事件触发，未记录 + { + status_Old[STA_i] |= BIT_n; + Write_Change(code); + } + } + else + { + if((status_New[STA_i] & BIT_n) == 0) //事件消失，恢复标志位 + { + status_Old[STA_i] &= ~BIT_n; + Write_Change(code+0x80); + } + } +} + +//事件[发生]的判断与记录，释放直接释放 +//code: 记录事件的对应码 +void Check_OnlyOn(uint8_t STA_i, uint16_t BIT_n, uint8_t code) +{ + if((status_Old[STA_i] & BIT_n) == 0) + { + if((status_New[STA_i] & BIT_n) != 0) //事件触发，未记录 + { + status_Old[STA_i] |= BIT_n; + Write_Change(code); + } + } + else + { + if((status_New[STA_i] & BIT_n) == 0) //事件消失，恢复标志位 + { + status_Old[STA_i] &= ~BIT_n; + } + } +} + +//应上报的状态转变的判断 +void Check_staChange(void) +{ + //Check_OnlyOn(0, BIT1, 0x01); //充电状态 + //Check_OnlyOn(0, BIT2, 0x02); //放电状态 + Check_Change(0, BIT3, 0x03); //预充状态 + Check_Change(0, BIT4, 0x04); //充电MOS状态 + Check_Change(0, BIT5, 0x05); //放电MOS状态 + //Check_Change(0, BIT6, 0x06); //预充MOS状态 + Check_Change(0, BIT7, 0x07); //充电限流状态 + //Check_Change(0, BIT8, 0x08); //均衡控制状态 + + Check_OnlyOn(1, BIT0, 0x10); //充电过流保护多次锁定 + Check_OnlyOn(1, BIT1, 0x11); //放电过流1保护多次锁定 + Check_OnlyOn(1, BIT2, 0x12); //放电过流2保护多次锁定 + Check_OnlyOn(1, BIT3, 0x13); //浪涌保护多次锁定 + Check_OnlyOn(1, BIT4, 0x14); //短路保护多次锁定 + Check_Change(1, BIT5, 0x15); //充电MOS故障 + Check_Change(1, BIT6, 0x16); //放电MOS故障 + Check_Change(1, BIT7, 0x17); //DO脱扣器功能 + Check_Change(1, BIT8, 0x18); //强制关闭欠压保护功能 +} + +//应上报的的判断 +void Check_protectChange(void) +{ + Check_Change(2, BIT0, 0x20); //总体过压保护 + Check_Change(2, BIT1, 0x21); //总体欠压保护 + Check_Change(2, BIT2, 0x22); //单体过压保护 + Check_Change(2, BIT3, 0x23); //单体欠压保护 + Check_OnlyOn(2, BIT4, 0x24); //异常高压保护 + Check_OnlyOn(2, BIT5, 0x25); //低电压禁止充电 + + Check_Change(3, BIT0, 0x30); //充电过流保护 + Check_Change(3, BIT1, 0x31); //放电过流1保护 + Check_Change(3, BIT2, 0x32); //放电过流2保护 + Check_Change(3, BIT3, 0x33); //浪涌保护 + Check_Change(3, BIT4, 0x34); //短路保护 + + Check_Change(4, BIT0, 0x40); //电芯充电高温保护 + Check_Change(4, BIT1, 0x41); //电芯放电高温保护 + Check_Change(4, BIT2, 0x42); //电芯充电低温保护 + Check_Change(4, BIT3, 0x43); //电芯放电低温保护 + Check_Change(4, BIT4, 0x44); //环境充电高温保护 + Check_Change(4, BIT5, 0x45); //环境放电高温保护 + Check_Change(4, BIT6, 0x46); //环境充电低温保护 + Check_Change(4, BIT7, 0x47); //环境放电低温保护 + Check_Change(4, BIT8, 0x48); //MOS充电高温保护 + Check_Change(4, BIT9, 0x49); //MOS放电高温保护 + //Check_Change(4, BIT10, 0x4A); //MOS充电低温保护 + //Check_Change(4, BIT11, 0x4B); //MOS放电低温保护 +} + +//应上报的报警的判断 +void Check_warningChange(void) +{ +// Check_Change(5, BIT0, 0x50); //总体过压报警 +// Check_Change(5, BIT1, 0x51); //总体欠压报警 +// Check_Change(5, BIT2, 0x52); //单体过压报警 +// Check_Change(5, BIT3, 0x53); //单体欠压报警 +// +// Check_Change(6, BIT0, 0x60); //充电过流报警 +// Check_Change(6, BIT1, 0x61); //放电过流报警 +// +// Check_Change(7, BIT0, 0x70); //电芯充电高温报警 +// Check_Change(7, BIT1, 0x71); //电芯放电高温报警 +// Check_Change(7, BIT2, 0x72); //电芯充电低温报警 +// Check_Change(7, BIT3, 0x73); //电芯放电低温报警 +// Check_Change(7, BIT4, 0x74); //环境充电高温报警 +// Check_Change(7, BIT5, 0x75); //环境放电高温报警 +// Check_Change(7, BIT6, 0x76); //环境充电低温报警 +// Check_Change(7, BIT7, 0x77); //环境放电低温报警 +// Check_Change(7, BIT8, 0x78); //MOS充电高温报警 +// Check_Change(7, BIT9, 0x79); //MOS放电高温报警 +// //Check_Change(7, BIT10, 0x7A); //MOS充电低温报警 +// //Check_Change(7, BIT11, 0x7B); //MOS放电低温报警 +} + +//应上报的告警/保护/故障/加热/状态，转变的判断 每1s执行1次 +void Check_eventChange(void) +{ + //清零 + NomalStatus = 0; + SpecialStatus = 0; + Protect_Vol = 0; + Protect_Cur = 0; + Protect_Temp = 0; + Warning_Vol = 0; + Warning_Cur = 0; + Warning_Temp = 0; + + /*更新标志*/ + //常见状态 + NomalStatus |= ChargeStatus<<1; + NomalStatus |= DischargeStatus<<2; + NomalStatus |= PreChargeStatus<<3; + //NomalStatus |= ChgMosStatus<<4; + //NomalStatus |= DsgMosStatus<<5; + //NomalStatus |= PchgMosStatus<<6; + NomalStatus |= ChgLimitStatus<<7; + NomalStatus |= BalanceStatus<<8; + //特殊状态 + SpecialStatus |= LockOCC<<0; + SpecialStatus |= LockOCD1<<1; + SpecialStatus |= LockOCD2<<2; + SpecialStatus |= LockSP<<3; + SpecialStatus |= LockSC<<4; + SpecialStatus |= ChgMosFault<<5; + SpecialStatus |= DsgMosFault<<6; + SpecialStatus |= DOStatus<<7; + SpecialStatus |= ForceOffUV<<8; + //保护 + Protect_Vol |= PackOV<<0; + Protect_Vol |= PackUV<<1; + Protect_Vol |= CellOV<<2; + Protect_Vol |= CellUV<<3; + Protect_Vol |= PF<<4; + Protect_Vol |= L0V<<5; + Protect_Cur |= OCC<<0; + Protect_Cur |= OCD1<<1; + Protect_Cur |= OCD2<<2; + Protect_Cur |= SP<<3; + Protect_Cur |= SC<<4; + Protect_Temp |= McuOTC<<0; + Protect_Temp |= McuOTD<<1; + Protect_Temp |= McuUTC<<2; + Protect_Temp |= McuUTD<<3; + Protect_Temp |= AmbientOTC<<4; + Protect_Temp |= AmbientOTD<<5; + Protect_Temp |= AmbientUTC<<6; + Protect_Temp |= AmbientUTD<<7; + Protect_Temp |= MosOTC<<8; + Protect_Temp |= MosOTD<<9; + Protect_Temp |= MosUTC<<10; + Protect_Temp |= MosUTD<<11; + //报警 + Warning_Vol |= PackOVWarning<<0; + Warning_Vol |= PackUVWarning<<1; + Warning_Vol |= CellOVWarning<<2; + Warning_Vol |= CellUVWarning<<3; + Warning_Cur |= OCCWarning<<0; + Warning_Cur |= OCDWarning<<1; + Warning_Temp |= McuOTCWarning<<0; + Warning_Temp |= McuOTDWarning<<1; + Warning_Temp |= McuUTCWarning<<2; + Warning_Temp |= McuUTDWarning<<3; + Warning_Temp |= AmbientOTCWarning<<4; + Warning_Temp |= AmbientOTDWarning<<5; + Warning_Temp |= AmbientUTCWarning<<6; + Warning_Temp |= AmbientUTDWarning<<7; + Warning_Temp |= MosOTCWarning<<8; + Warning_Temp |= MosOTDWarning<<9; + //Warning_Temp |= MosUTCWarning<<10; + //Warning_Temp |= MosUTDWarning<<11; + + status_New[0] = NomalStatus; + status_New[1] = SpecialStatus; + status_New[2] = Protect_Vol; + status_New[3] = Protect_Cur; + status_New[4] = Protect_Temp; + status_New[5] = Warning_Vol; + status_New[6] = Warning_Cur; + status_New[7] = Warning_Temp; + + //检查新变动 + if(staChange_num < MaxSaveNum) //超出个数后不再记录，直到发完 + { + Check_staChange(); + Check_protectChange(); + Check_warningChange(); + } +} + +//解析的固定格式 +void To_incident(uint8_t flag, const char* str, uint8_t len) +{ + incident_str = str; //事件名称 + incident_len = len; //事件名称长度 + incident_flag = flag; //上报true/false +} + +//4G模块上报事件的解析 +//code: 记录事件的对应码 +//str: 事件名称 +//len: 事件名称的长度 +void Explain_incident(uint8_t code, const char* str, uint8_t len) +{ + if(staChange[staChange_index] == code) + { + To_incident(1, str, len); //上报true + } + else if(staChange[staChange_index] == code+0x80) + { + To_incident(2, str, len); //上报false + } +} + +//4G模块上报[事件] +void Transmit_incident(void) +{ + //判断是否要上传事件 + if(incident_flag == 0) //1次只上传1条，若之前有事件还在上传，不进行处理 + { + if(staChange_num != 0) //存在事件 + { + //if(staChange[staChange_index] == 0x01) + //{ + // To_incident(1, "ChargeStatus", 12); + //} + //else if(staChange[staChange_index] == 0x02) + //{ + // To_incident(1, "DischargeStatus", 15); + //} + + Explain_incident(0x03, "PreChargeStatus", 15); //预充状态 + Explain_incident(0x04, "ChgMosStatus", 12); //充电MOS状态 + Explain_incident(0x05, "DsgMosStatus", 12); //放电MOS状态 + //Explain_incident(0x06, "PchgMosStatus", 13); //预充MOS状态 + Explain_incident(0x07, "ChgLimitStatus", 14); //充电限流状态 + //Explain_incident(0x08, "BalanceStatus", 13); //均衡控制状态 + + Explain_incident(0x10, "LockOCC", 7); //充电过流保护多次锁定 + Explain_incident(0x11, "LockOCD1", 8); //放电过流1保护多次锁定 + Explain_incident(0x12, "LockOCD2", 8); //放电过流2保护多次锁定 + Explain_incident(0x13, "LockSP", 6); //浪涌保护多次锁定 + Explain_incident(0x14, "LockSC", 6); //短路保护多次锁定 + Explain_incident(0x15, "ChgMosFault", 11); //充电MOS故障 + Explain_incident(0x16, "DsgMosFault", 11); //放电MOS故障 + Explain_incident(0x17, "DOStatus", 8); //DO脱扣器功能 + Explain_incident(0x18, "ForceOffUV", 10); //强制关闭欠压保护功能 + + Explain_incident(0x20, "PackOV", 6); //总体过压保护 + Explain_incident(0x21, "PackUV", 6); //总体欠压保护 + Explain_incident(0x22, "CellOV", 6); //单体过压保护 + Explain_incident(0x23, "CellUV", 6); //单体欠压保护 + Explain_incident(0x24, "PF", 2); //异常高压保护 + Explain_incident(0x25, "L0V", 2); //低电压禁止充电 + Explain_incident(0x30, "OCC", 3); //充电过流保护 + Explain_incident(0x31, "OCD1", 4); //放电过流1保护 + Explain_incident(0x32, "OCD2", 4); //放电过流2保护 + Explain_incident(0x33, "SP", 2); //浪涌保护 + Explain_incident(0x34, "SC", 2); //短路保护 + Explain_incident(0x40, "McuOTC", 6); //电芯充电高温保护 + Explain_incident(0x41, "McuOTD", 6); //电芯放电高温保护 + Explain_incident(0x42, "McuUTC", 6); //电芯充电低温保护 + Explain_incident(0x43, "McuUTD", 6); //电芯放电低温保护 + Explain_incident(0x44, "AmbientOTC", 10); //环境充电高温保护 + Explain_incident(0x45, "AmbientOTD", 10); //环境放电高温保护 + Explain_incident(0x46, "AmbientUTC", 10); //环境充电低温保护 + Explain_incident(0x47, "AmbientUTD", 10); //环境放电低温保护 + Explain_incident(0x48, "MosOTC", 6); //MOS充电高温保护 + Explain_incident(0x49, "MosOTD", 6); //MOS放电高温保护 + //Explain_incident(0x4A, "MosUTC", 6); //MOS充电低温保护 + //Explain_incident(0x4B, "MosUTD", 6); //MOS放电低温保护 + +// Explain_incident(0x50, "PackOVWarning", 6+7); //总体过压报警 +// Explain_incident(0x51, "PackUVWarning", 6+7); //总体欠压报警 +// Explain_incident(0x52, "CellOVWarning", 6+7); //单体过压报警 +// Explain_incident(0x53, "CellUVWarning", 6+7); //单体欠压报警 +// Explain_incident(0x60, "OCCWarning", 3+7); //充电过流报警 +// Explain_incident(0x61, "OCDWarning", 3+7); //放电过流报警 +// Explain_incident(0x70, "McuOTCWarning", 6+7); //电芯充电高温报警 +// Explain_incident(0x71, "McuOTDWarning", 6+7); //电芯放电高温报警 +// Explain_incident(0x72, "McuUTCWarning", 6+7); //电芯充电低温报警 +// Explain_incident(0x73, "McuUTDWarning", 6+7); //电芯放电低温报警 +// Explain_incident(0x74, "AmbientOTCWarning", 10+7); //环境充电高温报警 +// Explain_incident(0x75, "AmbientOTDWarning", 10+7); //环境放电高温报警 +// Explain_incident(0x76, "AmbientUTCWarning", 10+7); //环境充电低温报警 +// Explain_incident(0x77, "AmbientUTDWarning", 10+7); //环境放电低温报警 +// Explain_incident(0x78, "MosOTCWarning", 6+7); //MOS充电高温报警 +// Explain_incident(0x79, "MosOTDWarning", 6+7); //MOS放电高温报警 +// //Explain_incident(0x7A, "MosUTCWarning", 6+7); //MOS充电低温报警 +// //Explain_incident(0x7B, "MosUTDWarning", 6+7); //MOS放电低温报警 + + + //发生时间 + incident_time = staChange_time[staChange_index]; + incident_len += uint_str_len(incident_time); + + + //发送完最后一个，清空数组 + staChange_index++; + if((staChange_index >= staChange_num) || (staChange_num > MaxSaveNum)) //当存储事件全部上报，清零重新积累 //总个数最大50，存在异常先清零 + { + staChange_index = 0; + staChange_num = 0; + memset(staChange, 0, MaxSaveNum+5); //清零数组 + memset(staChange_time, 0, MaxSaveNum+5); + } + } + } +} +#endif + diff --git a/MOUDLE/YiBang.c b/MOUDLE/YiBang.c new file mode 100644 index 0000000..e445415 --- /dev/null +++ b/MOUDLE/YiBang.c @@ -0,0 +1,1004 @@ +/** + ****************************************************************************** + * @file YiBang.c + * @author + * @version + * @date + * @brief + ****************************************************************************** + * @attention + * + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" +#include "global.h" +#include "string.h" +#include +#include + + +#if WIFI_Conn +//通用定义 +#define PIN_WIFI_RST GPIO_Pin_2 //PC2 0:不做处理 1:WIFI复位 + +#define WIFI_UART UART4 +#define WIFI_Send WIFI_printf + +#define WIFI_MON_CNT 6000 //6000*10ms = 60s +#define WIFI_RX_BUF_LEN 512 //接收的最大长度 +#define WIFI_TX_BUF_LEN 128 //发送的最大长度 +#define WIFI_ORDER_LEN 128 //回复指令的缓冲区的最大长度 + +char WIFI_Rx_Buf[WIFI_RX_BUF_LEN]; +char WIFI_Tx_Buf[WIFI_TX_BUF_LEN]; +char WIFI_buffer[WIFI_ORDER_LEN]; + +uint16_t WIFI_Rx_BufIndex; +uint16_t WIFI_Moni_Count; + + +//状态/保护/报警的字符串：false/true +//固定发： +//状态 +const char* WIFI_ChargeStatus_str; +const char* WIFI_DischargeStatus_str; +const char* WIFI_PreChargeStatus_str; +const char* WIFI_ChgMosStatus_str; +const char* WIFI_DsgMosStatus_str; +const char* WIFI_PchgMosStatus_str; +const char* WIFI_ChgLimitStatus_str; +const char* WIFI_BalanceStatus_str; +//出现才发： +uint8_t WIFI_SendFlag; //bit0:发特殊状态 bit1:发保护 bit2:发报警 +//特殊状态 +uint8_t WIFI_SendStatus[9]; //出现则赋值1，否则赋值0 +//保护 +uint8_t WIFI_SendProtect_Vol[6]; +uint8_t WIFI_SendProtect_Cur[5]; +uint8_t WIFI_SendProtect_Temp[12]; +//报警 +uint8_t WIFI_SendWarning_Vol[4]; +uint8_t WIFI_SendWarning_Cur[2]; +uint8_t WIFI_SendWarning_Temp[12]; + + +uint8_t WIFI_01_RxFlg; //WIFI收到请求采集数据的标志 +uint8_t WIFI_04_RxFlg; //WIFI收到请求写参数的标志 +uint8_t WIFI_05_RxFlg; //WIFI收到请求读参数的标志 + +uint8_t WIFI_01_TxStep; //执行步骤 0:第一部分 1:第二部分 …… + + +//WIFI专用的printf函数 +int WIFI_printf(const char *fmt, ...) +{ + va_list args; + va_start(args, fmt); + int len = vsnprintf(WIFI_Tx_Buf, sizeof(WIFI_Tx_Buf), fmt, args); + va_end(args); + + for(int i = 0; i < len; i++) + { + while(!(UART4->SR & USART_SR_TXE)); // 等待发送完成 + UART4->DR = WIFI_Tx_Buf[i]; + } + + return len; +} + +//相关引脚初始化 +void WIFI_IO_Init(void) +{ + //初始化引脚 + GPIO_InitTypeDef GPIO_InitStructure; + + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC , ENABLE); + + GPIO_InitStructure.GPIO_Pin = PIN_WIFI_RST; //WIFI复位控制引脚 + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOC, &GPIO_InitStructure); + + GPIO_ResetBits(GPIOC, PIN_WIFI_RST); //WIFI复位控制脚，默认关闭状态 +} + +//开机 +void WIFI_Open(void) +{ + //预留 +} + +//关机 +void WIFI_Close(void) +{ + //预留 +} + +//复位 +void WIFI_Reset(void) +{ +// GPIO_ResetBits(GPIOC, PIN_WIFI_RST); +// delay_ms(200); +// GPIO_SetBits(GPIOC, PIN_WIFI_RST); +// delay_ms(200); +// GPIO_ResetBits(GPIOC, PIN_WIFI_RST); +} + +//清空标志 +void WIFI_ClearFlg(void) +{ + WIFI_01_RxFlg = 0; + WIFI_04_RxFlg = 0; + WIFI_05_RxFlg = 0; + + WIFI_01_TxStep = 0; + + setPara_reply_flg = 0; + getPara_reply_flg = 0; +} + +//清空接收缓冲区 +void WIFI_ClearBuf(void) +{ + WIFI_Rx_BufIndex = 0; + memset(WIFI_Rx_Buf, 0, WIFI_RX_BUF_LEN); +} + +//初始化通讯 +void WIFI_Init(void) +{ + WIFI_ClearFlg(); + WIFI_ClearBuf(); + + WIFI_Moni_Count = WIFI_MON_CNT; + uf_UART4_Init(115200); +} + +//一定时间没有连接任何设备，初始化通讯，并再次更新名称 +void WIFI_TIM_Moni(void) +{ + WIFI_Moni_Count--; + if(WIFI_Moni_Count == 0) + { + WIFI_Init(); + } +} + +//WIFI写参数 +void WIFI_SETPARA(void) +{ + if(strstr(WIFI_Rx_Buf, "\"data\":{") && strstr(WIFI_Rx_Buf, "}}")) + { + char para_str[6]; //0~65535 或 -32768~32767 + uint8_t len = 0; //字符串长度 + uint16_t temp; //无符号过程量 + + //获取原始数据，包括'{''}' + const char* paramsKey = "\"data\":"; + char* paramsStart = strstr(WIFI_Rx_Buf, paramsKey); paramsStart += strlen(paramsKey); + char* paramsEnd = strchr(paramsStart, '}'); + len = paramsEnd - paramsStart; + if(len > sizeof(params_str)-2) //防溢出 + { + len = sizeof(params_str)-2; + } + strncpy(params_str, paramsStart, len); + params_str[len] = '}'; + params_str[len+1] = '\0'; + + + //识别存在的参数，并给予对应值 + setPara_reply_num = 0; + + if(strstr(params_str, "\"Protocol\"")) //写协议 + { + //获取参数值 + len = GetStr("\"Protocol\":", ',', '}', params_str, para_str); + sscanf(para_str, "%hu", &temp); + + //符合范围的放入 + if(((int)temp >= 0) && (temp <= ProtocolSum) && (len > 0)) //0~38 + { + protocol = temp; + + EEPROM_WrMulByte(EE_PROTOCOL,&protocol); + delay_ms(5); + uf_CAN1_Init();//CAN的波特率更新 + //SCR_DispProcotol(); //屏幕显示更新 + + protocol_reply_flg = 1; + protocol_reply_index = setPara_reply_num; + + //准备回复 + setPara_reply_name[setPara_reply_num] = "Protocol"; + setPara_reply_temp[setPara_reply_num] = temp; + setPara_reply_num++; + } + else + { + setPara_reply_flg = 0xBB; //参数值超出范围，设备拒绝执行 + } + } + + if(setPara_reply_num > 0) + { + setPara_reply_flg = 1; //正常回复 + } + else if(setPara_reply_flg != 0xBB) //无任何符合的值&不是因为参数不符合范围 + { + setPara_reply_flg = 0xAA; //设备无该属性 + } + } + else + { + setPara_reply_flg = 0xBB; //设备拒绝执行 + } +} + +//WIFI读参数 +void WIFI_GETPARA(void) +{ + if(strstr(WIFI_Rx_Buf, "\"params\":[") && strstr(WIFI_Rx_Buf, "]}")) + { + uint16_t len = 0; //字符串长度 + + //获取原始数据 + const char* paramsKey = "\"params\":["; + char* paramsStart = strstr(WIFI_Rx_Buf, paramsKey); paramsStart += strlen(paramsKey); + char* paramsEnd = strchr(paramsStart, ']'); + len = paramsEnd - paramsStart; + if(len > sizeof(params_str)-1) //防溢出 + { + len = sizeof(params_str)-1; + } + strncpy(params_str, paramsStart, len); + params_str[len] = '\0'; + + //识别存在的参数，并给予对应值 + getPara_reply_num = 0; + + if(strstr(params_str, "\"Protocol\"")) //读协议 + { + protocol_reply_flg = 1; + protocol_reply_index = getPara_reply_num; + + //准备回复 + getPara_reply_name[getPara_reply_num] = "protocol"; + getPara_reply_temp[getPara_reply_num] = protocol; + getPara_reply_num++; + } + + if(getPara_reply_num > 0) + { + getPara_reply_flg = 1; //回复 + } + else //无任何符合的值 + { + getPara_reply_flg = 0xAA; //设备无该属性 + } + } + else + { + getPara_reply_flg = 0xBB; //设备拒绝执行 + } +} + +//接收数据，在串口中断执行 +void WIFI_IT_Receive(void) +{ + uint8_t received_byte = USART_ReceiveData(WIFI_UART); + + if(WIFI_Rx_BufIndex < WIFI_RX_BUF_LEN - 1) + { + WIFI_Rx_Buf[WIFI_Rx_BufIndex] = received_byte; + WIFI_Rx_BufIndex++; + } + else + { + WIFI_ClearBuf(); + } + + //更新计时 + WIFI_Moni_Count = WIFI_MON_CNT; +} + +//处理数据，接收报文识别后执行 +//波特率115200 +void WIFI_IT_Update(void) +{ + if(strstr(WIFI_Rx_Buf,"\"dataType\":\"0x01\"")) //收到"0x01"发送采集数据 + { + WIFI_01_RxFlg = 1; + WIFI_ClearBuf(); + } + else if(strstr(WIFI_Rx_Buf,"\"dataType\":\"0x04\"")) //收到"0x04"开始解析数据 写参数 + { + WIFI_SETPARA(); + + WIFI_04_RxFlg = 1; + WIFI_ClearBuf(); + } + else if(strstr(WIFI_Rx_Buf,"\"dataType\":\"0x05\"")) //收到"0x05"开始解析数据 读参数 + { + WIFI_GETPARA(); + + WIFI_05_RxFlg = 1; + WIFI_ClearBuf(); + } +} + +//根据当前已知信息，选择接下来要执行的指令，0.1s执行1次 +void WIFI_IQ_Update(void) +{ + if(WIFI_01_RxFlg == 1) //WIFI请求采集数据 + { + WIFI_01_TxStep++; + + if(WIFI_01_TxStep == 1) //状态：固定发送 + { + //更新true/false + WIFI_ChargeStatus_str = Status[ChargeStatus]; + WIFI_DischargeStatus_str = Status[DischargeStatus]; + WIFI_PreChargeStatus_str = Status[PreChargeStatus]; + WIFI_ChgMosStatus_str = Status[ChgMosStatus]; + WIFI_DsgMosStatus_str = Status[DsgMosStatus]; + WIFI_PchgMosStatus_str = Status[PchgMosStatus]; + WIFI_ChgLimitStatus_str = Status[ChgLimitStatus]; + WIFI_BalanceStatus_str = Status[BalanceStatus]; + } + else if(WIFI_01_TxStep == 3) //特殊状态：当前存在任一状态才发送 + { + if(((bmsMem.bStatus2 & 0x00C0) != 0) || ((bmsMem.temperaStatus & 0x0080) != 0) || ((bmsMem.balanceStatus & 0x07E0) != 0)) + { + WIFI_SendFlag |= BIT0; + + //更新1:true/0:false + WIFI_SendStatus[0] = LockOCC; + WIFI_SendStatus[1] = LockOCD1; + WIFI_SendStatus[2] = LockOCD2; + WIFI_SendStatus[3] = LockSP; + WIFI_SendStatus[4] = LockSC; + WIFI_SendStatus[5] = ChgMosFault; + WIFI_SendStatus[6] = DsgMosFault; + WIFI_SendStatus[7] = DOStatus; + WIFI_SendStatus[8] = ForceOffUV; + } + else + { + WIFI_SendFlag &= ~BIT0; + } + } + else if(WIFI_01_TxStep == 4) //保护：当前存在任一状态才发送 + { + if(((bmsMem.bStatus1 & 0x077f) != 0) || ((bmsMem.bStatus2 & 0x00ff) !=0) || ((bmsMem.bStatus3 & 0x0008) !=0) || ((bmsMem.temperaStatus & 0x0f7f) !=0)) + { + WIFI_SendFlag |= BIT1; + + //更新1:true/0:false + WIFI_SendProtect_Vol[0] = PackOV; + WIFI_SendProtect_Vol[1] = PackUV; + WIFI_SendProtect_Vol[2] = CellOV; + WIFI_SendProtect_Vol[3] = CellUV; + WIFI_SendProtect_Vol[4] = PF; + WIFI_SendProtect_Vol[5] = L0V; + + WIFI_SendProtect_Cur[0] = OCC; + WIFI_SendProtect_Cur[1] = OCD1; + WIFI_SendProtect_Cur[2] = OCD2; + WIFI_SendProtect_Cur[3] = SP; + WIFI_SendProtect_Cur[4] = SC; + + WIFI_SendProtect_Temp[0] = McuOTC; + WIFI_SendProtect_Temp[1] = McuOTD; + WIFI_SendProtect_Temp[2] = McuUTC; + WIFI_SendProtect_Temp[3] = McuUTD; + WIFI_SendProtect_Temp[4] = AmbientOTC; + WIFI_SendProtect_Temp[5] = AmbientOTD; + WIFI_SendProtect_Temp[6] = AmbientUTC; + WIFI_SendProtect_Temp[7] = AmbientUTD; + WIFI_SendProtect_Temp[8] = MosOTC; + WIFI_SendProtect_Temp[9] = MosOTD; + WIFI_SendProtect_Temp[10] = MosUTC; + WIFI_SendProtect_Temp[11] = MosUTD; + } + else + { + WIFI_SendFlag &= ~BIT1; + } + } + else if(WIFI_01_TxStep == 5) //报警：当前存在任一状态才发送 + { + if(((bmsMem.bStatus2 & 0xff00) !=0) || ((bmsMem.bStatus3 & 0x3f00) !=0) || ((bmsMem.temperaStatus & 0xf000) !=0)) + { + WIFI_SendFlag |= BIT2; + + //更新1:true/0:false + WIFI_SendWarning_Vol[0] = PackOVWarning; + WIFI_SendWarning_Vol[1] = PackUVWarning; + WIFI_SendWarning_Vol[2] = CellOVWarning; + WIFI_SendWarning_Vol[3] = CellUVWarning; + + WIFI_SendWarning_Cur[0] = OCCWarning; + WIFI_SendWarning_Cur[1] = OCDWarning; + + WIFI_SendWarning_Temp[0] = McuOTCWarning; + WIFI_SendWarning_Temp[1] = McuOTDWarning; + WIFI_SendWarning_Temp[2] = McuUTCWarning; + WIFI_SendWarning_Temp[3] = McuUTDWarning; + WIFI_SendWarning_Temp[4] = AmbientOTCWarning; + WIFI_SendWarning_Temp[5] = AmbientOTDWarning; + WIFI_SendWarning_Temp[6] = AmbientUTCWarning; + WIFI_SendWarning_Temp[7] = AmbientUTDWarning; + WIFI_SendWarning_Temp[8] = MosOTCWarning; + WIFI_SendWarning_Temp[9] = MosOTDWarning; + WIFI_SendWarning_Temp[10] = MosUTCWarning; + WIFI_SendWarning_Temp[11] = MosUTDWarning; + } + else + { + WIFI_SendFlag &= ~BIT2; + } + } + } +} + +//该函数用于发送报文，0.1s执行1次 +void WIFI_IQ_Transmit(void) +{ +// WIFI_Rx_BufIndex = 0; +// memset(WIFI_Rx_Buf, 0, WIFI_RX_BUF_LEN); //填入前先清空 +// memset(WIFI_Tx_Buf, 0, WIFI_TX_BUF_LEN); + + if(WIFI_01_RxFlg == 1) //WIFI请求采集数据 + { + if(WIFI_01_TxStep == 1) + { + //上报内容 %u:unsigned int %d:int %s:char + //第一帧 + //开头 + WIFI_Send("{"); + WIFI_Send("\"dataType\":\"0x01\","); + WIFI_Send("\"data\":"); + //内容 + WIFI_Send("{"); + WIFI_Send("\"BmsSN\":\"%s\",", BMS_SN); + WIFI_Send("\"PackSN\":\"%s\",", PACK_SN); + WIFI_Send("\"FirmwareVersion\":\"%s\",", FirmwareVersion); + WIFI_Send("\"HardwareVersion\":\"%s\",", HardwareVersion); + if(ScreenVersion[0] != 0) + { + WIFI_Send("\"ScreenVersion\":\"%s\",", ScreenVersion); + } + WIFI_Send("\"FCC\":%u,", bmsMem.ncc/3600); + WIFI_Send("\"RCC\":%u,", bmsMem.rcc/3600); + WIFI_Send("\"SOC\":%u,", bmsMem.soc); + WIFI_Send("\"SOH\":%u,", bmsMem.soh); + WIFI_Send("\"CYC\":%u,", bmsMem.cycleCount); + WIFI_Send("\"ChargeStatus\":%s,", WIFI_ChargeStatus_str); + WIFI_Send("\"DischargeStatus\":%s,", WIFI_DischargeStatus_str); + WIFI_Send("\"PreChargeStatus\":%s,", WIFI_PreChargeStatus_str); + WIFI_Send("\"ChgMosStatus\":%s,", WIFI_ChgMosStatus_str); + WIFI_Send("\"DsgMosStatus\":%s,", WIFI_DsgMosStatus_str); + WIFI_Send("\"PchgMosStatus\":%s,", WIFI_PchgMosStatus_str); + WIFI_Send("\"ChgLimitStatus\":%s,", WIFI_ChgLimitStatus_str); + WIFI_Send("\"BalanceStatus\":%s}", WIFI_BalanceStatus_str); + //结尾 + WIFI_Send("}"); + } + else if(WIFI_01_TxStep == 2) + { + //上报内容 %u:unsigned int %d:int %s:char + //第一帧 + //开头 + WIFI_Send("{"); + WIFI_Send("\"dataType\":\"0x01\","); + WIFI_Send("\"data\":"); + //内容 + WIFI_Send("{"); + WIFI_Send("\"CellVol1\":%d,", cellVol[0]); + WIFI_Send("\"CellVol2\":%d,", cellVol[1]); + WIFI_Send("\"CellVol3\":%d,", cellVol[2]); + WIFI_Send("\"CellVol4\":%d,", cellVol[3]); + WIFI_Send("\"CellVol5\":%d,", cellVol[4]); + WIFI_Send("\"CellVol6\":%d,", cellVol[5]); + WIFI_Send("\"CellVol7\":%d,", cellVol[6]); + WIFI_Send("\"CellVol8\":%d,", cellVol[7]); + WIFI_Send("\"CellVol9\":%d,", cellVol[8]); + WIFI_Send("\"CellVol10\":%d,", cellVol[9]); + WIFI_Send("\"CellVol11\":%d,", cellVol[10]); + WIFI_Send("\"CellVol12\":%d,", cellVol[11]); + WIFI_Send("\"CellVol13\":%d,", cellVol[12]); + WIFI_Send("\"CellVol14\":%d,", cellVol[13]); + WIFI_Send("\"CellVol15\":%d,", cellVol[14]); + WIFI_Send("\"CellVol16\":%d,", cellVol[15]); + WIFI_Send("\"CellVol17\":%d,", cellVol[16]); + WIFI_Send("\"CellVol18\":%d,", cellVol[17]); + WIFI_Send("\"CellVol19\":%d,", cellVol[18]); + WIFI_Send("\"CellVol20\":%d,", cellVol[19]); + WIFI_Send("\"PackVol\":%u,", bmsMem.packVoltage); + WIFI_Send("\"PackCur\":%d,", bmsMem.packCurrent); + WIFI_Send("\"VolMax\":%d,", cellVoltageMax); + WIFI_Send("\"VolMin\":%d,", cellVoltageMin); + WIFI_Send("\"VolMaxIndex\":%u,", bmsMem.cellVoltageMaxIndex); + WIFI_Send("\"VolMinIndex\":%u,", bmsMem.cellVoltageMinIndex); + WIFI_Send("\"MosT1\":%.1f,", (float)(bmsMem.afe_T1-2731)/10); + WIFI_Send("\"MosT2\":%.1f,", (float)(bmsMem.afe_T2-2731)/10); + WIFI_Send("\"AmbientT\":%.1f,", (float)(bmsMem.afe_T3-2731)/10); + WIFI_Send("\"BatteryT1\":%.1f,", (float)(bmsMem.mcu_T1-2731)/10); + WIFI_Send("\"BatteryT2\":%.1f,", (float)(bmsMem.mcu_T2-2731)/10); + WIFI_Send("\"BatteryT3\":%.1f,", (float)(bmsMem.mcu_T3-2731)/10); + WIFI_Send("\"BatteryT4\":%.1f}", (float)(bmsMem.mcu_T4-2731)/10); + //结尾 + WIFI_Send("}"); + } + else if((WIFI_01_TxStep == 3) & ((WIFI_SendFlag & BIT0) != 0)) + { + uint8_t firstflag = 0; //当出现过第1个上传状态后置1 + + //上报内容 %u:unsigned int %d:int %s:char + //第三帧 + //开头 + WIFI_Send("{"); + WIFI_Send("\"dataType\":\"0x01\","); + WIFI_Send("\"data\":"); + //内容 + WIFI_Send("{"); + //特殊状态 + if(WIFI_SendStatus[0] != 0) + { + WIFI_Send("\"LockOCC\":true"); + firstflag = 1; + } + if(WIFI_SendStatus[1] != 0) + { + if(firstflag == 1) WIFI_Send(","); + WIFI_Send("\"LockOCD1\":true"); + firstflag = 1; + } + if(WIFI_SendStatus[2] != 0) + { + if(firstflag == 1) WIFI_Send(","); + WIFI_Send("\"LockOCD2\":true"); + firstflag = 1; + } + if(WIFI_SendStatus[3] != 0) + { + if(firstflag == 1) WIFI_Send(","); + WIFI_Send("\"LockSP\":true"); + firstflag = 1; + } + if(WIFI_SendStatus[4] != 0) + { + if(firstflag == 1) WIFI_Send(","); + WIFI_Send("\"LockSC\":true"); + firstflag = 1; + } + if(WIFI_SendStatus[5] != 0) + { + if(firstflag == 1) WIFI_Send(","); + WIFI_Send("\"ChgMosFault\":true"); + firstflag = 1; + } + if(WIFI_SendStatus[6] != 0) + { + if(firstflag == 1) WIFI_Send(","); + WIFI_Send("\"DsgMosFault\":true"); + firstflag = 1; + } + if(WIFI_SendStatus[7] != 0) + { + if(firstflag == 1) WIFI_Send(","); + WIFI_Send("\"DOStatus\":true"); + firstflag = 1; + } + if(WIFI_SendStatus[8] != 0) + { + if(firstflag == 1) WIFI_Send(","); + WIFI_Send("\"ForceOffUV\":true"); + firstflag = 1; + } + WIFI_Send("}"); + //结尾 + WIFI_Send("}"); + } + else if((WIFI_01_TxStep == 4) & ((WIFI_SendFlag & BIT1) != 0)) + { + uint8_t firstflag = 0; //当出现过第1个上传状态后置1 + + //上报内容 %u:unsigned int %d:int %s:char + //第三帧 + //开头 + WIFI_Send("{"); + WIFI_Send("\"dataType\":\"0x01\","); + WIFI_Send("\"data\":"); + //内容 + WIFI_Send("{"); + //电压保护 + if(WIFI_SendProtect_Vol[0] != 0) + { + WIFI_Send("\"PackOV\":true"); + firstflag = 1; + } + if(WIFI_SendProtect_Vol[1] != 0) + { + if(firstflag == 1) WIFI_Send(","); + WIFI_Send("\"PackUV\":true"); + firstflag = 1; + } + if(WIFI_SendProtect_Vol[2] != 0) + { + if(firstflag == 1) WIFI_Send(","); + WIFI_Send("\"CellOV\":true"); + firstflag = 1; + } + if(WIFI_SendProtect_Vol[3] != 0) + { + if(firstflag == 1) WIFI_Send(","); + WIFI_Send("\"CellUV\":true"); + firstflag = 1; + } + if(WIFI_SendProtect_Vol[4] != 0) + { + if(firstflag == 1) WIFI_Send(","); + WIFI_Send("\"PF\":true"); + firstflag = 1; + } + if(WIFI_SendProtect_Vol[5] != 0) + { + if(firstflag == 1) WIFI_Send(","); + WIFI_Send("\"L0V\":true"); + firstflag = 1; + } + //电流保护 + if(WIFI_SendProtect_Cur[0] != 0) + { + if(firstflag == 1) WIFI_Send(","); + WIFI_Send("\"OCC\":true"); + firstflag = 1; + } + if(WIFI_SendProtect_Cur[1] != 0) + { + if(firstflag == 1) WIFI_Send(","); + WIFI_Send("\"OCD1\":true"); + firstflag = 1; + } + if(WIFI_SendProtect_Cur[2] != 0) + { + if(firstflag == 1) WIFI_Send(","); + WIFI_Send("\"OCD2\":true"); + firstflag = 1; + } + if(WIFI_SendProtect_Cur[3] != 0) + { + if(firstflag == 1) WIFI_Send(","); + WIFI_Send("\"SP\":true"); + firstflag = 1; + } + if(WIFI_SendProtect_Cur[4] != 0) + { + if(firstflag == 1) WIFI_Send(","); + WIFI_Send("\"SC\":true"); + firstflag = 1; + } + //温度保护 + if(WIFI_SendProtect_Temp[0] != 0) + { + if(firstflag == 1) WIFI_Send(","); + WIFI_Send("\"McuOTC\":true"); + firstflag = 1; + } + if(WIFI_SendProtect_Temp[1] != 0) + { + if(firstflag == 1) WIFI_Send(","); + WIFI_Send("\"McuOTD\":true"); + firstflag = 1; + } + if(WIFI_SendProtect_Temp[2] != 0) + { + if(firstflag == 1) WIFI_Send(","); + WIFI_Send("\"McuUTC\":true"); + firstflag = 1; + } + if(WIFI_SendProtect_Temp[3] != 0) + { + if(firstflag == 1) WIFI_Send(","); + WIFI_Send("\"McuUTD\":true"); + firstflag = 1; + } + if(WIFI_SendProtect_Temp[4] != 0) + { + if(firstflag == 1) WIFI_Send(","); + WIFI_Send("\"AmbientOTC\":true"); + firstflag = 1; + } + if(WIFI_SendProtect_Temp[5] != 0) + { + if(firstflag == 1) WIFI_Send(","); + WIFI_Send("\"AmbientOTD\":true"); + firstflag = 1; + } + if(WIFI_SendProtect_Temp[6] != 0) + { + if(firstflag == 1) WIFI_Send(","); + WIFI_Send("\"AmbientUTC\":true"); + firstflag = 1; + } + if(WIFI_SendProtect_Temp[7] != 0) + { + if(firstflag == 1) WIFI_Send(","); + WIFI_Send("\"AmbientUTD\":true"); + firstflag = 1; + } + if(WIFI_SendProtect_Temp[8] != 0) + { + if(firstflag == 1) WIFI_Send(","); + WIFI_Send("\"MosOTC\":true"); + firstflag = 1; + } + if(WIFI_SendProtect_Temp[9] != 0) + { + if(firstflag == 1) WIFI_Send(","); + WIFI_Send("\"MosOTD\":true"); + firstflag = 1; + } +// if(WIFI_SendProtect_Temp[10] != 0) +// { +// if(firstflag == 1) WIFI_Send(","); +// WIFI_Send("\"MosUTC\":true"); +// firstflag = 1; +// } +// if(WIFI_SendProtect_Temp[11] != 0) +// { +// if(firstflag == 1) WIFI_Send(","); +// WIFI_Send("\"MosUTD\":true"); +// firstflag = 1; +// } + WIFI_Send("}"); + //结尾 + WIFI_Send("}"); + } + else if((WIFI_01_TxStep == 5) & ((WIFI_SendFlag & BIT2) != 0)) + { + uint8_t firstflag = 0; //当出现过第1个上传状态后置1 + + //上报内容 %u:unsigned int %d:int %s:char + //第三帧 + //开头 + WIFI_Send("{"); + WIFI_Send("\"dataType\":\"0x01\","); + WIFI_Send("\"data\":"); + //内容 + WIFI_Send("{"); + //电压报警 + if(WIFI_SendWarning_Vol[0] != 0) + { + WIFI_Send("\"PackOVWarning\":true"); + firstflag = 1; + } + if(WIFI_SendWarning_Vol[1] != 0) + { + if(firstflag == 1) WIFI_Send(","); + WIFI_Send("\"PackUVWarning\":true"); + firstflag = 1; + } + if(WIFI_SendWarning_Vol[2] != 0) + { + if(firstflag == 1) WIFI_Send(","); + WIFI_Send("\"CellOVWarning\":true"); + firstflag = 1; + } + if(WIFI_SendWarning_Vol[3] != 0) + { + if(firstflag == 1) WIFI_Send(","); + WIFI_Send("\"CellUVWarning\":true"); + firstflag = 1; + } + //电流报警 + if(WIFI_SendWarning_Cur[0] != 0) + { + if(firstflag == 1) WIFI_Send(","); + WIFI_Send("\"OCCWarning\":true"); + firstflag = 1; + } + if(WIFI_SendWarning_Cur[1] != 0) + { + if(firstflag == 1) WIFI_Send(","); + WIFI_Send("\"OCDWarning\":true"); + firstflag = 1; + } + //温度报警 + if(WIFI_SendWarning_Temp[0] != 0) + { + if(firstflag == 1) WIFI_Send(","); + WIFI_Send("\"McuOTCWarning\":true"); + firstflag = 1; + } + if(WIFI_SendWarning_Temp[1] != 0) + { + if(firstflag == 1) WIFI_Send(","); + WIFI_Send("\"McuOTDWarning\":true"); + firstflag = 1; + } + if(WIFI_SendWarning_Temp[2] != 0) + { + if(firstflag == 1) WIFI_Send(","); + WIFI_Send("\"McuUTCWarning\":true"); + firstflag = 1; + } + if(WIFI_SendWarning_Temp[3] != 0) + { + if(firstflag == 1) WIFI_Send(","); + WIFI_Send("\"McuUTDWarning\":true"); + firstflag = 1; + } + if(WIFI_SendWarning_Temp[4] != 0) + { + if(firstflag == 1) WIFI_Send(","); + WIFI_Send("\"AmbientOTCWarning\":true"); + firstflag = 1; + } + if(WIFI_SendWarning_Temp[5] != 0) + { + if(firstflag == 1) WIFI_Send(","); + WIFI_Send("\"AmbientOTDWarning\":true"); + firstflag = 1; + } + if(WIFI_SendWarning_Temp[6] != 0) + { + if(firstflag == 1) WIFI_Send(","); + WIFI_Send("\"AmbientUTCWarning\":true"); + firstflag = 1; + } + if(WIFI_SendWarning_Temp[7] != 0) + { + if(firstflag == 1) WIFI_Send(","); + WIFI_Send("\"AmbientUTDWarning\":true"); + firstflag = 1; + } + if(WIFI_SendWarning_Temp[8] != 0) + { + if(firstflag == 1) WIFI_Send(","); + WIFI_Send("\"MosOTCWarning\":true"); + firstflag = 1; + } + if(WIFI_SendWarning_Temp[9] != 0) + { + if(firstflag == 1) WIFI_Send(","); + WIFI_Send("\"MosOTDWarning\":true"); + firstflag = 1; + } +// if(WIFI_SendWarning_Temp[10] != 0) +// { +// if(firstflag == 1) WIFI_Send(","); +// WIFI_Send("\"MosUTCWarning\":true"); +// firstflag = 1; +// } +// if(WIFI_SendWarning_Temp[11] != 0) +// { +// if(firstflag == 1) WIFI_Send(","); +// WIFI_Send("\"MosUTDWarning\":true"); +// firstflag = 1; +// } + WIFI_Send("}"); + //结尾 + WIFI_Send("}"); + } + //每0.1s发送一帧 + else if(WIFI_01_TxStep >= 10) + { + WIFI_01_RxFlg = 0; + WIFI_01_TxStep = 0; + } + } + else if(WIFI_04_RxFlg == 1) //回复写数据操作 + { + WIFI_04_RxFlg = 0; //回复后恢复正常状态 + + //上报内容 %u:unsigned int %d:int %s:char + //开头 + WIFI_Send("{"); + WIFI_Send("\"dataType\":\"0x04\","); + //内容 + if(setPara_reply_flg == 1) //正确 + { + uint8_t i; + uint8_t firstflag = 0; //当出现过第1个上传状态后置1 + + WIFI_Send("\"code\":0,"); + WIFI_Send("\"set_num\":%hu,", setPara_reply_num); + WIFI_Send("\"data\":"); + + WIFI_Send("{"); + for(i=0;i + +
+
礦ision Build Log

+
Tool Versions:

+IDE-Version: μVision V5.25.0.0
+Copyright (C) 2017 ARM Ltd and ARM Germany GmbH. All rights reserved.
+License Information: 4 3, 2, LIC=ZB4EI-T663M-30XNC-7JX79-N00Q7-1ZNRI
+ 
+Tool Versions:
+Toolchain:       MDK-ARM Plus  Version: 5.25.0.0
+Toolchain Path:  E:\keil_v5_old\ARM\ARMCC\Bin
+C Compiler:      Armcc.exe V5.06 update 6 (build 750)
+Assembler:       Armasm.exe V5.06 update 6 (build 750)
+Linker/Locator:  ArmLink.exe V5.06 update 6 (build 750)
+Library Manager: ArmAr.exe V5.06 update 6 (build 750)
+Hex Converter:   FromElf.exe V5.06 update 6 (build 750)
+CPU DLL:         SARMCM3.DLL V5.25.0.0
+Dialog DLL:      DCM.DLL V1.17.0.0
+Target DLL:      Segger\JL2CM3.dll V2.99.28.0
+Dialog DLL:      TCM.DLL V1.34.0.0
+ 
+
Project:

+C:\Users\yue\Desktop\20串200A项目\3、测试代码\BMS_STM32_[V4.0.0.0](串数写入优化)(充放电高温看状态)(屏幕遮挡历史优化)(屏幕剩余时间优化)(200A参数)+[20020SF]+[V1.0.0]\USER\BT_BMS_V3.0.uvprojx
+Project File Date:  08/25/2026
+
+
Output:

+*** Using Compiler 'V5.06 update 6 (build 750)', folder: 'E:\keil_v5_old\ARM\ARMCC\Bin'
+Build target 'Target 1'
+compiling flash.c...
+linking...
+Program Size: Code=89934 RO-data=6498 RW-data=1596 ZI-data=7548  
+"..\OBJ\BT_BMS_V3.0" - 0 Error(s), 0 Warning(s).
+
+
Software Packages used:

+
+Package Vendor: Keil
+                http://www.keil.com/pack/Keil.STM32F1xx_DFP.2.3.0.pack
+                Keil.STM32F1xx_DFP.2.3.0
+                STMicroelectronics STM32F1 Series Device Support, Drivers and Examples
+
+
Collection of Component include folders:

+  .\RTE\_Target_1
+  E:\keil_v5_old\ARM\PACK\Keil\STM32F1xx_DFP\2.3.0\Device\Include
+
+
Collection of Component Files used:

+Build Time Elapsed:  00:00:06
+
+ + diff --git a/OBJ/BT_BMS_V3.htm b/OBJ/BT_BMS_V3.htm new file mode 100644 index 0000000..ef5720c --- /dev/null +++ b/OBJ/BT_BMS_V3.htm @@ -0,0 +1,4883 @@ + + +Static Call Graph - [..\OBJ\BT_BMS_V3.0] +
+

Static Call Graph for image ..\OBJ\BT_BMS_V3.0

+

#<CALLGRAPH># ARM Linker, 5060750: Last Updated: Tue Aug 25 14:38:26 2026 +

+

Maximum Stack Usage = 576 bytes + Unknown(Functions without stacksize, Cycles, Untraceable Function Pointers)

+Call chain for Maximum Stack Depth:

+__rt_entry_main ⇒ main ⇒ MODBUS_IQ_Transmit ⇒ MEMORY_UpdateFlash ⇒ FLASH_WrData ⇒ FLASH_ProgramHalfWord ⇒ FLASH_WaitForLastOperation +

+

+Functions with no stack information +

+ +

+

+Mutually Recursive functions +

  • ADC1_2_IRQHandler   ⇒   ADC1_2_IRQHandler
    +
  • BusFault_Handler   ⇒   BusFault_Handler
    +
  • MemManage_Handler   ⇒   MemManage_Handler
    +
  • UsageFault_Handler   ⇒   UsageFault_Handler
    + +

    +

    +Function Pointers +

      +
    • ADC1_2_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • ADC3_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • BusFault_Handler from stm32f10x_it.o(i.BusFault_Handler) referenced from startup_stm32f10x_hd.o(RESET) +
    • CAN1_RX1_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • CAN1_SCE_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • DMA1_Channel1_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • DMA1_Channel2_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • DMA1_Channel3_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • DMA1_Channel4_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • DMA1_Channel5_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • DMA1_Channel6_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • DMA1_Channel7_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • DMA2_Channel1_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • DMA2_Channel2_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • DMA2_Channel3_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • DMA2_Channel4_5_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • DebugMon_Handler from stm32f10x_it.o(i.DebugMon_Handler) referenced from startup_stm32f10x_hd.o(RESET) +
    • EXTI0_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • EXTI15_10_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • EXTI1_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • EXTI2_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • EXTI3_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • EXTI4_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • EXTI9_5_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • FLASH_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • FSMC_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • HardFault_Handler from stm32f10x_it.o(i.HardFault_Handler) referenced from startup_stm32f10x_hd.o(RESET) +
    • I2C1_ER_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • I2C1_EV_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • I2C2_ER_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • I2C2_EV_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • MemManage_Handler from stm32f10x_it.o(i.MemManage_Handler) referenced from startup_stm32f10x_hd.o(RESET) +
    • NMI_Handler from stm32f10x_it.o(i.NMI_Handler) referenced from startup_stm32f10x_hd.o(RESET) +
    • PVD_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • PendSV_Handler from stm32f10x_it.o(i.PendSV_Handler) referenced from startup_stm32f10x_hd.o(RESET) +
    • RCC_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • RTCAlarm_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • RTC_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • Reset_Handler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • SDIO_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • SPI1_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • SPI2_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • SPI3_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • SVC_Handler from stm32f10x_it.o(i.SVC_Handler) referenced from startup_stm32f10x_hd.o(RESET) +
    • SysTick_Handler from stm32f10x_it.o(i.SysTick_Handler) referenced from startup_stm32f10x_hd.o(RESET) +
    • SystemInit from system_stm32f10x.o(i.SystemInit) referenced from startup_stm32f10x_hd.o(.text) +
    • TAMPER_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • TIM1_BRK_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • TIM1_CC_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • TIM1_TRG_COM_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • TIM1_UP_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • TIM2_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • TIM3_IRQHandler from tim.o(i.TIM3_IRQHandler) referenced from startup_stm32f10x_hd.o(RESET) +
    • TIM4_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • TIM5_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • TIM6_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • TIM7_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • TIM8_BRK_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • TIM8_CC_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • TIM8_TRG_COM_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • TIM8_UP_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • UART4_IRQHandler from uart.o(i.UART4_IRQHandler) referenced from startup_stm32f10x_hd.o(RESET) +
    • UART5_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • USART1_IRQHandler from uart.o(i.USART1_IRQHandler) referenced from startup_stm32f10x_hd.o(RESET) +
    • USART2_IRQHandler from uart.o(i.USART2_IRQHandler) referenced from startup_stm32f10x_hd.o(RESET) +
    • USART3_IRQHandler from uart.o(i.USART3_IRQHandler) referenced from startup_stm32f10x_hd.o(RESET) +
    • USBWakeUp_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • USB_HP_CAN1_TX_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • USB_LP_CAN1_RX0_IRQHandler from can.o(i.USB_LP_CAN1_RX0_IRQHandler) referenced from startup_stm32f10x_hd.o(RESET) +
    • UsageFault_Handler from stm32f10x_it.o(i.UsageFault_Handler) referenced from startup_stm32f10x_hd.o(RESET) +
    • WWDG_IRQHandler from startup_stm32f10x_hd.o(.text) referenced from startup_stm32f10x_hd.o(RESET) +
    • __main from __main.o(!!!main) referenced from startup_stm32f10x_hd.o(.text) +
    • _get_lc_ctype from lc_ctype_c.o(locale$$code) referenced from rt_ctype_table.o(.text) +
    • _printf_input_char from _printf_char_common.o(.text) referenced from _printf_char_common.o(.text) +
    • _sbackspace from _sgetc.o(.text) referenced from __0sscanf.o(.text) +
    • _scanf_char_input from scanf_char.o(.text) referenced from scanf_char.o(.text) +
    • _sgetc from _sgetc.o(.text) referenced from __0sscanf.o(.text) +
    • _snputc from _snputc.o(.text) referenced from vsnprintf.o(.text) +
    • _sputc from _sputc.o(.text) referenced from __2sprintf.o(.text) +
    • isspace from isspace.o(.text) referenced from scanf_char.o(.text) +
    +

    +

    +Global Symbols +

    +

    __main (Thumb, 8 bytes, Stack size 0 bytes, __main.o(!!!main)) +

    [Calls]

    • >>   __rt_entry +
    • >>   __scatterload +
    + +

    __scatterload (Thumb, 0 bytes, Stack size unknown bytes, __scatter.o(!!!scatter)) +

    [Called By]

    • >>   __main +
    + +

    __scatterload_rt2 (Thumb, 44 bytes, Stack size unknown bytes, __scatter.o(!!!scatter), UNUSED) +

    [Calls]

    • >>   __rt_entry +
    + +

    __scatterload_rt2_thumb_only (Thumb, 0 bytes, Stack size unknown bytes, __scatter.o(!!!scatter), UNUSED) + +

    __scatterload_null (Thumb, 0 bytes, Stack size unknown bytes, __scatter.o(!!!scatter), UNUSED) + +

    __decompress (Thumb, 90 bytes, Stack size unknown bytes, __dczerorl2.o(!!dczerorl2), UNUSED) + +

    __decompress1 (Thumb, 0 bytes, Stack size unknown bytes, __dczerorl2.o(!!dczerorl2), UNUSED) + +

    __scatterload_zeroinit (Thumb, 28 bytes, Stack size unknown bytes, __scatter_zi.o(!!handler_zi), UNUSED) + +

    _printf_n (Thumb, 0 bytes, Stack size unknown bytes, _printf_n.o(.ARM.Collect$$_printf_percent$$00000001)) +

    [Calls]

    • >>   _printf_charcount +
    + +

    _printf_percent (Thumb, 0 bytes, Stack size unknown bytes, _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000)) +

    [Called By]

    • >>   __printf +
    + +

    _printf_p (Thumb, 0 bytes, Stack size unknown bytes, _printf_p.o(.ARM.Collect$$_printf_percent$$00000002)) +

    [Stack]

    • Max Depth = 64 + Unknown Stack Size +
    • Call Chain = _printf_p ⇒ _printf_hex_ptr ⇒ _printf_longlong_hex ⇒ _printf_int_common ⇒ _printf_post_padding +
    +
    [Calls]
    • >>   _printf_hex_ptr +
    + +

    _printf_f (Thumb, 0 bytes, Stack size unknown bytes, _printf_f.o(.ARM.Collect$$_printf_percent$$00000003)) +

    [Stack]

    • Max Depth = 324 + Unknown Stack Size +
    • Call Chain = _printf_f ⇒ _printf_fp_dec ⇒ _printf_fp_dec_real ⇒ _fp_digits ⇒ _btod_etento ⇒ _btod_emul ⇒ _e2e +
    +
    [Calls]
    • >>   _printf_fp_dec +
    + +

    _printf_e (Thumb, 0 bytes, Stack size unknown bytes, _printf_e.o(.ARM.Collect$$_printf_percent$$00000004)) +

    [Stack]

    • Max Depth = 324 + Unknown Stack Size +
    • Call Chain = _printf_e ⇒ _printf_fp_dec ⇒ _printf_fp_dec_real ⇒ _fp_digits ⇒ _btod_etento ⇒ _btod_emul ⇒ _e2e +
    +
    [Calls]
    • >>   _printf_fp_dec +
    + +

    _printf_g (Thumb, 0 bytes, Stack size unknown bytes, _printf_g.o(.ARM.Collect$$_printf_percent$$00000005)) +

    [Stack]

    • Max Depth = 324 + Unknown Stack Size +
    • Call Chain = _printf_g ⇒ _printf_fp_dec ⇒ _printf_fp_dec_real ⇒ _fp_digits ⇒ _btod_etento ⇒ _btod_emul ⇒ _e2e +
    +
    [Calls]
    • >>   _printf_fp_dec +
    + +

    _printf_a (Thumb, 0 bytes, Stack size unknown bytes, _printf_a.o(.ARM.Collect$$_printf_percent$$00000006)) +

    [Stack]

    • Max Depth = 112 + Unknown Stack Size +
    • Call Chain = _printf_a ⇒ _printf_fp_hex ⇒ _printf_fp_hex_real ⇒ _printf_fp_infnan ⇒ _printf_post_padding +
    +
    [Calls]
    • >>   _printf_fp_hex +
    + +

    _printf_ll (Thumb, 0 bytes, Stack size unknown bytes, _printf_ll.o(.ARM.Collect$$_printf_percent$$00000007)) + +

    _printf_i (Thumb, 0 bytes, Stack size unknown bytes, _printf_i.o(.ARM.Collect$$_printf_percent$$00000008)) +

    [Stack]

    • Max Depth = 72 + Unknown Stack Size +
    • Call Chain = _printf_i ⇒ _printf_int_dec ⇒ _printf_int_common ⇒ _printf_post_padding +
    +
    [Calls]
    • >>   _printf_int_dec +
    + +

    _printf_d (Thumb, 0 bytes, Stack size unknown bytes, _printf_d.o(.ARM.Collect$$_printf_percent$$00000009)) +

    [Stack]

    • Max Depth = 72 + Unknown Stack Size +
    • Call Chain = _printf_d ⇒ _printf_int_dec ⇒ _printf_int_common ⇒ _printf_post_padding +
    +
    [Calls]
    • >>   _printf_int_dec +
    + +

    _printf_u (Thumb, 0 bytes, Stack size unknown bytes, _printf_u.o(.ARM.Collect$$_printf_percent$$0000000A)) +

    [Stack]

    • Max Depth = 72 + Unknown Stack Size +
    • Call Chain = _printf_u ⇒ _printf_int_dec ⇒ _printf_int_common ⇒ _printf_post_padding +
    +
    [Calls]
    • >>   _printf_int_dec +
    + +

    _printf_o (Thumb, 0 bytes, Stack size unknown bytes, _printf_o.o(.ARM.Collect$$_printf_percent$$0000000B)) +

    [Stack]

    • Max Depth = 64 + Unknown Stack Size +
    • Call Chain = _printf_o ⇒ _printf_int_oct ⇒ _printf_longlong_oct ⇒ _printf_int_common ⇒ _printf_post_padding +
    +
    [Calls]
    • >>   _printf_int_oct +
    + +

    _printf_x (Thumb, 0 bytes, Stack size unknown bytes, _printf_x.o(.ARM.Collect$$_printf_percent$$0000000C)) +

    [Stack]

    • Max Depth = 80 + Unknown Stack Size +
    • Call Chain = _printf_x ⇒ _printf_int_hex ⇒ _printf_longlong_hex ⇒ _printf_int_common ⇒ _printf_post_padding +
    +
    [Calls]
    • >>   _printf_int_hex +
    + +

    _printf_lli (Thumb, 0 bytes, Stack size unknown bytes, _printf_lli.o(.ARM.Collect$$_printf_percent$$0000000D)) +

    [Stack]

    • Max Depth = 72 + Unknown Stack Size +
    • Call Chain = _printf_lli ⇒ _printf_longlong_dec ⇒ _printf_int_common ⇒ _printf_post_padding +
    +
    [Calls]
    • >>   _printf_longlong_dec +
    + +

    _printf_lld (Thumb, 0 bytes, Stack size unknown bytes, _printf_lld.o(.ARM.Collect$$_printf_percent$$0000000E)) +

    [Stack]

    • Max Depth = 72 + Unknown Stack Size +
    • Call Chain = _printf_lld ⇒ _printf_longlong_dec ⇒ _printf_int_common ⇒ _printf_post_padding +
    +
    [Calls]
    • >>   _printf_longlong_dec +
    + +

    _printf_llu (Thumb, 0 bytes, Stack size unknown bytes, _printf_llu.o(.ARM.Collect$$_printf_percent$$0000000F)) +

    [Stack]

    • Max Depth = 72 + Unknown Stack Size +
    • Call Chain = _printf_llu ⇒ _printf_longlong_dec ⇒ _printf_int_common ⇒ _printf_post_padding +
    +
    [Calls]
    • >>   _printf_longlong_dec +
    + +

    _printf_llo (Thumb, 0 bytes, Stack size unknown bytes, _printf_llo.o(.ARM.Collect$$_printf_percent$$00000010)) +

    [Stack]

    • Max Depth = 56 + Unknown Stack Size +
    • Call Chain = _printf_llo ⇒ _printf_ll_oct ⇒ _printf_longlong_oct ⇒ _printf_int_common ⇒ _printf_post_padding +
    +
    [Calls]
    • >>   _printf_ll_oct +
    + +

    _printf_llx (Thumb, 0 bytes, Stack size unknown bytes, _printf_llx.o(.ARM.Collect$$_printf_percent$$00000011)) +

    [Stack]

    • Max Depth = 64 + Unknown Stack Size +
    • Call Chain = _printf_llx ⇒ _printf_ll_hex ⇒ _printf_longlong_hex ⇒ _printf_int_common ⇒ _printf_post_padding +
    +
    [Calls]
    • >>   _printf_ll_hex +
    + +

    _printf_l (Thumb, 0 bytes, Stack size unknown bytes, _printf_l.o(.ARM.Collect$$_printf_percent$$00000012)) + +

    _printf_c (Thumb, 0 bytes, Stack size unknown bytes, _printf_c.o(.ARM.Collect$$_printf_percent$$00000013)) +

    [Stack]

    • Max Depth = 40 + Unknown Stack Size +
    • Call Chain = _printf_c ⇒ _printf_char ⇒ _printf_cs_common ⇒ _printf_str ⇒ _printf_post_padding +
    +
    [Calls]
    • >>   _printf_char +
    + +

    _printf_s (Thumb, 0 bytes, Stack size unknown bytes, _printf_s.o(.ARM.Collect$$_printf_percent$$00000014)) +

    [Stack]

    • Max Depth = 40 + Unknown Stack Size +
    • Call Chain = _printf_s ⇒ _printf_string ⇒ _printf_cs_common ⇒ _printf_str ⇒ _printf_post_padding +
    +
    [Calls]
    • >>   _printf_string +
    + +

    _printf_lc (Thumb, 0 bytes, Stack size unknown bytes, _printf_lc.o(.ARM.Collect$$_printf_percent$$00000015)) +

    [Stack]

    • Max Depth = 88 + Unknown Stack Size +
    • Call Chain = _printf_lc ⇒ _printf_wchar ⇒ _printf_lcs_common ⇒ _printf_wctomb ⇒ _wcrtomb ⇒ __rt_ctype_table +
    +
    [Calls]
    • >>   _printf_wchar +
    + +

    _printf_ls (Thumb, 0 bytes, Stack size unknown bytes, _printf_ls.o(.ARM.Collect$$_printf_percent$$00000016)) +

    [Stack]

    • Max Depth = 88 + Unknown Stack Size +
    • Call Chain = _printf_ls ⇒ _printf_wstring ⇒ _printf_lcs_common ⇒ _printf_wctomb ⇒ _wcrtomb ⇒ __rt_ctype_table +
    +
    [Calls]
    • >>   _printf_wstring +
    + +

    _printf_percent_end (Thumb, 0 bytes, Stack size unknown bytes, _printf_percent_end.o(.ARM.Collect$$_printf_percent$$00000017)) + +

    __rt_lib_init (Thumb, 0 bytes, Stack size unknown bytes, libinit.o(.ARM.Collect$$libinit$$00000000)) +

    [Called By]

    • >>   __rt_entry_li +
    + +

    __rt_lib_init_fp_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000002)) + +

    __rt_lib_init_heap_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000A)) + +

    __rt_lib_init_lc_common (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000F)) +

    [Calls]

    • >>   __rt_locale +
    + +

    __rt_lib_init_preinit_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000004)) + +

    __rt_lib_init_rand_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000E)) + +

    __rt_lib_init_user_alloc_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000C)) + +

    __rt_lib_init_lc_collate_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000011)) + +

    __rt_lib_init_lc_ctype_2 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000012)) +

    [Stack]

    • Max Depth = 8 + Unknown Stack Size +
    • Call Chain = __rt_lib_init_lc_ctype_2 ⇒ _get_lc_ctype +
    +
    [Calls]
    • >>   _get_lc_ctype +
    + +

    __rt_lib_init_lc_ctype_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000013)) + +

    __rt_lib_init_lc_monetary_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000015)) + +

    __rt_lib_init_lc_numeric_2 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000016)) +

    [Stack]

    • Max Depth = 8 + Unknown Stack Size +
    • Call Chain = __rt_lib_init_lc_numeric_2 ⇒ _get_lc_numeric +
    +
    [Calls]
    • >>   _get_lc_numeric +
    + +

    __rt_lib_init_alloca_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000002E)) + +

    __rt_lib_init_argv_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000002C)) + +

    __rt_lib_init_atexit_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001B)) + +

    __rt_lib_init_clock_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000021)) + +

    __rt_lib_init_cpp_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000032)) + +

    __rt_lib_init_exceptions_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000030)) + +

    __rt_lib_init_fp_trap_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001F)) + +

    __rt_lib_init_getenv_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000023)) + +

    __rt_lib_init_lc_numeric_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000017)) + +

    __rt_lib_init_lc_time_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000019)) + +

    __rt_lib_init_return (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000033)) + +

    __rt_lib_init_signal_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001D)) + +

    __rt_lib_init_stdio_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000025)) + +

    __rt_lib_shutdown (Thumb, 0 bytes, Stack size unknown bytes, libshutdown.o(.ARM.Collect$$libshutdown$$00000000)) +

    [Called By]

    • >>   __rt_exit_ls +
    + +

    __rt_lib_shutdown_cpp_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000002)) + +

    __rt_lib_shutdown_fp_trap_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000007)) + +

    __rt_lib_shutdown_heap_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F)) + +

    __rt_lib_shutdown_return (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000010)) + +

    __rt_lib_shutdown_signal_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$0000000A)) + +

    __rt_lib_shutdown_stdio_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000004)) + +

    __rt_lib_shutdown_user_alloc_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C)) + +

    __rt_entry (Thumb, 0 bytes, Stack size unknown bytes, __rtentry.o(.ARM.Collect$$rtentry$$00000000)) +

    [Called By]

    • >>   __main +
    • >>   __scatterload_rt2 +
    + +

    __rt_entry_presh_1 (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$00000002)) + +

    __rt_entry_sh (Thumb, 0 bytes, Stack size unknown bytes, __rtentry4.o(.ARM.Collect$$rtentry$$00000004)) +

    [Stack]

    • Max Depth = 8 + Unknown Stack Size +
    • Call Chain = __rt_entry_sh ⇒ __user_setup_stackheap +
    +
    [Calls]
    • >>   __user_setup_stackheap +
    + +

    __rt_entry_li (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$0000000A)) +

    [Calls]

    • >>   __rt_lib_init +
    + +

    __rt_entry_postsh_1 (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$00000009)) + +

    __rt_entry_main (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$0000000D)) +

    [Stack]

    • Max Depth = 576 + Unknown Stack Size +
    • Call Chain = __rt_entry_main ⇒ main ⇒ MODBUS_IQ_Transmit ⇒ MEMORY_UpdateFlash ⇒ FLASH_WrData ⇒ FLASH_ProgramHalfWord ⇒ FLASH_WaitForLastOperation +
    +
    [Calls]
    • >>   main +
    • >>   exit +
    + +

    __rt_entry_postli_1 (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$0000000C)) + +

    __rt_exit (Thumb, 0 bytes, Stack size unknown bytes, rtexit.o(.ARM.Collect$$rtexit$$00000000)) +

    [Called By]

    • >>   exit +
    + +

    __rt_exit_ls (Thumb, 0 bytes, Stack size unknown bytes, rtexit2.o(.ARM.Collect$$rtexit$$00000003)) +

    [Calls]

    • >>   __rt_lib_shutdown +
    + +

    __rt_exit_prels_1 (Thumb, 0 bytes, Stack size unknown bytes, rtexit2.o(.ARM.Collect$$rtexit$$00000002)) + +

    __rt_exit_exit (Thumb, 0 bytes, Stack size unknown bytes, rtexit2.o(.ARM.Collect$$rtexit$$00000004)) +

    [Calls]

    • >>   _sys_exit +
    + +

    Reset_Handler (Thumb, 8 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    ADC1_2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +

    [Calls]

    • >>   ADC1_2_IRQHandler +
    +
    [Called By]
    • >>   ADC1_2_IRQHandler +
    +
    [Address Reference Count : 1]
    • startup_stm32f10x_hd.o(RESET) +
    +

    ADC3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    CAN1_RX1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    CAN1_SCE_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    DMA1_Channel1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    DMA1_Channel2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    DMA1_Channel3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    DMA1_Channel4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    DMA1_Channel5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    DMA1_Channel6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    DMA1_Channel7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    DMA2_Channel1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    DMA2_Channel2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    DMA2_Channel3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    DMA2_Channel4_5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    EXTI0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    EXTI15_10_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    EXTI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    EXTI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    EXTI3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    EXTI4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    EXTI9_5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    FLASH_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    FSMC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    I2C1_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    I2C1_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    I2C2_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    I2C2_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    PVD_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    RCC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    RTCAlarm_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    RTC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    SDIO_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    SPI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    SPI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    SPI3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    TAMPER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    TIM1_BRK_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    TIM1_CC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    TIM1_TRG_COM_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    TIM1_UP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    TIM2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    TIM4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    TIM5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    TIM6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    TIM7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    TIM8_BRK_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    TIM8_CC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    TIM8_TRG_COM_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    TIM8_UP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    UART5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    USBWakeUp_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    USB_HP_CAN1_TX_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    WWDG_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32f10x_hd.o(.text)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    __user_initial_stackheap (Thumb, 0 bytes, Stack size unknown bytes, startup_stm32f10x_hd.o(.text)) +

    [Called By]

    • >>   __user_setup_stackheap +
    + +

    vsnprintf (Thumb, 48 bytes, Stack size 24 bytes, vsnprintf.o(.text)) +

    [Stack]

    • Max Depth = 128 + Unknown Stack Size +
    • Call Chain = vsnprintf ⇒ _printf_char_common ⇒ __printf +
    +
    [Calls]
    • >>   _sputc +
    • >>   _printf_char_common +
    +
    [Called By]
    • >>   USART2_printf +
    • >>   BLE_printf +
    + +

    __2sprintf (Thumb, 38 bytes, Stack size 32 bytes, __2sprintf.o(.text)) +

    [Stack]

    • Max Depth = 136 + Unknown Stack Size +
    • Call Chain = __2sprintf ⇒ _printf_char_common ⇒ __printf +
    +
    [Calls]
    • >>   _sputc +
    • >>   _printf_char_common +
    +
    [Called By]
    • >>   Refresh_ScreenVersion +
    • >>   Refresh_PACK_SN +
    • >>   Refresh_HardwareVersion +
    • >>   Refresh_FirmwareVersion +
    • >>   Refresh_BMS_SN +
    • >>   Screen_IQ_Transmit +
    • >>   SCR_Send_Time +
    • >>   SCR_Send_RecordInfo +
    + +

    _printf_pre_padding (Thumb, 44 bytes, Stack size 16 bytes, _printf_pad.o(.text)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = _printf_pre_padding +
    +
    [Called By]
    • >>   _printf_fp_infnan +
    • >>   _printf_fp_hex_real +
    • >>   _printf_fp_dec_real +
    • >>   _printf_wctomb +
    • >>   _printf_int_common +
    • >>   _printf_str +
    + +

    _printf_post_padding (Thumb, 34 bytes, Stack size 16 bytes, _printf_pad.o(.text)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = _printf_post_padding +
    +
    [Called By]
    • >>   _printf_fp_infnan +
    • >>   _printf_fp_hex_real +
    • >>   _printf_fp_dec_real +
    • >>   _printf_wctomb +
    • >>   _printf_int_common +
    • >>   _printf_str +
    + +

    _printf_str (Thumb, 82 bytes, Stack size 16 bytes, _printf_str.o(.text)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = _printf_str ⇒ _printf_post_padding +
    +
    [Calls]
    • >>   _printf_post_padding +
    • >>   _printf_pre_padding +
    +
    [Called By]
    • >>   _printf_cs_common +
    + +

    _printf_int_dec (Thumb, 104 bytes, Stack size 24 bytes, _printf_dec.o(.text)) +

    [Stack]

    • Max Depth = 72
    • Call Chain = _printf_int_dec ⇒ _printf_int_common ⇒ _printf_post_padding +
    +
    [Calls]
    • >>   _printf_int_common +
    • >>   _printf_truncate_unsigned +
    • >>   _printf_truncate_signed +
    +
    [Called By]
    • >>   _printf_i +
    • >>   _printf_u +
    • >>   _printf_d +
    + +

    _printf_longlong_hex (Thumb, 86 bytes, Stack size 16 bytes, _printf_hex_int_ll_ptr.o(.text)) +

    [Stack]

    • Max Depth = 64
    • Call Chain = _printf_longlong_hex ⇒ _printf_int_common ⇒ _printf_post_padding +
    +
    [Calls]
    • >>   _printf_int_common +
    +
    [Called By]
    • >>   _printf_hex_ptr +
    • >>   _printf_ll_hex +
    • >>   _printf_int_hex +
    + +

    _printf_int_hex (Thumb, 28 bytes, Stack size 16 bytes, _printf_hex_int_ll_ptr.o(.text)) +

    [Stack]

    • Max Depth = 80
    • Call Chain = _printf_int_hex ⇒ _printf_longlong_hex ⇒ _printf_int_common ⇒ _printf_post_padding +
    +
    [Calls]
    • >>   _printf_truncate_unsigned +
    • >>   _printf_longlong_hex +
    +
    [Called By]
    • >>   _printf_x +
    + +

    _printf_ll_hex (Thumb, 12 bytes, Stack size 0 bytes, _printf_hex_int_ll_ptr.o(.text)) +

    [Stack]

    • Max Depth = 64
    • Call Chain = _printf_ll_hex ⇒ _printf_longlong_hex ⇒ _printf_int_common ⇒ _printf_post_padding +
    +
    [Calls]
    • >>   _printf_longlong_hex +
    +
    [Called By]
    • >>   _printf_llx +
    + +

    _printf_hex_ptr (Thumb, 18 bytes, Stack size 0 bytes, _printf_hex_int_ll_ptr.o(.text)) +

    [Stack]

    • Max Depth = 64
    • Call Chain = _printf_hex_ptr ⇒ _printf_longlong_hex ⇒ _printf_int_common ⇒ _printf_post_padding +
    +
    [Calls]
    • >>   _printf_longlong_hex +
    +
    [Called By]
    • >>   _printf_p +
    + +

    __printf (Thumb, 388 bytes, Stack size 40 bytes, __printf_flags_ss_wp.o(.text)) +

    [Stack]

    • Max Depth = 40 + Unknown Stack Size +
    • Call Chain = __printf +
    +
    [Calls]
    • >>   _printf_percent +
    • >>   _is_digit +
    +
    [Called By]
    • >>   _printf_char_common +
    + +

    __0sscanf (Thumb, 52 bytes, Stack size 72 bytes, __0sscanf.o(.text)) +

    [Stack]

    • Max Depth = 224
    • Call Chain = __0sscanf ⇒ __vfscanf_char ⇒ __vfscanf ⇒ _scanf_int +
    +
    [Calls]
    • >>   __vfscanf_char +
    +
    [Called By]
    • >>   BLE_SETPARA +
    + +

    _scanf_int (Thumb, 332 bytes, Stack size 56 bytes, _scanf_int.o(.text)) +

    [Stack]

    • Max Depth = 56
    • Call Chain = _scanf_int +
    +
    [Calls]
    • >>   _chval +
    +
    [Called By]
    • >>   __vfscanf +
    + +

    strchr (Thumb, 20 bytes, Stack size 0 bytes, strchr.o(.text)) +

    [Called By]

    • >>   GetStr +
    • >>   BLE_SETPARA +
    • >>   BLE_PUTSRVC +
    • >>   BLE_GETPARA +
    + +

    strstr (Thumb, 36 bytes, Stack size 12 bytes, strstr.o(.text)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = strstr +
    +
    [Called By]
    • >>   GetStr +
    • >>   Screen_IT_Update +
    • >>   BLE_IT_Update +
    • >>   BLE_SETPARA +
    • >>   BLE_PUTSRVC +
    • >>   BLE_GETPARA +
    • >>   BLE_CheckName +
    + +

    memcmp (Thumb, 88 bytes, Stack size 8 bytes, memcmp.o(.text)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = memcmp +
    +
    [Called By]
    • >>   findHexStr +
    + +

    strcpy (Thumb, 72 bytes, Stack size 12 bytes, strcpy.o(.text)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = strcpy +
    +
    [Called By]
    • >>   UART3_ProtocolSwitch +
    • >>   UART1_ProtocolSwitch +
    + +

    strlen (Thumb, 62 bytes, Stack size 8 bytes, strlen.o(.text)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = strlen +
    +
    [Called By]
    • >>   GetStr +
    • >>   UART3_ProtocolSwitch +
    • >>   UART1_ProtocolSwitch +
    • >>   BLE_SETPARA +
    • >>   BLE_PUTSRVC +
    • >>   BLE_GETPARA +
    + +

    __aeabi_memcpy (Thumb, 0 bytes, Stack size 0 bytes, rt_memcpy_v6.o(.text)) +

    [Called By]

    • >>   MEMORY_UpdateFlash +
    • >>   FLASH_ReadCheck +
    • >>   SCR_Send_Record +
    • >>   MODBUS1_F10_Rx +
    • >>   MODBUS1_CtrlMOS_Rx +
    • >>   MODBUS_F10_Rx +
    • >>   MODBUS_CtrlMOS_Rx +
    + +

    __rt_memcpy (Thumb, 138 bytes, Stack size 0 bytes, rt_memcpy_v6.o(.text), UNUSED) +

    [Calls]

    • >>   __aeabi_memcpy4 +
    + +

    _memcpy_lastbytes (Thumb, 0 bytes, Stack size unknown bytes, rt_memcpy_v6.o(.text), UNUSED) + +

    __aeabi_memcpy4 (Thumb, 0 bytes, Stack size 8 bytes, rt_memcpy_w.o(.text)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = __aeabi_memcpy4 +
    +
    [Called By]
    • >>   MEMORY_UpdateFlash +
    • >>   FLASH_ReadCheck +
    • >>   __rt_memcpy +
    + +

    __aeabi_memcpy8 (Thumb, 0 bytes, Stack size 8 bytes, rt_memcpy_w.o(.text), UNUSED) + +

    __rt_memcpy_w (Thumb, 100 bytes, Stack size 8 bytes, rt_memcpy_w.o(.text), UNUSED) + +

    _memcpy_lastbytes_aligned (Thumb, 0 bytes, Stack size unknown bytes, rt_memcpy_w.o(.text), UNUSED) + +

    __aeabi_memset (Thumb, 16 bytes, Stack size 0 bytes, aeabi_memset.o(.text)) +

    [Calls]

    • >>   _memset +
    +
    [Called By]
    • >>   Screen_IT_Update +
    + +

    __aeabi_memclr (Thumb, 0 bytes, Stack size 0 bytes, rt_memclr.o(.text)) +

    [Called By]

    • >>   uf_GLOBAL_Init +
    • >>   Screen_ClearBuf +
    • >>   SCR_Send_Record +
    • >>   strncpy +
    + +

    __rt_memclr (Thumb, 68 bytes, Stack size 0 bytes, rt_memclr.o(.text), UNUSED) +

    [Calls]

    • >>   _memset_w +
    + +

    _memset (Thumb, 0 bytes, Stack size unknown bytes, rt_memclr.o(.text)) +

    [Called By]

    • >>   __aeabi_memset +
    + +

    __aeabi_memclr4 (Thumb, 0 bytes, Stack size 4 bytes, rt_memclr_w.o(.text)) +

    [Stack]

    • Max Depth = 4
    • Call Chain = __aeabi_memclr4 +
    +
    [Called By]
    • >>   BLE_ClearBuf +
    + +

    __aeabi_memclr8 (Thumb, 0 bytes, Stack size 4 bytes, rt_memclr_w.o(.text), UNUSED) + +

    __rt_memclr_w (Thumb, 78 bytes, Stack size 4 bytes, rt_memclr_w.o(.text), UNUSED) + +

    _memset_w (Thumb, 0 bytes, Stack size unknown bytes, rt_memclr_w.o(.text), UNUSED) +

    [Called By]

    • >>   __rt_memclr +
    + +

    strncpy (Thumb, 86 bytes, Stack size 8 bytes, strncpy.o(.text)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = strncpy +
    +
    [Calls]
    • >>   __aeabi_memclr +
    +
    [Called By]
    • >>   GetStr +
    • >>   BLE_SETPARA +
    • >>   BLE_PUTSRVC +
    • >>   BLE_GETPARA +
    + +

    __use_two_region_memory (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED) + +

    __rt_heap_escrow$2region (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED) + +

    __rt_heap_expand$2region (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED) + +

    _printf_truncate_signed (Thumb, 18 bytes, Stack size 0 bytes, _printf_truncate.o(.text)) +

    [Called By]

    • >>   _printf_int_dec +
    + +

    _printf_truncate_unsigned (Thumb, 18 bytes, Stack size 0 bytes, _printf_truncate.o(.text)) +

    [Called By]

    • >>   _printf_int_oct +
    • >>   _printf_int_hex +
    • >>   _printf_int_dec +
    + +

    _printf_int_common (Thumb, 178 bytes, Stack size 32 bytes, _printf_intcommon.o(.text)) +

    [Stack]

    • Max Depth = 48
    • Call Chain = _printf_int_common ⇒ _printf_post_padding +
    +
    [Calls]
    • >>   _printf_post_padding +
    • >>   _printf_pre_padding +
    +
    [Called By]
    • >>   _printf_longlong_oct +
    • >>   _printf_longlong_dec +
    • >>   _printf_longlong_hex +
    • >>   _printf_int_dec +
    + +

    _printf_charcount (Thumb, 40 bytes, Stack size 0 bytes, _printf_charcount.o(.text)) +

    [Called By]

    • >>   _printf_n +
    + +

    _printf_char_common (Thumb, 32 bytes, Stack size 64 bytes, _printf_char_common.o(.text)) +

    [Stack]

    • Max Depth = 104 + Unknown Stack Size +
    • Call Chain = _printf_char_common ⇒ __printf +
    +
    [Calls]
    • >>   __printf +
    +
    [Called By]
    • >>   __2sprintf +
    • >>   vsnprintf +
    + +

    _sputc (Thumb, 10 bytes, Stack size 0 bytes, _sputc.o(.text)) +

    [Called By]

    • >>   __2sprintf +
    • >>   vsnprintf +
    +
    [Address Reference Count : 1]
    • __2sprintf.o(.text) +
    +

    _snputc (Thumb, 16 bytes, Stack size 0 bytes, _snputc.o(.text)) +
    [Address Reference Count : 1]

    • vsnprintf.o(.text) +
    +

    _printf_cs_common (Thumb, 20 bytes, Stack size 8 bytes, _printf_char.o(.text)) +

    [Stack]

    • Max Depth = 40
    • Call Chain = _printf_cs_common ⇒ _printf_str ⇒ _printf_post_padding +
    +
    [Calls]
    • >>   _printf_str +
    +
    [Called By]
    • >>   _printf_string +
    • >>   _printf_char +
    + +

    _printf_char (Thumb, 16 bytes, Stack size 0 bytes, _printf_char.o(.text)) +

    [Stack]

    • Max Depth = 40
    • Call Chain = _printf_char ⇒ _printf_cs_common ⇒ _printf_str ⇒ _printf_post_padding +
    +
    [Calls]
    • >>   _printf_cs_common +
    +
    [Called By]
    • >>   _printf_c +
    + +

    _printf_string (Thumb, 8 bytes, Stack size 0 bytes, _printf_char.o(.text)) +

    [Stack]

    • Max Depth = 40
    • Call Chain = _printf_string ⇒ _printf_cs_common ⇒ _printf_str ⇒ _printf_post_padding +
    +
    [Calls]
    • >>   _printf_cs_common +
    +
    [Called By]
    • >>   _printf_s +
    + +

    _printf_wctomb (Thumb, 182 bytes, Stack size 56 bytes, _printf_wctomb.o(.text)) +

    [Stack]

    • Max Depth = 80
    • Call Chain = _printf_wctomb ⇒ _wcrtomb ⇒ __rt_ctype_table +
    +
    [Calls]
    • >>   _wcrtomb +
    • >>   _printf_post_padding +
    • >>   _printf_pre_padding +
    +
    [Called By]
    • >>   _printf_lcs_common +
    + +

    _printf_longlong_dec (Thumb, 108 bytes, Stack size 24 bytes, _printf_longlong_dec.o(.text)) +

    [Stack]

    • Max Depth = 72
    • Call Chain = _printf_longlong_dec ⇒ _printf_int_common ⇒ _printf_post_padding +
    +
    [Calls]
    • >>   _ll_udiv10 +
    • >>   _printf_int_common +
    +
    [Called By]
    • >>   _printf_llu +
    • >>   _printf_lld +
    • >>   _printf_lli +
    + +

    _printf_longlong_oct (Thumb, 66 bytes, Stack size 8 bytes, _printf_oct_int_ll.o(.text)) +

    [Stack]

    • Max Depth = 56
    • Call Chain = _printf_longlong_oct ⇒ _printf_int_common ⇒ _printf_post_padding +
    +
    [Calls]
    • >>   _printf_int_common +
    +
    [Called By]
    • >>   _printf_ll_oct +
    • >>   _printf_int_oct +
    + +

    _printf_int_oct (Thumb, 24 bytes, Stack size 8 bytes, _printf_oct_int_ll.o(.text)) +

    [Stack]

    • Max Depth = 64
    • Call Chain = _printf_int_oct ⇒ _printf_longlong_oct ⇒ _printf_int_common ⇒ _printf_post_padding +
    +
    [Calls]
    • >>   _printf_longlong_oct +
    • >>   _printf_truncate_unsigned +
    +
    [Called By]
    • >>   _printf_o +
    + +

    _printf_ll_oct (Thumb, 12 bytes, Stack size 0 bytes, _printf_oct_int_ll.o(.text)) +

    [Stack]

    • Max Depth = 56
    • Call Chain = _printf_ll_oct ⇒ _printf_longlong_oct ⇒ _printf_int_common ⇒ _printf_post_padding +
    +
    [Calls]
    • >>   _printf_longlong_oct +
    +
    [Called By]
    • >>   _printf_llo +
    + +

    _chval (Thumb, 28 bytes, Stack size 0 bytes, _chval.o(.text)) +

    [Called By]

    • >>   _scanf_int +
    + +

    __vfscanf_char (Thumb, 24 bytes, Stack size 0 bytes, scanf_char.o(.text)) +

    [Stack]

    • Max Depth = 152
    • Call Chain = __vfscanf_char ⇒ __vfscanf ⇒ _scanf_int +
    +
    [Calls]
    • >>   __vfscanf +
    +
    [Called By]
    • >>   __0sscanf +
    + +

    _sgetc (Thumb, 30 bytes, Stack size 0 bytes, _sgetc.o(.text)) +
    [Address Reference Count : 1]

    • __0sscanf.o(.text) +
    +

    _sbackspace (Thumb, 34 bytes, Stack size 0 bytes, _sgetc.o(.text)) +
    [Address Reference Count : 1]

    • __0sscanf.o(.text) +
    +

    _ll_udiv10 (Thumb, 138 bytes, Stack size 12 bytes, lludiv10.o(.text)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = _ll_udiv10 +
    +
    [Called By]
    • >>   _fp_digits +
    • >>   _printf_longlong_dec +
    + +

    isspace (Thumb, 18 bytes, Stack size 8 bytes, isspace.o(.text)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = isspace ⇒ __rt_ctype_table +
    +
    [Calls]
    • >>   __rt_ctype_table +
    +
    [Address Reference Count : 1]
    • scanf_char.o(.text) +
    +

    __lib_sel_fp_printf (Thumb, 2 bytes, Stack size 0 bytes, _printf_fp_dec.o(.text), UNUSED) + +

    _printf_fp_dec_real (Thumb, 620 bytes, Stack size 104 bytes, _printf_fp_dec.o(.text)) +

    [Stack]

    • Max Depth = 324
    • Call Chain = _printf_fp_dec_real ⇒ _fp_digits ⇒ _btod_etento ⇒ _btod_emul ⇒ _e2e +
    +
    [Calls]
    • >>   _printf_fp_infnan +
    • >>   __rt_locale +
    • >>   __ARM_fpclassify +
    • >>   _fp_digits +
    • >>   _printf_post_padding +
    • >>   _printf_pre_padding +
    +
    [Called By]
    • >>   _printf_fp_dec +
    + +

    _printf_fp_hex_real (Thumb, 756 bytes, Stack size 72 bytes, _printf_fp_hex.o(.text)) +

    [Stack]

    • Max Depth = 112
    • Call Chain = _printf_fp_hex_real ⇒ _printf_fp_infnan ⇒ _printf_post_padding +
    +
    [Calls]
    • >>   _printf_fp_infnan +
    • >>   __ARM_fpclassify +
    • >>   _printf_post_padding +
    • >>   _printf_pre_padding +
    +
    [Called By]
    • >>   _printf_fp_hex +
    + +

    _printf_lcs_common (Thumb, 20 bytes, Stack size 8 bytes, _printf_wchar.o(.text)) +

    [Stack]

    • Max Depth = 88
    • Call Chain = _printf_lcs_common ⇒ _printf_wctomb ⇒ _wcrtomb ⇒ __rt_ctype_table +
    +
    [Calls]
    • >>   _printf_wctomb +
    +
    [Called By]
    • >>   _printf_wstring +
    • >>   _printf_wchar +
    + +

    _printf_wchar (Thumb, 16 bytes, Stack size 0 bytes, _printf_wchar.o(.text)) +

    [Stack]

    • Max Depth = 88
    • Call Chain = _printf_wchar ⇒ _printf_lcs_common ⇒ _printf_wctomb ⇒ _wcrtomb ⇒ __rt_ctype_table +
    +
    [Calls]
    • >>   _printf_lcs_common +
    +
    [Called By]
    • >>   _printf_lc +
    + +

    _printf_wstring (Thumb, 8 bytes, Stack size 0 bytes, _printf_wchar.o(.text)) +

    [Stack]

    • Max Depth = 88
    • Call Chain = _printf_wstring ⇒ _printf_lcs_common ⇒ _printf_wctomb ⇒ _wcrtomb ⇒ __rt_ctype_table +
    +
    [Calls]
    • >>   _printf_lcs_common +
    +
    [Called By]
    • >>   _printf_ls +
    + +

    __vfscanf (Thumb, 878 bytes, Stack size 96 bytes, _scanf.o(.text)) +

    [Stack]

    • Max Depth = 152
    • Call Chain = __vfscanf ⇒ _scanf_int +
    +
    [Calls]
    • >>   _scanf_int +
    +
    [Called By]
    • >>   __vfscanf_char +
    + +

    _wcrtomb (Thumb, 64 bytes, Stack size 16 bytes, _wcrtomb.o(.text)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = _wcrtomb ⇒ __rt_ctype_table +
    +
    [Calls]
    • >>   __rt_ctype_table +
    +
    [Called By]
    • >>   _printf_wctomb +
    + +

    __user_libspace (Thumb, 8 bytes, Stack size 0 bytes, libspace.o(.text), UNUSED) + +

    __user_perproc_libspace (Thumb, 0 bytes, Stack size 0 bytes, libspace.o(.text)) +

    [Called By]

    • >>   __user_setup_stackheap +
    + +

    __user_perthread_libspace (Thumb, 0 bytes, Stack size 0 bytes, libspace.o(.text), UNUSED) + +

    __user_setup_stackheap (Thumb, 74 bytes, Stack size 8 bytes, sys_stackheap_outer.o(.text)) +

    [Stack]

    • Max Depth = 8 + Unknown Stack Size +
    • Call Chain = __user_setup_stackheap +
    +
    [Calls]
    • >>   __user_initial_stackheap +
    • >>   __user_perproc_libspace +
    +
    [Called By]
    • >>   __rt_entry_sh +
    + +

    __rt_ctype_table (Thumb, 16 bytes, Stack size 8 bytes, rt_ctype_table.o(.text)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = __rt_ctype_table +
    +
    [Calls]
    • >>   __rt_locale +
    +
    [Called By]
    • >>   _wcrtomb +
    • >>   isspace +
    + +

    __rt_locale (Thumb, 8 bytes, Stack size 0 bytes, rt_locale_intlibspace.o(.text)) +

    [Called By]

    • >>   __rt_ctype_table +
    • >>   _printf_fp_dec_real +
    • >>   __rt_lib_init_lc_common +
    + +

    _printf_fp_infnan (Thumb, 112 bytes, Stack size 24 bytes, _printf_fp_infnan.o(.text)) +

    [Stack]

    • Max Depth = 40
    • Call Chain = _printf_fp_infnan ⇒ _printf_post_padding +
    +
    [Calls]
    • >>   _printf_post_padding +
    • >>   _printf_pre_padding +
    +
    [Called By]
    • >>   _printf_fp_hex_real +
    • >>   _printf_fp_dec_real +
    + +

    _btod_etento (Thumb, 224 bytes, Stack size 72 bytes, bigflt0.o(.text)) +

    [Stack]

    • Max Depth = 124
    • Call Chain = _btod_etento ⇒ _btod_emul ⇒ _e2e +
    +
    [Calls]
    • >>   _btod_emul +
    • >>   _btod_ediv +
    +
    [Called By]
    • >>   _fp_digits +
    + +

    exit (Thumb, 18 bytes, Stack size 8 bytes, exit.o(.text)) +

    [Stack]

    • Max Depth = 8 + Unknown Stack Size +
    • Call Chain = exit +
    +
    [Calls]
    • >>   __rt_exit +
    +
    [Called By]
    • >>   __rt_entry_main +
    + +

    strcmp (Thumb, 128 bytes, Stack size 0 bytes, strcmpv7m.o(.text)) +

    [Called By]

    • >>   _get_lc_numeric +
    • >>   _get_lc_ctype +
    + +

    _sys_exit (Thumb, 8 bytes, Stack size 0 bytes, sys_exit.o(.text)) +

    [Called By]

    • >>   __rt_exit_exit +
    + +

    __I$use$semihosting (Thumb, 0 bytes, Stack size 0 bytes, use_no_semi.o(.text), UNUSED) + +

    __use_no_semihosting_swi (Thumb, 2 bytes, Stack size 0 bytes, use_no_semi.o(.text), UNUSED) + +

    __semihosting_library_function (Thumb, 0 bytes, Stack size 0 bytes, indicate_semi.o(.text), UNUSED) + +

    _btod_d2e (Thumb, 62 bytes, Stack size 0 bytes, btod.o(CL$$btod_d2e)) +

    [Calls]

    • >>   _d2e_norm_op1 +
    +
    [Called By]
    • >>   _fp_digits +
    + +

    _d2e_denorm_low (Thumb, 70 bytes, Stack size 0 bytes, btod.o(CL$$btod_d2e_denorm_low)) +

    [Called By]

    • >>   _d2e_norm_op1 +
    + +

    _d2e_norm_op1 (Thumb, 96 bytes, Stack size 0 bytes, btod.o(CL$$btod_d2e_norm_op1)) +

    [Calls]

    • >>   _d2e_denorm_low +
    +
    [Called By]
    • >>   _btod_d2e +
    + +

    __btod_div_common (Thumb, 696 bytes, Stack size 24 bytes, btod.o(CL$$btod_div_common)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = __btod_div_common +
    +
    [Called By]
    • >>   _btod_ediv +
    + +

    _e2e (Thumb, 220 bytes, Stack size 24 bytes, btod.o(CL$$btod_e2e)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = _e2e +
    +
    [Called By]
    • >>   _btod_emul +
    • >>   _btod_ediv +
    + +

    _btod_ediv (Thumb, 42 bytes, Stack size 28 bytes, btod.o(CL$$btod_ediv)) +

    [Stack]

    • Max Depth = 52
    • Call Chain = _btod_ediv ⇒ _e2e +
    +
    [Calls]
    • >>   _e2e +
    • >>   __btod_div_common +
    +
    [Called By]
    • >>   _btod_etento +
    • >>   _fp_digits +
    + +

    _btod_emul (Thumb, 42 bytes, Stack size 28 bytes, btod.o(CL$$btod_emul)) +

    [Stack]

    • Max Depth = 52
    • Call Chain = _btod_emul ⇒ _e2e +
    +
    [Calls]
    • >>   __btod_mult_common +
    • >>   _e2e +
    +
    [Called By]
    • >>   _btod_etento +
    • >>   _fp_digits +
    + +

    __btod_mult_common (Thumb, 580 bytes, Stack size 16 bytes, btod.o(CL$$btod_mult_common)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = __btod_mult_common +
    +
    [Called By]
    • >>   _btod_emul +
    + +

    ADC_Cmd (Thumb, 20 bytes, Stack size 0 bytes, stm32f10x_adc.o(i.ADC_Cmd)) +

    [Called By]

    • >>   uf_ADC_Init +
    + +

    ADC_DeInit (Thumb, 56 bytes, Stack size 8 bytes, stm32f10x_adc.o(i.ADC_DeInit)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = ADC_DeInit +
    +
    [Calls]
    • >>   RCC_APB2PeriphResetCmd +
    +
    [Called By]
    • >>   uf_ADC_Init +
    + +

    ADC_GetCalibrationStatus (Thumb, 14 bytes, Stack size 0 bytes, stm32f10x_adc.o(i.ADC_GetCalibrationStatus)) +

    [Called By]

    • >>   uf_ADC_Init +
    + +

    ADC_GetConversionValue (Thumb, 6 bytes, Stack size 0 bytes, stm32f10x_adc.o(i.ADC_GetConversionValue)) +

    [Called By]

    • >>   ADC_GetVal +
    + +

    ADC_GetFlagStatus (Thumb, 14 bytes, Stack size 0 bytes, stm32f10x_adc.o(i.ADC_GetFlagStatus)) +

    [Called By]

    • >>   ADC_GetVal +
    + +

    ADC_GetResetCalibrationStatus (Thumb, 14 bytes, Stack size 0 bytes, stm32f10x_adc.o(i.ADC_GetResetCalibrationStatus)) +

    [Called By]

    • >>   uf_ADC_Init +
    + +

    ADC_GetVal (Thumb, 46 bytes, Stack size 8 bytes, adc.o(i.ADC_GetVal)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = ADC_GetVal ⇒ ADC_RegularChannelConfig +
    +
    [Calls]
    • >>   ADC_SoftwareStartConvCmd +
    • >>   ADC_RegularChannelConfig +
    • >>   ADC_GetFlagStatus +
    • >>   ADC_GetConversionValue +
    +
    [Called By]
    • >>   MCU_TemperaProcess +
    • >>   LOAD_VOL +
    + +

    ADC_Init (Thumb, 62 bytes, Stack size 8 bytes, stm32f10x_adc.o(i.ADC_Init)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = ADC_Init +
    +
    [Called By]
    • >>   uf_ADC_Init +
    + +

    ADC_RegularChannelConfig (Thumb, 116 bytes, Stack size 16 bytes, stm32f10x_adc.o(i.ADC_RegularChannelConfig)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = ADC_RegularChannelConfig +
    +
    [Called By]
    • >>   ADC_GetVal +
    + +

    ADC_ResetCalibration (Thumb, 10 bytes, Stack size 0 bytes, stm32f10x_adc.o(i.ADC_ResetCalibration)) +

    [Called By]

    • >>   uf_ADC_Init +
    + +

    ADC_SoftwareStartConvCmd (Thumb, 20 bytes, Stack size 0 bytes, stm32f10x_adc.o(i.ADC_SoftwareStartConvCmd)) +

    [Called By]

    • >>   ADC_GetVal +
    + +

    ADC_StartCalibration (Thumb, 10 bytes, Stack size 0 bytes, stm32f10x_adc.o(i.ADC_StartCalibration)) +

    [Called By]

    • >>   uf_ADC_Init +
    + +

    ADDR_Assign_Moni (Thumb, 80 bytes, Stack size 16 bytes, gpio.o(i.ADDR_Assign_Moni)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = ADDR_Assign_Moni +
    +
    [Calls]
    • >>   IO1_IN +
    +
    [Called By]
    • >>   TIM3_IRQHandler +
    + +

    ADDR_Rank_Moni (Thumb, 132 bytes, Stack size 32 bytes, gpio.o(i.ADDR_Rank_Moni)) +

    [Stack]

    • Max Depth = 124
    • Call Chain = ADDR_Rank_Moni ⇒ MODBUS_Init ⇒ uf_UART1_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq +
    +
    [Calls]
    • >>   MODBUS_Init +
    • >>   IO3_IN +
    +
    [Called By]
    • >>   TIM3_IRQHandler +
    + +

    AFE_Ctrl (Thumb, 330 bytes, Stack size 24 bytes, afe_sh3673520.o(i.AFE_Ctrl)) +

    [Stack]

    • Max Depth = 136
    • Call Chain = AFE_Ctrl ⇒ PCHG_Ctrl ⇒ CTRL_Off ⇒ AFE_Write ⇒ AFE_WriteOneByte ⇒ delay_us +
    +
    [Calls]
    • >>   AFE_Write +
    • >>   CHG_LIMIT_On +
    • >>   CHG_LIMIT_Off +
    • >>   PCHG_Ctrl +
    +
    [Called By]
    • >>   main +
    + +

    AFE_CurrentProcess (Thumb, 402 bytes, Stack size 24 bytes, afe_sh3673520.o(i.AFE_CurrentProcess)) +

    [Stack]

    • Max Depth = 136
    • Call Chain = AFE_CurrentProcess ⇒ AFE_Read ⇒ AFE_ReadMulByte ⇒ delay_us +
    +
    [Calls]
    • >>   SLEEP_Refresh +
    • >>   SLEEP2_Refresh +
    • >>   AFE_Read +
    • >>   CHG_LIMIT_PWM_Adjust +
    +
    [Called By]
    • >>   main +
    + +

    AFE_ProtectProcess (Thumb, 1790 bytes, Stack size 40 bytes, afe_sh3673520.o(i.AFE_ProtectProcess)) +

    [Stack]

    • Max Depth = 276
    • Call Chain = AFE_ProtectProcess ⇒ SOE_BkData ⇒ EEPROM_RdMulByte ⇒ I2C_GetFlagStatus +
    +
    [Calls]
    • >>   LED_ALARM_Off +
    • >>   AFE_Write +
    • >>   AFE_Read +
    • >>   CTRL_Off +
    • >>   LED_ALARM_On +
    • >>   DO_On +
    • >>   DO_Off +
    • >>   SOE_BkData +
    +
    [Called By]
    • >>   main +
    + +

    AFE_Read (Thumb, 54 bytes, Stack size 16 bytes, afe_sh3673520.o(i.AFE_Read)) +

    [Stack]

    • Max Depth = 112
    • Call Chain = AFE_Read ⇒ AFE_ReadMulByte ⇒ delay_us +
    +
    [Calls]
    • >>   delay_ms +
    • >>   SPI2_Error +
    • >>   AFE_ReadMulByte +
    +
    [Called By]
    • >>   AFE_VoltageProcess +
    • >>   AFE_TemperaProcess +
    • >>   AFE_ProtectProcess +
    • >>   AFE_CurrentProcess +
    • >>   MEMORY_UpdateAFE +
    • >>   OCC2_Ctrl +
    + +

    AFE_ReadMulByte (Thumb, 302 bytes, Stack size 80 bytes, spi.o(i.AFE_ReadMulByte)) +

    [Stack]

    • Max Depth = 96
    • Call Chain = AFE_ReadMulByte ⇒ delay_us +
    +
    [Calls]
    • >>   CRC8_Cal +
    • >>   delay_us +
    • >>   SPI_I2S_SendData +
    • >>   SPI_I2S_ReceiveData +
    • >>   SPI_I2S_GetFlagStatus +
    • >>   GPIO_SetBits +
    • >>   GPIO_ResetBits +
    +
    [Called By]
    • >>   AFE_Read +
    + +

    AFE_Reset (Thumb, 140 bytes, Stack size 48 bytes, spi.o(i.AFE_Reset)) +

    [Stack]

    • Max Depth = 56
    • Call Chain = AFE_Reset ⇒ CRC8_Cal +
    +
    [Calls]
    • >>   CRC8_Cal +
    • >>   SPI_I2S_SendData +
    • >>   SPI_I2S_ReceiveData +
    • >>   SPI_I2S_GetFlagStatus +
    • >>   GPIO_SetBits +
    • >>   GPIO_ResetBits +
    +
    [Called By]
    • >>   MEMORY_UpdateAFE +
    + +

    AFE_TemperaProcess (Thumb, 152 bytes, Stack size 16 bytes, afe_sh3673520.o(i.AFE_TemperaProcess)) +

    [Stack]

    • Max Depth = 128
    • Call Chain = AFE_TemperaProcess ⇒ AFE_Read ⇒ AFE_ReadMulByte ⇒ delay_us +
    +
    [Calls]
    • >>   AFE_Read +
    • >>   Trigger_amTProtect +
    • >>   Trigger_amTAlarm +
    • >>   Trigger_afeTProtect +
    • >>   Trigger_afeTAlarm +
    • >>   TEMP_Cal_CMFA +
    • >>   Release_amTProtect +
    • >>   Release_amTAlarm +
    • >>   Release_afeTProtect +
    • >>   Release_afeTAlarm +
    +
    [Called By]
    • >>   main +
    + +

    AFE_VoltageProcess (Thumb, 990 bytes, Stack size 64 bytes, afe_sh3673520.o(i.AFE_VoltageProcess)) +

    [Stack]

    • Max Depth = 176
    • Call Chain = AFE_VoltageProcess ⇒ AFE_Read ⇒ AFE_ReadMulByte ⇒ delay_us +
    +
    [Calls]
    • >>   AFE_Read +
    • >>   Trigger_UVProtect +
    • >>   Trigger_UVAlarm +
    • >>   Trigger_OVProtect +
    • >>   Trigger_OVAlarm +
    • >>   Release_UVProtect +
    • >>   Release_UVAlarm +
    • >>   Release_OVProtect +
    • >>   Release_OVAlarm +
    +
    [Called By]
    • >>   main +
    + +

    AFE_Write (Thumb, 76 bytes, Stack size 24 bytes, afe_sh3673520.o(i.AFE_Write)) +

    [Stack]

    • Max Depth = 88
    • Call Chain = AFE_Write ⇒ AFE_WriteOneByte ⇒ delay_us +
    +
    [Calls]
    • >>   delay_ms +
    • >>   AFE_WriteOneByte +
    +
    [Called By]
    • >>   AFE_ProtectProcess +
    • >>   AFE_Ctrl +
    • >>   MEMORY_UpdateAFE +
    • >>   OCC2_Ctrl +
    • >>   CTRL_Off +
    + +

    AFE_WriteOneByte (Thumb, 144 bytes, Stack size 48 bytes, spi.o(i.AFE_WriteOneByte)) +

    [Stack]

    • Max Depth = 64
    • Call Chain = AFE_WriteOneByte ⇒ delay_us +
    +
    [Calls]
    • >>   CRC8_Cal +
    • >>   delay_us +
    • >>   SPI_I2S_SendData +
    • >>   SPI_I2S_ReceiveData +
    • >>   SPI_I2S_GetFlagStatus +
    • >>   GPIO_SetBits +
    • >>   GPIO_ResetBits +
    +
    [Called By]
    • >>   AFE_Write +
    + +

    Addr_Set (Thumb, 166 bytes, Stack size 24 bytes, global.o(i.Addr_Set)) +

    [Stack]

    • Max Depth = 76
    • Call Chain = Addr_Set ⇒ EEPROM_WrMulByte ⇒ I2C_GetFlagStatus +
    +
    [Calls]
    • >>   IO2_OUTSet +
    • >>   IO2_OUTReset +
    • >>   EEPROM_WrMulByte +
    • >>   delay_ms +
    +
    [Called By]
    • >>   main +
    + +

    BKP_DeInit (Thumb, 18 bytes, Stack size 8 bytes, stm32f10x_bkp.o(i.BKP_DeInit)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = BKP_DeInit +
    +
    [Calls]
    • >>   RCC_BackupResetCmd +
    +
    [Called By]
    • >>   uf_RTC_Update +
    • >>   uf_RTC_Init +
    + +

    BKP_ReadBackupRegister (Thumb, 12 bytes, Stack size 8 bytes, stm32f10x_bkp.o(i.BKP_ReadBackupRegister)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = BKP_ReadBackupRegister +
    +
    [Called By]
    • >>   uf_RTC_Init +
    + +

    BKP_WriteBackupRegister (Thumb, 12 bytes, Stack size 8 bytes, stm32f10x_bkp.o(i.BKP_WriteBackupRegister)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = BKP_WriteBackupRegister +
    +
    [Called By]
    • >>   uf_RTC_Update +
    • >>   uf_RTC_Init +
    + +

    BLE_CheckName (Thumb, 96 bytes, Stack size 8 bytes, mbo26a.o(i.BLE_CheckName)) +

    [Stack]

    • Max Depth = 176 + Unknown Stack Size +
    • Call Chain = BLE_CheckName ⇒ BLE_Reset ⇒ BLE_printf ⇒ vsnprintf ⇒ _printf_char_common ⇒ __printf +
    +
    [Calls]
    • >>   delay_ms +
    • >>   BLE_printf +
    • >>   BLE_Reset +
    • >>   BLE_ClearBuf +
    • >>   strstr +
    +
    [Called By]
    • >>   BLE_IQ_Update +
    • >>   BLE_IQ_Transmit +
    • >>   BLE_IT_Update +
    • >>   BLE_WriteName +
    + +

    BLE_ClearBuf (Thumb, 16 bytes, Stack size 0 bytes, mbo26a.o(i.BLE_ClearBuf)) +

    [Stack]

    • Max Depth = 4
    • Call Chain = BLE_ClearBuf ⇒ __aeabi_memclr4 +
    +
    [Calls]
    • >>   __aeabi_memclr4 +
    +
    [Called By]
    • >>   BLE_Init +
    • >>   BLE_IT_Receive +
    • >>   BLE_IT_Update +
    • >>   BLE_CheckName +
    + +

    BLE_ClearFlg (Thumb, 16 bytes, Stack size 0 bytes, mbo26a.o(i.BLE_ClearFlg)) +

    [Called By]

    • >>   BLE_Init +
    + +

    BLE_GETPARA (Thumb, 148 bytes, Stack size 16 bytes, mbo26a.o(i.BLE_GETPARA)) +

    [Stack]

    • Max Depth = 28
    • Call Chain = BLE_GETPARA ⇒ strstr +
    +
    [Calls]
    • >>   strncpy +
    • >>   strlen +
    • >>   strstr +
    • >>   strchr +
    +
    [Called By]
    • >>   BLE_IT_Update +
    + +

    BLE_IO_Init (Thumb, 50 bytes, Stack size 16 bytes, mbo26a.o(i.BLE_IO_Init)) +

    [Stack]

    • Max Depth = 36
    • Call Chain = BLE_IO_Init ⇒ GPIO_Init +
    +
    [Calls]
    • >>   RCC_APB2PeriphClockCmd +
    • >>   GPIO_ResetBits +
    • >>   GPIO_Init +
    +
    [Called By]
    • >>   main +
    + +

    BLE_IQ_Transmit (Thumb, 4254 bytes, Stack size 40 bytes, mbo26a.o(i.BLE_IQ_Transmit)) +

    [Stack]

    • Max Depth = 216 + Unknown Stack Size +
    • Call Chain = BLE_IQ_Transmit ⇒ BLE_CheckName ⇒ BLE_Reset ⇒ BLE_printf ⇒ vsnprintf ⇒ _printf_char_common ⇒ __printf +
    +
    [Calls]
    • >>   BLE_printf +
    • >>   BLE_Reset +
    • >>   BLE_CheckName +
    • >>   __aeabi_i2f +
    • >>   __aeabi_fdiv +
    • >>   __aeabi_f2d +
    +
    [Called By]
    • >>   main +
    + +

    BLE_IQ_Update (Thumb, 680 bytes, Stack size 24 bytes, mbo26a.o(i.BLE_IQ_Update)) +

    [Stack]

    • Max Depth = 200 + Unknown Stack Size +
    • Call Chain = BLE_IQ_Update ⇒ BLE_CheckName ⇒ BLE_Reset ⇒ BLE_printf ⇒ vsnprintf ⇒ _printf_char_common ⇒ __printf +
    +
    [Calls]
    • >>   BLE_SetBaud +
    • >>   BLE_CheckName +
    +
    [Called By]
    • >>   main +
    + +

    BLE_IT_Receive (Thumb, 36 bytes, Stack size 8 bytes, mbo26a.o(i.BLE_IT_Receive)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = BLE_IT_Receive ⇒ BLE_ClearBuf ⇒ __aeabi_memclr4 +
    +
    [Calls]
    • >>   USART_ReceiveData +
    • >>   BLE_ClearBuf +
    +
    [Called By]
    • >>   UART4_IRQHandler +
    + +

    BLE_IT_Update (Thumb, 152 bytes, Stack size 16 bytes, mbo26a.o(i.BLE_IT_Update)) +

    [Stack]

    • Max Depth = 280 + Unknown Stack Size +
    • Call Chain = BLE_IT_Update ⇒ BLE_SETPARA ⇒ __0sscanf ⇒ __vfscanf_char ⇒ __vfscanf ⇒ _scanf_int +
    +
    [Calls]
    • >>   BLE_SetBaud +
    • >>   BLE_SETPARA +
    • >>   BLE_PUTSRVC +
    • >>   BLE_GETPARA +
    • >>   BLE_ClearBuf +
    • >>   BLE_CheckName +
    • >>   strstr +
    +
    [Called By]
    • >>   TIM3_IRQHandler +
    + +

    BLE_Init (Thumb, 40 bytes, Stack size 8 bytes, mbo26a.o(i.BLE_Init)) +

    [Stack]

    • Max Depth = 92
    • Call Chain = BLE_Init ⇒ uf_UART4_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq +
    +
    [Calls]
    • >>   uf_UART4_Init +
    • >>   BLE_ClearFlg +
    • >>   BLE_ClearBuf +
    +
    [Called By]
    • >>   main +
    • >>   BLE_TIM_Moni +
    + +

    BLE_Open (Thumb, 2 bytes, Stack size 0 bytes, mbo26a.o(i.BLE_Open)) +

    [Called By]

    • >>   main +
    + +

    BLE_PUTSRVC (Thumb, 220 bytes, Stack size 24 bytes, mbo26a.o(i.BLE_PUTSRVC)) +

    [Stack]

    • Max Depth = 36
    • Call Chain = BLE_PUTSRVC ⇒ strstr +
    +
    [Calls]
    • >>   RTC_GetCounter +
    • >>   strncpy +
    • >>   strlen +
    • >>   strstr +
    • >>   strchr +
    +
    [Called By]
    • >>   BLE_IT_Update +
    + +

    BLE_Reset (Thumb, 20 bytes, Stack size 8 bytes, mbo26a.o(i.BLE_Reset)) +

    [Stack]

    • Max Depth = 168 + Unknown Stack Size +
    • Call Chain = BLE_Reset ⇒ BLE_printf ⇒ vsnprintf ⇒ _printf_char_common ⇒ __printf +
    +
    [Calls]
    • >>   BLE_printf +
    +
    [Called By]
    • >>   BLE_IQ_Transmit +
    • >>   BLE_CheckName +
    + +

    BLE_SETPARA (Thumb, 222 bytes, Stack size 40 bytes, mbo26a.o(i.BLE_SETPARA)) +

    [Stack]

    • Max Depth = 264
    • Call Chain = BLE_SETPARA ⇒ __0sscanf ⇒ __vfscanf_char ⇒ __vfscanf ⇒ _scanf_int +
    +
    [Calls]
    • >>   EEPROM_WrMulByte +
    • >>   GetStr +
    • >>   uf_CAN1_Init +
    • >>   delay_ms +
    • >>   strncpy +
    • >>   strlen +
    • >>   strstr +
    • >>   strchr +
    • >>   __0sscanf +
    +
    [Called By]
    • >>   BLE_IT_Update +
    + +

    BLE_SetBaud (Thumb, 26 bytes, Stack size 8 bytes, mbo26a.o(i.BLE_SetBaud)) +

    [Stack]

    • Max Depth = 168 + Unknown Stack Size +
    • Call Chain = BLE_SetBaud ⇒ BLE_printf ⇒ vsnprintf ⇒ _printf_char_common ⇒ __printf +
    +
    [Calls]
    • >>   delay_ms +
    • >>   uf_UART4_Init +
    • >>   BLE_printf +
    +
    [Called By]
    • >>   BLE_IQ_Update +
    • >>   BLE_IT_Update +
    + +

    BLE_TIM_Moni (Thumb, 38 bytes, Stack size 8 bytes, mbo26a.o(i.BLE_TIM_Moni)) +

    [Stack]

    • Max Depth = 100
    • Call Chain = BLE_TIM_Moni ⇒ BLE_Init ⇒ uf_UART4_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq +
    +
    [Calls]
    • >>   BLE_Init +
    +
    [Called By]
    • >>   TIM3_IRQHandler +
    + +

    BLE_WriteName (Thumb, 4 bytes, Stack size 0 bytes, mbo26a.o(i.BLE_WriteName)) +

    [Stack]

    • Max Depth = 176 + Unknown Stack Size +
    • Call Chain = BLE_WriteName ⇒ BLE_CheckName ⇒ BLE_Reset ⇒ BLE_printf ⇒ vsnprintf ⇒ _printf_char_common ⇒ __printf +
    +
    [Calls]
    • >>   BLE_CheckName +
    +
    [Called By]
    • >>   MODBUS_IQ_Transmit +
    • >>   MODBUS1_IQ_Transmit +
    + +

    BLE_printf (Thumb, 50 bytes, Stack size 32 bytes, mbo26a.o(i.BLE_printf)) +

    [Stack]

    • Max Depth = 160 + Unknown Stack Size +
    • Call Chain = BLE_printf ⇒ vsnprintf ⇒ _printf_char_common ⇒ __printf +
    +
    [Calls]
    • >>   vsnprintf +
    +
    [Called By]
    • >>   BLE_IQ_Transmit +
    • >>   BLE_SetBaud +
    • >>   BLE_Reset +
    • >>   BLE_CheckName +
    + +

    BusFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f10x_it.o(i.BusFault_Handler)) +

    [Calls]

    • >>   BusFault_Handler +
    +
    [Called By]
    • >>   BusFault_Handler +
    +
    [Address Reference Count : 1]
    • startup_stm32f10x_hd.o(RESET) +
    +

    CALI_CurrentProcess (Thumb, 102 bytes, Stack size 24 bytes, afe_sh3673520.o(i.CALI_CurrentProcess)) +

    [Stack]

    • Max Depth = 108
    • Call Chain = CALI_CurrentProcess ⇒ EEPROM_CALI_WrZero ⇒ EEPROM_RdMulByte ⇒ I2C_GetFlagStatus +
    +
    [Calls]
    • >>   EEPROM_CALI_WrZero +
    • >>   EEPROM_CALI_WrGain +
    +
    [Called By]
    • >>   main +
    + +

    CAN1_SendData (Thumb, 138 bytes, Stack size 24 bytes, can.o(i.CAN1_SendData)) +

    [Stack]

    • Max Depth = 36
    • Call Chain = CAN1_SendData ⇒ CAN_Transmit +
    +
    [Calls]
    • >>   CAN_TransmitStatus +
    • >>   CAN_Transmit +
    +
    [Called By]
    • >>   CAN_Protocol_solis +
    • >>   CAN_Protocol_SolArk +
    • >>   CAN_Protocol_Pylon +
    • >>   CAN_Protocol_Growatt +
    • >>   CAN_Protocol_Deye +
    + +

    CAN_DeInit (Thumb, 38 bytes, Stack size 8 bytes, stm32f10x_can.o(i.CAN_DeInit)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = CAN_DeInit +
    +
    [Calls]
    • >>   RCC_APB1PeriphResetCmd +
    +
    [Called By]
    • >>   uf_CAN1_Init +
    + +

    CAN_FilterInit (Thumb, 194 bytes, Stack size 20 bytes, stm32f10x_can.o(i.CAN_FilterInit)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = CAN_FilterInit +
    +
    [Called By]
    • >>   uf_CAN1_Init +
    + +

    CAN_GetITStatus (Thumb, 162 bytes, Stack size 0 bytes, stm32f10x_can.o(i.CAN_GetITStatus)) +

    [Calls]

    • >>   CheckITStatus +
    +
    [Called By]
    • >>   USB_LP_CAN1_RX0_IRQHandler +
    + +

    CAN_ITConfig (Thumb, 16 bytes, Stack size 0 bytes, stm32f10x_can.o(i.CAN_ITConfig)) +

    [Called By]

    • >>   uf_CAN1_Init +
    + +

    CAN_Init (Thumb, 232 bytes, Stack size 8 bytes, stm32f10x_can.o(i.CAN_Init)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = CAN_Init +
    +
    [Called By]
    • >>   uf_CAN1_Init +
    + +

    CAN_Protocol_Deye (Thumb, 664 bytes, Stack size 40 bytes, protocolswitch_p1.o(i.CAN_Protocol_Deye)) +

    [Stack]

    • Max Depth = 76
    • Call Chain = CAN_Protocol_Deye ⇒ CAN1_SendData ⇒ CAN_Transmit +
    +
    [Calls]
    • >>   CAN1_SendData +
    +
    [Called By]
    • >>   CAN_UpdateData +
    + +

    CAN_Protocol_Growatt (Thumb, 862 bytes, Stack size 48 bytes, protocolswitch_p1.o(i.CAN_Protocol_Growatt)) +

    [Stack]

    • Max Depth = 84
    • Call Chain = CAN_Protocol_Growatt ⇒ CAN1_SendData ⇒ CAN_Transmit +
    +
    [Calls]
    • >>   CAN1_SendData +
    +
    [Called By]
    • >>   CAN_UpdateData +
    + +

    CAN_Protocol_Pylon (Thumb, 1378 bytes, Stack size 48 bytes, protocolswitch_p1.o(i.CAN_Protocol_Pylon)) +

    [Stack]

    • Max Depth = 84
    • Call Chain = CAN_Protocol_Pylon ⇒ CAN1_SendData ⇒ CAN_Transmit +
    +
    [Calls]
    • >>   CAN1_SendData +
    +
    [Called By]
    • >>   CAN_UpdateData +
    + +

    CAN_Protocol_SolArk (Thumb, 770 bytes, Stack size 48 bytes, protocolswitch_p1.o(i.CAN_Protocol_SolArk)) +

    [Stack]

    • Max Depth = 84
    • Call Chain = CAN_Protocol_SolArk ⇒ CAN1_SendData ⇒ CAN_Transmit +
    +
    [Calls]
    • >>   CAN1_SendData +
    +
    [Called By]
    • >>   CAN_UpdateData +
    + +

    CAN_Protocol_solis (Thumb, 590 bytes, Stack size 40 bytes, protocolswitch_p1.o(i.CAN_Protocol_solis)) +

    [Stack]

    • Max Depth = 76
    • Call Chain = CAN_Protocol_solis ⇒ CAN1_SendData ⇒ CAN_Transmit +
    +
    [Calls]
    • >>   CAN1_SendData +
    +
    [Called By]
    • >>   CAN_UpdateData +
    + +

    CAN_Receive (Thumb, 144 bytes, Stack size 8 bytes, stm32f10x_can.o(i.CAN_Receive)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = CAN_Receive +
    +
    [Called By]
    • >>   USB_LP_CAN1_RX0_IRQHandler +
    + +

    CAN_StructInit (Thumb, 32 bytes, Stack size 0 bytes, stm32f10x_can.o(i.CAN_StructInit)) +

    [Called By]

    • >>   uf_CAN1_Init +
    + +

    CAN_TIM_Moni (Thumb, 20 bytes, Stack size 0 bytes, can.o(i.CAN_TIM_Moni)) +

    [Stack]

    • Max Depth = 80
    • Call Chain = CAN_TIM_Moni ⇒ uf_CAN1_Init ⇒ delay_ms +
    +
    [Calls]
    • >>   uf_CAN1_Init +
    +
    [Called By]
    • >>   TIM3_IRQHandler +
    + +

    CAN_Transmit (Thumb, 164 bytes, Stack size 12 bytes, stm32f10x_can.o(i.CAN_Transmit)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = CAN_Transmit +
    +
    [Called By]
    • >>   CAN1_SendData +
    + +

    CAN_TransmitStatus (Thumb, 88 bytes, Stack size 0 bytes, stm32f10x_can.o(i.CAN_TransmitStatus)) +

    [Called By]

    • >>   CAN1_SendData +
    + +

    CAN_UpdateData (Thumb, 46 bytes, Stack size 0 bytes, can.o(i.CAN_UpdateData)) +

    [Stack]

    • Max Depth = 84
    • Call Chain = CAN_UpdateData ⇒ CAN_Protocol_SolArk ⇒ CAN1_SendData ⇒ CAN_Transmit +
    +
    [Calls]
    • >>   CAN_Protocol_solis +
    • >>   CAN_Protocol_SolArk +
    • >>   CAN_Protocol_Pylon +
    • >>   CAN_Protocol_Growatt +
    • >>   CAN_Protocol_Deye +
    +
    [Called By]
    • >>   main +
    + +

    CHG_LIMIT_Ctrl (Thumb, 212 bytes, Stack size 12 bytes, afe_sh3673520.o(i.CHG_LIMIT_Ctrl)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = CHG_LIMIT_Ctrl +
    +
    [Called By]
    • >>   main +
    + +

    CHG_LIMIT_Init (Thumb, 68 bytes, Stack size 16 bytes, pwm.o(i.CHG_LIMIT_Init)) +

    [Stack]

    • Max Depth = 84
    • Call Chain = CHG_LIMIT_Init ⇒ TIM4_PWM_Init ⇒ GPIO_Init +
    +
    [Calls]
    • >>   TIM4_PWM_Init +
    • >>   RCC_APB2PeriphClockCmd +
    • >>   GPIO_ResetBits +
    • >>   GPIO_Init +
    +
    [Called By]
    • >>   uf_GPIO_Init +
    + +

    CHG_LIMIT_Off (Thumb, 46 bytes, Stack size 16 bytes, pwm.o(i.CHG_LIMIT_Off)) +

    [Stack]

    • Max Depth = 40
    • Call Chain = CHG_LIMIT_Off ⇒ delay_ms +
    +
    [Calls]
    • >>   delay_ms +
    • >>   PWM_Set_Duty_Percent +
    • >>   GPIO_ResetBits +
    +
    [Called By]
    • >>   AFE_Ctrl +
    + +

    CHG_LIMIT_On (Thumb, 146 bytes, Stack size 24 bytes, pwm.o(i.CHG_LIMIT_On)) +

    [Stack]

    • Max Depth = 56
    • Call Chain = CHG_LIMIT_On ⇒ __aeabi_d2iz +
    +
    [Calls]
    • >>   delay_ms +
    • >>   PWM_Set_Duty_Percent +
    • >>   GPIO_SetBits +
    • >>   __aeabi_fmul +
    • >>   __aeabi_ui2f +
    • >>   __aeabi_i2f +
    • >>   __aeabi_fdiv +
    • >>   __aeabi_f2d +
    • >>   __aeabi_d2iz +
    • >>   __aeabi_dadd +
    +
    [Called By]
    • >>   AFE_Ctrl +
    + +

    CHG_LIMIT_PWM_Adjust (Thumb, 188 bytes, Stack size 16 bytes, pwm.o(i.CHG_LIMIT_PWM_Adjust)) +

    [Stack]

    • Max Depth = 40
    • Call Chain = CHG_LIMIT_PWM_Adjust ⇒ PWM_Set_Duty_Percent ⇒ __aeabi_fmul +
    +
    [Calls]
    • >>   PWM_Set_Duty_Percent +
    • >>   __aeabi_fsub +
    • >>   __aeabi_fadd +
    +
    [Called By]
    • >>   AFE_CurrentProcess +
    + +

    CRC16_Cal (Thumb, 54 bytes, Stack size 16 bytes, rs485_modbus.o(i.CRC16_Cal)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = CRC16_Cal +
    +
    [Called By]
    • >>   MODBUS_WrIndex_Tx +
    • >>   MODBUS_Screen_WrSlaveAddr_Tx +
    • >>   MODBUS_Screen_RdSlave_Tx +
    • >>   MODBUS_MASTER_Polling_Tx +
    • >>   MODBUS_IQ_Transmit +
    • >>   MODBUS_Config_RdSlave_Tx +
    • >>   MODBUS_AddrAssign_Tx +
    • >>   MODBUS1_IQ_Transmit +
    • >>   UART3_ReadRecord +
    • >>   UART3_ProtocolSwitch +
    • >>   UART3_ClearRecord +
    • >>   MODBUS1_Fbb_Rx +
    • >>   MODBUS1_Faa_Rx +
    • >>   MODBUS1_F10_Rx +
    • >>   MODBUS1_F03_Rx +
    • >>   MODBUS1_CtrlMOS_Rx +
    • >>   UART1_ReadRecord +
    • >>   UART1_ProtocolSwitch +
    • >>   UART1_ClearRecord +
    • >>   MODBUS_WrIndex_Rx +
    • >>   MODBUS_MASTER_F10_Rx +
    • >>   MODBUS_MASTER_F03_Rx +
    • >>   MODBUS_Fbb_Rx +
    • >>   MODBUS_Faa_Rx +
    • >>   MODBUS_F10_Rx +
    • >>   MODBUS_F03_Rx +
    • >>   MODBUS_CtrlMOS_Rx +
    + +

    CRC8_Cal (Thumb, 30 bytes, Stack size 8 bytes, global.o(i.CRC8_Cal)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = CRC8_Cal +
    +
    [Called By]
    • >>   MEMORY_UpdateFlash +
    • >>   uf_GLOBAL_Init +
    • >>   Screen_IQ_Transmit +
    • >>   MODBUS_Screen_WrSlaveAddr_Tx +
    • >>   MODBUS_AddrAssign_Tx +
    • >>   FLASH_ReadCheck +
    • >>   AFE_WriteOneByte +
    • >>   AFE_Reset +
    • >>   AFE_ReadMulByte +
    • >>   MODBUS1_F10_Rx +
    • >>   MODBUS_F10_Rx +
    + +

    CTRL_Off (Thumb, 26 bytes, Stack size 8 bytes, afe_sh3673520.o(i.CTRL_Off)) +

    [Stack]

    • Max Depth = 96
    • Call Chain = CTRL_Off ⇒ AFE_Write ⇒ AFE_WriteOneByte ⇒ delay_us +
    +
    [Calls]
    • >>   AFE_Write +
    +
    [Called By]
    • >>   TSC_Detect +
    • >>   AFE_ProtectProcess +
    • >>   PCHG_Ctrl +
    + +

    CTRL_On (Thumb, 8 bytes, Stack size 0 bytes, afe_sh3673520.o(i.CTRL_On)) +

    [Called By]

    • >>   TSC_Detect +
    • >>   PCHG_StartCtrl +
    • >>   PCHG_Ctrl +
    + +

    Cali_FCC_Moni (Thumb, 218 bytes, Stack size 24 bytes, gasgauge.o(i.Cali_FCC_Moni)) +

    [Stack]

    • Max Depth = 76
    • Call Chain = Cali_FCC_Moni ⇒ EEPROM_WrMulByte ⇒ I2C_GetFlagStatus +
    +
    [Calls]
    • >>   RTC_GetCounter +
    • >>   EEPROM_WrMulByte +
    • >>   delay_ms +
    +
    [Called By]
    • >>   GaugeManage +
    + +

    Cali_SOC_Moni (Thumb, 62 bytes, Stack size 0 bytes, gasgauge.o(i.Cali_SOC_Moni)) +

    [Called By]

    • >>   TIM3_IRQHandler +
    + +

    DO_Off (Thumb, 8 bytes, Stack size 0 bytes, gpio.o(i.DO_Off)) +

    [Calls]

    • >>   GPIO_ResetBits +
    +
    [Called By]
    • >>   AFE_ProtectProcess +
    + +

    DO_On (Thumb, 8 bytes, Stack size 0 bytes, gpio.o(i.DO_On)) +

    [Calls]

    • >>   GPIO_SetBits +
    +
    [Called By]
    • >>   AFE_ProtectProcess +
    + +

    DebugMon_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f10x_it.o(i.DebugMon_Handler)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    EEPROM_CALI_RdGain (Thumb, 188 bytes, Stack size 16 bytes, i2c.o(i.EEPROM_CALI_RdGain)) +

    [Stack]

    • Max Depth = 84
    • Call Chain = EEPROM_CALI_RdGain ⇒ EEPROM_RdMulByte ⇒ I2C_GetFlagStatus +
    +
    [Calls]
    • >>   EEPROM_WrMulByte +
    • >>   EEPROM_RdMulByte +
    • >>   delay_ms +
    +
    [Called By]
    • >>   uf_GLOBAL_Init +
    + +

    EEPROM_CALI_RdZero (Thumb, 186 bytes, Stack size 16 bytes, i2c.o(i.EEPROM_CALI_RdZero)) +

    [Stack]

    • Max Depth = 84
    • Call Chain = EEPROM_CALI_RdZero ⇒ EEPROM_RdMulByte ⇒ I2C_GetFlagStatus +
    +
    [Calls]
    • >>   EEPROM_WrMulByte +
    • >>   EEPROM_RdMulByte +
    • >>   delay_ms +
    +
    [Called By]
    • >>   uf_GLOBAL_Init +
    + +

    EEPROM_CALI_WrGain (Thumb, 96 bytes, Stack size 16 bytes, i2c.o(i.EEPROM_CALI_WrGain)) +

    [Stack]

    • Max Depth = 84
    • Call Chain = EEPROM_CALI_WrGain ⇒ EEPROM_RdMulByte ⇒ I2C_GetFlagStatus +
    +
    [Calls]
    • >>   EEPROM_WrMulByte +
    • >>   EEPROM_RdMulByte +
    • >>   delay_ms +
    +
    [Called By]
    • >>   CALI_CurrentProcess +
    + +

    EEPROM_CALI_WrZero (Thumb, 96 bytes, Stack size 16 bytes, i2c.o(i.EEPROM_CALI_WrZero)) +

    [Stack]

    • Max Depth = 84
    • Call Chain = EEPROM_CALI_WrZero ⇒ EEPROM_RdMulByte ⇒ I2C_GetFlagStatus +
    +
    [Calls]
    • >>   EEPROM_WrMulByte +
    • >>   EEPROM_RdMulByte +
    • >>   delay_ms +
    +
    [Called By]
    • >>   CALI_CurrentProcess +
    + +

    EEPROM_RdMulByte (Thumb, 420 bytes, Stack size 56 bytes, i2c.o(i.EEPROM_RdMulByte)) +

    [Stack]

    • Max Depth = 68
    • Call Chain = EEPROM_RdMulByte ⇒ I2C_GetFlagStatus +
    +
    [Calls]
    • >>   I2C_SendData +
    • >>   I2C_Send7bitAddress +
    • >>   I2C_ReceiveData +
    • >>   I2C_GetFlagStatus +
    • >>   I2C_GenerateSTOP +
    • >>   I2C_GenerateSTART +
    • >>   I2C_CheckEvent +
    • >>   I2C_AcknowledgeConfig +
    +
    [Called By]
    • >>   EEPROM_CALI_RdZero +
    • >>   EEPROM_CALI_RdGain +
    • >>   uf_RTC_Init +
    • >>   uf_I2C1_Init +
    • >>   uf_GLOBAL_Init +
    • >>   Screen_IT_Update +
    • >>   ParaChange +
    • >>   OCV_CaliSOC +
    • >>   MODBUS_IQ_Transmit +
    • >>   MODBUS1_IQ_Transmit +
    • >>   InitGasGauge +
    • >>   EEPROM_CALI_WrZero +
    • >>   EEPROM_CALI_WrGain +
    • >>   SCR_Send_RecordInfo +
    • >>   SCR_DispProcotol +
    • >>   UART3_ClearRecord +
    • >>   UART1_ClearRecord +
    • >>   SOE_BkData +
    + +

    EEPROM_WrMulByte (Thumb, 308 bytes, Stack size 40 bytes, i2c.o(i.EEPROM_WrMulByte)) +

    [Stack]

    • Max Depth = 52
    • Call Chain = EEPROM_WrMulByte ⇒ I2C_GetFlagStatus +
    +
    [Calls]
    • >>   I2C_SendData +
    • >>   I2C_Send7bitAddress +
    • >>   I2C_GetFlagStatus +
    • >>   I2C_GenerateSTOP +
    • >>   I2C_GenerateSTART +
    • >>   I2C_CheckEvent +
    +
    [Called By]
    • >>   EEPROM_CALI_RdZero +
    • >>   EEPROM_CALI_RdGain +
    • >>   uf_RTC_Update +
    • >>   uf_I2C1_Init +
    • >>   uf_GLOBAL_Init +
    • >>   Screen_IT_Update +
    • >>   RTC_Get +
    • >>   RTC_BackUp +
    • >>   ParaChange +
    • >>   OCV_CaliSOC +
    • >>   MODBUS_IQ_Transmit +
    • >>   MODBUS1_IQ_Transmit +
    • >>   InitGasGauge +
    • >>   GaugeManage +
    • >>   Addr_Set +
    • >>   EEPROM_CALI_WrZero +
    • >>   EEPROM_CALI_WrGain +
    • >>   Cali_FCC_Moni +
    • >>   MODBUS_WrIndex_Rx +
    • >>   SOE_BkData +
    • >>   BLE_SETPARA +
    + +

    FCCCali_TIM_Moni (Thumb, 44 bytes, Stack size 0 bytes, global.o(i.FCCCali_TIM_Moni)) +

    [Called By]

    • >>   TIM3_IRQHandler +
    + +

    FLASH_ClearFlag (Thumb, 6 bytes, Stack size 0 bytes, stm32f10x_flash.o(i.FLASH_ClearFlag)) +

    [Called By]

    • >>   FLASH_WrData +
    + +

    FLASH_ErasePage (Thumb, 56 bytes, Stack size 16 bytes, stm32f10x_flash.o(i.FLASH_ErasePage)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = FLASH_ErasePage ⇒ FLASH_WaitForLastOperation +
    +
    [Calls]
    • >>   FLASH_WaitForLastOperation +
    +
    [Called By]
    • >>   FLASH_WrData +
    + +

    FLASH_GetBank1Status (Thumb, 34 bytes, Stack size 0 bytes, stm32f10x_flash.o(i.FLASH_GetBank1Status)) +

    [Called By]

    • >>   FLASH_WaitForLastOperation +
    + +

    FLASH_Lock (Thumb, 12 bytes, Stack size 0 bytes, stm32f10x_flash.o(i.FLASH_Lock)) +

    [Called By]

    • >>   FLASH_WrData +
    + +

    FLASH_ProgramHalfWord (Thumb, 48 bytes, Stack size 20 bytes, stm32f10x_flash.o(i.FLASH_ProgramHalfWord)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = FLASH_ProgramHalfWord ⇒ FLASH_WaitForLastOperation +
    +
    [Calls]
    • >>   FLASH_WaitForLastOperation +
    +
    [Called By]
    • >>   FLASH_WrData +
    + +

    FLASH_RdDataByte (Thumb, 20 bytes, Stack size 8 bytes, flash.o(i.FLASH_RdDataByte)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = FLASH_RdDataByte +
    +
    [Called By]
    • >>   MEMORY_UpdateFlash +
    • >>   FLASH_ReadCheck +
    + +

    FLASH_RdWord (Thumb, 26 bytes, Stack size 8 bytes, flash.o(i.FLASH_RdWord)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = FLASH_RdWord +
    +
    [Called By]
    • >>   uf_I2C1_Init +
    + +

    FLASH_ReadCheck (Thumb, 78 bytes, Stack size 408 bytes, flash.o(i.FLASH_ReadCheck)) +

    [Stack]

    • Max Depth = 416
    • Call Chain = FLASH_ReadCheck ⇒ CRC8_Cal +
    +
    [Calls]
    • >>   CRC8_Cal +
    • >>   FLASH_RdDataByte +
    • >>   __aeabi_memcpy4 +
    • >>   __aeabi_memcpy +
    +
    [Called By]
    • >>   FLASH_UpdateMemory +
    + +

    FLASH_Unlock (Thumb, 12 bytes, Stack size 0 bytes, stm32f10x_flash.o(i.FLASH_Unlock)) +

    [Called By]

    • >>   FLASH_WrData +
    + +

    FLASH_UpdateMemory (Thumb, 26 bytes, Stack size 8 bytes, flash.o(i.FLASH_UpdateMemory)) +

    [Stack]

    • Max Depth = 424
    • Call Chain = FLASH_UpdateMemory ⇒ FLASH_ReadCheck ⇒ CRC8_Cal +
    +
    [Calls]
    • >>   FLASH_ReadCheck +
    +
    [Called By]
    • >>   uf_FLASH_Init +
    + +

    FLASH_WaitForLastOperation (Thumb, 36 bytes, Stack size 4 bytes, stm32f10x_flash.o(i.FLASH_WaitForLastOperation)) +

    [Stack]

    • Max Depth = 4
    • Call Chain = FLASH_WaitForLastOperation +
    +
    [Calls]
    • >>   FLASH_GetBank1Status +
    +
    [Called By]
    • >>   FLASH_ProgramHalfWord +
    • >>   FLASH_ErasePage +
    + +

    FLASH_WrData (Thumb, 64 bytes, Stack size 24 bytes, flash.o(i.FLASH_WrData)) +

    [Stack]

    • Max Depth = 48
    • Call Chain = FLASH_WrData ⇒ FLASH_ProgramHalfWord ⇒ FLASH_WaitForLastOperation +
    +
    [Calls]
    • >>   FLASH_Unlock +
    • >>   FLASH_ProgramHalfWord +
    • >>   FLASH_Lock +
    • >>   FLASH_ErasePage +
    • >>   FLASH_ClearFlag +
    +
    [Called By]
    • >>   MEMORY_UpdateFlash +
    • >>   uf_I2C1_Init +
    + +

    GPIO_Init (Thumb, 162 bytes, Stack size 20 bytes, stm32f10x_gpio.o(i.GPIO_Init)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = GPIO_Init +
    +
    [Called By]
    • >>   uf_SPI2_Init +
    • >>   uf_I2C1_Init +
    • >>   uf_GPIO_Init +
    • >>   uf_CAN1_Init +
    • >>   uf_ADC_Init +
    • >>   BLE_IO_Init +
    • >>   TIM4_PWM_Init +
    • >>   uf_UART4_Init +
    • >>   uf_UART3_Init +
    • >>   uf_UART2_Init +
    • >>   uf_UART1_Init +
    • >>   CHG_LIMIT_Init +
    + +

    GPIO_PinRemapConfig (Thumb, 82 bytes, Stack size 20 bytes, stm32f10x_gpio.o(i.GPIO_PinRemapConfig)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = GPIO_PinRemapConfig +
    +
    [Called By]
    • >>   uf_GPIO_Init +
    + +

    GPIO_ReadInputDataBit (Thumb, 14 bytes, Stack size 0 bytes, stm32f10x_gpio.o(i.GPIO_ReadInputDataBit)) +

    [Called By]

    • >>   KEY_IN +
    • >>   IO3_IN +
    • >>   IO1_IN +
    + +

    GPIO_ResetBits (Thumb, 4 bytes, Stack size 0 bytes, stm32f10x_gpio.o(i.GPIO_ResetBits)) +

    [Called By]

    • >>   IO2_OUTReset +
    • >>   uf_GPIO_Init +
    • >>   LED_RUN_Off +
    • >>   LED_ALARM_Off +
    • >>   BLE_IO_Init +
    • >>   CHG_LIMIT_Off +
    • >>   AFE_WriteOneByte +
    • >>   AFE_Reset +
    • >>   AFE_ReadMulByte +
    • >>   CHG_LIMIT_Init +
    • >>   PCHG_Off +
    • >>   LED4_Off +
    • >>   LED3_Off +
    • >>   LED2_Off +
    • >>   LED1_Off +
    • >>   DO_Off +
    + +

    GPIO_SetBits (Thumb, 4 bytes, Stack size 0 bytes, stm32f10x_gpio.o(i.GPIO_SetBits)) +

    [Called By]

    • >>   IO2_OUTSet +
    • >>   uf_SPI2_Init +
    • >>   uf_GPIO_Init +
    • >>   LED_RUN_On +
    • >>   CHG_LIMIT_On +
    • >>   AFE_WriteOneByte +
    • >>   AFE_Reset +
    • >>   AFE_ReadMulByte +
    • >>   PCHG_On +
    • >>   LED_ALARM_On +
    • >>   LED4_On +
    • >>   LED3_On +
    • >>   LED2_On +
    • >>   LED1_On +
    • >>   DO_On +
    + +

    GaugeManage (Thumb, 1226 bytes, Stack size 40 bytes, gasgauge.o(i.GaugeManage)) +

    [Stack]

    • Max Depth = 116
    • Call Chain = GaugeManage ⇒ Cali_FCC_Moni ⇒ EEPROM_WrMulByte ⇒ I2C_GetFlagStatus +
    +
    [Calls]
    • >>   EEPROM_WrMulByte +
    • >>   delay_ms +
    • >>   LED_ALARM_Off +
    • >>   LED_ALARM_On +
    • >>   LED4_On +
    • >>   LED4_Off +
    • >>   LED3_On +
    • >>   LED3_Off +
    • >>   LED2_On +
    • >>   LED2_Off +
    • >>   LED1_On +
    • >>   LED1_Off +
    • >>   Cali_FCC_Moni +
    +
    [Called By]
    • >>   main +
    + +

    GetStr (Thumb, 84 bytes, Stack size 24 bytes, global.o(i.GetStr)) +

    [Stack]

    • Max Depth = 36
    • Call Chain = GetStr ⇒ strstr +
    +
    [Calls]
    • >>   strncpy +
    • >>   strlen +
    • >>   strstr +
    • >>   strchr +
    +
    [Called By]
    • >>   Screen_IT_Update +
    • >>   BLE_SETPARA +
    + +

    HAL_GPIO_TogglePin (Thumb, 16 bytes, Stack size 0 bytes, gpio.o(i.HAL_GPIO_TogglePin)) +

    [Called By]

    • >>   LED_RUN_Toggle +
    • >>   LED_ALARM_Toggle +
    + +

    HardFault_Handler (Thumb, 20 bytes, Stack size 0 bytes, stm32f10x_it.o(i.HardFault_Handler)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    I2C_AcknowledgeConfig (Thumb, 20 bytes, Stack size 0 bytes, stm32f10x_i2c.o(i.I2C_AcknowledgeConfig)) +

    [Called By]

    • >>   EEPROM_RdMulByte +
    • >>   uf_I2C1_Init +
    + +

    I2C_CheckEvent (Thumb, 24 bytes, Stack size 0 bytes, stm32f10x_i2c.o(i.I2C_CheckEvent)) +

    [Called By]

    • >>   EEPROM_WrMulByte +
    • >>   EEPROM_RdMulByte +
    + +

    I2C_Cmd (Thumb, 20 bytes, Stack size 0 bytes, stm32f10x_i2c.o(i.I2C_Cmd)) +

    [Called By]

    • >>   uf_I2C1_Init +
    + +

    I2C_DeInit (Thumb, 38 bytes, Stack size 8 bytes, stm32f10x_i2c.o(i.I2C_DeInit)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = I2C_DeInit +
    +
    [Calls]
    • >>   RCC_APB1PeriphResetCmd +
    +
    [Called By]
    • >>   uf_I2C1_Init +
    + +

    I2C_GenerateSTART (Thumb, 20 bytes, Stack size 0 bytes, stm32f10x_i2c.o(i.I2C_GenerateSTART)) +

    [Called By]

    • >>   EEPROM_WrMulByte +
    • >>   EEPROM_RdMulByte +
    + +

    I2C_GenerateSTOP (Thumb, 20 bytes, Stack size 0 bytes, stm32f10x_i2c.o(i.I2C_GenerateSTOP)) +

    [Called By]

    • >>   EEPROM_WrMulByte +
    • >>   EEPROM_RdMulByte +
    + +

    I2C_GetFlagStatus (Thumb, 42 bytes, Stack size 12 bytes, stm32f10x_i2c.o(i.I2C_GetFlagStatus)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = I2C_GetFlagStatus +
    +
    [Called By]
    • >>   EEPROM_WrMulByte +
    • >>   EEPROM_RdMulByte +
    + +

    I2C_Init (Thumb, 178 bytes, Stack size 40 bytes, stm32f10x_i2c.o(i.I2C_Init)) +

    [Stack]

    • Max Depth = 52
    • Call Chain = I2C_Init ⇒ RCC_GetClocksFreq +
    +
    [Calls]
    • >>   RCC_GetClocksFreq +
    +
    [Called By]
    • >>   uf_I2C1_Init +
    + +

    I2C_ReceiveData (Thumb, 6 bytes, Stack size 0 bytes, stm32f10x_i2c.o(i.I2C_ReceiveData)) +

    [Called By]

    • >>   EEPROM_RdMulByte +
    + +

    I2C_Send7bitAddress (Thumb, 16 bytes, Stack size 0 bytes, stm32f10x_i2c.o(i.I2C_Send7bitAddress)) +

    [Called By]

    • >>   EEPROM_WrMulByte +
    • >>   EEPROM_RdMulByte +
    + +

    I2C_SendData (Thumb, 4 bytes, Stack size 0 bytes, stm32f10x_i2c.o(i.I2C_SendData)) +

    [Called By]

    • >>   EEPROM_WrMulByte +
    • >>   EEPROM_RdMulByte +
    + +

    IO1_IN (Thumb, 10 bytes, Stack size 0 bytes, gpio.o(i.IO1_IN)) +

    [Calls]

    • >>   GPIO_ReadInputDataBit +
    +
    [Called By]
    • >>   ADDR_Assign_Moni +
    + +

    IO2_OUTReset (Thumb, 10 bytes, Stack size 0 bytes, gpio.o(i.IO2_OUTReset)) +

    [Calls]

    • >>   GPIO_ResetBits +
    +
    [Called By]
    • >>   MODBUS_AddrAssign_Tx +
    • >>   Addr_Set +
    + +

    IO2_OUTSet (Thumb, 10 bytes, Stack size 0 bytes, gpio.o(i.IO2_OUTSet)) +

    [Calls]

    • >>   GPIO_SetBits +
    +
    [Called By]
    • >>   MODBUS_AddrAssign_Tx +
    • >>   Addr_Set +
    + +

    IO3_IN (Thumb, 8 bytes, Stack size 0 bytes, gpio.o(i.IO3_IN)) +

    [Calls]

    • >>   GPIO_ReadInputDataBit +
    +
    [Called By]
    • >>   ADDR_Rank_Moni +
    + +

    IWDG_Enable (Thumb, 10 bytes, Stack size 0 bytes, stm32f10x_iwdg.o(i.IWDG_Enable)) +

    [Called By]

    • >>   uf_IWDG_Init +
    + +

    IWDG_Feed (Thumb, 4 bytes, Stack size 0 bytes, wdg.o(i.IWDG_Feed)) +

    [Called By]

    • >>   main +
    + +

    IWDG_ReloadCounter (Thumb, 10 bytes, Stack size 0 bytes, stm32f10x_iwdg.o(i.IWDG_ReloadCounter)) +

    [Called By]

    • >>   uf_IWDG_Init +
    + +

    IWDG_SetPrescaler (Thumb, 6 bytes, Stack size 0 bytes, stm32f10x_iwdg.o(i.IWDG_SetPrescaler)) +

    [Called By]

    • >>   uf_IWDG_Init +
    + +

    IWDG_SetReload (Thumb, 6 bytes, Stack size 0 bytes, stm32f10x_iwdg.o(i.IWDG_SetReload)) +

    [Called By]

    • >>   uf_IWDG_Init +
    + +

    IWDG_WriteAccessCmd (Thumb, 6 bytes, Stack size 0 bytes, stm32f10x_iwdg.o(i.IWDG_WriteAccessCmd)) +

    [Called By]

    • >>   uf_IWDG_Init +
    + +

    InitGasGauge (Thumb, 384 bytes, Stack size 32 bytes, gasgauge.o(i.InitGasGauge)) +

    [Stack]

    • Max Depth = 100
    • Call Chain = InitGasGauge ⇒ EEPROM_RdMulByte ⇒ I2C_GetFlagStatus +
    +
    [Calls]
    • >>   EEPROM_WrMulByte +
    • >>   EEPROM_RdMulByte +
    • >>   delay_ms +
    • >>   OCV_CaliSoc_dp +
    • >>   OCV_CaliSOC_DataWr +
    +
    [Called By]
    • >>   main +
    + +

    Is_Leap_Year (Thumb, 44 bytes, Stack size 0 bytes, rtc.o(i.Is_Leap_Year)) +

    [Called By]

    • >>   RTC_Get +
    • >>   RTC_Set +
    + +

    KEY_IN (Thumb, 8 bytes, Stack size 0 bytes, gpio.o(i.KEY_IN)) +

    [Calls]

    • >>   GPIO_ReadInputDataBit +
    +
    [Called By]
    • >>   KEY_TIM_Moni +
    + +

    KEY_TIM_Moni (Thumb, 174 bytes, Stack size 16 bytes, gpio.o(i.KEY_TIM_Moni)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = KEY_TIM_Moni +
    +
    [Calls]
    • >>   KEY_IN +
    +
    [Called By]
    • >>   TIM3_IRQHandler +
    + +

    LED1_Off (Thumb, 8 bytes, Stack size 0 bytes, gpio.o(i.LED1_Off)) +

    [Calls]

    • >>   GPIO_ResetBits +
    +
    [Called By]
    • >>   GaugeManage +
    + +

    LED1_On (Thumb, 8 bytes, Stack size 0 bytes, gpio.o(i.LED1_On)) +

    [Calls]

    • >>   GPIO_SetBits +
    +
    [Called By]
    • >>   GaugeManage +
    + +

    LED2_Off (Thumb, 10 bytes, Stack size 0 bytes, gpio.o(i.LED2_Off)) +

    [Calls]

    • >>   GPIO_ResetBits +
    +
    [Called By]
    • >>   GaugeManage +
    + +

    LED2_On (Thumb, 10 bytes, Stack size 0 bytes, gpio.o(i.LED2_On)) +

    [Calls]

    • >>   GPIO_SetBits +
    +
    [Called By]
    • >>   GaugeManage +
    + +

    LED3_Off (Thumb, 8 bytes, Stack size 0 bytes, gpio.o(i.LED3_Off)) +

    [Calls]

    • >>   GPIO_ResetBits +
    +
    [Called By]
    • >>   GaugeManage +
    + +

    LED3_On (Thumb, 8 bytes, Stack size 0 bytes, gpio.o(i.LED3_On)) +

    [Calls]

    • >>   GPIO_SetBits +
    +
    [Called By]
    • >>   GaugeManage +
    + +

    LED4_Off (Thumb, 8 bytes, Stack size 0 bytes, gpio.o(i.LED4_Off)) +

    [Calls]

    • >>   GPIO_ResetBits +
    +
    [Called By]
    • >>   GaugeManage +
    + +

    LED4_On (Thumb, 8 bytes, Stack size 0 bytes, gpio.o(i.LED4_On)) +

    [Calls]

    • >>   GPIO_SetBits +
    +
    [Called By]
    • >>   GaugeManage +
    + +

    LED_ALARM_Off (Thumb, 8 bytes, Stack size 0 bytes, gpio.o(i.LED_ALARM_Off)) +

    [Calls]

    • >>   GPIO_ResetBits +
    +
    [Called By]
    • >>   GaugeManage +
    • >>   AFE_ProtectProcess +
    • >>   main +
    + +

    LED_ALARM_On (Thumb, 8 bytes, Stack size 0 bytes, gpio.o(i.LED_ALARM_On)) +

    [Calls]

    • >>   GPIO_SetBits +
    +
    [Called By]
    • >>   GaugeManage +
    • >>   AFE_ProtectProcess +
    + +

    LED_ALARM_Toggle (Thumb, 8 bytes, Stack size 0 bytes, gpio.o(i.LED_ALARM_Toggle)) +

    [Calls]

    • >>   HAL_GPIO_TogglePin +
    +
    [Called By]
    • >>   main +
    + +

    LED_RUN_Off (Thumb, 10 bytes, Stack size 0 bytes, gpio.o(i.LED_RUN_Off)) +

    [Calls]

    • >>   GPIO_ResetBits +
    +
    [Called By]
    • >>   main +
    + +

    LED_RUN_On (Thumb, 10 bytes, Stack size 0 bytes, gpio.o(i.LED_RUN_On)) +

    [Calls]

    • >>   GPIO_SetBits +
    +
    [Called By]
    • >>   main +
    + +

    LED_RUN_Toggle (Thumb, 10 bytes, Stack size 0 bytes, gpio.o(i.LED_RUN_Toggle)) +

    [Calls]

    • >>   HAL_GPIO_TogglePin +
    +
    [Called By]
    • >>   main +
    + +

    LOAD_VOL (Thumb, 26 bytes, Stack size 8 bytes, adc.o(i.LOAD_VOL)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = LOAD_VOL ⇒ ADC_GetVal ⇒ ADC_RegularChannelConfig +
    +
    [Calls]
    • >>   ADC_GetVal +
    +
    [Called By]
    • >>   TSC_Detect +
    • >>   PCHG_StartCtrl +
    • >>   PCHG_Ctrl +
    + +

    MCU_TemperaProcess (Thumb, 440 bytes, Stack size 40 bytes, adc.o(i.MCU_TemperaProcess)) +

    [Stack]

    • Max Depth = 72
    • Call Chain = MCU_TemperaProcess ⇒ Trigger_mcuTProtect +
    +
    [Calls]
    • >>   Trigger_mcuTProtect +
    • >>   Trigger_mcuTAlarm +
    • >>   Trigger_CurProtectLock +
    • >>   Trigger_CurProtect +
    • >>   Trigger_CurAlarm +
    • >>   TEMP_Cal +
    • >>   Release_mcuTProtect +
    • >>   Release_mcuTAlarm +
    • >>   Release_CurProtect +
    • >>   Release_CurAlarm +
    • >>   ADC_GetVal +
    +
    [Called By]
    • >>   main +
    + +

    MEMORY_UpdateAFE (Thumb, 232 bytes, Stack size 48 bytes, afe_sh3673520.o(i.MEMORY_UpdateAFE)) +

    [Stack]

    • Max Depth = 160
    • Call Chain = MEMORY_UpdateAFE ⇒ AFE_Read ⇒ AFE_ReadMulByte ⇒ delay_us +
    +
    [Calls]
    • >>   AFE_Write +
    • >>   AFE_Read +
    • >>   AFE_Reset +
    +
    [Called By]
    • >>   uf_FLASH_Init +
    • >>   Screen_IQ_Transmit +
    • >>   MODBUS_IQ_Transmit +
    • >>   MODBUS1_IQ_Transmit +
    + +

    MEMORY_UpdateFlash (Thumb, 90 bytes, Stack size 416 bytes, flash.o(i.MEMORY_UpdateFlash)) +

    [Stack]

    • Max Depth = 464
    • Call Chain = MEMORY_UpdateFlash ⇒ FLASH_WrData ⇒ FLASH_ProgramHalfWord ⇒ FLASH_WaitForLastOperation +
    +
    [Calls]
    • >>   CRC8_Cal +
    • >>   FLASH_RdDataByte +
    • >>   FLASH_WrData +
    • >>   __aeabi_memcpy4 +
    • >>   __aeabi_memcpy +
    +
    [Called By]
    • >>   Screen_IQ_Transmit +
    • >>   ParaChange +
    • >>   MODBUS_IQ_Transmit +
    • >>   MODBUS1_IQ_Transmit +
    + +

    MODBUS1_CtrlMOS_Rx (Thumb, 68 bytes, Stack size 16 bytes, rs485_modbus_inverter.o(i.MODBUS1_CtrlMOS_Rx)) +

    [Stack]

    • Max Depth = 100
    • Call Chain = MODBUS1_CtrlMOS_Rx ⇒ MODBUS1_Init ⇒ uf_UART3_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq +
    +
    [Calls]
    • >>   MODBUS1_Init +
    • >>   CRC16_Cal +
    • >>   __aeabi_memcpy +
    +
    [Called By]
    • >>   MODBUS1_IT_TIMUpdate +
    + +

    MODBUS1_F03_Rx (Thumb, 188 bytes, Stack size 24 bytes, rs485_modbus_inverter.o(i.MODBUS1_F03_Rx)) +

    [Stack]

    • Max Depth = 108
    • Call Chain = MODBUS1_F03_Rx ⇒ MODBUS1_Init ⇒ uf_UART3_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq +
    +
    [Calls]
    • >>   MODBUS1_Init +
    • >>   USART_ITConfig +
    • >>   CRC16_Cal +
    +
    [Called By]
    • >>   MODBUS1_IT_TIMUpdate +
    + +

    MODBUS1_F10_Rx (Thumb, 292 bytes, Stack size 56 bytes, rs485_modbus_inverter.o(i.MODBUS1_F10_Rx)) +

    [Stack]

    • Max Depth = 140
    • Call Chain = MODBUS1_F10_Rx ⇒ MODBUS1_Init ⇒ uf_UART3_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq +
    +
    [Calls]
    • >>   CRC8_Cal +
    • >>   MODBUS1_Init +
    • >>   USART_ITConfig +
    • >>   CRC16_Cal +
    • >>   __aeabi_memcpy +
    +
    [Called By]
    • >>   MODBUS1_IT_TIMUpdate +
    + +

    MODBUS1_Faa_Rx (Thumb, 60 bytes, Stack size 8 bytes, rs485_modbus_inverter.o(i.MODBUS1_Faa_Rx)) +

    [Stack]

    • Max Depth = 92
    • Call Chain = MODBUS1_Faa_Rx ⇒ MODBUS1_Init ⇒ uf_UART3_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq +
    +
    [Calls]
    • >>   MODBUS1_Init +
    • >>   USART_ITConfig +
    • >>   CRC16_Cal +
    +
    [Called By]
    • >>   MODBUS1_IT_TIMUpdate +
    + +

    MODBUS1_Fbb_Rx (Thumb, 76 bytes, Stack size 8 bytes, rs485_modbus_inverter.o(i.MODBUS1_Fbb_Rx)) +

    [Stack]

    • Max Depth = 92
    • Call Chain = MODBUS1_Fbb_Rx ⇒ MODBUS1_Init ⇒ uf_UART3_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq +
    +
    [Calls]
    • >>   MODBUS1_Init +
    • >>   USART_ITConfig +
    • >>   CRC16_Cal +
    +
    [Called By]
    • >>   MODBUS1_IT_TIMUpdate +
    + +

    MODBUS1_IQ_Transmit (Thumb, 1088 bytes, Stack size 112 bytes, rs485_modbus_inverter.o(i.MODBUS1_IQ_Transmit)) +

    [Stack]

    • Max Depth = 576 + Unknown Stack Size +
    • Call Chain = MODBUS1_IQ_Transmit ⇒ MEMORY_UpdateFlash ⇒ FLASH_WrData ⇒ FLASH_ProgramHalfWord ⇒ FLASH_WaitForLastOperation +
    +
    [Calls]
    • >>   MEMORY_UpdateFlash +
    • >>   EEPROM_WrMulByte +
    • >>   EEPROM_RdMulByte +
    • >>   Refresh_ScreenVersion +
    • >>   Refresh_PACK_SN +
    • >>   Refresh_HardwareVersion +
    • >>   Refresh_BMS_SN +
    • >>   uf_CAN1_Init +
    • >>   delay_ms +
    • >>   MEMORY_UpdateAFE +
    • >>   USART_ITConfig +
    • >>   USART3_SendMulByte +
    • >>   BLE_WriteName +
    • >>   CRC16_Cal +
    +
    [Called By]
    • >>   main +
    + +

    MODBUS1_IT_Receive (Thumb, 60 bytes, Stack size 8 bytes, rs485_modbus_inverter.o(i.MODBUS1_IT_Receive)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = MODBUS1_IT_Receive +
    +
    [Calls]
    • >>   TIM_Cmd +
    • >>   USART_ReceiveData +
    • >>   TIM_SetCounter +
    +
    [Called By]
    • >>   USART3_IRQHandler +
    + +

    MODBUS1_IT_TIMUpdate (Thumb, 770 bytes, Stack size 24 bytes, rs485_modbus_inverter.o(i.MODBUS1_IT_TIMUpdate)) +

    [Stack]

    • Max Depth = 164
    • Call Chain = MODBUS1_IT_TIMUpdate ⇒ MODBUS1_F10_Rx ⇒ MODBUS1_Init ⇒ uf_UART3_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq +
    +
    [Calls]
    • >>   SLEEP_Refresh +
    • >>   SLEEP2_Refresh +
    • >>   MODBUS1_Init +
    • >>   YDN_Protocol_Pylon +
    • >>   UART3_ReadRecord +
    • >>   UART3_ProtocolSwitch +
    • >>   UART3_EraseIAP +
    • >>   UART3_ClearRecord +
    • >>   MODBUS1_Fbb_Rx +
    • >>   MODBUS1_Faa_Rx +
    • >>   MODBUS1_F10_Rx +
    • >>   MODBUS1_F03_Rx +
    • >>   MODBUS1_CtrlMOS_Rx +
    +
    [Called By]
    • >>   TIM3_IRQHandler +
    + +

    MODBUS1_Init (Thumb, 38 bytes, Stack size 0 bytes, rs485_modbus_inverter.o(i.MODBUS1_Init)) +

    [Stack]

    • Max Depth = 84
    • Call Chain = MODBUS1_Init ⇒ uf_UART3_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq +
    +
    [Calls]
    • >>   uf_UART3_Init +
    +
    [Called By]
    • >>   main +
    • >>   MODBUS1_TIM_Moni +
    • >>   MODBUS1_IT_TIMUpdate +
    • >>   YDN +
    • >>   UART3_ReadRecord +
    • >>   UART3_EraseIAP +
    • >>   UART3_ClearRecord +
    • >>   MODBUS1_Fbb_Rx +
    • >>   MODBUS1_Faa_Rx +
    • >>   MODBUS1_F10_Rx +
    • >>   MODBUS1_F03_Rx +
    • >>   MODBUS1_CtrlMOS_Rx +
    + +

    MODBUS1_TIM_Moni (Thumb, 26 bytes, Stack size 8 bytes, rs485_modbus_inverter.o(i.MODBUS1_TIM_Moni)) +

    [Stack]

    • Max Depth = 92
    • Call Chain = MODBUS1_TIM_Moni ⇒ MODBUS1_Init ⇒ uf_UART3_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq +
    +
    [Calls]
    • >>   MODBUS1_Init +
    +
    [Called By]
    • >>   TIM3_IRQHandler +
    + +

    MODBUS1_UpdateData (Thumb, 22 bytes, Stack size 0 bytes, rs485_modbus_inverter.o(i.MODBUS1_UpdateData)) +

    [Stack]

    • Max Depth = 36
    • Call Chain = MODBUS1_UpdateData ⇒ MOD_Protocol_Voltronic +
    +
    [Calls]
    • >>   MOD_Protocol_Voltronic +
    • >>   MOD_Protocol_Growatt +
    +
    [Called By]
    • >>   main +
    + +

    MODBUS_AddrAssign_Tx (Thumb, 268 bytes, Stack size 32 bytes, rs485_modbus.o(i.MODBUS_AddrAssign_Tx)) +

    [Stack]

    • Max Depth = 124
    • Call Chain = MODBUS_AddrAssign_Tx ⇒ MODBUS_Init ⇒ uf_UART1_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq +
    +
    [Calls]
    • >>   IO2_OUTSet +
    • >>   IO2_OUTReset +
    • >>   get_random +
    • >>   CRC8_Cal +
    • >>   MODBUS_Init +
    • >>   USART_ITConfig +
    • >>   USART1_SendMulByte +
    • >>   CRC16_Cal +
    +
    [Called By]
    • >>   main +
    + +

    MODBUS_Config_RdSlave_Tx (Thumb, 226 bytes, Stack size 24 bytes, rs485_modbus.o(i.MODBUS_Config_RdSlave_Tx)) +

    [Stack]

    • Max Depth = 116
    • Call Chain = MODBUS_Config_RdSlave_Tx ⇒ MODBUS_Init ⇒ uf_UART1_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq +
    +
    [Calls]
    • >>   MODBUS_Init +
    • >>   USART_ITConfig +
    • >>   USART1_SendMulByte +
    • >>   CRC16_Cal +
    +
    [Called By]
    • >>   main +
    + +

    MODBUS_CtrlMOS_Rx (Thumb, 68 bytes, Stack size 16 bytes, rs485_modbus.o(i.MODBUS_CtrlMOS_Rx)) +

    [Stack]

    • Max Depth = 108
    • Call Chain = MODBUS_CtrlMOS_Rx ⇒ MODBUS_Init ⇒ uf_UART1_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq +
    +
    [Calls]
    • >>   MODBUS_Init +
    • >>   CRC16_Cal +
    • >>   __aeabi_memcpy +
    +
    [Called By]
    • >>   MODBUS_IT_TIMUpdate +
    + +

    MODBUS_F03_Rx (Thumb, 120 bytes, Stack size 16 bytes, rs485_modbus.o(i.MODBUS_F03_Rx)) +

    [Stack]

    • Max Depth = 108
    • Call Chain = MODBUS_F03_Rx ⇒ MODBUS_Init ⇒ uf_UART1_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq +
    +
    [Calls]
    • >>   MODBUS_Init +
    • >>   USART_ITConfig +
    • >>   CRC16_Cal +
    +
    [Called By]
    • >>   MODBUS_IT_TIMUpdate +
    + +

    MODBUS_F10_Rx (Thumb, 294 bytes, Stack size 56 bytes, rs485_modbus.o(i.MODBUS_F10_Rx)) +

    [Stack]

    • Max Depth = 148
    • Call Chain = MODBUS_F10_Rx ⇒ MODBUS_Init ⇒ uf_UART1_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq +
    +
    [Calls]
    • >>   CRC8_Cal +
    • >>   MODBUS_Init +
    • >>   USART_ITConfig +
    • >>   CRC16_Cal +
    • >>   __aeabi_memcpy +
    +
    [Called By]
    • >>   MODBUS_IT_TIMUpdate +
    + +

    MODBUS_Faa_Rx (Thumb, 60 bytes, Stack size 8 bytes, rs485_modbus.o(i.MODBUS_Faa_Rx)) +

    [Stack]

    • Max Depth = 100
    • Call Chain = MODBUS_Faa_Rx ⇒ MODBUS_Init ⇒ uf_UART1_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq +
    +
    [Calls]
    • >>   MODBUS_Init +
    • >>   USART_ITConfig +
    • >>   CRC16_Cal +
    +
    [Called By]
    • >>   MODBUS_IT_TIMUpdate +
    + +

    MODBUS_Fbb_Rx (Thumb, 76 bytes, Stack size 8 bytes, rs485_modbus.o(i.MODBUS_Fbb_Rx)) +

    [Stack]

    • Max Depth = 100
    • Call Chain = MODBUS_Fbb_Rx ⇒ MODBUS_Init ⇒ uf_UART1_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq +
    +
    [Calls]
    • >>   MODBUS_Init +
    • >>   USART_ITConfig +
    • >>   CRC16_Cal +
    +
    [Called By]
    • >>   MODBUS_IT_TIMUpdate +
    + +

    MODBUS_IQ_Transmit (Thumb, 870 bytes, Stack size 112 bytes, rs485_modbus.o(i.MODBUS_IQ_Transmit)) +

    [Stack]

    • Max Depth = 576 + Unknown Stack Size +
    • Call Chain = MODBUS_IQ_Transmit ⇒ MEMORY_UpdateFlash ⇒ FLASH_WrData ⇒ FLASH_ProgramHalfWord ⇒ FLASH_WaitForLastOperation +
    +
    [Calls]
    • >>   MEMORY_UpdateFlash +
    • >>   EEPROM_WrMulByte +
    • >>   EEPROM_RdMulByte +
    • >>   Refresh_ScreenVersion +
    • >>   Refresh_PACK_SN +
    • >>   Refresh_HardwareVersion +
    • >>   uf_CAN1_Init +
    • >>   delay_ms +
    • >>   MEMORY_UpdateAFE +
    • >>   USART_ITConfig +
    • >>   USART1_SendMulByte +
    • >>   BLE_WriteName +
    • >>   CRC16_Cal +
    +
    [Called By]
    • >>   main +
    + +

    MODBUS_IT_Receive (Thumb, 76 bytes, Stack size 8 bytes, rs485_modbus.o(i.MODBUS_IT_Receive)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = MODBUS_IT_Receive +
    +
    [Calls]
    • >>   TIM_Cmd +
    • >>   USART_ReceiveData +
    • >>   TIM_SetCounter +
    +
    [Called By]
    • >>   USART1_IRQHandler +
    + +

    MODBUS_IT_TIMUpdate (Thumb, 764 bytes, Stack size 32 bytes, rs485_modbus.o(i.MODBUS_IT_TIMUpdate)) +

    [Stack]

    • Max Depth = 180
    • Call Chain = MODBUS_IT_TIMUpdate ⇒ MODBUS_F10_Rx ⇒ MODBUS_Init ⇒ uf_UART1_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq +
    +
    [Calls]
    • >>   SLEEP_Refresh +
    • >>   SLEEP2_Refresh +
    • >>   MODBUS_Init +
    • >>   UART1_ReadRecord +
    • >>   UART1_ProtocolSwitch +
    • >>   UART1_ClearRecord +
    • >>   MODBUS_WrIndex_Rx +
    • >>   MODBUS_MASTER_F10_Rx +
    • >>   MODBUS_MASTER_F03_Rx +
    • >>   MODBUS_Fbb_Rx +
    • >>   MODBUS_Faa_Rx +
    • >>   MODBUS_F10_Rx +
    • >>   MODBUS_F03_Rx +
    • >>   MODBUS_CtrlMOS_Rx +
    +
    [Called By]
    • >>   TIM3_IRQHandler +
    + +

    MODBUS_Init (Thumb, 62 bytes, Stack size 0 bytes, rs485_modbus.o(i.MODBUS_Init)) +

    [Stack]

    • Max Depth = 92
    • Call Chain = MODBUS_Init ⇒ uf_UART1_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq +
    +
    [Calls]
    • >>   uf_UART1_Init +
    +
    [Called By]
    • >>   MODBUS_Screen_WrSlaveAddr_Tx +
    • >>   MODBUS_Screen_RdSlave_Tx +
    • >>   MODBUS_MASTER_Polling_Tx +
    • >>   MODBUS_Config_RdSlave_Tx +
    • >>   MODBUS_AddrAssign_Tx +
    • >>   main +
    • >>   MODBUS_TIM_Moni +
    • >>   MODBUS_IT_TIMUpdate +
    • >>   ADDR_Rank_Moni +
    • >>   UART1_ReadRecord +
    • >>   UART1_ClearRecord +
    • >>   MODBUS_WrIndex_Rx +
    • >>   MODBUS_Fbb_Rx +
    • >>   MODBUS_Faa_Rx +
    • >>   MODBUS_F10_Rx +
    • >>   MODBUS_F03_Rx +
    • >>   MODBUS_CtrlMOS_Rx +
    + +

    MODBUS_MASTER_F03_Rx (Thumb, 120 bytes, Stack size 24 bytes, rs485_modbus.o(i.MODBUS_MASTER_F03_Rx)) +

    [Stack]

    • Max Depth = 40
    • Call Chain = MODBUS_MASTER_F03_Rx ⇒ CRC16_Cal +
    +
    [Calls]
    • >>   USART_ITConfig +
    • >>   CRC16_Cal +
    +
    [Called By]
    • >>   MODBUS_IT_TIMUpdate +
    + +

    MODBUS_MASTER_F10_Rx (Thumb, 54 bytes, Stack size 8 bytes, rs485_modbus.o(i.MODBUS_MASTER_F10_Rx)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = MODBUS_MASTER_F10_Rx ⇒ CRC16_Cal +
    +
    [Calls]
    • >>   USART_ITConfig +
    • >>   CRC16_Cal +
    +
    [Called By]
    • >>   MODBUS_IT_TIMUpdate +
    + +

    MODBUS_Poll_Init (Thumb, 148 bytes, Stack size 12 bytes, rs485_modbus.o(i.MODBUS_Poll_Init)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = MODBUS_Poll_Init +
    +
    [Called By]
    • >>   main +
    • >>   MODBUS_TIM_Moni +
    + +

    MODBUS_TIM_Moni (Thumb, 30 bytes, Stack size 8 bytes, rs485_modbus.o(i.MODBUS_TIM_Moni)) +

    [Stack]

    • Max Depth = 100
    • Call Chain = MODBUS_TIM_Moni ⇒ MODBUS_Init ⇒ uf_UART1_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq +
    +
    [Calls]
    • >>   MODBUS_Poll_Init +
    • >>   MODBUS_Init +
    +
    [Called By]
    • >>   TIM3_IRQHandler +
    + +

    MemManage_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f10x_it.o(i.MemManage_Handler)) +

    [Calls]

    • >>   MemManage_Handler +
    +
    [Called By]
    • >>   MemManage_Handler +
    +
    [Address Reference Count : 1]
    • startup_stm32f10x_hd.o(RESET) +
    +

    NMI_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f10x_it.o(i.NMI_Handler)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    NVIC_PriorityGroupConfig (Thumb, 10 bytes, Stack size 0 bytes, misc.o(i.NVIC_PriorityGroupConfig)) +

    [Called By]

    • >>   uf_EXTI_Init +
    + +

    PCHG_Off (Thumb, 8 bytes, Stack size 0 bytes, gpio.o(i.PCHG_Off)) +

    [Calls]

    • >>   GPIO_ResetBits +
    +
    [Called By]
    • >>   PCHG_StartCtrl +
    • >>   PCHG_Ctrl +
    + +

    PendSV_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f10x_it.o(i.PendSV_Handler)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    SPI2_Error (Thumb, 4 bytes, Stack size 0 bytes, spi.o(i.SPI2_Error)) +

    [Stack]

    • Max Depth = 60
    • Call Chain = SPI2_Error ⇒ uf_SPI2_Init ⇒ GPIO_Init +
    +
    [Calls]
    • >>   uf_SPI2_Init +
    +
    [Called By]
    • >>   AFE_Read +
    + +

    SVC_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f10x_it.o(i.SVC_Handler)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    MODBUS_MASTER_Polling_Tx (Thumb, 700 bytes, Stack size 32 bytes, rs485_modbus.o(i.MODBUS_MASTER_Polling_Tx)) +

    [Stack]

    • Max Depth = 124
    • Call Chain = MODBUS_MASTER_Polling_Tx ⇒ MODBUS_Init ⇒ uf_UART1_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq +
    +
    [Calls]
    • >>   MODBUS_Init +
    • >>   USART_ITConfig +
    • >>   USART1_SendMulByte +
    • >>   CRC16_Cal +
    +
    [Called By]
    • >>   main +
    + +

    MODBUS_Screen_RdSlave_Tx (Thumb, 216 bytes, Stack size 24 bytes, rs485_modbus.o(i.MODBUS_Screen_RdSlave_Tx)) +

    [Stack]

    • Max Depth = 116
    • Call Chain = MODBUS_Screen_RdSlave_Tx ⇒ MODBUS_Init ⇒ uf_UART1_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq +
    +
    [Calls]
    • >>   MODBUS_Init +
    • >>   USART_ITConfig +
    • >>   USART1_SendMulByte +
    • >>   CRC16_Cal +
    +
    [Called By]
    • >>   main +
    + +

    MODBUS_Screen_WrSlaveAddr_Tx (Thumb, 170 bytes, Stack size 32 bytes, rs485_modbus.o(i.MODBUS_Screen_WrSlaveAddr_Tx)) +

    [Stack]

    • Max Depth = 124
    • Call Chain = MODBUS_Screen_WrSlaveAddr_Tx ⇒ MODBUS_Init ⇒ uf_UART1_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq +
    +
    [Calls]
    • >>   CRC8_Cal +
    • >>   MODBUS_Init +
    • >>   USART_ITConfig +
    • >>   USART1_SendMulByte +
    • >>   CRC16_Cal +
    +
    [Called By]
    • >>   main +
    + +

    MODBUS_WrIndex_Rx (Thumb, 88 bytes, Stack size 8 bytes, rs485_modbus.o(i.MODBUS_WrIndex_Rx)) +

    [Stack]

    • Max Depth = 100
    • Call Chain = MODBUS_WrIndex_Rx ⇒ MODBUS_Init ⇒ uf_UART1_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq +
    +
    [Calls]
    • >>   EEPROM_WrMulByte +
    • >>   delay_ms +
    • >>   MODBUS_Init +
    • >>   CRC16_Cal +
    +
    [Called By]
    • >>   MODBUS_IT_TIMUpdate +
    + +

    MODBUS_WrIndex_Tx (Thumb, 78 bytes, Stack size 8 bytes, rs485_modbus.o(i.MODBUS_WrIndex_Tx)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = MODBUS_WrIndex_Tx ⇒ USART1_SendMulByte +
    +
    [Calls]
    • >>   USART_ITConfig +
    • >>   USART1_SendMulByte +
    • >>   CRC16_Cal +
    +
    [Called By]
    • >>   main +
    + +

    MOD_Protocol_Growatt (Thumb, 708 bytes, Stack size 20 bytes, protocolswitch_p1.o(i.MOD_Protocol_Growatt)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = MOD_Protocol_Growatt +
    +
    [Called By]
    • >>   MODBUS1_UpdateData +
    + +

    MOD_Protocol_Voltronic (Thumb, 840 bytes, Stack size 36 bytes, protocolswitch_p2.o(i.MOD_Protocol_Voltronic)) +

    [Stack]

    • Max Depth = 36
    • Call Chain = MOD_Protocol_Voltronic +
    +
    [Called By]
    • >>   MODBUS1_UpdateData +
    + +

    NVIC_Init (Thumb, 94 bytes, Stack size 16 bytes, misc.o(i.NVIC_Init)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = NVIC_Init +
    +
    [Called By]
    • >>   uf_TIM3_Init +
    • >>   uf_CAN1_Init +
    • >>   uf_UART4_Init +
    • >>   uf_UART3_Init +
    • >>   uf_UART2_Init +
    • >>   uf_UART1_Init +
    + +

    OCC2_Ctrl (Thumb, 66 bytes, Stack size 16 bytes, afe_sh3673520.o(i.OCC2_Ctrl)) +

    [Stack]

    • Max Depth = 128
    • Call Chain = OCC2_Ctrl ⇒ AFE_Read ⇒ AFE_ReadMulByte ⇒ delay_us +
    +
    [Calls]
    • >>   AFE_Write +
    • >>   AFE_Read +
    +
    [Called By]
    • >>   TIM3_IRQHandler +
    + +

    OCC2_TIM_Moni (Thumb, 64 bytes, Stack size 16 bytes, afe_sh3673520.o(i.OCC2_TIM_Moni)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = OCC2_TIM_Moni +
    +
    [Called By]
    • >>   TIM3_IRQHandler +
    + +

    OCV_CaliSOC (Thumb, 420 bytes, Stack size 32 bytes, ocv.o(i.OCV_CaliSOC)) +

    [Stack]

    • Max Depth = 100
    • Call Chain = OCV_CaliSOC ⇒ EEPROM_RdMulByte ⇒ I2C_GetFlagStatus +
    +
    [Calls]
    • >>   RTC_GetCounter +
    • >>   EEPROM_WrMulByte +
    • >>   EEPROM_RdMulByte +
    • >>   delay_ms +
    • >>   OCV_CaliSoc_dp +
    • >>   OCV_CaliSOC_DataWr +
    +
    [Called By]
    • >>   main +
    + +

    OCV_CaliSOC_DataWr (Thumb, 168 bytes, Stack size 12 bytes, ocv.o(i.OCV_CaliSOC_DataWr)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = OCV_CaliSOC_DataWr +
    +
    [Called By]
    • >>   OCV_CaliSOC +
    • >>   InitGasGauge +
    + +

    OCV_CaliSoc_dp (Thumb, 172 bytes, Stack size 8 bytes, ocv.o(i.OCV_CaliSoc_dp)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = OCV_CaliSoc_dp +
    +
    [Called By]
    • >>   OCV_CaliSOC +
    • >>   InitGasGauge +
    + +

    PCHG_Ctrl (Thumb, 140 bytes, Stack size 16 bytes, gpio.o(i.PCHG_Ctrl)) +

    [Stack]

    • Max Depth = 112
    • Call Chain = PCHG_Ctrl ⇒ CTRL_Off ⇒ AFE_Write ⇒ AFE_WriteOneByte ⇒ delay_us +
    +
    [Calls]
    • >>   delay_ms +
    • >>   LOAD_VOL +
    • >>   CTRL_On +
    • >>   CTRL_Off +
    • >>   PCHG_On +
    • >>   PCHG_Off +
    +
    [Called By]
    • >>   AFE_Ctrl +
    + +

    PCHG_On (Thumb, 8 bytes, Stack size 0 bytes, gpio.o(i.PCHG_On)) +

    [Calls]

    • >>   GPIO_SetBits +
    +
    [Called By]
    • >>   PCHG_StartCtrl +
    • >>   PCHG_Ctrl +
    + +

    PCHG_StartCtrl (Thumb, 136 bytes, Stack size 16 bytes, gpio.o(i.PCHG_StartCtrl)) +

    [Stack]

    • Max Depth = 48
    • Call Chain = PCHG_StartCtrl ⇒ LOAD_VOL ⇒ ADC_GetVal ⇒ ADC_RegularChannelConfig +
    +
    [Calls]
    • >>   delay_ms +
    • >>   LOAD_VOL +
    • >>   CTRL_On +
    • >>   PCHG_On +
    • >>   PCHG_Off +
    +
    [Called By]
    • >>   main +
    + +

    PWM_Set_Duty_Percent (Thumb, 54 bytes, Stack size 8 bytes, pwm.o(i.PWM_Set_Duty_Percent)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = PWM_Set_Duty_Percent ⇒ __aeabi_fmul +
    +
    [Calls]
    • >>   TIM_SetCompare4 +
    • >>   __aeabi_fmul +
    • >>   __aeabi_f2uiz +
    • >>   __aeabi_fdiv +
    • >>   __aeabi_fadd +
    +
    [Called By]
    • >>   CHG_LIMIT_PWM_Adjust +
    • >>   CHG_LIMIT_On +
    • >>   CHG_LIMIT_Off +
    + +

    PWR_BackupAccessCmd (Thumb, 6 bytes, Stack size 0 bytes, stm32f10x_pwr.o(i.PWR_BackupAccessCmd)) +

    [Called By]

    • >>   uf_RTC_Update +
    • >>   uf_RTC_Init +
    • >>   RTC_Set +
    + +

    ParaChange (Thumb, 750 bytes, Stack size 48 bytes, global.o(i.ParaChange)) +

    [Stack]

    • Max Depth = 512
    • Call Chain = ParaChange ⇒ MEMORY_UpdateFlash ⇒ FLASH_WrData ⇒ FLASH_ProgramHalfWord ⇒ FLASH_WaitForLastOperation +
    +
    [Calls]
    • >>   MEMORY_UpdateFlash +
    • >>   EEPROM_WrMulByte +
    • >>   EEPROM_RdMulByte +
    • >>   SLEEP_Refresh +
    • >>   SLEEP2_Refresh +
    • >>   delay_ms +
    +
    [Called By]
    • >>   main +
    + +

    RCC_ADCCLKConfig (Thumb, 14 bytes, Stack size 0 bytes, stm32f10x_rcc.o(i.RCC_ADCCLKConfig)) +

    [Called By]

    • >>   uf_ADC_Init +
    + +

    RCC_APB1PeriphClockCmd (Thumb, 18 bytes, Stack size 0 bytes, stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd)) +

    [Called By]

    • >>   uf_TIM3_Init +
    • >>   uf_SPI2_Init +
    • >>   uf_RTC_Update +
    • >>   uf_RTC_Init +
    • >>   uf_I2C1_Init +
    • >>   uf_CAN1_Init +
    • >>   TIM4_PWM_Init +
    • >>   RTC_Set +
    • >>   uf_UART4_Init +
    • >>   uf_UART3_Init +
    • >>   uf_UART2_Init +
    + +

    RCC_APB1PeriphResetCmd (Thumb, 18 bytes, Stack size 0 bytes, stm32f10x_rcc.o(i.RCC_APB1PeriphResetCmd)) +

    [Called By]

    • >>   CAN_DeInit +
    • >>   SPI_I2S_DeInit +
    • >>   I2C_DeInit +
    + +

    RCC_APB2PeriphClockCmd (Thumb, 18 bytes, Stack size 0 bytes, stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd)) +

    [Called By]

    • >>   uf_SPI2_Init +
    • >>   uf_I2C1_Init +
    • >>   uf_GPIO_Init +
    • >>   uf_CAN1_Init +
    • >>   uf_ADC_Init +
    • >>   BLE_IO_Init +
    • >>   TIM4_PWM_Init +
    • >>   uf_UART4_Init +
    • >>   uf_UART3_Init +
    • >>   uf_UART2_Init +
    • >>   uf_UART1_Init +
    • >>   CHG_LIMIT_Init +
    + +

    RCC_APB2PeriphResetCmd (Thumb, 18 bytes, Stack size 0 bytes, stm32f10x_rcc.o(i.RCC_APB2PeriphResetCmd)) +

    [Called By]

    • >>   ADC_DeInit +
    • >>   SPI_I2S_DeInit +
    + +

    RCC_BackupResetCmd (Thumb, 6 bytes, Stack size 0 bytes, stm32f10x_rcc.o(i.RCC_BackupResetCmd)) +

    [Called By]

    • >>   BKP_DeInit +
    + +

    RCC_GetClocksFreq (Thumb, 128 bytes, Stack size 12 bytes, stm32f10x_rcc.o(i.RCC_GetClocksFreq)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = RCC_GetClocksFreq +
    +
    [Called By]
    • >>   I2C_Init +
    • >>   USART_Init +
    + +

    RCC_GetFlagStatus (Thumb, 44 bytes, Stack size 0 bytes, stm32f10x_rcc.o(i.RCC_GetFlagStatus)) +

    [Called By]

    • >>   uf_RTC_Update +
    • >>   uf_RTC_Init +
    + +

    RCC_LSEConfig (Thumb, 28 bytes, Stack size 0 bytes, stm32f10x_rcc.o(i.RCC_LSEConfig)) +

    [Called By]

    • >>   uf_RTC_Update +
    • >>   uf_RTC_Init +
    + +

    RCC_RTCCLKCmd (Thumb, 6 bytes, Stack size 0 bytes, stm32f10x_rcc.o(i.RCC_RTCCLKCmd)) +

    [Called By]

    • >>   uf_RTC_Update +
    • >>   uf_RTC_Init +
    + +

    RCC_RTCCLKConfig (Thumb, 10 bytes, Stack size 0 bytes, stm32f10x_rcc.o(i.RCC_RTCCLKConfig)) +

    [Called By]

    • >>   uf_RTC_Update +
    • >>   uf_RTC_Init +
    + +

    RTC_BackUp (Thumb, 144 bytes, Stack size 24 bytes, rtc.o(i.RTC_BackUp)) +

    [Stack]

    • Max Depth = 76
    • Call Chain = RTC_BackUp ⇒ EEPROM_WrMulByte ⇒ I2C_GetFlagStatus +
    +
    [Calls]
    • >>   EEPROM_WrMulByte +
    • >>   delay_ms +
    +
    [Called By]
    • >>   main +
    + +

    RTC_EnterConfigMode (Thumb, 12 bytes, Stack size 0 bytes, stm32f10x_rtc.o(i.RTC_EnterConfigMode)) +

    [Called By]

    • >>   uf_RTC_Update +
    • >>   uf_RTC_Init +
    • >>   RTC_SetPrescaler +
    • >>   RTC_SetCounter +
    + +

    RTC_ExitConfigMode (Thumb, 12 bytes, Stack size 0 bytes, stm32f10x_rtc.o(i.RTC_ExitConfigMode)) +

    [Called By]

    • >>   uf_RTC_Update +
    • >>   uf_RTC_Init +
    • >>   RTC_SetPrescaler +
    • >>   RTC_SetCounter +
    + +

    RTC_GetCounter (Thumb, 28 bytes, Stack size 0 bytes, stm32f10x_rtc.o(i.RTC_GetCounter)) +

    [Called By]

    • >>   get_random +
    • >>   SLEEP_Refresh +
    • >>   SLEEP2_Refresh +
    • >>   uf_RTC_Init +
    • >>   Screen_IT_Update +
    • >>   RTC_Get +
    • >>   OCV_CaliSOC +
    • >>   Cali_FCC_Moni +
    • >>   BLE_PUTSRVC +
    + +

    RTC_GetSynchro (Thumb, 46 bytes, Stack size 16 bytes, rtc.o(i.RTC_GetSynchro)) +

    [Stack]

    • Max Depth = 40
    • Call Chain = RTC_GetSynchro ⇒ delay_ms +
    +
    [Calls]
    • >>   delay_ms +
    +
    [Called By]
    • >>   uf_RTC_Init +
    + +

    RTC_Get_Week (Thumb, 142 bytes, Stack size 16 bytes, rtc.o(i.RTC_Get_Week)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = RTC_Get_Week +
    +
    [Called By]
    • >>   RTC_Get +
    + +

    RTC_WaitForLastTask (Thumb, 10 bytes, Stack size 0 bytes, stm32f10x_rtc.o(i.RTC_WaitForLastTask)) +

    [Called By]

    • >>   uf_RTC_Update +
    • >>   uf_RTC_Init +
    • >>   RTC_Set +
    + +

    SPI_I2S_ReceiveData (Thumb, 4 bytes, Stack size 0 bytes, stm32f10x_spi.o(i.SPI_I2S_ReceiveData)) +

    [Called By]

    • >>   AFE_WriteOneByte +
    • >>   AFE_Reset +
    • >>   AFE_ReadMulByte +
    + +

    RTC_Get (Thumb, 926 bytes, Stack size 40 bytes, rtc.o(i.RTC_Get)) +

    [Stack]

    • Max Depth = 92
    • Call Chain = RTC_Get ⇒ EEPROM_WrMulByte ⇒ I2C_GetFlagStatus +
    +
    [Calls]
    • >>   RTC_GetCounter +
    • >>   EEPROM_WrMulByte +
    • >>   delay_ms +
    • >>   RTC_Get_Week +
    • >>   Is_Leap_Year +
    +
    [Called By]
    • >>   main +
    + +

    RTC_ITConfig (Thumb, 18 bytes, Stack size 0 bytes, stm32f10x_rtc.o(i.RTC_ITConfig)) +

    [Called By]

    • >>   uf_RTC_Update +
    • >>   uf_RTC_Init +
    + +

    RTC_Set (Thumb, 288 bytes, Stack size 40 bytes, rtc.o(i.RTC_Set)) +

    [Stack]

    • Max Depth = 44
    • Call Chain = RTC_Set ⇒ RTC_SetCounter +
    +
    [Calls]
    • >>   RTC_WaitForLastTask +
    • >>   RTC_SetCounter +
    • >>   PWR_BackupAccessCmd +
    • >>   Is_Leap_Year +
    • >>   RCC_APB1PeriphClockCmd +
    +
    [Called By]
    • >>   uf_RTC_Update +
    • >>   uf_RTC_Init +
    + +

    RTC_SetCounter (Thumb, 26 bytes, Stack size 4 bytes, stm32f10x_rtc.o(i.RTC_SetCounter)) +

    [Stack]

    • Max Depth = 4
    • Call Chain = RTC_SetCounter +
    +
    [Calls]
    • >>   RTC_ExitConfigMode +
    • >>   RTC_EnterConfigMode +
    +
    [Called By]
    • >>   RTC_Set +
    + +

    RTC_SetPrescaler (Thumb, 28 bytes, Stack size 4 bytes, stm32f10x_rtc.o(i.RTC_SetPrescaler)) +

    [Stack]

    • Max Depth = 4
    • Call Chain = RTC_SetPrescaler +
    +
    [Calls]
    • >>   RTC_ExitConfigMode +
    • >>   RTC_EnterConfigMode +
    +
    [Called By]
    • >>   uf_RTC_Update +
    • >>   uf_RTC_Init +
    + +

    RTC_WaitForSynchro (Thumb, 18 bytes, Stack size 0 bytes, stm32f10x_rtc.o(i.RTC_WaitForSynchro)) +

    [Called By]

    • >>   uf_RTC_Update +
    • >>   uf_RTC_Init +
    + +

    Refresh_BMS_SN (Thumb, 30 bytes, Stack size 16 bytes, global.o(i.Refresh_BMS_SN)) +

    [Stack]

    • Max Depth = 152 + Unknown Stack Size +
    • Call Chain = Refresh_BMS_SN ⇒ __2sprintf ⇒ _printf_char_common ⇒ __printf +
    +
    [Calls]
    • >>   __2sprintf +
    +
    [Called By]
    • >>   uf_GLOBAL_Init +
    • >>   MODBUS1_IQ_Transmit +
    + +

    Refresh_FirmwareVersion (Thumb, 36 bytes, Stack size 16 bytes, global.o(i.Refresh_FirmwareVersion)) +

    [Stack]

    • Max Depth = 152 + Unknown Stack Size +
    • Call Chain = Refresh_FirmwareVersion ⇒ __2sprintf ⇒ _printf_char_common ⇒ __printf +
    +
    [Calls]
    • >>   __2sprintf +
    +
    [Called By]
    • >>   uf_GLOBAL_Init +
    + +

    Refresh_HardwareVersion (Thumb, 32 bytes, Stack size 8 bytes, global.o(i.Refresh_HardwareVersion)) +

    [Stack]

    • Max Depth = 144 + Unknown Stack Size +
    • Call Chain = Refresh_HardwareVersion ⇒ __2sprintf ⇒ _printf_char_common ⇒ __printf +
    +
    [Calls]
    • >>   __2sprintf +
    +
    [Called By]
    • >>   uf_GLOBAL_Init +
    • >>   MODBUS_IQ_Transmit +
    • >>   MODBUS1_IQ_Transmit +
    + +

    Refresh_PACK_SN (Thumb, 34 bytes, Stack size 16 bytes, global.o(i.Refresh_PACK_SN)) +

    [Stack]

    • Max Depth = 152 + Unknown Stack Size +
    • Call Chain = Refresh_PACK_SN ⇒ __2sprintf ⇒ _printf_char_common ⇒ __printf +
    +
    [Calls]
    • >>   __2sprintf +
    +
    [Called By]
    • >>   uf_GLOBAL_Init +
    • >>   MODBUS_IQ_Transmit +
    • >>   MODBUS1_IQ_Transmit +
    + +

    Refresh_ScreenVersion (Thumb, 102 bytes, Stack size 8 bytes, global.o(i.Refresh_ScreenVersion)) +

    [Stack]

    • Max Depth = 144 + Unknown Stack Size +
    • Call Chain = Refresh_ScreenVersion ⇒ __2sprintf ⇒ _printf_char_common ⇒ __printf +
    +
    [Calls]
    • >>   __2sprintf +
    +
    [Called By]
    • >>   uf_GLOBAL_Init +
    • >>   MODBUS_IQ_Transmit +
    • >>   MODBUS1_IQ_Transmit +
    + +

    Release_CurAlarm (Thumb, 228 bytes, Stack size 20 bytes, status.o(i.Release_CurAlarm)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = Release_CurAlarm +
    +
    [Called By]
    • >>   MCU_TemperaProcess +
    + +

    Release_CurProtect (Thumb, 214 bytes, Stack size 16 bytes, status.o(i.Release_CurProtect)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = Release_CurProtect +
    +
    [Called By]
    • >>   MCU_TemperaProcess +
    + +

    Release_OVAlarm (Thumb, 284 bytes, Stack size 32 bytes, status.o(i.Release_OVAlarm)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = Release_OVAlarm +
    +
    [Called By]
    • >>   AFE_VoltageProcess +
    + +

    Release_OVProtect (Thumb, 260 bytes, Stack size 32 bytes, status.o(i.Release_OVProtect)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = Release_OVProtect +
    +
    [Called By]
    • >>   AFE_VoltageProcess +
    + +

    Release_UVAlarm (Thumb, 188 bytes, Stack size 20 bytes, status.o(i.Release_UVAlarm)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = Release_UVAlarm +
    +
    [Called By]
    • >>   AFE_VoltageProcess +
    + +

    Release_UVProtect (Thumb, 182 bytes, Stack size 20 bytes, status.o(i.Release_UVProtect)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = Release_UVProtect +
    +
    [Called By]
    • >>   AFE_VoltageProcess +
    + +

    Release_afeTAlarm (Thumb, 140 bytes, Stack size 20 bytes, status.o(i.Release_afeTAlarm)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = Release_afeTAlarm +
    +
    [Called By]
    • >>   AFE_TemperaProcess +
    + +

    Release_afeTProtect (Thumb, 140 bytes, Stack size 20 bytes, status.o(i.Release_afeTProtect)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = Release_afeTProtect +
    +
    [Called By]
    • >>   AFE_TemperaProcess +
    + +

    Release_amTAlarm (Thumb, 238 bytes, Stack size 20 bytes, status.o(i.Release_amTAlarm)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = Release_amTAlarm +
    +
    [Called By]
    • >>   AFE_TemperaProcess +
    + +

    Release_amTProtect (Thumb, 238 bytes, Stack size 20 bytes, status.o(i.Release_amTProtect)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = Release_amTProtect +
    +
    [Called By]
    • >>   AFE_TemperaProcess +
    + +

    Release_mcuTAlarm (Thumb, 256 bytes, Stack size 20 bytes, status.o(i.Release_mcuTAlarm)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = Release_mcuTAlarm +
    +
    [Called By]
    • >>   MCU_TemperaProcess +
    + +

    Release_mcuTProtect (Thumb, 256 bytes, Stack size 20 bytes, status.o(i.Release_mcuTProtect)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = Release_mcuTProtect +
    +
    [Called By]
    • >>   MCU_TemperaProcess +
    + +

    SCR_ClearAlarm (Thumb, 84 bytes, Stack size 8 bytes, screen.o(i.SCR_ClearAlarm)) +

    [Stack]

    • Max Depth = 168 + Unknown Stack Size +
    • Call Chain = SCR_ClearAlarm ⇒ USART2_printf ⇒ vsnprintf ⇒ _printf_char_common ⇒ __printf +
    +
    [Calls]
    • >>   USART2_printf +
    +
    [Called By]
    • >>   SCR_Send_Slave_BasicInfo +
    • >>   SCR_Send_Self_BasicInfo +
    + +

    SCR_DispProcotol (Thumb, 454 bytes, Stack size 16 bytes, screen.o(i.SCR_DispProcotol)) +

    [Stack]

    • Max Depth = 176 + Unknown Stack Size +
    • Call Chain = SCR_DispProcotol ⇒ USART2_printf ⇒ vsnprintf ⇒ _printf_char_common ⇒ __printf +
    +
    [Calls]
    • >>   EEPROM_RdMulByte +
    • >>   USART2_printf +
    +
    [Called By]
    • >>   Screen_IQ_Transmit +
    + +

    SCR_JumpToAlarm (Thumb, 18 bytes, Stack size 8 bytes, screen.o(i.SCR_JumpToAlarm)) +

    [Stack]

    • Max Depth = 168 + Unknown Stack Size +
    • Call Chain = SCR_JumpToAlarm ⇒ USART2_printf ⇒ vsnprintf ⇒ _printf_char_common ⇒ __printf +
    +
    [Calls]
    • >>   USART2_printf +
    +
    [Called By]
    • >>   SCR_Send_Slave_BasicInfo +
    • >>   SCR_Send_Self_BasicInfo +
    + +

    SCR_Send_Record (Thumb, 542 bytes, Stack size 24 bytes, screen.o(i.SCR_Send_Record)) +

    [Stack]

    • Max Depth = 184 + Unknown Stack Size +
    • Call Chain = SCR_Send_Record ⇒ USART2_printf ⇒ vsnprintf ⇒ _printf_char_common ⇒ __printf +
    +
    [Calls]
    • >>   USART2_printf +
    • >>   __aeabi_memclr +
    • >>   __aeabi_memcpy +
    +
    [Called By]
    • >>   SCR_Send_RecordInfo +
    + +

    SCR_Send_RecordInfo (Thumb, 366 bytes, Stack size 96 bytes, screen.o(i.SCR_Send_RecordInfo)) +

    [Stack]

    • Max Depth = 280 + Unknown Stack Size +
    • Call Chain = SCR_Send_RecordInfo ⇒ SCR_Send_Record ⇒ USART2_printf ⇒ vsnprintf ⇒ _printf_char_common ⇒ __printf +
    +
    [Calls]
    • >>   EEPROM_RdMulByte +
    • >>   delay_ms +
    • >>   USART2_printf +
    • >>   Set_Row_Hide +
    • >>   Send_Record_Blank +
    • >>   SCR_Send_Record +
    • >>   __2sprintf +
    +
    [Called By]
    • >>   Screen_IQ_Transmit +
    + +

    SCR_Send_Self_BasicInfo (Thumb, 1786 bytes, Stack size 32 bytes, screen.o(i.SCR_Send_Self_BasicInfo)) +

    [Stack]

    • Max Depth = 200 + Unknown Stack Size +
    • Call Chain = SCR_Send_Self_BasicInfo ⇒ SCR_ShowAlarm ⇒ USART2_printf ⇒ vsnprintf ⇒ _printf_char_common ⇒ __printf +
    +
    [Calls]
    • >>   USART2_printf +
    • >>   SCR_ShowAlarm +
    • >>   SCR_JumpToAlarm +
    • >>   SCR_ClearAlarm +
    • >>   __aeabi_ui2f +
    • >>   __aeabi_i2f +
    • >>   __aeabi_fdiv +
    • >>   __aeabi_f2d +
    • >>   __aeabi_ui2d +
    +
    [Called By]
    • >>   Screen_IQ_Transmit +
    + +

    SCR_Send_Slave_BasicInfo (Thumb, 1968 bytes, Stack size 32 bytes, screen.o(i.SCR_Send_Slave_BasicInfo)) +

    [Stack]

    • Max Depth = 200 + Unknown Stack Size +
    • Call Chain = SCR_Send_Slave_BasicInfo ⇒ SCR_ShowAlarm_Slave ⇒ USART2_printf ⇒ vsnprintf ⇒ _printf_char_common ⇒ __printf +
    +
    [Calls]
    • >>   USART2_printf +
    • >>   SCR_ShowAlarm_Slave +
    • >>   SCR_JumpToAlarm +
    • >>   SCR_ClearAlarm +
    • >>   __aeabi_ui2f +
    • >>   __aeabi_i2f +
    • >>   __aeabi_fdiv +
    • >>   __aeabi_f2d +
    • >>   __aeabi_ui2d +
    +
    [Called By]
    • >>   Screen_IQ_Transmit +
    + +

    SCR_Send_Slave_RecordBank (Thumb, 60 bytes, Stack size 8 bytes, screen.o(i.SCR_Send_Slave_RecordBank)) +

    [Stack]

    • Max Depth = 176 + Unknown Stack Size +
    • Call Chain = SCR_Send_Slave_RecordBank ⇒ Send_Record_Blank ⇒ USART2_printf ⇒ vsnprintf ⇒ _printf_char_common ⇒ __printf +
    +
    [Calls]
    • >>   USART2_printf +
    • >>   Set_Row_Hide +
    • >>   Send_Record_Blank +
    +
    [Called By]
    • >>   Screen_IQ_Transmit +
    + +

    SCR_Send_Time (Thumb, 42 bytes, Stack size 48 bytes, screen.o(i.SCR_Send_Time)) +

    [Stack]

    • Max Depth = 208 + Unknown Stack Size +
    • Call Chain = SCR_Send_Time ⇒ USART2_printf ⇒ vsnprintf ⇒ _printf_char_common ⇒ __printf +
    +
    [Calls]
    • >>   USART2_printf +
    • >>   __2sprintf +
    +
    [Called By]
    • >>   Screen_IQ_Transmit +
    + +

    SCR_Send_TotalInfo (Thumb, 452 bytes, Stack size 48 bytes, screen.o(i.SCR_Send_TotalInfo)) +

    [Stack]

    • Max Depth = 208 + Unknown Stack Size +
    • Call Chain = SCR_Send_TotalInfo ⇒ USART2_printf ⇒ vsnprintf ⇒ _printf_char_common ⇒ __printf +
    +
    [Calls]
    • >>   USART2_printf +
    • >>   __aeabi_ui2f +
    • >>   __aeabi_i2f +
    • >>   __aeabi_fdiv +
    • >>   __aeabi_f2d +
    • >>   __aeabi_dmul +
    • >>   __aeabi_ui2d +
    • >>   __aeabi_d2uiz +
    • >>   __aeabi_ddiv +
    +
    [Called By]
    • >>   Screen_IQ_Transmit +
    + +

    SCR_Send_VER (Thumb, 58 bytes, Stack size 8 bytes, screen.o(i.SCR_Send_VER)) +

    [Stack]

    • Max Depth = 168 + Unknown Stack Size +
    • Call Chain = SCR_Send_VER ⇒ USART2_printf ⇒ vsnprintf ⇒ _printf_char_common ⇒ __printf +
    +
    [Calls]
    • >>   USART2_printf +
    +
    [Called By]
    • >>   Screen_IQ_Transmit +
    + +

    SCR_ShowAlarm (Thumb, 326 bytes, Stack size 8 bytes, screen.o(i.SCR_ShowAlarm)) +

    [Stack]

    • Max Depth = 168 + Unknown Stack Size +
    • Call Chain = SCR_ShowAlarm ⇒ USART2_printf ⇒ vsnprintf ⇒ _printf_char_common ⇒ __printf +
    +
    [Calls]
    • >>   USART2_printf +
    +
    [Called By]
    • >>   SCR_Send_Self_BasicInfo +
    + +

    SCR_ShowAlarm_Slave (Thumb, 314 bytes, Stack size 8 bytes, screen.o(i.SCR_ShowAlarm_Slave)) +

    [Stack]

    • Max Depth = 168 + Unknown Stack Size +
    • Call Chain = SCR_ShowAlarm_Slave ⇒ USART2_printf ⇒ vsnprintf ⇒ _printf_char_common ⇒ __printf +
    +
    [Calls]
    • >>   USART2_printf +
    +
    [Called By]
    • >>   SCR_Send_Slave_BasicInfo +
    + +

    SLEEP2_Refresh (Thumb, 118 bytes, Stack size 8 bytes, global.o(i.SLEEP2_Refresh)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = SLEEP2_Refresh +
    +
    [Calls]
    • >>   RTC_GetCounter +
    +
    [Called By]
    • >>   Screen_IT_Update +
    • >>   ParaChange +
    • >>   AFE_CurrentProcess +
    • >>   USB_LP_CAN1_RX0_IRQHandler +
    • >>   MODBUS_IT_TIMUpdate +
    • >>   MODBUS1_IT_TIMUpdate +
    + +

    SLEEP2_TIM_Moni (Thumb, 124 bytes, Stack size 8 bytes, global.o(i.SLEEP2_TIM_Moni)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = SLEEP2_TIM_Moni +
    +
    [Called By]
    • >>   TIM3_IRQHandler +
    + +

    SLEEP_Refresh (Thumb, 40 bytes, Stack size 8 bytes, global.o(i.SLEEP_Refresh)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = SLEEP_Refresh +
    +
    [Calls]
    • >>   RTC_GetCounter +
    +
    [Called By]
    • >>   Screen_IT_Update +
    • >>   ParaChange +
    • >>   AFE_CurrentProcess +
    • >>   USB_LP_CAN1_RX0_IRQHandler +
    • >>   MODBUS_IT_TIMUpdate +
    • >>   MODBUS1_IT_TIMUpdate +
    + +

    SLEEP_TIM_Moni (Thumb, 44 bytes, Stack size 0 bytes, global.o(i.SLEEP_TIM_Moni)) +

    [Called By]

    • >>   TIM3_IRQHandler +
    + +

    SOE_BkData (Thumb, 1072 bytes, Stack size 168 bytes, soe.o(i.SOE_BkData)) +

    [Stack]

    • Max Depth = 236
    • Call Chain = SOE_BkData ⇒ EEPROM_RdMulByte ⇒ I2C_GetFlagStatus +
    +
    [Calls]
    • >>   EEPROM_WrMulByte +
    • >>   EEPROM_RdMulByte +
    • >>   delay_ms +
    +
    [Called By]
    • >>   AFE_ProtectProcess +
    + +

    SPI_Cmd (Thumb, 20 bytes, Stack size 0 bytes, stm32f10x_spi.o(i.SPI_Cmd)) +

    [Called By]

    • >>   uf_SPI2_Init +
    + +

    SPI_I2S_DeInit (Thumb, 72 bytes, Stack size 8 bytes, stm32f10x_spi.o(i.SPI_I2S_DeInit)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = SPI_I2S_DeInit +
    +
    [Calls]
    • >>   RCC_APB2PeriphResetCmd +
    • >>   RCC_APB1PeriphResetCmd +
    +
    [Called By]
    • >>   uf_SPI2_Init +
    + +

    SPI_I2S_GetFlagStatus (Thumb, 14 bytes, Stack size 0 bytes, stm32f10x_spi.o(i.SPI_I2S_GetFlagStatus)) +

    [Called By]

    • >>   AFE_WriteOneByte +
    • >>   AFE_Reset +
    • >>   AFE_ReadMulByte +
    + +

    SPI_I2S_SendData (Thumb, 4 bytes, Stack size 0 bytes, stm32f10x_spi.o(i.SPI_I2S_SendData)) +

    [Called By]

    • >>   AFE_WriteOneByte +
    • >>   AFE_Reset +
    • >>   AFE_ReadMulByte +
    + +

    SPI_Init (Thumb, 56 bytes, Stack size 12 bytes, stm32f10x_spi.o(i.SPI_Init)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = SPI_Init +
    +
    [Called By]
    • >>   uf_SPI2_Init +
    + +

    Screen_ClearBuf (Thumb, 14 bytes, Stack size 0 bytes, screen.o(i.Screen_ClearBuf)) +

    [Calls]

    • >>   __aeabi_memclr +
    +
    [Called By]
    • >>   Screen_Init +
    • >>   Screen_IT_Update +
    • >>   Screen_IT_Receive +
    + +

    Screen_IQ_Transmit (Thumb, 1902 bytes, Stack size 72 bytes, screen.o(i.Screen_IQ_Transmit)) +

    [Stack]

    • Max Depth = 536 + Unknown Stack Size +
    • Call Chain = Screen_IQ_Transmit ⇒ MEMORY_UpdateFlash ⇒ FLASH_WrData ⇒ FLASH_ProgramHalfWord ⇒ FLASH_WaitForLastOperation +
    +
    [Calls]
    • >>   MEMORY_UpdateFlash +
    • >>   CRC8_Cal +
    • >>   MEMORY_UpdateAFE +
    • >>   USART2_printf +
    • >>   SCR_Send_VER +
    • >>   SCR_Send_TotalInfo +
    • >>   SCR_Send_Time +
    • >>   SCR_Send_Slave_RecordBank +
    • >>   SCR_Send_Slave_BasicInfo +
    • >>   SCR_Send_Self_BasicInfo +
    • >>   SCR_Send_RecordInfo +
    • >>   SCR_DispProcotol +
    • >>   __aeabi_ui2f +
    • >>   __aeabi_fdiv +
    • >>   __aeabi_f2d +
    • >>   __2sprintf +
    +
    [Called By]
    • >>   main +
    + +

    Screen_IT_Receive (Thumb, 40 bytes, Stack size 8 bytes, screen.o(i.Screen_IT_Receive)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = Screen_IT_Receive +
    +
    [Calls]
    • >>   Screen_ClearBuf +
    • >>   USART_ReceiveData +
    +
    [Called By]
    • >>   USART2_IRQHandler +
    + +

    Screen_IT_Update (Thumb, 5314 bytes, Stack size 144 bytes, screen.o(i.Screen_IT_Update)) +

    [Stack]

    • Max Depth = 304 + Unknown Stack Size +
    • Call Chain = Screen_IT_Update ⇒ USART2_printf ⇒ vsnprintf ⇒ _printf_char_common ⇒ __printf +
    +
    [Calls]
    • >>   RTC_GetCounter +
    • >>   EEPROM_WrMulByte +
    • >>   EEPROM_RdMulByte +
    • >>   SLEEP_Refresh +
    • >>   SLEEP2_Refresh +
    • >>   GetStr +
    • >>   uf_CAN1_Init +
    • >>   delay_ms +
    • >>   findHexStr +
    • >>   USART2_printf +
    • >>   Screen_ClearBuf +
    • >>   __aeabi_memset +
    • >>   strstr +
    +
    [Called By]
    • >>   main +
    + +

    Screen_Init (Thumb, 26 bytes, Stack size 8 bytes, screen.o(i.Screen_Init)) +

    [Stack]

    • Max Depth = 92
    • Call Chain = Screen_Init ⇒ uf_UART2_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq +
    +
    [Calls]
    • >>   uf_UART2_Init +
    • >>   Screen_ClearBuf +
    +
    [Called By]
    • >>   main +
    • >>   Screen_TIM_Moni +
    + +

    Screen_TIM_Moni (Thumb, 20 bytes, Stack size 0 bytes, screen.o(i.Screen_TIM_Moni)) +

    [Stack]

    • Max Depth = 92
    • Call Chain = Screen_TIM_Moni ⇒ Screen_Init ⇒ uf_UART2_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq +
    +
    [Calls]
    • >>   Screen_Init +
    +
    [Called By]
    • >>   TIM3_IRQHandler +
    + +

    Send_Record_Blank (Thumb, 76 bytes, Stack size 8 bytes, screen.o(i.Send_Record_Blank)) +

    [Stack]

    • Max Depth = 168 + Unknown Stack Size +
    • Call Chain = Send_Record_Blank ⇒ USART2_printf ⇒ vsnprintf ⇒ _printf_char_common ⇒ __printf +
    +
    [Calls]
    • >>   USART2_printf +
    • >>   Set_Row_Hide +
    +
    [Called By]
    • >>   SCR_Send_Slave_RecordBank +
    • >>   SCR_Send_RecordInfo +
    + +

    Set_Row_Hide (Thumb, 50 bytes, Stack size 0 bytes, screen.o(i.Set_Row_Hide)) +

    [Stack]

    • Max Depth = 160 + Unknown Stack Size +
    • Call Chain = Set_Row_Hide ⇒ USART2_printf ⇒ vsnprintf ⇒ _printf_char_common ⇒ __printf +
    +
    [Calls]
    • >>   USART2_printf +
    +
    [Called By]
    • >>   Send_Record_Blank +
    • >>   SCR_Send_Slave_RecordBank +
    • >>   SCR_Send_RecordInfo +
    + +

    SysTick_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f10x_it.o(i.SysTick_Handler)) +
    [Address Reference Count : 1]

    • startup_stm32f10x_hd.o(RESET) +
    +

    SystemInit (Thumb, 64 bytes, Stack size 8 bytes, system_stm32f10x.o(i.SystemInit)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = SystemInit ⇒ SetSysClockTo72 +
    +
    [Calls]
    • >>   SetSysClockTo72 +
    +
    [Address Reference Count : 1]
    • startup_stm32f10x_hd.o(.text) +
    +

    TEMP_Cal (Thumb, 122 bytes, Stack size 8 bytes, ntc.o(i.TEMP_Cal)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = TEMP_Cal +
    +
    [Called By]
    • >>   MCU_TemperaProcess +
    + +

    TEMP_Cal_CMFA (Thumb, 122 bytes, Stack size 8 bytes, ntc.o(i.TEMP_Cal_CMFA)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = TEMP_Cal_CMFA +
    +
    [Called By]
    • >>   AFE_TemperaProcess +
    + +

    TIM3_IRQHandler (Thumb, 246 bytes, Stack size 8 bytes, tim.o(i.TIM3_IRQHandler)) +

    [Stack]

    • Max Depth = 288 + Unknown Stack Size +
    • Call Chain = TIM3_IRQHandler ⇒ BLE_IT_Update ⇒ BLE_SETPARA ⇒ __0sscanf ⇒ __vfscanf_char ⇒ __vfscanf ⇒ _scanf_int +
    +
    [Calls]
    • >>   UVOff_TIM_Moni +
    • >>   SLEEP_TIM_Moni +
    • >>   SLEEP2_TIM_Moni +
    • >>   FCCCali_TIM_Moni +
    • >>   TIM_GetITStatus +
    • >>   TIM_ClearITPendingBit +
    • >>   Screen_TIM_Moni +
    • >>   OCC2_TIM_Moni +
    • >>   OCC2_Ctrl +
    • >>   MODBUS_TIM_Moni +
    • >>   MODBUS_IT_TIMUpdate +
    • >>   MODBUS1_TIM_Moni +
    • >>   MODBUS1_IT_TIMUpdate +
    • >>   Cali_SOC_Moni +
    • >>   CAN_TIM_Moni +
    • >>   BLE_TIM_Moni +
    • >>   BLE_IT_Update +
    • >>   KEY_TIM_Moni +
    • >>   ADDR_Rank_Moni +
    • >>   ADDR_Assign_Moni +
    +
    [Address Reference Count : 1]
    • startup_stm32f10x_hd.o(RESET) +
    +

    TIM4_PWM_Init (Thumb, 144 bytes, Stack size 48 bytes, pwm.o(i.TIM4_PWM_Init)) +

    [Stack]

    • Max Depth = 68
    • Call Chain = TIM4_PWM_Init ⇒ GPIO_Init +
    +
    [Calls]
    • >>   TIM_OC4PreloadConfig +
    • >>   TIM_OC4Init +
    • >>   TIM_CtrlPWMOutputs +
    • >>   TIM_ARRPreloadConfig +
    • >>   TIM_TimeBaseInit +
    • >>   TIM_Cmd +
    • >>   RCC_APB1PeriphClockCmd +
    • >>   RCC_APB2PeriphClockCmd +
    • >>   GPIO_Init +
    +
    [Called By]
    • >>   CHG_LIMIT_Init +
    + +

    TIMER_IsOut (Thumb, 28 bytes, Stack size 0 bytes, tim.o(i.TIMER_IsOut)) +

    [Called By]

    • >>   main +
    + +

    TIMER_Update (Thumb, 6 bytes, Stack size 0 bytes, tim.o(i.TIMER_Update)) +

    [Called By]

    • >>   main +
    + +

    TIM_ARRPreloadConfig (Thumb, 20 bytes, Stack size 0 bytes, stm32f10x_tim.o(i.TIM_ARRPreloadConfig)) +

    [Called By]

    • >>   TIM4_PWM_Init +
    + +

    TIM_ClearITPendingBit (Thumb, 6 bytes, Stack size 0 bytes, stm32f10x_tim.o(i.TIM_ClearITPendingBit)) +

    [Called By]

    • >>   TIM3_IRQHandler +
    + +

    TIM_Cmd (Thumb, 20 bytes, Stack size 0 bytes, stm32f10x_tim.o(i.TIM_Cmd)) +

    [Called By]

    • >>   uf_TIM3_Init +
    • >>   TIM4_PWM_Init +
    • >>   MODBUS_IT_Receive +
    • >>   MODBUS1_IT_Receive +
    + +

    TIM_CtrlPWMOutputs (Thumb, 22 bytes, Stack size 0 bytes, stm32f10x_tim.o(i.TIM_CtrlPWMOutputs)) +

    [Called By]

    • >>   TIM4_PWM_Init +
    + +

    TIM_GetITStatus (Thumb, 24 bytes, Stack size 0 bytes, stm32f10x_tim.o(i.TIM_GetITStatus)) +

    [Called By]

    • >>   TIM3_IRQHandler +
    + +

    TIM_ITConfig (Thumb, 16 bytes, Stack size 0 bytes, stm32f10x_tim.o(i.TIM_ITConfig)) +

    [Called By]

    • >>   uf_TIM3_Init +
    + +

    TIM_OC4Init (Thumb, 90 bytes, Stack size 16 bytes, stm32f10x_tim.o(i.TIM_OC4Init)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = TIM_OC4Init +
    +
    [Called By]
    • >>   TIM4_PWM_Init +
    + +

    TIM_OC4PreloadConfig (Thumb, 20 bytes, Stack size 0 bytes, stm32f10x_tim.o(i.TIM_OC4PreloadConfig)) +

    [Called By]

    • >>   TIM4_PWM_Init +
    + +

    TIM_SetCompare4 (Thumb, 6 bytes, Stack size 0 bytes, stm32f10x_tim.o(i.TIM_SetCompare4)) +

    [Called By]

    • >>   PWM_Set_Duty_Percent +
    + +

    TIM_SetCounter (Thumb, 4 bytes, Stack size 0 bytes, stm32f10x_tim.o(i.TIM_SetCounter)) +

    [Called By]

    • >>   MODBUS_IT_Receive +
    • >>   MODBUS1_IT_Receive +
    + +

    TIM_TimeBaseInit (Thumb, 114 bytes, Stack size 12 bytes, stm32f10x_tim.o(i.TIM_TimeBaseInit)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = TIM_TimeBaseInit +
    +
    [Called By]
    • >>   uf_TIM3_Init +
    • >>   TIM4_PWM_Init +
    + +

    TSC_Detect (Thumb, 82 bytes, Stack size 8 bytes, gpio.o(i.TSC_Detect)) +

    [Stack]

    • Max Depth = 104
    • Call Chain = TSC_Detect ⇒ CTRL_Off ⇒ AFE_Write ⇒ AFE_WriteOneByte ⇒ delay_us +
    +
    [Calls]
    • >>   delay_ms +
    • >>   LOAD_VOL +
    • >>   CTRL_On +
    • >>   CTRL_Off +
    +
    [Called By]
    • >>   main +
    + +

    Trigger_CurAlarm (Thumb, 132 bytes, Stack size 20 bytes, status.o(i.Trigger_CurAlarm)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = Trigger_CurAlarm +
    +
    [Called By]
    • >>   MCU_TemperaProcess +
    + +

    Trigger_CurProtect (Thumb, 140 bytes, Stack size 20 bytes, status.o(i.Trigger_CurProtect)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = Trigger_CurProtect +
    +
    [Called By]
    • >>   MCU_TemperaProcess +
    + +

    Trigger_CurProtectLock (Thumb, 2 bytes, Stack size 0 bytes, status.o(i.Trigger_CurProtectLock)) +

    [Called By]

    • >>   MCU_TemperaProcess +
    + +

    Trigger_OVAlarm (Thumb, 138 bytes, Stack size 20 bytes, status.o(i.Trigger_OVAlarm)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = Trigger_OVAlarm +
    +
    [Called By]
    • >>   AFE_VoltageProcess +
    + +

    Trigger_OVProtect (Thumb, 198 bytes, Stack size 20 bytes, status.o(i.Trigger_OVProtect)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = Trigger_OVProtect +
    +
    [Called By]
    • >>   AFE_VoltageProcess +
    + +

    Trigger_UVAlarm (Thumb, 138 bytes, Stack size 20 bytes, status.o(i.Trigger_UVAlarm)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = Trigger_UVAlarm +
    +
    [Called By]
    • >>   AFE_VoltageProcess +
    + +

    Trigger_UVProtect (Thumb, 192 bytes, Stack size 20 bytes, status.o(i.Trigger_UVProtect)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = Trigger_UVProtect +
    +
    [Called By]
    • >>   AFE_VoltageProcess +
    + +

    Trigger_afeTAlarm (Thumb, 178 bytes, Stack size 20 bytes, status.o(i.Trigger_afeTAlarm)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = Trigger_afeTAlarm +
    +
    [Called By]
    • >>   AFE_TemperaProcess +
    + +

    Trigger_afeTProtect (Thumb, 176 bytes, Stack size 20 bytes, status.o(i.Trigger_afeTProtect)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = Trigger_afeTProtect +
    +
    [Called By]
    • >>   AFE_TemperaProcess +
    + +

    Trigger_amTAlarm (Thumb, 288 bytes, Stack size 28 bytes, status.o(i.Trigger_amTAlarm)) +

    [Stack]

    • Max Depth = 28
    • Call Chain = Trigger_amTAlarm +
    +
    [Called By]
    • >>   AFE_TemperaProcess +
    + +

    Trigger_amTProtect (Thumb, 288 bytes, Stack size 28 bytes, status.o(i.Trigger_amTProtect)) +

    [Stack]

    • Max Depth = 28
    • Call Chain = Trigger_amTProtect +
    +
    [Called By]
    • >>   AFE_TemperaProcess +
    + +

    Trigger_mcuTAlarm (Thumb, 294 bytes, Stack size 32 bytes, status.o(i.Trigger_mcuTAlarm)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = Trigger_mcuTAlarm +
    +
    [Called By]
    • >>   MCU_TemperaProcess +
    + +

    Trigger_mcuTProtect (Thumb, 292 bytes, Stack size 32 bytes, status.o(i.Trigger_mcuTProtect)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = Trigger_mcuTProtect +
    +
    [Called By]
    • >>   MCU_TemperaProcess +
    + +

    UART1_ClearRecord (Thumb, 86 bytes, Stack size 8 bytes, rs485_modbus.o(i.UART1_ClearRecord)) +

    [Stack]

    • Max Depth = 100
    • Call Chain = UART1_ClearRecord ⇒ MODBUS_Init ⇒ uf_UART1_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq +
    +
    [Calls]
    • >>   EEPROM_RdMulByte +
    • >>   MODBUS_Init +
    • >>   USART_ITConfig +
    • >>   CRC16_Cal +
    +
    [Called By]
    • >>   MODBUS_IT_TIMUpdate +
    + +

    UART1_ProtocolSwitch (Thumb, 138 bytes, Stack size 32 bytes, rs485_modbus.o(i.UART1_ProtocolSwitch)) +

    [Stack]

    • Max Depth = 48
    • Call Chain = UART1_ProtocolSwitch ⇒ CRC16_Cal +
    +
    [Calls]
    • >>   USART_ITConfig +
    • >>   CRC16_Cal +
    • >>   strlen +
    • >>   strcpy +
    +
    [Called By]
    • >>   MODBUS_IT_TIMUpdate +
    + +

    UART1_ReadRecord (Thumb, 60 bytes, Stack size 8 bytes, rs485_modbus.o(i.UART1_ReadRecord)) +

    [Stack]

    • Max Depth = 100
    • Call Chain = UART1_ReadRecord ⇒ MODBUS_Init ⇒ uf_UART1_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq +
    +
    [Calls]
    • >>   MODBUS_Init +
    • >>   USART_ITConfig +
    • >>   CRC16_Cal +
    +
    [Called By]
    • >>   MODBUS_IT_TIMUpdate +
    + +

    UART3_ClearRecord (Thumb, 86 bytes, Stack size 8 bytes, rs485_modbus_inverter.o(i.UART3_ClearRecord)) +

    [Stack]

    • Max Depth = 92
    • Call Chain = UART3_ClearRecord ⇒ MODBUS1_Init ⇒ uf_UART3_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq +
    +
    [Calls]
    • >>   EEPROM_RdMulByte +
    • >>   MODBUS1_Init +
    • >>   USART_ITConfig +
    • >>   CRC16_Cal +
    +
    [Called By]
    • >>   MODBUS1_IT_TIMUpdate +
    + +

    UART3_EraseIAP (Thumb, 36 bytes, Stack size 0 bytes, rs485_modbus_inverter.o(i.UART3_EraseIAP)) +

    [Stack]

    • Max Depth = 84
    • Call Chain = UART3_EraseIAP ⇒ MODBUS1_Init ⇒ uf_UART3_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq +
    +
    [Calls]
    • >>   MODBUS1_Init +
    • >>   USART_ITConfig +
    +
    [Called By]
    • >>   MODBUS1_IT_TIMUpdate +
    + +

    UART3_ProtocolSwitch (Thumb, 160 bytes, Stack size 40 bytes, rs485_modbus_inverter.o(i.UART3_ProtocolSwitch)) +

    [Stack]

    • Max Depth = 56
    • Call Chain = UART3_ProtocolSwitch ⇒ CRC16_Cal +
    +
    [Calls]
    • >>   USART_ITConfig +
    • >>   CRC16_Cal +
    • >>   strlen +
    • >>   strcpy +
    +
    [Called By]
    • >>   MODBUS1_IT_TIMUpdate +
    + +

    UART3_ReadRecord (Thumb, 60 bytes, Stack size 8 bytes, rs485_modbus_inverter.o(i.UART3_ReadRecord)) +

    [Stack]

    • Max Depth = 92
    • Call Chain = UART3_ReadRecord ⇒ MODBUS1_Init ⇒ uf_UART3_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq +
    +
    [Calls]
    • >>   MODBUS1_Init +
    • >>   USART_ITConfig +
    • >>   CRC16_Cal +
    +
    [Called By]
    • >>   MODBUS1_IT_TIMUpdate +
    + +

    UART4_IRQHandler (Thumb, 36 bytes, Stack size 8 bytes, uart.o(i.UART4_IRQHandler)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = UART4_IRQHandler ⇒ USART_GetITStatus +
    +
    [Calls]
    • >>   USART_GetITStatus +
    • >>   BLE_IT_Receive +
    +
    [Address Reference Count : 1]
    • startup_stm32f10x_hd.o(RESET) +
    +

    USART1_IRQHandler (Thumb, 36 bytes, Stack size 8 bytes, uart.o(i.USART1_IRQHandler)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = USART1_IRQHandler ⇒ USART_GetITStatus +
    +
    [Calls]
    • >>   USART_GetITStatus +
    • >>   MODBUS_IT_Receive +
    +
    [Address Reference Count : 1]
    • startup_stm32f10x_hd.o(RESET) +
    +

    USART1_SendMulByte (Thumb, 48 bytes, Stack size 24 bytes, uart.o(i.USART1_SendMulByte)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = USART1_SendMulByte +
    +
    [Calls]
    • >>   USART_SendData +
    • >>   USART_GetFlagStatus +
    +
    [Called By]
    • >>   MODBUS_WrIndex_Tx +
    • >>   MODBUS_Screen_WrSlaveAddr_Tx +
    • >>   MODBUS_Screen_RdSlave_Tx +
    • >>   MODBUS_MASTER_Polling_Tx +
    • >>   MODBUS_IQ_Transmit +
    • >>   MODBUS_Config_RdSlave_Tx +
    • >>   MODBUS_AddrAssign_Tx +
    + +

    USART2_IRQHandler (Thumb, 36 bytes, Stack size 8 bytes, uart.o(i.USART2_IRQHandler)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = USART2_IRQHandler ⇒ USART_GetITStatus +
    +
    [Calls]
    • >>   USART_GetITStatus +
    • >>   Screen_IT_Receive +
    +
    [Address Reference Count : 1]
    • startup_stm32f10x_hd.o(RESET) +
    +

    USART2_printf (Thumb, 48 bytes, Stack size 32 bytes, screen.o(i.USART2_printf)) +

    [Stack]

    • Max Depth = 160 + Unknown Stack Size +
    • Call Chain = USART2_printf ⇒ vsnprintf ⇒ _printf_char_common ⇒ __printf +
    +
    [Calls]
    • >>   vsnprintf +
    +
    [Called By]
    • >>   Screen_IT_Update +
    • >>   Screen_IQ_Transmit +
    • >>   Set_Row_Hide +
    • >>   Send_Record_Blank +
    • >>   SCR_ShowAlarm_Slave +
    • >>   SCR_ShowAlarm +
    • >>   SCR_Send_VER +
    • >>   SCR_Send_TotalInfo +
    • >>   SCR_Send_Time +
    • >>   SCR_Send_Slave_RecordBank +
    • >>   SCR_Send_Slave_BasicInfo +
    • >>   SCR_Send_Self_BasicInfo +
    • >>   SCR_Send_RecordInfo +
    • >>   SCR_Send_Record +
    • >>   SCR_JumpToAlarm +
    • >>   SCR_DispProcotol +
    • >>   SCR_ClearAlarm +
    + +

    USART3_IRQHandler (Thumb, 36 bytes, Stack size 8 bytes, uart.o(i.USART3_IRQHandler)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = USART3_IRQHandler ⇒ USART_GetITStatus +
    +
    [Calls]
    • >>   USART_GetITStatus +
    • >>   MODBUS1_IT_Receive +
    +
    [Address Reference Count : 1]
    • startup_stm32f10x_hd.o(RESET) +
    +

    USART3_SendMulByte (Thumb, 48 bytes, Stack size 24 bytes, uart.o(i.USART3_SendMulByte)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = USART3_SendMulByte +
    +
    [Calls]
    • >>   USART_SendData +
    • >>   USART_GetFlagStatus +
    +
    [Called By]
    • >>   MODBUS1_IQ_Transmit +
    + +

    USART_Cmd (Thumb, 20 bytes, Stack size 0 bytes, stm32f10x_usart.o(i.USART_Cmd)) +

    [Called By]

    • >>   uf_UART4_Init +
    • >>   uf_UART3_Init +
    • >>   uf_UART2_Init +
    • >>   uf_UART1_Init +
    + +

    USART_GetFlagStatus (Thumb, 14 bytes, Stack size 0 bytes, stm32f10x_usart.o(i.USART_GetFlagStatus)) +

    [Called By]

    • >>   USART3_SendMulByte +
    • >>   USART1_SendMulByte +
    + +

    USART_GetITStatus (Thumb, 62 bytes, Stack size 12 bytes, stm32f10x_usart.o(i.USART_GetITStatus)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = USART_GetITStatus +
    +
    [Called By]
    • >>   USART3_IRQHandler +
    • >>   USART2_IRQHandler +
    • >>   USART1_IRQHandler +
    • >>   UART4_IRQHandler +
    + +

    USART_ITConfig (Thumb, 48 bytes, Stack size 8 bytes, stm32f10x_usart.o(i.USART_ITConfig)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = USART_ITConfig +
    +
    [Called By]
    • >>   MODBUS_WrIndex_Tx +
    • >>   MODBUS_Screen_WrSlaveAddr_Tx +
    • >>   MODBUS_Screen_RdSlave_Tx +
    • >>   MODBUS_MASTER_Polling_Tx +
    • >>   MODBUS_IQ_Transmit +
    • >>   MODBUS_Config_RdSlave_Tx +
    • >>   MODBUS_AddrAssign_Tx +
    • >>   MODBUS1_IQ_Transmit +
    • >>   uf_UART4_Init +
    • >>   uf_UART3_Init +
    • >>   uf_UART2_Init +
    • >>   uf_UART1_Init +
    • >>   YDN +
    • >>   UART3_ReadRecord +
    • >>   UART3_ProtocolSwitch +
    • >>   UART3_EraseIAP +
    • >>   UART3_ClearRecord +
    • >>   MODBUS1_Fbb_Rx +
    • >>   MODBUS1_Faa_Rx +
    • >>   MODBUS1_F10_Rx +
    • >>   MODBUS1_F03_Rx +
    • >>   UART1_ReadRecord +
    • >>   UART1_ProtocolSwitch +
    • >>   UART1_ClearRecord +
    • >>   MODBUS_MASTER_F10_Rx +
    • >>   MODBUS_MASTER_F03_Rx +
    • >>   MODBUS_Fbb_Rx +
    • >>   MODBUS_Faa_Rx +
    • >>   MODBUS_F10_Rx +
    • >>   MODBUS_F03_Rx +
    + +

    USART_Init (Thumb, 166 bytes, Stack size 32 bytes, stm32f10x_usart.o(i.USART_Init)) +

    [Stack]

    • Max Depth = 44
    • Call Chain = USART_Init ⇒ RCC_GetClocksFreq +
    +
    [Calls]
    • >>   RCC_GetClocksFreq +
    +
    [Called By]
    • >>   uf_UART4_Init +
    • >>   uf_UART3_Init +
    • >>   uf_UART2_Init +
    • >>   uf_UART1_Init +
    + +

    USART_ReceiveData (Thumb, 8 bytes, Stack size 0 bytes, stm32f10x_usart.o(i.USART_ReceiveData)) +

    [Called By]

    • >>   Screen_IT_Receive +
    • >>   MODBUS_IT_Receive +
    • >>   MODBUS1_IT_Receive +
    • >>   BLE_IT_Receive +
    + +

    USART_SendData (Thumb, 8 bytes, Stack size 0 bytes, stm32f10x_usart.o(i.USART_SendData)) +

    [Called By]

    • >>   USART3_SendMulByte +
    • >>   USART1_SendMulByte +
    + +

    USB_LP_CAN1_RX0_IRQHandler (Thumb, 74 bytes, Stack size 8 bytes, can.o(i.USB_LP_CAN1_RX0_IRQHandler)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = USB_LP_CAN1_RX0_IRQHandler ⇒ SLEEP_Refresh +
    +
    [Calls]
    • >>   SLEEP_Refresh +
    • >>   SLEEP2_Refresh +
    • >>   CAN_Receive +
    • >>   CAN_GetITStatus +
    +
    [Address Reference Count : 1]
    • startup_stm32f10x_hd.o(RESET) +
    +

    UVOff_TIM_Moni (Thumb, 46 bytes, Stack size 8 bytes, global.o(i.UVOff_TIM_Moni)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = UVOff_TIM_Moni +
    +
    [Called By]
    • >>   TIM3_IRQHandler +
    + +

    UsageFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32f10x_it.o(i.UsageFault_Handler)) +

    [Calls]

    • >>   UsageFault_Handler +
    +
    [Called By]
    • >>   UsageFault_Handler +
    +
    [Address Reference Count : 1]
    • startup_stm32f10x_hd.o(RESET) +
    +

    YDN (Thumb, 2662 bytes, Stack size 40 bytes, rs485_modbus_inverter.o(i.YDN)) +

    [Stack]

    • Max Depth = 124
    • Call Chain = YDN ⇒ MODBUS1_Init ⇒ uf_UART3_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq +
    +
    [Calls]
    • >>   toASCII +
    • >>   MODBUS1_Init +
    • >>   USART_ITConfig +
    +
    [Called By]
    • >>   YDN_Protocol_Pylon +
    + +

    YDN_Protocol_Pylon (Thumb, 4 bytes, Stack size 0 bytes, protocolswitch_p1.o(i.YDN_Protocol_Pylon)) +

    [Stack]

    • Max Depth = 124
    • Call Chain = YDN_Protocol_Pylon ⇒ YDN ⇒ MODBUS1_Init ⇒ uf_UART3_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq +
    +
    [Calls]
    • >>   YDN +
    +
    [Called By]
    • >>   MODBUS1_IT_TIMUpdate +
    + +

    __ARM_fpclassify (Thumb, 40 bytes, Stack size 0 bytes, fpclassify.o(i.__ARM_fpclassify)) +

    [Called By]

    • >>   _printf_fp_hex_real +
    • >>   _printf_fp_dec_real +
    + +

    _is_digit (Thumb, 14 bytes, Stack size 0 bytes, __printf_wp.o(i._is_digit)) +

    [Called By]

    • >>   __printf +
    + +

    canMem_refresh (Thumb, 1296 bytes, Stack size 120 bytes, global.o(i.canMem_refresh)) +

    [Stack]

    • Max Depth = 120
    • Call Chain = canMem_refresh +
    +
    [Called By]
    • >>   main +
    + +

    delay_ms (Thumb, 70 bytes, Stack size 24 bytes, systick.o(i.delay_ms)) +

    [Stack]

    • Max Depth = 24
    • Call Chain = delay_ms +
    +
    [Called By]
    • >>   EEPROM_CALI_RdZero +
    • >>   EEPROM_CALI_RdGain +
    • >>   uf_RTC_Update +
    • >>   uf_RTC_Init +
    • >>   uf_I2C1_Init +
    • >>   uf_GLOBAL_Init +
    • >>   uf_CAN1_Init +
    • >>   TSC_Detect +
    • >>   Screen_IT_Update +
    • >>   RTC_Get +
    • >>   RTC_BackUp +
    • >>   ParaChange +
    • >>   PCHG_StartCtrl +
    • >>   OCV_CaliSOC +
    • >>   MODBUS_IQ_Transmit +
    • >>   MODBUS1_IQ_Transmit +
    • >>   InitGasGauge +
    • >>   GaugeManage +
    • >>   Addr_Set +
    • >>   main +
    • >>   AFE_Write +
    • >>   AFE_Read +
    • >>   CHG_LIMIT_On +
    • >>   CHG_LIMIT_Off +
    • >>   RTC_GetSynchro +
    • >>   EEPROM_CALI_WrZero +
    • >>   EEPROM_CALI_WrGain +
    • >>   PCHG_Ctrl +
    • >>   Cali_FCC_Moni +
    • >>   SCR_Send_RecordInfo +
    • >>   MODBUS_WrIndex_Rx +
    • >>   SOE_BkData +
    • >>   BLE_SetBaud +
    • >>   BLE_SETPARA +
    • >>   BLE_CheckName +
    + +

    delay_us (Thumb, 62 bytes, Stack size 16 bytes, systick.o(i.delay_us)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = delay_us +
    +
    [Called By]
    • >>   AFE_WriteOneByte +
    • >>   AFE_ReadMulByte +
    + +

    findHexStr (Thumb, 46 bytes, Stack size 24 bytes, screen.o(i.findHexStr)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = findHexStr ⇒ memcmp +
    +
    [Calls]
    • >>   memcmp +
    +
    [Called By]
    • >>   Screen_IT_Update +
    + +

    get_random (Thumb, 46 bytes, Stack size 8 bytes, global.o(i.get_random)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = get_random +
    +
    [Calls]
    • >>   RTC_GetCounter +
    +
    [Called By]
    • >>   MODBUS_AddrAssign_Tx +
    + +

    main (Thumb, 720 bytes, Stack size 0 bytes, main.o(i.main)) +

    [Stack]

    • Max Depth = 576 + Unknown Stack Size +
    • Call Chain = main ⇒ MODBUS_IQ_Transmit ⇒ MEMORY_UpdateFlash ⇒ FLASH_WrData ⇒ FLASH_ProgramHalfWord ⇒ FLASH_WaitForLastOperation +
    +
    [Calls]
    • >>   uf_TIM3_Init +
    • >>   uf_SPI2_Init +
    • >>   uf_RTC_Update +
    • >>   uf_RTC_Init +
    • >>   uf_IWDG_Init +
    • >>   uf_I2C1_Init +
    • >>   uf_GPIO_Init +
    • >>   uf_GLOBAL_Init +
    • >>   uf_FLASH_Init +
    • >>   uf_EXTI_Init +
    • >>   uf_CAN1_Init +
    • >>   uf_ADC_Init +
    • >>   onlineMem_refresh +
    • >>   delay_ms +
    • >>   canMem_refresh +
    • >>   TSC_Detect +
    • >>   TIMER_Update +
    • >>   TIMER_IsOut +
    • >>   Screen_Init +
    • >>   Screen_IT_Update +
    • >>   Screen_IQ_Transmit +
    • >>   RTC_Get +
    • >>   RTC_BackUp +
    • >>   ParaChange +
    • >>   PCHG_StartCtrl +
    • >>   OCV_CaliSOC +
    • >>   MODBUS_WrIndex_Tx +
    • >>   MODBUS_Screen_WrSlaveAddr_Tx +
    • >>   MODBUS_Screen_RdSlave_Tx +
    • >>   MODBUS_Poll_Init +
    • >>   MODBUS_MASTER_Polling_Tx +
    • >>   MODBUS_Init +
    • >>   MODBUS_IQ_Transmit +
    • >>   MODBUS_Config_RdSlave_Tx +
    • >>   MODBUS_AddrAssign_Tx +
    • >>   MODBUS1_UpdateData +
    • >>   MODBUS1_Init +
    • >>   MODBUS1_IQ_Transmit +
    • >>   MCU_TemperaProcess +
    • >>   LED_RUN_Toggle +
    • >>   LED_RUN_On +
    • >>   LED_RUN_Off +
    • >>   LED_ALARM_Toggle +
    • >>   LED_ALARM_Off +
    • >>   InitGasGauge +
    • >>   IWDG_Feed +
    • >>   GaugeManage +
    • >>   CHG_LIMIT_Ctrl +
    • >>   CAN_UpdateData +
    • >>   CALI_CurrentProcess +
    • >>   BLE_Open +
    • >>   BLE_Init +
    • >>   BLE_IQ_Update +
    • >>   BLE_IQ_Transmit +
    • >>   BLE_IO_Init +
    • >>   Addr_Set +
    • >>   AFE_VoltageProcess +
    • >>   AFE_TemperaProcess +
    • >>   AFE_ProtectProcess +
    • >>   AFE_CurrentProcess +
    • >>   AFE_Ctrl +
    +
    [Called By]
    • >>   __rt_entry_main +
    + +

    onlineMem_refresh (Thumb, 136 bytes, Stack size 20 bytes, global.o(i.onlineMem_refresh)) +

    [Stack]

    • Max Depth = 20
    • Call Chain = onlineMem_refresh +
    +
    [Called By]
    • >>   main +
    + +

    toASCII (Thumb, 14 bytes, Stack size 0 bytes, global.o(i.toASCII)) +

    [Called By]

    • >>   YDN +
    + +

    uf_ADC_Init (Thumb, 160 bytes, Stack size 40 bytes, adc.o(i.uf_ADC_Init)) +

    [Stack]

    • Max Depth = 60
    • Call Chain = uf_ADC_Init ⇒ GPIO_Init +
    +
    [Calls]
    • >>   RCC_ADCCLKConfig +
    • >>   ADC_StartCalibration +
    • >>   ADC_ResetCalibration +
    • >>   ADC_Init +
    • >>   ADC_GetResetCalibrationStatus +
    • >>   ADC_GetCalibrationStatus +
    • >>   ADC_DeInit +
    • >>   ADC_Cmd +
    • >>   RCC_APB2PeriphClockCmd +
    • >>   GPIO_Init +
    +
    [Called By]
    • >>   main +
    + +

    uf_CAN1_Init (Thumb, 286 bytes, Stack size 56 bytes, can.o(i.uf_CAN1_Init)) +

    [Stack]

    • Max Depth = 80
    • Call Chain = uf_CAN1_Init ⇒ delay_ms +
    +
    [Calls]
    • >>   delay_ms +
    • >>   CAN_StructInit +
    • >>   CAN_Init +
    • >>   CAN_ITConfig +
    • >>   CAN_FilterInit +
    • >>   CAN_DeInit +
    • >>   RCC_APB1PeriphClockCmd +
    • >>   NVIC_Init +
    • >>   RCC_APB2PeriphClockCmd +
    • >>   GPIO_Init +
    +
    [Called By]
    • >>   Screen_IT_Update +
    • >>   MODBUS_IQ_Transmit +
    • >>   MODBUS1_IQ_Transmit +
    • >>   main +
    • >>   CAN_TIM_Moni +
    • >>   BLE_SETPARA +
    + +

    uf_EXTI_Init (Thumb, 8 bytes, Stack size 0 bytes, gpio.o(i.uf_EXTI_Init)) +

    [Calls]

    • >>   NVIC_PriorityGroupConfig +
    +
    [Called By]
    • >>   main +
    + +

    uf_FLASH_Init (Thumb, 56 bytes, Stack size 8 bytes, flash.o(i.uf_FLASH_Init)) +

    [Stack]

    • Max Depth = 432
    • Call Chain = uf_FLASH_Init ⇒ FLASH_UpdateMemory ⇒ FLASH_ReadCheck ⇒ CRC8_Cal +
    +
    [Calls]
    • >>   MEMORY_UpdateAFE +
    • >>   FLASH_UpdateMemory +
    +
    [Called By]
    • >>   main +
    + +

    uf_GLOBAL_Init (Thumb, 488 bytes, Stack size 32 bytes, global.o(i.uf_GLOBAL_Init)) +

    [Stack]

    • Max Depth = 184 + Unknown Stack Size +
    • Call Chain = uf_GLOBAL_Init ⇒ Refresh_PACK_SN ⇒ __2sprintf ⇒ _printf_char_common ⇒ __printf +
    +
    [Calls]
    • >>   EEPROM_WrMulByte +
    • >>   EEPROM_RdMulByte +
    • >>   EEPROM_CALI_RdZero +
    • >>   EEPROM_CALI_RdGain +
    • >>   Refresh_ScreenVersion +
    • >>   Refresh_PACK_SN +
    • >>   Refresh_HardwareVersion +
    • >>   Refresh_FirmwareVersion +
    • >>   Refresh_BMS_SN +
    • >>   CRC8_Cal +
    • >>   delay_ms +
    • >>   __aeabi_memclr +
    +
    [Called By]
    • >>   main +
    + +

    uf_GPIO_Init (Thumb, 430 bytes, Stack size 40 bytes, gpio.o(i.uf_GPIO_Init)) +

    [Stack]

    • Max Depth = 124
    • Call Chain = uf_GPIO_Init ⇒ CHG_LIMIT_Init ⇒ TIM4_PWM_Init ⇒ GPIO_Init +
    +
    [Calls]
    • >>   RCC_APB2PeriphClockCmd +
    • >>   GPIO_SetBits +
    • >>   GPIO_ResetBits +
    • >>   GPIO_PinRemapConfig +
    • >>   GPIO_Init +
    • >>   CHG_LIMIT_Init +
    +
    [Called By]
    • >>   main +
    + +

    uf_I2C1_Init (Thumb, 464 bytes, Stack size 56 bytes, i2c.o(i.uf_I2C1_Init)) +

    [Stack]

    • Max Depth = 124
    • Call Chain = uf_I2C1_Init ⇒ EEPROM_RdMulByte ⇒ I2C_GetFlagStatus +
    +
    [Calls]
    • >>   EEPROM_WrMulByte +
    • >>   EEPROM_RdMulByte +
    • >>   delay_ms +
    • >>   I2C_Init +
    • >>   I2C_DeInit +
    • >>   I2C_Cmd +
    • >>   I2C_AcknowledgeConfig +
    • >>   RCC_APB1PeriphClockCmd +
    • >>   RCC_APB2PeriphClockCmd +
    • >>   GPIO_Init +
    • >>   FLASH_WrData +
    • >>   FLASH_RdWord +
    +
    [Called By]
    • >>   main +
    + +

    uf_IWDG_Init (Thumb, 38 bytes, Stack size 16 bytes, wdg.o(i.uf_IWDG_Init)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = uf_IWDG_Init +
    +
    [Calls]
    • >>   IWDG_WriteAccessCmd +
    • >>   IWDG_SetReload +
    • >>   IWDG_SetPrescaler +
    • >>   IWDG_ReloadCounter +
    • >>   IWDG_Enable +
    +
    [Called By]
    • >>   main +
    + +

    uf_RTC_Init (Thumb, 418 bytes, Stack size 40 bytes, rtc.o(i.uf_RTC_Init)) +

    [Stack]

    • Max Depth = 108
    • Call Chain = uf_RTC_Init ⇒ EEPROM_RdMulByte ⇒ I2C_GetFlagStatus +
    +
    [Calls]
    • >>   RTC_GetCounter +
    • >>   EEPROM_RdMulByte +
    • >>   delay_ms +
    • >>   RTC_WaitForSynchro +
    • >>   RTC_WaitForLastTask +
    • >>   RTC_SetPrescaler +
    • >>   RTC_ITConfig +
    • >>   RTC_ExitConfigMode +
    • >>   RTC_EnterConfigMode +
    • >>   RCC_RTCCLKConfig +
    • >>   RCC_RTCCLKCmd +
    • >>   RCC_LSEConfig +
    • >>   RCC_GetFlagStatus +
    • >>   PWR_BackupAccessCmd +
    • >>   BKP_WriteBackupRegister +
    • >>   BKP_ReadBackupRegister +
    • >>   BKP_DeInit +
    • >>   RTC_Set +
    • >>   RTC_GetSynchro +
    • >>   RCC_APB1PeriphClockCmd +
    +
    [Called By]
    • >>   main +
    + +

    uf_RTC_Update (Thumb, 238 bytes, Stack size 32 bytes, rtc.o(i.uf_RTC_Update)) +

    [Stack]

    • Max Depth = 84
    • Call Chain = uf_RTC_Update ⇒ EEPROM_WrMulByte ⇒ I2C_GetFlagStatus +
    +
    [Calls]
    • >>   EEPROM_WrMulByte +
    • >>   delay_ms +
    • >>   RTC_WaitForSynchro +
    • >>   RTC_WaitForLastTask +
    • >>   RTC_SetPrescaler +
    • >>   RTC_ITConfig +
    • >>   RTC_ExitConfigMode +
    • >>   RTC_EnterConfigMode +
    • >>   RCC_RTCCLKConfig +
    • >>   RCC_RTCCLKCmd +
    • >>   RCC_LSEConfig +
    • >>   RCC_GetFlagStatus +
    • >>   PWR_BackupAccessCmd +
    • >>   BKP_WriteBackupRegister +
    • >>   BKP_DeInit +
    • >>   RTC_Set +
    • >>   RCC_APB1PeriphClockCmd +
    +
    [Called By]
    • >>   main +
    + +

    uf_SPI2_Init (Thumb, 186 bytes, Stack size 40 bytes, spi.o(i.uf_SPI2_Init)) +

    [Stack]

    • Max Depth = 60
    • Call Chain = uf_SPI2_Init ⇒ GPIO_Init +
    +
    [Calls]
    • >>   SPI_Init +
    • >>   SPI_I2S_DeInit +
    • >>   SPI_Cmd +
    • >>   RCC_APB1PeriphClockCmd +
    • >>   RCC_APB2PeriphClockCmd +
    • >>   GPIO_SetBits +
    • >>   GPIO_Init +
    +
    [Called By]
    • >>   main +
    • >>   SPI2_Error +
    + +

    uf_TIM3_Init (Thumb, 90 bytes, Stack size 32 bytes, tim.o(i.uf_TIM3_Init)) +

    [Stack]

    • Max Depth = 48
    • Call Chain = uf_TIM3_Init ⇒ NVIC_Init +
    +
    [Calls]
    • >>   TIM_TimeBaseInit +
    • >>   TIM_ITConfig +
    • >>   TIM_Cmd +
    • >>   RCC_APB1PeriphClockCmd +
    • >>   NVIC_Init +
    +
    [Called By]
    • >>   main +
    + +

    uf_UART1_Init (Thumb, 174 bytes, Stack size 48 bytes, uart.o(i.uf_UART1_Init)) +

    [Stack]

    • Max Depth = 92
    • Call Chain = uf_UART1_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq +
    +
    [Calls]
    • >>   USART_Init +
    • >>   USART_ITConfig +
    • >>   USART_Cmd +
    • >>   NVIC_Init +
    • >>   RCC_APB2PeriphClockCmd +
    • >>   GPIO_Init +
    +
    [Called By]
    • >>   MODBUS_Init +
    + +

    uf_UART2_Init (Thumb, 162 bytes, Stack size 40 bytes, uart.o(i.uf_UART2_Init)) +

    [Stack]

    • Max Depth = 84
    • Call Chain = uf_UART2_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq +
    +
    [Calls]
    • >>   USART_Init +
    • >>   USART_ITConfig +
    • >>   USART_Cmd +
    • >>   RCC_APB1PeriphClockCmd +
    • >>   NVIC_Init +
    • >>   RCC_APB2PeriphClockCmd +
    • >>   GPIO_Init +
    +
    [Called By]
    • >>   Screen_Init +
    + +

    uf_UART3_Init (Thumb, 160 bytes, Stack size 40 bytes, uart.o(i.uf_UART3_Init)) +

    [Stack]

    • Max Depth = 84
    • Call Chain = uf_UART3_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq +
    +
    [Calls]
    • >>   USART_Init +
    • >>   USART_ITConfig +
    • >>   USART_Cmd +
    • >>   RCC_APB1PeriphClockCmd +
    • >>   NVIC_Init +
    • >>   RCC_APB2PeriphClockCmd +
    • >>   GPIO_Init +
    +
    [Called By]
    • >>   MODBUS1_Init +
    + +

    uf_UART4_Init (Thumb, 160 bytes, Stack size 40 bytes, uart.o(i.uf_UART4_Init)) +

    [Stack]

    • Max Depth = 84
    • Call Chain = uf_UART4_Init ⇒ USART_Init ⇒ RCC_GetClocksFreq +
    +
    [Calls]
    • >>   USART_Init +
    • >>   USART_ITConfig +
    • >>   USART_Cmd +
    • >>   RCC_APB1PeriphClockCmd +
    • >>   NVIC_Init +
    • >>   RCC_APB2PeriphClockCmd +
    • >>   GPIO_Init +
    +
    [Called By]
    • >>   BLE_Init +
    • >>   BLE_SetBaud +
    + +

    _get_lc_numeric (Thumb, 44 bytes, Stack size 8 bytes, lc_numeric_c.o(locale$$code)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = _get_lc_numeric +
    +
    [Calls]
    • >>   strcmp +
    +
    [Called By]
    • >>   __rt_lib_init_lc_numeric_2 +
    + +

    _get_lc_ctype (Thumb, 44 bytes, Stack size 8 bytes, lc_ctype_c.o(locale$$code)) +

    [Stack]

    • Max Depth = 8
    • Call Chain = _get_lc_ctype +
    +
    [Calls]
    • >>   strcmp +
    +
    [Called By]
    • >>   __rt_lib_init_lc_ctype_2 +
    +
    [Address Reference Count : 1]
    • rt_ctype_table.o(.text) +
    +

    __aeabi_dadd (Thumb, 0 bytes, Stack size 16 bytes, daddsub_clz.o(x$fpl$dadd)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = __aeabi_dadd +
    +
    [Called By]
    • >>   CHG_LIMIT_On +
    + +

    _dadd (Thumb, 332 bytes, Stack size 16 bytes, daddsub_clz.o(x$fpl$dadd), UNUSED) +

    [Calls]

    • >>   __fpl_dretinf +
    • >>   __fpl_dnaninf +
    • >>   _dsub1 +
    + +

    __aeabi_ddiv (Thumb, 0 bytes, Stack size 32 bytes, ddiv.o(x$fpl$ddiv)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = __aeabi_ddiv +
    +
    [Called By]
    • >>   SCR_Send_TotalInfo +
    + +

    _ddiv (Thumb, 552 bytes, Stack size 32 bytes, ddiv.o(x$fpl$ddiv), UNUSED) +

    [Calls]

    • >>   __fpl_dretinf +
    • >>   __fpl_dnaninf +
    + +

    __aeabi_d2iz (Thumb, 0 bytes, Stack size 32 bytes, dfix.o(x$fpl$dfix)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = __aeabi_d2iz +
    +
    [Called By]
    • >>   CHG_LIMIT_On +
    + +

    _dfix (Thumb, 94 bytes, Stack size 32 bytes, dfix.o(x$fpl$dfix), UNUSED) +

    [Calls]

    • >>   __fpl_dnaninf +
    + +

    __aeabi_d2uiz (Thumb, 0 bytes, Stack size 32 bytes, dfixu.o(x$fpl$dfixu)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = __aeabi_d2uiz +
    +
    [Called By]
    • >>   SCR_Send_TotalInfo +
    + +

    _dfixu (Thumb, 90 bytes, Stack size 32 bytes, dfixu.o(x$fpl$dfixu), UNUSED) +

    [Calls]

    • >>   __fpl_dnaninf +
    + +

    __aeabi_ui2d (Thumb, 0 bytes, Stack size 0 bytes, dflt_clz.o(x$fpl$dfltu)) +

    [Called By]

    • >>   SCR_Send_TotalInfo +
    • >>   SCR_Send_Slave_BasicInfo +
    • >>   SCR_Send_Self_BasicInfo +
    + +

    _dfltu (Thumb, 38 bytes, Stack size 0 bytes, dflt_clz.o(x$fpl$dfltu), UNUSED) + +

    __aeabi_dmul (Thumb, 0 bytes, Stack size 32 bytes, dmul.o(x$fpl$dmul)) +

    [Stack]

    • Max Depth = 32
    • Call Chain = __aeabi_dmul +
    +
    [Called By]
    • >>   SCR_Send_TotalInfo +
    + +

    _dmul (Thumb, 332 bytes, Stack size 32 bytes, dmul.o(x$fpl$dmul), UNUSED) +

    [Calls]

    • >>   __fpl_dretinf +
    • >>   __fpl_dnaninf +
    + +

    __fpl_dnaninf (Thumb, 156 bytes, Stack size 16 bytes, dnaninf.o(x$fpl$dnaninf), UNUSED) +

    [Called By]

    • >>   _dmul +
    • >>   _dfixu +
    • >>   _dfix +
    • >>   _ddiv +
    • >>   _dsub +
    • >>   _dadd +
    + +

    __fpl_dretinf (Thumb, 12 bytes, Stack size 0 bytes, dretinf.o(x$fpl$dretinf), UNUSED) +

    [Called By]

    • >>   _f2d +
    • >>   _dmul +
    • >>   _ddiv +
    • >>   _dadd +
    + +

    __aeabi_dsub (Thumb, 0 bytes, Stack size 32 bytes, daddsub_clz.o(x$fpl$dsub), UNUSED) + +

    _dsub (Thumb, 464 bytes, Stack size 32 bytes, daddsub_clz.o(x$fpl$dsub), UNUSED) +

    [Calls]

    • >>   __fpl_dnaninf +
    • >>   _dadd1 +
    + +

    __aeabi_f2d (Thumb, 0 bytes, Stack size 16 bytes, f2d.o(x$fpl$f2d)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = __aeabi_f2d +
    +
    [Called By]
    • >>   Screen_IQ_Transmit +
    • >>   BLE_IQ_Transmit +
    • >>   CHG_LIMIT_On +
    • >>   SCR_Send_TotalInfo +
    • >>   SCR_Send_Slave_BasicInfo +
    • >>   SCR_Send_Self_BasicInfo +
    + +

    _f2d (Thumb, 86 bytes, Stack size 16 bytes, f2d.o(x$fpl$f2d), UNUSED) +

    [Calls]

    • >>   __fpl_fnaninf +
    • >>   __fpl_dretinf +
    + +

    __aeabi_fadd (Thumb, 0 bytes, Stack size 16 bytes, faddsub_clz.o(x$fpl$fadd)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = __aeabi_fadd +
    +
    [Called By]
    • >>   PWM_Set_Duty_Percent +
    • >>   CHG_LIMIT_PWM_Adjust +
    + +

    _fadd (Thumb, 196 bytes, Stack size 16 bytes, faddsub_clz.o(x$fpl$fadd), UNUSED) +

    [Calls]

    • >>   __fpl_fretinf +
    • >>   __fpl_fnaninf +
    • >>   _fsub1 +
    + +

    __aeabi_fdiv (Thumb, 0 bytes, Stack size 16 bytes, fdiv.o(x$fpl$fdiv)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = __aeabi_fdiv +
    +
    [Called By]
    • >>   Screen_IQ_Transmit +
    • >>   BLE_IQ_Transmit +
    • >>   PWM_Set_Duty_Percent +
    • >>   CHG_LIMIT_On +
    • >>   SCR_Send_TotalInfo +
    • >>   SCR_Send_Slave_BasicInfo +
    • >>   SCR_Send_Self_BasicInfo +
    + +

    _fdiv (Thumb, 384 bytes, Stack size 16 bytes, fdiv.o(x$fpl$fdiv), UNUSED) +

    [Calls]

    • >>   __fpl_fretinf +
    • >>   __fpl_fnaninf +
    + +

    __aeabi_f2uiz (Thumb, 0 bytes, Stack size 16 bytes, ffixu.o(x$fpl$ffixu)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = __aeabi_f2uiz +
    +
    [Called By]
    • >>   PWM_Set_Duty_Percent +
    + +

    _ffixu (Thumb, 62 bytes, Stack size 16 bytes, ffixu.o(x$fpl$ffixu), UNUSED) +

    [Calls]

    • >>   __fpl_fnaninf +
    + +

    __aeabi_i2f (Thumb, 0 bytes, Stack size 0 bytes, fflt_clz.o(x$fpl$fflt)) +

    [Called By]

    • >>   BLE_IQ_Transmit +
    • >>   CHG_LIMIT_On +
    • >>   SCR_Send_TotalInfo +
    • >>   SCR_Send_Slave_BasicInfo +
    • >>   SCR_Send_Self_BasicInfo +
    + +

    _fflt (Thumb, 48 bytes, Stack size 0 bytes, fflt_clz.o(x$fpl$fflt), UNUSED) + +

    __aeabi_ui2f (Thumb, 0 bytes, Stack size 0 bytes, fflt_clz.o(x$fpl$ffltu)) +

    [Called By]

    • >>   Screen_IQ_Transmit +
    • >>   CHG_LIMIT_On +
    • >>   SCR_Send_TotalInfo +
    • >>   SCR_Send_Slave_BasicInfo +
    • >>   SCR_Send_Self_BasicInfo +
    + +

    _ffltu (Thumb, 38 bytes, Stack size 0 bytes, fflt_clz.o(x$fpl$ffltu), UNUSED) + +

    __aeabi_fmul (Thumb, 0 bytes, Stack size 16 bytes, fmul.o(x$fpl$fmul)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = __aeabi_fmul +
    +
    [Called By]
    • >>   PWM_Set_Duty_Percent +
    • >>   CHG_LIMIT_On +
    + +

    _fmul (Thumb, 258 bytes, Stack size 16 bytes, fmul.o(x$fpl$fmul), UNUSED) +

    [Calls]

    • >>   __fpl_fretinf +
    • >>   __fpl_fnaninf +
    + +

    __fpl_fnaninf (Thumb, 140 bytes, Stack size 8 bytes, fnaninf.o(x$fpl$fnaninf), UNUSED) +

    [Called By]

    • >>   _fmul +
    • >>   _ffixu +
    • >>   _fdiv +
    • >>   _fsub +
    • >>   _fadd +
    • >>   _f2d +
    + +

    __fpl_fretinf (Thumb, 10 bytes, Stack size 0 bytes, fretinf.o(x$fpl$fretinf), UNUSED) +

    [Called By]

    • >>   _fmul +
    • >>   _fdiv +
    • >>   _fadd +
    + +

    __aeabi_fsub (Thumb, 0 bytes, Stack size 16 bytes, faddsub_clz.o(x$fpl$fsub)) +

    [Stack]

    • Max Depth = 16
    • Call Chain = __aeabi_fsub +
    +
    [Called By]
    • >>   CHG_LIMIT_PWM_Adjust +
    + +

    _fsub (Thumb, 234 bytes, Stack size 16 bytes, faddsub_clz.o(x$fpl$fsub), UNUSED) +

    [Calls]

    • >>   __fpl_fnaninf +
    • >>   _fadd1 +
    + +

    _printf_fp_dec (Thumb, 4 bytes, Stack size 0 bytes, printf1.o(x$fpl$printf1)) +

    [Stack]

    • Max Depth = 324
    • Call Chain = _printf_fp_dec ⇒ _printf_fp_dec_real ⇒ _fp_digits ⇒ _btod_etento ⇒ _btod_emul ⇒ _e2e +
    +
    [Calls]
    • >>   _printf_fp_dec_real +
    +
    [Called By]
    • >>   _printf_g +
    • >>   _printf_e +
    • >>   _printf_f +
    + +

    _printf_fp_hex (Thumb, 4 bytes, Stack size 0 bytes, printf2.o(x$fpl$printf2)) +

    [Stack]

    • Max Depth = 112
    • Call Chain = _printf_fp_hex ⇒ _printf_fp_hex_real ⇒ _printf_fp_infnan ⇒ _printf_post_padding +
    +
    [Calls]
    • >>   _printf_fp_hex_real +
    +
    [Called By]
    • >>   _printf_a +
    +

    +

    +Local Symbols +

    +

    SetSysClockTo72 (Thumb, 160 bytes, Stack size 12 bytes, system_stm32f10x.o(i.SetSysClockTo72)) +

    [Stack]

    • Max Depth = 12
    • Call Chain = SetSysClockTo72 +
    +
    [Called By]
    • >>   SystemInit +
    + +

    CheckITStatus (Thumb, 12 bytes, Stack size 0 bytes, stm32f10x_can.o(i.CheckITStatus)) +

    [Called By]

    • >>   CAN_GetITStatus +
    + +

    _dadd1 (Thumb, 0 bytes, Stack size unknown bytes, daddsub_clz.o(x$fpl$dadd), UNUSED) +

    [Called By]

    • >>   _dsub +
    + +

    _dsub1 (Thumb, 0 bytes, Stack size unknown bytes, daddsub_clz.o(x$fpl$dsub), UNUSED) +

    [Called By]

    • >>   _dadd +
    + +

    _fadd1 (Thumb, 0 bytes, Stack size unknown bytes, faddsub_clz.o(x$fpl$fadd), UNUSED) +

    [Called By]

    • >>   _fsub +
    + +

    _fsub1 (Thumb, 0 bytes, Stack size unknown bytes, faddsub_clz.o(x$fpl$fsub), UNUSED) +

    [Called By]

    • >>   _fadd +
    + +

    _printf_input_char (Thumb, 10 bytes, Stack size 0 bytes, _printf_char_common.o(.text)) +
    [Address Reference Count : 1]

    • _printf_char_common.o(.text) +
    +

    _scanf_char_input (Thumb, 12 bytes, Stack size 0 bytes, scanf_char.o(.text)) +
    [Address Reference Count : 1]

    • scanf_char.o(.text) +
    +

    _fp_digits (Thumb, 432 bytes, Stack size 96 bytes, _printf_fp_dec.o(.text)) +

    [Stack]

    • Max Depth = 220
    • Call Chain = _fp_digits ⇒ _btod_etento ⇒ _btod_emul ⇒ _e2e +
    +
    [Calls]
    • >>   _btod_emul +
    • >>   _btod_ediv +
    • >>   _btod_d2e +
    • >>   _btod_etento +
    • >>   _ll_udiv10 +
    +
    [Called By]
    • >>   _printf_fp_dec_real +
    +

    +

    +Undefined Global Symbols +

    diff --git a/OBJ/BT_BMS_V3.lnp b/OBJ/BT_BMS_V3.lnp new file mode 100644 index 0000000..d44fce3 --- /dev/null +++ b/OBJ/BT_BMS_V3.lnp @@ -0,0 +1,62 @@ +--cpu Cortex-M3 +"..\obj\core_cm3.o" +"..\obj\startup_stm32f10x_hd.o" +"..\obj\main.o" +"..\obj\global.o" +"..\obj\stm32f10x_it.o" +"..\obj\system_stm32f10x.o" +"..\obj\gpio.o" +"..\obj\tim.o" +"..\obj\uart.o" +"..\obj\i2c.o" +"..\obj\spi.o" +"..\obj\flash.o" +"..\obj\rtc.o" +"..\obj\systick.o" +"..\obj\can.o" +"..\obj\adc.o" +"..\obj\pwm.o" +"..\obj\wdg.o" +"..\obj\afe_sh3673520.o" +"..\obj\rs485_modbus.o" +"..\obj\rs485_modbus_inverter.o" +"..\obj\ntc.o" +"..\obj\screen.o" +"..\obj\gasgauge.o" +"..\obj\soe.o" +"..\obj\ocv.o" +"..\obj\status.o" +"..\obj\mbo26a.o" +"..\obj\yibang.o" +"..\obj\h7690c.o" +"..\obj\lbs_transmit.o" +"..\obj\ota.o" +"..\obj\misc.o" +"..\obj\stm32f10x_adc.o" +"..\obj\stm32f10x_bkp.o" +"..\obj\stm32f10x_can.o" +"..\obj\stm32f10x_cec.o" +"..\obj\stm32f10x_crc.o" +"..\obj\stm32f10x_dac.o" +"..\obj\stm32f10x_dbgmcu.o" +"..\obj\stm32f10x_dma.o" +"..\obj\stm32f10x_exti.o" +"..\obj\stm32f10x_flash.o" +"..\obj\stm32f10x_fsmc.o" +"..\obj\stm32f10x_gpio.o" +"..\obj\stm32f10x_i2c.o" +"..\obj\stm32f10x_iwdg.o" +"..\obj\stm32f10x_pwr.o" +"..\obj\stm32f10x_rcc.o" +"..\obj\stm32f10x_rtc.o" +"..\obj\stm32f10x_sdio.o" +"..\obj\stm32f10x_spi.o" +"..\obj\stm32f10x_tim.o" +"..\obj\stm32f10x_usart.o" +"..\obj\stm32f10x_wwdg.o" +"..\obj\protocolswitch_p1.o" +"..\obj\protocolswitch_p2.o" +--strict --scatter "..\OBJ\BT_BMS_V3.sct" +--summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols +--info sizes --info totals --info unused --info veneers +--list ".\Listings\BT_BMS_V3.map" -o ..\OBJ\BT_BMS_V3.0 \ No newline at end of file diff --git a/OBJ/BT_BMS_V3.sct b/OBJ/BT_BMS_V3.sct new file mode 100644 index 0000000..fd82337 --- /dev/null +++ b/OBJ/BT_BMS_V3.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x08000000 0x00040000 { ; load region size_region + ER_IROM1 0x08000000 0x00040000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x0000C000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/OBJ/BT_BMS_V3_sct.Bak b/OBJ/BT_BMS_V3_sct.Bak new file mode 100644 index 0000000..8728412 --- /dev/null +++ b/OBJ/BT_BMS_V3_sct.Bak @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x08001800 0x00040000 { ; load region size_region + ER_IROM1 0x08001800 0x00040000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x0000C000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/OBJ/ExtDll.iex b/OBJ/ExtDll.iex new file mode 100644 index 0000000..6c0896e --- /dev/null +++ b/OBJ/ExtDll.iex @@ -0,0 +1,2 @@ +[EXTDLL] +Count=0 diff --git a/OBJ/adc.crf b/OBJ/adc.crf new file mode 100644 index 0000000..aa732e7 Binary files /dev/null and b/OBJ/adc.crf differ diff --git a/OBJ/adc.d b/OBJ/adc.d new file mode 100644 index 0000000..27a31ad --- /dev/null +++ b/OBJ/adc.d @@ -0,0 +1,32 @@ +..\obj\adc.o: ..\BSP\adc.c +..\obj\adc.o: ..\USER\stm32f10x.h +..\obj\adc.o: ..\CORE\core_cm3.h +..\obj\adc.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\adc.o: ..\USER\system_stm32f10x.h +..\obj\adc.o: ..\USER\stm32f10x_conf.h +..\obj\adc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\adc.o: ..\USER\stm32f10x.h +..\obj\adc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\adc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\adc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\adc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\adc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\adc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\adc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\adc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\adc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\adc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\adc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\adc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\adc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\adc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\adc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\adc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\adc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\adc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\adc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\adc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\adc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\adc.o: ..\STM32F10x_FWLIB\inc\misc.h +..\obj\adc.o: ..\USER\global.h +..\obj\adc.o: ..\MOUDLE\AFE_SH3673520.h diff --git a/OBJ/adc.o b/OBJ/adc.o new file mode 100644 index 0000000..fe618ac Binary files /dev/null and b/OBJ/adc.o differ diff --git a/OBJ/afe_sh367309.crf b/OBJ/afe_sh367309.crf new file mode 100644 index 0000000..3a9898e Binary files /dev/null and b/OBJ/afe_sh367309.crf differ diff --git a/OBJ/afe_sh367309.d b/OBJ/afe_sh367309.d new file mode 100644 index 0000000..26f14d7 --- /dev/null +++ b/OBJ/afe_sh367309.d @@ -0,0 +1,34 @@ +..\obj\afe_sh367309.o: ..\MOUDLE\AFE_SH367309.c +..\obj\afe_sh367309.o: ..\USER\stm32f10x.h +..\obj\afe_sh367309.o: ..\CORE\core_cm3.h +..\obj\afe_sh367309.o: C:\Users\Public\keil_C51\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\afe_sh367309.o: ..\USER\system_stm32f10x.h +..\obj\afe_sh367309.o: ..\USER\stm32f10x_conf.h +..\obj\afe_sh367309.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\afe_sh367309.o: ..\USER\stm32f10x.h +..\obj\afe_sh367309.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\afe_sh367309.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\afe_sh367309.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\afe_sh367309.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\afe_sh367309.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\afe_sh367309.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\afe_sh367309.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\afe_sh367309.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\afe_sh367309.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\afe_sh367309.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\afe_sh367309.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\afe_sh367309.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\afe_sh367309.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\afe_sh367309.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\afe_sh367309.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\afe_sh367309.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\afe_sh367309.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\afe_sh367309.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\afe_sh367309.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\afe_sh367309.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\afe_sh367309.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\afe_sh367309.o: ..\STM32F10x_FWLIB\inc\misc.h +..\obj\afe_sh367309.o: ..\USER\global.h +..\obj\afe_sh367309.o: C:\Users\Public\keil_C51\ARM\ARMCC\Bin\..\include\string.h +..\obj\afe_sh367309.o: ..\MOUDLE\AFE_SH367309.h +..\obj\afe_sh367309.o: ..\MOUDLE\soe.h diff --git a/OBJ/afe_sh367309.o b/OBJ/afe_sh367309.o new file mode 100644 index 0000000..7dd7e15 Binary files /dev/null and b/OBJ/afe_sh367309.o differ diff --git a/OBJ/afe_sh3673510.d b/OBJ/afe_sh3673510.d new file mode 100644 index 0000000..66a32d1 --- /dev/null +++ b/OBJ/afe_sh3673510.d @@ -0,0 +1,34 @@ +..\obj\afe_sh3673510.o: ..\MOUDLE\AFE_SH3673510.c +..\obj\afe_sh3673510.o: ..\USER\stm32f10x.h +..\obj\afe_sh3673510.o: ..\CORE\core_cm3.h +..\obj\afe_sh3673510.o: C:\Users\Public\keil_C51\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\afe_sh3673510.o: ..\USER\system_stm32f10x.h +..\obj\afe_sh3673510.o: ..\USER\stm32f10x_conf.h +..\obj\afe_sh3673510.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\afe_sh3673510.o: ..\USER\stm32f10x.h +..\obj\afe_sh3673510.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\afe_sh3673510.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\afe_sh3673510.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\afe_sh3673510.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\afe_sh3673510.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\afe_sh3673510.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\afe_sh3673510.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\afe_sh3673510.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\afe_sh3673510.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\afe_sh3673510.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\afe_sh3673510.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\afe_sh3673510.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\afe_sh3673510.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\afe_sh3673510.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\afe_sh3673510.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\afe_sh3673510.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\afe_sh3673510.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\afe_sh3673510.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\afe_sh3673510.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\afe_sh3673510.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\afe_sh3673510.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\afe_sh3673510.o: ..\STM32F10x_FWLIB\inc\misc.h +..\obj\afe_sh3673510.o: ..\USER\global.h +..\obj\afe_sh3673510.o: C:\Users\Public\keil_C51\ARM\ARMCC\Bin\..\include\string.h +..\obj\afe_sh3673510.o: ..\MOUDLE\AFE_SH3673510.h +..\obj\afe_sh3673510.o: ..\MOUDLE\soe.h diff --git a/OBJ/afe_sh3673520.crf b/OBJ/afe_sh3673520.crf new file mode 100644 index 0000000..531661d Binary files /dev/null and b/OBJ/afe_sh3673520.crf differ diff --git a/OBJ/afe_sh3673520.d b/OBJ/afe_sh3673520.d new file mode 100644 index 0000000..fa175e8 --- /dev/null +++ b/OBJ/afe_sh3673520.d @@ -0,0 +1,34 @@ +..\obj\afe_sh3673520.o: ..\MOUDLE\AFE_SH3673520.c +..\obj\afe_sh3673520.o: ..\USER\stm32f10x.h +..\obj\afe_sh3673520.o: ..\CORE\core_cm3.h +..\obj\afe_sh3673520.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\afe_sh3673520.o: ..\USER\system_stm32f10x.h +..\obj\afe_sh3673520.o: ..\USER\stm32f10x_conf.h +..\obj\afe_sh3673520.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\afe_sh3673520.o: ..\USER\stm32f10x.h +..\obj\afe_sh3673520.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\afe_sh3673520.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\afe_sh3673520.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\afe_sh3673520.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\afe_sh3673520.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\afe_sh3673520.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\afe_sh3673520.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\afe_sh3673520.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\afe_sh3673520.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\afe_sh3673520.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\afe_sh3673520.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\afe_sh3673520.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\afe_sh3673520.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\afe_sh3673520.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\afe_sh3673520.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\afe_sh3673520.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\afe_sh3673520.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\afe_sh3673520.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\afe_sh3673520.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\afe_sh3673520.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\afe_sh3673520.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\afe_sh3673520.o: ..\STM32F10x_FWLIB\inc\misc.h +..\obj\afe_sh3673520.o: ..\USER\global.h +..\obj\afe_sh3673520.o: ..\MOUDLE\AFE_SH3673520.h +..\obj\afe_sh3673520.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\string.h +..\obj\afe_sh3673520.o: ..\MOUDLE\soe.h diff --git a/OBJ/afe_sh3673520.o b/OBJ/afe_sh3673520.o new file mode 100644 index 0000000..2f03dc6 Binary files /dev/null and b/OBJ/afe_sh3673520.o differ diff --git a/OBJ/can.crf b/OBJ/can.crf new file mode 100644 index 0000000..1bc38e4 Binary files /dev/null and b/OBJ/can.crf differ diff --git a/OBJ/can.d b/OBJ/can.d new file mode 100644 index 0000000..e48246f --- /dev/null +++ b/OBJ/can.d @@ -0,0 +1,32 @@ +..\obj\can.o: ..\BSP\can.c +..\obj\can.o: ..\USER\stm32f10x.h +..\obj\can.o: ..\CORE\core_cm3.h +..\obj\can.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\can.o: ..\USER\system_stm32f10x.h +..\obj\can.o: ..\USER\stm32f10x_conf.h +..\obj\can.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\can.o: ..\USER\stm32f10x.h +..\obj\can.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\can.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\can.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\can.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\can.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\can.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\can.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\can.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\can.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\can.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\can.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\can.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\can.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\can.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\can.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\can.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\can.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\can.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\can.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\can.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\can.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\can.o: ..\STM32F10x_FWLIB\inc\misc.h +..\obj\can.o: ..\USER\global.h +..\obj\can.o: ..\MOUDLE\AFE_SH3673520.h diff --git a/OBJ/can.o b/OBJ/can.o new file mode 100644 index 0000000..d17b8ad Binary files /dev/null and b/OBJ/can.o differ diff --git a/OBJ/core_cm3.crf b/OBJ/core_cm3.crf new file mode 100644 index 0000000..41bd0fa Binary files /dev/null and b/OBJ/core_cm3.crf differ diff --git a/OBJ/core_cm3.d b/OBJ/core_cm3.d new file mode 100644 index 0000000..324cc6c --- /dev/null +++ b/OBJ/core_cm3.d @@ -0,0 +1,2 @@ +..\obj\core_cm3.o: ..\CORE\core_cm3.c +..\obj\core_cm3.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h diff --git a/OBJ/core_cm3.o b/OBJ/core_cm3.o new file mode 100644 index 0000000..4debb5c Binary files /dev/null and b/OBJ/core_cm3.o differ diff --git a/OBJ/flash.crf b/OBJ/flash.crf new file mode 100644 index 0000000..b7a1863 Binary files /dev/null and b/OBJ/flash.crf differ diff --git a/OBJ/flash.d b/OBJ/flash.d new file mode 100644 index 0000000..d68f77c --- /dev/null +++ b/OBJ/flash.d @@ -0,0 +1,33 @@ +..\obj\flash.o: ..\BSP\flash.c +..\obj\flash.o: ..\USER\stm32f10x.h +..\obj\flash.o: ..\CORE\core_cm3.h +..\obj\flash.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\flash.o: ..\USER\system_stm32f10x.h +..\obj\flash.o: ..\USER\stm32f10x_conf.h +..\obj\flash.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\flash.o: ..\USER\stm32f10x.h +..\obj\flash.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\flash.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\flash.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\flash.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\flash.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\flash.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\flash.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\flash.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\flash.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\flash.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\flash.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\flash.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\flash.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\flash.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\flash.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\flash.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\flash.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\flash.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\flash.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\flash.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\flash.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\flash.o: ..\STM32F10x_FWLIB\inc\misc.h +..\obj\flash.o: ..\USER\global.h +..\obj\flash.o: ..\MOUDLE\AFE_SH3673520.h +..\obj\flash.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\string.h diff --git a/OBJ/flash.o b/OBJ/flash.o new file mode 100644 index 0000000..435ce8d Binary files /dev/null and b/OBJ/flash.o differ diff --git a/OBJ/gasgauge.crf b/OBJ/gasgauge.crf new file mode 100644 index 0000000..5a4c9bd Binary files /dev/null and b/OBJ/gasgauge.crf differ diff --git a/OBJ/gasgauge.d b/OBJ/gasgauge.d new file mode 100644 index 0000000..20b382f --- /dev/null +++ b/OBJ/gasgauge.d @@ -0,0 +1,34 @@ +..\obj\gasgauge.o: ..\MOUDLE\GasGauge.c +..\obj\gasgauge.o: ..\USER\stm32f10x.h +..\obj\gasgauge.o: ..\CORE\core_cm3.h +..\obj\gasgauge.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\gasgauge.o: ..\USER\system_stm32f10x.h +..\obj\gasgauge.o: ..\USER\stm32f10x_conf.h +..\obj\gasgauge.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\gasgauge.o: ..\USER\stm32f10x.h +..\obj\gasgauge.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\gasgauge.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\gasgauge.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\gasgauge.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\gasgauge.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\gasgauge.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\gasgauge.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\gasgauge.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\gasgauge.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\gasgauge.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\gasgauge.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\gasgauge.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\gasgauge.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\gasgauge.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\gasgauge.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\gasgauge.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\gasgauge.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\gasgauge.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\gasgauge.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\gasgauge.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\gasgauge.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\gasgauge.o: ..\STM32F10x_FWLIB\inc\misc.h +..\obj\gasgauge.o: ..\USER\global.h +..\obj\gasgauge.o: ..\MOUDLE\AFE_SH3673520.h +..\obj\gasgauge.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\string.h +..\obj\gasgauge.o: ..\BSP\rtc.h diff --git a/OBJ/gasgauge.o b/OBJ/gasgauge.o new file mode 100644 index 0000000..f145c1f Binary files /dev/null and b/OBJ/gasgauge.o differ diff --git a/OBJ/global.crf b/OBJ/global.crf new file mode 100644 index 0000000..58011e8 Binary files /dev/null and b/OBJ/global.crf differ diff --git a/OBJ/global.d b/OBJ/global.d new file mode 100644 index 0000000..08419cb --- /dev/null +++ b/OBJ/global.d @@ -0,0 +1,34 @@ +..\obj\global.o: global.c +..\obj\global.o: stm32f10x.h +..\obj\global.o: ..\CORE\core_cm3.h +..\obj\global.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\global.o: system_stm32f10x.h +..\obj\global.o: stm32f10x_conf.h +..\obj\global.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\global.o: ..\USER\stm32f10x.h +..\obj\global.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\global.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\global.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\global.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\global.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\global.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\global.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\global.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\global.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\global.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\global.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\global.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\global.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\global.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\global.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\global.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\global.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\global.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\global.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\global.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\global.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\global.o: ..\STM32F10x_FWLIB\inc\misc.h +..\obj\global.o: global.h +..\obj\global.o: ..\MOUDLE\AFE_SH3673520.h +..\obj\global.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\string.h +..\obj\global.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdio.h diff --git a/OBJ/global.o b/OBJ/global.o new file mode 100644 index 0000000..9b6b369 Binary files /dev/null and b/OBJ/global.o differ diff --git a/OBJ/gpio.crf b/OBJ/gpio.crf new file mode 100644 index 0000000..610995a Binary files /dev/null and b/OBJ/gpio.crf differ diff --git a/OBJ/gpio.d b/OBJ/gpio.d new file mode 100644 index 0000000..7427fbe --- /dev/null +++ b/OBJ/gpio.d @@ -0,0 +1,32 @@ +..\obj\gpio.o: ..\BSP\gpio.c +..\obj\gpio.o: ..\USER\stm32f10x.h +..\obj\gpio.o: ..\CORE\core_cm3.h +..\obj\gpio.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\gpio.o: ..\USER\system_stm32f10x.h +..\obj\gpio.o: ..\USER\stm32f10x_conf.h +..\obj\gpio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\gpio.o: ..\USER\stm32f10x.h +..\obj\gpio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\gpio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\gpio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\gpio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\gpio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\gpio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\gpio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\gpio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\gpio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\gpio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\gpio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\gpio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\gpio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\gpio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\gpio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\gpio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\gpio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\gpio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\gpio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\gpio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\gpio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\gpio.o: ..\STM32F10x_FWLIB\inc\misc.h +..\obj\gpio.o: ..\USER\global.h +..\obj\gpio.o: ..\MOUDLE\AFE_SH3673520.h diff --git a/OBJ/gpio.o b/OBJ/gpio.o new file mode 100644 index 0000000..8788d0e Binary files /dev/null and b/OBJ/gpio.o differ diff --git a/OBJ/h7690c.crf b/OBJ/h7690c.crf new file mode 100644 index 0000000..6eb86af Binary files /dev/null and b/OBJ/h7690c.crf differ diff --git a/OBJ/h7690c.d b/OBJ/h7690c.d new file mode 100644 index 0000000..9ebd1e7 --- /dev/null +++ b/OBJ/h7690c.d @@ -0,0 +1,37 @@ +..\obj\h7690c.o: ..\MOUDLE\H7690C.c +..\obj\h7690c.o: ..\USER\stm32f10x.h +..\obj\h7690c.o: ..\CORE\core_cm3.h +..\obj\h7690c.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\h7690c.o: ..\USER\system_stm32f10x.h +..\obj\h7690c.o: ..\USER\stm32f10x_conf.h +..\obj\h7690c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\h7690c.o: ..\USER\stm32f10x.h +..\obj\h7690c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\h7690c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\h7690c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\h7690c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\h7690c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\h7690c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\h7690c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\h7690c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\h7690c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\h7690c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\h7690c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\h7690c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\h7690c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\h7690c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\h7690c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\h7690c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\h7690c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\h7690c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\h7690c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\h7690c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\h7690c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\h7690c.o: ..\STM32F10x_FWLIB\inc\misc.h +..\obj\h7690c.o: ..\USER\global.h +..\obj\h7690c.o: ..\MOUDLE\AFE_SH3673520.h +..\obj\h7690c.o: ..\BSP\rtc.h +..\obj\h7690c.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\string.h +..\obj\h7690c.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdarg.h +..\obj\h7690c.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdio.h +..\obj\h7690c.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdlib.h diff --git a/OBJ/h7690c.o b/OBJ/h7690c.o new file mode 100644 index 0000000..8d743b6 Binary files /dev/null and b/OBJ/h7690c.o differ diff --git a/OBJ/i2c.crf b/OBJ/i2c.crf new file mode 100644 index 0000000..0fc5159 Binary files /dev/null and b/OBJ/i2c.crf differ diff --git a/OBJ/i2c.d b/OBJ/i2c.d new file mode 100644 index 0000000..94f93bd --- /dev/null +++ b/OBJ/i2c.d @@ -0,0 +1,35 @@ +..\obj\i2c.o: ..\BSP\i2c.c +..\obj\i2c.o: ..\USER\stm32f10x.h +..\obj\i2c.o: ..\CORE\core_cm3.h +..\obj\i2c.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\i2c.o: ..\USER\system_stm32f10x.h +..\obj\i2c.o: ..\USER\stm32f10x_conf.h +..\obj\i2c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\i2c.o: ..\USER\stm32f10x.h +..\obj\i2c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\i2c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\i2c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\i2c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\i2c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\i2c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\i2c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\i2c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\i2c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\i2c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\i2c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\i2c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\i2c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\i2c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\i2c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\i2c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\i2c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\i2c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\i2c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\i2c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\i2c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\i2c.o: ..\STM32F10x_FWLIB\inc\misc.h +..\obj\i2c.o: ..\USER\global.h +..\obj\i2c.o: ..\MOUDLE\AFE_SH3673520.h +..\obj\i2c.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\string.h +..\obj\i2c.o: ..\BSP\sys.h +..\obj\i2c.o: ..\MOUDLE\soe.h diff --git a/OBJ/i2c.o b/OBJ/i2c.o new file mode 100644 index 0000000..2b9c1ac Binary files /dev/null and b/OBJ/i2c.o differ diff --git a/OBJ/lbs_transmit.crf b/OBJ/lbs_transmit.crf new file mode 100644 index 0000000..0f1112e Binary files /dev/null and b/OBJ/lbs_transmit.crf differ diff --git a/OBJ/lbs_transmit.d b/OBJ/lbs_transmit.d new file mode 100644 index 0000000..d92b48f --- /dev/null +++ b/OBJ/lbs_transmit.d @@ -0,0 +1,33 @@ +..\obj\lbs_transmit.o: ..\MOUDLE\LBS_Transmit.c +..\obj\lbs_transmit.o: ..\USER\stm32f10x.h +..\obj\lbs_transmit.o: ..\CORE\core_cm3.h +..\obj\lbs_transmit.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\lbs_transmit.o: ..\USER\system_stm32f10x.h +..\obj\lbs_transmit.o: ..\USER\stm32f10x_conf.h +..\obj\lbs_transmit.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\lbs_transmit.o: ..\USER\stm32f10x.h +..\obj\lbs_transmit.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\lbs_transmit.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\lbs_transmit.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\lbs_transmit.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\lbs_transmit.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\lbs_transmit.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\lbs_transmit.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\lbs_transmit.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\lbs_transmit.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\lbs_transmit.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\lbs_transmit.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\lbs_transmit.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\lbs_transmit.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\lbs_transmit.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\lbs_transmit.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\lbs_transmit.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\lbs_transmit.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\lbs_transmit.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\lbs_transmit.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\lbs_transmit.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\lbs_transmit.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\lbs_transmit.o: ..\STM32F10x_FWLIB\inc\misc.h +..\obj\lbs_transmit.o: ..\USER\global.h +..\obj\lbs_transmit.o: ..\MOUDLE\AFE_SH3673520.h +..\obj\lbs_transmit.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\math.h diff --git a/OBJ/lbs_transmit.o b/OBJ/lbs_transmit.o new file mode 100644 index 0000000..df7e804 Binary files /dev/null and b/OBJ/lbs_transmit.o differ diff --git a/OBJ/main.crf b/OBJ/main.crf new file mode 100644 index 0000000..7020da9 Binary files /dev/null and b/OBJ/main.crf differ diff --git a/OBJ/main.d b/OBJ/main.d new file mode 100644 index 0000000..033e1b2 --- /dev/null +++ b/OBJ/main.d @@ -0,0 +1,34 @@ +..\obj\main.o: main.c +..\obj\main.o: stm32f10x.h +..\obj\main.o: ..\CORE\core_cm3.h +..\obj\main.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\main.o: system_stm32f10x.h +..\obj\main.o: stm32f10x_conf.h +..\obj\main.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\main.o: ..\USER\stm32f10x.h +..\obj\main.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\main.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\main.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\main.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\main.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\main.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\main.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\main.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\main.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\main.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\main.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\main.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\main.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\main.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\main.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\main.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\main.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\main.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\main.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\main.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\main.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\main.o: ..\STM32F10x_FWLIB\inc\misc.h +..\obj\main.o: global.h +..\obj\main.o: ..\MOUDLE\AFE_SH3673520.h +..\obj\main.o: ..\BSP\rtc.h +..\obj\main.o: ..\MOUDLE\soe.h diff --git a/OBJ/main.o b/OBJ/main.o new file mode 100644 index 0000000..5f3a53d Binary files /dev/null and b/OBJ/main.o differ diff --git a/OBJ/mbo26a.crf b/OBJ/mbo26a.crf new file mode 100644 index 0000000..4333a8d Binary files /dev/null and b/OBJ/mbo26a.crf differ diff --git a/OBJ/mbo26a.d b/OBJ/mbo26a.d new file mode 100644 index 0000000..c737517 --- /dev/null +++ b/OBJ/mbo26a.d @@ -0,0 +1,35 @@ +..\obj\mbo26a.o: ..\MOUDLE\MBO26A.c +..\obj\mbo26a.o: ..\USER\stm32f10x.h +..\obj\mbo26a.o: ..\CORE\core_cm3.h +..\obj\mbo26a.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\mbo26a.o: ..\USER\system_stm32f10x.h +..\obj\mbo26a.o: ..\USER\stm32f10x_conf.h +..\obj\mbo26a.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\mbo26a.o: ..\USER\stm32f10x.h +..\obj\mbo26a.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\mbo26a.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\mbo26a.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\mbo26a.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\mbo26a.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\mbo26a.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\mbo26a.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\mbo26a.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\mbo26a.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\mbo26a.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\mbo26a.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\mbo26a.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\mbo26a.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\mbo26a.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\mbo26a.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\mbo26a.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\mbo26a.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\mbo26a.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\mbo26a.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\mbo26a.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\mbo26a.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\mbo26a.o: ..\STM32F10x_FWLIB\inc\misc.h +..\obj\mbo26a.o: ..\USER\global.h +..\obj\mbo26a.o: ..\MOUDLE\AFE_SH3673520.h +..\obj\mbo26a.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\string.h +..\obj\mbo26a.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdarg.h +..\obj\mbo26a.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdio.h diff --git a/OBJ/mbo26a.o b/OBJ/mbo26a.o new file mode 100644 index 0000000..eb2e55f Binary files /dev/null and b/OBJ/mbo26a.o differ diff --git a/OBJ/misc.crf b/OBJ/misc.crf new file mode 100644 index 0000000..694abae Binary files /dev/null and b/OBJ/misc.crf differ diff --git a/OBJ/misc.d b/OBJ/misc.d new file mode 100644 index 0000000..9eb5c77 --- /dev/null +++ b/OBJ/misc.d @@ -0,0 +1,31 @@ +..\obj\misc.o: ..\STM32F10x_FWLIB\src\misc.c +..\obj\misc.o: ..\STM32F10x_FWLIB\inc\misc.h +..\obj\misc.o: ..\USER\stm32f10x.h +..\obj\misc.o: ..\CORE\core_cm3.h +..\obj\misc.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\misc.o: ..\USER\system_stm32f10x.h +..\obj\misc.o: ..\USER\stm32f10x_conf.h +..\obj\misc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\misc.o: ..\USER\stm32f10x.h +..\obj\misc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\misc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\misc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\misc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\misc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\misc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\misc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\misc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\misc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\misc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\misc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\misc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\misc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\misc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\misc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\misc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\misc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\misc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\misc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\misc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\misc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\misc.o: ..\STM32F10x_FWLIB\inc\misc.h diff --git a/OBJ/misc.o b/OBJ/misc.o new file mode 100644 index 0000000..c2138c5 Binary files /dev/null and b/OBJ/misc.o differ diff --git a/OBJ/ntc.crf b/OBJ/ntc.crf new file mode 100644 index 0000000..cdff479 Binary files /dev/null and b/OBJ/ntc.crf differ diff --git a/OBJ/ntc.d b/OBJ/ntc.d new file mode 100644 index 0000000..d1d620f --- /dev/null +++ b/OBJ/ntc.d @@ -0,0 +1,32 @@ +..\obj\ntc.o: ..\MOUDLE\NTC.c +..\obj\ntc.o: ..\USER\stm32f10x.h +..\obj\ntc.o: ..\CORE\core_cm3.h +..\obj\ntc.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\ntc.o: ..\USER\system_stm32f10x.h +..\obj\ntc.o: ..\USER\stm32f10x_conf.h +..\obj\ntc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\ntc.o: ..\USER\stm32f10x.h +..\obj\ntc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\ntc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\ntc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\ntc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\ntc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\ntc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\ntc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\ntc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\ntc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\ntc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\ntc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\ntc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\ntc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\ntc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\ntc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\ntc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\ntc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\ntc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\ntc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\ntc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\ntc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\ntc.o: ..\STM32F10x_FWLIB\inc\misc.h +..\obj\ntc.o: ..\USER\global.h +..\obj\ntc.o: ..\MOUDLE\AFE_SH3673520.h diff --git a/OBJ/ntc.o b/OBJ/ntc.o new file mode 100644 index 0000000..b20b6a6 Binary files /dev/null and b/OBJ/ntc.o differ diff --git a/OBJ/ocv.crf b/OBJ/ocv.crf new file mode 100644 index 0000000..5c243f2 Binary files /dev/null and b/OBJ/ocv.crf differ diff --git a/OBJ/ocv.d b/OBJ/ocv.d new file mode 100644 index 0000000..d4c1c97 --- /dev/null +++ b/OBJ/ocv.d @@ -0,0 +1,32 @@ +..\obj\ocv.o: ..\MOUDLE\OCV.c +..\obj\ocv.o: ..\USER\stm32f10x.h +..\obj\ocv.o: ..\CORE\core_cm3.h +..\obj\ocv.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\ocv.o: ..\USER\system_stm32f10x.h +..\obj\ocv.o: ..\USER\stm32f10x_conf.h +..\obj\ocv.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\ocv.o: ..\USER\stm32f10x.h +..\obj\ocv.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\ocv.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\ocv.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\ocv.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\ocv.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\ocv.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\ocv.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\ocv.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\ocv.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\ocv.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\ocv.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\ocv.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\ocv.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\ocv.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\ocv.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\ocv.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\ocv.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\ocv.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\ocv.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\ocv.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\ocv.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\ocv.o: ..\STM32F10x_FWLIB\inc\misc.h +..\obj\ocv.o: ..\USER\global.h +..\obj\ocv.o: ..\MOUDLE\AFE_SH3673520.h diff --git a/OBJ/ocv.o b/OBJ/ocv.o new file mode 100644 index 0000000..66aada4 Binary files /dev/null and b/OBJ/ocv.o differ diff --git a/OBJ/ota.crf b/OBJ/ota.crf new file mode 100644 index 0000000..9fcccb4 Binary files /dev/null and b/OBJ/ota.crf differ diff --git a/OBJ/ota.d b/OBJ/ota.d new file mode 100644 index 0000000..b946824 --- /dev/null +++ b/OBJ/ota.d @@ -0,0 +1,34 @@ +..\obj\ota.o: ..\MOUDLE\OTA.c +..\obj\ota.o: ..\USER\stm32f10x.h +..\obj\ota.o: ..\CORE\core_cm3.h +..\obj\ota.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\ota.o: ..\USER\system_stm32f10x.h +..\obj\ota.o: ..\USER\stm32f10x_conf.h +..\obj\ota.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\ota.o: ..\USER\stm32f10x.h +..\obj\ota.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\ota.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\ota.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\ota.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\ota.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\ota.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\ota.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\ota.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\ota.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\ota.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\ota.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\ota.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\ota.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\ota.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\ota.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\ota.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\ota.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\ota.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\ota.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\ota.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\ota.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\ota.o: ..\STM32F10x_FWLIB\inc\misc.h +..\obj\ota.o: ..\USER\global.h +..\obj\ota.o: ..\MOUDLE\AFE_SH3673520.h +..\obj\ota.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\string.h +..\obj\ota.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdio.h diff --git a/OBJ/ota.o b/OBJ/ota.o new file mode 100644 index 0000000..7ba1180 Binary files /dev/null and b/OBJ/ota.o differ diff --git a/OBJ/protocolswitch_p1.crf b/OBJ/protocolswitch_p1.crf new file mode 100644 index 0000000..fdc406b Binary files /dev/null and b/OBJ/protocolswitch_p1.crf differ diff --git a/OBJ/protocolswitch_p1.d b/OBJ/protocolswitch_p1.d new file mode 100644 index 0000000..463d3ff --- /dev/null +++ b/OBJ/protocolswitch_p1.d @@ -0,0 +1,32 @@ +..\obj\protocolswitch_p1.o: ..\PROTOCOL\ProtocolSwitch_P1.c +..\obj\protocolswitch_p1.o: ..\USER\stm32f10x.h +..\obj\protocolswitch_p1.o: ..\CORE\core_cm3.h +..\obj\protocolswitch_p1.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\protocolswitch_p1.o: ..\USER\system_stm32f10x.h +..\obj\protocolswitch_p1.o: ..\USER\stm32f10x_conf.h +..\obj\protocolswitch_p1.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\protocolswitch_p1.o: ..\USER\stm32f10x.h +..\obj\protocolswitch_p1.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\protocolswitch_p1.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\protocolswitch_p1.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\protocolswitch_p1.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\protocolswitch_p1.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\protocolswitch_p1.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\protocolswitch_p1.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\protocolswitch_p1.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\protocolswitch_p1.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\protocolswitch_p1.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\protocolswitch_p1.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\protocolswitch_p1.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\protocolswitch_p1.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\protocolswitch_p1.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\protocolswitch_p1.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\protocolswitch_p1.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\protocolswitch_p1.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\protocolswitch_p1.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\protocolswitch_p1.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\protocolswitch_p1.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\protocolswitch_p1.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\protocolswitch_p1.o: ..\STM32F10x_FWLIB\inc\misc.h +..\obj\protocolswitch_p1.o: ..\USER\global.h +..\obj\protocolswitch_p1.o: ..\MOUDLE\AFE_SH3673520.h diff --git a/OBJ/protocolswitch_p1.o b/OBJ/protocolswitch_p1.o new file mode 100644 index 0000000..08be408 Binary files /dev/null and b/OBJ/protocolswitch_p1.o differ diff --git a/OBJ/protocolswitch_p2.crf b/OBJ/protocolswitch_p2.crf new file mode 100644 index 0000000..0f2dd6b Binary files /dev/null and b/OBJ/protocolswitch_p2.crf differ diff --git a/OBJ/protocolswitch_p2.d b/OBJ/protocolswitch_p2.d new file mode 100644 index 0000000..fa72d6c --- /dev/null +++ b/OBJ/protocolswitch_p2.d @@ -0,0 +1,32 @@ +..\obj\protocolswitch_p2.o: ..\PROTOCOL\ProtocolSwitch_P2.c +..\obj\protocolswitch_p2.o: ..\USER\stm32f10x.h +..\obj\protocolswitch_p2.o: ..\CORE\core_cm3.h +..\obj\protocolswitch_p2.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\protocolswitch_p2.o: ..\USER\system_stm32f10x.h +..\obj\protocolswitch_p2.o: ..\USER\stm32f10x_conf.h +..\obj\protocolswitch_p2.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\protocolswitch_p2.o: ..\USER\stm32f10x.h +..\obj\protocolswitch_p2.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\protocolswitch_p2.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\protocolswitch_p2.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\protocolswitch_p2.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\protocolswitch_p2.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\protocolswitch_p2.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\protocolswitch_p2.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\protocolswitch_p2.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\protocolswitch_p2.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\protocolswitch_p2.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\protocolswitch_p2.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\protocolswitch_p2.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\protocolswitch_p2.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\protocolswitch_p2.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\protocolswitch_p2.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\protocolswitch_p2.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\protocolswitch_p2.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\protocolswitch_p2.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\protocolswitch_p2.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\protocolswitch_p2.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\protocolswitch_p2.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\protocolswitch_p2.o: ..\STM32F10x_FWLIB\inc\misc.h +..\obj\protocolswitch_p2.o: ..\USER\global.h +..\obj\protocolswitch_p2.o: ..\MOUDLE\AFE_SH3673520.h diff --git a/OBJ/protocolswitch_p2.o b/OBJ/protocolswitch_p2.o new file mode 100644 index 0000000..9222147 Binary files /dev/null and b/OBJ/protocolswitch_p2.o differ diff --git a/OBJ/protocolswitch_p3.crf b/OBJ/protocolswitch_p3.crf new file mode 100644 index 0000000..7045f49 Binary files /dev/null and b/OBJ/protocolswitch_p3.crf differ diff --git a/OBJ/protocolswitch_p3.d b/OBJ/protocolswitch_p3.d new file mode 100644 index 0000000..000de26 --- /dev/null +++ b/OBJ/protocolswitch_p3.d @@ -0,0 +1,31 @@ +..\obj\protocolswitch_p3.o: ..\PROTOCOL\ProtocolSwitch_P3.c +..\obj\protocolswitch_p3.o: ..\USER\stm32f10x.h +..\obj\protocolswitch_p3.o: ..\CORE\core_cm3.h +..\obj\protocolswitch_p3.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\protocolswitch_p3.o: ..\USER\system_stm32f10x.h +..\obj\protocolswitch_p3.o: ..\USER\stm32f10x_conf.h +..\obj\protocolswitch_p3.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\protocolswitch_p3.o: ..\USER\stm32f10x.h +..\obj\protocolswitch_p3.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\protocolswitch_p3.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\protocolswitch_p3.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\protocolswitch_p3.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\protocolswitch_p3.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\protocolswitch_p3.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\protocolswitch_p3.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\protocolswitch_p3.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\protocolswitch_p3.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\protocolswitch_p3.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\protocolswitch_p3.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\protocolswitch_p3.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\protocolswitch_p3.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\protocolswitch_p3.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\protocolswitch_p3.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\protocolswitch_p3.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\protocolswitch_p3.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\protocolswitch_p3.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\protocolswitch_p3.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\protocolswitch_p3.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\protocolswitch_p3.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\protocolswitch_p3.o: ..\STM32F10x_FWLIB\inc\misc.h +..\obj\protocolswitch_p3.o: ..\USER\global.h diff --git a/OBJ/protocolswitch_p3.o b/OBJ/protocolswitch_p3.o new file mode 100644 index 0000000..79811fb Binary files /dev/null and b/OBJ/protocolswitch_p3.o differ diff --git a/OBJ/protocolswitch_p4.crf b/OBJ/protocolswitch_p4.crf new file mode 100644 index 0000000..95b39e3 Binary files /dev/null and b/OBJ/protocolswitch_p4.crf differ diff --git a/OBJ/protocolswitch_p4.d b/OBJ/protocolswitch_p4.d new file mode 100644 index 0000000..cc9362c --- /dev/null +++ b/OBJ/protocolswitch_p4.d @@ -0,0 +1,31 @@ +..\obj\protocolswitch_p4.o: ..\PROTOCOL\ProtocolSwitch_P4.c +..\obj\protocolswitch_p4.o: ..\USER\stm32f10x.h +..\obj\protocolswitch_p4.o: ..\CORE\core_cm3.h +..\obj\protocolswitch_p4.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\protocolswitch_p4.o: ..\USER\system_stm32f10x.h +..\obj\protocolswitch_p4.o: ..\USER\stm32f10x_conf.h +..\obj\protocolswitch_p4.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\protocolswitch_p4.o: ..\USER\stm32f10x.h +..\obj\protocolswitch_p4.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\protocolswitch_p4.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\protocolswitch_p4.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\protocolswitch_p4.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\protocolswitch_p4.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\protocolswitch_p4.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\protocolswitch_p4.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\protocolswitch_p4.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\protocolswitch_p4.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\protocolswitch_p4.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\protocolswitch_p4.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\protocolswitch_p4.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\protocolswitch_p4.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\protocolswitch_p4.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\protocolswitch_p4.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\protocolswitch_p4.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\protocolswitch_p4.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\protocolswitch_p4.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\protocolswitch_p4.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\protocolswitch_p4.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\protocolswitch_p4.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\protocolswitch_p4.o: ..\STM32F10x_FWLIB\inc\misc.h +..\obj\protocolswitch_p4.o: ..\USER\global.h diff --git a/OBJ/protocolswitch_p4.o b/OBJ/protocolswitch_p4.o new file mode 100644 index 0000000..ee92622 Binary files /dev/null and b/OBJ/protocolswitch_p4.o differ diff --git a/OBJ/protocolswitch_p5.crf b/OBJ/protocolswitch_p5.crf new file mode 100644 index 0000000..bcdfa88 Binary files /dev/null and b/OBJ/protocolswitch_p5.crf differ diff --git a/OBJ/protocolswitch_p5.d b/OBJ/protocolswitch_p5.d new file mode 100644 index 0000000..d12d767 --- /dev/null +++ b/OBJ/protocolswitch_p5.d @@ -0,0 +1,31 @@ +..\obj\protocolswitch_p5.o: ..\PROTOCOL\ProtocolSwitch_P5.c +..\obj\protocolswitch_p5.o: ..\USER\stm32f10x.h +..\obj\protocolswitch_p5.o: ..\CORE\core_cm3.h +..\obj\protocolswitch_p5.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\protocolswitch_p5.o: ..\USER\system_stm32f10x.h +..\obj\protocolswitch_p5.o: ..\USER\stm32f10x_conf.h +..\obj\protocolswitch_p5.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\protocolswitch_p5.o: ..\USER\stm32f10x.h +..\obj\protocolswitch_p5.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\protocolswitch_p5.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\protocolswitch_p5.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\protocolswitch_p5.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\protocolswitch_p5.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\protocolswitch_p5.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\protocolswitch_p5.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\protocolswitch_p5.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\protocolswitch_p5.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\protocolswitch_p5.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\protocolswitch_p5.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\protocolswitch_p5.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\protocolswitch_p5.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\protocolswitch_p5.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\protocolswitch_p5.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\protocolswitch_p5.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\protocolswitch_p5.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\protocolswitch_p5.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\protocolswitch_p5.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\protocolswitch_p5.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\protocolswitch_p5.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\protocolswitch_p5.o: ..\STM32F10x_FWLIB\inc\misc.h +..\obj\protocolswitch_p5.o: ..\USER\global.h diff --git a/OBJ/protocolswitch_p5.o b/OBJ/protocolswitch_p5.o new file mode 100644 index 0000000..c9f69e5 Binary files /dev/null and b/OBJ/protocolswitch_p5.o differ diff --git a/OBJ/pwm.crf b/OBJ/pwm.crf new file mode 100644 index 0000000..a200117 Binary files /dev/null and b/OBJ/pwm.crf differ diff --git a/OBJ/pwm.d b/OBJ/pwm.d new file mode 100644 index 0000000..227dfca --- /dev/null +++ b/OBJ/pwm.d @@ -0,0 +1,32 @@ +..\obj\pwm.o: ..\BSP\pwm.c +..\obj\pwm.o: ..\USER\stm32f10x.h +..\obj\pwm.o: ..\CORE\core_cm3.h +..\obj\pwm.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\pwm.o: ..\USER\system_stm32f10x.h +..\obj\pwm.o: ..\USER\stm32f10x_conf.h +..\obj\pwm.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\pwm.o: ..\USER\stm32f10x.h +..\obj\pwm.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\pwm.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\pwm.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\pwm.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\pwm.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\pwm.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\pwm.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\pwm.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\pwm.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\pwm.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\pwm.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\pwm.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\pwm.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\pwm.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\pwm.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\pwm.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\pwm.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\pwm.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\pwm.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\pwm.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\pwm.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\pwm.o: ..\STM32F10x_FWLIB\inc\misc.h +..\obj\pwm.o: ..\USER\global.h +..\obj\pwm.o: ..\MOUDLE\AFE_SH3673520.h diff --git a/OBJ/pwm.o b/OBJ/pwm.o new file mode 100644 index 0000000..dd03f0e Binary files /dev/null and b/OBJ/pwm.o differ diff --git a/OBJ/rs485_modbus.crf b/OBJ/rs485_modbus.crf new file mode 100644 index 0000000..32c2008 Binary files /dev/null and b/OBJ/rs485_modbus.crf differ diff --git a/OBJ/rs485_modbus.d b/OBJ/rs485_modbus.d new file mode 100644 index 0000000..316341d --- /dev/null +++ b/OBJ/rs485_modbus.d @@ -0,0 +1,35 @@ +..\obj\rs485_modbus.o: ..\MOUDLE\RS485_Modbus.c +..\obj\rs485_modbus.o: ..\USER\stm32f10x.h +..\obj\rs485_modbus.o: ..\CORE\core_cm3.h +..\obj\rs485_modbus.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\rs485_modbus.o: ..\USER\system_stm32f10x.h +..\obj\rs485_modbus.o: ..\USER\stm32f10x_conf.h +..\obj\rs485_modbus.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\rs485_modbus.o: ..\USER\stm32f10x.h +..\obj\rs485_modbus.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\rs485_modbus.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\rs485_modbus.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\rs485_modbus.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\rs485_modbus.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\rs485_modbus.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\rs485_modbus.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\rs485_modbus.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\rs485_modbus.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\rs485_modbus.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\rs485_modbus.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\rs485_modbus.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\rs485_modbus.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\rs485_modbus.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\rs485_modbus.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\rs485_modbus.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\rs485_modbus.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\rs485_modbus.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\rs485_modbus.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\rs485_modbus.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\rs485_modbus.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\rs485_modbus.o: ..\STM32F10x_FWLIB\inc\misc.h +..\obj\rs485_modbus.o: ..\USER\global.h +..\obj\rs485_modbus.o: ..\MOUDLE\AFE_SH3673520.h +..\obj\rs485_modbus.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\string.h +..\obj\rs485_modbus.o: ..\BSP\rtc.h +..\obj\rs485_modbus.o: ..\MOUDLE\soe.h diff --git a/OBJ/rs485_modbus.o b/OBJ/rs485_modbus.o new file mode 100644 index 0000000..c693609 Binary files /dev/null and b/OBJ/rs485_modbus.o differ diff --git a/OBJ/rs485_modbus_inverter.crf b/OBJ/rs485_modbus_inverter.crf new file mode 100644 index 0000000..e60a067 Binary files /dev/null and b/OBJ/rs485_modbus_inverter.crf differ diff --git a/OBJ/rs485_modbus_inverter.d b/OBJ/rs485_modbus_inverter.d new file mode 100644 index 0000000..2c86b4c --- /dev/null +++ b/OBJ/rs485_modbus_inverter.d @@ -0,0 +1,35 @@ +..\obj\rs485_modbus_inverter.o: ..\MOUDLE\RS485_Modbus_Inverter.c +..\obj\rs485_modbus_inverter.o: ..\USER\stm32f10x.h +..\obj\rs485_modbus_inverter.o: ..\CORE\core_cm3.h +..\obj\rs485_modbus_inverter.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\rs485_modbus_inverter.o: ..\USER\system_stm32f10x.h +..\obj\rs485_modbus_inverter.o: ..\USER\stm32f10x_conf.h +..\obj\rs485_modbus_inverter.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\rs485_modbus_inverter.o: ..\USER\stm32f10x.h +..\obj\rs485_modbus_inverter.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\rs485_modbus_inverter.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\rs485_modbus_inverter.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\rs485_modbus_inverter.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\rs485_modbus_inverter.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\rs485_modbus_inverter.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\rs485_modbus_inverter.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\rs485_modbus_inverter.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\rs485_modbus_inverter.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\rs485_modbus_inverter.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\rs485_modbus_inverter.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\rs485_modbus_inverter.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\rs485_modbus_inverter.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\rs485_modbus_inverter.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\rs485_modbus_inverter.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\rs485_modbus_inverter.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\rs485_modbus_inverter.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\rs485_modbus_inverter.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\rs485_modbus_inverter.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\rs485_modbus_inverter.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\rs485_modbus_inverter.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\rs485_modbus_inverter.o: ..\STM32F10x_FWLIB\inc\misc.h +..\obj\rs485_modbus_inverter.o: ..\USER\global.h +..\obj\rs485_modbus_inverter.o: ..\MOUDLE\AFE_SH3673520.h +..\obj\rs485_modbus_inverter.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\string.h +..\obj\rs485_modbus_inverter.o: ..\BSP\rtc.h +..\obj\rs485_modbus_inverter.o: ..\MOUDLE\soe.h diff --git a/OBJ/rs485_modbus_inverter.o b/OBJ/rs485_modbus_inverter.o new file mode 100644 index 0000000..da36d99 Binary files /dev/null and b/OBJ/rs485_modbus_inverter.o differ diff --git a/OBJ/rtc.crf b/OBJ/rtc.crf new file mode 100644 index 0000000..a9b7311 Binary files /dev/null and b/OBJ/rtc.crf differ diff --git a/OBJ/rtc.d b/OBJ/rtc.d new file mode 100644 index 0000000..592850b --- /dev/null +++ b/OBJ/rtc.d @@ -0,0 +1,33 @@ +..\obj\rtc.o: ..\BSP\rtc.c +..\obj\rtc.o: ..\USER\stm32f10x.h +..\obj\rtc.o: ..\CORE\core_cm3.h +..\obj\rtc.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\rtc.o: ..\USER\system_stm32f10x.h +..\obj\rtc.o: ..\USER\stm32f10x_conf.h +..\obj\rtc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\rtc.o: ..\USER\stm32f10x.h +..\obj\rtc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\rtc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\rtc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\rtc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\rtc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\rtc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\rtc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\rtc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\rtc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\rtc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\rtc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\rtc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\rtc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\rtc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\rtc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\rtc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\rtc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\rtc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\rtc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\rtc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\rtc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\rtc.o: ..\STM32F10x_FWLIB\inc\misc.h +..\obj\rtc.o: ..\BSP\rtc.h +..\obj\rtc.o: ..\USER\global.h +..\obj\rtc.o: ..\MOUDLE\AFE_SH3673520.h diff --git a/OBJ/rtc.o b/OBJ/rtc.o new file mode 100644 index 0000000..6c46dfa Binary files /dev/null and b/OBJ/rtc.o differ diff --git a/OBJ/screen.crf b/OBJ/screen.crf new file mode 100644 index 0000000..b0dac42 Binary files /dev/null and b/OBJ/screen.crf differ diff --git a/OBJ/screen.d b/OBJ/screen.d new file mode 100644 index 0000000..26d5f80 --- /dev/null +++ b/OBJ/screen.d @@ -0,0 +1,37 @@ +..\obj\screen.o: ..\MOUDLE\Screen.c +..\obj\screen.o: ..\USER\stm32f10x.h +..\obj\screen.o: ..\CORE\core_cm3.h +..\obj\screen.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\screen.o: ..\USER\system_stm32f10x.h +..\obj\screen.o: ..\USER\stm32f10x_conf.h +..\obj\screen.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\screen.o: ..\USER\stm32f10x.h +..\obj\screen.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\screen.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\screen.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\screen.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\screen.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\screen.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\screen.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\screen.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\screen.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\screen.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\screen.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\screen.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\screen.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\screen.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\screen.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\screen.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\screen.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\screen.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\screen.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\screen.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\screen.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\screen.o: ..\STM32F10x_FWLIB\inc\misc.h +..\obj\screen.o: ..\USER\global.h +..\obj\screen.o: ..\MOUDLE\AFE_SH3673520.h +..\obj\screen.o: ..\BSP\rtc.h +..\obj\screen.o: ..\MOUDLE\soe.h +..\obj\screen.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\string.h +..\obj\screen.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdarg.h +..\obj\screen.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdio.h diff --git a/OBJ/screen.o b/OBJ/screen.o new file mode 100644 index 0000000..9965c21 Binary files /dev/null and b/OBJ/screen.o differ diff --git a/OBJ/sdwa.crf b/OBJ/sdwa.crf new file mode 100644 index 0000000..e9c8980 Binary files /dev/null and b/OBJ/sdwa.crf differ diff --git a/OBJ/sdwa.d b/OBJ/sdwa.d new file mode 100644 index 0000000..04ef58e --- /dev/null +++ b/OBJ/sdwa.d @@ -0,0 +1,35 @@ +..\obj\sdwa.o: ..\MOUDLE\SDWA.c +..\obj\sdwa.o: ..\USER\stm32f10x.h +..\obj\sdwa.o: ..\CORE\core_cm3.h +..\obj\sdwa.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\sdwa.o: ..\USER\system_stm32f10x.h +..\obj\sdwa.o: ..\USER\stm32f10x_conf.h +..\obj\sdwa.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\sdwa.o: ..\USER\stm32f10x.h +..\obj\sdwa.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\sdwa.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\sdwa.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\sdwa.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\sdwa.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\sdwa.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\sdwa.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\sdwa.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\sdwa.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\sdwa.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\sdwa.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\sdwa.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\sdwa.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\sdwa.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\sdwa.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\sdwa.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\sdwa.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\sdwa.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\sdwa.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\sdwa.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\sdwa.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\sdwa.o: ..\STM32F10x_FWLIB\inc\misc.h +..\obj\sdwa.o: ..\USER\global.h +..\obj\sdwa.o: ..\BSP\rtc.h +..\obj\sdwa.o: ..\MOUDLE\soe.h +..\obj\sdwa.o: ..\MOUDLE\AFE_SH367309.h +..\obj\sdwa.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\string.h diff --git a/OBJ/sdwa.o b/OBJ/sdwa.o new file mode 100644 index 0000000..92ca887 Binary files /dev/null and b/OBJ/sdwa.o differ diff --git a/OBJ/soe.crf b/OBJ/soe.crf new file mode 100644 index 0000000..c74efe0 Binary files /dev/null and b/OBJ/soe.crf differ diff --git a/OBJ/soe.d b/OBJ/soe.d new file mode 100644 index 0000000..dc77cac --- /dev/null +++ b/OBJ/soe.d @@ -0,0 +1,35 @@ +..\obj\soe.o: ..\MOUDLE\SOE.c +..\obj\soe.o: ..\USER\stm32f10x.h +..\obj\soe.o: ..\CORE\core_cm3.h +..\obj\soe.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\soe.o: ..\USER\system_stm32f10x.h +..\obj\soe.o: ..\USER\stm32f10x_conf.h +..\obj\soe.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\soe.o: ..\USER\stm32f10x.h +..\obj\soe.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\soe.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\soe.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\soe.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\soe.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\soe.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\soe.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\soe.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\soe.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\soe.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\soe.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\soe.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\soe.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\soe.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\soe.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\soe.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\soe.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\soe.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\soe.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\soe.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\soe.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\soe.o: ..\STM32F10x_FWLIB\inc\misc.h +..\obj\soe.o: ..\USER\global.h +..\obj\soe.o: ..\MOUDLE\AFE_SH3673520.h +..\obj\soe.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\string.h +..\obj\soe.o: ..\BSP\rtc.h +..\obj\soe.o: ..\MOUDLE\soe.h diff --git a/OBJ/soe.o b/OBJ/soe.o new file mode 100644 index 0000000..429d0b8 Binary files /dev/null and b/OBJ/soe.o differ diff --git a/OBJ/spi.crf b/OBJ/spi.crf new file mode 100644 index 0000000..c0f2e5f Binary files /dev/null and b/OBJ/spi.crf differ diff --git a/OBJ/spi.d b/OBJ/spi.d new file mode 100644 index 0000000..7314ace --- /dev/null +++ b/OBJ/spi.d @@ -0,0 +1,32 @@ +..\obj\spi.o: ..\BSP\spi.c +..\obj\spi.o: ..\USER\stm32f10x.h +..\obj\spi.o: ..\CORE\core_cm3.h +..\obj\spi.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\spi.o: ..\USER\system_stm32f10x.h +..\obj\spi.o: ..\USER\stm32f10x_conf.h +..\obj\spi.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\spi.o: ..\USER\stm32f10x.h +..\obj\spi.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\spi.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\spi.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\spi.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\spi.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\spi.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\spi.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\spi.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\spi.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\spi.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\spi.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\spi.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\spi.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\spi.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\spi.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\spi.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\spi.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\spi.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\spi.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\spi.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\spi.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\spi.o: ..\STM32F10x_FWLIB\inc\misc.h +..\obj\spi.o: ..\USER\global.h +..\obj\spi.o: ..\MOUDLE\AFE_SH3673520.h diff --git a/OBJ/spi.o b/OBJ/spi.o new file mode 100644 index 0000000..af8b20d Binary files /dev/null and b/OBJ/spi.o differ diff --git a/OBJ/startup_stm32f10x_hd.d b/OBJ/startup_stm32f10x_hd.d new file mode 100644 index 0000000..170b3db --- /dev/null +++ b/OBJ/startup_stm32f10x_hd.d @@ -0,0 +1 @@ +..\obj\startup_stm32f10x_hd.o: ..\CORE\startup_stm32f10x_hd.s diff --git a/OBJ/startup_stm32f10x_hd.o b/OBJ/startup_stm32f10x_hd.o new file mode 100644 index 0000000..e22124e Binary files /dev/null and b/OBJ/startup_stm32f10x_hd.o differ diff --git a/OBJ/status.crf b/OBJ/status.crf new file mode 100644 index 0000000..c718f00 Binary files /dev/null and b/OBJ/status.crf differ diff --git a/OBJ/status.d b/OBJ/status.d new file mode 100644 index 0000000..ac1bb71 --- /dev/null +++ b/OBJ/status.d @@ -0,0 +1,33 @@ +..\obj\status.o: ..\MOUDLE\Status.c +..\obj\status.o: ..\USER\stm32f10x.h +..\obj\status.o: ..\CORE\core_cm3.h +..\obj\status.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\status.o: ..\USER\system_stm32f10x.h +..\obj\status.o: ..\USER\stm32f10x_conf.h +..\obj\status.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\status.o: ..\USER\stm32f10x.h +..\obj\status.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\status.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\status.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\status.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\status.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\status.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\status.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\status.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\status.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\status.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\status.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\status.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\status.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\status.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\status.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\status.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\status.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\status.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\status.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\status.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\status.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\status.o: ..\STM32F10x_FWLIB\inc\misc.h +..\obj\status.o: ..\USER\global.h +..\obj\status.o: ..\MOUDLE\AFE_SH3673520.h +..\obj\status.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\string.h diff --git a/OBJ/status.o b/OBJ/status.o new file mode 100644 index 0000000..99d88d0 Binary files /dev/null and b/OBJ/status.o differ diff --git a/OBJ/stm32f10x_adc.crf b/OBJ/stm32f10x_adc.crf new file mode 100644 index 0000000..9bd0696 Binary files /dev/null and b/OBJ/stm32f10x_adc.crf differ diff --git a/OBJ/stm32f10x_adc.d b/OBJ/stm32f10x_adc.d new file mode 100644 index 0000000..c58df39 --- /dev/null +++ b/OBJ/stm32f10x_adc.d @@ -0,0 +1,31 @@ +..\obj\stm32f10x_adc.o: ..\STM32F10x_FWLIB\src\stm32f10x_adc.c +..\obj\stm32f10x_adc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\stm32f10x_adc.o: ..\USER\stm32f10x.h +..\obj\stm32f10x_adc.o: ..\CORE\core_cm3.h +..\obj\stm32f10x_adc.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\stm32f10x_adc.o: ..\USER\system_stm32f10x.h +..\obj\stm32f10x_adc.o: ..\USER\stm32f10x_conf.h +..\obj\stm32f10x_adc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\stm32f10x_adc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\stm32f10x_adc.o: ..\USER\stm32f10x.h +..\obj\stm32f10x_adc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\stm32f10x_adc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\stm32f10x_adc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\stm32f10x_adc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\stm32f10x_adc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\stm32f10x_adc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\stm32f10x_adc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\stm32f10x_adc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\stm32f10x_adc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\stm32f10x_adc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\stm32f10x_adc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\stm32f10x_adc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\stm32f10x_adc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\stm32f10x_adc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\stm32f10x_adc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\stm32f10x_adc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\stm32f10x_adc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\stm32f10x_adc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\stm32f10x_adc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\stm32f10x_adc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\stm32f10x_adc.o: ..\STM32F10x_FWLIB\inc\misc.h diff --git a/OBJ/stm32f10x_adc.o b/OBJ/stm32f10x_adc.o new file mode 100644 index 0000000..3ef8ef8 Binary files /dev/null and b/OBJ/stm32f10x_adc.o differ diff --git a/OBJ/stm32f10x_bkp.crf b/OBJ/stm32f10x_bkp.crf new file mode 100644 index 0000000..6bde0b1 Binary files /dev/null and b/OBJ/stm32f10x_bkp.crf differ diff --git a/OBJ/stm32f10x_bkp.d b/OBJ/stm32f10x_bkp.d new file mode 100644 index 0000000..90424b9 --- /dev/null +++ b/OBJ/stm32f10x_bkp.d @@ -0,0 +1,31 @@ +..\obj\stm32f10x_bkp.o: ..\STM32F10x_FWLIB\src\stm32f10x_bkp.c +..\obj\stm32f10x_bkp.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\stm32f10x_bkp.o: ..\USER\stm32f10x.h +..\obj\stm32f10x_bkp.o: ..\CORE\core_cm3.h +..\obj\stm32f10x_bkp.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\stm32f10x_bkp.o: ..\USER\system_stm32f10x.h +..\obj\stm32f10x_bkp.o: ..\USER\stm32f10x_conf.h +..\obj\stm32f10x_bkp.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\stm32f10x_bkp.o: ..\USER\stm32f10x.h +..\obj\stm32f10x_bkp.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\stm32f10x_bkp.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\stm32f10x_bkp.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\stm32f10x_bkp.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\stm32f10x_bkp.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\stm32f10x_bkp.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\stm32f10x_bkp.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\stm32f10x_bkp.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\stm32f10x_bkp.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\stm32f10x_bkp.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\stm32f10x_bkp.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\stm32f10x_bkp.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\stm32f10x_bkp.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\stm32f10x_bkp.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\stm32f10x_bkp.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\stm32f10x_bkp.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\stm32f10x_bkp.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\stm32f10x_bkp.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\stm32f10x_bkp.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\stm32f10x_bkp.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\stm32f10x_bkp.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\stm32f10x_bkp.o: ..\STM32F10x_FWLIB\inc\misc.h diff --git a/OBJ/stm32f10x_bkp.o b/OBJ/stm32f10x_bkp.o new file mode 100644 index 0000000..823706e Binary files /dev/null and b/OBJ/stm32f10x_bkp.o differ diff --git a/OBJ/stm32f10x_can.crf b/OBJ/stm32f10x_can.crf new file mode 100644 index 0000000..9674487 Binary files /dev/null and b/OBJ/stm32f10x_can.crf differ diff --git a/OBJ/stm32f10x_can.d b/OBJ/stm32f10x_can.d new file mode 100644 index 0000000..ffb02f2 --- /dev/null +++ b/OBJ/stm32f10x_can.d @@ -0,0 +1,31 @@ +..\obj\stm32f10x_can.o: ..\STM32F10x_FWLIB\src\stm32f10x_can.c +..\obj\stm32f10x_can.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\stm32f10x_can.o: ..\USER\stm32f10x.h +..\obj\stm32f10x_can.o: ..\CORE\core_cm3.h +..\obj\stm32f10x_can.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\stm32f10x_can.o: ..\USER\system_stm32f10x.h +..\obj\stm32f10x_can.o: ..\USER\stm32f10x_conf.h +..\obj\stm32f10x_can.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\stm32f10x_can.o: ..\USER\stm32f10x.h +..\obj\stm32f10x_can.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\stm32f10x_can.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\stm32f10x_can.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\stm32f10x_can.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\stm32f10x_can.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\stm32f10x_can.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\stm32f10x_can.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\stm32f10x_can.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\stm32f10x_can.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\stm32f10x_can.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\stm32f10x_can.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\stm32f10x_can.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\stm32f10x_can.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\stm32f10x_can.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\stm32f10x_can.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\stm32f10x_can.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\stm32f10x_can.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\stm32f10x_can.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\stm32f10x_can.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\stm32f10x_can.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\stm32f10x_can.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\stm32f10x_can.o: ..\STM32F10x_FWLIB\inc\misc.h diff --git a/OBJ/stm32f10x_can.o b/OBJ/stm32f10x_can.o new file mode 100644 index 0000000..073a0da Binary files /dev/null and b/OBJ/stm32f10x_can.o differ diff --git a/OBJ/stm32f10x_cec.crf b/OBJ/stm32f10x_cec.crf new file mode 100644 index 0000000..aaf55b2 Binary files /dev/null and b/OBJ/stm32f10x_cec.crf differ diff --git a/OBJ/stm32f10x_cec.d b/OBJ/stm32f10x_cec.d new file mode 100644 index 0000000..ecdf488 --- /dev/null +++ b/OBJ/stm32f10x_cec.d @@ -0,0 +1,31 @@ +..\obj\stm32f10x_cec.o: ..\STM32F10x_FWLIB\src\stm32f10x_cec.c +..\obj\stm32f10x_cec.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\stm32f10x_cec.o: ..\USER\stm32f10x.h +..\obj\stm32f10x_cec.o: ..\CORE\core_cm3.h +..\obj\stm32f10x_cec.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\stm32f10x_cec.o: ..\USER\system_stm32f10x.h +..\obj\stm32f10x_cec.o: ..\USER\stm32f10x_conf.h +..\obj\stm32f10x_cec.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\stm32f10x_cec.o: ..\USER\stm32f10x.h +..\obj\stm32f10x_cec.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\stm32f10x_cec.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\stm32f10x_cec.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\stm32f10x_cec.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\stm32f10x_cec.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\stm32f10x_cec.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\stm32f10x_cec.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\stm32f10x_cec.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\stm32f10x_cec.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\stm32f10x_cec.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\stm32f10x_cec.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\stm32f10x_cec.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\stm32f10x_cec.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\stm32f10x_cec.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\stm32f10x_cec.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\stm32f10x_cec.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\stm32f10x_cec.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\stm32f10x_cec.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\stm32f10x_cec.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\stm32f10x_cec.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\stm32f10x_cec.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\stm32f10x_cec.o: ..\STM32F10x_FWLIB\inc\misc.h diff --git a/OBJ/stm32f10x_cec.o b/OBJ/stm32f10x_cec.o new file mode 100644 index 0000000..bef61c3 Binary files /dev/null and b/OBJ/stm32f10x_cec.o differ diff --git a/OBJ/stm32f10x_crc.crf b/OBJ/stm32f10x_crc.crf new file mode 100644 index 0000000..b11da0e Binary files /dev/null and b/OBJ/stm32f10x_crc.crf differ diff --git a/OBJ/stm32f10x_crc.d b/OBJ/stm32f10x_crc.d new file mode 100644 index 0000000..695f5db --- /dev/null +++ b/OBJ/stm32f10x_crc.d @@ -0,0 +1,31 @@ +..\obj\stm32f10x_crc.o: ..\STM32F10x_FWLIB\src\stm32f10x_crc.c +..\obj\stm32f10x_crc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\stm32f10x_crc.o: ..\USER\stm32f10x.h +..\obj\stm32f10x_crc.o: ..\CORE\core_cm3.h +..\obj\stm32f10x_crc.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\stm32f10x_crc.o: ..\USER\system_stm32f10x.h +..\obj\stm32f10x_crc.o: ..\USER\stm32f10x_conf.h +..\obj\stm32f10x_crc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\stm32f10x_crc.o: ..\USER\stm32f10x.h +..\obj\stm32f10x_crc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\stm32f10x_crc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\stm32f10x_crc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\stm32f10x_crc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\stm32f10x_crc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\stm32f10x_crc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\stm32f10x_crc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\stm32f10x_crc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\stm32f10x_crc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\stm32f10x_crc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\stm32f10x_crc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\stm32f10x_crc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\stm32f10x_crc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\stm32f10x_crc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\stm32f10x_crc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\stm32f10x_crc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\stm32f10x_crc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\stm32f10x_crc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\stm32f10x_crc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\stm32f10x_crc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\stm32f10x_crc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\stm32f10x_crc.o: ..\STM32F10x_FWLIB\inc\misc.h diff --git a/OBJ/stm32f10x_crc.o b/OBJ/stm32f10x_crc.o new file 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..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\stm32f10x_dac.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\stm32f10x_dac.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\stm32f10x_dac.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\stm32f10x_dac.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\stm32f10x_dac.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\stm32f10x_dac.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\stm32f10x_dac.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\stm32f10x_dac.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\stm32f10x_dac.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\stm32f10x_dac.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\stm32f10x_dac.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\stm32f10x_dac.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\stm32f10x_dac.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\stm32f10x_dac.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\stm32f10x_dac.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\stm32f10x_dac.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\stm32f10x_dac.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\stm32f10x_dac.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\stm32f10x_dac.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\stm32f10x_dac.o: ..\STM32F10x_FWLIB\inc\misc.h diff --git a/OBJ/stm32f10x_dac.o b/OBJ/stm32f10x_dac.o new file mode 100644 index 0000000..ba03fce Binary files /dev/null and b/OBJ/stm32f10x_dac.o differ diff --git a/OBJ/stm32f10x_dbgmcu.crf b/OBJ/stm32f10x_dbgmcu.crf new file mode 100644 index 0000000..65a1589 Binary files /dev/null and b/OBJ/stm32f10x_dbgmcu.crf differ diff --git a/OBJ/stm32f10x_dbgmcu.d b/OBJ/stm32f10x_dbgmcu.d new file mode 100644 index 0000000..48001c6 --- /dev/null +++ b/OBJ/stm32f10x_dbgmcu.d @@ -0,0 +1,31 @@ +..\obj\stm32f10x_dbgmcu.o: ..\STM32F10x_FWLIB\src\stm32f10x_dbgmcu.c +..\obj\stm32f10x_dbgmcu.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\stm32f10x_dbgmcu.o: ..\USER\stm32f10x.h +..\obj\stm32f10x_dbgmcu.o: ..\CORE\core_cm3.h +..\obj\stm32f10x_dbgmcu.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\stm32f10x_dbgmcu.o: ..\USER\system_stm32f10x.h +..\obj\stm32f10x_dbgmcu.o: ..\USER\stm32f10x_conf.h +..\obj\stm32f10x_dbgmcu.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\stm32f10x_dbgmcu.o: ..\USER\stm32f10x.h +..\obj\stm32f10x_dbgmcu.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\stm32f10x_dbgmcu.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\stm32f10x_dbgmcu.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\stm32f10x_dbgmcu.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\stm32f10x_dbgmcu.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\stm32f10x_dbgmcu.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\stm32f10x_dbgmcu.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\stm32f10x_dbgmcu.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\stm32f10x_dbgmcu.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\stm32f10x_dbgmcu.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\stm32f10x_dbgmcu.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\stm32f10x_dbgmcu.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\stm32f10x_dbgmcu.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\stm32f10x_dbgmcu.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\stm32f10x_dbgmcu.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\stm32f10x_dbgmcu.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\stm32f10x_dbgmcu.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\stm32f10x_dbgmcu.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\stm32f10x_dbgmcu.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\stm32f10x_dbgmcu.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\stm32f10x_dbgmcu.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\stm32f10x_dbgmcu.o: ..\STM32F10x_FWLIB\inc\misc.h diff --git a/OBJ/stm32f10x_dbgmcu.o b/OBJ/stm32f10x_dbgmcu.o new file mode 100644 index 0000000..d44a0fe Binary files /dev/null and b/OBJ/stm32f10x_dbgmcu.o differ diff --git a/OBJ/stm32f10x_dma.crf b/OBJ/stm32f10x_dma.crf new file mode 100644 index 0000000..65e6648 Binary files /dev/null and b/OBJ/stm32f10x_dma.crf differ diff --git a/OBJ/stm32f10x_dma.d b/OBJ/stm32f10x_dma.d new file mode 100644 index 0000000..a316578 --- /dev/null +++ b/OBJ/stm32f10x_dma.d @@ -0,0 +1,31 @@ +..\obj\stm32f10x_dma.o: ..\STM32F10x_FWLIB\src\stm32f10x_dma.c +..\obj\stm32f10x_dma.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\stm32f10x_dma.o: ..\USER\stm32f10x.h +..\obj\stm32f10x_dma.o: ..\CORE\core_cm3.h +..\obj\stm32f10x_dma.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\stm32f10x_dma.o: ..\USER\system_stm32f10x.h +..\obj\stm32f10x_dma.o: ..\USER\stm32f10x_conf.h +..\obj\stm32f10x_dma.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\stm32f10x_dma.o: ..\USER\stm32f10x.h +..\obj\stm32f10x_dma.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\stm32f10x_dma.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\stm32f10x_dma.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\stm32f10x_dma.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\stm32f10x_dma.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\stm32f10x_dma.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\stm32f10x_dma.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\stm32f10x_dma.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\stm32f10x_dma.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\stm32f10x_dma.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\stm32f10x_dma.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\stm32f10x_dma.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\stm32f10x_dma.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\stm32f10x_dma.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\stm32f10x_dma.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\stm32f10x_dma.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\stm32f10x_dma.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\stm32f10x_dma.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\stm32f10x_dma.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\stm32f10x_dma.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\stm32f10x_dma.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\stm32f10x_dma.o: ..\STM32F10x_FWLIB\inc\misc.h diff --git a/OBJ/stm32f10x_dma.o b/OBJ/stm32f10x_dma.o new file mode 100644 index 0000000..f7411ed Binary files /dev/null and b/OBJ/stm32f10x_dma.o differ diff --git a/OBJ/stm32f10x_exti.crf b/OBJ/stm32f10x_exti.crf new file mode 100644 index 0000000..e16e03a Binary files /dev/null and b/OBJ/stm32f10x_exti.crf differ diff --git a/OBJ/stm32f10x_exti.d b/OBJ/stm32f10x_exti.d new file mode 100644 index 0000000..e0d031a --- /dev/null +++ b/OBJ/stm32f10x_exti.d @@ -0,0 +1,31 @@ +..\obj\stm32f10x_exti.o: ..\STM32F10x_FWLIB\src\stm32f10x_exti.c +..\obj\stm32f10x_exti.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\stm32f10x_exti.o: ..\USER\stm32f10x.h +..\obj\stm32f10x_exti.o: ..\CORE\core_cm3.h +..\obj\stm32f10x_exti.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\stm32f10x_exti.o: ..\USER\system_stm32f10x.h +..\obj\stm32f10x_exti.o: ..\USER\stm32f10x_conf.h +..\obj\stm32f10x_exti.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\stm32f10x_exti.o: ..\USER\stm32f10x.h +..\obj\stm32f10x_exti.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\stm32f10x_exti.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\stm32f10x_exti.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\stm32f10x_exti.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\stm32f10x_exti.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\stm32f10x_exti.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\stm32f10x_exti.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\stm32f10x_exti.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\stm32f10x_exti.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\stm32f10x_exti.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\stm32f10x_exti.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\stm32f10x_exti.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\stm32f10x_exti.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\stm32f10x_exti.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\stm32f10x_exti.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\stm32f10x_exti.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\stm32f10x_exti.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\stm32f10x_exti.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\stm32f10x_exti.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\stm32f10x_exti.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\stm32f10x_exti.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\stm32f10x_exti.o: ..\STM32F10x_FWLIB\inc\misc.h diff --git a/OBJ/stm32f10x_exti.o b/OBJ/stm32f10x_exti.o new file mode 100644 index 0000000..5f53130 Binary files /dev/null and b/OBJ/stm32f10x_exti.o differ diff --git a/OBJ/stm32f10x_flash.crf b/OBJ/stm32f10x_flash.crf new file mode 100644 index 0000000..03c99cf Binary files /dev/null and b/OBJ/stm32f10x_flash.crf differ diff --git a/OBJ/stm32f10x_flash.d b/OBJ/stm32f10x_flash.d new file mode 100644 index 0000000..c5677b3 --- /dev/null +++ b/OBJ/stm32f10x_flash.d @@ -0,0 +1,31 @@ +..\obj\stm32f10x_flash.o: ..\STM32F10x_FWLIB\src\stm32f10x_flash.c +..\obj\stm32f10x_flash.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\stm32f10x_flash.o: ..\USER\stm32f10x.h +..\obj\stm32f10x_flash.o: ..\CORE\core_cm3.h +..\obj\stm32f10x_flash.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\stm32f10x_flash.o: ..\USER\system_stm32f10x.h +..\obj\stm32f10x_flash.o: ..\USER\stm32f10x_conf.h +..\obj\stm32f10x_flash.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\stm32f10x_flash.o: ..\USER\stm32f10x.h +..\obj\stm32f10x_flash.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\stm32f10x_flash.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\stm32f10x_flash.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\stm32f10x_flash.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\stm32f10x_flash.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\stm32f10x_flash.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\stm32f10x_flash.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\stm32f10x_flash.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\stm32f10x_flash.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\stm32f10x_flash.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\stm32f10x_flash.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\stm32f10x_flash.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\stm32f10x_flash.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\stm32f10x_flash.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\stm32f10x_flash.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\stm32f10x_flash.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\stm32f10x_flash.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\stm32f10x_flash.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\stm32f10x_flash.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\stm32f10x_flash.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\stm32f10x_flash.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\stm32f10x_flash.o: ..\STM32F10x_FWLIB\inc\misc.h diff --git a/OBJ/stm32f10x_flash.o b/OBJ/stm32f10x_flash.o new file mode 100644 index 0000000..4a52cb5 Binary files /dev/null and b/OBJ/stm32f10x_flash.o differ diff --git a/OBJ/stm32f10x_fsmc.crf b/OBJ/stm32f10x_fsmc.crf new file mode 100644 index 0000000..396cd59 Binary files /dev/null and b/OBJ/stm32f10x_fsmc.crf differ diff --git a/OBJ/stm32f10x_fsmc.d b/OBJ/stm32f10x_fsmc.d new file mode 100644 index 0000000..f1ebb56 --- /dev/null +++ b/OBJ/stm32f10x_fsmc.d @@ -0,0 +1,31 @@ +..\obj\stm32f10x_fsmc.o: ..\STM32F10x_FWLIB\src\stm32f10x_fsmc.c +..\obj\stm32f10x_fsmc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\stm32f10x_fsmc.o: ..\USER\stm32f10x.h +..\obj\stm32f10x_fsmc.o: ..\CORE\core_cm3.h +..\obj\stm32f10x_fsmc.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\stm32f10x_fsmc.o: ..\USER\system_stm32f10x.h +..\obj\stm32f10x_fsmc.o: ..\USER\stm32f10x_conf.h +..\obj\stm32f10x_fsmc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\stm32f10x_fsmc.o: ..\USER\stm32f10x.h +..\obj\stm32f10x_fsmc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\stm32f10x_fsmc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\stm32f10x_fsmc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\stm32f10x_fsmc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\stm32f10x_fsmc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\stm32f10x_fsmc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\stm32f10x_fsmc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\stm32f10x_fsmc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\stm32f10x_fsmc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\stm32f10x_fsmc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\stm32f10x_fsmc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\stm32f10x_fsmc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\stm32f10x_fsmc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\stm32f10x_fsmc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\stm32f10x_fsmc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\stm32f10x_fsmc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\stm32f10x_fsmc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\stm32f10x_fsmc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\stm32f10x_fsmc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\stm32f10x_fsmc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\stm32f10x_fsmc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\stm32f10x_fsmc.o: ..\STM32F10x_FWLIB\inc\misc.h diff --git a/OBJ/stm32f10x_fsmc.o b/OBJ/stm32f10x_fsmc.o new file mode 100644 index 0000000..93017dd Binary files /dev/null and b/OBJ/stm32f10x_fsmc.o differ diff --git a/OBJ/stm32f10x_gpio.crf b/OBJ/stm32f10x_gpio.crf new file mode 100644 index 0000000..f4fd799 Binary files /dev/null and b/OBJ/stm32f10x_gpio.crf differ diff --git a/OBJ/stm32f10x_gpio.d b/OBJ/stm32f10x_gpio.d new file mode 100644 index 0000000..095491e --- /dev/null +++ b/OBJ/stm32f10x_gpio.d @@ -0,0 +1,31 @@ +..\obj\stm32f10x_gpio.o: ..\STM32F10x_FWLIB\src\stm32f10x_gpio.c +..\obj\stm32f10x_gpio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\stm32f10x_gpio.o: ..\USER\stm32f10x.h +..\obj\stm32f10x_gpio.o: ..\CORE\core_cm3.h +..\obj\stm32f10x_gpio.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\stm32f10x_gpio.o: ..\USER\system_stm32f10x.h +..\obj\stm32f10x_gpio.o: ..\USER\stm32f10x_conf.h +..\obj\stm32f10x_gpio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\stm32f10x_gpio.o: ..\USER\stm32f10x.h +..\obj\stm32f10x_gpio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\stm32f10x_gpio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\stm32f10x_gpio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\stm32f10x_gpio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\stm32f10x_gpio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\stm32f10x_gpio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\stm32f10x_gpio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\stm32f10x_gpio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\stm32f10x_gpio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\stm32f10x_gpio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\stm32f10x_gpio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\stm32f10x_gpio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\stm32f10x_gpio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\stm32f10x_gpio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\stm32f10x_gpio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\stm32f10x_gpio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\stm32f10x_gpio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\stm32f10x_gpio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\stm32f10x_gpio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\stm32f10x_gpio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\stm32f10x_gpio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\stm32f10x_gpio.o: ..\STM32F10x_FWLIB\inc\misc.h diff --git a/OBJ/stm32f10x_gpio.o b/OBJ/stm32f10x_gpio.o new file mode 100644 index 0000000..3620e4c Binary files /dev/null and b/OBJ/stm32f10x_gpio.o differ diff --git a/OBJ/stm32f10x_i2c.crf b/OBJ/stm32f10x_i2c.crf new file mode 100644 index 0000000..6ebb5e0 Binary files /dev/null and b/OBJ/stm32f10x_i2c.crf differ diff --git a/OBJ/stm32f10x_i2c.d b/OBJ/stm32f10x_i2c.d new file mode 100644 index 0000000..bfb2e24 --- /dev/null +++ b/OBJ/stm32f10x_i2c.d @@ -0,0 +1,31 @@ +..\obj\stm32f10x_i2c.o: ..\STM32F10x_FWLIB\src\stm32f10x_i2c.c +..\obj\stm32f10x_i2c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\stm32f10x_i2c.o: ..\USER\stm32f10x.h +..\obj\stm32f10x_i2c.o: ..\CORE\core_cm3.h +..\obj\stm32f10x_i2c.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\stm32f10x_i2c.o: ..\USER\system_stm32f10x.h +..\obj\stm32f10x_i2c.o: ..\USER\stm32f10x_conf.h +..\obj\stm32f10x_i2c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\stm32f10x_i2c.o: ..\USER\stm32f10x.h +..\obj\stm32f10x_i2c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\stm32f10x_i2c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\stm32f10x_i2c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\stm32f10x_i2c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\stm32f10x_i2c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\stm32f10x_i2c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\stm32f10x_i2c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\stm32f10x_i2c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\stm32f10x_i2c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\stm32f10x_i2c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\stm32f10x_i2c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\stm32f10x_i2c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\stm32f10x_i2c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\stm32f10x_i2c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\stm32f10x_i2c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\stm32f10x_i2c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\stm32f10x_i2c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\stm32f10x_i2c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\stm32f10x_i2c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\stm32f10x_i2c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\stm32f10x_i2c.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\stm32f10x_i2c.o: ..\STM32F10x_FWLIB\inc\misc.h diff --git a/OBJ/stm32f10x_i2c.o b/OBJ/stm32f10x_i2c.o new file mode 100644 index 0000000..b097483 Binary files /dev/null and b/OBJ/stm32f10x_i2c.o differ diff --git a/OBJ/stm32f10x_it.crf b/OBJ/stm32f10x_it.crf new file mode 100644 index 0000000..77d9adb Binary files /dev/null and b/OBJ/stm32f10x_it.crf differ diff --git a/OBJ/stm32f10x_it.d b/OBJ/stm32f10x_it.d new file mode 100644 index 0000000..75e6e3e --- /dev/null +++ b/OBJ/stm32f10x_it.d @@ -0,0 +1,31 @@ +..\obj\stm32f10x_it.o: stm32f10x_it.c +..\obj\stm32f10x_it.o: stm32f10x_it.h +..\obj\stm32f10x_it.o: stm32f10x.h +..\obj\stm32f10x_it.o: ..\CORE\core_cm3.h +..\obj\stm32f10x_it.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\stm32f10x_it.o: system_stm32f10x.h +..\obj\stm32f10x_it.o: stm32f10x_conf.h +..\obj\stm32f10x_it.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\stm32f10x_it.o: ..\USER\stm32f10x.h +..\obj\stm32f10x_it.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\stm32f10x_it.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\stm32f10x_it.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\stm32f10x_it.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\stm32f10x_it.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\stm32f10x_it.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\stm32f10x_it.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\stm32f10x_it.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\stm32f10x_it.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\stm32f10x_it.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\stm32f10x_it.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\stm32f10x_it.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\stm32f10x_it.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\stm32f10x_it.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\stm32f10x_it.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\stm32f10x_it.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\stm32f10x_it.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\stm32f10x_it.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\stm32f10x_it.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\stm32f10x_it.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\stm32f10x_it.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\stm32f10x_it.o: ..\STM32F10x_FWLIB\inc\misc.h diff --git a/OBJ/stm32f10x_it.o b/OBJ/stm32f10x_it.o new file mode 100644 index 0000000..da26de3 Binary files /dev/null and b/OBJ/stm32f10x_it.o differ diff --git a/OBJ/stm32f10x_iwdg.crf b/OBJ/stm32f10x_iwdg.crf new file mode 100644 index 0000000..ff8b92e Binary files /dev/null and b/OBJ/stm32f10x_iwdg.crf differ diff --git a/OBJ/stm32f10x_iwdg.d b/OBJ/stm32f10x_iwdg.d new file mode 100644 index 0000000..d60df23 --- /dev/null +++ b/OBJ/stm32f10x_iwdg.d @@ -0,0 +1,31 @@ +..\obj\stm32f10x_iwdg.o: ..\STM32F10x_FWLIB\src\stm32f10x_iwdg.c +..\obj\stm32f10x_iwdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\stm32f10x_iwdg.o: ..\USER\stm32f10x.h +..\obj\stm32f10x_iwdg.o: ..\CORE\core_cm3.h +..\obj\stm32f10x_iwdg.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\stm32f10x_iwdg.o: ..\USER\system_stm32f10x.h +..\obj\stm32f10x_iwdg.o: ..\USER\stm32f10x_conf.h +..\obj\stm32f10x_iwdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\stm32f10x_iwdg.o: ..\USER\stm32f10x.h +..\obj\stm32f10x_iwdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\stm32f10x_iwdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\stm32f10x_iwdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\stm32f10x_iwdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\stm32f10x_iwdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\stm32f10x_iwdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\stm32f10x_iwdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\stm32f10x_iwdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\stm32f10x_iwdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\stm32f10x_iwdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\stm32f10x_iwdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\stm32f10x_iwdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\stm32f10x_iwdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\stm32f10x_iwdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\stm32f10x_iwdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\stm32f10x_iwdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\stm32f10x_iwdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\stm32f10x_iwdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\stm32f10x_iwdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\stm32f10x_iwdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\stm32f10x_iwdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\stm32f10x_iwdg.o: ..\STM32F10x_FWLIB\inc\misc.h diff --git a/OBJ/stm32f10x_iwdg.o b/OBJ/stm32f10x_iwdg.o new file mode 100644 index 0000000..10aa83c Binary files /dev/null and b/OBJ/stm32f10x_iwdg.o differ diff --git a/OBJ/stm32f10x_pwr.crf b/OBJ/stm32f10x_pwr.crf new file mode 100644 index 0000000..0843bfb Binary files /dev/null and b/OBJ/stm32f10x_pwr.crf differ diff --git a/OBJ/stm32f10x_pwr.d b/OBJ/stm32f10x_pwr.d new file mode 100644 index 0000000..52c4c2b --- /dev/null +++ b/OBJ/stm32f10x_pwr.d @@ -0,0 +1,31 @@ +..\obj\stm32f10x_pwr.o: ..\STM32F10x_FWLIB\src\stm32f10x_pwr.c +..\obj\stm32f10x_pwr.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\stm32f10x_pwr.o: ..\USER\stm32f10x.h +..\obj\stm32f10x_pwr.o: ..\CORE\core_cm3.h +..\obj\stm32f10x_pwr.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\stm32f10x_pwr.o: ..\USER\system_stm32f10x.h +..\obj\stm32f10x_pwr.o: ..\USER\stm32f10x_conf.h +..\obj\stm32f10x_pwr.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\stm32f10x_pwr.o: ..\USER\stm32f10x.h +..\obj\stm32f10x_pwr.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\stm32f10x_pwr.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\stm32f10x_pwr.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\stm32f10x_pwr.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\stm32f10x_pwr.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\stm32f10x_pwr.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\stm32f10x_pwr.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\stm32f10x_pwr.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\stm32f10x_pwr.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\stm32f10x_pwr.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\stm32f10x_pwr.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\stm32f10x_pwr.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\stm32f10x_pwr.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\stm32f10x_pwr.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\stm32f10x_pwr.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\stm32f10x_pwr.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\stm32f10x_pwr.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\stm32f10x_pwr.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\stm32f10x_pwr.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\stm32f10x_pwr.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\stm32f10x_pwr.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\stm32f10x_pwr.o: ..\STM32F10x_FWLIB\inc\misc.h diff --git a/OBJ/stm32f10x_pwr.o b/OBJ/stm32f10x_pwr.o new file mode 100644 index 0000000..d2f94dd Binary files /dev/null and b/OBJ/stm32f10x_pwr.o differ diff --git a/OBJ/stm32f10x_rcc.crf b/OBJ/stm32f10x_rcc.crf new file mode 100644 index 0000000..ffb5a47 Binary files /dev/null and b/OBJ/stm32f10x_rcc.crf differ diff --git a/OBJ/stm32f10x_rcc.d b/OBJ/stm32f10x_rcc.d new file mode 100644 index 0000000..dcaeb03 --- /dev/null +++ b/OBJ/stm32f10x_rcc.d @@ -0,0 +1,31 @@ +..\obj\stm32f10x_rcc.o: ..\STM32F10x_FWLIB\src\stm32f10x_rcc.c +..\obj\stm32f10x_rcc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\stm32f10x_rcc.o: ..\USER\stm32f10x.h +..\obj\stm32f10x_rcc.o: ..\CORE\core_cm3.h +..\obj\stm32f10x_rcc.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\stm32f10x_rcc.o: ..\USER\system_stm32f10x.h +..\obj\stm32f10x_rcc.o: ..\USER\stm32f10x_conf.h +..\obj\stm32f10x_rcc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\stm32f10x_rcc.o: ..\USER\stm32f10x.h +..\obj\stm32f10x_rcc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\stm32f10x_rcc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\stm32f10x_rcc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\stm32f10x_rcc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\stm32f10x_rcc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\stm32f10x_rcc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\stm32f10x_rcc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\stm32f10x_rcc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\stm32f10x_rcc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\stm32f10x_rcc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\stm32f10x_rcc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\stm32f10x_rcc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\stm32f10x_rcc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\stm32f10x_rcc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\stm32f10x_rcc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\stm32f10x_rcc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\stm32f10x_rcc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\stm32f10x_rcc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\stm32f10x_rcc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\stm32f10x_rcc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\stm32f10x_rcc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\stm32f10x_rcc.o: ..\STM32F10x_FWLIB\inc\misc.h diff --git a/OBJ/stm32f10x_rcc.o b/OBJ/stm32f10x_rcc.o new file mode 100644 index 0000000..19d75b9 Binary files /dev/null and b/OBJ/stm32f10x_rcc.o differ diff --git a/OBJ/stm32f10x_rtc.crf b/OBJ/stm32f10x_rtc.crf new file mode 100644 index 0000000..bc1d73a Binary files /dev/null and b/OBJ/stm32f10x_rtc.crf differ diff --git a/OBJ/stm32f10x_rtc.d b/OBJ/stm32f10x_rtc.d new file mode 100644 index 0000000..5721d4e --- /dev/null +++ b/OBJ/stm32f10x_rtc.d @@ -0,0 +1,31 @@ +..\obj\stm32f10x_rtc.o: ..\STM32F10x_FWLIB\src\stm32f10x_rtc.c +..\obj\stm32f10x_rtc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\stm32f10x_rtc.o: ..\USER\stm32f10x.h +..\obj\stm32f10x_rtc.o: ..\CORE\core_cm3.h +..\obj\stm32f10x_rtc.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\stm32f10x_rtc.o: ..\USER\system_stm32f10x.h +..\obj\stm32f10x_rtc.o: ..\USER\stm32f10x_conf.h +..\obj\stm32f10x_rtc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\stm32f10x_rtc.o: ..\USER\stm32f10x.h +..\obj\stm32f10x_rtc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\stm32f10x_rtc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\stm32f10x_rtc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\stm32f10x_rtc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\stm32f10x_rtc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\stm32f10x_rtc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\stm32f10x_rtc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\stm32f10x_rtc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\stm32f10x_rtc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\stm32f10x_rtc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\stm32f10x_rtc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\stm32f10x_rtc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\stm32f10x_rtc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\stm32f10x_rtc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\stm32f10x_rtc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\stm32f10x_rtc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\stm32f10x_rtc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\stm32f10x_rtc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\stm32f10x_rtc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\stm32f10x_rtc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\stm32f10x_rtc.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\stm32f10x_rtc.o: ..\STM32F10x_FWLIB\inc\misc.h diff --git a/OBJ/stm32f10x_rtc.o b/OBJ/stm32f10x_rtc.o new file mode 100644 index 0000000..0931709 Binary files /dev/null and b/OBJ/stm32f10x_rtc.o differ diff --git a/OBJ/stm32f10x_sdio.crf b/OBJ/stm32f10x_sdio.crf new file mode 100644 index 0000000..5e7efc5 Binary files /dev/null and b/OBJ/stm32f10x_sdio.crf differ diff --git a/OBJ/stm32f10x_sdio.d b/OBJ/stm32f10x_sdio.d new file mode 100644 index 0000000..0b13da3 --- /dev/null +++ b/OBJ/stm32f10x_sdio.d @@ -0,0 +1,31 @@ +..\obj\stm32f10x_sdio.o: ..\STM32F10x_FWLIB\src\stm32f10x_sdio.c +..\obj\stm32f10x_sdio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\stm32f10x_sdio.o: ..\USER\stm32f10x.h +..\obj\stm32f10x_sdio.o: ..\CORE\core_cm3.h +..\obj\stm32f10x_sdio.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\stm32f10x_sdio.o: ..\USER\system_stm32f10x.h +..\obj\stm32f10x_sdio.o: ..\USER\stm32f10x_conf.h +..\obj\stm32f10x_sdio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\stm32f10x_sdio.o: ..\USER\stm32f10x.h +..\obj\stm32f10x_sdio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\stm32f10x_sdio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\stm32f10x_sdio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\stm32f10x_sdio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\stm32f10x_sdio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\stm32f10x_sdio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\stm32f10x_sdio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\stm32f10x_sdio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\stm32f10x_sdio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\stm32f10x_sdio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\stm32f10x_sdio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\stm32f10x_sdio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\stm32f10x_sdio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\stm32f10x_sdio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\stm32f10x_sdio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\stm32f10x_sdio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\stm32f10x_sdio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\stm32f10x_sdio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\stm32f10x_sdio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\stm32f10x_sdio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\stm32f10x_sdio.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\stm32f10x_sdio.o: ..\STM32F10x_FWLIB\inc\misc.h diff --git a/OBJ/stm32f10x_sdio.o b/OBJ/stm32f10x_sdio.o new file mode 100644 index 0000000..37fcd13 Binary files /dev/null and b/OBJ/stm32f10x_sdio.o differ diff --git a/OBJ/stm32f10x_spi.crf b/OBJ/stm32f10x_spi.crf new file mode 100644 index 0000000..cd6b7da Binary files /dev/null and b/OBJ/stm32f10x_spi.crf differ diff --git a/OBJ/stm32f10x_spi.d b/OBJ/stm32f10x_spi.d new file mode 100644 index 0000000..68c6336 --- /dev/null +++ b/OBJ/stm32f10x_spi.d @@ -0,0 +1,31 @@ +..\obj\stm32f10x_spi.o: ..\STM32F10x_FWLIB\src\stm32f10x_spi.c +..\obj\stm32f10x_spi.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\stm32f10x_spi.o: ..\USER\stm32f10x.h +..\obj\stm32f10x_spi.o: ..\CORE\core_cm3.h +..\obj\stm32f10x_spi.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\stm32f10x_spi.o: ..\USER\system_stm32f10x.h +..\obj\stm32f10x_spi.o: ..\USER\stm32f10x_conf.h +..\obj\stm32f10x_spi.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\stm32f10x_spi.o: ..\USER\stm32f10x.h +..\obj\stm32f10x_spi.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\stm32f10x_spi.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\stm32f10x_spi.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\stm32f10x_spi.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\stm32f10x_spi.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\stm32f10x_spi.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\stm32f10x_spi.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\stm32f10x_spi.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\stm32f10x_spi.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\stm32f10x_spi.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\stm32f10x_spi.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\stm32f10x_spi.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\stm32f10x_spi.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\stm32f10x_spi.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\stm32f10x_spi.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\stm32f10x_spi.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\stm32f10x_spi.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\stm32f10x_spi.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\stm32f10x_spi.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\stm32f10x_spi.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\stm32f10x_spi.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\stm32f10x_spi.o: ..\STM32F10x_FWLIB\inc\misc.h diff --git a/OBJ/stm32f10x_spi.o b/OBJ/stm32f10x_spi.o new file mode 100644 index 0000000..0f17fee Binary files /dev/null and b/OBJ/stm32f10x_spi.o differ diff --git a/OBJ/stm32f10x_tim.crf b/OBJ/stm32f10x_tim.crf new file mode 100644 index 0000000..9d3d7b8 Binary files /dev/null and b/OBJ/stm32f10x_tim.crf differ diff --git a/OBJ/stm32f10x_tim.d b/OBJ/stm32f10x_tim.d new file mode 100644 index 0000000..68d253f --- /dev/null +++ b/OBJ/stm32f10x_tim.d @@ -0,0 +1,31 @@ +..\obj\stm32f10x_tim.o: ..\STM32F10x_FWLIB\src\stm32f10x_tim.c +..\obj\stm32f10x_tim.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\stm32f10x_tim.o: ..\USER\stm32f10x.h +..\obj\stm32f10x_tim.o: ..\CORE\core_cm3.h +..\obj\stm32f10x_tim.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\stm32f10x_tim.o: ..\USER\system_stm32f10x.h +..\obj\stm32f10x_tim.o: ..\USER\stm32f10x_conf.h +..\obj\stm32f10x_tim.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\stm32f10x_tim.o: ..\USER\stm32f10x.h +..\obj\stm32f10x_tim.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\stm32f10x_tim.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\stm32f10x_tim.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\stm32f10x_tim.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\stm32f10x_tim.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\stm32f10x_tim.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\stm32f10x_tim.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\stm32f10x_tim.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\stm32f10x_tim.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\stm32f10x_tim.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\stm32f10x_tim.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\stm32f10x_tim.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\stm32f10x_tim.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\stm32f10x_tim.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\stm32f10x_tim.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\stm32f10x_tim.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\stm32f10x_tim.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\stm32f10x_tim.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\stm32f10x_tim.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\stm32f10x_tim.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\stm32f10x_tim.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\stm32f10x_tim.o: ..\STM32F10x_FWLIB\inc\misc.h diff --git a/OBJ/stm32f10x_tim.o b/OBJ/stm32f10x_tim.o new file mode 100644 index 0000000..91b5265 Binary files /dev/null and b/OBJ/stm32f10x_tim.o differ diff --git a/OBJ/stm32f10x_usart.crf b/OBJ/stm32f10x_usart.crf new file mode 100644 index 0000000..1d7e5f2 Binary files /dev/null and b/OBJ/stm32f10x_usart.crf differ diff --git a/OBJ/stm32f10x_usart.d b/OBJ/stm32f10x_usart.d new file mode 100644 index 0000000..92a6d74 --- /dev/null +++ b/OBJ/stm32f10x_usart.d @@ -0,0 +1,31 @@ +..\obj\stm32f10x_usart.o: ..\STM32F10x_FWLIB\src\stm32f10x_usart.c +..\obj\stm32f10x_usart.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\stm32f10x_usart.o: ..\USER\stm32f10x.h +..\obj\stm32f10x_usart.o: ..\CORE\core_cm3.h +..\obj\stm32f10x_usart.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\stm32f10x_usart.o: ..\USER\system_stm32f10x.h +..\obj\stm32f10x_usart.o: ..\USER\stm32f10x_conf.h +..\obj\stm32f10x_usart.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\stm32f10x_usart.o: ..\USER\stm32f10x.h +..\obj\stm32f10x_usart.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\stm32f10x_usart.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\stm32f10x_usart.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\stm32f10x_usart.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\stm32f10x_usart.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\stm32f10x_usart.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\stm32f10x_usart.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\stm32f10x_usart.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\stm32f10x_usart.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\stm32f10x_usart.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\stm32f10x_usart.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\stm32f10x_usart.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\stm32f10x_usart.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\stm32f10x_usart.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\stm32f10x_usart.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\stm32f10x_usart.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\stm32f10x_usart.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\stm32f10x_usart.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\stm32f10x_usart.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\stm32f10x_usart.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\stm32f10x_usart.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\stm32f10x_usart.o: ..\STM32F10x_FWLIB\inc\misc.h diff --git a/OBJ/stm32f10x_usart.o b/OBJ/stm32f10x_usart.o new file mode 100644 index 0000000..3a615a1 Binary files /dev/null and b/OBJ/stm32f10x_usart.o differ diff --git a/OBJ/stm32f10x_wwdg.crf b/OBJ/stm32f10x_wwdg.crf new file mode 100644 index 0000000..410da79 Binary files /dev/null and b/OBJ/stm32f10x_wwdg.crf differ diff --git a/OBJ/stm32f10x_wwdg.d b/OBJ/stm32f10x_wwdg.d new file mode 100644 index 0000000..bb82b8f --- /dev/null +++ b/OBJ/stm32f10x_wwdg.d @@ -0,0 +1,31 @@ +..\obj\stm32f10x_wwdg.o: ..\STM32F10x_FWLIB\src\stm32f10x_wwdg.c +..\obj\stm32f10x_wwdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\stm32f10x_wwdg.o: ..\USER\stm32f10x.h +..\obj\stm32f10x_wwdg.o: ..\CORE\core_cm3.h +..\obj\stm32f10x_wwdg.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\stm32f10x_wwdg.o: ..\USER\system_stm32f10x.h +..\obj\stm32f10x_wwdg.o: ..\USER\stm32f10x_conf.h +..\obj\stm32f10x_wwdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\stm32f10x_wwdg.o: ..\USER\stm32f10x.h +..\obj\stm32f10x_wwdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\stm32f10x_wwdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\stm32f10x_wwdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\stm32f10x_wwdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\stm32f10x_wwdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\stm32f10x_wwdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\stm32f10x_wwdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\stm32f10x_wwdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\stm32f10x_wwdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\stm32f10x_wwdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\stm32f10x_wwdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\stm32f10x_wwdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\stm32f10x_wwdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\stm32f10x_wwdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\stm32f10x_wwdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\stm32f10x_wwdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\stm32f10x_wwdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\stm32f10x_wwdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\stm32f10x_wwdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\stm32f10x_wwdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\stm32f10x_wwdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\stm32f10x_wwdg.o: ..\STM32F10x_FWLIB\inc\misc.h diff --git a/OBJ/stm32f10x_wwdg.o b/OBJ/stm32f10x_wwdg.o new file mode 100644 index 0000000..0a01148 Binary files /dev/null and b/OBJ/stm32f10x_wwdg.o differ diff --git a/OBJ/system_stm32f10x.crf b/OBJ/system_stm32f10x.crf new file mode 100644 index 0000000..bacc2cd Binary files /dev/null and b/OBJ/system_stm32f10x.crf differ diff --git a/OBJ/system_stm32f10x.d b/OBJ/system_stm32f10x.d new file mode 100644 index 0000000..5a7a8ef --- /dev/null +++ b/OBJ/system_stm32f10x.d @@ -0,0 +1,30 @@ +..\obj\system_stm32f10x.o: system_stm32f10x.c +..\obj\system_stm32f10x.o: stm32f10x.h +..\obj\system_stm32f10x.o: ..\CORE\core_cm3.h +..\obj\system_stm32f10x.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\system_stm32f10x.o: system_stm32f10x.h +..\obj\system_stm32f10x.o: stm32f10x_conf.h +..\obj\system_stm32f10x.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\system_stm32f10x.o: ..\USER\stm32f10x.h +..\obj\system_stm32f10x.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\system_stm32f10x.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\system_stm32f10x.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\system_stm32f10x.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\system_stm32f10x.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\system_stm32f10x.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\system_stm32f10x.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\system_stm32f10x.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\system_stm32f10x.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\system_stm32f10x.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\system_stm32f10x.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\system_stm32f10x.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\system_stm32f10x.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\system_stm32f10x.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\system_stm32f10x.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\system_stm32f10x.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\system_stm32f10x.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\system_stm32f10x.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\system_stm32f10x.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\system_stm32f10x.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\system_stm32f10x.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\system_stm32f10x.o: ..\STM32F10x_FWLIB\inc\misc.h diff --git a/OBJ/system_stm32f10x.o b/OBJ/system_stm32f10x.o new file mode 100644 index 0000000..e969942 Binary files /dev/null and b/OBJ/system_stm32f10x.o differ diff --git a/OBJ/systick.crf b/OBJ/systick.crf new file mode 100644 index 0000000..4313edf Binary files /dev/null and b/OBJ/systick.crf differ diff --git a/OBJ/systick.d b/OBJ/systick.d new file mode 100644 index 0000000..e626712 --- /dev/null +++ b/OBJ/systick.d @@ -0,0 +1,32 @@ +..\obj\systick.o: ..\BSP\systick.c +..\obj\systick.o: ..\USER\stm32f10x.h +..\obj\systick.o: ..\CORE\core_cm3.h +..\obj\systick.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\systick.o: ..\USER\system_stm32f10x.h +..\obj\systick.o: ..\USER\stm32f10x_conf.h +..\obj\systick.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\systick.o: ..\USER\stm32f10x.h +..\obj\systick.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\systick.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\systick.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\systick.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\systick.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\systick.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\systick.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\systick.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\systick.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\systick.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\systick.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\systick.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\systick.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\systick.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\systick.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\systick.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\systick.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\systick.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\systick.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\systick.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\systick.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\systick.o: ..\STM32F10x_FWLIB\inc\misc.h +..\obj\systick.o: ..\USER\global.h +..\obj\systick.o: ..\MOUDLE\AFE_SH3673520.h diff --git a/OBJ/systick.o b/OBJ/systick.o new file mode 100644 index 0000000..178df0c Binary files /dev/null and b/OBJ/systick.o differ diff --git a/OBJ/tim.crf b/OBJ/tim.crf new file mode 100644 index 0000000..348be99 Binary files /dev/null and b/OBJ/tim.crf differ diff --git a/OBJ/tim.d b/OBJ/tim.d new file mode 100644 index 0000000..ed11ecf --- /dev/null +++ b/OBJ/tim.d @@ -0,0 +1,32 @@ +..\obj\tim.o: ..\BSP\tim.c +..\obj\tim.o: ..\USER\stm32f10x.h +..\obj\tim.o: ..\CORE\core_cm3.h +..\obj\tim.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\tim.o: ..\USER\system_stm32f10x.h +..\obj\tim.o: ..\USER\stm32f10x_conf.h +..\obj\tim.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\tim.o: ..\USER\stm32f10x.h +..\obj\tim.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\tim.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\tim.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\tim.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\tim.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\tim.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\tim.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\tim.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\tim.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\tim.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\tim.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\tim.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\tim.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\tim.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\tim.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\tim.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\tim.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\tim.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\tim.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\tim.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\tim.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\tim.o: ..\STM32F10x_FWLIB\inc\misc.h +..\obj\tim.o: ..\USER\global.h +..\obj\tim.o: ..\MOUDLE\AFE_SH3673520.h diff --git a/OBJ/tim.o b/OBJ/tim.o new file mode 100644 index 0000000..4833d38 Binary files /dev/null and b/OBJ/tim.o differ diff --git a/OBJ/uart.crf b/OBJ/uart.crf new file mode 100644 index 0000000..f0f94ba Binary files /dev/null and b/OBJ/uart.crf differ diff --git a/OBJ/uart.d b/OBJ/uart.d new file mode 100644 index 0000000..9d79ac2 --- /dev/null +++ b/OBJ/uart.d @@ -0,0 +1,32 @@ +..\obj\uart.o: ..\BSP\uart.c +..\obj\uart.o: ..\USER\stm32f10x.h +..\obj\uart.o: ..\CORE\core_cm3.h +..\obj\uart.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\uart.o: ..\USER\system_stm32f10x.h +..\obj\uart.o: ..\USER\stm32f10x_conf.h +..\obj\uart.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\uart.o: ..\USER\stm32f10x.h +..\obj\uart.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\uart.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\uart.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\uart.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\uart.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\uart.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\uart.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\uart.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\uart.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\uart.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\uart.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\uart.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\uart.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\uart.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\uart.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\uart.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\uart.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\uart.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\uart.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\uart.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\uart.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\uart.o: ..\STM32F10x_FWLIB\inc\misc.h +..\obj\uart.o: ..\USER\global.h +..\obj\uart.o: ..\MOUDLE\AFE_SH3673520.h diff --git a/OBJ/uart.o b/OBJ/uart.o new file mode 100644 index 0000000..003af27 Binary files /dev/null and b/OBJ/uart.o differ diff --git a/OBJ/wdg.crf b/OBJ/wdg.crf new file mode 100644 index 0000000..55ca362 Binary files /dev/null and b/OBJ/wdg.crf differ diff --git a/OBJ/wdg.d b/OBJ/wdg.d new file mode 100644 index 0000000..373093c --- /dev/null +++ b/OBJ/wdg.d @@ -0,0 +1,32 @@ +..\obj\wdg.o: ..\BSP\wdg.c +..\obj\wdg.o: ..\USER\stm32f10x.h +..\obj\wdg.o: ..\CORE\core_cm3.h +..\obj\wdg.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\wdg.o: ..\USER\system_stm32f10x.h +..\obj\wdg.o: ..\USER\stm32f10x_conf.h +..\obj\wdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\wdg.o: ..\USER\stm32f10x.h +..\obj\wdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\wdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\wdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\wdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\wdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\wdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\wdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\wdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\wdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\wdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\wdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\wdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\wdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\wdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\wdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\wdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\wdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\wdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\wdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\wdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\wdg.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\wdg.o: ..\STM32F10x_FWLIB\inc\misc.h +..\obj\wdg.o: ..\USER\global.h +..\obj\wdg.o: ..\MOUDLE\AFE_SH3673520.h diff --git a/OBJ/wdg.o b/OBJ/wdg.o new file mode 100644 index 0000000..4dd8d1a Binary files /dev/null and b/OBJ/wdg.o differ diff --git a/OBJ/yibang.crf b/OBJ/yibang.crf new file mode 100644 index 0000000..8aa26ff Binary files /dev/null and b/OBJ/yibang.crf differ diff --git a/OBJ/yibang.d b/OBJ/yibang.d new file mode 100644 index 0000000..718013f --- /dev/null +++ b/OBJ/yibang.d @@ -0,0 +1,35 @@ +..\obj\yibang.o: ..\MOUDLE\YiBang.c +..\obj\yibang.o: ..\USER\stm32f10x.h +..\obj\yibang.o: ..\CORE\core_cm3.h +..\obj\yibang.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\yibang.o: ..\USER\system_stm32f10x.h +..\obj\yibang.o: ..\USER\stm32f10x_conf.h +..\obj\yibang.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\yibang.o: ..\USER\stm32f10x.h +..\obj\yibang.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\yibang.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\yibang.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\yibang.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\yibang.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\yibang.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\yibang.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\yibang.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\yibang.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\yibang.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\yibang.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\yibang.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\yibang.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\yibang.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\yibang.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\yibang.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\yibang.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\yibang.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\yibang.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\yibang.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\yibang.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\yibang.o: ..\STM32F10x_FWLIB\inc\misc.h +..\obj\yibang.o: ..\USER\global.h +..\obj\yibang.o: ..\MOUDLE\AFE_SH3673520.h +..\obj\yibang.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\string.h +..\obj\yibang.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdarg.h +..\obj\yibang.o: E:\keil_v5_old\ARM\ARMCC\Bin\..\include\stdio.h diff --git a/OBJ/yibang.o b/OBJ/yibang.o new file mode 100644 index 0000000..84dde10 Binary files /dev/null and b/OBJ/yibang.o differ diff --git a/OBJ/zs1211.crf b/OBJ/zs1211.crf new file mode 100644 index 0000000..075a9ef Binary files /dev/null and b/OBJ/zs1211.crf differ diff --git a/OBJ/zs1211.d b/OBJ/zs1211.d new file mode 100644 index 0000000..3ac5ca9 --- /dev/null +++ b/OBJ/zs1211.d @@ -0,0 +1,34 @@ +..\obj\zs1211.o: ..\MOUDLE\ZS1211.c +..\obj\zs1211.o: ..\USER\stm32f10x.h +..\obj\zs1211.o: ..\CORE\core_cm3.h +..\obj\zs1211.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h +..\obj\zs1211.o: ..\USER\system_stm32f10x.h +..\obj\zs1211.o: ..\USER\stm32f10x_conf.h +..\obj\zs1211.o: ..\STM32F10x_FWLIB\inc\stm32f10x_adc.h +..\obj\zs1211.o: ..\USER\stm32f10x.h +..\obj\zs1211.o: ..\STM32F10x_FWLIB\inc\stm32f10x_bkp.h +..\obj\zs1211.o: ..\STM32F10x_FWLIB\inc\stm32f10x_can.h +..\obj\zs1211.o: ..\STM32F10x_FWLIB\inc\stm32f10x_cec.h +..\obj\zs1211.o: ..\STM32F10x_FWLIB\inc\stm32f10x_crc.h +..\obj\zs1211.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dac.h +..\obj\zs1211.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dbgmcu.h +..\obj\zs1211.o: ..\STM32F10x_FWLIB\inc\stm32f10x_dma.h +..\obj\zs1211.o: ..\STM32F10x_FWLIB\inc\stm32f10x_exti.h +..\obj\zs1211.o: ..\STM32F10x_FWLIB\inc\stm32f10x_flash.h +..\obj\zs1211.o: ..\STM32F10x_FWLIB\inc\stm32f10x_fsmc.h +..\obj\zs1211.o: ..\STM32F10x_FWLIB\inc\stm32f10x_gpio.h +..\obj\zs1211.o: ..\STM32F10x_FWLIB\inc\stm32f10x_i2c.h +..\obj\zs1211.o: ..\STM32F10x_FWLIB\inc\stm32f10x_iwdg.h +..\obj\zs1211.o: ..\STM32F10x_FWLIB\inc\stm32f10x_pwr.h +..\obj\zs1211.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rcc.h +..\obj\zs1211.o: ..\STM32F10x_FWLIB\inc\stm32f10x_rtc.h +..\obj\zs1211.o: ..\STM32F10x_FWLIB\inc\stm32f10x_sdio.h +..\obj\zs1211.o: ..\STM32F10x_FWLIB\inc\stm32f10x_spi.h +..\obj\zs1211.o: ..\STM32F10x_FWLIB\inc\stm32f10x_tim.h +..\obj\zs1211.o: ..\STM32F10x_FWLIB\inc\stm32f10x_usart.h +..\obj\zs1211.o: ..\STM32F10x_FWLIB\inc\stm32f10x_wwdg.h +..\obj\zs1211.o: ..\STM32F10x_FWLIB\inc\misc.h +..\obj\zs1211.o: ..\USER\global.h +..\obj\zs1211.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\string.h +..\obj\zs1211.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdarg.h +..\obj\zs1211.o: C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdio.h diff --git a/OBJ/zs1211.o b/OBJ/zs1211.o new file mode 100644 index 0000000..1baf9c5 Binary files /dev/null and b/OBJ/zs1211.o differ diff --git a/PROTOCOL/ProtocolSwitch_P1.c b/PROTOCOL/ProtocolSwitch_P1.c new file mode 100644 index 0000000..ada0eac --- /dev/null +++ b/PROTOCOL/ProtocolSwitch_P1.c @@ -0,0 +1,4810 @@ +/** + ****************************************************************************** + * @file InverterSwitch_Page1.c + * @author - + * @version - + * @date 2026.3.26 + * @brief - + ****************************************************************************** + * @attention + * + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" +#include "global.h" + + +//这里放的是基本款的第1页函数，不根据发货要求变动 +//CAN: +//1.Sol-Ark 2.GoodWe 3.Megarevo 4.Pylon +//5.Deye 6.MUST 7.solis 8.Growatt +//9.Aiswei 10.Afore 11.Victron 12.Sorotec +//Modbus: +//8.Growatt 12.Sorotec +//YDN: +//4.Pylon + + +//CAN: +//Sol-Ark +void CAN_Protocol_SolArk(void) +{ + uint8_t data[8]; + uint16_t totalCapacity; + + uint16_t tempVol; + int16_t tempCur; + + uint16_t chgVolLimit; + uint16_t dsgVolLimit; + int16_t chgCurLimit; + int16_t dsgCurLimit; + + uint8_t protectByte1 = 0; + uint8_t protectByte2 = 0; + + int16_t T_Average; // 平均温度 + + uint8_t alarmByte1 = 0; + uint8_t alarmByte2 = 0; + + //保护 + //放电过流保护 + //discharge over current，SC, OCD1, OCD2 + if( ((canMem[0].status_byte1 & 0x042c) != 0) || ((canMem[0].status_byte2 & 0x0010) != 0) || ((canMem[0].status_byte4 & 0x0020) != 0)) + { + protectByte1 |= 0x80; + } + else + { + protectByte1 &= 0x7f; + } + + //低温保护 + //under temp at charging or discharging + if(((canMem[0].status_byte2 & 0x0005) != 0) || ((canMem[0].status_byte4 & 0x0C0C) != 0)) + { + protectByte1 |= 0x10; + } + else + { + protectByte1 &= 0xef; + } + + //过温保护 + //over temp at charging or discharging + if(((canMem[0].status_byte2 & 0x000A) != 0) || ((canMem[0].status_byte4 & 0x0303) != 0)) + { + protectByte1 |= 0x08; + } + else + { + protectByte1 &= 0xf7; + } + + //欠压保护 + //cell_uv+pack_uv+l0v + if(((canMem[0].status_byte1 & 0x0202) != 0) || ((canMem[0].status_byte3 & 0x0008) != 0)) + { + protectByte1 |= 0x04; + } + else + { + protectByte1 &= 0xfb; + } + +// //过压保护 +// //cell_ov+pack_ov+pf +// if((canMem[0].status_byte1 & 0x0141) != 0) +// { +// if(canMem[0].soc < 99) +// { +// protectByte1 |= 0x02; +// } +// else +// { +// protectByte1 &= 0xfd; +// } +// } +// else +// { +// protectByte1 &= 0xfd; +// } + + //充电过流保护 + //charge over current + if( ((canMem[0].status_byte1 & 0x0010) != 0) || ((canMem[0].status_byte4 & 0x0010) != 0)) + { + protectByte2 |= 0x01; + } + else + { + protectByte2 &= 0xfe; + } + + //告警 + //放电过流告警 + if((canMem[0].status_byte3 & 0x2000) != 0) + { + alarmByte1 |= 0x80; + } + else + { + alarmByte1 &= 0x7f; + } + + //低温告警 + if(((canMem[0].status_byte2 & 0xCC00) != 0) || ((canMem[0].status_byte4 & 0xC000) != 0)) + { + alarmByte1 |= 0x10; + } + else + { + alarmByte1 &= 0xef; + } + + //过温告警 + if(((canMem[0].status_byte2 & 0x3300) != 0) || ((canMem[0].status_byte4 & 0x3000) != 0)) + { + alarmByte1 |= 0x08; + } + else + { + alarmByte1 &= 0xf7; + } + + //欠压告警 + if((canMem[0].status_byte3 & 0x0A00) != 0) + { + alarmByte1 |= 0x04; + } + else + { + alarmByte1 &= 0xfb; + } + +// //过压告警 +// if((canMem[0].status_byte3 & 0x0500) != 0) +// { +// if(canMem[0].soc < 99) +// { +// alarmByte1 |= 0x02; +// } +// else +// { +// alarmByte1 &= 0xfd; +// } +// } +// else +// { +// alarmByte1 &= 0xfd; +// } + + //充电过流告警 + if((canMem[0].status_byte3 & 0x1000) != 0) + { + alarmByte2 |= 0x01; + } + else + { + alarmByte2 &= 0xfe; + } + + if(CAN_SendCount ==0) //ID=0x359 + { + data[0] = protectByte1; + data[1] = protectByte2; + data[2] = alarmByte1; + data[3] = alarmByte2; + data[4] = OnlineNum; + data[5] = 0x50; + data[6] = 0x4E; + data[7] = 0X00; + CAN1_SendData(0x359, &data[0]); + } + if(CAN_SendCount ==1) //ID = 0x351 + { + //充放电电流限制需要有符号区别吗？ + chgVolLimit = bmsMem.inverter_chgVolLimit; //充电电压限制，上位机配置，默认值57.6V + dsgVolLimit = bmsMem.inverter_dsgVolLimit; //放电电压限制，上位机配置，默认值41.6V + + if(chg_forbidFlg == 1) + { + chgCurLimit = 0; //Sol-Ark禁充 + } + else if(chg_curlimitFlg == 1) + { + chgCurLimit = Inv_curlimit * (OnlineNum-chg_cur0Num); //限流40A*未保护个数 + } + else + { + chgCurLimit = bmsMem.inverter_chgCurLimit * (OnlineNum-chg_curLimitNum); //充电电流限制，上位机配置，默认值100A + } + if(dsg_forbidFlg == 1) + { + dsgCurLimit = 0; //Sol-Ark禁放 + } + else + { + dsgCurLimit = bmsMem.inverter_dsgCurLimit * (OnlineNum-dsg_curLimitNum); //放电电流限制，上位机配置，默认值100A + } + + data[0] = chgVolLimit & 0xFF; //充电电压限制低位 + data[1] = (chgVolLimit >> 8) & 0xFF; + data[2] = chgCurLimit & 0xFF; //充电电流限制低位 + data[3] = (chgCurLimit >> 8) & 0xFF; + data[4] = dsgCurLimit & 0xFF; //放电电流限制低位 + data[5] = (dsgCurLimit >> 8) & 0xFF; + data[6] = dsgVolLimit & 0xFF; //放电电压限制低位 + data[7] = (dsgVolLimit >> 8) & 0xFF; + CAN1_SendData(0x351, &data[0]); + } + if(CAN_SendCount ==2) + { + data[0] = canMem[0].soc & 0xFF; //SOC + data[1] = 0; + data[2] = canMem[0].soh & 0xFF; //SOH + data[3] = 0; + data[4] = 0X00; + data[5] = 0x00; + data[6] = 0x00; + data[7] = 0X00; + CAN1_SendData(0x355, &data[0]); + } + if(CAN_SendCount ==3) + { + tempVol = (uint16_t)(bmsMem.packVoltage/10); //单位0.01 + tempCur = (int16_t)(canMem[0].cur/10); //单位0.1 + T_Average = canMem[0].temp;// 平均温度 + + data[0] = tempVol & 0xFF; + data[1] = (tempVol >>8) & 0xFF; //电池包电压 + data[2] = tempCur & 0xFF; + data[3] = (tempCur >>8) & 0xFF; //电池包电流 + data[4] = (T_Average -2731) & 0xFF;; + data[5] = ((T_Average -2731) >>8) & 0xFF; //温度-暂时取平均温度，具体哪一路需要客户确认 + data[6] = 0x00; + data[7] = 0X00; + CAN1_SendData(0x356, &data[0]); + } + if(CAN_SendCount ==4) + { + RequestFlag = 0xC0; //充电允许0x80，放电允许0x40，不强充~0x20 + if(chg_forbidFlg == 1)//Sol-Ark + { + RequestFlag &= 0x7F; //禁充 + } + if(dsg_forbidFlg == 1)//Sol-Ark + { + RequestFlag &= 0xBF; //禁放 + } + if(chg_forceFlg == 1)//Sol-Ark + { + RequestFlag |= 0x20; //强充 + } + + data[0] = RequestFlag; + data[1] = 0x00; + data[2] = 0x00; + data[3] = 0x00; + data[4] = 0X00; + data[5] = 0x00; + data[6] = 0x00; + data[7] = 0X00; + CAN1_SendData(0x35C, &data[0]); + } + if(CAN_SendCount ==5) //0x379 + { + totalCapacity = ncc_Ah * OnlineNum; //单位1Ah + + data[0] = totalCapacity & 0xFF; //充电电压限制低位 + data[1] = (totalCapacity >> 8) & 0xFF; + data[2] = 0x00; + data[3] = 0x00; + data[4] = 0X00; + data[5] = 0x00; + data[6] = 0x00; + data[7] = 0X00; + CAN1_SendData(0x379, &data[0]); + } + if(CAN_SendCount ==6) + { + data[0] = 'B'; + data[1] = 'T'; + data[2] = 'Y'; + data[3] = 'G'; + data[4] = '-'; + data[5] = 'B'; + data[6] = 'M'; + data[7] = 'S'; + CAN1_SendData(0x35e, &data[0]); + } + + if(CAN_SendCount>=7) + { + CAN_SendCount = 0; + } +} + +//GoodWe 固德威 +void CAN_Protocol_GoodWe(void) +{ + uint8_t data[8]; +// uint16_t totalCapacity; + + int16_t tempVol; + int16_t tempCur; + + uint16_t chgVolLimit; +// uint16_t dsgVolLimit; + int16_t chgCurLimit; + int16_t dsgCurLimit; + + uint8_t protectByte1 = 0; + uint8_t protectByte2 = 0; + uint8_t alarmByte1 = 0; //固德威在Cell Balance功能上protect和alarm显示不同 + uint8_t alarmByte2 = 0; + + int16_t T_Average; // 平均温度 + int16_t T_Max; // 最高温度 + int16_t T_Min; // 最低温度 + uint16_t T_MaxIndex;// 最高温度序号，范围0-6 + uint16_t T_MinIndex;// 最低温度序号，范围0-6 + + uint16_t cellVolMax=0; // 电芯单体最高电压-固德威 + int16_t cellVolMin=0; // 电芯单体最低电压-固德威 + uint16_t cellVolMaxIndex; // 电芯单体最高电压序号，范围0-15-固德威 + int16_t cellVolMinIndex; // 电芯单体最低电压序号，范围0-15-固德威 + + + //保护 + //放电过流保护 + //discharge over current，SC, OCD1, OCD2 + if( ((canMem[0].status_byte1 & 0x042c) != 0) || ((canMem[0].status_byte2 & 0x0010) != 0) || ((canMem[0].status_byte4 & 0x0020) != 0)) + { + protectByte1 |= 0x80; + } + else + { + protectByte1 &= 0x7f; + } + + //低温保护 + //under temp at charging or discharging + if(((canMem[0].status_byte2 & 0x0005) != 0) || ((canMem[0].status_byte4 & 0x0C0C) != 0)) + { + protectByte1 |= 0x10; + } + else + { + protectByte1 &= 0xef; + } + + //过温保护 + //over temp at charging or discharging + if(((canMem[0].status_byte2 & 0x000A) != 0) || ((canMem[0].status_byte4 & 0x0303) != 0)) + { + protectByte1 |= 0x08; + } + else + { + protectByte1 &= 0xf7; + } + + //欠压保护 + //cell_uv+pack_uv+l0v + if(((canMem[0].status_byte1 & 0x0202) != 0) || ((canMem[0].status_byte3 & 0x0008) != 0)) + { + protectByte1 |= 0x04; + } + else + { + protectByte1 &= 0xfb; + } + +// //过压保护 +// //cell_ov+pack_ov+pf +// if((canMem[0].status_byte1 & 0x0141) != 0) +// { +// if(canMem[0].soc < 99) +// { +// protectByte1 |= 0x02; +// } +// else +// { +// protectByte1 &= 0xfd; +// } +// } +// else +// { +// protectByte1 &= 0xfd; +// } + + //充电过流保护 + //charge over current + if( ((canMem[0].status_byte1 & 0x0010) != 0) || ((canMem[0].status_byte4 & 0x0010) != 0)) + { + protectByte2 |= 0x01; + } + else + { + protectByte2 &= 0xfe; + } + + //告警 + //放电过流告警 + if((canMem[0].status_byte3 & 0x2000) != 0) + { + alarmByte1 |= 0x80; + } + else + { + alarmByte1 &= 0x7f; + } + + //低温告警 + if(((canMem[0].status_byte2 & 0xCC00) != 0) || ((canMem[0].status_byte4 & 0xC000) != 0)) + { + alarmByte1 |= 0x10; + } + else + { + alarmByte1 &= 0xef; + } + + //过温告警 + if(((canMem[0].status_byte2 & 0x3300) != 0) || ((canMem[0].status_byte4 & 0x3000) != 0)) + { + alarmByte1 |= 0x08; + } + else + { + alarmByte1 &= 0xf7; + } + + //欠压告警 + if((canMem[0].status_byte3 & 0x0A00) != 0) + { + alarmByte1 |= 0x04; + } + else + { + alarmByte1 &= 0xfb; + } + +// //过压告警 +// if((canMem[0].status_byte3 & 0x0500) != 0) +// { +// if(canMem[0].soc < 99) +// { +// alarmByte1 |= 0x02; +// } +// else +// { +// alarmByte1 &= 0xfd; +// } +// } +// else +// { +// alarmByte1 &= 0xfd; +// } + + //充电过流告警 + if((canMem[0].status_byte3 & 0x1000) != 0) + { + alarmByte2 |= 0x01; + } + else + { + alarmByte2 &= 0xfe; + } + +// //Data1 BIT4 cell balance +// if((bmsMem.balanceStatus & 0x01) !=0) +// { +// protectByte2 |= 0x10; +// alarmByte2 &= 0xef; +// } +// else +// { +// protectByte2 &= 0xef; +// alarmByte2 |= 0x10; +// } + + if(CAN_SendCount ==0) //ID = 0x359 - 报警/警告信息（前4行数据改为更直接的值，后面置0） + { + data[0] = protectByte1; + data[1] = protectByte2; + data[2] = alarmByte1; + data[3] = alarmByte2; + data[4] = 0X00; + data[5] = 0X00; + data[6] = 0X00; + data[7] = 0X00; + CAN1_SendData(0x359, &data[0]); + } + if(CAN_SendCount ==1) //ID = 0x351 - 充电限压/限流，放电限流（已修改，不要求放电限压） + { + //充放电电流限制需要有符号区别吗？ + chgVolLimit = bmsMem.inverter_chgVolLimit; //充电电压限制，上位机配置，默认值57.6V + //dsgVolLimit = bmsMem.inverter_dsgVolLimit; //放电电压限制，上位机配置，默认值41.6V + + if(chg_forbidFlg == 1) + { + chgCurLimit = 0; //GoodWe禁充 + } + else if(chg_curlimitFlg == 1) + { + chgCurLimit = Inv_curlimit * (OnlineNum-chg_cur0Num); //限流40A*未保护个数 + } + else + { + chgCurLimit = bmsMem.inverter_chgCurLimit * (OnlineNum-chg_curLimitNum); //充电电流限制，上位机配置，默认值100A + } + if(dsg_forbidFlg == 1) + { + dsgCurLimit = 0; //GoodWe禁放 + } + else + { + dsgCurLimit = bmsMem.inverter_dsgCurLimit * (OnlineNum-dsg_curLimitNum); //放电电流限制，上位机配置，默认值100A + } + + data[0] = chgVolLimit & 0xFF; //充电电压限制低位 + data[1] = (chgVolLimit >> 8) & 0xFF; + data[2] = chgCurLimit & 0xFF; //充电电流限制低位 + data[3] = (chgCurLimit >> 8) & 0xFF; + data[4] = dsgCurLimit & 0xFF; //放电电流限制低位 + data[5] = (dsgCurLimit >> 8) & 0xFF; + data[6] = 0x00; + data[7] = 0x00; + CAN1_SendData(0x351, &data[0]); + } + if(CAN_SendCount ==2) //ID = 0x355 - 电量SOC/SOH（应该不修改） + { + data[0] = canMem[0].soc & 0xFF; //SOC + data[1] = 0; + data[2] = canMem[0].soh & 0xFF; //SOH + data[3] = 0; + data[4] = 0X00; + data[5] = 0x00; + data[6] = 0x00; + data[7] = 0X00; + CAN1_SendData(0x355, &data[0]); + } + if(CAN_SendCount ==3) //ID = 0x356 - 电池电压/电流/温度（应该不修改） + { + tempVol = (uint16_t)(bmsMem.packVoltage/10); //单位0.01 + tempCur = (int16_t)(canMem[0].cur/10); //单位0.1 + T_Average = canMem[0].temp;// 平均温度 + + data[0] = tempVol & 0xFF; + data[1] = (tempVol >>8) & 0xFF; //电池包电压 + data[2] = tempCur & 0xFF; + data[3] = (tempCur >>8) & 0xFF; //电池包电流 + data[4] = (T_Average -2731) & 0xFF; + data[5] = ((T_Average -2731) >>8) & 0xFF; //温度-暂时取平均温度，具体哪一路需要客户确认 //signed有符号数 + data[6] = 0x00; + data[7] = 0X00; + CAN1_SendData(0x356, &data[0]); + } + if(CAN_SendCount ==4) //ID = 0x35C - 充电/放电开关（已修改，由Data[0]的bit6、7控制） + { + RequestFlag = 0xC0; //充电允许0x80，放电允许0x40，不强充~0x20 + if(chg_forbidFlg == 1)//GoodWe + { + RequestFlag &= 0x7F; //禁充 + } + if(dsg_forbidFlg == 1)//GoodWe + { + RequestFlag &= 0xBF; //禁放 + } + if(chg_forceFlg == 1)//GoodWe + { + RequestFlag |= 0x20; //强充 + } + + data[0] = 0XC0; //充电允许，放电允许 + data[1] = 0x00; + data[2] = 0x00; + data[3] = 0x00; + data[4] = 0X00; + data[5] = 0x00; + data[6] = 0x00; + data[7] = 0X00; + CAN1_SendData(0x35C, &data[0]); + } + if(CAN_SendCount ==5) //ID = 0x370 - 最大/最小单体温度，最大/最小单体电压（新加入） + { + T_Max = canMem[0].TempMax; // 最高温度 + T_Min = canMem[0].TempMin; // 最低温度 + cellVolMax = canMem[0].VolMax; + cellVolMin = canMem[0].VolMin; + + data[0] = (T_Max -2731) & 0xFF; //最大单体温度 + data[1] = ((T_Max -2731) >> 8) & 0xFF; + data[2] = (T_Min -2731) & 0xFF; //最小单体温度 + data[3] = ((T_Min -2731) >> 8) & 0xFF; + data[4] = cellVolMax & 0xFF; //最大单体电压 + data[5] = (cellVolMax >> 8) & 0xFF; + data[6] = cellVolMin & 0xFF; //最小单体电压 + data[7] = (cellVolMin >> 8) & 0xFF; + CAN1_SendData(0x370, &data[0]); + } + if(CAN_SendCount ==6) //ID = 0x371 - 最大/最小单体温度ID，最大/最小单体电压ID（新加入） + { + T_MaxIndex = canMem[0].TempMaxIndex;// 最高温度序号，范围0-6 + T_MinIndex = canMem[0].TempMinIndex;// 最低温度序号，范围0-6 + cellVolMaxIndex = canMem[0].VolMaxIndex; + cellVolMinIndex = canMem[0].VolMinIndex; + + data[0] = (T_MaxIndex+1) & 0xFF; //最大单体温度序号，实际显示从1开始 + data[1] = ((T_MaxIndex+1) >> 8) & 0xFF; + data[2] = (T_MinIndex+1) & 0xFF; //最小单体温度序号 + data[3] = ((T_MinIndex+1) >> 8) & 0xFF; + data[4] = (cellVolMaxIndex+1) & 0xFF; //最大单体电压序号 + data[5] = ((cellVolMaxIndex+1) >> 8) & 0xFF; + data[6] = (cellVolMinIndex+1) & 0xFF; //最小单体电压序号 + data[7] = ((cellVolMinIndex+1) >> 8) & 0xFF; + CAN1_SendData(0x371, &data[0]); + } +// if(CAN_SendCount ==7) //ID = 0x380 - 传递信息1-4（无要求） +// { +// data[0] = 'B'; +// data[1] = ('B' >> 8) & 0xFF; +// data[2] = 'T'; +// data[3] = ('T' >> 8) & 0xFF; +// data[4] = 'Y'; +// data[5] = ('Y' >> 8) & 0xFF; +// data[6] = 'G'; +// data[7] = ('G' >> 8) & 0xFF; +// CAN1_SendData(0x380, &data[0]); +// } +// if(CAN_SendCount ==8) //ID = 0x381 - 传递信息5-8（无要求） +// { +// data[0] = '-'; +// data[1] = ('-' >> 8) & 0xFF; +// data[2] = 'B'; +// data[3] = ('B' >> 8) & 0xFF; +// data[4] = 'M'; +// data[5] = ('M' >> 8) & 0xFF; +// data[6] = 'S'; +// data[7] = ('S' >> 8) & 0xFF; +// CAN1_SendData(0x381, &data[0]); +// } + + if(CAN_SendCount>=7) + { + CAN_SendCount = 0; + } +} + +//Megarevo 迈格瑞能 +void CAN_Protocol_Megarevo(void) +{ + uint8_t data[8]; + + uint16_t tempVol; + int16_t tempCur; //总电流 + + uint16_t chgVolLimit; + int16_t chgCurLimit; + int16_t dsgCurLimit; + + uint8_t protectByte1 = 0; + uint8_t protectByte2 = 0; + uint8_t alarmByte1 = 0; + uint8_t alarmByte2 = 0; + + + int16_t T_Average; // 平均温度 + + + //保护 + //放电过流保护 + //discharge over current，SC, OCD1, OCD2 + if( ((canMem[0].status_byte1 & 0x042c) != 0) || ((canMem[0].status_byte2 & 0x0010) != 0) || ((canMem[0].status_byte4 & 0x0020) != 0)) + { + protectByte1 |= 0x80; + } + else + { + protectByte1 &= 0x7f; + } + + //低温保护 + //under temp at charging or discharging + if(((canMem[0].status_byte2 & 0x0005) != 0) || ((canMem[0].status_byte4 & 0x0C0C) != 0)) + { + protectByte1 |= 0x10; + } + else + { + protectByte1 &= 0xef; + } + + //过温保护 + //over temp at charging or discharging + if(((canMem[0].status_byte2 & 0x000A) != 0) || ((canMem[0].status_byte4 & 0x0303) != 0)) + { + protectByte1 |= 0x08; + } + else + { + protectByte1 &= 0xf7; + } + + //欠压保护 + //cell_uv+pack_uv+l0v + if(((canMem[0].status_byte1 & 0x0202) != 0) || ((canMem[0].status_byte3 & 0x0008) != 0)) + { + protectByte1 |= 0x04; + } + else + { + protectByte1 &= 0xfb; + } + +// //过压保护 +// //cell_ov+pack_ov+pf +// if((canMem[0].status_byte1 & 0x0141) != 0) +// { +// if(canMem[0].soc < 99) +// { +// protectByte1 |= 0x02; +// } +// else +// { +// protectByte1 &= 0xfd; +// } +// } +// else +// { +// protectByte1 &= 0xfd; +// } + + //充电过流保护 + //charge over current + if( ((canMem[0].status_byte1 & 0x0010) != 0) || ((canMem[0].status_byte4 & 0x0010) != 0)) + { + protectByte2 |= 0x02; + } + else + { + protectByte2 &= 0xfD; + } + + + //告警 + //放电过流告警 + if((canMem[0].status_byte3 & 0x2000) != 0) + { + alarmByte1 |= 0x80; + } + else + { + alarmByte1 &= 0x7f; + } + + //低温告警 + if(((canMem[0].status_byte2 & 0xCC00) != 0) || ((canMem[0].status_byte4 & 0xC000) != 0)) + { + alarmByte1 |= 0x10; + } + else + { + alarmByte1 &= 0xef; + } + + //过温告警 + if(((canMem[0].status_byte2 & 0x3300) != 0) || ((canMem[0].status_byte4 & 0x3000) != 0)) + { + alarmByte1 |= 0x08; + } + else + { + alarmByte1 &= 0xf7; + } + + //欠压告警 + if((canMem[0].status_byte3 & 0x0A00) != 0) + { + alarmByte1 |= 0x04; + } + else + { + alarmByte1 &= 0xfb; + } + +// //过压告警 +// if((canMem[0].status_byte3 & 0x0500) != 0) +// { +// if(canMem[0].soc < 99) +// { +// alarmByte1 |= 0x02; +// } +// else +// { +// alarmByte1 &= 0xfd; +// } +// } +// else +// { +// alarmByte1 &= 0xfd; +// } + + //充电过流告警 + if((canMem[0].status_byte3 & 0x1000) != 0) + { + alarmByte2 |= 0x01; + } + else + { + alarmByte2 &= 0xfe; + } + + + if(CAN_SendCount ==0) //ID=0x359 - 报警/保护 + { + data[0] = protectByte1; + data[1] = protectByte2; + data[2] = alarmByte1; + data[3] = alarmByte2; + data[4] = 0x00; + data[5] = 0x00; + data[6] = 0x00; + data[7] = 0x00; + CAN1_SendData(0x359, &data[0]); + } + if(CAN_SendCount ==1) //ID = 0x351 --- 充放电电压/电流限制 + { + //充放电电流限制需要有符号区别吗？ + chgVolLimit = bmsMem.inverter_chgVolLimit; //充电电压限制，上位机配置，默认值57.6V + //dsgVolLimit = bmsMem.inverter_dsgVolLimit; //放电电压限制，上位机配置，默认值41.6V + + if(chg_forbidFlg == 1) + { + chgCurLimit = 0; //Megarevo禁充 + } + else if(chg_curlimitFlg == 1) + { + chgCurLimit = Inv_curlimit * (OnlineNum-chg_cur0Num); //限流40A*未保护个数 + } + else + { + chgCurLimit = bmsMem.inverter_chgCurLimit * (OnlineNum-chg_curLimitNum); //充电电流限制，上位机配置，默认值100A + } + if(dsg_forbidFlg == 1) + { + dsgCurLimit = 0; //Megarevo禁放 + } + else + { + dsgCurLimit = bmsMem.inverter_dsgCurLimit * (OnlineNum-dsg_curLimitNum); //放电电流限制，上位机配置，默认值100A + } + + data[0] = chgVolLimit & 0xFF; //充电电压限制低位 + data[1] = (chgVolLimit >> 8) & 0xFF; + data[2] = chgCurLimit & 0xFF; //充电电流限制低位 + data[3] = (chgCurLimit >> 8) & 0xFF; + data[4] = dsgCurLimit & 0xFF; //放电电流限制低位 + data[5] = (dsgCurLimit >> 8) & 0xFF; + data[6] = 0x00; + data[7] = 0x00; + CAN1_SendData(0x351, &data[0]); + } + if(CAN_SendCount ==2) //ID = 0x355 --- SOC/SOH + { + data[0] = canMem[0].soc & 0xFF; //SOC + data[1] = 0; + data[2] = canMem[0].soh & 0xFF; //SOH + data[3] = 0; + data[4] = 0X00; + data[5] = 0x00; + data[6] = 0x00; + data[7] = 0X00; + CAN1_SendData(0x355, &data[0]); + } + if(CAN_SendCount ==3) //ID = 0x356 --- 总电压/电流/温度 + { + tempVol = (uint16_t)(bmsMem.packVoltage/10); //单位0.01 + tempCur = (int16_t)(canMem[0].cur/10); //单位0.1 + T_Average = canMem[0].temp;//单位0.1 + + data[0] = tempVol & 0xFF; + data[1] = (tempVol >>8) & 0xFF; //电池包电压 + data[2] = tempCur & 0xFF; + data[3] = (tempCur >>8) & 0xFF; //电池包电流 + data[4] = (T_Average -2731) & 0xFF; + data[5] = ((T_Average -2731) >>8) & 0xFF; //温度-平均温度 + data[6] = 0x00; + data[7] = 0X00; + CAN1_SendData(0x356, &data[0]); + } + if(CAN_SendCount ==4) //ID = 0x35C --- 充放电允许 + { + RequestFlag = 0xC0; //充电允许0x80，放电允许0x40，不强充~0x20 + if(chg_forbidFlg == 1)//Megarevo + { + RequestFlag &= 0x7F; //禁充 + } + if(dsg_forbidFlg == 1)//Megarevo + { + RequestFlag &= 0xBF; //禁放 + } + if(chg_forceFlg == 1)//Megarevo + { + RequestFlag |= 0x20; //强充 + } + + data[0] = RequestFlag; //充电允许，放电允许 + data[1] = 0x00; + data[2] = 0x00; + data[3] = 0x00; + data[4] = 0X00; + data[5] = 0x00; + data[6] = 0x00; + data[7] = 0X00; + CAN1_SendData(0x35C, &data[0]); + } + + if(CAN_SendCount>=5) + { + CAN_SendCount = 0; + } +} + +//Pylon 派能 +void CAN_Protocol_Pylon(void) +{ + uint8_t data[8]; + uint32_t totalCapacity; + + uint16_t tempVol; + int16_t tempCur; + + uint16_t chgVolLimit; + uint16_t dsgVolLimit; + int16_t chgCurLimit; + int16_t dsgCurLimit; + + uint8_t protectByte1 = 0; + uint8_t protectByte2 = 0; + uint8_t protectByte3 = 0; + uint8_t protectByte4 = 0; + uint8_t protectByte5 = 0; + uint8_t protectByte6 = 0; + + uint8_t alarmByte1 = 0; + uint8_t alarmByte2 = 0; + + int16_t T_Average; // 平均温度 + int16_t T_Max; // 最高温度 + int16_t T_Min; // 最低温度 + uint16_t T_MaxIndex;// 最高温度序号，范围0-6 + uint16_t T_MinIndex;// 最低温度序号，范围0-6 + + uint16_t cellVolMax=0; // 电芯单体最高电压-Pylon + uint16_t cellVolMin=0; // 电芯单体最低电压-Pylon + uint16_t cellVolMaxIndex_Byte1; // 电芯单体最高电压序号，范围0-15-Pylon + uint16_t cellVolMaxIndex_Byte2; + uint16_t cellVolMinIndex_Byte1; // 电芯单体最低电压序号，范围0-15-Pylon + uint16_t cellVolMinIndex_Byte2; + + + //保护 + //放电过流保护 + //discharge over current，SC, OCD1, OCD2 + if( ((canMem[0].status_byte1 & 0x042c) != 0) || ((canMem[0].status_byte2 & 0x0010) != 0) || ((canMem[0].status_byte4 & 0x0020) != 0)) + { + protectByte1 |= 0x80; + } + else + { + protectByte1 &= 0x7f; + } + + //低温保护 + //under temp at charging or discharging + if(((canMem[0].status_byte2 & 0x0005) != 0) || ((canMem[0].status_byte4 & 0x0C0C) != 0)) + { + protectByte1 |= 0x10; + } + else + { + protectByte1 &= 0xef; + } + + //过温保护 + //over temp at charging or discharging + if(((canMem[0].status_byte2 & 0x000A) != 0) || ((canMem[0].status_byte4 & 0x0303) != 0)) + { + protectByte1 |= 0x08; + } + else + { + protectByte1 &= 0xf7; + } + + //欠压保护 + //cell_uv+pack_uv+l0v + if(((canMem[0].status_byte1 & 0x0202) != 0) || ((canMem[0].status_byte3 & 0x0008) != 0)) + { + protectByte1 |= 0x04; + } + else + { + protectByte1 &= 0xfb; + } + +// //过压保护 +// //cell_ov+pack_ov+pf +// if((canMem[0].status_byte1 & 0x0141) != 0) +// { +// if(canMem[0].soc < 99) +// { +// protectByte1 |= 0x02; +// } +// else +// { +// protectByte1 &= 0xfd; +// } +// } +// else +// { +// protectByte1 &= 0xfd; +// } + + //充电过流保护 + //charge over current + if( ((canMem[0].status_byte1 & 0x0010) != 0) || ((canMem[0].status_byte4 & 0x0010) != 0)) + { + protectByte2 |= 0x01; + } + else + { + protectByte2 &= 0xfe; + } + + //告警 + //放电过流告警 + if((canMem[0].status_byte3 & 0x2000) != 0) + { + alarmByte1 |= 0x80; + } + else + { + alarmByte1 &= 0x7f; + } + + //低温告警 + if(((canMem[0].status_byte2 & 0xCC00) != 0) || ((canMem[0].status_byte4 & 0xC000) != 0)) + { + alarmByte1 |= 0x10; + } + else + { + alarmByte1 &= 0xef; + } + + //过温告警 + if(((canMem[0].status_byte2 & 0x3300) != 0) || ((canMem[0].status_byte4 & 0x3000) != 0)) + { + alarmByte1 |= 0x08; + } + else + { + alarmByte1 &= 0xf7; + } + + //欠压告警 + if((canMem[0].status_byte3 & 0x0A00) != 0) + { + alarmByte1 |= 0x04; + } + else + { + alarmByte1 &= 0xfb; + } + +// //过压告警 +// if((canMem[0].status_byte3 & 0x0500) != 0) +// { +// if(canMem[0].soc < 99) +// { +// alarmByte1 |= 0x02; +// } +// else +// { +// alarmByte1 &= 0xfd; +// } +// } +// else +// { +// alarmByte1 &= 0xfd; +// } + + //充电过流告警 + if((canMem[0].status_byte3 & 0x1000) != 0) + { + alarmByte2 |= 0x01; + } + else + { + alarmByte2 &= 0xfe; + } + + //Data0 BIT0.1 General[Cancel] //0000 0010 + protectByte3 |= 0x02; + + //保护 + //放电高温保护 + //over temp at discharging + if(((canMem[0].status_byte2 & 0x0008) != 0) || ((canMem[0].status_byte4 & 0x0202) != 0)) + { + protectByte3 &= 0x7f; + protectByte3 |= 0x40; + } + else + { + protectByte3 &= 0xbf; + protectByte3 |= 0x80; + } + + //欠压保护 + //cell_uv+pack_uv+l0v + if(((canMem[0].status_byte1 & 0x0202) != 0) || ((canMem[0].status_byte3 & 0x0008) != 0)) + { + protectByte3 &= 0xdf; + protectByte3 |= 0x10; + } + else + { + protectByte3 &= 0xef; + protectByte3 |= 0x20; + } + +// //过压保护 +// //cell_ov+pack_ov+pf +// if((canMem[0].status_byte1 & 0x0141) != 0) +// { +// if(canMem[0].soc < 99) +// { +// protectByte3 &= 0xf7; //去掉leave +// protectByte3 |= 0x04; //赋值arrive +// } +// else +// { +// protectByte3 &= 0xfb; +// protectByte3 |= 0x08; +// } +// } +// else +// { +// protectByte3 &= 0xfb; +// protectByte3 |= 0x08; +// } + + //放电过流保护 + //discharge over current，SC, OCD1, OCD2 + if( ((canMem[0].status_byte1 & 0x042c) != 0) || ((canMem[0].status_byte2 & 0x0010) != 0) || ((canMem[0].status_byte4 & 0x0020) != 0)) + { + protectByte4 &= 0x7f; + protectByte4 |= 0x40; + } + else + { + protectByte4 &= 0xbf; + protectByte4 |= 0x80; + } + + //充电低温保护 + //Data1 BIT4.5 under temp at charging //0001 0000 + if( ((canMem[0].status_byte2 & 0x0001) != 0) || ((canMem[0].status_byte4 & 0x0404) != 0) ) + { + protectByte4 &= 0xdf; + protectByte4 |= 0x10; + } + else + { + protectByte4 &= 0xef; + protectByte4 |= 0x20; + } + + //充电高温保护 + //Data1 BIT2.3 over temp at charging //0000 0100 + if( ((canMem[0].status_byte2 & 0x0002) != 0) || ((canMem[0].status_byte4 & 0x0101) != 0) ) + { + protectByte4 &= 0xf7; + protectByte4 |= 0x04; + } + else + { + protectByte4 &= 0xfb; + protectByte4 |= 0x08; + } + + //放电低温保护 + //Data1 BIT0.1 under temp at discharging //0000 0001 + if( ((canMem[0].status_byte2 & 0x0004) != 0) || ((canMem[0].status_byte4 & 0x0808) != 0) ) + { + protectByte4 &= 0xfd; + protectByte4 |= 0x01; + } + else + { + protectByte4 &= 0xfe; + protectByte4 |= 0x02; + } + + //短路 + //Data2 BIT4.5 short circuit //0001 0000 + if((canMem[0].status_byte1 & 0x20) != 0) + { + protectByte5 &= 0xdf; + protectByte5 |= 0x10; + } + else + { + protectByte5 &= 0xef; + protectByte5 |= 0x20; + } + + //充电过流保护 + //charge over current + if( ((canMem[0].status_byte1 & 0x0010) != 0) || ((canMem[0].status_byte4 & 0x0010) != 0)) + { + protectByte5 &= 0xfd; + protectByte5 |= 0x01; + } + else + { + protectByte5 &= 0xfe; + protectByte5 |= 0x02; + } + //Data2 BIT2.3 Contactor[Cancel] //0000 1000 + protectByte5 |= 0x08; + //Data2 BIT6.7 BMS internal[Cancel] //1000 0000 + protectByte5 |= 0x80; +// //Data3 BIT0.1 cell imbanlance //0000 0001 +// if((bmsMem.balanceStatus & 0x01) !=0) //0x01表示平衡 +// { +// protectByte6 &= 0xfe; +// protectByte6 |= 0x02; +// } +// else +// { +// protectByte6 &= 0xfd; +// protectByte6 |= 0x01; +// } + + + if(CAN_SendCount ==0) //ID=0x359 ---保护/报警 + { + data[0] = protectByte1; + data[1] = protectByte2; + data[2] = alarmByte1; + data[3] = alarmByte2; + data[4] = OnlineNum; + data[5] = 0x50; + data[6] = 0x4E; + data[7] = 0X00; + CAN1_SendData(0x359, &data[0]); + } + if(CAN_SendCount ==1) //ID = 0x351 --- 充放电电压/电流限制 + { + //充放电电流限制需要有符号区别吗？ + chgVolLimit = bmsMem.inverter_chgVolLimit; //充电电压限制，上位机配置，默认值57.6V + dsgVolLimit = bmsMem.inverter_dsgVolLimit; //放电电压限制，上位机配置，默认值41.6V + + if(chg_forbidFlg == 1) + { + chgCurLimit = 0; //Pylon禁充 + } + else if(chg_curlimitFlg == 1) + { + chgCurLimit = Inv_curlimit * (OnlineNum-chg_cur0Num); //限流40A*未保护个数 + } + else + { + chgCurLimit = bmsMem.inverter_chgCurLimit * (OnlineNum-chg_curLimitNum); //充电电流限制，上位机配置，默认值100A + } + if(dsg_forbidFlg == 1) + { + dsgCurLimit = 0; //Pylon禁放 + } + else + { + dsgCurLimit = bmsMem.inverter_dsgCurLimit * (OnlineNum-dsg_curLimitNum); //放电电流限制，上位机配置，默认值100A + } + + data[0] = chgVolLimit & 0xFF; //充电电压限制低位 + data[1] = (chgVolLimit >> 8) & 0xFF; + data[2] = chgCurLimit & 0xFF; //充电电流限制低位 + data[3] = (chgCurLimit >> 8) & 0xFF; + data[4] = dsgCurLimit & 0xFF; //放电电流限制低位 + data[5] = (dsgCurLimit >> 8) & 0xFF; + data[6] = dsgVolLimit & 0xFF; //放电电压限制低位 + data[7] = (dsgVolLimit >> 8) & 0xFF; + CAN1_SendData(0x351, &data[0]); + } + if(CAN_SendCount ==2) //ID = 0x355 --- SOC/SOH + { + data[0] = canMem[0].soc & 0xFF; //SOC + data[1] = 0; + data[2] = canMem[0].soh & 0xFF; //SOH + data[3] = 0; + data[4] = 0X00; + data[5] = 0x00; + data[6] = 0x00; + data[7] = 0X00; + CAN1_SendData(0x355, &data[0]); + } + if(CAN_SendCount ==3) //ID = 0x356 --- 电池电压/电流/温度 + { + tempVol = (uint16_t)(bmsMem.packVoltage/10); //单位0.01 + tempCur = (int16_t)(canMem[0].cur/10); //单位0.1 + T_Average = canMem[0].temp;// 平均温度 + + data[0] = tempVol & 0xFF; + data[1] = (tempVol >>8) & 0xFF; //电池包电压 + data[2] = tempCur & 0xFF; + data[3] = (tempCur >>8) & 0xFF; //电池包电流 + data[4] = (T_Average -2731) & 0xFF; + data[5] = ((T_Average -2731) >>8) & 0xFF; //温度-平均温度 + data[6] = 0x00; + data[7] = 0X00; + CAN1_SendData(0x356, &data[0]); + } + if(CAN_SendCount ==4) //ID = 0x35C --- 充放电允许 + { + RequestFlag = 0xC0; //充电允许0x80，放电允许0x40，不强充~0x20 + if(chg_forbidFlg == 1)//Pylon + { + RequestFlag &= 0x7F; //禁充 + } + if(dsg_forbidFlg == 1)//Pylon + { + RequestFlag &= 0xBF; //禁放 + } + if(chg_forceFlg == 1)//Pylon + { + RequestFlag |= 0x20; //强充 + } + + data[0] = RequestFlag; + data[1] = 0x00; + data[2] = 0x00; + data[3] = 0x00; + data[4] = 0X00; + data[5] = 0x00; + data[6] = 0x00; + data[7] = 0X00; + CAN1_SendData(0x35C, &data[0]); + } + if(CAN_SendCount ==5) //ID = 0x35E --- 电池厂商 + { + data[0] = 'P'; + data[1] = 'Y'; + data[2] = 'L'; + data[3] = 'O'; + data[4] = 'N'; + data[5] = 0X00; + data[6] = 0X00; + data[7] = 0X00; + CAN1_SendData(0x35E, &data[0]); + } + if(CAN_SendCount ==6) //ID = 0x373 - 最大/最小单体电压/温度（与固德威配置相同） + { + cellVolMax = canMem[0].VolMax; + cellVolMin = canMem[0].VolMin; + T_Max = canMem[0].TempMax/10; // 最高温度 + T_Min = canMem[0].TempMin/10; // 最低温度 + + data[0] = cellVolMin & 0xFF; //最小单体电压 + data[1] = (cellVolMin >> 8) & 0xFF; + data[2] = cellVolMax & 0xFF; //最大单体电压 + data[3] = (cellVolMax >> 8) & 0xFF; + data[4] = (T_Min ) & 0xFF; //最小单体温度 + data[5] = ((T_Min ) >> 8) & 0xFF; + data[6] = (T_Max ) & 0xFF; //最大单体温度 + data[7] = ((T_Max ) >> 8) & 0xFF; + CAN1_SendData(0x373, &data[0]); + } + if(CAN_SendCount ==7) //ID = 0x379 --- 容量 + { + totalCapacity = ncc_Ah * OnlineNum; //单位1Ah + + data[0] = (totalCapacity >> 0 ) & 0xFF; //电池容量 + data[1] = (totalCapacity >> 8 ) & 0xFF; + data[2] = (totalCapacity >> 16) & 0xFF; + data[3] = (totalCapacity >> 24) & 0xFF; + data[4] = 0X00; + data[5] = 0X00; + data[6] = 0X00; + data[7] = 0X00; + CAN1_SendData(0x379, &data[0]); + } + if(CAN_SendCount ==8) //ID = 0x35A - Alarms/Warnings + { + data[0] = protectByte3; + data[1] = protectByte4; + data[2] = protectByte5; + data[3] = protectByte6; + data[4] = 0X00; + data[5] = 0X00; + data[6] = 0X00; + data[7] = 0X00; + CAN1_SendData(0x35A, &data[0]); + } + + if(CAN_SendCount ==9) //ID = 0x374 - 最小电池电压地址 + { + if((canMem[0].VolMinIndex + 1) >= 10) + { + cellVolMinIndex_Byte1 = 1; + cellVolMinIndex_Byte2 = (canMem[0].VolMinIndex+1)-10; + } + else + { + cellVolMinIndex_Byte1 = 0; + cellVolMinIndex_Byte2 = (canMem[0].VolMinIndex+1); + } + + data[0] = '0'; + data[1] = '1'; + data[2] = 0x30 + cellVolMinIndex_Byte1; + data[3] = 0X30 + cellVolMinIndex_Byte2; + data[4] = 0X00; + data[5] = 0X00; + data[6] = 0X00; + data[7] = 0X00; + CAN1_SendData(0x374, &data[0]); + } + if(CAN_SendCount ==10) //ID = 0x375 - 最大电池电压地址 + { + if((canMem[0].VolMaxIndex+1)>= 10) + { + cellVolMaxIndex_Byte1 = 1; + cellVolMaxIndex_Byte2 = (canMem[0].VolMaxIndex+1)-10; + } + else + { + cellVolMaxIndex_Byte1 = 0; + cellVolMaxIndex_Byte2 = (canMem[0].VolMaxIndex+1); + } + + data[0] = '0'; + data[1] = '1'; + data[2] = 0x30 + cellVolMaxIndex_Byte1; + data[3] = 0x30 + cellVolMaxIndex_Byte2; + data[4] = 0X00; + data[5] = 0X00; + data[6] = 0X00; + data[7] = 0X00; + CAN1_SendData(0x375, &data[0]); + } + if(CAN_SendCount ==11) //ID = 0x376 - 最小电池温度地址 + { + T_MinIndex = canMem[0].TempMinIndex;// 最低温度序号，范围0-6 + + data[0] = '0'; + data[1] = '1'; + data[2] = '0'; + data[3] = 0x30 + (T_MinIndex+1); + data[4] = 0X00; + data[5] = 0X00; + data[6] = 0X00; + data[7] = 0X00; + CAN1_SendData(0x376, &data[0]); + } + if(CAN_SendCount ==12) //ID = 0x377 - 最大电池温度地址 + { + T_MaxIndex = canMem[0].TempMaxIndex;// 最高温度序号，范围0-6 + + data[0] = '0'; + data[1] = '1'; + data[2] = '0'; + data[3] = 0x30 + (T_MaxIndex+1); + data[4] = 0X00; + data[5] = 0X00; + data[6] = 0X00; + data[7] = 0X00; + CAN1_SendData(0x377, &data[0]); + } + + if(CAN_SendCount>=13) + { + CAN_SendCount = 0; + } +} + +//Deye 德业 +uint8_t Deye_dsg_forbidFlg; //单独属于德业的标志 +void CAN_Protocol_Deye(void) +{ + uint8_t data[8]; +// uint16_t totalCapacity; + + uint16_t tempVol; + int16_t tempCur; + + uint16_t chgVolLimit; + uint16_t dsgVolLimit; + int16_t chgCurLimit; + int16_t dsgCurLimit; + + uint8_t protectByte1 = 0; + uint8_t protectByte2 = 0; + + uint8_t alarmByte1 = 0; + uint8_t alarmByte2 = 0; + + + int16_t T_Average; // 平均温度 + + + //保护 + //放电过流保护 + //discharge over current，SC, OCD1, OCD2 + if( ((canMem[0].status_byte1 & 0x042c) != 0) || ((canMem[0].status_byte2 & 0x0010) != 0) || ((canMem[0].status_byte4 & 0x0020) != 0)) + { + protectByte1 |= 0x80; + } + else + { + protectByte1 &= 0x7f; + } + + //低温保护 + //under temp at charging or discharging + if(((canMem[0].status_byte2 & 0x0005) != 0) || ((canMem[0].status_byte4 & 0x0C0C) != 0)) + { + protectByte1 |= 0x10; + } + else + { + protectByte1 &= 0xef; + } + + //过温保护 + //over temp at charging or discharging + if(((canMem[0].status_byte2 & 0x000A) != 0) || ((canMem[0].status_byte4 & 0x0303) != 0)) + { + protectByte1 |= 0x08; + } + else + { + protectByte1 &= 0xf7; + } + + //欠压保护 + //cell_uv+pack_uv+l0v + if(((canMem[0].status_byte1 & 0x0202) != 0) || ((canMem[0].status_byte3 & 0x0008) != 0)) + { + protectByte1 |= 0x04; + } + else + { + protectByte1 &= 0xfb; + } + +// //过压保护 +// //cell_ov+pack_ov+pf +// if((canMem[0].status_byte1 & 0x0141) != 0) +// { +// if(canMem[0].soc < 99) +// { +// protectByte1 |= 0x02; +// } +// else +// { +// protectByte1 &= 0xfd; +// } +// } +// else +// { +// protectByte1 &= 0xfd; +// } + + //充电过流保护 + //charge over current + if( ((canMem[0].status_byte1 & 0x0010) != 0) || ((canMem[0].status_byte4 & 0x0010) != 0)) + { + protectByte2 |= 0x01; + } + else + { + protectByte2 &= 0xfe; + } + + //告警 + //放电过流告警 + if((canMem[0].status_byte3 & 0x2000) != 0) + { + alarmByte1 |= 0x80; + } + else + { + alarmByte1 &= 0x7f; + } + + //低温告警 + if(((canMem[0].status_byte2 & 0xCC00) != 0) || ((canMem[0].status_byte4 & 0xC000) != 0)) + { + alarmByte1 |= 0x10; + } + else + { + alarmByte1 &= 0xef; + } + + //过温告警 + if(((canMem[0].status_byte2 & 0x3300) != 0) || ((canMem[0].status_byte4 & 0x3000) != 0)) + { + alarmByte1 |= 0x08; + } + else + { + alarmByte1 &= 0xf7; + } + + //欠压告警 + if((canMem[0].status_byte3 & 0x0A00) != 0) + { + alarmByte1 |= 0x04; + } + else + { + alarmByte1 &= 0xfb; + } + +// //过压告警 +// if((canMem[0].status_byte3 & 0x0500) != 0) +// { +// if(canMem[0].soc < 99) +// { +// alarmByte1 |= 0x02; +// } +// else +// { +// alarmByte1 &= 0xfd; +// } +// } +// else +// { +// alarmByte1 &= 0xfd; +// } + + //充电过流告警 + if((canMem[0].status_byte3 & 0x1000) != 0) + { + alarmByte2 |= 0x01; + } + else + { + alarmByte2 &= 0xfe; + } + + if(canMem[0].soc<=5) //Deye自己的强充标志变化值 + { + Deye_dsg_forbidFlg = 1; + } + else if(canMem[0].soc>=10) + { + Deye_dsg_forbidFlg = 0; + } + + + if(CAN_SendCount ==0) //ID = 0x359 --- 报警/保护 + { + data[0] = protectByte1; //电芯过压 + data[1] = protectByte2; + data[2] = alarmByte1; + data[3] = alarmByte2; + data[4] = 0X00; + data[5] = 0x50; + data[6] = 0x4E; + data[7] = 0X00; + CAN1_SendData(0x359, &data[0]); + } + if(CAN_SendCount ==1) //ID = 0x351 --- 充放电限压/限流 + { + //充放电电流限制需要有符号区别吗？ + chgVolLimit = bmsMem.inverter_chgVolLimit; //充电电压限制，上位机配置，默认值57.6V + dsgVolLimit = bmsMem.inverter_dsgVolLimit; //放电电压限制，上位机配置，默认值41.6V + + if(chg_forbidFlg == 1) + { + chgCurLimit = 0; //Deye禁充 + } + else if(chg_curlimitFlg == 1) + { + chgCurLimit = Inv_curlimit * (OnlineNum-chg_cur0Num); //限流40A*未保护个数 + } + else + { + chgCurLimit = bmsMem.inverter_chgCurLimit * (OnlineNum-chg_curLimitNum); //充电电流限制，上位机配置，默认值100A + } + if(Deye_dsg_forbidFlg == 1) + { + dsgCurLimit = 0; //Deye禁放(范围是5%和10%，与其他协议分开) + } + else + { + dsgCurLimit = bmsMem.inverter_dsgCurLimit * (OnlineNum-dsg_curLimitNum); //放电电流限制，上位机配置，默认值100A + } + + data[0] = chgVolLimit & 0xFF; //充电电压限制低位 + data[1] = (chgVolLimit >> 8) & 0xFF; + data[2] = chgCurLimit & 0xFF; //充电电流限制低位 + data[3] = (chgCurLimit >> 8) & 0xFF; + data[4] = dsgCurLimit & 0xFF; //放电电流限制低位 + data[5] = (dsgCurLimit >> 8) & 0xFF; + data[6] = dsgVolLimit & 0xFF; //放电电压限制低位 + data[7] = (dsgVolLimit >> 8) & 0xFF; + CAN1_SendData(0x351, &data[0]); + } + if(CAN_SendCount ==2) //ID = 0x355 --- SOC/SOH + { + data[0] = canMem[0].soc & 0xFF; //SOC + data[1] = 0; + data[2] = canMem[0].soh & 0xFF; //SOH + data[3] = 0; + data[4] = 0X00; + data[5] = 0x00; + data[6] = 0x00; + data[7] = 0X00; + CAN1_SendData(0x355, &data[0]); + } + if(CAN_SendCount ==3) //ID = 0x356 --- 总电压/电流/平均温度 + { + tempVol = (uint16_t)(bmsMem.packVoltage/10); //单位0.01 + tempCur = (int16_t)(canMem[0].cur/10); //单位0.1 + T_Average = canMem[0].temp;//单位0.1 + + data[0] = tempVol & 0xFF; + data[1] = (tempVol >>8) & 0xFF; //电池包电压 + data[2] = tempCur & 0xFF; + data[3] = (tempCur >>8) & 0xFF; //电池包电流 + data[4] = (T_Average -2731) & 0xFF; + data[5] = ((T_Average -2731) >>8) & 0xFF; //温度-平均温度 + data[6] = 0x00; + data[7] = 0X00; + CAN1_SendData(0x356, &data[0]); + } + if(CAN_SendCount ==4) //ID = 0x35C --- 强充 + { + if(Deye_dsg_forbidFlg == 1) //Deye独有的强充标志变化值 + { + RequestFlag = 0x20; //强充请求 + } + else + { + RequestFlag = 0x00; //停止强充 + } + + data[0] = RequestFlag; + data[1] = 0x00; + data[2] = 0x00; + data[3] = 0x00; + data[4] = 0X00; + data[5] = 0x00; + data[6] = 0x00; + data[7] = 0X00; + CAN1_SendData(0x35C, &data[0]); + } + if(CAN_SendCount ==5) //0x35E --- 电池品牌 + { + data[0] = 0x00; + data[1] = 0x00; + data[2] = 0x00; + data[3] = 0x00; + data[4] = 0X00; + data[5] = 0x00; + data[6] = 0x00; + data[7] = 0X00; + CAN1_SendData(0x35E, &data[0]); + } + + if(CAN_SendCount>=6) + { + CAN_SendCount = 0; + } +} + +//MUST 美世乐 +void CAN_Protocol_MUST(void) +{ + uint8_t data[8]; +// uint16_t totalCapacity; + + uint16_t tempVol; + int16_t tempCur; + + uint16_t chgVolLimit; + uint16_t dsgVolLimit; + int16_t chgCurLimit; + int16_t dsgCurLimit; + + uint8_t alarmByte1 = 0; + + int16_t T_Average; // 平均温度 + + + //告警 +// //过压告警 +// if((canMem[0].status_byte3 & 0x0500) != 0) +// { +// if(canMem[0].soc < 99) +// { +// protectByte1 |= 0x01; +// } +// else +// { +// protectByte1 &= 0xfe; +// } +// } +// else +// { +// protectByte1 &= 0xfe; +// } + + //欠压告警 + if((canMem[0].status_byte3 & 0x0A00) != 0) + { + alarmByte1 |= 0x02; + } + else + { + alarmByte1 &= 0xfd; + } + + //充电过流告警 + if((canMem[0].status_byte3 & 0x1000) != 0) + { + alarmByte1 |= 0x04; + } + else + { + alarmByte1 &= 0xfb; + } + + //放电过流告警 + if((canMem[0].status_byte3 & 0x2000) != 0) + { + alarmByte1 |= 0x08; + } + else + { + alarmByte1 &= 0xf7; + } + + //过温告警 + if(((canMem[0].status_byte2 & 0x3300) != 0) || ((canMem[0].status_byte4 & 0x3000) != 0)) + { + alarmByte1 |= 0x10; + } + else + { + alarmByte1 &= 0xEF; + } + + //低温告警 + if(((canMem[0].status_byte2 & 0xCC00) != 0) || ((canMem[0].status_byte4 & 0xC000) != 0)) + { + alarmByte1 |= 0x20; + } + else + { + alarmByte1 &= 0xdf; + } + // BIT6 short circuit + if((canMem[0].status_byte1 & 0x20) != 0) + { + alarmByte1 |= 0x40; + } + else + { + alarmByte1 &= 0xbf; + } + + + if(CAN_SendCount ==0) //ID = 0x00030400 - 电池电压、电流、温度、报警 + { + tempVol = (uint16_t)(bmsMem.packVoltage/100); //单位0.01 + tempCur = (int16_t)(canMem[0].cur/10); //单位0.1 + T_Average = canMem[0].temp;// 平均温度 + + data[0] = tempVol & 0xFF; + data[1] = (tempVol >>8) & 0xFF; //电池包电压 + data[2] = tempCur & 0xFF; + data[3] = (tempCur >>8) & 0xFF; //电池包电流 + data[4] = ((T_Average -2731)/10) & 0xFF; + data[5] = ((T_Average -2731)/10 >>8) & 0xFF; //温度-暂时取平均温度，具体哪一路需要客户确认 //signed有符号数 + data[6] = alarmByte1; + data[7] = 0x00; + CAN1_SendData(0x00030400, &data[0]); + } + if(CAN_SendCount ==1) //ID = 0x00030500 —— SOC/SOH (修改) + { + data[0] = canMem[0].soc & 0xFF; //SOC + data[1] = 0; + data[2] = canMem[0].soh & 0xFF; //SOH + data[3] = 0; + data[4] = 0x00; + data[5] = 0x00; + data[6] = 0x00; + data[7] = 0x00; + CAN1_SendData(0x00030500, &data[0]); + } + if(CAN_SendCount ==2) //ID = 0x00030200 --- 电池禁用/SOC禁用(先给0x00测试，后换成0xFF测试) + { + data[0] = 0x00; //电池禁用标志 + data[1] = 0x00; + data[2] = 0x00; //SOC禁用标志 + data[3] = 0x00; + if(chg_forbidFlg == 1)//MUST + { + RequestFlag = 0xFF; //禁充 + } + else + { + RequestFlag = 0x00; //充电允许 + } + data[4] = RequestFlag; //电池充电禁用标志 + data[5] = RequestFlag; + if(dsg_forbidFlg == 1)//MUST + { + RequestFlag = 0xFF; //禁放 + } + else + { + RequestFlag = 0x00; //放电允许 + } + data[6] = RequestFlag; //电池放电禁用标志 + data[7] = RequestFlag; + CAN1_SendData(0x00030200, &data[0]); + } + if(CAN_SendCount ==3) //ID = 0x00030100 —— 充放电限压/限流 + { + //充放电电流限制需要有符号区别吗？ + chgVolLimit = bmsMem.inverter_chgVolLimit; //充电电压限制，上位机配置，默认值57.6V + dsgVolLimit = bmsMem.inverter_dsgVolLimit; //放电电压限制，上位机配置，默认值41.6V + + if(chg_forbidFlg == 1) + { + chgCurLimit = 0; //MUST禁充 + } + else if(chg_curlimitFlg == 1) + { + chgCurLimit = Inv_curlimit * (OnlineNum-chg_cur0Num); //限流40A*未保护个数 + } + else + { + chgCurLimit = bmsMem.inverter_chgCurLimit * (OnlineNum-chg_curLimitNum); //充电电流限制，上位机配置，默认值100A + } + if(dsg_forbidFlg == 1) + { + dsgCurLimit = 0; //MUST禁放 + } + else + { + dsgCurLimit = bmsMem.inverter_dsgCurLimit * (OnlineNum-dsg_curLimitNum); //放电电流限制，上位机配置，默认值100A + } + + data[0] = chgVolLimit & 0xFF; //充电电压限制低位 + data[1] = (chgVolLimit >> 8) & 0xFF; + data[2] = chgCurLimit & 0xFF; //充电电流限制低位 + data[3] = (chgCurLimit >> 8) & 0xFF; + data[4] = dsgVolLimit & 0xFF; //放电电压限制低位 + data[5] = (dsgVolLimit >> 8) & 0xFF; + data[6] = dsgCurLimit & 0xFF; //放电电流限制低位 + data[7] = (dsgCurLimit >> 8) & 0xFF; + CAN1_SendData(0x00030100, &data[0]); + } + if(CAN_SendCount ==4) //ID = 0x00030700 - 充放电/循环/远程快速停止命令(需要定制，先给0xFF) + { + if(chg_forceFlg == 1)//MUST + { + RequestFlag = 0xFF; //强充 + } + else + { + RequestFlag = 0x00; //不强充 + } + + data[0] = RequestFlag; //强充指令 + data[1] = RequestFlag; + data[2] = 0x00; //强放指令 + data[3] = 0x00; + data[4] = 0x00; //循环指令 + data[5] = 0x00; + data[6] = 0x00; //远程快速停止指令 + data[7] = 0x00; + CAN1_SendData(0x00030700, &data[0]); + } + + if(CAN_SendCount>=5) + { + CAN_SendCount = 0; + } +} + +//solis 锦浪 +void CAN_Protocol_solis(void) +{ + uint8_t data[8]; + uint16_t totalCapacity; + + uint16_t tempVol; + int16_t tempCur; + + uint16_t chgVolLimit; + uint16_t dsgVolLimit; + int16_t chgCurLimit; + int16_t dsgCurLimit; + + uint8_t protectByte1 = 0; + uint8_t protectByte2 = 0; + uint8_t alarmByte1 = 0; + uint8_t alarmByte2 = 0; + + + int16_t T_Average; // 平均温度 + + + //保护 + //放电过流保护 + //discharge over current，SC, OCD1, OCD2 + if( ((canMem[0].status_byte1 & 0x042c) != 0) || ((canMem[0].status_byte2 & 0x0010) != 0) || ((canMem[0].status_byte4 & 0x0020) != 0)) + { + protectByte1 |= 0x80; + } + else + { + protectByte1 &= 0x7f; + } + + //低温保护 + //under temp at charging or discharging + if(((canMem[0].status_byte2 & 0x0005) != 0) || ((canMem[0].status_byte4 & 0x0C0C) != 0)) + { + protectByte1 |= 0x10; + } + else + { + protectByte1 &= 0xef; + } + + //过温保护 + //over temp at charging or discharging + if(((canMem[0].status_byte2 & 0x000A) != 0) || ((canMem[0].status_byte4 & 0x0303) != 0)) + { + protectByte1 |= 0x08; + } + else + { + protectByte1 &= 0xf7; + } + + //欠压保护 + //cell_uv+pack_uv+l0v + if(((canMem[0].status_byte1 & 0x0202) != 0) || ((canMem[0].status_byte3 & 0x0008) != 0)) + { + protectByte1 |= 0x04; + } + else + { + protectByte1 &= 0xfb; + } + +// //过压保护 +// //cell_ov+pack_ov+pf +// if((canMem[0].status_byte1 & 0x0141) != 0) +// { +// if(canMem[0].soc < 99) +// { +// protectByte1 |= 0x02; +// } +// else +// { +// protectByte1 &= 0xfd; +// } +// } +// else +// { +// protectByte1 &= 0xfd; +// } + + //充电过流保护 + //charge over current + if( ((canMem[0].status_byte1 & 0x0010) != 0) || ((canMem[0].status_byte4 & 0x0010) != 0)) + { + protectByte2 |= 0x01; + } + else + { + protectByte2 &= 0xfe; + } + + //告警 + //放电过流告警 + if((canMem[0].status_byte3 & 0x2000) != 0) + { + alarmByte1 |= 0x80; + } + else + { + alarmByte1 &= 0x7f; + } + + //低温告警 + if(((canMem[0].status_byte2 & 0xCC00) != 0) || ((canMem[0].status_byte4 & 0xC000) != 0)) + { + alarmByte1 |= 0x10; + } + else + { + alarmByte1 &= 0xef; + } + + //过温告警 + if(((canMem[0].status_byte2 & 0x3300) != 0) || ((canMem[0].status_byte4 & 0x3000) != 0)) + { + alarmByte1 |= 0x08; + } + else + { + alarmByte1 &= 0xf7; + } + + //欠压告警 + if((canMem[0].status_byte3 & 0x0A00) != 0) + { + alarmByte1 |= 0x04; + } + else + { + alarmByte1 &= 0xfb; + } + +// //过压告警 +// if((canMem[0].status_byte3 & 0x0500) != 0) +// { +// if(canMem[0].soc < 99) +// { +// alarmByte1 |= 0x02; +// } +// else +// { +// alarmByte1 &= 0xfd; +// } +// } +// else +// { +// alarmByte1 &= 0xfd; +// } + + //充电过流告警 + if((canMem[0].status_byte3 & 0x1000) != 0) + { + alarmByte2 |= 0x01; + } + else + { + alarmByte2 &= 0xfe; + } + + + if(CAN_SendCount ==0) //ID=0x359 告警 + { + data[0] = protectByte1; //电芯过压 + data[1] = protectByte2; + data[2] = protectByte1; + data[3] = protectByte2; + data[4] = 0X00; + data[5] = 0X00; + data[6] = 0X00; + data[7] = 0X00; + CAN1_SendData(0x359, &data[0]); + } + if(CAN_SendCount ==1) //ID = 0x351 充放电限压/限流 + { + //充放电电流限制需要有符号区别吗？ + chgVolLimit = bmsMem.inverter_chgVolLimit; //充电电压限制，上位机配置，默认值57.6V + dsgVolLimit = bmsMem.inverter_dsgVolLimit; //放电电压限制，上位机配置，默认值41.6V + + if(chg_forbidFlg == 1) + { + chgCurLimit = 0; //GINLONG禁充 + } + else if(chg_curlimitFlg == 1) + { + chgCurLimit = Inv_curlimit * (OnlineNum-chg_cur0Num); //限流40A*未保护个数 + } + else + { + chgCurLimit = bmsMem.inverter_chgCurLimit * (OnlineNum-chg_curLimitNum); //充电电流限制，上位机配置，默认值100A + } + if(dsg_forbidFlg == 1) + { + dsgCurLimit = 0; //GINLONG禁放 + } + else + { + dsgCurLimit = bmsMem.inverter_dsgCurLimit * (OnlineNum-dsg_curLimitNum); //放电电流限制，上位机配置，默认值100A + } + + data[0] = chgVolLimit & 0xFF; //充电电压限制低位 + data[1] = (chgVolLimit >> 8) & 0xFF; + data[2] = chgCurLimit & 0xFF; //充电电流限制低位 + data[3] = (chgCurLimit >> 8) & 0xFF; + data[4] = dsgCurLimit & 0xFF; //放电电流限制低位 + data[5] = (dsgCurLimit >> 8) & 0xFF; + data[6] = dsgVolLimit & 0xFF; //放电电压限制低位 + data[7] = (dsgVolLimit >> 8) & 0xFF; + CAN1_SendData(0x351, &data[0]); + } + if(CAN_SendCount ==2) //ID = 0x355 SOC/SOH + { + data[0] = canMem[0].soc & 0xFF; //SOC + data[1] = 0; + data[2] = canMem[0].soh & 0xFF; //SOH + data[3] = 0; + data[4] = 0X00; + data[5] = 0x00; + data[6] = 0x00; + data[7] = 0X00; + CAN1_SendData(0x355, &data[0]); + } + if(CAN_SendCount ==3) //ID = 0x356 总电压/电流/温度 + { + tempVol = (uint16_t)(bmsMem.packVoltage/10); //单位0.01 + tempCur = (int16_t)(canMem[0].cur/10); //单位0.1 + T_Average = canMem[0].temp;// 平均温度 + + data[0] = tempVol & 0xFF; + data[1] = (tempVol >>8) & 0xFF; //电池包电压 + data[2] = tempCur & 0xFF; + data[3] = (tempCur >>8) & 0xFF; //电池包电流 + data[4] = (T_Average -2731) & 0xFF;; + data[5] = ((T_Average -2731) >>8) & 0xFF; //温度-暂时取平均温度，具体哪一路需要客户确认 + data[6] = 0x00; + data[7] = 0X00; + CAN1_SendData(0x356, &data[0]); + } + if(CAN_SendCount ==4) //ID = 0x35C 强充/满充 + { + if(chg_forceFlg == 1)//QINLONG + { + RequestFlag = 0x20; //强充请求 + } + else + { + RequestFlag = 0x00; //停止强充 + } + + data[0] = RequestFlag; + data[1] = 0x00; + data[2] = 0x00; + data[3] = 0x00; + data[4] = 0X00; + data[5] = 0x00; + data[6] = 0x00; + data[7] = 0X00; + CAN1_SendData(0x35C, &data[0]); + } + if(CAN_SendCount ==5) //0x35E + { + totalCapacity = ncc_Ah * OnlineNum; //单位1Ah + + data[0] = 0x00; + data[1] = 0x00; + data[2] = 0x00; + data[3] = 0x00; + data[4] = 0X00; + data[5] = 0x00; //电池制造商名称 + data[6] = totalCapacity & 0xFF; //容量 + data[7] = (totalCapacity >> 8) & 0xFF; + CAN1_SendData(0x35E, &data[0]); + } + if(CAN_SendCount ==6) //ID = 0x71C + { + data[0] = 0x00; + data[1] = 0x00; + data[2] = 0x00; + data[3] = 0x00; //电池序列号 + data[4] = 0x00; + data[5] = 0x00; //BMS固件版本 + data[6] = 0x00; //产品型号 + data[7] = 0x00; + CAN1_SendData(0x71C, &data[0]); + } + + if(CAN_SendCount>=7) + { + CAN_SendCount = 0; + } +} + +//Growatt 古瑞瓦特 +void CAN_Protocol_Growatt(void) //特改8.8 +{ + uint8_t data[8]; + uint16_t totalCapacity; //总容量 + uint16_t remainCapacity; //剩余容量 + + int16_t tempVol; //总电压 + int16_t tempCur; //总电流 + + uint16_t chgVolLimit; //充电限压 +// uint16_t dsgVolLimit; //放电限压 + uint16_t chgCurLimit; //充电限流 + uint16_t dsgCurLimit; //放电限流 + + uint8_t protectByte1 = 0; //保护位1，与告警位1值相同 + uint8_t protectByte2 = 0; //保护位2，与告警位2值相同 + + uint8_t statusByte1 = 0; //状态位1 + uint8_t statusByte2 = 0; //状态位2 + uint8_t totalNum = 0; //总电池节数 + + int16_t T_Average; // 平均温度 + int16_t T_Max; // 最高温度 + int16_t T_Min; // 最低温度 + uint16_t T_MaxIndex;// 最高温度序号，范围0-6 + uint16_t T_MinIndex;// 最低温度序号，范围0-6 + + uint16_t cellVolMax=0; // 电芯单体最高电压 + uint16_t cellVolMin=0; // 电芯单体最低电压 + uint16_t cellVolMaxIndex; // 电芯单体最高电压序号，范围0-15 + uint16_t cellVolMinIndex; // 电芯单体最低电压序号，范围0-15 + + + //保护、报警赋值： + //Data0 BIT3 cell uv-under voltage + if((canMem[0].status_byte1 & 0x02) !=0) + { + protectByte1 |= 0x08; + } + else + { + protectByte1 &= 0xF7; + } + //Data0 BIT4 cell ov-over voltage + if((canMem[0].status_byte1 & 0x01) !=0) + { + if(canMem[0].soc < 99) + { + protectByte1 |= 0x10; + } + else + { + protectByte1 &= 0xEF; + } + } + else + { + protectByte1 &= 0xEF; + } + //Data0 BIT5 sc-short circuit + + //Data0 BIT6 occ-charge over current + if( ((canMem[0].status_byte1 & 0x10) !=0) || ((canMem[0].status_byte4 & 0x10) !=0) ) + { + protectByte1 |= 0x40; + } + else + { + protectByte1 &= 0xBF; + } + //Data0 BIT7 ocd-discharge over current + if( ((canMem[0].status_byte1 & 0x2c) !=0) || ((canMem[0].status_byte4 & 0x20) !=0) ) + { + protectByte1 |= 0x80; + } + else + { + protectByte1 &= 0x7F; + } +// //Data1 BIT2 cell imbalance +// if((bmsMem.balanceStatus & 0x01) !=0) //表示开启了均衡 +// { +// protectByte2 |= 0xFB; +// } +// else +// { +// protectByte2 &= 0x04; +// } + //Data1 BIT4 cell utc-charge under temp + if( ((canMem[0].status_byte2 & 0x01) !=0) || ((canMem[0].status_byte4 & 0x04) !=0) ) + { + protectByte2 |= 0x10; + } + else + { + protectByte2 &= 0xEF; + } + //Data1 BIT5 cell utd-discharge under temp + if( ((canMem[0].status_byte2 & 0x04) !=0) || ((canMem[0].status_byte4 & 0x08) !=0) ) + { + protectByte2 |= 0x20; + } + else + { + protectByte2 &= 0xDF; + } + //Data1 BIT6 cell otc-charge over temp + if( ((canMem[0].status_byte2 & 0x02) !=0) || ((canMem[0].status_byte4 & 0x01) !=0) ) + { + protectByte2 |= 0x40; + } + else + { + protectByte2 &= 0xBF; + } + //Data1 BIT7 cell otd-discharge over temp + if( ((canMem[0].status_byte2 & 0x08) !=0) || ((canMem[0].status_byte4 & 0x02) !=0) ) + { + protectByte2 |= 0x80; + } + else + { + protectByte2 &= 0x7F; + } + + + //状态位赋值： + if(bmsMem.E2_485Snum != 1) //01并机/00单机模式 + { + statusByte1 |= 0x01; + } + else + { + statusByte1 &= 0xFE; + } + if(bCHGING == 1) //充电 + { + statusByte2 |= 0x02; + } + else + { + statusByte2 &= 0xFD; + } + if(bDSGING == 1) //放电 + { + statusByte2 |= 0x03; + } + else + { + statusByte2 &= 0xFC; + } +// if((bmsMem.balanceStatus & 0x01) !=0) //均衡状态 +// { +// statusByte2 |= 0x08; +// } +// else +// { +// statusByte2 &= 0xF7; +// } + + + if(CAN_SendCount ==0) //ID = 0x311 + { + //充放电电流限制需要有符号区别吗？ + chgVolLimit = bmsMem.inverter_chgVolLimit; //充电电压限制，上位机配置，默认值57.6V + //dsgVolLimit = bmsMem.inverter_dsgVolLimit; //放电电压限制，上位机配置，默认值41.6V + + if(chg_forbidFlg == 0) + { + chgCurLimit = bmsMem.inverter_chgCurLimit * (OnlineNum-chg_curLimitNum); //充电电流限制，上位机配置，默认值100A + } + else + { + chgCurLimit = 0; //Growatt禁充 + } + if(dsg_forbidFlg == 0) + { + dsgCurLimit = bmsMem.inverter_dsgCurLimit * (OnlineNum-dsg_curLimitNum); //放电电流限制，上位机配置，默认值100A + } + else + { + dsgCurLimit = 0; //Growatt禁放 + } + + statusByte2 |= 0x60; + if(chg_forbidFlg == 1)//Growatt + { + statusByte2 &= ~0x40; //禁充 bit6 + } + if(dsg_forbidFlg == 1)//Growatt + { + statusByte2 &= ~0x20; //禁放 bit5 + } + + data[0] = (chgVolLimit >> 8) & 0xFF; + data[1] = chgVolLimit & 0xFF; //充电电压限制低位 + data[2] = (chgCurLimit >> 8) & 0xFF; + data[3] = chgCurLimit & 0xFF; //充电电流限制低位 + data[4] = (dsgCurLimit >> 8) & 0xFF; + data[5] = dsgCurLimit & 0xFF; //放电电流限制低位 + data[6] = statusByte1; + data[7] = statusByte2; //状态位 + CAN1_SendData(0x311, &data[0]); + } + if(CAN_SendCount ==1) //ID = 0x312 - 保护/告警 + { + data[0] = protectByte1; + data[1] = protectByte2; + data[2] = protectByte1; + data[3] = protectByte2; + data[4] = OnlineNum; + data[5] = 0X00; + data[6] = 0X00; //电池降功率原因(暂无) + data[7] = 0X00; + CAN1_SendData(0x312, &data[0]); + } + if(CAN_SendCount ==2) //ID = 0x313 + { + tempVol = (int16_t)(bmsMem.packVoltage/10); //单位0.01 + tempCur = (int16_t)(canMem[0].cur/10); //单位0.1 + T_Average = canMem[0].temp;// 平均温度 + + data[0] = (tempVol >>8) & 0xFF; //电池组电压 0.01 + data[1] = tempVol & 0xFF; + data[2] = (tempCur >>8) & 0xFF; //电池组电流 0.1 + data[3] = tempCur & 0xFF; + data[4] = ((T_Average-2731) >>8) & 0xFF; + data[5] = (T_Average-2731) & 0xFF; //平均温度 0.1 + data[6] = canMem[0].soc & 0xFF; //SOC + data[7] = canMem[0].soh & 0xFF; //SOH + CAN1_SendData(0x313, &data[0]); + } + if(CAN_SendCount ==3) //ID = 0x314 + { + totalCapacity = 100 * fcc_Ah * OnlineNum; //单位0.01Ah + remainCapacity = 100 * rcc_Ah * OnlineNum; //单位0.01Ah + + data[0] = (remainCapacity >> 8) & 0xFF; + data[1] = remainCapacity & 0xFF; //剩余容量 10mAh + data[2] = (totalCapacity >> 8) & 0xFF; + data[3] = totalCapacity & 0xFF; //电池满充容量 10mAh + data[4] = 0x00; + data[5] = (canMem[0].VolMax - canMem[0].VolMin) & 0xFF; //最大电压差 1mV + data[6] = 0x00; + data[7] = 0x00; //循环次数(暂无) + CAN1_SendData(0x314, &data[0]); + } + if(CAN_SendCount ==4) //ID = 0x319 - 电池最低最高单体电压 + { + RequestFlag = 0xC0; //充电允许0x80，放电允许0x40，不强充~0x20 + if(chg_forbidFlg == 1)//Growatt + { + RequestFlag &= ~0x80; //禁充 + } + if(dsg_forbidFlg == 1)//Growatt + { + RequestFlag &= ~0x40; //禁放 + } + if(chg_forceFlg == 1)//Growatt + { + RequestFlag |= 0x20; //强充 + } + + cellVolMax = canMem[0].VolMax; + cellVolMin = canMem[0].VolMin; + cellVolMaxIndex = canMem[0].VolMaxIndex; + cellVolMinIndex = canMem[0].VolMinIndex; + + data[0] = RequestFlag; //充电允许放电允许 电池类型00 + data[1] = (cellVolMax >> 8) & 0xFF; + data[2] = cellVolMax & 0xFF; //最大单体电压 + data[3] = (cellVolMin >> 8) & 0xFF; + data[4] = cellVolMin & 0xFF; //最小单体电压 + data[5] = (cellVolMaxIndex+1) & 0xFF; //最大单体电压序号 + data[6] = (cellVolMinIndex+1) & 0xFF; //最小单体电压序号 + data[7] = 0x00; //故障电池地址(暂无) + CAN1_SendData(0x319, &data[0]); + } + if(CAN_SendCount ==5) //ID = 0x320 - 制造商缩写RICN SMART + { + data[0] = 'S'; + data[1] = 'R'; //制造商缩写 + data[2] = 0x00; + data[3] = 0x00; + data[4] = 0x00; + data[5] = 0x00; + data[6] = 0x00; + data[7] = 0x00; + CAN1_SendData(0x320, &data[0]); + } + if(CAN_SendCount ==6) //ID = 0x322 - 电池最低最高单体温度 + { + T_Max = canMem[0].TempMax; // 最高温度 + T_Min = canMem[0].TempMin; // 最低温度 + T_MaxIndex = canMem[0].TempMaxIndex;// 最高温度序号，范围0-6 + T_MinIndex = canMem[0].TempMinIndex;// 最低温度序号，范围0-6 + + data[0] = ((T_Max -2731) >> 8) & 0xFF; + data[1] = (T_Max -2731) & 0xFF; //最高单体温度 + data[2] = ((T_Min -2731) >> 8) & 0xFF; + data[3] = (T_Min -2731) & 0xFF; //最低单体温度 + data[4] = (T_MaxIndex+1) & 0xFF; //最高单体温度序号 + data[5] = (T_MinIndex+1) & 0xFF; //最低单体温度序号 + data[6] = 100; //最大SOC + data[7] = 0; //最小SOC + CAN1_SendData(0x322, &data[0]); + } + if(CAN_SendCount ==7) //ID = 0x323 - 总电池节数 + { + totalNum = bmsMem.ucCellNum * OnlineNum; + + data[0] = totalNum; //总电池节数 1-254 U8 + data[1] = 0x00; + data[2] = 0x00; + data[3] = 0x00; + data[4] = 0x00; + data[5] = 0x00; + data[6] = 0x00; + data[7] = 0x00; + CAN1_SendData(0x323, &data[0]); + } + + if(CAN_SendCount>=8) + { + CAN_SendCount = 0; + } +} + +//Aiswei 爱士惟 +void CAN_Protocol_Aiswei(void) +{ + uint8_t data[8]; + uint16_t totalCapacity; + + uint16_t tempVol; + int16_t tempCur; + + uint16_t chgVolLimit; +// uint16_t dsgVolLimit; + uint16_t chgCurLimit; + uint16_t dsgCurLimit; + + uint8_t protectByte1 = 0; + uint8_t protectByte2 = 0; + + int16_t T_Average; // 平均温度 + int16_t T_Max; // 最高温度 + int16_t T_Min; // 最低温度 + uint16_t T_MaxIndex;// 最高温度序号，范围0-6 + uint16_t T_MinIndex;// 最低温度序号，范围0-6 + + uint16_t cellVolMax=0; // 电芯单体最高电压-Aiswei + uint16_t cellVolMin=0; // 电芯单体最低电压-Aiswei + uint16_t cellVolMaxIndex; // 电芯单体最高电压序号，范围0-15-Aiswei + uint16_t cellVolMinIndex; // 电芯单体最低电压序号，范围0-15-Aiswei + + + uint8_t alarmByte1 = 0; + uint8_t alarmByte2 = 0; + + + //保护 + //放电过流保护 + //discharge over current，SC, OCD1, OCD2 + if( ((canMem[0].status_byte1 & 0x042c) != 0) || ((canMem[0].status_byte2 & 0x0010) != 0) || ((canMem[0].status_byte4 & 0x0020) != 0)) + { + protectByte1 |= 0x80; + } + else + { + protectByte1 &= 0x7f; + } + + //低温保护 + //under temp at charging or discharging + if(((canMem[0].status_byte2 & 0x0005) != 0) || ((canMem[0].status_byte4 & 0x0C0C) != 0)) + { + protectByte1 |= 0x10; + } + else + { + protectByte1 &= 0xef; + } + + //过温保护 + //over temp at charging or discharging + if(((canMem[0].status_byte2 & 0x000A) != 0) || ((canMem[0].status_byte4 & 0x0303) != 0)) + { + protectByte1 |= 0x08; + } + else + { + protectByte1 &= 0xf7; + } + + //欠压保护 + //cell_uv+pack_uv+l0v + if(((canMem[0].status_byte1 & 0x0202) != 0) || ((canMem[0].status_byte3 & 0x0008) != 0)) + { + protectByte1 |= 0x04; + } + else + { + protectByte1 &= 0xfb; + } + +// //过压保护 +// //cell_ov+pack_ov+pf +// if((canMem[0].status_byte1 & 0x0141) != 0) +// { +// if(canMem[0].soc < 99) +// { +// protectByte1 |= 0x02; +// } +// else +// { +// protectByte1 &= 0xfd; +// } +// } +// else +// { +// protectByte1 &= 0xfd; +// } + + //充电过流保护 + //charge over current + if( ((canMem[0].status_byte1 & 0x0010) != 0) || ((canMem[0].status_byte4 & 0x0010) != 0)) + { + protectByte2 |= 0x01; + } + else + { + protectByte2 &= 0xfe; + } + + //告警 + //放电过流告警 + if((canMem[0].status_byte3 & 0x2000) != 0) + { + alarmByte1 |= 0x80; + } + else + { + alarmByte1 &= 0x7f; + } + + //低温告警 + if(((canMem[0].status_byte2 & 0xCC00) != 0) || ((canMem[0].status_byte4 & 0xC000) != 0)) + { + alarmByte1 |= 0x10; + } + else + { + alarmByte1 &= 0xef; + } + + //过温告警 + if(((canMem[0].status_byte2 & 0x3300) != 0) || ((canMem[0].status_byte4 & 0x3000) != 0)) + { + alarmByte1 |= 0x08; + } + else + { + alarmByte1 &= 0xf7; + } + + //欠压告警 + if((canMem[0].status_byte3 & 0x0A00) != 0) + { + alarmByte1 |= 0x04; + } + else + { + alarmByte1 &= 0xfb; + } + +// //过压告警 +// if((canMem[0].status_byte3 & 0x0500) != 0) +// { +// if(canMem[0].soc < 99) +// { +// alarmByte1 |= 0x02; +// } +// else +// { +// alarmByte1 &= 0xfd; +// } +// } +// else +// { +// alarmByte1 &= 0xfd; +// } + + //充电过流告警 + if((canMem[0].status_byte3 & 0x1000) != 0) + { + alarmByte2 |= 0x01; + } + else + { + alarmByte2 &= 0xfe; + } + + + if(CAN_SendCount ==0) //ID=0x359 - 保护与警告（与Sol-Ark配置相同） + { + data[0] = protectByte1; //电芯过压 + data[1] = protectByte2; + data[2] = alarmByte1; + data[3] = alarmByte2; + data[4] = OnlineNum; + data[5] = 0x50; + data[6] = 0x4E; + data[7] = 0X00; + CAN1_SendData(0x359, &data[0]); + } + if(CAN_SendCount ==1) //ID: 0x351 - 充电电压/充电限流/放电限流(前3个与Sol-Ark配置相同，无4) + { + //充放电电流限制需要有符号区别吗？ + chgVolLimit = bmsMem.inverter_chgVolLimit; //充电电压限制，上位机配置，默认值57.6V + //dsgVolLimit = bmsMem.inverter_dsgVolLimit; //放电电压限制，上位机配置，默认值41.6V + + if(chg_forbidFlg == 1) + { + chgCurLimit = 0; //Aiswei禁充 + } + else if(chg_curlimitFlg == 1) + { + chgCurLimit = Inv_curlimit * (OnlineNum-chg_cur0Num); //限流40A*未保护个数 + } + else + { + chgCurLimit = bmsMem.inverter_chgCurLimit * (OnlineNum-chg_curLimitNum); //充电电流限制，上位机配置，默认值100A + } + if(dsg_forbidFlg == 1) + { + dsgCurLimit = 0; //Aiswei禁放 + } + else + { + dsgCurLimit = bmsMem.inverter_dsgCurLimit * (OnlineNum-dsg_curLimitNum); //放电电流限制，上位机配置，默认值100A + } + + data[0] = chgVolLimit & 0xFF; //充电电压限制低位 + data[1] = (chgVolLimit >> 8) & 0xFF; + data[2] = chgCurLimit & 0xFF; //充电电流限制低位 + data[3] = (chgCurLimit >> 8) & 0xFF; + data[4] = dsgCurLimit & 0xFF; //放电电流限制低位 + data[5] = (dsgCurLimit >> 8) & 0xFF; + data[6] = 0x00; + data[7] = 0x00; + CAN1_SendData(0x351, &data[0]); + } + if(CAN_SendCount ==2) //ID: 0x355 - SOC/SOH(与Sol-Ark配置相同) + { + data[0] = canMem[0].soc & 0xFF; //SOC + data[1] = 0; + data[2] = canMem[0].soh & 0xFF; //SOH + data[3] = 0; + data[4] = 0X00; + data[5] = 0x00; + data[6] = 0x00; + data[7] = 0X00; + CAN1_SendData(0x355, &data[0]); + } + if(CAN_SendCount ==3) //ID: 0x356 - 系统电压/系统总电流/平均单体温度(与Sol-Ark配置相同) + { + tempVol = (uint16_t)(bmsMem.packVoltage/10); //单位0.01 + tempCur = (int16_t)(canMem[0].cur/10); //单位0.1 + T_Average = canMem[0].temp;// 平均温度 + + data[0] = tempVol & 0xFF; + data[1] = (tempVol >>8) & 0xFF; //电池包电压 + data[2] = tempCur & 0xFF; + data[3] = (tempCur >>8) & 0xFF; //电池包电流 + data[4] = (T_Average -2731) & 0xFF;; + data[5] = ((T_Average -2731) >>8) & 0xFF; //温度-平均温度 + data[6] = 0x00; + data[7] = 0X00; + CAN1_SendData(0x356, &data[0]); + } + if(CAN_SendCount ==4) //ID: 0x35C - 满充请求/强制充电请求I/强制充电请求II/放电允许/充电允许(与Sol-Ark配置相同) + { + RequestFlag = 0xC0; //充电允许0x80，放电允许0x40，不强充~0x20 + if(chg_forbidFlg == 1)//Aiswei + { + RequestFlag &= 0x7F; //禁充 + } + if(dsg_forbidFlg == 1)//Aiswei + { + RequestFlag &= 0xBF; //禁放 + } + if(chg_forceFlg == 1)//Aiswei + { + RequestFlag |= 0x20; //强充 + } + + data[0] = RequestFlag; //充电允许，放电允许 + data[1] = 0x00; + data[2] = 0x00; + data[3] = 0x00; + data[4] = 0X00; + data[5] = 0x00; + data[6] = 0x00; + data[7] = 0X00; + CAN1_SendData(0x35C, &data[0]); + } + if(CAN_SendCount ==5) //ID: 0x379 - 总容量/当前在线数量（与Sol-Ark配置相同） + { + totalCapacity = ncc_Ah * OnlineNum; //单位1Ah + + data[0] = totalCapacity & 0xFF; //电池容量 + data[1] = (totalCapacity >> 8) & 0xFF; + data[2] = 0x00; + data[3] = 0x00; + data[4] = 0X00; + data[5] = 0x00; + data[6] = 0x00; + data[7] = 0X00; + CAN1_SendData(0x379, &data[0]); + } + if(CAN_SendCount ==6) //ID: 0x35e - 厂家名称"AISWEI"-ASCII（与Sol-Ark配置相同） + { + data[0] = 'B'; + data[1] = 'T'; + data[2] = 'Y'; + data[3] = 'G'; + data[4] = '-'; + data[5] = 'B'; + data[6] = 'M'; + data[7] = 'S'; + CAN1_SendData(0x35e, &data[0]); + } + if(CAN_SendCount ==7) //ID = 0x373 - 最大/最小单体电压/温度（与固德威配置相同） + { + cellVolMax = canMem[0].VolMax/100; + cellVolMin = canMem[0].VolMin/100; + T_Max = canMem[0].TempMax; // 最高温度 + T_Min = canMem[0].TempMin; // 最低温度 + + data[0] = cellVolMin & 0xFF; //最小单体电压 + data[1] = (cellVolMin >> 8) & 0xFF; + data[2] = cellVolMax & 0xFF; //最大单体电压 + data[3] = (cellVolMax >> 8) & 0xFF; + data[4] = (T_Min -2731) & 0xFF; //最小单体温度 + data[5] = ((T_Min -2731) >> 8) & 0xFF; + data[6] = (T_Max -2731) & 0xFF; //最大单体温度 + data[7] = ((T_Max -2731) >> 8) & 0xFF; + CAN1_SendData(0x373, &data[0]); + } + if(CAN_SendCount ==8) //ID: 0x374 - 最大/最小单体温度/电压的ID（与固德威配置相同） + { + cellVolMaxIndex = canMem[0].VolMaxIndex; + cellVolMinIndex = canMem[0].VolMinIndex; + T_MaxIndex = canMem[0].TempMaxIndex;// 最高温度序号，范围0-6 + T_MinIndex = canMem[0].TempMinIndex;// 最低温度序号，范围0-6 + + data[0] = (cellVolMinIndex+1) & 0xFF; //最小单体电压序号 + data[1] = ((cellVolMinIndex+1) >> 8) & 0xFF; + data[2] = (cellVolMaxIndex+1) & 0xFF; //最大单体电压序号 + data[3] = ((cellVolMaxIndex+1) >> 8) & 0xFF; + data[4] = (T_MinIndex+1) & 0xFF; //最小单体温度序号 + data[5] = ((T_MinIndex+1) >> 8) & 0xFF; + data[6] = (T_MaxIndex+1) & 0xFF; //最大单体温度序号，实际显示从1开始 + data[7] = ((T_MaxIndex+1) >> 8) & 0xFF; + CAN1_SendData(0x374, &data[0]); + } + + if(CAN_SendCount>=9) + { + CAN_SendCount = 0; + } +} + +//Afore 艾伏 +void CAN_Protocol_Afore(void) +{ + uint8_t data[8]; + + uint16_t tempVol; + int16_t tempCur; + + uint16_t chgVolLimit; + uint16_t dsgVolLimit; + uint16_t chgCurLimit; + uint16_t dsgCurLimit; + + uint8_t protectByte1 = 0; //故障H + uint8_t protectByte2 = 0; //故障 + uint8_t statusbyte = 0; //故障L + + uint8_t alarmByte1 = 0; //告警 + uint8_t alarmByte2 = 0; + + int16_t T_Average; // 平均温度 + int16_t T_Max; // 最高温度 + int16_t T_Min; // 最低温度 + uint16_t T_MaxIndex;// 最高温度序号，范围0-6 + uint16_t T_MinIndex;// 最低温度序号，范围0-6 + + uint16_t cellVolMax=0; // 电芯单体最高电压-Afore + uint16_t cellVolMin=0; // 电芯单体最低电压-Afore + uint16_t cellVolMaxIndex; // 电芯单体最高电压序号，范围0-15-Afore + uint16_t cellVolMinIndex; // 电芯单体最低电压序号，范围0-15-Afore + + + //保护 + //充电过流保护 + //charge over current + if( ((canMem[0].status_byte1 & 0x0010) != 0) || ((canMem[0].status_byte4 & 0x0010) != 0)) + { + protectByte1 |= 0x80; + } + else + { + protectByte1 &= 0x7F; + } + + //低温保护 + //under temp at charging or discharging + if(((canMem[0].status_byte2 & 0x0005) != 0) || ((canMem[0].status_byte4 & 0x0C0C) != 0)) + { + protectByte1 |= 0x20; + } + else + { + protectByte1 &= 0xDF; + } + + //过温保护 + //over temp at charging or discharging + if(((canMem[0].status_byte2 & 0x000A) != 0) || ((canMem[0].status_byte4 & 0x0303) != 0)) + { + protectByte1 |= 0x40; + } + else + { + protectByte1 &= 0xBF; + } + + //总体欠压保护 + if((canMem[0].status_byte1 & 0x0200) !=0) + { + protectByte1 |= 0x08; + } + else + { + protectByte1 &= 0xF7; + } + +// //总体过压保护 +// if((canMem[0].status_byte1 & 0x0100) !=0) +// { +// if(canMem[0].soc < 99) +// { +// protectByte1 |= 0x04; +// } +// else +// { +// protectByte1 &= 0xFb; +// } +// } +// else +// { +// protectByte1 &= 0xFb; +// } + + //单体欠压保护 + if(((canMem[0].status_byte1 & 0x0002) !=0) || ((canMem[0].status_byte3 & 0x0008) != 0)) + { + protectByte1 |= 0x02; + } + else + { + protectByte1 &= 0xFD; + } + +// //单体过压保护 +// if(((canMem[0].status_byte1 & 0x0001) !=0) || ((canMem[0].status_byte1 & 0x0040) != 0)) +// { +// if(canMem[0].soc < 99) +// { +// protectByte1 |= 0x01; +// } +// else +// { +// protectByte1 &= 0xFE; +// } +// } +// else +// { +// protectByte1 &= 0xFE; +// } + + //放电过流保护 + //discharge over current，SC, OCD1, OCD2 + if( ((canMem[0].status_byte1 & 0x042c) != 0) || ((canMem[0].status_byte2 & 0x0010) != 0) || ((canMem[0].status_byte4 & 0x0020) != 0)) + { + protectByte2 |= 0x01; + } + else + { + protectByte2 &= 0xFE; + } + + + //告警 + //低温告警 + if(((canMem[0].status_byte2 & 0xCC00) != 0) || ((canMem[0].status_byte4 & 0xC000) != 0)) + { + alarmByte1 |= 0x80; + } + else + { + alarmByte1 &= 0x7F; + } + + //过温告警 + if(((canMem[0].status_byte2 & 0x3300) != 0) || ((canMem[0].status_byte4 & 0x3000) != 0)) + { + alarmByte1 |= 0x40; + } + else + { + alarmByte1 &= 0xBF; + } + + //总体欠压告警 + if((canMem[0].status_byte3 & 0x0800) !=0) + { + alarmByte1 |= 0x08; + } + else + { + alarmByte1 &= 0xF7; + } + +// //总体过压告警 +// if((canMem[0].status_byte3 & 0x0400) !=0) +// { +// if(canMem[0].soc < 99) +// { +// alarmByte1 |= 0x04; +// } +// else +// { +// alarmByte1 &= 0xFb; +// } +// } +// else +// { +// alarmByte1 &= 0xFb; +// } + + //单体欠压告警 + if((canMem[0].status_byte3 & 0x0200) !=0) + { + alarmByte1 |= 0x02; + } + else + { + alarmByte1 &= 0xFD; + } + +// //单体过压告警 +// if((canMem[0].status_byte3 & 0x0100) !=0) +// { +// alarmByte1 |= 0x01; +// } +// else +// { +// alarmByte1 &= 0xFE; +// } + + //放电过流告警 + if((canMem[0].status_byte3 & 0x2000) != 0) + { + alarmByte2 |= 0x02; + } + else + { + alarmByte2 &= 0xFD; + } + + //充电过流告警 + if((canMem[0].status_byte3 & 0x1000) != 0) + { + alarmByte2 |= 0x01; + } + else + { + alarmByte2 &= 0xFE; + } + +// if((bmsMem.balanceStatus & 0x01) !=0) //均衡状态 +// { +// statusbyte |= 0x80; +// } +// else +// { +// statusbyte &= 0x7F; +// } + + + if(CAN_SendCount ==0) //ID: 0x350 - 运行信息(系统电压/系统总电流/平均单体温度) + { + tempVol = (uint16_t)(bmsMem.packVoltage/100); //单位0.1V + tempCur = (int16_t)((canMem[0].cur/10) + 5000); //单位0.1A(偏移5000) + T_Average = (canMem[0].temp + 1000);// 平均温度 单位0.1℃(偏移1000) + + data[0] = tempVol & 0xFF; + data[1] = (tempVol >>8) & 0xFF; //电池包电压 + data[2] = tempCur & 0xFF; + data[3] = (tempCur >>8) & 0xFF; //电池包电流 + data[4] = (T_Average -2731) & 0xFF;; + data[5] = ((T_Average -2731) >>8) & 0xFF; //温度-平均温度 + data[6] = 0x00; + data[7] = 0X00; + CAN1_SendData(0x350, &data[0]); + } + if(CAN_SendCount ==1) //ID: 0x351 - 电池信息(SOC/SOH) + { + RequestFlag = 0x23; //充电允许0x01，放电允许0x02，不强充~0x04 + if(chg_forbidFlg == 1)//Afore + { + RequestFlag &= 0xFE; //禁充 + } + if(dsg_forbidFlg == 1)//Afore + { + RequestFlag &= 0xFD; //禁放 + } + if(chg_forceFlg == 1)//Afore + { + RequestFlag |= 0x04; //强充 + } + + data[0] = canMem[0].soc & 0xFF; //SOC + data[1] = canMem[0].soh & 0xFF; //SOH + data[2] = 0x64; //最大SOC + data[3] = 0x00; //最小SOC + data[4] = RequestFlag; //充放电允许及BMS工作状态 + data[5] = 0x00; + data[6] = bmsMem.ucCellNum; //电芯数量 + data[7] = 0X00; + CAN1_SendData(0x351, &data[0]); + } + if(CAN_SendCount ==2) //ID: 0x352 - 保护参数(充/放电限流/压) + { + //充放电电流限制需要有符号区别吗？ + chgVolLimit = bmsMem.inverter_chgVolLimit; //充电电压限制，上位机配置，默认值57.6V + dsgVolLimit = bmsMem.inverter_dsgVolLimit; //放电电压限制，上位机配置，默认值41.6V + + if(chg_forbidFlg == 1) + { + chgCurLimit = 0; //Afore禁充 + } + else if(chg_curlimitFlg == 1) + { + chgCurLimit = Inv_curlimit * (OnlineNum-chg_cur0Num); //限流40A*未保护个数 + } + else + { + chgCurLimit = bmsMem.inverter_chgCurLimit * (OnlineNum-chg_curLimitNum); //充电电流限制，上位机配置，默认值100A + } + if(dsg_forbidFlg == 1) + { + dsgCurLimit = 0; //Afore禁放 + } + else + { + dsgCurLimit = bmsMem.inverter_dsgCurLimit * (OnlineNum-dsg_curLimitNum); //放电电流限制，上位机配置，默认值100A + } + + data[0] = chgCurLimit & 0xFF; //充电电流限制低位 + data[1] = (chgCurLimit >> 8) & 0xFF; + data[2] = dsgCurLimit & 0xFF; //放电电流限制低位 + data[3] = (dsgCurLimit >> 8) & 0xFF; + data[4] = chgVolLimit & 0xFF; //充电电压限制低位 + data[5] = (chgVolLimit >> 8) & 0xFF; + data[6] = dsgVolLimit & 0xFF; //放电电压限制低位 + data[7] = (dsgVolLimit >> 8) & 0xFF; + CAN1_SendData(0x352, &data[0]); + } + if(CAN_SendCount ==3) //ID: 0x353 - 故障 + { + data[0] = protectByte1;//故障H + data[1] = protectByte2;//故障L + data[2] = 0x00; + data[3] = statusbyte; + data[4] = 0x00; + data[5] = 0x00; + data[6] = 0x00; + data[7] = 0x00; + CAN1_SendData(0x353, &data[0]); + } + if(CAN_SendCount ==4) //ID = 0x354 - 单体电压参数(最大/最小单体电压及序号) + { + cellVolMax = canMem[0].VolMax; + cellVolMin = canMem[0].VolMin; + cellVolMaxIndex = canMem[0].VolMaxIndex; + cellVolMinIndex = canMem[0].VolMinIndex; + + data[0] = cellVolMax & 0xFF; //最大单体电压 + data[1] = (cellVolMax >> 8) & 0xFF; + data[2] = cellVolMin & 0xFF; //最小单体电压 + data[3] = (cellVolMin >> 8) & 0xFF; + data[4] = (cellVolMaxIndex+1) & 0xFF; //最大单体电压序号 + data[5] = ((cellVolMaxIndex+1) >> 8) & 0xFF; + data[6] = (cellVolMinIndex+1) & 0xFF; //最小单体电压序号 + data[7] = ((cellVolMinIndex+1) >> 8) & 0xFF; + CAN1_SendData(0x354, &data[0]); + } + if(CAN_SendCount ==5) //ID = 0x355 - 单体温度参数(最大/最小温度及序号) + { + T_Max = (canMem[0].TempMax + 1000); // 最高温度 单位0.1℃ (偏移1000) + T_Min = canMem[0].TempMin; // 最低温度 单位0.1℃ (协议中未要求偏移) + T_MaxIndex = canMem[0].TempMaxIndex;// 最高温度序号，范围0-6 + T_MinIndex = canMem[0].TempMinIndex;// 最低温度序号，范围0-6 + + data[0] = (T_Max -2731) & 0xFF; //最大单体温度 + data[1] = ((T_Max -2731) >> 8) & 0xFF; + data[2] = (T_Min -2731) & 0xFF; //最小单体温度 + data[3] = ((T_Min -2731) >> 8) & 0xFF; + data[4] = (T_MaxIndex+1) & 0xFF; //最大单体温度序号，实际显示从1开始 + data[5] = ((T_MaxIndex+1) >> 8) & 0xFF; + data[6] = (T_MinIndex+1) & 0xFF; //最小单体温度序号 + data[7] = ((T_MinIndex+1) >> 8) & 0xFF; + CAN1_SendData(0x355, &data[0]); + } + if(CAN_SendCount ==6) //ID = 0x357 - 告警信息 + { + data[0] = alarmByte1; + data[1] = alarmByte2; + data[2] = 0x00; + data[3] = 0x00; + data[4] = 0x00; + data[5] = 0x00; + data[6] = 0x00; + data[7] = 0x00; + CAN1_SendData(0x357, &data[0]); + } + if(CAN_SendCount ==7) //ID: 0x356 - 单体保护参数(因电池特性不同，参数暂未给定) + { + data[0] = 0x00; + data[1] = 0x00; + data[2] = 0x00; + data[3] = 0x00; + data[4] = 0x00; + data[5] = 0x00; + data[6] = 0x00; + data[7] = 0x00; + CAN1_SendData(0x356, &data[0]); + } + if(CAN_SendCount ==8) //ID=0x358 - 版本信息 + { + data[0] = 0x00;//硬件版本V + data[1] = 0x00;//硬件版本R + data[2] = 0x00;//软件版本V + data[3] = 0x00;//软件版本R + data[4] = 0x00; + data[5] = 0x00; + data[6] = 0x00; + data[7] = 0x00; + CAN1_SendData(0x358, &data[0]); + } + if(CAN_SendCount ==9) //ID=0x359 电池SN 0~7 + { + data[0] = 0x00; + data[1] = 0x00; + data[2] = 0x00; + data[3] = 0x00; + data[4] = 0x00; + data[5] = 0x00; + data[6] = 0x00; + data[7] = 0x00; + CAN1_SendData(0x359, &data[0]); + } + if(CAN_SendCount ==10) //ID=0x35A - 电池SN 8~15 + { + data[0] = 0x00; + data[1] = 0x00; + data[2] = 0x00; + data[3] = 0x00; + data[4] = 0x00; + data[5] = 0x00; + data[6] = 0x00; + data[7] = 0x00; + CAN1_SendData(0x35A, &data[0]); + } + + if(CAN_SendCount>=11) + { + CAN_SendCount = 0; + } +} + +//Victron 维克托 +void CAN_Protocol_Victron(void) +{ + uint8_t data[8]; + uint16_t totalCapacity;//总容量 + + uint16_t tempVol; + int16_t tempCur; + + uint16_t chgVolLimit; + uint16_t dsgVolLimit; + int16_t chgCurLimit; + int16_t dsgCurLimit; + + uint8_t protectByte1 = 0; + uint8_t protectByte2 = 0; + uint8_t protectByte3 = 0; + uint8_t protectByte4 = 0; + + uint8_t alarmByte1 = 0; + uint8_t alarmByte2 = 0; + uint8_t alarmByte3 = 0; + uint8_t alarmByte4 = 0; + + + int16_t T_Average = 0; + int16_t T_Max; // 最高温度 + int16_t T_Min; // 最低温度 + uint16_t T_MaxIndex;// 最高温度序号，范围0-6 + uint16_t T_MinIndex;// 最低温度序号，范围0-6 + + uint16_t cellVolMax=0; // 电芯单体最高电压-Victron + uint16_t cellVolMin=0; // 电芯单体最低电压-Victron + uint16_t cellVolMaxIndex_Byte1; // 电芯单体最高电压序号，范围0-15-Victron + uint16_t cellVolMaxIndex_Byte2; + uint16_t cellVolMinIndex_Byte1; // 电芯单体最低电压序号，范围0-15-Victron + uint16_t cellVolMinIndex_Byte2; + + + //Data0 BIT0.1 General[Cancel] //0000 0010 + protectByte1 |= 0x01; + + //保护 + //放电高温保护 + //over temp at discharging + if(((canMem[0].status_byte2 & 0x0008) != 0) || ((canMem[0].status_byte4 & 0x0202) != 0)) + { + protectByte1 &= 0x7f; + protectByte1 |= 0x40; + } + else + { + protectByte1 &= 0xbf; + protectByte1 |= 0x80; + } + + //欠压保护 + //cell_uv+pack_uv+l0v + if(((canMem[0].status_byte1 & 0x0202) != 0) || ((canMem[0].status_byte3 & 0x0008) != 0)) + { + protectByte1 &= 0xdf; + protectByte1 |= 0x10; + } + else + { + protectByte1 &= 0xef; + protectByte1 |= 0x20; + } + +// //过压保护 +// //cell_ov+pack_ov+pf +// if((canMem[0].status_byte1 & 0x0141) != 0) +// { +// if(canMem[0].soc < 99) +// { +// protectByte1 &= 0xf7; //去掉leave +// protectByte1 |= 0x04; //赋值arrive +// } +// else +// { +// protectByte1 &= 0xfb; +// protectByte1 |= 0x08; +// } +// } +// else +// { +// protectByte1 &= 0xfb; +// protectByte1 |= 0x08; +// } + + //放电过流保护 + //discharge over current，SC, OCD1, OCD2 + if( ((canMem[0].status_byte1 & 0x042c) != 0) || ((canMem[0].status_byte2 & 0x0010) != 0) || ((canMem[0].status_byte4 & 0x0020) != 0)) + { + protectByte2 &= 0x7f; + protectByte2 |= 0x40; + } + else + { + protectByte2 &= 0xbf; + protectByte2 |= 0x80; + } + + //充电低温保护 + //Data1 BIT4.5 under temp at charging //0001 0000 + if( ((canMem[0].status_byte2 & 0x0001) != 0) || ((canMem[0].status_byte4 & 0x0404) != 0) ) + { + protectByte2 &= 0xdf; + protectByte2 |= 0x10; + } + else + { + protectByte2 &= 0xef; + protectByte2 |= 0x20; + } + + //充电高温保护 + //Data1 BIT2.3 over temp at charging //0000 0100 + if( ((canMem[0].status_byte2 & 0x0002) != 0) || ((canMem[0].status_byte4 & 0x0101) != 0) ) + { + protectByte2 &= 0xf7; + protectByte2 |= 0x04; + } + else + { + protectByte2 &= 0xfb; + protectByte2 |= 0x08; + } + + //放电低温保护 + //Data1 BIT0.1 under temp at discharging //0000 0001 + if( ((canMem[0].status_byte2 & 0x0004) != 0) || ((canMem[0].status_byte4 & 0x0808) != 0) ) + { + protectByte2 &= 0xfd; + protectByte2 |= 0x01; + } + else + { + protectByte2 &= 0xfe; + protectByte2 |= 0x02; + } + + //短路 + //Data2 BIT4.5 short circuit //0001 0000 + if((canMem[0].status_byte1 & 0x20) != 0) + { + protectByte3 &= 0xdf; + protectByte3 |= 0x10; + } + else + { + protectByte3 &= 0xef; + protectByte3 |= 0x20; + } + + //充电过流保护 + //charge over current + if( ((canMem[0].status_byte1 & 0x0010) != 0) || ((canMem[0].status_byte4 & 0x0010) != 0)) + { + protectByte3 &= 0xfd; + protectByte3 |= 0x01; + } + else + { + protectByte3 &= 0xfe; + protectByte3 |= 0x02; + } + //Data2 BIT2.3 Contactor[Cancel] //0000 1000 + protectByte3 |= 0x08; + //Data2 BIT6.7 BMS internal[Cancel] //1000 0000 + protectByte3 |= 0x80; +// //Data3 BIT0.1 cell imbanlance //0000 0001 +// if((bmsMem.balanceStatus & 0x01) !=0) //0x01表示平衡 +// { +// protectByte4 &= 0xfe; +// protectByte4 |= 0x02; +// } +// else +// { +// protectByte4 &= 0xfd; +// protectByte4 |= 0x01; +// } + + + //告警 + //放电高温告警 + //over temp at discharging + if(((canMem[0].status_byte2 & 0x2200) != 0) || ((canMem[0].status_byte4 & 0x2000) != 0)) + { + alarmByte1 &= 0x7f; + alarmByte1 |= 0x40; + } + else + { + alarmByte1 &= 0xbf; + alarmByte1 |= 0x80; + } + + //欠压告警 + if((canMem[0].status_byte3 & 0x0A00) != 0) + { + alarmByte1 &= 0xdf; + alarmByte1 |= 0x10; + } + else + { + alarmByte1 &= 0xef; + alarmByte1 |= 0x20; + } + +// //过压告警 +// if((canMem[0].status_byte3 & 0x0500) != 0) +// { +// if(canMem[0].soc < 99) +// { +// alarmByte1 &= 0xf7; //去掉leave +// alarmByte1 |= 0x04; //赋值arrive +// } +// else +// { +// alarmByte1 &= 0xfb; +// alarmByte1 |= 0x08; +// } +// } +// else +// { +// alarmByte1 &= 0xfb; +// alarmByte1 |= 0x08; +// } + + //放电过流告警 + if((canMem[0].status_byte3 & 0x2000) != 0) + { + alarmByte2 &= 0x7f; + alarmByte2 |= 0x40; + } + else + { + alarmByte2 &= 0xbf; + alarmByte2 |= 0x80; + } + + //充电低温告警 + //Data1 BIT4.5 under temp at charging //0001 0000 + if( ((canMem[0].status_byte2 & 0x4400) != 0) || ((canMem[0].status_byte4 & 0x4000) != 0) ) + { + alarmByte2 &= 0xdf; + alarmByte2 |= 0x10; + } + else + { + alarmByte2 &= 0xef; + alarmByte2 |= 0x20; + } + + //充电高温告警 + //Data1 BIT2.3 over temp at charging //0000 0100 + if( ((canMem[0].status_byte2 & 0x1100) != 0) || ((canMem[0].status_byte4 & 0x1000) != 0) ) + { + alarmByte2 &= 0xf7; + alarmByte2 |= 0x04; + } + else + { + alarmByte2 &= 0xfb; + alarmByte2 |= 0x08; + } + + //放电低温告警 + //Data1 BIT0.1 under temp at discharging //0000 0001 + if( ((canMem[0].status_byte2 & 0x8800) != 0) || ((canMem[0].status_byte4 & 0x8000) != 0) ) + { + alarmByte2 &= 0xfd; + alarmByte2 |= 0x01; + } + else + { + alarmByte2 &= 0xfe; + alarmByte2 |= 0x02; + } + + //短路 + //Data2 BIT4.5 short circuit //0001 0000 + if((canMem[0].status_byte1 & 0x20) != 0) + { + alarmByte3 &= 0xdf; + alarmByte3 |= 0x10; + } + else + { + alarmByte3 &= 0xef; + alarmByte3 |= 0x20; + } + + //充电过流告警 + if((canMem[0].status_byte3 & 0x1000) != 0) + { + alarmByte3 &= 0xfd; + alarmByte3 |= 0x01; + } + else + { + alarmByte3 &= 0xfe; + alarmByte3 |= 0x02; + } + +// if((bmsMem.balanceStatus & 0x01) !=0) //0x01表示平衡 +// { +// alarmByte4 &= 0xfe; +// alarmByte4 |= 0x02; +// } +// else +// { +// alarmByte4 &= 0xfd; +// alarmByte4 |= 0x01; +// } + + + if(CAN_SendCount ==0) //ID=0x35A - Alarms/Warnings + { + data[0] = protectByte1; + data[1] = protectByte2; + data[2] = protectByte3; + data[3] = protectByte4; + data[4] = alarmByte1; //报警和保护信号相同 + data[5] = alarmByte2; + data[6] = alarmByte3; + data[7] = alarmByte4; + CAN1_SendData(0x35A, &data[0]); + } + if(CAN_SendCount ==1) //ID = 0x351 - 电池充电/放电电压，充电/放电限流 + { + //充放电电流限制需要有符号区别吗？ + chgVolLimit = bmsMem.inverter_chgVolLimit; //充电电压限制，上位机配置，默认值57.6V + dsgVolLimit = bmsMem.inverter_dsgVolLimit; //放电电压限制，上位机配置，默认值41.6V + + if(chg_forbidFlg == 1) + { + chgCurLimit = 0; //Victron禁充 + } + else if(chg_curlimitFlg == 1) + { + chgCurLimit = Inv_curlimit * (OnlineNum-chg_cur0Num); //限流40A*未保护个数 + } + else + { + chgCurLimit = bmsMem.inverter_chgCurLimit * (OnlineNum-chg_curLimitNum); //充电电流限制，上位机配置，默认值100A + } + if(dsg_forbidFlg == 1) + { + dsgCurLimit = 0; //Victron禁放 + } + else + { + dsgCurLimit = bmsMem.inverter_dsgCurLimit * (OnlineNum-dsg_curLimitNum); //放电电流限制，上位机配置，默认值100A + } + + data[0] = chgVolLimit & 0xFF; //充电电压限制低位 + data[1] = (chgVolLimit >> 8) & 0xFF; + data[2] = chgCurLimit & 0xFF; //充电电流限制低位 + data[3] = (chgCurLimit >> 8) & 0xFF; + data[4] = dsgCurLimit & 0xFF; //放电电流限制低位 + data[5] = (dsgCurLimit >> 8) & 0xFF; + data[6] = dsgVolLimit & 0xFF; //放电电压限制低位 + data[7] = (dsgVolLimit >> 8) & 0xFF; + CAN1_SendData(0x351, &data[0]); + } + if(CAN_SendCount ==2) //ID = 0x355 - 电量SOC/SOH + { + data[0] = canMem[0].soc & 0xFF; //SOC + data[1] = 0; + data[2] = canMem[0].soh & 0xFF; //SOH + data[3] = 0; + data[4] = 0X00; + data[5] = 0x00; + data[6] = 0x00; + data[7] = 0X00; + CAN1_SendData(0x355, &data[0]); + } + if(CAN_SendCount ==3) //ID = 0x356 - 电池电压/电流/温度 + { + tempVol = (uint16_t)(bmsMem.packVoltage/10); //单位0.01 + tempCur = (int16_t)(canMem[0].cur/10); //单位0.1 + T_Average = canMem[0].temp;//单位0.1 + + data[0] = tempVol & 0xFF; + data[1] = (tempVol >>8) & 0xFF; //电池包电压 + data[2] = tempCur & 0xFF; + data[3] = (tempCur >>8) & 0xFF; //电池包电流 + data[4] = (T_Average -2731) & 0xFF;; + data[5] = ((T_Average -2731) >>8) & 0xFF; //温度-平均温度 + data[6] = 0x00; + data[7] = 0X00; + CAN1_SendData(0x356, &data[0]); + } + if(CAN_SendCount ==4) //ID = 0x35E - 制造商名称-ASCII + { + data[0] = 'B'; + data[1] = 'T'; + data[2] = 'Y'; + data[3] = 'G'; + data[4] = '-'; + data[5] = 'B'; + data[6] = 'M'; + data[7] = 'S'; + CAN1_SendData(0x35E, &data[0]); + } + if(CAN_SendCount ==5) //ID = 0x370 - 电池/BMS名称第1部分 + { + data[0] = 'B'; + data[1] = 'T'; + data[2] = 'Y'; + data[3] = 'G'; + data[4] = 0X00; + data[5] = 0X00; + data[6] = 0X00; + data[7] = 0X00; + CAN1_SendData(0x370, &data[0]); + } + if(CAN_SendCount ==6) //ID = 0x371 - 电池/BMS名称第2部分 + { + data[0] = 'B'; + data[1] = 'M'; + data[2] = 'S'; + data[3] = 0X00; + data[4] = 0X00; + data[5] = 0X00; + data[6] = 0X00; + data[7] = 0X00; + CAN1_SendData(0x371, &data[0]); + } + if(CAN_SendCount ==7) //ID = 0x373 - 最大/最小单体电压/温度（与固德威配置相同） + { + cellVolMax = canMem[0].VolMax; + cellVolMin = canMem[0].VolMin; + T_Max = canMem[0].TempMax/10; // 最高温度 + T_Min = canMem[0].TempMin/10; // 最低温度 + + data[0] = cellVolMin & 0xFF; //最小单体电压 + data[1] = (cellVolMin >> 8) & 0xFF; + data[2] = cellVolMax & 0xFF; //最大单体电压 + data[3] = (cellVolMax >> 8) & 0xFF; + data[4] = (T_Min ) & 0xFF; //最小单体温度 + data[5] = ((T_Min ) >> 8) & 0xFF; + data[6] = (T_Max ) & 0xFF; //最大单体温度 + data[7] = ((T_Max ) >> 8) & 0xFF; + CAN1_SendData(0x373, &data[0]); + } + if(CAN_SendCount ==8) //ID = 0x374 - 最小电池电压地址 + { + if((canMem[0].VolMinIndex + 1) >= 10) + { + cellVolMinIndex_Byte1 = 1; + cellVolMinIndex_Byte2 = (canMem[0].VolMinIndex+1)-10; + } + else + { + cellVolMinIndex_Byte1 = 0; + cellVolMinIndex_Byte2 = (canMem[0].VolMinIndex+1); + } + + data[0] = 0x30 + cellVolMinIndex_Byte1; + data[1] = 0X30 + cellVolMinIndex_Byte2; + data[2] = 0X00; + data[3] = 0X00; + data[4] = 0X00; + data[5] = 0X00; + data[6] = 0X00; + data[7] = 0X00; + CAN1_SendData(0x374, &data[0]); + } + if(CAN_SendCount ==9) //ID = 0x375 - 最大电池电压地址 + { + if((canMem[0].VolMaxIndex+1)>= 10) + { + cellVolMaxIndex_Byte1 = 1; + cellVolMaxIndex_Byte2 = (canMem[0].VolMaxIndex+1)-10; + } + else + { + cellVolMaxIndex_Byte1 = 0; + cellVolMaxIndex_Byte2 = (canMem[0].VolMaxIndex+1); + } + + data[0] = 0x30 + cellVolMaxIndex_Byte1; + data[1] = 0x30 + cellVolMaxIndex_Byte2; + data[2] = 0X00; + data[3] = 0X00; + data[4] = 0X00; + data[5] = 0X00; + data[6] = 0X00; + data[7] = 0X00; + CAN1_SendData(0x375, &data[0]); + } + if(CAN_SendCount ==10) //ID = 0x376 - 最小电池温度地址 + { + T_MinIndex = canMem[0].TempMinIndex;// 最低温度序号，范围0-6 + + data[0] = 0x30 + (T_MinIndex+1); + data[1] = 0X00; + data[2] = 0X00; + data[3] = 0X00; + data[4] = 0X00; + data[5] = 0X00; + data[6] = 0X00; + data[7] = 0X00; + CAN1_SendData(0x376, &data[0]); + } + if(CAN_SendCount ==11) //ID = 0x377 - 最大电池温度地址 + { + T_MaxIndex = canMem[0].TempMaxIndex;// 最高温度序号，范围0-6 + + data[0] = 0x30 + (T_MaxIndex+1); + data[1] = 0X00; + data[2] = 0X00; + data[3] = 0X00; + data[4] = 0X00; + data[5] = 0X00; + data[6] = 0X00; + data[7] = 0X00; + CAN1_SendData(0x377, &data[0]); + } + if(CAN_SendCount ==12) //ID = 0x379 --- 容量 + { + totalCapacity = ncc_Ah * OnlineNum; //单位1Ah + + data[0] = totalCapacity & 0xFF; //电池容量 + data[1] = (totalCapacity >> 8) & 0xFF; + data[2] = 0X00; + data[3] = 0X00; + data[4] = 0X00; + data[5] = 0X00; + data[6] = 0X00; + data[7] = 0X00; + CAN1_SendData(0x379, &data[0]); + } + + if(CAN_SendCount>=13) + { + CAN_SendCount = 0; + } +} + +//Sorotec 索瑞德 +void CAN_Protocol_Sorotec(void) +{ + uint8_t data[8]; + uint16_t totalCapacity; + + int16_t tempVol; + int16_t tempCur; + + uint16_t chgVolLimit; + uint16_t dsgVolLimit; + int16_t chgCurLimit; + int16_t dsgCurLimit; + + uint8_t protectByte1 = 0; + uint8_t protectByte2 = 0; + uint8_t protectByte3 = 0; + uint8_t protectByte4 = 0; + + uint8_t alarmByte1 = 0; + uint8_t alarmByte2 = 0; + uint8_t alarmByte3 = 0; + uint8_t alarmByte4 = 0; + + + int16_t T_Average; // 平均温度 + + + //Data0 BIT0.1 General[Cancel] //0000 0010 + protectByte1 |= 0x01; + + //保护 + //放电高温保护 + //over temp at discharging + if(((canMem[0].status_byte2 & 0x0008) != 0) || ((canMem[0].status_byte4 & 0x0202) != 0)) + { + protectByte1 &= 0x7f; + protectByte1 |= 0x40; + } + else + { + protectByte1 &= 0xbf; + protectByte1 |= 0x80; + } + + //欠压保护 + //cell_uv+pack_uv+l0v + if(((canMem[0].status_byte1 & 0x0202) != 0) || ((canMem[0].status_byte3 & 0x0008) != 0)) + { + protectByte1 &= 0xdf; + protectByte1 |= 0x10; + } + else + { + protectByte1 &= 0xef; + protectByte1 |= 0x20; + } + +// //过压保护 +// //cell_ov+pack_ov+pf +// if((canMem[0].status_byte1 & 0x0141) != 0) +// { +// if(canMem[0].soc < 99) +// { +// protectByte1 &= 0xf7; //去掉leave +// protectByte1 |= 0x04; //赋值arrive +// } +// else +// { +// protectByte1 &= 0xfb; +// protectByte1 |= 0x08; +// } +// } +// else +// { +// protectByte1 &= 0xfb; +// protectByte1 |= 0x08; +// } + + //放电过流保护 + //discharge over current，SC, OCD1, OCD2 + if( ((canMem[0].status_byte1 & 0x042c) != 0) || ((canMem[0].status_byte2 & 0x0010) != 0) || ((canMem[0].status_byte4 & 0x0020) != 0)) + { + protectByte2 &= 0x7f; + protectByte2 |= 0x40; + } + else + { + protectByte2 &= 0xbf; + protectByte2 |= 0x80; + } + + //充电低温保护 + //Data1 BIT4.5 under temp at charging //0001 0000 + if( ((canMem[0].status_byte2 & 0x0001) != 0) || ((canMem[0].status_byte4 & 0x0404) != 0) ) + { + protectByte2 &= 0xdf; + protectByte2 |= 0x10; + } + else + { + protectByte2 &= 0xef; + protectByte2 |= 0x20; + } + + //充电高温保护 + //Data1 BIT2.3 over temp at charging //0000 0100 + if( ((canMem[0].status_byte2 & 0x0002) != 0) || ((canMem[0].status_byte4 & 0x0101) != 0) ) + { + protectByte2 &= 0xf7; + protectByte2 |= 0x04; + } + else + { + protectByte2 &= 0xfb; + protectByte2 |= 0x08; + } + + //放电低温保护 + //Data1 BIT0.1 under temp at discharging //0000 0001 + if( ((canMem[0].status_byte2 & 0x0004) != 0) || ((canMem[0].status_byte4 & 0x0808) != 0) ) + { + protectByte2 &= 0xfd; + protectByte2 |= 0x01; + } + else + { + protectByte2 &= 0xfe; + protectByte2 |= 0x02; + } + + //短路 + //Data2 BIT4.5 short circuit //0001 0000 + if((canMem[0].status_byte1 & 0x20) != 0) + { + protectByte3 &= 0xdf; + protectByte3 |= 0x10; + } + else + { + protectByte3 &= 0xef; + protectByte3 |= 0x20; + } + + //充电过流保护 + //charge over current + if( ((canMem[0].status_byte1 & 0x0010) != 0) || ((canMem[0].status_byte4 & 0x0010) != 0)) + { + protectByte3 &= 0xfd; + protectByte3 |= 0x01; + } + else + { + protectByte3 &= 0xfe; + protectByte3 |= 0x02; + } + //Data2 BIT2.3 Contactor[Cancel] //0000 1000 + protectByte3 |= 0x08; + //Data2 BIT6.7 BMS internal[Cancel] //1000 0000 + protectByte3 |= 0x80; +// //Data3 BIT0.1 cell imbanlance //0000 0001 +// if((bmsMem.balanceStatus & 0x01) !=0) //0x01表示平衡 +// { +// protectByte4 &= 0xfe; +// protectByte4 |= 0x02; +// } +// else +// { +// protectByte4 &= 0xfd; +// protectByte4 |= 0x01; +// } + + + //告警 + //放电高温告警 + //over temp at discharging + if(((canMem[0].status_byte2 & 0x2200) != 0) || ((canMem[0].status_byte4 & 0x2000) != 0)) + { + alarmByte1 &= 0x7f; + alarmByte1 |= 0x40; + } + else + { + alarmByte1 &= 0xbf; + alarmByte1 |= 0x80; + } + + //欠压告警 + if((canMem[0].status_byte3 & 0x0A00) != 0) + { + alarmByte1 &= 0xdf; + alarmByte1 |= 0x10; + } + else + { + alarmByte1 &= 0xef; + alarmByte1 |= 0x20; + } + +// //过压告警 +// if((canMem[0].status_byte3 & 0x0500) != 0) +// { +// if(canMem[0].soc < 99) +// { +// alarmByte1 &= 0xf7; //去掉leave +// alarmByte1 |= 0x04; //赋值arrive +// } +// else +// { +// alarmByte1 &= 0xfb; +// alarmByte1 |= 0x08; +// } +// } +// else +// { +// alarmByte1 &= 0xfb; +// alarmByte1 |= 0x08; +// } + + //放电过流告警 + if((canMem[0].status_byte3 & 0x2000) != 0) + { + alarmByte2 &= 0x7f; + alarmByte2 |= 0x40; + } + else + { + alarmByte2 &= 0xbf; + alarmByte2 |= 0x80; + } + + //充电低温告警 + //Data1 BIT4.5 under temp at charging //0001 0000 + if( ((canMem[0].status_byte2 & 0x4400) != 0) || ((canMem[0].status_byte4 & 0x4000) != 0) ) + { + alarmByte2 &= 0xdf; + alarmByte2 |= 0x10; + } + else + { + alarmByte2 &= 0xef; + alarmByte2 |= 0x20; + } + + //充电高温告警 + //Data1 BIT2.3 over temp at charging //0000 0100 + if( ((canMem[0].status_byte2 & 0x1100) != 0) || ((canMem[0].status_byte4 & 0x1000) != 0) ) + { + alarmByte2 &= 0xf7; + alarmByte2 |= 0x04; + } + else + { + alarmByte2 &= 0xfb; + alarmByte2 |= 0x08; + } + + //放电低温告警 + //Data1 BIT0.1 under temp at discharging //0000 0001 + if( ((canMem[0].status_byte2 & 0x8800) != 0) || ((canMem[0].status_byte4 & 0x8000) != 0) ) + { + alarmByte2 &= 0xfd; + alarmByte2 |= 0x01; + } + else + { + alarmByte2 &= 0xfe; + alarmByte2 |= 0x02; + } + + //短路 + //Data2 BIT4.5 short circuit //0001 0000 + if((canMem[0].status_byte1 & 0x20) != 0) + { + alarmByte3 &= 0xdf; + alarmByte3 |= 0x10; + } + else + { + alarmByte3 &= 0xef; + alarmByte3 |= 0x20; + } + + //充电过流告警 + if((canMem[0].status_byte3 & 0x1000) != 0) + { + alarmByte3 &= 0xfd; + alarmByte3 |= 0x01; + } + else + { + alarmByte3 &= 0xfe; + alarmByte3 |= 0x02; + } + +// if((bmsMem.balanceStatus & 0x01) !=0) //0x01表示平衡 +// { +// alarmByte4 &= 0xfe; +// alarmByte4 |= 0x02; +// } +// else +// { +// alarmByte4 &= 0xfd; +// alarmByte4 |= 0x01; +// } + + + if(CAN_SendCount ==0) //ID=0x35a - Alarms/Warnings + { + data[0] = protectByte1; + data[1] = protectByte2; + data[2] = protectByte3; + data[3] = protectByte4; + data[4] = alarmByte1; //报警和保护信号相同 + data[5] = alarmByte2; + data[6] = alarmByte3; + data[7] = alarmByte4; + CAN1_SendData(0x35a, &data[0]); + } + if(CAN_SendCount ==1) //ID = 0x351 - 电池充电/放电电压，充电/放电限流 + { + //充放电电流限制需要有符号区别吗？ + chgVolLimit = bmsMem.inverter_chgVolLimit; //充电电压限制，上位机配置，默认值57.6V + dsgVolLimit = bmsMem.inverter_dsgVolLimit; //放电电压限制，上位机配置，默认值41.6V + + if(chg_forbidFlg == 1) + { + chgCurLimit = 0; //Sorotec禁充 + } + else if(chg_curlimitFlg == 1) + { + chgCurLimit = Inv_curlimit * (OnlineNum-chg_cur0Num); //限流40A*未保护个数 + } + else + { + chgCurLimit = bmsMem.inverter_chgCurLimit * (OnlineNum-chg_curLimitNum); //充电电流限制，上位机配置，默认值100A + } + if(dsg_forbidFlg == 1) + { + dsgCurLimit = 0; //Sorotec禁放 + } + else + { + dsgCurLimit = bmsMem.inverter_dsgCurLimit * (OnlineNum-dsg_curLimitNum); //放电电流限制，上位机配置，默认值100A + } + + data[0] = chgVolLimit & 0xFF; //充电电压限制低位 + data[1] = (chgVolLimit >> 8) & 0xFF; + data[2] = chgCurLimit & 0xFF; //充电电流限制低位 + data[3] = (chgCurLimit >> 8) & 0xFF; + data[4] = dsgCurLimit & 0xFF; //放电电流限制低位 + data[5] = (dsgCurLimit >> 8) & 0xFF; + data[6] = dsgVolLimit & 0xFF; //放电电压限制低位 + data[7] = (dsgVolLimit >> 8) & 0xFF; + CAN1_SendData(0x351, &data[0]); + } + if(CAN_SendCount ==2) //ID = 0x355 - 电量SOC + { + data[0] = canMem[0].soc & 0xFF; //SOC + data[1] = 0; + data[2] = 0X00; + data[3] = 0X00; + data[4] = 0X00; + data[5] = 0x00; + data[6] = 0x00; + data[7] = 0X00; + CAN1_SendData(0x355, &data[0]); + } + if(CAN_SendCount ==3) //ID = 0x356 - 电池电压/电流/温度 + { + tempVol = (uint16_t)(bmsMem.packVoltage/10); //单位0.01 + tempCur = (int16_t)(canMem[0].cur/10); //单位0.1 + T_Average = canMem[0].temp;// 平均温度 + + data[0] = tempVol & 0xFF; + data[1] = (tempVol >>8) & 0xFF; //电池包电压 + data[2] = tempCur & 0xFF; + data[3] = (tempCur >>8) & 0xFF; //电池包电流 + data[4] = (T_Average -2731) & 0xFF;; + data[5] = ((T_Average -2731) >>8) & 0xFF; //温度-暂时取平均温度，具体哪一路需要客户确认 + data[6] = 0x00; + data[7] = 0X00; + CAN1_SendData(0x356, &data[0]); + } + if(CAN_SendCount ==4) //ID = 0x35e - 制造商名称-ASCII + { + data[0] = 'B'; + data[1] = 'T'; + data[2] = 'Y'; + data[3] = 'G'; + data[4] = '-'; + data[5] = 'B'; + data[6] = 'M'; + data[7] = 'S'; + CAN1_SendData(0x35e, &data[0]); + } + if(CAN_SendCount ==5) //ID = 0x35f - BMS版本号/总容量 + { + totalCapacity = ncc_Ah * OnlineNum; //单位1Ah + + data[0] = 0X00; + data[1] = 0X00; + data[2] = 0X00; //版本号暂无 + data[3] = 0X00; + data[4] = totalCapacity & 0xFF; //电池容量 + data[5] = (totalCapacity >> 8) & 0xFF; + data[6] = 0X00; + data[7] = 0X00; + CAN1_SendData(0x35f, &data[0]); + } + + if(CAN_SendCount>=6) + { + CAN_SendCount = 0; + } +} + +//Modbus: +//Growatt 古瑞瓦特 +void MOD_Protocol_Growatt(void) +{ + uint8_t i; + + uint16_t protectByte = 0; + uint16_t alarmByte = 0; + uint16_t statusByte = 0; + + + //保护 +// //过压保护 +// //cell_ov+pack_ov+pf +// if((canMem[0].status_byte1 & 0x0141) != 0) +// { +// if(canMem[0].soc < 99) +// { +// protectByte |= 0x0004; +// } +// else +// { +// protectByte &= 0xFFFB; +// } +// } +// else +// { +// protectByte &= 0xFFFB; +// } + + //欠压保护 + //cell_uv+pack_uv+l0v + if(((canMem[0].status_byte1 & 0x0202) != 0) || ((canMem[0].status_byte3 & 0x0008) != 0)) + { + protectByte |= 0x0008; + } + else + { + protectByte &= 0xFFF7; + } + + //放电过流保护 + //discharge over current，SC, OCD1, OCD2 + if( ((canMem[0].status_byte1 & 0x042c) != 0) || ((canMem[0].status_byte2 & 0x0010) != 0) || ((canMem[0].status_byte4 & 0x0020) != 0)) + { + protectByte |= 0x0001; + } + else + { + protectByte &= 0xFFFE; + } + + //充电过流保护 + //charge over current + if( ((canMem[0].status_byte1 & 0x0010) != 0) || ((canMem[0].status_byte4 & 0x0010) != 0)) + { + protectByte |= 0x0800; + } + else + { + protectByte &= 0xF7FF; + } + + //sc-short circuit (测) 短路 + if((canMem[0].status_byte1 & 0x20) != 0) + { + protectByte |= 0x0002; + } + else + { + protectByte &= 0xFFFD; + } + + //放电高温保护 + //discharge over temp + if( ((canMem[0].status_byte2 & 0x0008) !=0) || ((canMem[0].status_byte4 & 0x0202) !=0) ) + { + protectByte |= 0x0010; + } + else + { + protectByte &= 0xFFEF; + } + + //充电高温保护 + //charge over temp 高温 + if( ((canMem[0].status_byte2 & 0x0002) !=0) || ((canMem[0].status_byte4 & 0x0101) !=0) ) + { + protectByte |= 0x0020; + } + else + { + protectByte &= 0xFFDF; + } + + //放电低温保护 + //discharge under temp + if( ((canMem[0].status_byte2 & 0x0004) !=0) || ((canMem[0].status_byte4 & 0x0808) !=0) ) + { + protectByte |= 0x0040; + } + else + { + protectByte &= 0xFFBF; + } + + //充电低温保护 + //charge under temp 低温 + if( ((canMem[0].status_byte2 & 0x0001) !=0) || ((canMem[0].status_byte4 & 0x0404) !=0) ) + { + protectByte |= 0x0080; + + } + else + { + protectByte &= 0xFF7F; + + } + + //环境低温保护 0x4000 + if((canMem[0].status_byte4 & 0x0C00) !=0) //环境充放电低温 + { + protectByte |= 0x4000; + } + else + { + protectByte &= 0xBFFF; + } + + //环境高温保护 0x2000 + if((canMem[0].status_byte4 & 0x0300) !=0) //环境充放电高温 + { + protectByte |= 0x2000; + } + else + { + protectByte &= 0xDFFF; + } + + //MOS高温保护 0x1000 + if((canMem[0].status_byte2 & 0x0300) !=0) //MOS充放电高温 + { + protectByte |= 0x1000; + } + else + { + protectByte &= 0xEFFF; + } + + + //告警 +// //单体过压告警 +// //cell_ov+pack_ov+pf +// if((canMem[0].status_byte3 & 0x0100) != 0) +// { +// if(canMem[0].soc < 99) +// { +// alarmByte |= 0x0001; +// } +// else +// { +// alarmByte &= 0xFFFE; +// } +// } +// else +// { +// alarmByte &= 0xFFFE; +// } + + //单体欠压告警 + //cell_uv+pack_uv+l0v + if((canMem[0].status_byte3 & 0x0200) != 0) + { + alarmByte |= 0x0002; + } + else + { + alarmByte &= 0xFFFD; + } + +// //总体过压告警 +// if((canMem[0].status_byte3 & 0x0400) != 0) +// { +// alarmByte |= 0x0004; +// } +// else +// { +// alarmByte &= 0xFFFB; +// } + + //总体欠压告警 + if((canMem[0].status_byte3 & 0x0800) != 0) + { + alarmByte |= 0x0008; + } + else + { + alarmByte &= 0xFFF7; + } + + //放电过流告警 + //discharge over current，SC, OCD1, OCD2 + if((canMem[0].status_byte3 & 0x0200) != 0) + { + alarmByte |= 0x0010; + } + else + { + alarmByte &= 0xFFEF; + } + + //充电过流告警 + //charge over current + if((canMem[0].status_byte3 & 0x1000) != 0) + { + alarmByte |= 0x0020; + } + else + { + alarmByte &= 0xFFDF; + } + + //放电高温告警 + //discharge over temp + if( ((canMem[0].status_byte2 & 0x2200) !=0) || ((canMem[0].status_byte4 & 0x2000) !=0) ) + { + alarmByte |= 0x0040; + } + else + { + alarmByte &= 0xFFBF; + } + + //充电高温告警 + //charge over temp 高温 + if( ((canMem[0].status_byte2 & 0x1100) !=0) || ((canMem[0].status_byte4 & 0x1000) !=0) ) + { + alarmByte |= 0x0100; + } + else + { + alarmByte &= 0xFEFF; + + } + + //放电低温告警 + //discharge under temp + if( ((canMem[0].status_byte2 & 0x8800) !=0) || ((canMem[0].status_byte4 & 0x8000) !=0) ) + { + alarmByte |= 0x0080; + } + else + { + alarmByte &= 0xFF7F; + } + + //充电低温告警 + //charge under temp 低温 + if( ((canMem[0].status_byte2 & 0x4400) !=0) || ((canMem[0].status_byte4 & 0x4000) !=0) ) + { + alarmByte |= 0x0200; + } + else + { + alarmByte &= 0xFDFF; + } + + //环境低温告警 0x4000 + if((canMem[0].status_byte4 & 0xC000) !=0) //环境充放电低温 + { + alarmByte |= 0x4000; + } + else + { + alarmByte &= 0xBFFF; + } + + //环境高温告警 0x2000 + if((canMem[0].status_byte4 & 0x3000) !=0) //环境充放电高温 + { + alarmByte |= 0x2000; + } + else + { + alarmByte &= 0xDFFF; + } + + //MOS高温告警 0x1000 + if((canMem[0].status_byte2 & 0x3000) !=0) //MOS充放电高温 + { + alarmByte |= 0x1000; + } + else + { + alarmByte &= 0xEFFF; + } + + + //状态位赋值： + if(bmsMem.E2_485Snum != 1) //0100并机/0000单机模式 + { + statusByte |= 0x0100; + } + else + { + statusByte &= 0xFEFF; + } + if(bCHGING == 1) //充电 + { + statusByte |= 0x0002; + } + else + { + statusByte &= 0xFFFD; + } + if(bDSGING == 1) //放电 + { + statusByte |= 0x0003; + } + else + { + statusByte &= 0xFFFC; + } +// if((bmsMem.balanceStatus & 0x01) !=0) //均衡状态 +// { +// statusByte |= 0x0008; +// } +// else +// { +// statusByte &= 0xFFF7; +// } + if( ((canMem[0].status_byte3 & 0x02) !=0) ) //充电MOS状态 0x0013 Bit6 + { + statusByte |= 0x0040; + } + else + { + statusByte &= 0xFFBF; + } + if( ((canMem[0].status_byte3 & 0x01) !=0) ) //放电MOS状态 0x0013 Bit5 + { + statusByte |= 0x0020; + } + else + { + statusByte &= 0xFFDF; + } + + if(chg_forceFlg == 1)//Growatt + { + statusByte |= 0x1000; //bit12 强充标志 + } + else + { + statusByte &= 0xEFFF; + } + + GrowattMem.status_byte = statusByte; //状态 + GrowattMem.protect_byte = protectByte; //保护 + GrowattMem.alarm_byte = alarmByte; //报警 + + + GrowattMem.soc = (uint8_t)canMem[0].soc; //SOC % 2byte + GrowattMem.soh = (uint8_t)canMem[0].soh; //SOH % 2byte + + GrowattMem.packVoltage = (uint16_t)(bmsMem.packVoltage/10); //模块电压 10mV 2byte + GrowattMem.packCurrent = (int16_t)(canMem[0].cur); //充电电流 10mA 2byte + + GrowattMem.T_Average = (int16_t)((canMem[0].temp - 2731)/10); //电芯温度 ℃ + GrowattMem.rcc = 100 * ncc_Ah * OnlineNum * GrowattMem.soc/100; //剩余容量 10mAH 2byte + GrowattMem.fcc = 100 * ncc_Ah * OnlineNum; //满容量 10mAH 2byte + + GrowattMem.CV_Vol = bmsMem.inverter_chgVolLimit * 10; //CV电压&充电限压，上位机配置，默认值57.6V，10mV + if(chg_forbidFlg == 1) + { + GrowattMem.chgCurLimit = 0; //Growatt_485禁充 + } + else if(chg_curlimitFlg == 1) + { + GrowattMem.chgCurLimit = Inv_curlimit * (OnlineNum-chg_cur0Num); //限流40A*未保护个数 + } + else + { + GrowattMem.chgCurLimit = bmsMem.inverter_chgCurLimit * (OnlineNum-chg_curLimitNum); //充电电流限制，上位机配置，默认值100A + } + if(dsg_forbidFlg == 1) + { + GrowattMem.dsgCurLimit = 0; //Growatt_485禁放 + } + else + { + GrowattMem.dsgCurLimit = bmsMem.inverter_dsgCurLimit * (OnlineNum-dsg_curLimitNum); //放电电流限制，上位机配置，默认值100A，10mA + } + + GrowattMem.Delta = canMem[0].VolMax - canMem[0].VolMin;//压差 V + GrowattMem.cellVolMax = canMem[0].VolMax ; //单芯最高电压 + GrowattMem.cellVolMin = canMem[0].VolMin ; //单芯最低电压 + GrowattMem.cellVolMaxIndex = canMem[0].VolMaxIndex + 1; //最大电压序号 + GrowattMem.cellVolMinIndex = canMem[0].VolMinIndex + 1; //最小电压序号 + GrowattMem.cellNum = bmsMem.ucCellNum * OnlineNum; + + for(i=0;i<16;i++) + { + GrowattMem.cellVol[i] = bmsMem.vCell[i]; //电池电压 mV + } +} + +//Sorotec 索瑞德 +void MOD_Protocol_Sorotec(void) +{ + MOD_Protocol_Growatt(); +} + +//YDN: +//Pylon 派能(电总协议) +void YDN_Protocol_Pylon(void) +{ + YDN(); +} + diff --git a/PROTOCOL/ProtocolSwitch_P2.c b/PROTOCOL/ProtocolSwitch_P2.c new file mode 100644 index 0000000..a7bd9c7 --- /dev/null +++ b/PROTOCOL/ProtocolSwitch_P2.c @@ -0,0 +1,2940 @@ +/** + ****************************************************************************** + * @file InverterSwitch_Page2.c + * @author - + * @version - + * @date 2026.3.26 + * @brief - + ****************************************************************************** + * @attention + * + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" +#include "global.h" + + +//这里放的是基本款的第2页函数，不根据发货要求变动 +//CAN: +//13.SMA 14.Sunways 15.Luxpower 16.Schneider +//17.AlpSolarr +//Modbus: +//18.SRNE 19.Voltronic 20.COSUPER +//21.SMK 22.SAKO 23.SNADI 24.invt + + +//SMA 艾思玛 +void CAN_Protocol_SMA(void) +{ + uint8_t data[8]; + uint16_t totalCapacity; + + int16_t tempVol; + int16_t tempCur; + + uint16_t chgVolLimit; + uint16_t dsgVolLimit; + int16_t chgCurLimit; + int16_t dsgCurLimit; + + uint8_t protectByte1 = 0; + uint8_t protectByte2 = 0; + uint8_t protectByte3 = 0; + uint8_t protectByte4 = 0; + + uint8_t alarmByte1 = 0; + uint8_t alarmByte2 = 0; + uint8_t alarmByte3 = 0; + uint8_t alarmByte4 = 0; + + + int16_t T_Average; // 平均温度 + + + //Data0 BIT0.1 General[Cancel] //0000 0010 + protectByte1 |= 0x02; + + //保护 + //放电高温保护 + //over temp at discharging + if(((canMem[0].status_byte2 & 0x0008) != 0) || ((canMem[0].status_byte4 & 0x0202) != 0)) + { + protectByte1 &= 0x7f; + protectByte1 |= 0x40; + } + else + { + protectByte1 &= 0xbf; + protectByte1 |= 0x80; + } + + //欠压保护 + //cell_uv+pack_uv+l0v + if(((canMem[0].status_byte1 & 0x0202) != 0) || ((canMem[0].status_byte3 & 0x0008) != 0)) + { + protectByte1 &= 0xdf; + protectByte1 |= 0x10; + } + else + { + protectByte1 &= 0xef; + protectByte1 |= 0x20; + } + +// //过压保护 +// //cell_ov+pack_ov+pf +// if((canMem[0].status_byte1 & 0x0141) != 0) +// { +// if(canMem[0].soc < 99) +// { +// protectByte1 &= 0xf7; //去掉leave +// protectByte1 |= 0x04; //赋值arrive +// } +// else +// { +// protectByte1 &= 0xfb; +// protectByte1 |= 0x08; +// } +// } +// else +// { +// protectByte1 &= 0xfb; +// protectByte1 |= 0x08; +// } + + //放电过流保护 + //discharge over current，SC, OCD1, OCD2 + if( ((canMem[0].status_byte1 & 0x042c) != 0) || ((canMem[0].status_byte2 & 0x0010) != 0) || ((canMem[0].status_byte4 & 0x0020) != 0)) + { + protectByte2 &= 0x7f; + protectByte2 |= 0x40; + } + else + { + protectByte2 &= 0xbf; + protectByte2 |= 0x80; + } + + //充电低温保护 + //Data1 BIT4.5 under temp at charging //0001 0000 + if( ((canMem[0].status_byte2 & 0x0001) != 0) || ((canMem[0].status_byte4 & 0x0404) != 0) ) + { + protectByte2 &= 0xdf; + protectByte2 |= 0x10; + } + else + { + protectByte2 &= 0xef; + protectByte2 |= 0x20; + } + + //充电高温保护 + //Data1 BIT2.3 over temp at charging //0000 0100 + if( ((canMem[0].status_byte2 & 0x0002) != 0) || ((canMem[0].status_byte4 & 0x0101) != 0) ) + { + protectByte2 &= 0xf7; + protectByte2 |= 0x04; + } + else + { + protectByte2 &= 0xfb; + protectByte2 |= 0x08; + } + + //放电低温保护 + //Data1 BIT0.1 under temp at discharging //0000 0001 + if( ((canMem[0].status_byte2 & 0x0004) != 0) || ((canMem[0].status_byte4 & 0x0808) != 0) ) + { + protectByte2 &= 0xfd; + protectByte2 |= 0x01; + } + else + { + protectByte2 &= 0xfe; + protectByte2 |= 0x02; + } + + //短路 + //Data2 BIT4.5 short circuit //0001 0000 + if((canMem[0].status_byte1 & 0x20) != 0) + { + protectByte3 &= 0xdf; + protectByte3 |= 0x10; + } + else + { + protectByte3 &= 0xef; + protectByte3 |= 0x20; + } + + //充电过流保护 + //charge over current + if( ((canMem[0].status_byte1 & 0x0010) != 0) || ((canMem[0].status_byte4 & 0x0010) != 0)) + { + protectByte3 &= 0xfd; + protectByte3 |= 0x01; + } + else + { + protectByte3 &= 0xfe; + protectByte3 |= 0x02; + } + //Data2 BIT2.3 Contactor[Cancel] //0000 1000 + protectByte3 |= 0x08; + //Data2 BIT6.7 BMS internal[Cancel] //1000 0000 + protectByte3 |= 0x80; +// //Data3 BIT0.1 cell imbanlance //0000 0001 +// if((bmsMem.balanceStatus & 0x01) !=0) //0x01表示平衡 +// { +// protectByte4 &= 0xfe; +// protectByte4 |= 0x02; +// } +// else +// { +// protectByte4 &= 0xfd; +// protectByte4 |= 0x01; +// } + + + //告警 + //放电高温告警 + //over temp at discharging + if(((canMem[0].status_byte2 & 0x2200) != 0) || ((canMem[0].status_byte4 & 0x2000) != 0)) + { + alarmByte1 &= 0x7f; + alarmByte1 |= 0x40; + } + else + { + alarmByte1 &= 0xbf; + alarmByte1 |= 0x80; + } + + //欠压告警 + if((canMem[0].status_byte3 & 0x0A00) != 0) + { + alarmByte1 &= 0xdf; + alarmByte1 |= 0x10; + } + else + { + alarmByte1 &= 0xef; + alarmByte1 |= 0x20; + } + +// //过压告警 +// if((canMem[0].status_byte3 & 0x0500) != 0) +// { +// if(canMem[0].soc < 99) +// { +// alarmByte1 &= 0xf7; //去掉leave +// alarmByte1 |= 0x04; //赋值arrive +// } +// else +// { +// alarmByte1 &= 0xfb; +// alarmByte1 |= 0x08; +// } +// } +// else +// { +// alarmByte1 &= 0xfb; +// alarmByte1 |= 0x08; +// } + + //放电过流告警 + if((canMem[0].status_byte3 & 0x2000) != 0) + { + alarmByte2 &= 0x7f; + alarmByte2 |= 0x40; + } + else + { + alarmByte2 &= 0xbf; + alarmByte2 |= 0x80; + } + + //充电低温告警 + //Data1 BIT4.5 under temp at charging //0001 0000 + if( ((canMem[0].status_byte2 & 0x4400) != 0) || ((canMem[0].status_byte4 & 0x4000) != 0) ) + { + alarmByte2 &= 0xdf; + alarmByte2 |= 0x10; + } + else + { + alarmByte2 &= 0xef; + alarmByte2 |= 0x20; + } + + //充电高温告警 + //Data1 BIT2.3 over temp at charging //0000 0100 + if( ((canMem[0].status_byte2 & 0x1100) != 0) || ((canMem[0].status_byte4 & 0x1000) != 0) ) + { + alarmByte2 &= 0xf7; + alarmByte2 |= 0x04; + } + else + { + alarmByte2 &= 0xfb; + alarmByte2 |= 0x08; + } + + //放电低温告警 + //Data1 BIT0.1 under temp at discharging //0000 0001 + if( ((canMem[0].status_byte2 & 0x8800) != 0) || ((canMem[0].status_byte4 & 0x8000) != 0) ) + { + alarmByte2 &= 0xfd; + alarmByte2 |= 0x01; + } + else + { + alarmByte2 &= 0xfe; + alarmByte2 |= 0x02; + } + + //短路 + //Data2 BIT4.5 short circuit //0001 0000 + if((canMem[0].status_byte1 & 0x20) != 0) + { + alarmByte3 &= 0xdf; + alarmByte3 |= 0x10; + } + else + { + alarmByte3 &= 0xef; + alarmByte3 |= 0x20; + } + + //充电过流告警 + if((canMem[0].status_byte3 & 0x1000) != 0) + { + alarmByte3 &= 0xfd; + alarmByte3 |= 0x01; + } + else + { + alarmByte3 &= 0xfe; + alarmByte3 |= 0x02; + } + +// if((bmsMem.balanceStatus & 0x01) !=0) //0x01表示平衡 +// { +// alarmByte4 &= 0xfe; +// alarmByte4 |= 0x02; +// } +// else +// { +// alarmByte4 &= 0xfd; +// alarmByte4 |= 0x01; +// } + + + if(CAN_SendCount ==0) //ID=0x35a - Alarms/Warnings + { + data[0] = protectByte1; + data[1] = protectByte2; + data[2] = protectByte3; + data[3] = protectByte4; + data[4] = alarmByte1; //报警和保护信号相同 + data[5] = alarmByte2; + data[6] = alarmByte3; + data[7] = alarmByte4; + CAN1_SendData(0x35a, &data[0]); + } + if(CAN_SendCount ==1) //ID = 0x351 - 电池充电/放电电压，充电/放电限流 + { + //充放电电流限制需要有符号区别吗？ + chgVolLimit = bmsMem.inverter_chgVolLimit; //充电电压限制，上位机配置，默认值57.6V + dsgVolLimit = bmsMem.inverter_dsgVolLimit; //放电电压限制，上位机配置，默认值41.6V + + if(chg_forbidFlg == 1) + { + chgCurLimit = 0; //SMA禁充 + } + else if(chg_curlimitFlg == 1) + { + chgCurLimit = Inv_curlimit * (OnlineNum-chg_cur0Num); //限流40A*未保护个数 + } + else + { + chgCurLimit = bmsMem.inverter_chgCurLimit * (OnlineNum-chg_curLimitNum); //充电电流限制，上位机配置，默认值100A + } + if(dsg_forbidFlg == 1) + { + dsgCurLimit = 0; //SMA禁放 + } + else + { + dsgCurLimit = bmsMem.inverter_dsgCurLimit * (OnlineNum-dsg_curLimitNum); //放电电流限制，上位机配置，默认值100A + } + + data[0] = chgVolLimit & 0xFF; //充电电压限制低位 + data[1] = (chgVolLimit >> 8) & 0xFF; + data[2] = chgCurLimit & 0xFF; //充电电流限制低位 + data[3] = (chgCurLimit >> 8) & 0xFF; + data[4] = dsgCurLimit & 0xFF; //放电电流限制低位 + data[5] = (dsgCurLimit >> 8) & 0xFF; + data[6] = dsgVolLimit & 0xFF; //放电电压限制低位 + data[7] = (dsgVolLimit >> 8) & 0xFF; + CAN1_SendData(0x351, &data[0]); + } + if(CAN_SendCount ==2) //ID = 0x355 - 电量SOC/SOH + { + data[0] = canMem[0].soc & 0xFF; //SOC + data[1] = 0; + data[2] = canMem[0].soh & 0xFF; //SOH + data[3] = 0; + data[4] = 0X00; + data[5] = 0x00; + data[6] = 0x00; + data[7] = 0X00; + CAN1_SendData(0x355, &data[0]); + } + if(CAN_SendCount ==3) //ID = 0x356 - 电池电压/电流/温度 + { + tempVol = (uint16_t)(bmsMem.packVoltage/10); //单位0.01 + tempCur = (int16_t)(canMem[0].cur/10); //单位0.1 + T_Average = canMem[0].temp;// 平均温度 + + data[0] = tempVol & 0xFF; + data[1] = (tempVol >>8) & 0xFF; //电池包电压 + data[2] = tempCur & 0xFF; + data[3] = (tempCur >>8) & 0xFF; //电池包电流 + data[4] = (T_Average -2731) & 0xFF;; + data[5] = ((T_Average -2731) >>8) & 0xFF; //温度-暂时取平均温度，具体哪一路需要客户确认 + data[6] = 0x00; + data[7] = 0X00; + CAN1_SendData(0x356, &data[0]); + } + if(CAN_SendCount ==4) //ID = 0x35e - 制造商名称-ASCII + { + data[0] = 'B'; + data[1] = 'T'; + data[2] = 'Y'; + data[3] = 'G'; + data[4] = '-'; + data[5] = 'B'; + data[6] = 'M'; + data[7] = 'S'; + CAN1_SendData(0x35e, &data[0]); + } + if(CAN_SendCount ==5) //ID = 0x35f - 电池类型，BMS版本，电池容量，保留的制造商ID + { + totalCapacity = ncc_Ah * OnlineNum; //单位1Ah + + data[0] = 0X00; + data[1] = 0X00; + data[2] = 0X00; //版本号暂无 + data[3] = 0X00; + data[4] = totalCapacity & 0xFF; //电池容量 + data[5] = (totalCapacity >> 8) & 0xFF; + data[6] = 0X00; + data[7] = 0X00; + CAN1_SendData(0x35f, &data[0]); + } + + if(CAN_SendCount>=6) + { + CAN_SendCount = 0; + } +} + +//Sunways 尚唯斯 +void CAN_Protocol_Sunways(void) +{ + uint8_t data[8]; + uint16_t totalCapacity; + + uint16_t tempVol; + int16_t tempCur; + + uint16_t chgVolLimit; + uint16_t dsgVolLimit; + int16_t chgCurLimit = bmsMem.inverter_chgCurLimit; + int16_t dsgCurLimit = bmsMem.inverter_dsgCurLimit; + + uint8_t protectByte1 = 0; + uint8_t protectByte2 = 0; + + int16_t T_Average; // 平均温度 + + uint8_t alarmByte1 = 0; + uint8_t alarmByte2 = 0; + + uint8_t alarmByte3 = 0; //0x399传输告警位 + uint8_t status = 0; //0x399传输状态位 + uint8_t protectByte3 = 0; //0x399传输故障位 + + + //保护 + //放电过流保护 + //discharge over current，SC, OCD1, OCD2 + if( ((canMem[0].status_byte1 & 0x042c) != 0) || ((canMem[0].status_byte2 & 0x0010) != 0) || ((canMem[0].status_byte4 & 0x0020) != 0)) + { + protectByte1 |= 0x80; + } + else + { + protectByte1 &= 0x7f; + } + + //低温保护 + //under temp at charging or discharging + if(((canMem[0].status_byte2 & 0x0005) != 0) || ((canMem[0].status_byte4 & 0x0C0C) != 0)) + { + protectByte1 |= 0x10; + } + else + { + protectByte1 &= 0xef; + } + + //过温保护 + //over temp at charging or discharging + if(((canMem[0].status_byte2 & 0x000A) != 0) || ((canMem[0].status_byte4 & 0x0303) != 0)) + { + protectByte1 |= 0x08; + } + else + { + protectByte1 &= 0xf7; + } + + //欠压保护 + //cell_uv+pack_uv+l0v + if(((canMem[0].status_byte1 & 0x0202) != 0) || ((canMem[0].status_byte3 & 0x0008) != 0)) + { + protectByte1 |= 0x04; + alarmByte3 |= 0x02; + protectByte3 |= 0x04; + } + else + { + protectByte1 &= 0xfb; + alarmByte3 &= 0xfd; + protectByte3 &= 0xfb; + } + +// //过压保护 +// //cell_ov+pack_ov+pf +// if((canMem[0].status_byte1 & 0x0141) != 0) +// { +// if(canMem[0].soc < 99) +// { +// protectByte1 |= 0x02; +// } +// else +// { +// protectByte1 &= 0xfd; +// } +// } +// else +// { +// protectByte1 &= 0xfd; +// } + + //充电过流保护 + //charge over current + if( ((canMem[0].status_byte1 & 0x0010) != 0) || ((canMem[0].status_byte4 & 0x0010) != 0)) + { + protectByte2 |= 0x01; + } + else + { + protectByte2 &= 0xfe; + } + + //告警 + //放电过流告警 + if((canMem[0].status_byte3 & 0x2000) != 0) + { + alarmByte1 |= 0x80; + } + else + { + alarmByte1 &= 0x7f; + } + + //低温告警 + if(((canMem[0].status_byte2 & 0xCC00) != 0) || ((canMem[0].status_byte4 & 0xC000) != 0)) + { + alarmByte1 |= 0x10; + } + else + { + alarmByte1 &= 0xef; + } + + //过温告警 + if(((canMem[0].status_byte2 & 0x3300) != 0) || ((canMem[0].status_byte4 & 0x3000) != 0)) + { + alarmByte1 |= 0x08; + } + else + { + alarmByte1 &= 0xf7; + } + + //欠压告警 + if((canMem[0].status_byte3 & 0x0A00) != 0) + { + alarmByte1 |= 0x04; + } + else + { + alarmByte1 &= 0xfb; + } + +// //过压告警 +// if((canMem[0].status_byte3 & 0x0500) != 0) +// { +// if(canMem[0].soc < 99) +// { +// alarmByte1 |= 0x02; +// } +// else +// { +// alarmByte1 &= 0xfd; +// } +// } +// else +// { +// alarmByte1 &= 0xfd; +// } + + //充电过流告警 + if((canMem[0].status_byte3 & 0x1000) != 0) + { + alarmByte2 |= 0x01; + } + else + { + alarmByte2 &= 0xfe; + } + + + if(CAN_SendCount ==0) //ID=0x359 + { + data[0] = protectByte1; + data[1] = protectByte2; + data[2] = alarmByte1; + data[3] = alarmByte2; + data[4] = OnlineNum; + data[5] = 0x50; + data[6] = 0x4E; + data[7] = 0X00; + CAN1_SendData(0x359, &data[0]); + } + + if(CAN_SendCount ==1) //ID = 0x351 + { + //充放电电流限制需要有符号区别吗？ + chgVolLimit = bmsMem.inverter_chgVolLimit; //充电电压限制，上位机配置，默认值57.6V + dsgVolLimit = bmsMem.inverter_dsgVolLimit; //放电电压限制，上位机配置，默认值41.6V + + if(chg_forbidFlg == 1) + { + chgCurLimit = 0; //Sol-Ark禁充 + } + else if(chg_curlimitFlg == 1) + { + chgCurLimit = Inv_curlimit * (OnlineNum-chg_cur0Num); //限流40A*未保护个数 + } + else + { + chgCurLimit = bmsMem.inverter_chgCurLimit * (OnlineNum-chg_curLimitNum); //充电电流限制，上位机配置，默认值100A + } + if(dsg_forbidFlg == 1) + { + dsgCurLimit = 0; //Sol-Ark禁放 + } + else + { + dsgCurLimit = bmsMem.inverter_dsgCurLimit * (OnlineNum-dsg_curLimitNum); //放电电流限制，上位机配置，默认值100A + } + + data[0] = chgVolLimit & 0xFF; //充电电压限制低位 + data[1] = (chgVolLimit >> 8) & 0xFF; + data[2] = chgCurLimit & 0xFF; //充电电流限制低位 + data[3] = (chgCurLimit >> 8) & 0xFF; + data[4] = dsgCurLimit & 0xFF; //放电电流限制低位 + data[5] = (dsgCurLimit >> 8) & 0xFF; + data[6] = dsgVolLimit & 0xFF; //放电电压限制低位 + data[7] = (dsgVolLimit >> 8) & 0xFF; + CAN1_SendData(0x351, &data[0]); + } + + if(CAN_SendCount ==2) + { + data[0] = canMem[0].soc & 0xFF; //SOC + data[1] = 0; + data[2] = canMem[0].soh & 0xFF; //SOH + data[3] = 0; + data[4] = 0X00; + data[5] = 0x00; + data[6] = 0x00; + data[7] = 0X00; + CAN1_SendData(0x355, &data[0]); + } + + if(CAN_SendCount ==3) + { + tempVol = (uint16_t)(bmsMem.packVoltage/10); //单位0.01 + tempCur = (int16_t)(canMem[0].cur/10); //单位0.1 + T_Average = canMem[0].temp;// 平均温度 + + data[0] = tempVol & 0xFF; + data[1] = (tempVol >>8) & 0xFF; //电池包电压 + data[2] = tempCur & 0xFF; + data[3] = (tempCur >>8) & 0xFF; //电池包电流 + data[4] = (T_Average -2731) & 0xFF;; + data[5] = ((T_Average -2731) >>8) & 0xFF; //温度-暂时取平均温度，具体哪一路需要客户确认 + data[6] = 0x00; + data[7] = 0X00; + CAN1_SendData(0x356, &data[0]); + } + + if(CAN_SendCount ==4) + { + status = 0x03; + if(chg_forbidFlg == 1)//sunways + { + status &= ~0x01; //禁充 + } + if(dsg_forbidFlg == 1)//sunways + { + status &= ~0x02; //禁放 + } + if(chg_forceFlg == 1)//sunways + { + status |= ~0x04; //强充 + } + + data[0] = 0x00; + data[1] = 0x00; + data[2] = alarmByte3; + data[3] = status; + data[4] = protectByte3; + data[5] = 0x00; + data[6] = 0x00; + data[7] = 0X00; + CAN1_SendData(0x399, &data[0]); + } + + if(CAN_SendCount ==5) + { + totalCapacity = ncc_Ah * OnlineNum; //单位1Ah + + data[0] = 0x00;//电池类型 + data[1] = 0x00; + data[2] = VersionMem.Software[0] & 0xFF;//BMS版本号，仅传输大版本号及小修改 + data[3] = VersionMem.Software[3] & 0xFF; + data[4] = totalCapacity & 0xFF; //容量 + data[5] = (totalCapacity >> 8) & 0xFF; + data[6] = 0x00;//制造商ID + data[7] = 0X00; + CAN1_SendData(0x35F, &data[0]); + } + + if(CAN_SendCount ==6) + { + RequestFlag = 0xC0; //充电允许0x80，放电允许0x40，不强充~0x20 + if(chg_forbidFlg == 1)//sunways + { + RequestFlag &= 0x7F; //禁充 + } + if(dsg_forbidFlg == 1)//sunways + { + RequestFlag &= 0xBF; //禁放 + } + if(chg_forceFlg == 1)//sunways + { + RequestFlag |= 0x20; //强充 + } + + data[0] = RequestFlag; + data[1] = 0x00; + data[2] = 0x00; + data[3] = 0x00; + data[4] = 0X00; + data[5] = 0x00; + data[6] = 0x00; + data[7] = 0X00; + CAN1_SendData(0x35C, &data[0]); + } + + if(CAN_SendCount ==7) //0x370 + { + data[0] = bmsMem.vCell[0] & 0xFF; //电芯N电压 + data[1] = (bmsMem.vCell[0] >> 8) & 0xFF; + data[2] = bmsMem.vCell[1] & 0xFF; //电芯N+1电压 + data[3] = (bmsMem.vCell[1] >> 8) & 0xFF; + data[4] = bmsMem.vCell[2] & 0xFF; //电芯N+2电压 + data[5] = (bmsMem.vCell[2] >> 8) & 0xFF; + data[6] = bmsMem.vCell[3] & 0xFF; //电芯N+3电压 + data[7] = (bmsMem.vCell[3] >> 8) & 0xFF; + CAN1_SendData(0x370, &data[0]); + } + + if(CAN_SendCount ==8) //0x371 + { + data[0] = bmsMem.vCell[4] & 0xFF; //电芯N+4电压 + data[1] = (bmsMem.vCell[4] >> 8) & 0xFF; + data[2] = bmsMem.vCell[5] & 0xFF; //电芯N+5电压 + data[3] = (bmsMem.vCell[5] >> 8) & 0xFF; + data[4] = bmsMem.vCell[6] & 0xFF; //电芯N+6电压 + data[5] = (bmsMem.vCell[6] >> 8) & 0xFF; + data[6] = bmsMem.vCell[7] & 0xFF; //电芯N+7电压 + data[7] = (bmsMem.vCell[7] >> 8) & 0xFF; + CAN1_SendData(0x371, &data[0]); + } + + if(CAN_SendCount ==9) //0x372 + { + data[0] = bmsMem.vCell[8] & 0xFF; //电芯N+8电压 + data[1] = (bmsMem.vCell[8] >> 8) & 0xFF; + data[2] = bmsMem.vCell[9] & 0xFF; //电芯N+9电压 + data[3] = (bmsMem.vCell[9] >> 8) & 0xFF; + data[4] = bmsMem.vCell[10] & 0xFF; //电芯N+10电压 + data[5] = (bmsMem.vCell[10] >> 8) & 0xFF; + data[6] = bmsMem.vCell[11] & 0xFF; //电芯N+11电压 + data[7] = (bmsMem.vCell[11] >> 8) & 0xFF; + CAN1_SendData(0x372, &data[0]); + } + + if(CAN_SendCount ==10) //0x373 + { + data[0] = bmsMem.vCell[12] & 0xFF; //电芯N+12电压 + data[1] = (bmsMem.vCell[12] >> 8) & 0xFF; + data[2] = bmsMem.vCell[13] & 0xFF; //电芯N+13电压 + data[3] = (bmsMem.vCell[13] >> 8) & 0xFF; + data[4] = bmsMem.vCell[14] & 0xFF; //电芯N+14电压 + data[5] = (bmsMem.vCell[14] >> 8) & 0xFF; + data[6] = bmsMem.vCell[15] & 0xFF; //电芯N+15电压 + data[7] = (bmsMem.vCell[15] >> 8) & 0xFF; + CAN1_SendData(0x373, &data[0]); + } + + if(CAN_SendCount ==11) //0x3D0 + { + data[0] = ((bmsMem.mcu_T1 - 2731)/10 + 50) & 0xFF; + data[1] = ((bmsMem.mcu_T2 - 2731)/10 + 50) & 0xFF; + data[2] = ((bmsMem.mcu_T3 - 2731)/10 + 50) & 0xFF; + data[3] = ((bmsMem.mcu_T4 - 2731)/10 + 50) & 0xFF; + data[4] = ((bmsMem.afe_T1 - 2731)/10 + 50) & 0xFF; + data[5] = ((bmsMem.afe_T2 - 2731)/10 + 50) & 0xFF;; + data[6] = ((bmsMem.afe_T3 - 2731)/10 + 50) & 0xFF;; + data[7] = 0X00; + CAN1_SendData(0x3D0, &data[0]); + } + + if(CAN_SendCount ==12) //0x3DA + { + data[0] = bmsMem.can_VolMax & 0xFF; + data[1] = (bmsMem.can_VolMax >>8) & 0xFF; + data[2] = bmsMem.can_VolMin & 0xFF; + data[3] = (bmsMem.can_VolMin >>8) & 0xFF; + data[4] = (bmsMem.can_VolMaxIndex + 1) & 0xFF; + data[5] = (bmsMem.can_VolMinIndex + 1) & 0xFF; + data[6] = 0X00; + data[7] = 0X00; + CAN1_SendData(0x3DA, &data[0]); + } + + if(CAN_SendCount ==13) //0x3DB + { + data[0] = ((bmsMem.can_TempMax - 2731)/10 + 50) & 0xFF; + data[1] = (((bmsMem.can_TempMax - 2731)/10 + 50) >>8) & 0xFF; + data[2] = ((bmsMem.can_TempMin - 2731)/10 + 50) & 0xFF; + data[3] = (((bmsMem.can_TempMin - 2731)/10 + 50) >>8) & 0xFF; + data[4] = (bmsMem.can_TempMaxIndex + 1) & 0xFF; + data[5] = (bmsMem.can_TempMinIndex + 1) & 0xFF; + data[6] = 0X00; + data[7] = 0X00; + CAN1_SendData(0x3DB, &data[0]); + } + + if(CAN_SendCount ==14) //0x35E + { + data[0] = 0x50; //制造商名称 + data[1] = 0x4E; + data[2] = 0x00; + data[3] = 0x00; + data[4] = 0X00; + data[5] = 0x00; + data[6] = 0x00; + data[7] = 0X00; + CAN1_SendData(0x35E, &data[0]); + } + + if(CAN_SendCount>=15) + { + CAN_SendCount = 0; + } + +} +//Lux power 深圳鹏城 +void CAN_Protocol_Luxpower(void) +{ + uint8_t data[8]; + uint16_t totalCapacity;//总容量 + + uint16_t tempVol; + int16_t tempCur; //总电流 + + uint16_t chgVolLimit; + uint16_t dsgVolLimit; + int16_t chgCurLimit; + int16_t dsgCurLimit; + + uint8_t protectByte1 = 0; + uint8_t protectByte2 = 0; + + uint8_t alarmByte1 = 0; + uint8_t alarmByte2 = 0; + + int16_t T_Max; // 最高温度 + int16_t T_Min; // 最低温度 + uint16_t cellVolMax=0; // 电芯单体最高电压 + uint16_t cellVolMin=0; // 电芯单体最低电压 + + + //保护 + //放电过流保护 + //discharge over current，SC, OCD1, OCD2 + if( ((canMem[0].status_byte1 & 0x042c) != 0) || ((canMem[0].status_byte2 & 0x0010) != 0) || ((canMem[0].status_byte4 & 0x0020) != 0)) + { + protectByte1 |= 0x80; + } + else + { + protectByte1 &= 0x7f; + } + + //低温保护 + //under temp at charging or discharging + if(((canMem[0].status_byte2 & 0x0005) != 0) || ((canMem[0].status_byte4 & 0x0C0C) != 0)) + { + protectByte1 |= 0x10; + } + else + { + protectByte1 &= 0xef; + } + + //过温保护 + //over temp at charging or discharging + if(((canMem[0].status_byte2 & 0x000A) != 0) || ((canMem[0].status_byte4 & 0x0303) != 0)) + { + protectByte1 |= 0x08; + } + else + { + protectByte1 &= 0xf7; + } + + //欠压保护 + //cell_uv+pack_uv+l0v + if(((canMem[0].status_byte1 & 0x0202) != 0) || ((canMem[0].status_byte3 & 0x0008) != 0)) + { + protectByte1 |= 0x04; + } + else + { + protectByte1 &= 0xfb; + } + +// //过压保护 +// //cell_ov+pack_ov+pf +// if((canMem[0].status_byte1 & 0x0141) != 0) +// { +// if(canMem[0].soc < 99) +// { +// protectByte1 |= 0x02; +// } +// else +// { +// protectByte1 &= 0xfd; +// } +// } +// else +// { +// protectByte1 &= 0xfd; +// } + + //充电过流保护 + //charge over current + if( ((canMem[0].status_byte1 & 0x0010) != 0) || ((canMem[0].status_byte4 & 0x0010) != 0)) + { + protectByte2 |= 0x01; + } + else + { + protectByte2 &= 0xfe; + } + + //告警 + //放电过流告警 + if((canMem[0].status_byte3 & 0x2000) != 0) + { + alarmByte1 |= 0x80; + } + else + { + alarmByte1 &= 0x7f; + } + + //低温告警 + if(((canMem[0].status_byte2 & 0xCC00) != 0) || ((canMem[0].status_byte4 & 0xC000) != 0)) + { + alarmByte1 |= 0x10; + } + else + { + alarmByte1 &= 0xef; + } + + //过温告警 + if(((canMem[0].status_byte2 & 0x3300) != 0) || ((canMem[0].status_byte4 & 0x3000) != 0)) + { + alarmByte1 |= 0x08; + } + else + { + alarmByte1 &= 0xf7; + } + + //欠压告警 + if((canMem[0].status_byte3 & 0x0A00) != 0) + { + alarmByte1 |= 0x04; + } + else + { + alarmByte1 &= 0xfb; + } + +// //过压告警 +// if((canMem[0].status_byte3 & 0x0500) != 0) +// { +// if(canMem[0].soc < 99) +// { +// alarmByte1 |= 0x02; +// } +// else +// { +// alarmByte1 &= 0xfd; +// } +// } +// else +// { +// alarmByte1 &= 0xfd; +// } + + //充电过流告警 + if((canMem[0].status_byte3 & 0x1000) != 0) + { + alarmByte2 |= 0x01; + } + else + { + alarmByte2 &= 0xfe; + } + + + if(CAN_SendCount ==0) //ID = 0x359 --- 报警/保护、总容量 + { + totalCapacity = ncc_Ah * OnlineNum; //单位1Ah + + data[0] = protectByte1; + data[1] = protectByte2; + data[2] = alarmByte1; + data[3] = alarmByte2; + data[4] = OnlineNum; + data[5] = totalCapacity & 0xFF; + data[6] = (totalCapacity >> 8) & 0xFF; + data[7] = 0X00; + CAN1_SendData(0x359, &data[0]); + } + if(CAN_SendCount ==1) //ID = 0x351 --- 充/放电限压/限流 + { + //充放电电流限制需要有符号区别吗？ + chgVolLimit = bmsMem.inverter_chgVolLimit; //充电电压限制，上位机配置，默认值57.6V + dsgVolLimit = bmsMem.inverter_dsgVolLimit; //放电电压限制，上位机配置，默认值41.6V + + if(chg_forbidFlg == 1) + { + chgCurLimit = 0; //Luxpower禁充 + } + else if(chg_curlimitFlg == 1) + { + chgCurLimit = Inv_curlimit * (OnlineNum-chg_cur0Num); //限流40A*未保护个数 + } + else + { + chgCurLimit = bmsMem.inverter_chgCurLimit * (OnlineNum-chg_curLimitNum); //充电电流限制，上位机配置，默认值100A + } + if(dsg_forbidFlg == 1) + { + dsgCurLimit = 0; //Luxpower禁放 + } + else + { + dsgCurLimit = bmsMem.inverter_dsgCurLimit * (OnlineNum-dsg_curLimitNum); //放电电流限制，上位机配置，默认值100A + } + + data[0] = chgVolLimit & 0xFF; //充电电压限制低位 + data[1] = (chgVolLimit >> 8) & 0xFF; + data[2] = chgCurLimit & 0xFF; //充电电流限制低位 + data[3] = (chgCurLimit >> 8) & 0xFF; + data[4] = dsgCurLimit & 0xFF; //放电电流限制低位 + data[5] = (dsgCurLimit >> 8) & 0xFF; + data[6] = dsgVolLimit & 0xFF; //放电电压限制低位 + data[7] = (dsgVolLimit >> 8) & 0xFF; + CAN1_SendData(0x351, &data[0]); + } + if(CAN_SendCount ==2) //ID = 0x355 --- SOC/SOH、最大/小电压 + { + cellVolMax = canMem[0].VolMax; + cellVolMin = canMem[0].VolMin; + + data[0] = canMem[0].soc & 0xFF; //SOC + data[1] = 0; + data[2] = canMem[0].soh & 0xFF; //SOH + data[3] = 0; + data[4] = cellVolMax & 0xFF; //最大单体电压 + data[5] = (cellVolMax >> 8) & 0xFF; + data[6] = cellVolMin & 0xFF; //最小单体电压 + data[7] = (cellVolMin >> 8) & 0xFF; + CAN1_SendData(0x355, &data[0]); + } + if(CAN_SendCount ==3) //ID = 0x356 --- 总电压/电流、最大/小温度 + { + tempVol = (uint16_t)(bmsMem.packVoltage/10); //单位0.01 + tempCur = (int16_t)(canMem[0].cur/10); //单位0.1 + T_Max = canMem[0].TempMax; // 最高温度 单位0.1 + T_Min = canMem[0].TempMin; // 最低温度 单位0.1 + + data[0] = tempVol & 0xFF; + data[1] = (tempVol >>8) & 0xFF; //电池包电压 + data[2] = tempCur & 0xFF; + data[3] = (tempCur >>8) & 0xFF; //电池包电流 + data[4] = (T_Max -2731) & 0xFF; //最高单体温度 + data[5] = ((T_Max -2731) >> 8) & 0xFF; + data[6] = (T_Min -2731) & 0xFF; //最低单体温度 + data[7] = ((T_Min -2731) >> 8) & 0xFF; + CAN1_SendData(0x356, &data[0]); + } + if(CAN_SendCount ==4) //ID = 0x35C --- 总电压/电流、最大/小温度 + { + RequestFlag = 0xC0; //充电允许0x80，放电允许0x40，不强充~0x20 + if(chg_forbidFlg == 1)//Lux power + { + RequestFlag &= 0x7F; //禁充 + } + if(dsg_forbidFlg == 1)//Lux power + { + RequestFlag &= 0xBF; //禁放 + } + if(chg_forceFlg == 1)//Lux power + { + RequestFlag |= 0x20; //强充 + } + + data[0] = RequestFlag; //充电允许，放电允许 + data[1] = 0x00; + data[2] = 0x00; + data[3] = 0x00; + data[4] = 0X00; + data[5] = 0x00; + data[6] = 0x00; + data[7] = 0X00; + CAN1_SendData(0x35C, &data[0]); + } + + if(CAN_SendCount>=5) + { + CAN_SendCount = 0; + } +} + +//Schneider 施耐德 +void CAN_Protocol_Schneider(void) +{ + uint8_t data[8]; + uint16_t totalCapacity; //总容量 + + uint32_t tempVol; //总电压 + int32_t tempCur; //总电流 + + uint32_t chgVolLimit; //充电限压 + uint32_t dsgVolLimit; //放电限压 + int32_t chgCurLimit; //充电限流 + int32_t dsgCurLimit; //放电限流 + + uint8_t protectByte1 = 0; //保护位1，与告警位1值相同 + + uint8_t alarmByte1 = 0; + + + int16_t T_Average; // 平均温度 + int16_t T_Max; // 最高温度 + int16_t T_Min; // 最低温度 + + uint16_t cellVolMax=0; // 电芯单体最高电压 + uint16_t cellVolMin=0; // 电芯单体最低电压 + + +// //Data2 BIT6 cell imbalance +// if((bmsMem.balanceStatus & 0x01) !=0) //表示开启了均衡 +// { +// protectByte1 |= 0xBF; +// alarmByte1 |= 0xBF; +// } +// else +// { +// protectByte1 &= 0x40; +// alarmByte1 &= 0x40; +// } + + //保护 + //欠压保护 + //cell_uv+pack_uv+l0v + if(((canMem[0].status_byte1 & 0x0202) != 0) || ((canMem[0].status_byte3 & 0x0008) != 0)) + { + protectByte1 |= 0x20; + } + else + { + protectByte1 &= 0xDF; + } + +// //过压保护 +// //cell_ov+pack_ov+pf +// if((canMem[0].status_byte1 & 0x0141) != 0) +// { +// if(canMem[0].soc < 99) +// { +// protectByte1 |= 0x10; +// } +// else +// { +// protectByte1 &= 0xEF; +// } +// } +// else +// { +// protectByte1 &= 0xEF; +// } + + //低温保护 + //under temp at charging or discharging + if(((canMem[0].status_byte2 & 0x0005) != 0) || ((canMem[0].status_byte4 & 0x0C0C) != 0)) + { + protectByte1 |= 0x08; + } + else + { + protectByte1 &= 0xF7; + } + + //过温保护 + //over temp at charging or discharging + if(((canMem[0].status_byte2 & 0x000A) != 0) || ((canMem[0].status_byte4 & 0x0303) != 0)) + { + protectByte1 |= 0x04; + } + else + { + protectByte1 &= 0xFB; + } + + //放电过流保护 + //discharge over current，SC, OCD1, OCD2 + if( ((canMem[0].status_byte1 & 0x042c) != 0) || ((canMem[0].status_byte2 & 0x0010) != 0) || ((canMem[0].status_byte4 & 0x0020) != 0)) + { + protectByte1 |= 0x02; + } + else + { + protectByte1 &= 0xFD; + } + + //充电过流保护 + //charge over current + if( ((canMem[0].status_byte1 & 0x0010) != 0) || ((canMem[0].status_byte4 & 0x0010) != 0)) + { + protectByte1 |= 0x01; + } + else + { + protectByte1 &= 0xFE; + } + + //告警 + //欠压告警 + if((canMem[0].status_byte3 & 0x0A00) != 0) + { + alarmByte1 |= 0x20; + } + else + { + alarmByte1 &= 0xDF; + } + +// //过压告警 +// if((canMem[0].status_byte3 & 0x0500) != 0) +// { +// if(canMem[0].soc < 99) +// { +// alarmByte1 |= 0x10; +// } +// else +// { +// alarmByte1 &= 0xEF; +// } +// } +// else +// { +// alarmByte1 &= 0xEF; +// } + + //低温告警 + if(((canMem[0].status_byte2 & 0xCC00) != 0) || ((canMem[0].status_byte4 & 0xC000) != 0)) + { + alarmByte1 |= 0x08; + } + else + { + alarmByte1 &= 0xF7; + } + + //过温告警 + if(((canMem[0].status_byte2 & 0x3300) != 0) || ((canMem[0].status_byte4 & 0x3000) != 0)) + { + alarmByte1 |= 0x04; + } + else + { + alarmByte1 &= 0xFB; + } + + //放电过流告警 + if((canMem[0].status_byte3 & 0x2000) != 0) + { + alarmByte1 |= 0x02; + } + else + { + alarmByte1 &= 0xFD; + } + + //充电过流告警 + if((canMem[0].status_byte3 & 0x1000) != 0) + { + alarmByte1 |= 0x01; + } + else + { + alarmByte1 &= 0xFE; + } + + + if(CAN_SendCount ==0) //ID = 0x321 - 最大充电电压、最小放电电压 + { + //充放电电流限制需要有符号区别吗？ + chgVolLimit = bmsMem.inverter_chgVolLimit; //充电电压限制，上位机配置，默认值57.6V + dsgVolLimit = bmsMem.inverter_dsgVolLimit; //放电电压限制，上位机配置，默认值41.6V + + data[0] = 0x00; + data[1] = 0x00; + data[2] = (chgVolLimit >> 8) & 0xFF; + data[3] = chgVolLimit & 0xFF; //最大充电电压 + data[4] = 0x00; + data[5] = 0x00; + data[6] = (dsgVolLimit >> 8) & 0xFF; + data[7] = dsgVolLimit & 0xFF; //最小放电电压 + CAN1_SendData(0x321, &data[0]); + } + if(CAN_SendCount ==1) //ID = 0x322 - 最大充电电流、最大放电电流 + { + //充放电电流限制需要有符号区别吗？ + if(chg_forbidFlg == 1) + { + chgCurLimit = 0; //Schneider禁充 + } + else if(chg_curlimitFlg == 1) + { + chgCurLimit = Inv_curlimit * (OnlineNum-chg_cur0Num); //限流40A*未保护个数 + } + else + { + chgCurLimit = bmsMem.inverter_chgCurLimit * (OnlineNum-chg_curLimitNum); //充电电流限制，上位机配置，默认值100A + } + if(dsg_forbidFlg == 1) + { + dsgCurLimit = 0; //Schneider禁放 + } + else + { + dsgCurLimit = bmsMem.inverter_dsgCurLimit * (OnlineNum-dsg_curLimitNum); //放电电流限制，上位机配置，默认值100A + } + + data[0] = 0x00; + data[1] = 0x00; + data[2] = (chgCurLimit >> 8) & 0xFF; + data[3] = chgCurLimit & 0xFF; //最大充电电流 + data[4] = 0x00; + data[5] = 0x00; + data[6] = (dsgCurLimit >> 8) & 0xFF; + data[7] = dsgCurLimit & 0xFF; //最大放电电流 + CAN1_SendData(0x322, &data[0]); + } + if(CAN_SendCount ==2) //ID = 0x323 - 电池电压、电流 + { + tempVol = (int16_t)(bmsMem.packVoltage/10); //单位0.01 + tempCur = (int16_t)(canMem[0].cur/10); //单位0.1 + + data[0] = 0x00; + data[1] = 0x00; + data[2] = (tempVol >>8) & 0xFF; //电池组电压 0.01 + data[3] = tempVol & 0xFF; + data[4] = 0x00; + data[5] = 0x00; + data[6] = (tempCur >>8) & 0xFF; //电池组电流 0.1 + data[7] = tempCur & 0xFF; + CAN1_SendData(0x323, &data[0]); + } + if(CAN_SendCount ==3) //ID = 0x324 - 温度、SOC + { + totalCapacity = 100 * ncc_Ah * OnlineNum; //单位0.01Ah + T_Average = canMem[0].temp;// 平均温度 + + data[0] = ((T_Average-2731) >>8) & 0xFF; + data[1] = (T_Average-2731) & 0xFF; //平均温度 0.1 + data[2] = 0x00; + data[3] = canMem[0].soc & 0xFF; //SOC + data[4] = 0x00; + data[5] = 0x00; + data[6] = 0x00; + data[7] = 0x00; + CAN1_SendData(0x324, &data[0]); + } + if(CAN_SendCount ==4) //ID = 0x325 - 允许位、报警/保护 + { + RequestFlag = 0xC0; //充电允许0x02，放电允许0x04，不强充~0x01 + if(chg_forbidFlg == 1)//Schneider + { + RequestFlag &= 0xFD; //禁充 + } + if(dsg_forbidFlg == 1)//Schneider + { + RequestFlag &= 0xFB; //禁放 + } + if(chg_forceFlg == 1)//Schneider + { + RequestFlag |= 0x01; //强充 + } + + data[0] = RequestFlag; //充电允许放电允许 + data[1] = 0x00; + data[2] = protectByte1; + data[3] = 0x00; + data[4] = alarmByte1; + data[5] = 0x00; + data[6] = 0x00; + data[7] = 0x00; + CAN1_SendData(0x325, &data[0]); + } + if(CAN_SendCount ==5) //ID = 0x326 - SOH、满充容量 + { + totalCapacity = 100 * ncc_Ah * OnlineNum; //单位0.01Ah + + data[0] = 0x00; + data[1] = 0x00; + data[2] = 0x00; + data[3] = 0x00; + data[4] = 0; + data[5] = canMem[0].soh & 0xFF; //SOH + data[6] = (totalCapacity >> 8) & 0xFF; + data[7] = totalCapacity & 0xFF; //电池满充容量 10mAh + CAN1_SendData(0x326, &data[0]); + } + if(CAN_SendCount ==6) //ID = 0x327 - 电池最高/低温度、电池最高/低电压 + { + T_Max = canMem[0].TempMax; // 最高温度 + T_Min = canMem[0].TempMin; // 最低温度 + cellVolMax = canMem[0].VolMax; + cellVolMin = canMem[0].VolMin; + + data[0] = ((T_Max -2731) >> 8) & 0xFF; + data[1] = (T_Max -2731) & 0xFF; //最大电池温度 + data[2] = ((T_Min -2731) >> 8) & 0xFF; + data[3] = (T_Min -2731) & 0xFF; //最小电池温度 + data[4] = (cellVolMax >> 8) & 0xFF; + data[5] = cellVolMax & 0xFF; //最大电池电压 + data[6] = (cellVolMin >> 8) & 0xFF; + data[7] = cellVolMin & 0xFF; //最小电池电压 + CAN1_SendData(0x327, &data[0]); + } + + if(CAN_SendCount>=7) + { + CAN_SendCount = 0; + } +} + +//AlpSolarr 力高 +void CAN_Protocol_AlpSolarr(void) +{ + uint8_t data[8]; + uint16_t totalCapacity; + + uint16_t tempVol; + int16_t tempCur; + + uint16_t chgVolLimit; + uint16_t dsgVolLimit; + int16_t chgCurLimit; + int16_t dsgCurLimit; + + uint8_t protectByte1 = 0; + uint8_t protectByte2 = 0; + + int16_t T_Average; // 平均温度 + int16_t T_Max; // 最高温度 + int16_t T_Min; // 最低温度 + uint16_t cellVolMax=0; // 电芯单体最高电压 + int16_t cellVolMin=0; // 电芯单体最低电压 + + //BIT7 discharge over current，SC, OCD1, OCD2 + if( ((canMem[0].status_byte1 & 0x2c) !=0) || ((canMem[0].status_byte4 & 0x20) !=0) ) + { + protectByte1 |= 0x80; + } + else + { + protectByte1 &= 0x7f; + } + + //BIT4 cell under temp at charging or discharging + //add mcu temp protect status + if( ((canMem[0].status_byte2 & 0x05) !=0) || ((canMem[0].status_byte4 & 0x0C) !=0) ) + { + protectByte1 |= 0x10; + } + else + { + protectByte1 &= 0xEF; + } + + //BIT3 cell over temp at charging or discharging + //add mcu temp protect status + if( ((canMem[0].status_byte2 & 0x0A) !=0) || ((canMem[0].status_byte4 & 0x03) !=0) ) + { + protectByte1 |= 0x08; + } + else + { + protectByte1 &= 0xF7; + } + + //BIT2 cell uv + if((canMem[0].status_byte1 & 0x02) !=0) + { + protectByte1 |= 0x04; + } + else + { + protectByte1 &= 0xfb; + } + + //BIT1 cell ov + if((canMem[0].status_byte1 & 0x01) !=0) + { + if(canMem[0].soc < 99) + { + protectByte1 |= 0x02; + } + else + { + protectByte1 &= 0xfd; + } + } + else + { + protectByte1 &= 0xfd; + } + + //BIT0 charge over current + if( ((canMem[0].status_byte1 & 0x10) !=0) || ((canMem[0].status_byte4 & 0x10) !=0) ) + { + protectByte2 |= 0x01; + } + else + { + protectByte2 &= 0xfe; + } + +// //Data1 BIT4 cell balance +// if((bmsMem.balanceStatus & 0x01) !=0) +// { +// protectByte2 |= 0x10; +// } +// else +// { +// protectByte2 &= 0xef; +// } + + + if(CAN_SendCount ==0) //ID=0x359 + { + data[0] = protectByte1; + data[1] = protectByte2; + data[2] = protectByte1; + data[3] = protectByte2; + data[4] = 0X00; + data[5] = 0X00; + data[6] = 0X00; + data[7] = 0X00; + CAN1_SendData(0x359, &data[0]); + } + if(CAN_SendCount ==1) //ID = 0x351 + { + //充放电电流限制需要有符号区别吗？ + chgVolLimit = bmsMem.inverter_chgVolLimit; //充电电压限制，上位机配置，默认值57.6V + dsgVolLimit = bmsMem.inverter_dsgVolLimit; //放电电压限制，上位机配置，默认值41.6V + + if(chg_forbidFlg == 0) + { + chgCurLimit = bmsMem.inverter_chgCurLimit * (OnlineNum-chg_curLimitNum); //充电电流限制，上位机配置，默认值100A + } + else + { + chgCurLimit = 0; //禁充 + } + if(dsg_forbidFlg == 0) + { + dsgCurLimit = bmsMem.inverter_dsgCurLimit * (OnlineNum-dsg_curLimitNum); //放电电流限制，上位机配置，默认值100A + } + else + { + dsgCurLimit = 0; //禁放 + } + + data[0] = chgVolLimit & 0xFF; //充电电压限制低位 + data[1] = (chgVolLimit >> 8) & 0xFF; + data[2] = chgCurLimit & 0xFF; //充电电流限制低位 + data[3] = (chgCurLimit >> 8) & 0xFF; + data[4] = dsgCurLimit & 0xFF; //放电电流限制低位 + data[5] = (dsgCurLimit >> 8) & 0xFF; + data[6] = dsgVolLimit & 0xFF; //放电电压限制低位 + data[7] = (dsgVolLimit >> 8) & 0xFF; + CAN1_SendData(0x351, &data[0]); + } + if(CAN_SendCount ==2) + { + data[0] = canMem[0].soc & 0xFF; //SOC + data[1] = 0; + data[2] = canMem[0].soh & 0xFF; //SOH + data[3] = 0; + data[4] = 0X00; + data[5] = 0x00; + data[6] = 0x00; + data[7] = 0X00; + CAN1_SendData(0x355, &data[0]); + } + if(CAN_SendCount ==3) + { + tempVol = (uint16_t)(bmsMem.packVoltage/10); //单位0.01 + tempCur = (int16_t)(canMem[0].cur/10); //单位0.1 + T_Average = canMem[0].temp;// 平均温度 + + data[0] = tempVol & 0xFF; + data[1] = (tempVol >>8) & 0xFF; //电池包电压 + data[2] = tempCur & 0xFF; + data[3] = (tempCur >>8) & 0xFF; //电池包电流 + data[4] = (T_Average -2731) & 0xFF;; + data[5] = ((T_Average -2731) >>8) & 0xFF; //温度-暂时取平均温度，具体哪一路需要客户确认 + data[6] = 0x00; + data[7] = 0X00; + CAN1_SendData(0x356, &data[0]); + } + if(CAN_SendCount ==4) //ID = 0x370 - 最大/最小单体温度，最大/最小单体电压（新加入） + { + T_Max = canMem[0].TempMax; // 最高温度 + T_Min = canMem[0].TempMin; // 最低温度 + cellVolMax = canMem[0].VolMax; + cellVolMin = canMem[0].VolMin; + + data[0] = (T_Max -2731) & 0xFF; //最大单体温度 + data[1] = ((T_Max -2731) >> 8) & 0xFF; + data[2] = (T_Min -2731) & 0xFF; //最小单体温度 + data[3] = ((T_Min -2731) >> 8) & 0xFF; + data[4] = cellVolMax & 0xFF; //最大单体电压 + data[5] = (cellVolMax >> 8) & 0xFF; + data[6] = cellVolMin & 0xFF; //最小单体电压 + data[7] = (cellVolMin >> 8) & 0xFF; + CAN1_SendData(0x370, &data[0]); + } + if(CAN_SendCount ==5) + { + RequestFlag = 0xC0; //充电允许0x80，放电允许0x40，不强充~0x20 + if(chg_forbidFlg == 1) + { + RequestFlag &= 0x7F; //禁充 + } + if(dsg_forbidFlg == 1) + { + RequestFlag &= 0xBF; //禁放 + } + if(chg_forceFlg == 1) + { + RequestFlag |= 0x20; //强充 + } + + data[0] = RequestFlag; + data[1] = 0x00; + data[2] = 0x00; + data[3] = 0x00; + data[4] = 0X00; + data[5] = 0x00; + data[6] = 0x00; + data[7] = 0X00; + CAN1_SendData(0x35C, &data[0]); + } + if(CAN_SendCount ==6) //0x35E + { + totalCapacity = fcc_Ah * OnlineNum; //单位1Ah + + data[0] = 0x00; + data[1] = 0x00; + data[2] = 0x00; + data[3] = 0x00; + data[4] = 0x00; + data[5] = 0x00; + data[6] = totalCapacity & 0xFF; + data[7] = (totalCapacity >> 8) & 0xFF; + CAN1_SendData(0x35E, &data[0]); + } +// if(CAN_SendCount ==7) +// { +// data[0] = 0xAA; +// data[1] = 0xAA; +// data[2] = 0xAA; +// data[3] = 0xAA; +// data[4] = 0xAA; +// data[5] = 0xAA; +// data[6] = 0xAA; +// data[7] = 0xAA; +// CAN1_SendData(0x305, &data[0]); +// } + + if(CAN_SendCount>=7) + { + CAN_SendCount = 0; + } +} + +//MODBUS: +//SRNE 硕日 +void MOD_Protocol_SRNE(void) +{ + uint8_t i; + uint16_t protectByte = 0; //0x0000-0xFFFF + uint16_t alarmByte = 0; + uint16_t statusByte = 0; + + + //保护 +// //单体过压保护 +// //cell_ov+pack_ov+pf +// if(((canMem[0].status_byte1 & 0x0001) != 0) || ((canMem[0].status_byte1 & 0x0040) != 0)) +// { +// if(canMem[0].soc < 99) +// { +// alarmByte |= 0x0001; +// } +// else +// { +// alarmByte &= 0xFFFE; +// } +// } +// else +// { +// alarmByte &= 0xFFFE; +// } + + //单体欠压保护 + //cell_uv+pack_uv+l0v + if(((canMem[0].status_byte1 & 0x0002) != 0) || ((canMem[0].status_byte3 & 0x0008) != 0)) + { + alarmByte |= 0x0002; + } + else + { + alarmByte &= 0xFFFD; + } + +// //总体过压保护 +// if((canMem[0].status_byte1 & 0x0100) != 0) +// { +// alarmByte |= 0x0004; +// } +// else +// { +// alarmByte &= 0xFFFB; +// } + + //总体欠压保护 + if((canMem[0].status_byte1 & 0x0200) != 0) + { + alarmByte |= 0x0008; + } + else + { + alarmByte &= 0xFFF7; + } + + //充电过流保护 + //charge over current + if( ((canMem[0].status_byte1 & 0x0010) != 0) || ((canMem[0].status_byte4 & 0x0010) != 0)) + { + protectByte |= 0x0010; + } + else + { + protectByte &= 0xFFEF; + } + + //放电过流保护 + //discharge over current，SC, OCD1, OCD2 + if( ((canMem[0].status_byte1 & 0x042c) != 0) || ((canMem[0].status_byte2 & 0x0010) != 0) || ((canMem[0].status_byte4 & 0x0020) != 0)) + { + protectByte |= 0x0020; + } + else + { + protectByte &= 0xFFDF; + } + + //充电高温保护 + //charge over temp 高温 + if( ((canMem[0].status_byte2 & 0x0002) !=0) || ((canMem[0].status_byte4 & 0x0101) !=0) ) + { + protectByte |= 0x0100; + } + else + { + protectByte &= 0xFEFF; + } + + //放电高温保护 + //discharge over temp + if( ((canMem[0].status_byte2 & 0x0008) !=0) || ((canMem[0].status_byte4 & 0x0202) !=0) ) + { + protectByte |= 0x0200; + } + else + { + protectByte &= 0xFDFF; + } + + //充电低温保护 + //charge under temp 低温 + if( ((canMem[0].status_byte2 & 0x0001) !=0) || ((canMem[0].status_byte4 & 0x0404) !=0) ) + { + protectByte |= 0x0400; + } + else + { + protectByte &= 0xFBFF; + } + + //放电低温保护 + //discharge under temp + if( ((canMem[0].status_byte2 & 0x0004) !=0) || ((canMem[0].status_byte4 & 0x0808) !=0) ) + { + protectByte |= 0x0800; + } + else + { + protectByte &= 0xF7FF; + } + + //环境低温保护 0x4000 + if((canMem[0].status_byte4 & 0x0C00) !=0) //环境充放电低温 + { + protectByte |= 0x4000; + } + else + { + protectByte &= 0xBFFF; + } + + //环境高温保护 0x2000 + if((canMem[0].status_byte4 & 0x0300) !=0) //环境充放电高温 + { + protectByte |= 0x2000; + } + else + { + protectByte &= 0xDFFF; + } + + //MOS高温保护 0x1000 + if((canMem[0].status_byte2 & 0x0300) !=0) //MOS充放电高温 + { + protectByte |= 0x1000; + } + else + { + protectByte &= 0xEFFF; + } + + + //告警 +// //单体过压告警 +// //cell_ov+pack_ov+pf +// if((canMem[0].status_byte3 & 0x0100) != 0) +// { +// if(canMem[0].soc < 99) +// { +// alarmByte |= 0x0001; +// } +// else +// { +// alarmByte &= 0xFFFE; +// } +// } +// else +// { +// alarmByte &= 0xFFFE; +// } + + //单体欠压告警 + //cell_uv+pack_uv+l0v + if((canMem[0].status_byte3 & 0x0200) != 0) + { + alarmByte |= 0x0002; + } + else + { + alarmByte &= 0xFFFD; + } + +// //总体过压告警 +// if((canMem[0].status_byte3 & 0x0400) != 0) +// { +// alarmByte |= 0x0004; +// } +// else +// { +// alarmByte &= 0xFFFB; +// } + + //总体欠压告警 + if((canMem[0].status_byte3 & 0x0800) != 0) + { + alarmByte |= 0x0008; + } + else + { + alarmByte &= 0xFFF7; + } + + //充电过流告警 + //charge over current + if((canMem[0].status_byte3 & 0x1000) != 0) + { + alarmByte |= 0x0010; + } + else + { + alarmByte &= 0xFFEF; + } + + //放电过流告警 + //discharge over current，SC, OCD1, OCD2 + if((canMem[0].status_byte3 & 0x0200) != 0) + { + alarmByte |= 0x0020; + } + else + { + alarmByte &= 0xFFDF; + } + + //充电高温告警 + //charge over temp 高温 + if( ((canMem[0].status_byte2 & 0x1100) !=0) || ((canMem[0].status_byte4 & 0x1000) !=0) ) + { + alarmByte |= 0x0100; + } + else + { + alarmByte &= 0xFEFF; + } + + //放电高温告警 + //discharge over temp + if( ((canMem[0].status_byte2 & 0x2200) !=0) || ((canMem[0].status_byte4 & 0x2000) !=0) ) + { + alarmByte |= 0x0200; + } + else + { + alarmByte &= 0xFDFF; + } + + //充电低温告警 + //charge under temp 低温 + if( ((canMem[0].status_byte2 & 0x4400) !=0) || ((canMem[0].status_byte4 & 0x4000) !=0) ) + { + alarmByte |= 0x0400; + } + else + { + alarmByte &= 0xFBFF; + } + + //放电低温告警 + //discharge under temp + if( ((canMem[0].status_byte2 & 0x8800) !=0) || ((canMem[0].status_byte4 & 0x8000) !=0) ) + { + alarmByte |= 0x0800; + } + else + { + alarmByte &= 0xF7FF; + } + + //环境低温告警 0x4000 + if((canMem[0].status_byte4 & 0xC000) !=0) //环境充放电低温 + { + alarmByte |= 0x4000; + } + else + { + alarmByte &= 0xBFFF; + } + + //环境高温告警 0x2000 + if((canMem[0].status_byte4 & 0x3000) !=0) //环境充放电高温 + { + alarmByte |= 0x2000; + } + else + { + alarmByte &= 0xDFFF; + } + + //MOS高温告警 0x1000 + if((canMem[0].status_byte2 & 0x3000) !=0) //MOS充放电高温 + { + alarmByte |= 0x1000; + } + else + { + alarmByte &= 0xEFFF; + } + + + SRNEMem.protect_byte = protectByte; //保护标志 Hex 2byte + SRNEMem.alarm_byte = alarmByte; //告警标志 Hex 2byte + + //状态位赋值 + if(bCHGING == 1) //充电 + { + statusByte |= 0x0100; + } + else + { + statusByte &= 0xFEFF; + } + if(bDSGING == 1) //放电 + { + statusByte |= 0x0200; + } + else + { + statusByte &= 0xFDFF; + } + if((canMem[0].status_byte3 & 0x02) !=0) //充电MOS状态 + { + statusByte |= 0x0400; + } + else + { + statusByte &= 0xFBFF; + } + if((canMem[0].status_byte3 & 0x01) !=0) //放电MOS状态 + { + statusByte |= 0x0800; + } + else + { + statusByte &= 0xF7FF; + } + SRNEMem.status_byte = statusByte; //状态/故障标志 Hex 2byte + + + SRNEMem.balanceStatus = bmsMem.balanceStatus;//平衡状态 Hex 2byte + + + SRNEMem.packCurrent = (int16_t)(canMem[0].cur); //电流 10mA 2byte + SRNEMem.packVoltage = (uint16_t)(bmsMem.packVoltage/10); //电池组电压 10mA 2byte + + SRNEMem.soc = (uint8_t)canMem[0].soc; //SOC % 2byte + SRNEMem.soh = (uint8_t)canMem[0].soh; //SOH % 2byte + + SRNEMem.fcc = 100 * ncc_Ah * OnlineNum; //满容量 10mAH 2byte + SRNEMem.rcc = 100 * ncc_Ah * OnlineNum * SRNEMem.soc/100; //剩余容量 10mAH 2byte + + + //电芯电压 + for(i=0;i<16;i++) + { + SRNEMem.vCell[i] = bmsMem.vCell[i]; //电池电压 mV 32byte + } + //电芯温度 + SRNEMem.Tcell[0] = (int16_t)(bmsMem.mcu_T1-2731); //电池温度 0.1℃ 8byte + SRNEMem.Tcell[1] = (int16_t)(bmsMem.mcu_T2-2731); + SRNEMem.Tcell[2] = (int16_t)(bmsMem.mcu_T3-2731); + SRNEMem.Tcell[3] = (int16_t)(bmsMem.mcu_T4-2731); + + SRNEMem.afe_MOS = (int16_t)((bmsMem.afe_T1 + bmsMem.afe_T2)/2 - 2731); //MOS温度 0.1℃ 2byte 对应上下MOS的温度平均值 + SRNEMem.afe_MCU = (int16_t)(bmsMem.afe_T3-2731); //环境温度 0.1℃ 2byte 对应MCU芯片温度 + + //充放电电流限制需要有符号区别吗？ + SRNEMem.chgVolLimit = bmsMem.inverter_chgVolLimit; //充电电压限制，上位机配置，默认值57.6V + //SRNEMem.dsgVolLimit = bmsMem.inverter_dsgVolLimit; //放电电压限制，上位机配置，默认值41.6V + + if(chg_forbidFlg == 1) + { + SRNEMem.chgCurLimit = 0; //SRNE禁充 + } + else if(chg_curlimitFlg == 1) + { + SRNEMem.chgCurLimit = Inv_curlimit * (OnlineNum-chg_cur0Num); //限流40A*未保护个数 + } + else + { + SRNEMem.chgCurLimit = bmsMem.inverter_chgCurLimit * (OnlineNum-chg_curLimitNum); //充电电流限制，上位机配置，默认值100A + } + if(dsg_forbidFlg == 1) + { + SRNEMem.dsgCurLimit = 0; //SRNE禁放 + } + else + { + SRNEMem.dsgCurLimit = bmsMem.inverter_dsgCurLimit * (OnlineNum-dsg_curLimitNum); //放电电流限制，上位机配置，默认值100A + } + +} + +//Voltronic 日月元 +void MOD_Protocol_Voltronic(void) +{ + uint8_t i; + + uint16_t chg_alarm_byte = 0; + uint16_t dsg_alarm_byte = 0; + uint16_t chg_protect1_byte = 0; + uint16_t dsg_protect1_byte = 0; + + //充电告警 + //充电过流告警 + //charge over current + if((canMem[0].status_byte3 & 0x1000) !=0) + { + chg_alarm_byte |= 0x0008; + } + else + { + chg_alarm_byte &= 0xFFF7; + } + + //充电低温告警 + //charge under temp + if( ((canMem[0].status_byte2 & 0x4400) !=0) || ((canMem[0].status_byte4 & 0x4000) !=0) ) + { + chg_alarm_byte |= 0x0004; + } + else + { + chg_alarm_byte &= 0xFFFB; + } + +// //过压告警 +// if((canMem[0].status_byte3 & 0x0500) != 0) +// { +// if(canMem[0].soc < 99) +// { +// chg_alarm_byte |= 0x0002; +// } +// else +// { +// chg_alarm_byte &= 0xFFFD; +// } +// } +// else +// { +// chg_alarm_byte &= 0xFFFD; +// } + + //充电高温告警 + //charge over temp + if( ((canMem[0].status_byte2 & 0x1100) !=0) || ((canMem[0].status_byte4 & 0x1000) !=0) ) + { + chg_alarm_byte |= 0x0001; + } + else + { + chg_alarm_byte &= 0xFFFE; + } + + //放电告警 + //欠压告警 + if((canMem[0].status_byte3 & 0x0A00) != 0) + { + dsg_alarm_byte |= 0x0008; + } + else + { + dsg_alarm_byte &= 0xFFF7; + } + + //MOS高温告警 + if((canMem[0].status_byte2 & 0x0200) != 0) + { + dsg_alarm_byte |= 0x0004; + } + else + { + dsg_alarm_byte &= 0xFFFB; + } + + //放电低温告警 + //discharge under temp + if( ((canMem[0].status_byte2 & 0x8800) !=0) || ((canMem[0].status_byte4 & 0x8000) !=0) ) + { + dsg_alarm_byte |= 0x0002; + } + else + { + dsg_alarm_byte &= 0xFFFD; + } + + //放电高温告警 + //discharge over temp + if( ((canMem[0].status_byte2 & 0x2200) !=0) || ((canMem[0].status_byte4 & 0x2000) !=0) ) + { + dsg_alarm_byte |= 0x0001; + } + else + { + dsg_alarm_byte &= 0xFFFE; + } + + //保护 + //充电保护1 + //充电过流保护 + //charge over current + if( ((canMem[0].status_byte1 & 0x0010) != 0) || ((canMem[0].status_byte4 & 0x0010) != 0)) + { + chg_protect1_byte |= 0x0800; + } + else + { + chg_protect1_byte &= 0xF7FF; + } + + //过压保护 +// //cell_ov+pack_ov+pf +// if((canMem[0].status_byte1 & 0x0141) != 0) +// { +// if(canMem[0].soc < 99) +// { +// chg_protect1_byte |= 0x0400; +// } +// else +// { +// chg_protect1_byte &= 0xFBFF; +// } +// } +// else +// { +// chg_protect1_byte &= 0xFBFF; +// } + + //充电低温保护 + //charge under temp + if( ((canMem[0].status_byte2 & 0x0001) !=0) || ((canMem[0].status_byte4 & 0x0404) !=0) ) + { + chg_protect1_byte |= 0x0200; + } + else + { + chg_protect1_byte &= 0xFBFF; + } + + //充电高温保护 + //charge over temp + if( ((canMem[0].status_byte2 & 0x0002) !=0) || ((canMem[0].status_byte4 & 0x0101) !=0) ) + { + chg_protect1_byte |= 0x0100; + } + else + { + chg_protect1_byte &= 0xFEFF; + } + + //MOS高温保护 + if((canMem[0].status_byte2 & 0x0100) != 0) + { + dsg_alarm_byte |= 0x0040; + } + else + { + dsg_alarm_byte &= 0xFFBF; + } + + //放电保护1 + //放电高温保护 + //discharge over temp + if( ((canMem[0].status_byte2 & 0x0008) !=0) || ((canMem[0].status_byte4 & 0x0202) !=0) ) + { + dsg_protect1_byte |= 0x4000; + } + else + { + dsg_protect1_byte &= 0xBFFF; + } + + //放电低温保护 + //discharge under temp + if( ((canMem[0].status_byte2 & 0x0004) !=0) || ((canMem[0].status_byte4 & 0x0808) !=0) ) + { + dsg_protect1_byte |= 0x2000; + } + else + { + dsg_protect1_byte &= 0xBFFF; + } + + //放电过流保护 + //discharge over current，SC, OCD1, OCD2 + if( ((canMem[0].status_byte1 & 0x042c) !=0) || ((canMem[0].status_byte2 & 0x0010) != 0) || ((canMem[0].status_byte4 & 0x0020) !=0) ) + { + dsg_protect1_byte |= 0x1000; + } + else + { + dsg_protect1_byte &= 0xEFFF; + } + + //欠压保护 + //cell_uv+pack_uv+l0v + if(((canMem[0].status_byte1 & 0x0202) != 0) || ((canMem[0].status_byte3 & 0x0008) != 0)) + { + dsg_protect1_byte |= 0x0800; + } + else + { + dsg_protect1_byte &= 0xF7FF; + } + + RequestFlag = 0x00C0; //充电允许0x0080，放电允许0x0040，不强充~0x0020 + if(chg_forbidFlg == 1)//Voltronic + { + RequestFlag &= 0xFF7F; //禁充 + } + if(dsg_forbidFlg == 1)//Voltronic + { + RequestFlag &= 0xFFBF; //禁放 + } + if(chg_forceFlg == 1)//Voltronic + { + RequestFlag |= 0x0020; //强充 + } + + + VoltronicMem.chg_alarm_byte = chg_alarm_byte; // 充电报警 + VoltronicMem.dsg_alarm_byte = dsg_alarm_byte; // 放电报警 + VoltronicMem.chg_protect1_byte = chg_protect1_byte; // 充电保护 + VoltronicMem.dsg_protect1_byte = dsg_protect1_byte; // 放电保护 + VoltronicMem.status_byte = RequestFlag; // 充放电允许 + + + //常规数据填充 + VoltronicMem.protocolType = 0x0000; + VoltronicMem.protocolVer = 0x0100; + VoltronicMem.SoftwareH = VersionMem.Software[0]<<8 | VersionMem.Software[1]; + VoltronicMem.SoftwareL = VersionMem.Software[2]<<8 | VersionMem.Software[3]; + VoltronicMem.HardwareH = VersionMem.Hardware[0]; + VoltronicMem.HardwareL = VersionMem.Hardware[1]<<8 | VersionMem.Hardware[2]; + + //实时数据 + VoltronicMem.packNum = OnlineNum; + + VoltronicMem.cellNum = bmsMem.ucCellNum; + VoltronicMem.tempNum = 6; + + //电芯电压 + for(i=0;i<16;i++) + { + VoltronicMem.cellVol[i] = bmsMem.vCell[i]/100; //电池电压 0.1V + } + //电芯温度 + VoltronicMem.T[0] = bmsMem.mcu_T1; //电池温度 0.1K + VoltronicMem.T[1] = bmsMem.mcu_T2; + VoltronicMem.T[2] = bmsMem.mcu_T3; + VoltronicMem.T[3] = bmsMem.mcu_T4; + VoltronicMem.T[4] = bmsMem.afe_T3; + VoltronicMem.T[5] = (bmsMem.afe_T1 + bmsMem.afe_T2)/2; + + if(bCHGING==1) + { + VoltronicMem.chg_packCurrent = (uint16_t)(canMem[0].cur/10); //充电电流 0.1A 2byte + VoltronicMem.dsg_packCurrent = 0; + } + else + { + VoltronicMem.dsg_packCurrent = (uint16_t)(-canMem[0].cur/10); //放电电流 0.1A 2byte + VoltronicMem.chg_packCurrent = 0; + } + VoltronicMem.packVoltage = (uint16_t)(bmsMem.packVoltage/100); //模块电压 0.1V 2byte + + //mAH /3600 + VoltronicMem.soc = canMem[0].soc; //SOC % 2byte + VoltronicMem.fccH = ((1000 * ncc_Ah * OnlineNum)>>16) & 0xFFFF; //满容量 mAH 4byte + VoltronicMem.fccL = (1000 * ncc_Ah * OnlineNum) & 0xFFFF; + VoltronicMem.rccH = ((1000 * ncc_Ah * OnlineNum * VoltronicMem.soc/100)>>16) & 0xFFFF; //剩余容量 mAH 4byte + VoltronicMem.rccL = (1000 * ncc_Ah * OnlineNum * VoltronicMem.soc/100) & 0xFFFF; + + VoltronicMem.chgVolLimit = bmsMem.inverter_chgVolLimit; //充电电压限制，上位机配置，默认值57.6V + VoltronicMem.dsgVolLimit = bmsMem.inverter_dsgVolLimit; //放电电压限制，上位机配置，默认值41.6V + + if(chg_forbidFlg == 1) + { + VoltronicMem.chgCurLimit = 0; //Voltronic禁充 + } + else if(chg_curlimitFlg == 1) + { + VoltronicMem.chgCurLimit = Inv_curlimit * (OnlineNum-chg_cur0Num); //限流40A*未保护个数 + } + else + { + VoltronicMem.chgCurLimit = bmsMem.inverter_chgCurLimit * (OnlineNum-chg_curLimitNum); //充电电流限制，上位机配置，默认值100A + } + if(dsg_forbidFlg == 1) + { + VoltronicMem.dsgCurLimit = 0; //Voltronic禁放 + } + else + { + VoltronicMem.dsgCurLimit = bmsMem.inverter_dsgCurLimit * (OnlineNum-dsg_curLimitNum); //放电电流限制，上位机配置，默认值100A + } + + + VoltronicMem.cellNum2 = bmsMem.ucCellNum; + VoltronicMem.tempNum2 = 6; + + //各种状态位，0xF0表示未实现 + for(i=0;i<10;i++) + { + VoltronicMem.Vol_status[i]=0xF0; + } + for(i=0;i<5;i++) + { + VoltronicMem.T_status[i]=0xF0; + } + for(i=0;i<10;i++) + { + VoltronicMem.other_status[i]=0xF0; + } + +} + +//COSUPER 古顶 +void MOD_Protocol_COSUPER(void) +{ + uint8_t i; + uint16_t protectByte = 0; //0x0000-0xFFFF + uint16_t alarmByte = 0; + uint16_t statusByte = 0; + + + //保护 +// //单体过压保护 +// //cell_ov+pack_ov+pf +// if(((canMem[0].status_byte1 & 0x0001) != 0) || ((canMem[0].status_byte1 & 0x0040) != 0)) +// { +// if(canMem[0].soc < 99) +// { +// alarmByte |= 0x0001; +// } +// else +// { +// alarmByte &= 0xFFFE; +// } +// } +// else +// { +// alarmByte &= 0xFFFE; +// } + + //单体欠压保护 + //cell_uv+pack_uv+l0v + if(((canMem[0].status_byte1 & 0x0002) != 0) || ((canMem[0].status_byte3 & 0x0008) != 0)) + { + alarmByte |= 0x0002; + } + else + { + alarmByte &= 0xFFFD; + } + +// //总体过压保护 +// if((canMem[0].status_byte1 & 0x0100) != 0) +// { +// alarmByte |= 0x0004; +// } +// else +// { +// alarmByte &= 0xFFFB; +// } + + //总体欠压保护 + if((canMem[0].status_byte1 & 0x0200) != 0) + { + alarmByte |= 0x0008; + } + else + { + alarmByte &= 0xFFF7; + } + + //充电过流保护 + //charge over current + if( ((canMem[0].status_byte1 & 0x0010) != 0) || ((canMem[0].status_byte4 & 0x0010) != 0)) + { + protectByte |= 0x0010; + } + else + { + protectByte &= 0xFFEF; + } + + //放电过流保护 + //discharge over current，SC, OCD1, OCD2 + if( ((canMem[0].status_byte1 & 0x042c) != 0) || ((canMem[0].status_byte2 & 0x0010) != 0) || ((canMem[0].status_byte4 & 0x0020) != 0)) + { + protectByte |= 0x0020; + } + else + { + protectByte &= 0xFFDF; + } + + //充电高温保护 + //charge over temp 高温 + if( ((canMem[0].status_byte2 & 0x0002) !=0) || ((canMem[0].status_byte4 & 0x0101) !=0) ) + { + protectByte |= 0x0100; + } + else + { + protectByte &= 0xFEFF; + } + + //放电高温保护 + //discharge over temp + if( ((canMem[0].status_byte2 & 0x0008) !=0) || ((canMem[0].status_byte4 & 0x0202) !=0) ) + { + protectByte |= 0x0200; + } + else + { + protectByte &= 0xFDFF; + } + + //充电低温保护 + //charge under temp 低温 + if( ((canMem[0].status_byte2 & 0x0001) !=0) || ((canMem[0].status_byte4 & 0x0404) !=0) ) + { + protectByte |= 0x0400; + } + else + { + protectByte &= 0xFBFF; + } + + //放电低温保护 + //discharge under temp + if( ((canMem[0].status_byte2 & 0x0004) !=0) || ((canMem[0].status_byte4 & 0x0808) !=0) ) + { + protectByte |= 0x0800; + } + else + { + protectByte &= 0xF7FF; + } + + //环境低温保护 0x4000 + if((canMem[0].status_byte4 & 0x0C00) !=0) //环境充放电低温 + { + protectByte |= 0x4000; + } + else + { + protectByte &= 0xBFFF; + } + + //环境高温保护 0x2000 + if((canMem[0].status_byte4 & 0x0300) !=0) //环境充放电高温 + { + protectByte |= 0x2000; + } + else + { + protectByte &= 0xDFFF; + } + + //MOS高温保护 0x1000 + if((canMem[0].status_byte2 & 0x0300) !=0) //MOS充放电高温 + { + protectByte |= 0x1000; + } + else + { + protectByte &= 0xEFFF; + } + + + //告警 +// //单体过压告警 +// //cell_ov+pack_ov+pf +// if((canMem[0].status_byte3 & 0x0100) != 0) +// { +// if(canMem[0].soc < 99) +// { +// alarmByte |= 0x0001; +// } +// else +// { +// alarmByte &= 0xFFFE; +// } +// } +// else +// { +// alarmByte &= 0xFFFE; +// } + + //单体欠压告警 + //cell_uv+pack_uv+l0v + if((canMem[0].status_byte3 & 0x0200) != 0) + { + alarmByte |= 0x0002; + } + else + { + alarmByte &= 0xFFFD; + } + +// //总体过压告警 +// if((canMem[0].status_byte3 & 0x0400) != 0) +// { +// alarmByte |= 0x0004; +// } +// else +// { +// alarmByte &= 0xFFFB; +// } + + //总体欠压告警 + if((canMem[0].status_byte3 & 0x0800) != 0) + { + alarmByte |= 0x0008; + } + else + { + alarmByte &= 0xFFF7; + } + + //充电过流告警 + //charge over current + if((canMem[0].status_byte3 & 0x1000) != 0) + { + alarmByte |= 0x0010; + } + else + { + alarmByte &= 0xFFEF; + } + + //放电过流告警 + //discharge over current，SC, OCD1, OCD2 + if((canMem[0].status_byte3 & 0x0200) != 0) + { + alarmByte |= 0x0020; + } + else + { + alarmByte &= 0xFFDF; + } + + //充电高温告警 + //charge over temp 高温 + if( ((canMem[0].status_byte2 & 0x1100) !=0) || ((canMem[0].status_byte4 & 0x1000) !=0) ) + { + alarmByte |= 0x0100; + } + else + { + alarmByte &= 0xFEFF; + } + + //放电高温告警 + //discharge over temp + if( ((canMem[0].status_byte2 & 0x2200) !=0) || ((canMem[0].status_byte4 & 0x2000) !=0) ) + { + alarmByte |= 0x0200; + } + else + { + alarmByte &= 0xFDFF; + } + + //充电低温告警 + //charge under temp 低温 + if( ((canMem[0].status_byte2 & 0x4400) !=0) || ((canMem[0].status_byte4 & 0x4000) !=0) ) + { + alarmByte |= 0x0400; + } + else + { + alarmByte &= 0xFBFF; + } + + //放电低温告警 + //discharge under temp + if( ((canMem[0].status_byte2 & 0x8800) !=0) || ((canMem[0].status_byte4 & 0x8000) !=0) ) + { + alarmByte |= 0x0800; + } + else + { + alarmByte &= 0xF7FF; + } + + //环境低温告警 0x4000 + if((canMem[0].status_byte4 & 0xC000) !=0) //环境充放电低温 + { + alarmByte |= 0x4000; + } + else + { + alarmByte &= 0xBFFF; + } + + //环境高温告警 0x2000 + if((canMem[0].status_byte4 & 0x3000) !=0) //环境充放电高温 + { + alarmByte |= 0x2000; + } + else + { + alarmByte &= 0xDFFF; + } + + //MOS高温告警 0x1000 + if((canMem[0].status_byte2 & 0x3000) !=0) //MOS充放电高温 + { + alarmByte |= 0x1000; + } + else + { + alarmByte &= 0xEFFF; + } + + + SRNEMem.protect_byte = protectByte; //保护标志 Hex 2byte + SRNEMem.alarm_byte = alarmByte; //告警标志 Hex 2byte + + //状态位赋值 + if(bCHGING == 1) //充电 + { + statusByte |= 0x0100; + } + else + { + statusByte &= 0xFEFF; + } + if(bDSGING == 1) //放电 + { + statusByte |= 0x0200; + } + else + { + statusByte &= 0xFDFF; + } + if((canMem[0].status_byte3 & 0x02) !=0) //充电MOS状态 + { + statusByte |= 0x0400; + } + else + { + statusByte &= 0xFBFF; + } + if((canMem[0].status_byte3 & 0x01) !=0) //放电MOS状态 + { + statusByte |= 0x0800; + } + else + { + statusByte &= 0xF7FF; + } + SRNEMem.status_byte = statusByte; //状态/故障标志 Hex 2byte + + + SRNEMem.balanceStatus = bmsMem.balanceStatus;//平衡状态 Hex 2byte + + + SRNEMem.packCurrent = (int16_t)(canMem[0].cur); //电流 10mA 2byte + SRNEMem.packVoltage = (uint16_t)(bmsMem.packVoltage/10); //电池组电压 10mA 2byte + + SRNEMem.soc = (uint8_t)canMem[0].soc; //SOC % 2byte + SRNEMem.soh = (uint8_t)canMem[0].soh; //SOH % 2byte + + SRNEMem.fcc = 100 * ncc_Ah * OnlineNum; //满容量 10mAH 2byte + SRNEMem.rcc = 100 * ncc_Ah * OnlineNum * SRNEMem.soc/100; //剩余容量 10mAH 2byte + + + //电芯电压 + if( bmsMem.ucCellNum == 8) //板子设定为8串 + { + for(i=0;i<8;i++) + { + SRNEMem.vCell[i] = bmsMem.vCell[i]; //电池电压 mV 32byte + } + for(i=0;i<8;i++) + { + SRNEMem.vCell[8+i] = bmsMem.vCell[i]; //电池电压 mV 32byte + } + } + else //其他默认为16串 + { + for(i=0;i<16;i++) + { + SRNEMem.vCell[i] = bmsMem.vCell[i]; //电池电压 mV 32byte + } + } + + //电芯温度 + SRNEMem.Tcell[0] = (int16_t)(bmsMem.mcu_T1-2731); //电池温度 0.1℃ 8byte + SRNEMem.Tcell[1] = (int16_t)(bmsMem.mcu_T2-2731); + SRNEMem.Tcell[2] = (int16_t)(bmsMem.mcu_T3-2731); + SRNEMem.Tcell[3] = (int16_t)(bmsMem.mcu_T4-2731); + + SRNEMem.afe_MOS = (int16_t)((bmsMem.afe_T1 + bmsMem.afe_T2)/2 - 2731); //MOS温度 0.1℃ 2byte 对应上下MOS的温度平均值 + SRNEMem.afe_MCU = (int16_t)(bmsMem.afe_T3-2731); //环境温度 0.1℃ 2byte 对应MCU芯片温度 + + //充放电电流限制需要有符号区别吗？ + SRNEMem.chgVolLimit = bmsMem.inverter_chgVolLimit; //充电电压限制，上位机配置，默认值57.6V + //SRNEMem.dsgVolLimit = bmsMem.inverter_dsgVolLimit; //放电电压限制，上位机配置，默认值41.6V + + if(chg_forbidFlg == 1) + { + SRNEMem.chgCurLimit = 0; //COSUPER禁充 + } + else if(chg_curlimitFlg == 1) + { + SRNEMem.chgCurLimit = Inv_curlimit * (OnlineNum-chg_cur0Num); //限流40A*未保护个数 + } + else + { + SRNEMem.chgCurLimit = bmsMem.inverter_chgCurLimit * (OnlineNum-chg_curLimitNum); //充电电流限制，上位机配置，默认值100A + } + if(dsg_forbidFlg == 1) + { + SRNEMem.dsgCurLimit = 0; //COSUPER禁放 + } + else + { + SRNEMem.dsgCurLimit = bmsMem.inverter_dsgCurLimit * (OnlineNum-dsg_curLimitNum); //放电电流限制，上位机配置，默认值100A + } + +} + +//SMK +void MOD_Protocol_SMK(void) +{ + RequestFlag = 0x0060; //充电允许0x0040，放电允许0x0020，不强充~0x1000 + if(chg_forbidFlg == 1)//SMK + { + RequestFlag &= 0xFFBF; //禁充 + } + if(dsg_forbidFlg == 1)//SMK + { + RequestFlag &= 0xFFDF; //禁放 + } + if(chg_forceFlg == 1)//SMK + { + RequestFlag |= 0x1000; //强充 + } + + SMKMem.status_byte = RequestFlag; //状态：bit6充电禁止bit5放电禁止 + SMKMem.soc = (uint8_t)canMem[0].soc; //SOC % 2byte + SMKMem.rcc = 100 * ncc_Ah * OnlineNum * SMKMem.soc/100;//剩余容量 10mAH 2byte + SMKMem.fcc = 100 * ncc_Ah * OnlineNum; //额定容量 10mAH 2byte + SMKMem.packVoltage = (int16_t)(bmsMem.packVoltage/10); //模块电压 10mV 2byte + SMKMem.packCurrent = (int16_t)(canMem[0].cur); //模块电流 10mA 2byte + + SMKMem.chgVolLimit = bmsMem.inverter_chgVolLimit * 10; //充电电压限制，上位机配置，默认值57.6V + if(chg_forbidFlg == 1) + { + SMKMem.chgCurLimit = 0; //SMK禁充 + } + else if(chg_curlimitFlg == 1) + { + SMKMem.chgCurLimit = Inv_curlimit * (OnlineNum-chg_cur0Num); //限流40A*未保护个数 + } + else + { + SMKMem.chgCurLimit = (bmsMem.inverter_chgCurLimit * 10) * (OnlineNum-chg_curLimitNum); //充电电流限制，上位机配置，默认值100A + } + if(dsg_forbidFlg == 1) + { + SMKMem.dcsCurLimit = 0; //SMK禁放 + } + else + { + SMKMem.dcsCurLimit = (bmsMem.inverter_dsgCurLimit * 10) * (OnlineNum-chg_curLimitNum); //放电电流限制，上位机配置，默认值100A + } + +} + +//SAKO 三科 +void MOD_Protocol_SAKO(void) +{ + MOD_Protocol_Voltronic(); +} + +//SNADI 佛山斯奈特 +void MOD_Protocol_SNADI(void) +{ + +} + +//invt 英威腾 +void MOD_Protocol_invt(void) +{ + +} + diff --git a/README/readme.txt b/README/readme.txt new file mode 100644 index 0000000..0414a2e --- /dev/null +++ b/README/readme.txt @@ -0,0 +1,5038 @@ +2022.4.19 将默认HSE-PLL 72M系统时钟改为 HSI-PLL 36M时钟 +2022.4.21 Modbus F03调试成功，注意限制长度及可靠性测试，还存在大小端问题 + +//第一阶段计划 +2022.5.11 完成CAN发送接收测试，完成上位机读写功能； +2022.5.12-2022.5.13 完成BMS 基本功能； +2022.5.14-2022.5.15 完成BMS CAN Sol-Ark 协议； +2022.5.16 整体测试； +2022.5.17 PCB发客户测试； + +//第二阶段计划 + + + +/////////////////////////////////SOC 增加部分3.17 +(GasGuage.c 130-133行) + if(bmsMem.packVoltage > 56000) + { + bmsMem.rcc = bmsMem.fcc; + } + +(GasGuage.c 151-154行) + if(bmsMem.packVoltage < 43000) + { + bmsMem.rcc = 0; + } + + +////////////////////CAN协议汇总//////////////////// +Sol-Ark +GoodWe 3.6 +Koyoe 3.16 +Aiswei 3.17 +SMA 3.21 +Sorotec 3.27 + +//////////更改 +1.固德威的温度输出修改回bmsMem.mcu_T1 + +2.添加容量传输的协议，仿真注意看一下 +Sol-Ark 0x379 +Koyoe 0x18FAD201 (后加) +Aiswei 0x379 +SMA 0x35F (后加) +Sorotec 0x35F + +3.将TxMessage[CAN_SendCount]使用更全面，避免TxMessage[1]一类 + + + +///////////屏幕第6个协议的选择相关 +void SDWA_Init(void)增加 + SDWA_DispProcotol(0x03,0x05,0x00); + +void SDWA_RecvData(void) + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x03) && (sdwaBuf[5]==0x15)) + { + if(sdwaBuf[8]==0x01) + { + if(protocol !=0x06) + protocol = 0x06; + } + else if(sdwaBuf[8]==0x00) + { + if(protocol ==0x06) + protocol = 0x00; + } + } + + +///////////Growatt CAN协议，暂放在第1页第3个，代替Koyoe协议 4.3 + +///////////并联电流，取值位置0x42 + +/////////////////////////////////放电过流保护显示4.4 +//在上位机中新增的放电过流保护功能，给定值输入给变量bmsMem.mcu_ocd +//bmsMem.temperaStatus的bit5是用来新增判断放电过流保护的标志位 + +SDWA.c中改动显示的判断(L538) + if( ((bmsMem.bStatus1 & 0x0c) != 0) || ((bmsMem.temperaStatus & 0x20) != 0) ) + //放电过流报警的屏幕代码 A5 5A 05 82 01 94 00 01 + +AFE_SH367309.c改动报警判断(L566) +void AFE_ProtectProcess(void) +将bmsMem.temperaStatus & 0x0f改为0x2f + if( ( (bmsMem.bStatus1 & 0x7f)!=0) || ( (bmsMem.bStatus2 & 0x0f) !=0) || ((bmsMem.bStatus3 & 0x18) !=0) || (bmsMem.temperaStatus & 0x2f) !=0) + +can.c改动报警判断 +(L158 - Sol-Ark) + if( ((bmsMem.bStatus1 & 0x2c) !=0) || ((bmsMem.temperaStatus & 0x20) !=0) ) +(L461 - GoodWe) + if( ((bmsMem.bStatus1 & 0x2c) !=0) || ((bmsMem.temperaStatus & 0x20) !=0) ) +(L867 - Growatt) + if( ((bmsMem.bStatus1 & 0x2c) !=0) || ((bmsMem.temperaStatus & 0x20) !=0) ) +(L1231 - Aiswei) + if( ((bmsMem.bStatus1 & 0x2c) !=0) || ((bmsMem.temperaStatus & 0x20) !=0) ) +(L1603 - SMA) + if( ((bmsMem.bStatus1 & 0x2c) !=0) || ((bmsMem.temperaStatus & 0x20) !=0) ) +(L1892 - Sorotec) + if( ((bmsMem.bStatus1 & 0x2c) !=0) || ((bmsMem.temperaStatus & 0x20) !=0) ) + +/////////////////////////////////充电过流保护显示4.4 +//在上位机中新增的充电过流保护功能，给定值输入给变量bmsMem.mcu_occ +//bmsMem.temperaStatus的bit4是用来新增判断充电过流保护的标志位 + +SDWA.c中改动显示的判断(L538) + if( ((bmsMem.bStatus1 & 0x10) !=0) || ((bmsMem.temperaStatus & 0x10) !=0) ) + //充电过流报警的屏幕代码 A5 5A 05 82 01 94 00 01 + +AFE_SH367309.c改动报警判断(L566) +void AFE_ProtectProcess(void) +将bmsMem.temperaStatus & 0x2f改为0x3f + if( ( (bmsMem.bStatus1 & 0x7f)!=0) || ( (bmsMem.bStatus2 & 0x0f) !=0) || ((bmsMem.bStatus3 & 0x18) !=0) || (bmsMem.temperaStatus & 0x3f) !=0) + +can.c改动报警判断 +(L210 - Sol-Ark) + if( ((bmsMem.bStatus1 & 0x10) !=0) || ((bmsMem.temperaStatus & 0x10) !=0) ) +(L513 - GoodWe) + if( ((bmsMem.bStatus1 & 0x10) !=0) || ((bmsMem.temperaStatus & 0x10) !=0) ) +(L858 - Growatt) + if( ((bmsMem.bStatus1 & 0x10) !=0) || ((bmsMem.temperaStatus & 0x10) !=0) ) +(L1283 - Aiswei) + if( ((bmsMem.bStatus1 & 0x10) !=0) || ((bmsMem.temperaStatus & 0x10) !=0) ) +(L1614 - SMA) + if( ((bmsMem.bStatus1 & 0x10) !=0) || ((bmsMem.temperaStatus & 0x10) !=0) ) +(L1903 - Sorotec) + if( ((bmsMem.bStatus1 & 0x10) !=0) || ((bmsMem.temperaStatus & 0x10) !=0) ) + +/////////////////////////////////过流延时恢复功能4.4 +【adc.c】(L348) + if( (bmsMem.temperaStatus & BIT4) !=0 || (bmsMem.temperaStatus & BIT5) !=0 ) + + +/////////////////////////////////DIDO中断MOS 4.20 +//1.【gpio.c】修改PB15的定义变量名，把初始化改为输入脚 +(L35) +#define PIN_DIDO GPIO_Pin_15 //一键开关MOS +(L250) + //DIDO + GPIO_InitStructure.GPIO_Pin = PIN_DIDO; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; + +//2.【gpio.c】将原主动均衡功能改为PA8引脚，初始化改为输出脚，输出信号启动主动均衡板 +(L24) +#define PIN_BAL_OUT GPIO_Pin_8 //主动均衡板启动信号，高电平启动 +(L257) + //BAL + GPIO_InitStructure.GPIO_Pin = PIN_BAL_OUT; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; +(L255->L261) + GPIO_ResetBits(GPIOA, PIN_BAL_OUT); //将原来初始化PIN_BAL时置0的操作移动给现在的引脚 +(L161\L166)//从PB15到PA8 + GPIO_SetBits(GPIOA, PIN_BAL_OUT); + GPIO_ResetBits(GPIOA, PIN_BAL_OUT); + +//3.增加对DIDO口的反应 +【global.h】(L401) +//DIDO +extern uint8_t DIDO(void);//4.17新增一键开关MOS +extern void DIDO_TIM_Moni(void); +【gpio.c】 +(L43) +uint8_t DIDOMoniCount = 0; +(L198) +//DIDO(PB15) 输入-按下是0 +uint8_t DIDO(void) +{ + uint8_t status; + status = GPIO_ReadInputDataBit(GPIOB,PIN_DIDO); + + return status; +} +void DIDO_TIM_Moni(void) // 通过改变tmperaStatus标志的bit6来控制MOS +{ + (略) +} + +//4.【AFE_SH367309.c】只亮报警灯不跳转屏幕的判断条件增加bit6(L583) + else if( (bmsMem.temperaStatus & 0x40) !=0) + { + LED_ALARM_On(); + } + +//5.10ms中断速度太快，需特意改为只执行一次输出置高或置低 +【global.h】(L404) +extern void DIDO_CTRL_On(void); +extern void DIDO_CTRL_Off(void); +【gpio.c】 +(L44) +uint8_t DIDOFlag = 0; +(L150) +void DIDO_CTRL_On(void) +{ + if(DIDOFlag == 1) + { + GPIO_SetBits(GPIOB, PIN_CTLC); + DIDOFlag=0; + } +} + +void DIDO_CTRL_Off(void) +{ + if(DIDOFlag == 0)//初始为0，当执行一次关MOS后就置为1，使引脚只控制1次 + { + GPIO_ResetBits(GPIOB, PIN_CTLC); + DIDOFlag=1; + } +} + +//6.AFE控制函数void AFE_Ctrl(void)分化为中断内执行函数和主循环执行函数 +【global.h】(L406) +extern void DIDO_Ctrl(void); + +【AFE_SH367309.c】(L427) +void DIDO_Ctrl(void)//10ms中断 +{ + if((bmsMem.temperaStatus & 0x3f) == 0) //不能影响BIT0-5功能的运作 + { + (略) + } +} +void AFE_Ctrl(void)//主循环1s +{ + if((bmsMem.temperaStatus & 0x40) == 0) //不能影响BIT6功能的运作 + { + (略) + } +} + +//7.【tim.c】void TIM3_IRQHandler(void)增加 + DIDO_TIM_Moni(); + + DIDO_Ctrl(); + + +////////////////////SOC判0 4.21 +【GasGauge.c】(L156) + if(bmsMem.packVoltage < 43000) + { + bmsMem.rcc = 0; + } + + +////////////////////FLASH写入默认值的修改 4.23 +【global.c】(L70) + bmsMem.E2uiDsgEndVol = 2500; + +【flash.c】(L92-97/L138-143) + 0xEE, //过压保护电压 3750mV + 0x62, + 0xC6, //过压保护释放 3550mV + 0x7D, //欠压保护电压 2500mV + 0x87, //欠压保护释放 2700mV + 0xAF, //平衡开启电压 3500mV + + +/////////////////////////////////增加显示屏CAN协议选择共4页33项 4.26 +void CAN_UpdateData(void) +增加若干项 + else if(protocol_Index == 7){} + +void SDWA_Init(void) +注意修改中间的判断条件，增加若干项 + SDWA_DispProcotol(0x03,0x06,0x00); + +void SDWA_RecvData(void) +增加若干项 + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x03) && (sdwaBuf[5]==0x16)) + { + if(sdwaBuf[8]==0x01) + { + if(protocol !=0x07) + protocol = 0x07; + } + else if(sdwaBuf[8]==0x00) + { + if(protocol ==0x07) + protocol = 0x00; + } + } + + +////////////////////屏幕急停 4.28 +【L690】void SDWA_UpdateData(void) + if( (bmsMem.temperaStatus & 0x40) !=0) + { + SDWA_Send_VAR(0x0100, 5); + } + else + { + if(bCHGING ==1) + { + //SDWA_Send_Charging(0x0100); + SDWA_Send_VAR(0x0100, 0); + } + else + { + //SDWA_Send_Discharging(0x0100); + SDWA_Send_VAR(0x0100, 1); + } + } + + +////////////////////温度差保护 5.12 +【adc.c】 +(L59) +uint8_t Tdifference_count; + +(L113) + int16_t T[4]; + uint8_t i; + uint16_t max,min; + +(L158) + //计算电芯温度最大最小值 + T[0] = bmsMem.mcu_T1; + T[1] = bmsMem.mcu_T2; + T[2] = bmsMem.mcu_T3; + T[3] = bmsMem.mcu_T4; + max = T[0]; + min = T[0]; + for(i=0;i<4;i++) + { + if(maxT[i]) + { + min = T[i]; + } + } + +(L177) + //温差报警 + if((bmsMem.temperaStatus & BIT7) ==0) + { + if( (max-min)>100 ) //温差超过100*0.1摄氏度 + { + Tdifference_count++; + if(Tdifference_count> 3) + { + bmsMem.temperaStatus |= BIT7; //连续发生低温，保护 + Tdifference_count = 0; + } + } + else + { + Tdifference_count = 0; + } + } + +(L405) + //温差保护释放 + if((bmsMem.temperaStatus & BIT7) !=0) + { + if( (max-min)<100 ) //温差不再超过100*0.1摄氏度，确认3遍后执行释放 + { + Tdifference_count++; + if(Tdifference_count > 3) + { + bmsMem.temperaStatus &= ~BIT7; //连续发生低温，保护 + Tdifference_count = 0; + } + } + else + { + Tdifference_count = 0; + } + } + +【AFE_SH367309.c】添加新报警判断-只让报警灯亮，而且不影响其他报警显示 +//注意当温差保护时，报警灯亮但是屏幕不显示"Fault"字样 +void AFE_ProtectProcess(void) +(L603) +else if( (bmsMem.temperaStatus & 0xC0) !=0) + + +/////////////////////////////////上位机改变通信地址5.15 +1.将bmsMem更新，多加两个变量，此时叠加电流的地址42变为43【需要测试】 +【golbal.h】(L282) + //20230411--------------- + uint8_t mcu_address; //通过上位机改变板子的通信地址 + uint8_t addr_crc; + //20230411--------------- +【RS485_Modbus.c】(L471) + modbusBuf[3] = 0x43; + +2.SDWA新增，进行通信位改变 +【SDWA.c】(L737) + if(bmsMem.mcu_address !=0) + { + EEPROM_WrMulByte(0,0,1,&bmsMem.mcu_address); + delay_ms(5); + + bmsMem.E2_485Addr = bmsMem.mcu_address; + bmsMem.mcu_address = 0; + } + + +/////////////////////////////////上位机修改电池容量显示5.23 +【global.h】(L287) + //20230523--------------- + uint8_t writeCapacity; //通过上位机改变电池容量显示 + uint8_t capacity_crc; + //20230523--------------- +【RS485_Modbus.c】(L471) + modbusBuf[3] = 0x44; +【GasGauage.c】 +void InitGasGauge(void)(L34) + uint8_t tmpRd; + EEPROM_RdMulByte(7,1,1,&tmpRd); + bmsMem.fcc = 3600 * 1000*tmpRd; + +// bmsMem.fcc = 3600 * 100000; //系统满充容量暂定100AH = 100,000mAH = 360,000,000mAS + +void GaugeManage(void)(L126) //写入的Ah容量存放在EEPROM内 + if(bmsMem.writeCapacity !=0) + { + EEPROM_WrMulByte(7,1,1,&bmsMem.writeCapacity); + delay_ms(5); + + bmsMem.fcc = 3600 * 1000*bmsMem.writeCapacity; + bmsMem.writeCapacity = 0; + } +(L152) + bmsMem.rcc = bmsMem.fcc - bmsMem.fcc/100; +(L178) + bmsMem.rcc = bmsMem.fcc/100; + + +/////////////////////////////////主机与上位机通信，冲突时上位机优先级更高 +【RS485_Modbus.c】 +(L241) + else if((modbusBuf[0] == bmsMem.E2_485Addr) && (modbusBuf[1] == 0x03) ) //读数据处理 + { + MODBUS_F03_Rx(MODBUS_MEM_PT); + } + else if((modbusBuf[0] == bmsMem.E2_485Addr) && (modbusBuf[1] == 0x10) ) //写数据处理 + { + MODBUS_F10_Rx(MODBUS_MEM_PT); + } + else if((modbusBuf[0] == bmsMem.E2_485Addr) && (modbusBuf[1] == 0xaa) ) //CADC零点校准处理 + { + MODBUS_Faa_Rx(MODBUS_MEM_PT); + } + else if((modbusBuf[0] == bmsMem.E2_485Addr) && (modbusBuf[1] == 0xbb) ) //CADC增益校准处理 + { + MODBUS_Fbb_Rx(MODBUS_MEM_PT); + } + else + { + MODBUS_Init(); //没加这个时，换地址通讯连接不上，待监控时间到重新初始化之后才恢复连接 + } +(L489) + //如果主机在发送阶段收到了数据，说明有上位机在总线上请求数据，此时延后200ms再发送 + if(modbusBufIndex > 2) + { + delay_ms(200); + } + + +//////////代码量太大，修改优化编译等级level0 -> level3 + + +////////////////////MUST逆变器通讯通讯速率为100K 5.6 +void uf_CAN1_Init(void)程序下修改 +原： +CAN_InitStructure.CAN_Prescaler = 8; //36MHz/8/(1+6+2)=500kbs +改： +if(Protocol != 7) +CAN_InitStructure.CAN_Prescaler = 40; //36MHz/40/(1+6+2)=100kbs + +////////////////////SOFAR逆变器协议更新 6.5 + + + + +////////////////////增加网口1的Modbus协议-硕日//////////////////// +上位机/主从机功能：PA9、PA10 (USART1) +网口1：PB10、PB11 (USART3) +**********第1步 移植相关函数********** +【uart.c】 +void uf_UART3_Init( u32 bound ) +void USART3_SendMulByte(uint8_t *p, uint8_t size) +void USART3_IRQHandler(void) +【tim.c】在TIM4_IRQHandler函数中增加 +(L95)MODBUS1_IT_TIMUpdate(); +【main.c】在main函数中增加 +(L63)MODBUS1_Init(); +(L132)MODBUS1_IQ_Transmit(); +(L120)Protocol_UpdateData(); +【global.h】(L453) +//Modbus1 新加 +extern void uf_UART3_Init( u32 bound ); +extern void USART3_SendMulByte(uint8_t *bufPT, uint8_t size); +extern void MODBUS1_IT_Receive(void); +extern void MODBUS1_IQ_Transmit(void); +extern void MODBUS1_IT_TIMUpdate(void); +extern void MODBUS1_F03_Rx(uint8_t *mem); +extern void MODBUS1_Init(void); +extern void Protocol_UpdateData(void); +【RS485_Modbus_Inverter.c】加入工程下文件夹MOUDLE + +**********第2步 起始地址到一个新的类中，参数按照bmsMem的来********** +【global.h】新建结构体 +(L315)typedef struct{}PROTOCOL_SENE_MEMORY ; +extern PROTOCOL_SENE_MEMORY SENEMem; +【global.c】 +(L21)PROTOCOL_SENE_MEMORY SENEMem; + + +////////////////////增加网口1的Modbus协议-日月元//////////////////// +**********第1步 结构体放入********** +【global.h】新建结构体 +(L348)typedef struct{}PROTOCOL_VOLTRONIC_MEMORY ; +(L448)extern PROTOCOL_VOLTRONIC_MEMORY VoltronicMem; +【global.c】 +(L22)PROTOCOL_VOLTRONIC_MEMORY VoltronicMem; +【RS485_Modbus_Inverter.c】 +(L12)#define MODBUS1_VoltronicMEM_PT (uint8_t *)&VoltronicMem.rsvd1[0] +**********第2步 数据更新的选择框架放入********** +【RS485_Modbus_Inverter.c】 +extern uint8_t protocol; +//Modbus协议数据更新 +void Protocol_UpdateData(void) +{ + if(protocol == 13) MOD_Protocol_SENE(); + else if(protocol == 14) MOD_Protocol_Voltronic(); +} +//SENE 硕日 +void MOD_Protocol_SENE(void)(略) +**********第3步 网口1输出的起始地址改动********** +void MODBUS1_IT_TIMUpdate(void) +(L115) + if(protocol == 13) MODBUS1_F03_Rx(MODBUS1_SENEMEM_PT); + else if(protocol == 14) MODBUS1_F03_Rx(MODBUS1_VoltronicMEM_PT); + + +////////////////////增加网口1的Modbus协议-华倚太//////////////////// +**********第1步 结构体放入********** +【global.h】新建结构体 +(L399)typedef struct{}PROTOCOL_WAET_MEMORY ; +(L500)extern PROTOCOL_WAET_MEMORY WAETMem; +【global.c】 +(L23)PROTOCOL_WAET_MEMORY WAETMem; +【RS485_Modbus_Inverter.c】 +(L13)#define MODBUS1_WAETMEM_PT (uint8_t *)&WAETMem.rsvd1[0] +**********第2步 数据更新的选择框架放入********** +【RS485_Modbus_Inverter.c】 +void Protocol_UpdateData(void) + else if(protocol == 15) MOD_Protocol_WAET(); +void MOD_Protocol_WAET(void) +(略) +**********第3步 网口1输出的起始地址改动********** +void MODBUS1_IT_TIMUpdate(void) + else if(protocol == 15) MODBUS1_F03_Rx(MODBUS1_WAETMEM_PT); + + +////////////////////增加网口1的Modbus协议-三科//////////////////// +**********第1步 结构体放入********** +【global.h】新建结构体 +(L399)typedef struct{}PROTOCOL_SAKO_MEMORY ; +(L500)extern PROTOCOL_SAKO_MEMORY WAETMem; +【global.c】 +(L23)PROTOCOL_SAKO_MEMORY WAETMem; +【RS485_Modbus_Inverter.c】 +(L13)#define MODBUS1_SAKOMEM_PT (uint8_t *)&SAKOMem.rsvd1[0] +**********第2步 数据更新的选择框架放入********** +【RS485_Modbus_Inverter.c】 +void Protocol_UpdateData(void) + else if(protocol == 31) MOD_Protocol_SAKO(); +void MOD_Protocol_SAKO(void) +(略) +**********第3步 网口1输出的起始地址改动********** +void MODBUS1_IT_TIMUpdate(void) + else if(protocol == 31) MODBUS1_F03_Rx(MODBUS1_SAKOMEM_PT); + + +////////////////////容量显示不对，会将原有未写入容量的板子识别为255 +void InitGasGauge(void)(L33) + uint8_t tmpRd; + + EEPROM_RdMulByte(7,1,1,&tmpRd); + + if(tmpRd>0 && tmpRd<255) //如果之前写过容量值,就按照之前的值显示，否则显示100Ah + { + bmsMem.fcc = 3600 * 1000*tmpRd; + } + else + { + bmsMem.fcc = 3600 * 100000; //系统满充容量暂定100AH = 100,000mAH = 360,000,000mAS + tmpRd = 100; + EEPROM_WrMulByte(7,1,1,&tmpRd); + } + + +////////////////////485网口1的升级功能 +当网口1收到报文 +清除最后一PAGE回到IAP程序 +【RS485_Modbus_Inverter.c】 +(L134) +/******************************* +******* 清空PAGE存放信息 ******* +** M: A7 55 0f 02 03 04 5A A5 ** +** S: A7 65 0f 02 03 04 5A A5 ** +********************************/ +void MODBUS1_F0f_Rx(void) +{ + BYTE2 crc16; + + //CRC判断 + crc16 = CRC16_Cal_Inverter(modbus1Buf, 6); +// if( (modbus1Buf[7] == crc16.b8[1]) || (modbus1Buf[6] == crc16.b8[0]) ) + if( (modbus1Buf[7] == 0XA5) || (modbus1Buf[6] == 0X5A) ) + { + //1. + FLASH_Unlock(); //解锁 + FLASH_ErasePage(FLASH_PAGE_ADDR); //擦除Flash的最后一page,0x0800FC00-0x0800FFFF + FLASH_Lock();//上锁 + + //2. + //FLASH_WrData(FLASH_PAGE_ADDR,0,8); + + /*回送接收正确信号到PC*/ + modbus1Buf[0] = 0xA7; + modbus1Buf[1] = 0X65; + modbus1Buf[2] = 0X03; + modbus1Buf[3] = 0X02; + modbus1Buf[4] = 0X03; + modbus1Buf[5] = 0X04; + modbus1Buf[6] = 0X5A; + modbus1Buf[7] = 0XA5; + + modbus1F0fRxFlg = 1; + MODBUS1_UART_IT_RX_DISABLE; + } +} + +(L18) +#define FLASH_PAGE_ADDR 0x0800FC00//要擦除的FLASH页地址 + +(L22) +uint8_t modbus1F0fRxFlg; //升级信息接收正确标记 + +(L135) +else //485从机 + { + if(modbus1BufIndex > 2) + { + if((modbus1Buf[0] == 0xA7) && (modbus1Buf[1] == 0x55)) + { + MODBUS1_F0f_Rx(); //485升级操作 + } + else + { + MODBUS1_Init(); //没加这个时，换地址通讯连接不上，待监控时间到重新初始化之后才恢复连接 + } + } + else + { + MODBUS1_Init(); + } + } + +(L101) + if(modbus1FffRxFlg == 1) + { + modbus1FffRxFlg = 0; + modbus1BufIndex = 0; + MODBUS1_UART_SendMulByte(modbus1Buf, 8); + MODBUS1_UART_IT_RX_ENABLE; + + delay_ms(1000); + NVIC_SystemReset(); //软件复位 + } + else + +【global.h】(L667) +extern void MODBUS1_F0f_Rx(void); + +//接收清除PAGE指令并回复，测试成功 + + +//////////为方便测试需要，程序均取消了以下改动，注意发货前要修改 +0x8000000 ——> 0x8001000 +SCB->VTOR = FLASH_BASE | 0x1000; +$K\ARM\ARMCC\bin\fromelf.exe --bin --output=Bin\@L.bin !L + + +////////////////////上位机修改限流值 +//原来变量 +#define CHG_LIMIT_VALUE 120000 //单位A， 出厂设100A +#define CHG_LIMIT_COUNT 5 //过流5S, 启动限流模块 +#define CHG_LIMIT_RELEASE_COUNT 600 //限流模块工作60S, 恢复主充电 //出厂设600S + +（为统一命名，将先前的 +bmsMem.mcu_address改为bmsMem.write_Addr +bmsMem.writeCapacity改为bmsMem.write_Capacity) + +//新加上 +【global.h】(L290) + //20230614--------------- + uint8_t write_CHGLimit_Value; //通过上位机改变限流板保护电流 A + uint8_t write_CHGLimit_Count; //通过上位机改变限流板保护时间 S + uint16_t write_CHGLimit_ReleaseCount; //通过上位机改变限流板保护恢复时间 S + //20230614--------------- + +【AFE_SH367309.c】 +void CHG_LIMIT_Ctrl(void) +//CHG_LIMIT_VALUE -> bmsMem.write_CHGLimit_Value +//CHG_LIMIT_COUNT -> bmsMem.write_CHGLimit_Count +//CHG_LIMIT_RELEASE_COUNT -> bmsMem.write_CHGLimit_ReleaseCount + +【flash.c】 +(L132)/(L185) + //20230614 + 100, //保护电流 + 5, //保护时间 + 0x58, //保护释放时间 0x0258 = 600 + 0x02, + +uint8_t MEMORY_UpdateFlash(uint32_t addr) +//40改为44，一共2处 +//20改为22，一共1处 +uint8_t FLASH_ReadCheck(uint32_t addr) +//40改为44，一共3处 + + +////////////////////满充判定条件的总电压值，根据上位机的AFE配置决定 +if(bmsMem.packVoltage > 56000) //3.5*16 //3.75*num -4 +if(bmsMem.packVoltage < 43000) //2.6875*16 //2.5*num +3 + +原计算方式： +固定值56V = 单芯3.5V * 串数16 +固定值43V = 单芯2.6875V * 串数16 + +新计算方式： +[模块内个数cellNum] +cellNum = bmsMem.ee_sconf1 & 0x0F; +if( cellNum < 5 ) //其他代表16串，一般是0000 +{ + cellNum = 16; +} +[单体过压值cell_OV] = ( (bmsMem.ee_ovt_ldrt_ovh & 0x03) <<8 | bmsMem.ee_ovl ) * 5; +[单体欠压值cell_UV] = bmsMem.ee_uv * 20; +[模块过压值pack_OV] = cell_OV * cellNum -4000; +[模块欠压值pack_UV] = cell_UV * cellNum +3000; + + + + +/** 20230704增加补丁 **/ +////////////////////滤波改小为2，可监测到小电流200mA +void AFE_CurrentProcess(void) + +////////////////////最低电压 +【global.h】(L65) +extern uint8_t cellNum; //模块内个数 +【AFE_SH367309.c】(L362) +for(i=0;i CRC16_Cal +【global.h】(L677) +extern void UART_EraseIAP(void); + +//删掉 +【RS485_Modbus_Inverter.c】(L20) +uint8_t modbus1F0fRxFlg; + +//增加 +【RS485_Modbus_Inverter.c】 +(L21) +uint8_t cmdRxIapFlg; //升级信息 接收正确标记 +(L249) + cmdRxIapFlg = 0; + +//删掉 +【global.h】(L674) +extern void MODBUS1_F0f_Rx(void); +//增加 +【global.h】(L579) +extern void UART_EraseIAP(void); + +////////////////////0x44 -> 0x46 + + +/////////////////////////////////主机与上位机通信，冲突时上位机优先级更高 +【RS485_Modbus.c】 +(L467) + //如果主机在发送阶段收到了数据，说明有上位机在总线上请求数据，此时延后200ms再发送 + if(modbusBufIndex > 2) + { + delay_ms(200); + } +(L241) + else if((modbusBuf[0] == bmsMem.E2_485Addr) && (modbusBuf[1] == 0x03) ) //读数据处理 + { + MODBUS_F03_Rx(MODBUS_MEM_PT); + } + else if((modbusBuf[0] == bmsMem.E2_485Addr) && (modbusBuf[1] == 0x10) ) //写数据处理 + { + MODBUS_F10_Rx(MODBUS_MEM_PT); + } + else if((modbusBuf[0] == bmsMem.E2_485Addr) && (modbusBuf[1] == 0xaa) ) //CADC零点校准处理 + { + MODBUS_Faa_Rx(MODBUS_MEM_PT); + } + else if((modbusBuf[0] == bmsMem.E2_485Addr) && (modbusBuf[1] == 0xbb) ) //CADC增益校准处理 + { + MODBUS_Fbb_Rx(MODBUS_MEM_PT); + } + else + { + MODBUS_Init(); //没加这个时，换地址通讯连接不上，待监控时间到重新初始化之后才恢复连接 + } + + +////////////////////滤波改小为0 +void AFE_CurrentProcess(void) + + +////////////////////函数协议名写错，已改SENE -> SRNE + + +////////////////////地址1也可进行485升级 + + + + +/***** 7.14汇总 *****/ +**********主从机通信数据相关********** +*****1.MCU_TemperaProcess函数增加对最大最小温度和平均温度的计算 +//新建温度的全局变量 +int16_t TemperatureAverage; // 平均温度 +int16_t TemperatureMax; // 最高温度 +int16_t TemperatureMin; // 最低温度 +uint16_t TemperatureMaxIndex; // 最高温度序号 +uint16_t TemperatureMinIndex; // 最低温度序号 +//优化MCU_TemperaProcess函数 +//从各协议中简化相关计算： + //替换各协议中最高最低温度的取值，节约代码量 + //删除每个协议里的比大小的代码 + //替换协议函数内的局部变量名 + //在传递该函数的代码增加赋值 + //有的函数没有加can_protect_byte的相关赋值，已补全 + //统一把报警值改为总数据值 + //把所有单传温度值的通信改为平均温度 + //485类协议增加若不是地址1就只生成报警保护值的代码 + +*****2.总数据的获取： +//bmsMem.can_cur电流的单位统一0.01A +//电流输出时再根据协议要求变化 + int16_t tempCur; //总电流 + tempCur = (int16_t)(canMem[0].cur/10); //单位0.1 +//电流温度，主机获取的汇总数据可能会很大，改为int32_t类型 + int32_t cur; + int32_t temp; + canMem[1].cur = (int32_t) bmsMem.can_cur; + canMem[1].temp = (int32_t) bmsMem.can_temp; +//MODBUS_MASTER_Tx函数收集数据的代码补全 +//数据赋值就放在数据获取之后 + 电流：AFE_CurrentProcess函数 + bmsMem.can_cur = (int16_t) (bmsMem.packCurrent/10); //sum of all packs，统一数值单位0.01A + 温度：MCU_TemperaProcess函数 + bmsMem.can_temp = TemperatureAverage; //sum of all packs + SOC、SOH：GaugeManage函数 + bmsMem.can_soc = bmsMem.soc; //sum of all packs + bmsMem.can_soh = bmsMem.soh; //sum of all packs + + +**********逆变器通信协议相关********** +*****简化MUST逆变器的波特率问题 +//1.删去MUSTflag相关部分 +//2.在CAN1_Init中根据协议选择值更改 + if(protocol == 7) //MUST协议的波特率是100k + { + CAN_InitStructure.CAN_Prescaler = 40; //36MHz/8/(1+6+2)/5=100kbs + } + else //其他协议是500k + { + CAN_InitStructure.CAN_Prescaler = 8; //36MHz/8/(1+6+2)=500kbs + } + +////////////////////协议函数修改 +*****1.协议还是原来共31个选择，25个可用，但内容重新梳理一遍，全换成总数据： +//"protect_byte"的4个统一传递总数据 +//SOC统一换成平均值:bmsMem.soc -> canMem[0].soc +//SOH统一换成平均值:bmsMem.soh -> canMem[0].soh +//温度统一换成平均值:TemperatureAverage -> canMem[0].temp +//DONNERGY逆变器内电流单位0.01A，已修改 + +*****协议保护值变成总数据测试 +1.除了首航、硕日、日月元，其他都正常变成了总数据传输 +2.首航：与早期版本不符，以更早版本替换原有内容 + 硕日：保护报警共2个16位类型变量，拆分成4个8位类型传输再合并 + 日月元：保护报警共4个16位类型变量，把用到的部分摘出，化为4个8位类型，再进行相应放回 + + +////////////////////逆变器相关值可通过上位机修改 +//增加 +【global.h】(L305) + //20230705--------------- + uint16_t inverter_chgVolLimit; //通过上位机修改通信给逆变器的限压限流值 + uint16_t inverter_dsgVolLimit; //单位0.1V + uint16_t inverter_chgCurLimit; + uint16_t inverter_dsgCurLimit; //单位0.1A + //20230705--------------- +【flash.c】(L138/L201) + //20230705 + 0x40, //逆变器充电电压限制 0x0240 + 0x02, + 0xa0, //逆变器放电电压限制 0x01a0 + 0x01, + 0xe8, //逆变器充电电流限制 0x03e8 + 0x03, + 0xe8, //逆变器放电电流限制 0x03e8 + 0x03, + +//替换 +【flash.c】 +uint8_t MEMORY_UpdateFlash(uint32_t addr) +//44改为52，一共2处 +//22改为26，一共1处 +uint8_t FLASH_ReadCheck(uint32_t addr) +//44改为52，一共3处 +【ProtocolSwitch_P1/P2/P3/P4.c】 + chgCurLimit = 1000 * bmsMem.E2_485Snum; //充电电流限制100.0A，后面做出可配置 + dsgCurLimit = 1000 * bmsMem.E2_485Snum; //放电电流限制100.0A，后面做出可配置 + chgVolLimit = 576; //充电电压限制单节3.6，BMS保护可以设置3.65 + dsgVolLimit = 416; //放电电压限制单节2.6，BMS保护可以设置2.50 +——> + chgCurLimit = bmsMem.inverter_chgCurLimit; //充电电流限制，上位机配置，默认值100A + dsgCurLimit = bmsMem.inverter_dsgCurLimit; //放电电流限制，上位机配置，默认值100A + chgVolLimit = bmsMem.inverter_chgVolLimit; //充电电压限制，上位机配置，默认值57.6V + dsgVolLimit = bmsMem.inverter_dsgVolLimit; //放电电压限制，上位机配置，默认值41.6V + + +////////////////////0x46->0x4A + + +////////////////////小电流乱跳，会让充满电时，很快从100->99 +//增加对小电流范围1.2，-1.-2的延迟判定 +uint8_t DSGcount; //小电流放电计数 +uint8_t DSGminiFlag; //小电流放电标志 +uint8_t CHGcount; +uint8_t CHGminiFlag; + if(cali.tempCur < (-2)) //判断电池充放电状态 + { + bDSGING = 1; + } + else if(cali.tempCur > 2) + { + bCHGING = 1; + } + else if( (cali.tempCur >= (-2)) && (cali.tempCur < 0) ) //小电流放电，需要延迟考虑，只有连续三秒有小电流才会显示 + { + if(DSGminiFlag == 0) + { + DSGcount++; + if(DSGcount > 3) + { + DSGminiFlag = 1; + DSGcount = 0; + } + else + { + bmsMem.packCurrent = 0; + } + } + } + else if( (cali.tempCur > 0) && (cali.tempCur <= 2) ) //小电流充电，需要延迟考虑 + { + if(CHGminiFlag == 0) + { + CHGcount++; + if(CHGcount > 3) + { + CHGminiFlag = 1; + CHGcount = 0; + } + else + { + bmsMem.packCurrent = 0; + } + } + } + else //若即不充电，也不放电，则电流更新为0 + { + bDSGING = 1; + bmsMem.packCurrent = 0; + + DSGcount = 0; //小电流与0之间切换，当切回0，重新开始计数 + CHGcount = 0; + DSGminiFlag = 0; + DSGminiFlag = 0; + } + + +////////////////////上位机读取版本号 +//总数据存于新建结构体VersionMem +typedef struct +{ + uint8_t Hardware[3]; + uint8_t Software[4]; + uint8_t Screen; + uint8_t Batch_No[10]; +}VERSION_MEMORY ; + +VERSION_MEMORY VersionMem; + +//可先用03报文直接读取结构体，但要注意报文有区分，比如bmsMem.E2_485Addr 55 +#define MODBUS_VERSIONMEM_PT (uint8_t *)&VersionMem.Hardware[0]//上位机请求版本号通讯内存开始地址 + else if((modbusBuf[0] == 0xAA) && (modbusBuf[1] == 0x03) ) //上位机读取版本号 + { + MODBUS_F03_Rx(MODBUS_VERSIONMEM_PT); + } + + +////////////////////SOC精度改进 +1.在开机初始化读取时，把oldsoc也同时赋值，避免每次一上电就要进行一次写入SOC + oldsoc = tmp; +2.bmsMem.soc与oldsoc相差值大于1就会进行EEPROM的写入操作 + //SOC write to eeprom + if(bmsMem.soc > oldsoc) + { +// if( (bmsMem.soc - oldsoc) >= 5) +// { + oldsoc = bmsMem.soc; + tempW = bmsMem.soc; + EEPROM_WrMulByte(0,EEPROM_SOC_ADDR,1,&tempW); +// } + } + else if(bmsMem.soc < oldsoc) + { +// if((oldsoc - bmsMem.soc) >= 5 ) +// { + oldsoc = bmsMem.soc; + tempW = bmsMem.soc; + EEPROM_WrMulByte(0,EEPROM_SOC_ADDR,1,&tempW); +// } + } +3.bmsMem.soc的显示：0Ah->0% 0.1Ah->1% + bmsMem.soc = bmsMem.rcc/(bmsMem.fcc/100); + //如果实际容量百分比和soc相比至少高了0.1Ah，soc+1 + if( ( bmsMem.rcc%(bmsMem.fcc/100) ) /360000 ) //取精度0.1%作为判断标准 360000mAS = 0.1*1000*3600 = 0.1Ah + { + bmsMem.soc += 1; + } + + +////////////////////硕日协议更新充放电MOS状态 + if((bmsMem.bStatus3 & 0x02) !=0) //充电MOS状态 + { + statusByte |= 0x0400; + } + else + { + statusByte &= 0xFBFF; + } + if((bmsMem.bStatus3 & 0x01) !=0) //放电MOS状态 + { + statusByte |= 0x0800; + } + else + { + statusByte &= 0xF7FF; + } + + +////////////////////平均温度计算有误，已修改 +//计算总数时加上，清空原值 +TemperatureAverage = 0; + + +////////////////////SOC还未到满充时，充电会先跳到99Ah,99%，改成跳到99.1Ah,100%应该会更美观 +bmsMem.rcc = bmsMem.fcc - (bmsMem.fcc*9/1000); + + +////////////////////消除最后一个警告 +if(((int)tmp>=0) && (tmp<=100)) //在比较操作中使用类型转换不会改变变量本身的类型 + + +////////////////////上位机写入时间 6.25 +//文件夹内增加【rtc.h】 +//工程内替换【rtc.c】内代码 +//工程头文件路经增加"..\BSP" +//【main.c】增加 +(L25) +#include "rtc.h" +#include "soe.h" +(L78) + uf_RTC_Init(); //SOE + RTC_Get(); +(L130) + uf_RTC_Update(); //因为上位机的输入而修改时间 + RTC_Get(); //SOE,读时间 +//【i2c.c】增加/替换 +(L19) +#include "soe.h" +(L45) +void uf_I2C1_Init(void){(略)} +//可先用10报文进行写入结构体，但要注意报文有区分，比如bmsMem.E2_485Addr 66 +【RS485_Modbus.c】 +(L20) +#include "rtc.h" +#include "soe.h" +(L32) +#define Time_MEM_PT (uint8_t *)&calendar_Write.sec +(L268/307) + else if((modbusBuf[0] == bmsMem.E2_485Addr) && (modbusBuf[1] == 0x66) ) //上位机写时间 + { + MODBUS_F10_Rx(Time_MEM_PT); + } + + +////////////////////记录功能之在屏幕上的报警记录，同时暂时没有上位机记录 7.20 [V1.25.18.0] +//思路：此前已写的记录功能基本完善，分为“MCU将记录写入EEPROM”、“上位机校准时间”、“上位机写入定时参数”、“上位机通过MCU读取记录”四部分 +//现在只添加第一和第二部分，“MCU将记录写入EEPROM”(已完成)、“上位机校准时间”(已完成) +//同时把记录条数改为50条，目前只在屏幕上进行报警记录的查看 +//增加屏幕显示最新报警记录的功能；同时会因为序号变动而切换读取；有按钮可以清空所有记录 +//PS:IIC可能还会出现BUSY卡死现象，注意多测试，需要的话增加相关退出BUSY的代码 + +/********** 1.记录和时间功能移植 **********/ +//文件夹内增加【SOE.c】【SOE.h】 +//工程内添加【SOE.c】 + +/********** 2.修改记录数量 **********/ + if(soe.pc == 0x1C80) //0x1000-0x1C80共50条 + { + soe.pc = RECORD_START_ADDR; + } + + if(soe.num==50) + { + soe.num = 50; + } + +/********** 3.报警记录功能 **********/ +【AFE_SH367309.c】 +(L20) +#include "soe.h" +(L660)AFE_ProtectProcess()函数 + //soe记录判断 + soe.bsNew[0] = bmsMem.bStatus1; + soe.bsNew[1] = bmsMem.bStatus2; + soe.bsNew[2] = bmsMem.bStatus3; + soe.bsNew[3] = bmsMem.temperaStatus; + soe.bsNew[4] = bmsMem.balanceStatus; + soe.bsNew[5] = bmsMem.packStatus; + + + //电压报警备份 + if( ((soe.bsOld[0] & 0x43) ==0) && ((soe.bsOld[2] & 0x08) ==0) ) //原来是正常状态 + { + if((soe.bsNew[0] & 0x43) != 0) //报警触发 + { + soe.bsOld[0] = soe.bsNew[0]; //如果已经执行记录，就不会再执行 + soe.bkType = BKTYPE_ALARM; + } + + if((soe.bsNew[2] & 0x08) != 0) //报警触发 + { + soe.bsOld[2] = soe.bsNew[2]; //如果已经执行记录，就不会再执行 + soe.bkType = BKTYPE_ALARM; + } + } + else //已经出现报警 + { + if((soe.bsNew[0] & 0x43) == 0) //没有报警，上次清除 + { + soe.bsOld[0] &= 0XBC; //~0X43 + } + + if((soe.bsNew[2] & 0x08) == 0) //没有报警，上次清除 + { + soe.bsOld[2] &= 0XF7; //~0X08 + } + } + + //电流报警备份 + if( ((soe.bsOld[0] & 0x3c) ==0) && ((soe.bsOld[3] & 0x30) ==0) ) //原来是正常状态 + { + if((soe.bsNew[0] & 0x3c) != 0) //报警触发 + { + soe.bsOld[0] = soe.bsNew[0]; //如果已经执行记录，就不会再执行 + soe.bkType = BKTYPE_ALARM; + } + + if((soe.bsNew[3] & 0x30) != 0) //报警触发 + { + soe.bsOld[3] = soe.bsNew[3]; //如果已经执行记录，就不会再执行 + soe.bkType = BKTYPE_ALARM; + } + } + else //已经出现报警 + { + if((soe.bsNew[0] & 0x3c) == 0) //没有报警，上次清除 + { + soe.bsOld[0] &= 0XC3; //~0X3c + } + + if((soe.bsNew[3] & 0x30) == 0) //没有报警，上次清除 + { + soe.bsOld[3] &= 0XCF; //~0X30 + } + } + + //温度报警备份 + if( ((soe.bsOld[1] & 0x0f) ==0) && ((soe.bsOld[3] & 0x8f) ==0) ) //原来是正常状态 + { + if((soe.bsNew[1] & 0x0f) != 0) //报警触发 + { + soe.bsOld[1] = soe.bsNew[1]; //如果已经执行记录，就不会再执行 + soe.bkType = BKTYPE_ALARM; + } + + if((soe.bsNew[3] & 0x8f) != 0) //报警触发 + { + soe.bsOld[3] = soe.bsNew[3]; //如果已经执行记录，就不会再执行 + soe.bkType = BKTYPE_ALARM; + } + } + else //已经出现报警 + { + if((soe.bsNew[1] & 0x0f) == 0) //没有报警，上次清除 + { + soe.bsOld[1] &= 0XF0; //~0X0f + } + + if((soe.bsNew[3] & 0x8f) == 0) //没有报警，上次清除 + { + soe.bsOld[3] &= 0X70; //~0X8f + } + } + + //DI急停备份 + if( ((soe.bsOld[3] & 0x40) ==0) ) //原来是正常状态 + { + if((soe.bsNew[3] & 0x40) != 0) //报警触发 + { + soe.bsOld[3] = soe.bsNew[3]; //如果已经执行记录，就不会再执行 + soe.bkType = BKTYPE_ALARM; + } + } + else //已经出现报警 + { + if((soe.bsNew[3] & 0x40) == 0) //没有报警，上次清除 + { + soe.bsOld[3] &= 0XBF; //~0X40 + } + } + + if(soe.bkType !=0) //当出现情况，进行记录 + { + SOE_BkData(soe.bkType); //函数内部清除BKTYPE标记 + } + +/********** 4.报警记录的屏幕显示(其他) **********/ +1.时间显示-00A9【SDWA.c】 +#include "rtc.h" +//0x00A9 +//A5 5A 0A 82 00 A9 year month date week hour min sec +void SDWA_Send_Time(uint16_t addr){(略)} +2.星期数有误，会晚一天，在计算时多给1，此时数字“0”代表周日，数字"1"代表周一，以此类推【rtc.c】 +temp2=temp2+day+table_week[month-1]+1; + +3.删除报警记录的按钮【SDWA.c】 +#include "soe.h" +//直接放延时函数有可能影响其他进程，换成Flag/Count++的方法： +(L787) + if(clearFlag != 0) //删除记录的显示 + { + SDWA_Send_VAR(0x0420, 0); + SDWA_Send_VAR(0x0400, 1); + clearFlag++; + + if(clearFlag > 3) + { + clearFlag = 0; + SDWA_Send_VAR(0x0400, 0); + } + } +(L1513) + //删除记录按钮 + if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x04) && (sdwaBuf[5]==0x10)) //当按钮按下 + { + uint16_t i; + uint16_t pc; //待写入地址 + uint8_t adrh,adrl; + uint8_t wrBuf[64]; + + SDWA_Send_VAR(0x0420, 1); + + soe.index = 0; //起始序号0 + soe.pc = 0x1000; //起始地址0x1000 + soe.num = 0; //起始数量0 + + wrBuf[0] = (soe.index >> 24) & 0xff ; + wrBuf[1] = (soe.index >> 16) & 0xff ; + wrBuf[2] = (soe.index >> 8) & 0xff ; + wrBuf[3] = (soe.index >> 0) & 0xff ; + wrBuf[4] = (soe.pc >>8)&0XFF ; + wrBuf[5] = soe.pc & 0xff ; + wrBuf[6] = (soe.num >>8)&0XFF ; + wrBuf[7] = soe.num & 0xff ; + + EEPROM_WrMulByte(0x08,0x00,8,wrBuf); + delay_ms(10); + + pc = 0x1000; + for(i=0;i<52;i++) + { + wrBuf[i] = 0xff; + } + for(i=0;i<50;i++) + { + adrh = (pc>>8) & 0xff; + adrl = pc & 0xff; + EEPROM_WrMulByte(adrh,adrl,52,wrBuf); + delay_ms(10); + + pc += 0x40; + } + + read_index = 0; + clearFlag = 1; + } + +/********** 5.报警记录的屏幕显示(内容) **********/ +//在uf_I2C1_Init函数中有对于当前记录序号的读取函数，注意soe.pc和soe.index指向[下一个]可写地址和即将给与的序号 +1.显示当页的记录 + uint8_t i; + uint8_t adrh,adrl; + uint32_t ee_index[3]; + uint16_t ee_pc[3]; + + //报警记录序号,初始默认0，1，2 + ee_index[0] = read_index; + ee_pc[0] = 0x1000 + 0x0040 * ee_index[0]; + ee_index[1] = read_index+1; + ee_pc[1] = 0x1000 + 0x0040 * ee_index[1]; + ee_index[2] = read_index+2; + ee_pc[2] = 0x1000 + 0x0040 * ee_index[2]; + + USART_SendVarToSDWA(0x0701, ee_index[0]+1); + USART_SendVarToSDWA(0x0702, ee_index[1]+1); + USART_SendVarToSDWA(0x0703, ee_index[2]+1); + + //显示序号对应的报警记录 + if(read_index < soe.num)//为减少读写EEPROM次数，只当序号在soe.num范围内时可用 + { + for(i=0;i<3;i++) + { + adrh = (ee_pc[i]>>8) & 0xff; + adrl = ee_pc[i] & 0xff; + EEPROM_RdMulByte(adrh,adrl,52,recordBuf); + delay_ms(10); + + if(recordBuf[0]==0xff && recordBuf[1]==0xff && recordBuf[2]==0xff && recordBuf[3]==0xff)//序号数据全是0xff,表示无数据 + { + SDWA_Send_VAR(0x0705 + 0x0001*i,1); + } + else + { + SDWA_Send_VAR(0x0705 + 0x0001*i,0); + SDWA_Send_RecordTime(0x0710 + 0x0100*i); + SDWA_Send_Record(0x0790 + 0x0100*i); + } + } + } + else + { + for(i=0;i<3;i++) + { + SDWA_Send_VAR(0x0705 + 0x0001*i,1); + } + } +2.发送报警记录时间的报文： +void SDWA_Send_RecordTime(uint16_t addr){(略)} +3.发送报警记录内容的报文： +void SDWA_Send_Record(uint16_t addr){(略)} +4.报警记录个数的显示： +USART_SendVarToSDWA(0x0708, soe.num ); //记录个数的显示 +5.报警记录增加后，增加刷新SDWA的函数 + SDWA_Init(); +6.屏幕中之前写入的会被保留，增加填充空白的函数 +void SDWA_Send_Blank(uint16_t addr){(略)} + + +////////////////////当同类型报警先后出现，不会再记录后一个报警，已修改7.25 [V1.25.18.1] +//将同类型的报警拆分开更细 + + +////////////////////报警记录功能去掉序号51，始终显示1~50 [V1.25.18.2] +//SDWA_Init函数中： + if(ee_index[2] != 50) + { + SDWA_Send_VAR(0x0709, 0); + USART_SendVarToSDWA(0x0703, ee_index[2]+1); + } + else + { + SDWA_Send_VAR(0x0709, 1); + } + + +////////////////////屏幕报警显示与跳转分开 [V1.25.18.3] +1.把原来的SDWA_JumpToAlarm函数拆分成 + SDWA_ShowAlarm函数和SDWA_JumpToAlarm函数 +2.将SDWA_ShowAlarm函数用到SDWA_UpdateData函数中： + if(bAlarmFlag == 0) //无屏幕上的报警 + { + if( (bmsMem.temperaStatus & 0x40) !=0) //急停 + { + SDWA_Send_VAR(0x0100, 5); //“Emergency” + } + else + { + if(bCHGING ==1) //充电状态 + { + //SDWA_Send_Charging(0x0100); + SDWA_Send_VAR(0x0100, 0); //“Charge” + } + else //放电状态 + { + //SDWA_Send_Discharging(0x0100); + SDWA_Send_VAR(0x0100, 1); //“Discharge” + } + } + + SDWA_ClearAlarm(); + + } + else //出现了屏幕上的报警 + { + //SDWA_Send_Fault(0x0100); + SDWA_Send_VAR(0x0100, 2); //“Fault” + + if(bAlarmFlagOld ==0) + { + bAlarmFlagOld = 1; + SDWA_JumpToAlarm(); + } + + SDWA_ShowAlarm(); + + } + + +////////////////////屏幕修改总压值 [V1.25.18.4] +1.接收屏幕报文->把数据赋值给变量： + //修改逆变器充电限压：A5 5A 06 83 13 10 01 dataH dataL + if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x13) && (sdwaBuf[5]==0x10)) + { + uint16_t tmp; + tmp = sdwaBuf[7]<<8 | sdwaBuf[8]; + bmsMem.inverter_chgVolLimit = tmp; + } +2.在屏幕更新时显示值： + USART_SendVarToSDWA(0x1310, bmsMem.inverter_chgVolLimit ); + （在初始化函数中也加入显示：） + USART_SendVarToSDWA(0x1310, bmsMem.inverter_chgVolLimit ); + USART_SendVarToSDWA(0x0708, soe.num ); //记录个数的显示 +3.修改的值保存在Flash内： + PS：bmsMem.ee_sconf1~inverter_dsgCurLimit，是上位机写入配置参数的52位数据，皆会保存在Flash内 + 只有这之外的数据，才会专门存入EEPROM中，所以该值选择存入Flash中 +#include "AFE_SH367309.h" + //bmsMem中数据更新到FLASH A区和B区和AFE EEPORM + if(MEMORY_UpdateFlash(FLASH_DATA_A_BASE) ==0 && MEMORY_UpdateFlash(FLASH_DATA_B_BASE) ==0) + { + staPack.bits.flashUpdate= 0; + if(AFE_UpdateConfig() ==0) + { + staPack.bits.eepromUpdate = 0; + } + else + { + staPack.bits.eepromUpdate = 1; + } + } + else + { + staPack.bits.flashUpdate= 1; + } + bmsMem.packStatus = staPack.halfword; + + +////////////////////温差保护没有让MOS停下，是因为AFE_Ctrl里少了这个值 [V1.25.18.5] +AFE_Ctrl函数： +if((bmsMem.temperaStatus & 0xBf) != 0) //BIT0-5.7 +DIDO_Ctrl函数： + if((bmsMem.temperaStatus & 0xBf) == 0) //不能影响BIT0-5功能的运作 + + +////////////////////修改协议Victrion [V1.25.18.6] +Victrion协议内代码取消注释——协议书中标明但未落实的内容，并修改使其适配现在的变量。 +void CAN_Protocol_Victrion(void){(略)} + + +////////////////////修改通信协议:总容量的传输，因容量可写入修改，故协议传输也要改为变量 [V1.25.18.7] +【global.h】 +extern uint8_t capacity_Ah; +【GasGauge.c】 +(L28) +uint8_t capacity_Ah; //单板容量,用于计算总容量传给上位机 单位1Ah +(L45) + if(tmpRd>0 && tmpRd<255) //如果之前写过容量值,就按照之前的值显示，否则显示100Ah + { + bmsMem.fcc = 3600 * 1000*tmpRd; + capacity_Ah = tmpRd; + } + else + { + bmsMem.fcc = 3600 * 100000; //系统满充容量暂定100AH = 100,000mAH = 360,000,000mAS + capacity_Ah = 100; + tmpRd = 100; + EEPROM_WrMulByte(7,1,1,&tmpRd); + } +(L146) + if(bmsMem.write_Capacity !=0) + { + EEPROM_WrMulByte(7,1,1,&bmsMem.write_Capacity); + delay_ms(5); + + capacity_Ah = bmsMem.write_Capacity; + bmsMem.fcc = 3600 * 1000*bmsMem.write_Capacity; + bmsMem.write_Capacity = 0; + } +//协议中统一修改： +totalCapacity = 10000 * bmsMem.E2_485Snum; -> totalCapacity = 100 * capacity_Ah * bmsMem.E2_485Snum; //单位0.01Ah +totalCapacity = 100 * bmsMem.E2_485Snum; -> totalCapacity = capacity_Ah * bmsMem.E2_485Snum; //单位1Ah + + +////////////////////修改通信协议:上位机修改的逆变器限流值，只代表该单板本身的，传输值仍然要乘以个数 [V1.25.18.8] + + chgCurLimit = bmsMem.inverter_chgCurLimit; //充电电流限制，上位机配置，默认值100A + dsgCurLimit = bmsMem.inverter_dsgCurLimit; //放电电流限制，上位机配置，默认值100A +——> + chgCurLimit = bmsMem.inverter_chgCurLimit * bmsMem.E2_485Snum; //充电电流限制，上位机配置，默认值100A + dsgCurLimit = bmsMem.inverter_dsgCurLimit * bmsMem.E2_485Snum; //放电电流限制，上位机配置，默认值100A + + +////////////////////平均SOH相关 [V1.25.18.9] +1.canMem[0]汇总信息也有soh，只是不用传给逆变器 +2.通信协议:SOH固定99，不是平均值 + + +////////////////////Modbus主从机传输数据汇总的canMem变量增大范围 [V1.25.18.10] + uint8_t soc; + uint8_t soh; + ——> + uint16_t soc; + uint16_t soh; + + +////////////////////Modbus传输数据有出现过卡死问题，将初始化函数的值更多些 [V1.25.18.11] +//注意，SOC清零的话会影响逆变器正常工作，所以要注释掉 +void MODBUS_Init(void) +{ + modbusCurSta = 0; //主机当前采集状态 + modbusCurDev = 2; //主机当前采集设备，从从机2开始 + modbusCurRevdFlag = 0;// + modbusCurSlaveNum = 0; + + canMem[0].protect_byte1 = 0; + canMem[0].protect_byte2 = 0; + canMem[0].alarm_byte1 = 0; + canMem[0].alarm_byte2 = 0; + canMem[0].cur = 0; + canMem[0].temp = 0; +// canMem[0].soc = 0; +// canMem[0].soh = 0; + + modbusBufIndex = 0; + modbusF03RxFlg = 0; + modbusF10RxFlg = 0; + modbusFaaRxFlg = 0; + modbusFbbRxFlg = 0; + modbusMoniCount = MODBUS_MON_CNT; + + uf_UART_Init(9600); +} + + +////////////////////记录条数会超过50；新记录不覆盖旧的 [V1.25.18.12] +//总个数计算修改(Total) + if(soe.num >= 50) + { + soe.num = 50; + } +//新增最新报警所在显示(Latest) + + +////////////////////充电状态的小电流延时，没有显示充电状态，已修改 [V1.25.18.13] +//AFE_CurrentProcess()函数 + bDSGING = 1; + bCHGING = 1; + +////////////////////通信时有符号类型的浮动会让汇总的数据或有出错，在主机汇总数据时增加限额+/-500A [V1.25.18.14] + + +////////////////////数据转换问题 int16->int32 [V1.25.18.15] +//问题根源：收到从机数据后，未能正确转换类型 +原应该 -1.06A = -(006A) = 1111 1111 1111 1111 1111 1111 1001 0110 +现在传654.30A = 0000FF96 = 0000 0000 0000 0000 1111 1111 1001 0110 + + +////////////////////Growatt协议更新，适配手头测试的Growatt逆变器 [V1.25.18.16] + + +////////////////////屏幕暗了后，主动返回第一页(中显版) [V0.0.0.17] +1.MCU检测屏幕亮度SDWA_DetectBright() +2.屏幕返回变暗的对应数据，MCU进行页数的跳转 + //息屏再打开，跳转首页 + //屏幕亮度20: A5 5A 04 81 01 01 20 + //跳转设置界面指令: A5 5A 04 80 03 00 01 + if((sdwaBuf[2]==0x04) && (sdwaBuf[3]==0x81) && (sdwaBuf[6]==0x20)) + { + USART_SendData(USART2, 0xA5); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + USART_SendData(USART2, 0x5A); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + USART_SendData(USART2, 0x04); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + USART_SendData(USART2, 0x80); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + USART_SendData(USART2, 0x03); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + USART_SendData(USART2, 0x00); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + USART_SendData(USART2, 0x01); + while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET); + } + + +////////////////////修改急停对应英文"Emergency"->"RPSD_Activated" [V0.0.0.18] + if( ((temperaStatus & 0x40) !=0) ) //急停 RPSD_Activated + { + sendcount +=15; + *p = 'R'; p++; + *p = 'P'; p++; + *p = 'S'; p++; + *p = 'D'; p++; + *p = '_'; p++; + *p = 'A'; p++; + *p = 'c'; p++; + *p = 't'; p++; + *p = 'i'; p++; + *p = 'v'; p++; + *p = 'a'; p++; + *p = 't'; p++; + *p = 'e'; p++; + *p = 'd'; p++; + *p = ' '; p++; + } + + +**9.5** +////////////////////屏幕亮度检测，应不会导致执行SDWA_Init()函数，已修改 [0.0.18.19] + + +////////////////////屏幕写入增多，加一层判断以减少写入协议选择的次数 +【SDWA.c】 + uint8_t protocol_Index; + protocol_Index = protocol; + +protocol -> protocol_Index + + if(protocol != protocol_Index) + { + protocol = protocol_Index; + + EEPROM_WrMulByte(7,0,1,&protocol); + delay_ms(5); + } + + +////////////////////SOC满电，不会轻易掉到99.1Ah +//去掉=号 + + +////////////////////默认值修改105A [0.0.18.20] + + +** 9.25逐步增加排查BUG ** +【1】 +////////////////////添加第5页的协议选择勾选相关 No.34~42 +void SDWA_Init(void) +注意修改中间的判断条件，增加若干项 + SDWA_DispProcotol(0x03,0x06,0x00); + +void SDWA_RecvData(void) +增加若干项 + else if((sdwaBuf[2]==0x06) && (sdwaBuf[3]==0x83) && (sdwaBuf[4]==0x03) && (sdwaBuf[5]==0x16)) + { + if(sdwaBuf[8]==0x01) + { + if(protocol !=0x07) + protocol = 0x07; + } + else if(sdwaBuf[8]==0x00) + { + if(protocol ==0x07) + protocol = 0x00; + } + } + + +////////////////////新增协议 [0.29.0.0] +17.SMK 485 +32.COSUPER 485 SRNE +33.Sunway 485 SMK +30.Amensolar CAN Megarevo + +新建数据处理函数,同时加上额外定义 +void MOD_Protocol_COSUPER(void){} +extern void MOD_Protocol_COSUPER(void); + +void CAN_UpdateData(void) +增加若干项 + else if(protocol_Index == 32){} + +void Protocol_UpdateData(void)和void MODBUS1_IT_TIMUpdate(void) +增加若干项 + else if(protocol_Index == 32){} + + +【2】 +////////////////////初始化时，从机数量置0，主从机数量也应该置1 +【RS485_Modbus.c】(L461) + bmsMem.E2_485Snum = 1; + + +////////////////////屏幕没有的报警也会在主页显示“Fault” [0.0.18.21] + + +////////////////////MOS关闭还有2A以上电流，启动DO关断 [0.0.18.22] +平常继电器关闭， +当放电MOS关闭，仍存在放电电流，说明放电MOS可能损坏，需开启继电器，在外部进行电路的断开 + 此时若电流处在放电或者待机的值，无需开启继电器 +当充电MOS关闭，仍存在充电电流，说明充电MOS可能损坏，需开启继电器，在外部进行电路的断开 + 此时若电流处在放电或者待机的值，无需开启继电器 + +*报警灯亮，但不跳转屏幕 +*需要2bit标志位，表示充电MOS故障、放电MOS故障[bmsMem.bStatus2的bit7.8] +*传给上位机，上位机显示具体报警内容 +*报警记录C-MOS_Fault、D-MOS_Fault + +//把所有的DIDO->DI,DI_CTRL->DI +//DO对应PB14，使能函数为DO_On()和DO_Off() +//标志位用的是bmsMem.bStatus2的bit6和bit7，因输入参数bmsMem.packCurrent是1s计算一次，故检测执行代码一起直接放在AFE_ProtectProcess()中执行 +bmsMem.bStatus2 = temp[1] & 0x0f; //bit4~7用在其他地方 +//MOS故障的报警记录显示 + + +【3】 +////////////////////充电过压不报警 [0.0.18.23] +(当处于充电状态，)当SOC大于99%， +此时触发过压报警，不会跳转屏幕，也不会亮报警灯 + +*正常98 ->触发过压->灯亮+跳转+显示过压 ->其他报警->灯亮+跳转+显示过压 +*正常98 ->其他报警->灯亮+跳转+不显示过压 ->触发过压->灯亮+跳转+显示过压 + +*正常100 ->其他报警->灯亮+跳转+不显示过压 ->触发过压->灯亮+不跳+不显示过压 +*正常100 ->触发过压->不亮+不跳+不显示过压 ->其他报警->灯亮+跳转+不显示过压 + +//报警灯和屏幕跳转相关进行SOC判断 + + +【4】 +////////////////////待机状态Nomal [0.0.18.24] +//将待机状态认为是独立于充放电状态的值 +【AFE_SH367309.c】 +//在电流值计算后，若小于100mA且大于-100mA，就算待机，充放电状态不会因此置0 +【SDWA】 +//只影响屏幕显示，排在充放电状态前 +【GasGauge.c】 +//但是少于100mA的电流仍不会计入容量减少中 +SDWA_Send_VAR(0x0100, 6); + + +////////////////////古顶与硕日分开进行数据更新，古顶要适配8串也适配16串 [0.0.18.25] + + +////////////////////485协议的容量值改为变量 [0.0.18.26] + + +////////////////////DO控制的脱扣器，一旦给高电平就会启动，且不会自行返回 [0.0.18.27] +//增加对-2A~2A之间的DO动作 +//增加延时判断变量DODSGcount和DOCHGcount + + +////////////////////[0.0.18.26]的后续优化 [0.0.18.28] +1.485协议内的容量 +//bmsMem.fcc/3600*bmsMem.E2_485Snum/10 -> 100*capacity_Ah*bmsMem.E2_485Snum +//bmsMem.fcc/3600*bmsMem.E2_485Snum -> 1000*capacity_Ah*bmsMem.E2_485Snum +2.并机个数 +//(日月元协议内)固定1 -> bmsMem.E2_485Snum +3. +//统一整改电芯个数： +//删去变量cellNum的定义，(GaugeManage()函数中)替换成bmsMem.ucCellNum +//(COSUPER协议内)bmsMem.ee_sconf1&0x0f -> bmsMem.ucCellNum +//(日月元协议内+全局范围的串数相关值)固定16 -> bmsMem.ucCellNum +for(i=0;i<16;i++) -> for(i=0;i MODBUS1_UpdateData() +把CAN_UpdateData在主程序中朝后排，与MODBUS1_UpdateData放一起 +5.合并同类项：OUCO和Magerevo，Sunsynk和Deye +6.命名Victrion->Victron +7.补上485协议17.SMK的输出 + + +////////////////////屏幕输入参数充电限压，增加写入的上下限54~58V，超出则显示原值 [0.0.18.29] + + +////////////////////增加协议Afore，因逆变器通讯速率要求，特改为0.5s一个 [0.30.0.0] + + +////////////////////SDWn屏幕相关-地址上限0x03ff、息屏跳转不同 [0.0.0.0.n] +注意： +·屏幕息屏跳转需要主程序和全局变量共同完成 +·无实际报警记录那页，会先显示上次数据再刷新掉，需要把该页也纳入执行函数：if(read_index < soe.num+3) +·因SDWn的特性，报警清除成功图标的显示，会因为图标不可透明，需要用其他方式刷新掉：SDWA_Init(); + + +////////////////////容量变量限值变大255->65535 [0.0.18.30] +1.上位机写入capacity +//去掉crc8校验，扩大write_Capacity为u16 +//增大capacity_Ah +//初始化/写入时，存放到EEPROM地址的执行扩大成2位(7,1,2) +//收到要写入的容量后，判断是小于1000才会写入，否则置0 +//根据bmsMem.fcc = 3600 * 1000 * capacity_Ah，而bmsMem.fcc是u32的，0xFFFFFFFF对应的最大容量约1,193.04Ah，设置上位机上限为1000Ah +2.容量相关的应用过程 + + +////////////////////Pylon和盛能杰的总容量是uint32_t类型，输出应占4Byte，已修改 + + +////////////////////增加GSSTES精石逆变器的协议No.36 + + +////////////////////待机状态相关优化 [0.0.18.31] +//注释统一改为Standby +//待机状态时，电流值存在。因干扰值过多不参与容量计算，但参与电流校准 +【AFE_SH367309.c】 +//在电流值计算后，若小于100mA且大于-100mA，就算待机(屏幕最小显示0.1A) +//充放电状态此时置0 +【GasGauge.c】 +//改动AFE_CurrentProcess()函数 +//少于100mA的电流不会计入容量计算中 +//电流积分法和判断满充满放，都不需要额外判断充放电状态 +//满充跳转：100%->99.1% 改为 100%->99.5% 更合理 +//满放跳转：0%->0.9% 改为 0%->0.5% + + +////////////////////新版本号 [0.0.18.32] +硬件显示5.0.G +发货的软件显示类似：V1.24.A0.0 +测试/软件内部的程序，软件版本号显示:V0.0.0.0 +（屏幕分类暂时隐藏，不进行区分） + + +////////////////////CAN协议的数组CAN ID个数从10改为20，个别(Sigineer\Schneider\Pylon)需要 +CanTxMsg TxMessage[20]; +uint8_t TxMailBox[20]; + + +////////////////////MOS故障与限流板使用有冲突，增加判断条件curLimitFlag=0进行修正 11.7 [0.0.18.33] + + + + +////////////////////uf_UART_Init() -> uf_UART1_Init() + + +////////////////////测试旧上位机能否读删报警记录50条，暂时不加上定时记录 [V0.0.18.34] +1.【global.h】 +extern void UART1_ReadRecord(void); +extern void UART1_ClearRecord(void); +2.【RS485_Modbus.c】 +MODBUS_IT_TIMUpdate()函数内增加： + else if((modbusBuf[0] == bmsMem.E2_485Addr) && (modbusBuf[1] == 0Xdd) ) //读取记录 + { + UART1_ReadRecord(); + } + else if((modbusBuf[0] == bmsMem.E2_485Addr) && (modbusBuf[1] == 0xee) ) //清除记录 + { + UART1_ClearRecord(); + } +MODBUS_IQ_Transmit()函数内增加： + else if(modbusFddRxFlg == 1) //按顺序读记录 + { + modbusFddRxFlg = 0; + modbusBufIndex = 0; + + EEPROM_RdMulByte(modbusBuf[2],modbusBuf[3],52, &modbusBuf[4]); + crc16 = CRC16_Cal(modbusBuf, 56); + modbusBuf[56] = crc16.b8[0]; + modbusBuf[57] = crc16.b8[1]; + + MODBUS_UART_SendMulByte(modbusBuf, 58); + MODBUS_UART_IT_RX_ENABLE; + } + else if(modbusFeeRxFlg == 1) //清除记录 + { + modbusFeeRxFlg = 0; + modbusBufIndex = 0; + MODBUS_UART_SendMulByte(modbusBuf, 8 ); + MODBUS_UART_IT_RX_ENABLE; + } +新加： +uint8_t modbusFddRxFlg; //读取记录 接收正确标记 +uint8_t modbusFeeRxFlg; //清除记录 接收正确标记 + +/**************************************** +**** 按顺序读记录 ***** +** M: A1 dd 10 00 00 00 CRCL H ** +** S: A1 dd 10 00 d0-51 CRCL H ** +*****************************************/ +void UART1_ReadRecord(void) +{ + BYTE2 crc16; + + //CRC判断 + crc16 = CRC16_Cal(modbusBuf, 6); + if( (modbusBuf[7] == crc16.b8[1]) || (modbusBuf[6] == crc16.b8[0]) ) + { + modbusFddRxFlg = 1; + MODBUS_UART_IT_RX_DISABLE; + } + else + { + MODBUS_Init(); //没加这个时，换地址通讯连接不上，待监控时间到重新初始化之后才恢复连接 + } +} + +/**************************************** +**** 清除EEPROM内的记录 ***** +** M: A2 ee 00 55 00 aa CRCL H ** +** S: A2 ee 00 55 00 aa CRCL H ** +*****************************************/ +void UART1_ClearRecord(void) +{ + uint16_t i; + uint16_t pc; //待写入地址 + uint8_t adrh,adrl; + uint8_t wrBuf[64]; + BYTE2 crc16; + + //CRC判断 + crc16 = CRC16_Cal(modbusBuf, 6); + if( (modbusBuf[7] == crc16.b8[1]) || (modbusBuf[6] == crc16.b8[0]) ) + { + soe.index = 0; //起始序号0 + soe.pc = 0x1000; //起始地址0x1000 + soe.num = 0; //起始数量0 + + wrBuf[0] = (soe.index >> 24) & 0xff ; + wrBuf[1] = (soe.index >> 16) & 0xff ; + wrBuf[2] = (soe.index >> 8) & 0xff ; + wrBuf[3] = (soe.index >> 0) & 0xff ; + wrBuf[4] = (soe.pc >>8)&0XFF ; + wrBuf[5] = soe.pc & 0xff ; + wrBuf[6] = (soe.num >>8)&0XFF ; + wrBuf[7] = soe.num & 0xff ; + + EEPROM_WrMulByte(0x08,0x00,8,wrBuf); + delay_ms(10); + + pc = 0x1000; + for(i=0;i<52;i++) + { + wrBuf[i] = 0xff; + } + for(i=0;i<50;i++) + { + adrh = (pc>>8) & 0xff; + adrl = pc & 0xff; + EEPROM_WrMulByte(adrh,adrl,52,wrBuf); + delay_ms(10); + + pc += 0x40; + } + + + EEPROM_RdMulByte(0x08,0x04,4,&modbusBuf[2]); //当前序号 + + crc16 = CRC16_Cal(modbusBuf, 6); + modbusBuf[6] = crc16.b8[0]; + modbusBuf[7] = crc16.b8[1]; + + modbusFeeRxFlg = 1; + MODBUS_UART_IT_RX_DISABLE; + } + else + { + MODBUS_Init(); //没加这个时，换地址通讯连接不上，待监控时间到重新初始化之后才恢复连接 + } +} + + +////////////////////上位机修改Soc [V0.0.18.35] +【global.h】 + //20231109--------------- + uint8_t write_Soc; //通过上位机改变板子的通信地址 + uint8_t soc_crc; + //20231109--------------- +【RS485_Modbus.c】 +0x4A -> 0x4B +【GasGauge.c】 + if(bmsMem.write_Soc !=0) + { + EEPROM_WrMulByte(0,EEPROM_SOC_ADDR,1,&bmsMem.write_Soc); + delay_ms(5); + + bmsMem.soc = bmsMem.write_Soc; + bmsMem.rcc = (bmsMem.fcc/100) * bmsMem.soc; + bmsMem.write_Soc = 0; + } + + +////////////////////电芯个数关系到最大最小电压的判定，放到电压检测函数AFE_VoltageProcess()中 + bmsMem.ucCellNum = bmsMem.ee_sconf1 & 0x0F; + if( bmsMem.ucCellNum < 5 ) //其他代表16串，一般是0000 + { + bmsMem.ucCellNum = 16; + } + + +////////////////////只有4路环境温度进行平均温度、最高最低温度的计算 [Vx.x.18.36] + + +////////////////////后续去掉温差这一功能，temperatStatus.bit7空置预留 [Vx.x.18.37] + + +////////////////////和维克托逆变器实体对过后，修改协议内容 [Vx.x.18.38] + + +////////////////////改动轮询总数据的报警值流程 [Vx.x.18.39] +总数据的报警值从协议的改为传输bStatus1,2,3和temperaStatus +【global.h】改名： +BMS_MEMORY结构体：bmsMem.can_protect_byte1 -> bmsMem.can_status_byte1 +CAN_MEMORY结构体：canMem[i].protect_byte1 -> canMem[i].status_byte1 +【AFE_SH367309.c】 +AFE_ProtectProcess()函数增加： + //sum of all packs + bmsMem.can_status_byte1 = bmsMem.bStatus1; + bmsMem.can_status_byte2 = bmsMem.bStatus2; + bmsMem.can_status_byte3 = bmsMem.bStatus3; + bmsMem.can_status_byte4 = bmsMem.temperaStatus; //温度报警判断已在此之前执行 +【RS485_Modbus.c】和【ProtocolSwitch_P1/2/3/4/5.c】 +原来：bmsMem.bStatus1 -> 协议函数protectByte1 -> bmsMem.can_protect_byte1 -> canMem[i].protect_byte1 -> 协议函数输出 +现在：bmsMem.bStatus1 -> bmsMem.can_status_byte1 -> canMem[i].status_byte1 -> 协议函数protectByte1 -> 协议函数输出 + + +////////////////////IIC通信优化 [Vx.x.18.40] + + +////////////////////小电流滤波值调到3，使3以下的延迟显示 [Vx.x.18.41] + + +////////////////////温度电阻表一直未更新，已修改 [Vx.x.18.42] + + +////////////////////单板使用时，发给逆变器的电流数据一直会清空，有问题 [Vx.x.18.43] +//将数据清空操作改为赋值主机数据 + + +////////////////////Deye协议，增加强充标志的输出 [Vx.x.18.44] +//判断条件按客户给的Pylon协议(很相似)，以5%和10%为准 + + + + +////////////////////网口1的新上位机 [V0.0.19.00] +//读数据功能为了和逆变器区分，改为0x33 +【RS485_Modbus_Inverter.c】 +//增加 +(L5) +#include "rtc.h" +#include "soe.h" +(L14) +#define MODBUS1_MEM_PT (uint8_t *)&bmsMem.vCell[0] //上位机通讯内存开始地址 +#define MODBUS1_VersionMEM_PT (uint8_t *)&VersionMem.Hardware[0]//上位机请求版本号通讯内存开始地址 +#define MODBUS1_TimeMEM_PT (uint8_t *)&calendar_WRITE.sec //上位机时间校准通讯内存开始地址 +(L29) +uint8_t modbus1F10RxFlg; //写数据接收正确标记 +uint8_t modbus1FaaRxFlg; //CADC零点校准数据接收正确标记 +uint8_t modbus1FbbRxFlg; //CADC增益校准数据接收正确标记 +uint8_t modbus1FddRxFlg; //读取记录 接收正确标记 +uint8_t modbus1FeeRxFlg; //清除记录 接收正确标记 +(L88) + BYTE2 crc16; +(L97) + else if(modbus1F10RxFlg == 1) + { + modbus1F10RxFlg = 0; + modbus1BufIndex = 0; + + //bmsMem中数据更新到FLASH A区和B区和AFE EEPORM + if(MEMORY_UpdateFlash(FLASH_DATA_A_BASE) ==0 && MEMORY_UpdateFlash(FLASH_DATA_B_BASE) ==0) + { + staPack.bits.flashUpdate= 0; + if(AFE_UpdateConfig() ==0) + { + staPack.bits.eepromUpdate = 0; + MODBUS1_UART_SendMulByte(modbus1Buf, 8); + } + else + { + staPack.bits.eepromUpdate = 1; + } + } + else + { + staPack.bits.flashUpdate= 1; + } + bmsMem.packStatus = staPack.halfword; + MODBUS1_UART_IT_RX_ENABLE; + } + else if(modbus1FaaRxFlg == 1) + { + modbus1FaaRxFlg = 0; + modbus1BufIndex = 0; + + if(cali.flagZeroCaliFail ==0) //ok + { + // 01 AA 5A A5 03 04 CRCL H + modbus1Buf[0] = bmsMem.E2_485Addr; + modbus1Buf[1] = 0xaa; + modbus1Buf[2] = 0x5a; + modbus1Buf[3] = 0xa5; + modbus1Buf[4] = 0x03; + modbus1Buf[5] = 0x04; + crc16 = CRC16_Cal(modbus1Buf, 6); + modbus1Buf[6] = crc16.b8[0]; + modbus1Buf[7] = crc16.b8[1]; + MODBUS1_UART_SendMulByte(modbus1Buf, 8); + } + else //fail + { + // 01 AA 5A A5 05 06 CRCL H + modbus1Buf[0] = bmsMem.E2_485Addr; + modbus1Buf[1] = 0xaa; + modbus1Buf[2] = 0x5a; + modbus1Buf[3] = 0xa5; + modbus1Buf[4] = 0x05; + modbus1Buf[5] = 0x06; + crc16 = CRC16_Cal(modbus1Buf, 6); + modbus1Buf[6] = crc16.b8[0]; + modbus1Buf[7] = crc16.b8[1]; + MODBUS1_UART_SendMulByte(modbus1Buf, 8); + } + + MODBUS1_UART_IT_RX_ENABLE; + } + else if(modbus1FbbRxFlg == 1) + { + modbus1FbbRxFlg = 0; + modbus1BufIndex = 0; + + if(cali.flagGainCaliFail ==0) //ok + { + // 01 AA 5A A5 03 04 CRCL H + modbus1Buf[0] = bmsMem.E2_485Addr; + modbus1Buf[1] = 0xbb; + modbus1Buf[2] = 0x5b; + modbus1Buf[3] = 0xb5; + modbus1Buf[4] = 0x03; + modbus1Buf[5] = 0x04; + crc16 = CRC16_Cal(modbus1Buf, 6); + modbus1Buf[6] = crc16.b8[0]; + modbus1Buf[7] = crc16.b8[1]; + MODBUS1_UART_SendMulByte(modbus1Buf, 8); + } + else //fail + { + // 01 AA 5A A5 05 06 CRCL H + modbus1Buf[0] = bmsMem.E2_485Addr; + modbus1Buf[1] = 0xbb; + modbus1Buf[2] = 0x5b; + modbus1Buf[3] = 0xb5; + modbus1Buf[4] = 0x05; + modbus1Buf[5] = 0x06; + crc16 = CRC16_Cal(modbus1Buf, 6); + modbus1Buf[6] = crc16.b8[0]; + modbus1Buf[7] = crc16.b8[1]; + MODBUS1_UART_SendMulByte(modbus1Buf, 8); + } + + MODBUS1_UART_IT_RX_ENABLE; + } + else if(modbus1FddRxFlg == 1) //按顺序读记录 + { + modbus1FddRxFlg = 0; + modbus1BufIndex = 0; + + EEPROM_RdMulByte(modbus1Buf[2],modbus1Buf[3],52, &modbus1Buf[4]); + crc16 = CRC16_Cal(modbus1Buf, 56); + modbus1Buf[56] = crc16.b8[0]; + modbus1Buf[57] = crc16.b8[1]; + + MODBUS1_UART_SendMulByte(modbus1Buf, 58); + MODBUS1_UART_IT_RX_ENABLE; + } + else if(modbus1FeeRxFlg == 1) //清除记录 + { + modbus1FeeRxFlg = 0; + modbus1BufIndex = 0; + MODBUS1_UART_SendMulByte(modbus1Buf, 8 ); + MODBUS1_UART_IT_RX_ENABLE; + } +(L245) + else + { + MODBUS1_Init(); //没加这个时，换地址通讯连接不上，待监控时间到重新初始化之后才恢复连接 + } + } + + else if((modbus1Buf[0] == bmsMem.E2_485Addr) && (modbus1Buf[1] == 0x33) ) //上位机读数据处理 + { + MODBUS1_F03_Rx(MODBUS1_MEM_PT); + } + else if((modbus1Buf[0] == bmsMem.E2_485Addr) && (modbus1Buf[1] == 0x10) ) //写数据处理 + { + MODBUS1_F10_Rx(MODBUS1_MEM_PT); + } + else if((modbus1Buf[0] == bmsMem.E2_485Addr) && (modbus1Buf[1] == 0xaa) ) //CADC零点校准处理 + { + MODBUS1_Faa_Rx(MODBUS1_MEM_PT); + } + else if((modbus1Buf[0] == bmsMem.E2_485Addr) && (modbus1Buf[1] == 0xbb) ) //CADC增益校准处理 + { + MODBUS1_Fbb_Rx(MODBUS1_MEM_PT); + } + else if((modbus1Buf[0] == bmsMem.E2_485Addr) && (modbus1Buf[1] == 0x55) ) //上位机读取版本号 + { + MODBUS1_F03_Rx(MODBUS1_VersionMEM_PT); + } + else if((modbus1Buf[0] == bmsMem.E2_485Addr) && (modbus1Buf[1] == 0x66) ) //上位机写时间 + { + MODBUS1_F10_Rx(MODBUS1_TimeMEM_PT); + } + else if((modbus1Buf[0] == bmsMem.E2_485Addr) && (modbus1Buf[1] == 0Xdd) ) //读取记录 + { + UART3_ReadRecord(); + } + else if((modbus1Buf[0] == bmsMem.E2_485Addr) && (modbus1Buf[1] == 0xee) ) //清除记录 + { + UART3_ClearRecord(); + } +(L303) + if((modbus1Buf[0] == bmsMem.E2_485Addr) && (modbus1Buf[1] == 0x33) ) //读数据处理 + { + MODBUS1_F03_Rx(MODBUS1_MEM_PT); + } + else if((modbus1Buf[0] == bmsMem.E2_485Addr) && (modbus1Buf[1] == 0x10) ) //写数据处理 + { + MODBUS1_F10_Rx(MODBUS1_MEM_PT); + } + else if((modbus1Buf[0] == bmsMem.E2_485Addr) && (modbus1Buf[1] == 0xaa) ) //CADC零点校准处理 + { + MODBUS1_Faa_Rx(MODBUS1_MEM_PT); + } + else if((modbus1Buf[0] == bmsMem.E2_485Addr) && (modbus1Buf[1] == 0xbb) ) //CADC增益校准处理 + { + MODBUS1_Fbb_Rx(MODBUS1_MEM_PT); + } + else if((modbus1Buf[0] == bmsMem.E2_485Addr) && (modbus1Buf[1] == 0x55) ) //上位机读取版本号 + { + MODBUS1_F03_Rx(MODBUS1_VersionMEM_PT); + } + else if((modbus1Buf[0] == bmsMem.E2_485Addr) && (modbus1Buf[1] == 0x66) ) //上位机写时间 + { + MODBUS1_F10_Rx(MODBUS1_TimeMEM_PT); + } + else if((modbus1Buf[0] == bmsMem.E2_485Addr) && (modbus1Buf[1] == 0Xdd) ) //读取记录 + { + UART3_ReadRecord(); + } + else if((modbus1Buf[0] == bmsMem.E2_485Addr) && (modbus1Buf[1] == 0xee) ) //清除记录 + { + UART3_ClearRecord(); + } + + else +(L360) +/*********************************************** +**** MODBUS1 F10 写多个寄存器报文解析 ***** +** 01 10 ADRH L 0 LENTH 2LETH DATAn CRCL H ** +** 01 10 ADRH L 0 LENTH CRCL CRCH ** +************************************************/ +//mem point to bmsMem +void MODBUS1_F10_Rx(uint8_t *mem) +{ + BYTE2 crc16; + uint8_t adr; + uint8_t len; + + len = modbus1Buf[6]; + adr = modbus1Buf[3] <<1; + + //CRC判断 + crc16 = CRC16_Cal(modbus1Buf, len+7); + if( (modbus1Buf[len+8] == crc16.b8[1]) && (modbus1Buf[len+7] == crc16.b8[0]) ) + { + memcpy(mem+adr, &modbus1Buf[7], len); //将modbus1Buf数组数据COPY到bmsMem结构体，注意大小端 + crc16 = CRC16_Cal(modbus1Buf, 6); + modbus1Buf[6] = crc16.b8[0]; + modbus1Buf[7] = crc16.b8[1]; + + modbus1F10RxFlg = 1; + MODBUS1_UART_IT_RX_DISABLE; + } +} + +/**************************************** +**** MODBUS FAA CADC零点校准 ***** +** M: 01 AA 5A A5 01 02 CRCL H ** +** S: 01 AA 5A A5 03 04 CRCL H OK ** +** S: 01 AA 5A A5 05 06 CRCL H FAIL ** +*****************************************/ +void MODBUS1_Faa_Rx(uint8_t *mem) +{ + BYTE2 crc16; + + //CRC判断 + crc16 = CRC16_Cal(modbus1Buf, 6); + if( (modbus1Buf[7] == crc16.b8[1]) || (modbus1Buf[6] == crc16.b8[0]) ) + { + cali.cmdZero = 1; +// if( (modbus1Buf[2] == 0x5a) && (modbus1Buf[3] == 0xa5) && (modbus1Buf[4] == 0x01) && (modbus1Buf[5] == 0x02) ) +// { +// cali.cmdZero = 1; +// } + +// crc16 = CRC16_Cal(modbus1Buf, 6); +// modbus1Buf[6] = crc16.b8[0]; +// modbus1Buf[7] = crc16.b8[1]; + +// modbus1FaaRxFlg = 1; + MODBUS1_UART_IT_RX_DISABLE; + } +} + +/**************************************** +**** MODBUS Fbb CADC增益校准 ***** +** M: 01 BB D1 D2 D3 D4 CRCL H ** +** S: 01 BB 5B B5 03 04 CRCL H OK ** +** S: 01 BB 5B B5 05 06 CRCL H FAIL** +*****************************************/ +void MODBUS1_Fbb_Rx(uint8_t *mem) +{ + BYTE2 crc16; + + //CRC判断 + crc16 = CRC16_Cal(modbus1Buf, 6); + if( (modbus1Buf[7] == crc16.b8[1]) || (modbus1Buf[6] == crc16.b8[0]) ) + { + cali.current = modbus1Buf[2]<<24 | modbus1Buf[3]<<16 | modbus1Buf[4]<<8 | modbus1Buf[5]; + cali.cmdGain = 1; + +// crc16 = CRC16_Cal(modbus1Buf, 6); +// modbus1Buf[6] = crc16.b8[0]; +// modbus1Buf[7] = crc16.b8[1]; + +// modbus1FbbRxFlg = 1; + MODBUS1_UART_IT_RX_DISABLE; + } +} +(L486) + modbus1F10RxFlg = 0; + modbus1FaaRxFlg = 0; + modbus1FbbRxFlg = 0; + modbus1FddRxFlg = 0; + modbus1FeeRxFlg = 0; +(L64) +/**************************************** +**** 按顺序读记录 ***** +** M: A1 dd 10 00 00 00 CRCL H ** +** S: A1 dd 10 00 d0-51 CRCL H ** +*****************************************/ +void UART3_ReadRecord(void) +{ + BYTE2 crc16; + + //CRC判断 + crc16 = CRC16_Cal(modbus1Buf, 6); + if( (modbus1Buf[7] == crc16.b8[1]) || (modbus1Buf[6] == crc16.b8[0]) ) + { + modbus1FddRxFlg = 1; + MODBUS1_UART_IT_RX_DISABLE; + } + else + { + MODBUS1_Init(); //没加这个时，换地址通讯连接不上，待监控时间到重新初始化之后才恢复连接 + } +} + +/**************************************** +**** 清除EEPROM内的记录 ***** +** M: A2 ee 00 55 00 aa CRCL H ** +** S: A2 ee 00 55 00 aa CRCL H ** +*****************************************/ +void UART3_ClearRecord(void) +{ + uint16_t i; + uint16_t pc; //待写入地址 + uint8_t adrh,adrl; + uint8_t wrBuf[64]; + BYTE2 crc16; + + //CRC判断 + crc16 = CRC16_Cal(modbus1Buf, 6); + if( (modbus1Buf[7] == crc16.b8[1]) || (modbus1Buf[6] == crc16.b8[0]) ) + { + soe.index = 0; //起始序号0 + soe.pc = 0x1000; //起始地址0x1000 + soe.num = 0; //起始数量0 + + wrBuf[0] = (soe.index >> 24) & 0xff ; + wrBuf[1] = (soe.index >> 16) & 0xff ; + wrBuf[2] = (soe.index >> 8) & 0xff ; + wrBuf[3] = (soe.index >> 0) & 0xff ; + wrBuf[4] = (soe.pc >>8)&0XFF ; + wrBuf[5] = soe.pc & 0xff ; + wrBuf[6] = (soe.num >>8)&0XFF ; + wrBuf[7] = soe.num & 0xff ; + + EEPROM_WrMulByte(0x08,0x00,8,wrBuf); + delay_ms(10); + + pc = 0x1000; + for(i=0;i<52;i++) + { + wrBuf[i] = 0xff; + } + for(i=0;i<50;i++) + { + adrh = (pc>>8) & 0xff; + adrl = pc & 0xff; + EEPROM_WrMulByte(adrh,adrl,52,wrBuf); + delay_ms(10); + + pc += 0x40; + } + + + EEPROM_RdMulByte(0x08,0x04,4,&modbus1Buf[2]); //当前序号 + + crc16 = CRC16_Cal(modbus1Buf, 6); + modbus1Buf[6] = crc16.b8[0]; + modbus1Buf[7] = crc16.b8[1]; + + modbus1FeeRxFlg = 1; + MODBUS1_UART_IT_RX_DISABLE; + } + else + { + MODBUS1_Init(); //没加这个时，换地址通讯连接不上，待监控时间到重新初始化之后才恢复连接 + } +} +(L583) +//一定时间没有接收到数据，初始化MODBUS1通讯 +void MODBUS1_TIM_Moni(void) +{ + modbus1MoniCount--; + if(modbus1MoniCount == 0) + { + MODBUS1_Init(); + } +} + +【global.h】//增加 +(L643) +extern void UART3_ReadRecord(void); +extern void UART3_ClearRecord(void); +(L645) +extern void MODBUS1_F10_Rx(uint8_t *mem); +extern void MODBUS1_Faa_Rx(uint8_t *mem); +extern void MODBUS1_Fbb_Rx(uint8_t *mem); +(L58) +extern uint8_t modbus1FaaRxFlg; //CADC零点校准数据接收正确标记 +extern uint8_t modbus1FbbRxFlg; //CADC增益校准数据接收正确标记 +(L641) +extern void MODBUS1_TIM_Moni(void); + +【AFE_SH367309.c】 +CALI_CurrentProcess()加上 +modbus1FaaRxFlg +modbus1FbbRxFlg + +【tim.c】(L103) + MODBUS1_TIM_Moni(); + + +////////////////////高温会让均衡状态消失 [V0.0.19.01] + + +////////////////////容量可以写1~1000Ah，但发现此时写SOC=100%会失败 [V0.0.19.02] +if(bmsMem.rcc >= bmsMem.fcc+1000000) +//将rcc的类型改为uint32_t，当rcc被减到小于0时，会以极大值显示，故在满充容量上增加1000A的误差值后，以进行是否小于0的判断 + + +1.17 +////////////////////原本一直用Ctrl引脚来控制MOS关闭 [V0.0.19.03] +//现在换用写RAM方式进行MCU控制的保护，且只关单边 +//急停还是使用CTRL，但可以删去判断自身是否报警这一个了 + + +////////////////////温度保护的触发和当前状态无关 [V0.0.19.04] +//但电流判断是要根据实际状态的 + + +////////////////////轮询卡在地址2通信上的BUG修复 [V0.0.19.05] + + +////////////////////充放电MOS故障，原来只走DO动作 [V0.0.19.06] +//自身对充放电MOS故障也要行动，在出现故障后，就算之前把MOS关闭的其他原因消失了，也会一直维持控制MOS关闭的状态 +//奇怪，如果在置标志位后计数清零，故障又会消失和出现来回跳 +//所以要清零也是在报警条件消失后 + +Program Size: Code=56158 RO-data=3430 RW-data=156 ZI-data=3988 +56158+3430+156=59,744≈58.3K + +////////////////////地址1才进行逆变器通信 + + +1.19 +////////////////////屏幕代码量优化 [V0.0.19.07] +之前 +Program Size: Code=56138 RO-data=3430 RW-data=156 ZI-data=3988 +之后 +Program Size: Code=54958 RO-data=3430 RW-data=156 ZI-data=3988 + + +1.23 +////////////////////所有已有协议，在SOC<=10%时触发禁放 [V0.0.19.08] +【已加】 +CAN: +Sol-Ark,GoodWe固德威,Growatt古瑞瓦特,Aiswei爱士惟,MUST美世乐,JOHNRAY晶锐鸿,Pylon派能,Sacolar尚科,Luxpower深圳鹏城,Schneider施耐德,Sigineer赛吉纳,Senergy盛能杰,Victron维克托,Megarevo迈格瑞能,Afore艾伏,GSSTES精石 +MODBUS: +Voltronic日月元,SMK + +【没有相关状态位的】 +CAN:SMA艾思玛,Sorotec索瑞德,DONNERGY大能,SOFAR首航,Deye德业 +MODBUS:SRNE硕日 + +思考：MUST的强充强放指令删去；Pylon的强充指令对应特定型号US2000B所以暂不加；精石和Deye是Pylon的缩略版 + + +////////////////////将所有协议改为1s发送1包 [V0.0.19.09] +//艾伏协议放到1s里面而不是0.5s + + +Program Size: Code=56714 RO-data=3430 RW-data=160 ZI-data=3984 +56714+3430+160 = 60304 +////////////////////日月元协议回复优化 [V0.0.19.10] +日月元协议和标准485协议不同： +当是日月元协议时，数据长度占2个字节 +日月元协议里的协议类型和协议版本，数据为00 00 01 00(前几个地址的数据都补充完整) + +通信都是uint8_t类型，通信结构是“先高字节再低字节” +若定义的变量是 +2个uint8_t组成2字节，那要先低后高(会在发送前在通信函数里调换) +1个uint16_t组成2字节,那正常输出 +2个uint16_t组成4字节，那要先高后低(不受通信函数调换影响，正常先高后低) + + +////////////////////优化代码 [V0.0.19.11] +Program Size: Code=56714 RO-data=3430 RW-data=160 ZI-data=3984 +·温度保护的判断：用最低最高温度而不是4路温度都比较 + Program Size: Code=56610 RO-data=3430 RW-data=160 ZI-data=3984 +·写封装好的CAN报文生成函数send + 所有标准帧CAN协议完成： + 扩展帧也包含在函数里 (MUST是扩展帧，只有这1个) + 把CAN_SendCount++;放到Send函数里 + Program Size: Code=46146 RO-data=4030 RW-data=160 ZI-data=3984 + 46146+4030+160 = 50336 + +加上[V0.0.19.10]后的代码量： +Program Size: Code=46258 RO-data=3918 RW-data=160 ZI-data=3984 +46258+3918+160 = 50336 + + +////////////////////HpPlus改为Xindun + +////////////////////上位机选协议 [V0.0.19.12] +·参考03读数据的报文，但是实际功能是特殊的 +·上位机发送协议序号和协议名字符最大个数16 +·BMS回复协议序号和协议名表示选择成功；回复空数据表示无法选择/选择失败；长时间不收到回复表示超时 +·(目前只在V2.x上位机上可用) + +Program Size: Code=46710 RO-data=3466 RW-data=740 ZI-data=3988 +46710+3466+740 = 50916 + + +////////////////////增加CAN定时器函数，超时不收到305数据就会初始化 [V0.0.19.13] +Program Size: Code=46782 RO-data=3718 RW-data=740 ZI-data=3988 +46782+3718+740 = 51240 + + +////////////////////Sorotec协议有缺，全部协议复查一遍 [V0.0.19.14] +复查完成，只有Sorotec的电压/电流/平均温度没有正常赋值 +Program Size: Code=46794 RO-data=3706 RW-data=740 ZI-data=3988 +46794+3706+740 = 51240 + + +////////////////////若CRC校验错误，但没有初始化，会导致通信状态异常，无法接收下一帧数据 [V0.0.19.15] +03 10 aa bb的函数里都要加上 +Program Size: Code=46826 RO-data=3674 RW-data=740 ZI-data=3988 + + +////////////////////整理单独一个函数用于落实上位机的写地址功能 [V0.0.19.16] + + +////////////////////MODBUS_Init使用情况整理 [V0.0.19.17] +·if(modbusBufIndex > 2)对应的else部分都删去，以免不必要的初始化 +·具体表现应该是插拔时候就会初始化 + + +////////////////////Growatt-485协议 [V0.33.0.0] +Sorotec相同 + + +////////////////////扩充轮询数据 [V0.0.19.18] +·主机要收集从机的最大最小温度，才能知道实际最大温度是多少 +·最高最低电压能获得所有数据的之后，就把逆变器协议里的相关赋值都改掉 + +////////////////////3.4网口的初始化，标志位清零完善 + + +////////////////////轮询出现未连从机报警值出现问题 [V0.0.19.19] +·轮询获得从机报警时，先再次询问， + 若仍有回复，那就记录更新并继续轮询下一个 + 若没有回复，说明可能是电平波动导致，清空当前从机的数据 + + +////////////////////MODBUS的地址大小问题 [V0.0.19.20] +·03和10的求取地址，因为在处理时要<<1，所以实际得到的值应该存放在uint16_t中 +·CRC校验，要&&而不是|| + + +////////////////////通信协议里的平均温度，应该传递的是所有机子的平均温度 [V0.0.19.21] +//额外改动了一下Growatt的内容的先后 + + +////////////////////提高轮询速度 [V0.0.19.22] +·主从机轮询时间1s一个实在有点慢，串口的通信波特率9600，其实很快就传完了 + 发02 03 00 4B 00 0D F4 2A （8BIT） + 收02 03 1A 00 00 00 03 63 44 FF FA 0B 79 0C 97 0C 87 00 0D 00 0F 0B 82 0B 71 00 02 00 01 1E 50 （31BIT） + 总共就0.0040625s +·采用400ms完成一个从机的轮询，前200ms发，后200ms处理收并回复 + (试过100s一个收发的，但是时间太短处理不了数据，200ms的客户测试过也不太行) +·删去轮询函数里，若总线上有数据就延时的动作，3.4网口纯作为主从机通信用 +·将初始化的延时等待统一定为10s + +·分析TIMER_IsOut函数： + 使用格式是 + if(TIMER_IsOut(tmrTemp[a],b)) + { + tmrTemp[a] = TIMER_Update(); + ... + } + a:定义了一个数组，用以区分不同的时间间隔 + b:时间间隔 = 10ms x b + tmrTemp[a]:到了时间进入判断时,更新为此时的tmrSys值 + uint32_t TIMER_IsOut(uint32_t cnt, uint32_t tmr) + { + uint32_t tmp = tmrSys; + + tmp = cnt > tmp ? ( (uint32_t)(-1) - cnt + tmp ) : ( tmp-cnt ); + + if(tmp>=tmr) + return 1; + else + return 0; + } + 比较上次进入判断时的tmrSys值和现在的tmrSys值，差值足够大就回复1 + 若上次的大，说明值很可能溢出了： + (uint32_t)(-1) - cnt + tmp：用0xFFFF-上次的tmrSys值 + 现在的tmrSys值，得到差值 + 若这次的大(一般都是这次大)： +tmp-cnt：得到差值 + + +////////////////////SOC满充校准 逆变器限压值(57.6V)+2A [V0.0.19.23] + +////////////////////protocol的额外定义放在global.h中 + + +////////////////////设定一个结构体，专门放置特定测试写入和更改 [V0.0.19.24] +结构体： +功能码：f3->03 f4->10 +保存方式：EEPROM，从地址0x0400开始 +·要改多少就向EEPROM里写多少 + + +////////////////////主动均衡启动参数，上位机可设 +*采用弹窗形式，单独写（毕竟不是所有人都要配置主动均衡） +主动均衡 默认值 变量名 +开启电压 50mV act_bal_startV uint8_t +释放电压 30mV act_bal_stopV uint8_t +释放延时 600s act_bal_stopT uint16_t +////////////////////休眠时间和启用标志 +默认值 +0 代表启用 +60min 代表休眠时间60min + + +////////////////////主动均衡参数值放入实际使用中 [V0.0.19.25] + + +////////////////////休眠功能 [V0.0.19.26] +不充电不放电状态(2A以下)持续1h，且无任何通信设备接入，启用休眠模式 + +正常状态下，只有充放电会更新休眠计时； +休眠模式下，出现充电/通信/点亮屏幕/操作屏幕操作，更新休眠计时，退出休眠 + +或许加上： +执行休眠前，会在5s内检测是否有通信/屏幕操作，若有的话就更新休眠计时，不进入休眠； +(这样的好处是：休眠计时过程中，进行短暂的通信或屏幕操作，不影响休眠计时； +只有在要进入休眠的时候，若正在用通信维持板子正常运行，就不用进入休眠再出来，直接更新休眠时间) + +enable标志会控制sleepFlag是否可以成为1 + + +////////////////////ParaMem在EEPROM的地址问题和读取问题 [V0.0.19.27] +·IIC初始化中，读取有点问题，要改正 +·ParaMem写入EEPROM中时，地址是uint8类型对应的，原来写的有问题，要改正 + 因为上位机的报文已经有过了，所以ParaMem不动，只修改EEPROM的存放地址 +·EEPROM可用地址有0x0400~0x06FF，每个地址对应一个uint8_t字符 +·ParaMem用于MODBUS通信，通信时的每个地址对应一个uint16_t字符，LENTH对应16时的长度，2*LENTH对应8时的长度 + + +////////////////////单体欠压报警时放电MOS关闭 [V0.0.19.28] +·增加手动按钮，按下后把原AFE值写入EEPROM，然后将现AFE欠压报警值赋值500mV，并计时5min，到时间后读出EEPROM的值并写入AFE中 +·屏幕地址：按钮按下0291 按钮变色0290 计时文本02A0 +·状态位使用bmsMem.balanceStatus的bit5:0x20 + (注意协议中带平衡标志位的，赋值改动) + + +////////////////////状态位中增加部分状态显示 [V0.0.19.29] +限流板启动状态 +bmsMem.balanceStatus |= 0x0010; +手动关欠压启动状态 +bmsMem.balanceStatus |= 0x0020; +DO继电器状态 +bmsMem.temperaStatus |= 0x0080; +(预充状态) +bmsMem.bStatus3 |= 0x0020; +(预充失败) +bmsMem.bStatus2 |= 0x0020; + + +6.26 +////////////////////版本号用0而不是0x00,防止之后超过9的数字写错。只有特殊需要'A'之类的再用0xA0 + +////////////////////特殊屏幕按钮，按下会将EEPROM的0x0200~0x2000都清空 [V0.0.19.30] + + +6.28 +////////////////////因为更换了采样电阻，增益校准值要改动，原3225，现在改为7000 [V0.0.19.31] + + + + +7.1 +////////////////////限流板启用前，只关闭充电MOS，放电MOS保持开启以防止出现问题 [V0.0.19.32] + +////////////////////重整MOS和限流板的控制逻辑 [V0.0.19.33] +·重点：只让急停和充电相关报警，会关闭限流 + 休眠时会关闭放电MOS，但保持充电MOS和限流板当前状态，使可以在常态时充电唤醒 + +·[触发急停]充电MOS、放电MOS、限流板都关闭 +·[进入休眠]关闭放电MOS，不影响充电MOS和限流板状态 +·[触发充电相关报警]充电MOS关闭，限流板关闭，不影响放电MOS状态 +·[触发放电相关报警]放电MOS关闭，不影响充电MOS和限流板状态 +·[触发限流]充电MOS关闭，限流板打开，不影响放电MOS状态 +·[正常状态]充放MOS打开，限流板关闭 + + (充电相关报警：单体过压，充电过流，充电高温，充电低温，充电MOS故障) + (放电相关报警：单体欠压，放电过流，短路保护，放电高温，放电低温，放电MOS故障) + +·AFE的低功耗模式/仓运模式，会将充放电MOS都关闭，所以不能走这个 +·AFE正常工作时，如果AFE检测到过压、充电过流、充电过温，也会把充电MOS关闭，所以休眠保持充电MOS开启，也要考虑到是否满足充电条件 + + +7.4 +////////////////////把EEPROM读写的调用代码中的变量值统一#define在一起，方便之后管理 [V0.0.19.34] +·初始化时，若EEPROM里没有数据，赋默认值，但不进行写操作 +·若值有明确的范围，则判断条件直接是是否在范围内；若没有，则判断条件是EEPROM里都是0xff；电流校准值特殊，是判断另一个值是不是^的值 +·soe.tim和soe.timEn的EEPROM读写相关，都删掉 + +////////////////////零点校准和增益校准的地址和个数都要变 [V0.0.19.35] +·放在不更新区中 +·个数保留4位，前2位有效位，后2位是取异或^ +·在按下特殊EEPROM清空按钮后，程序会根据当前(3,0,4)有没有数据来决定是否要搬移零点+增益校准数据到现在程序的对应位置 + +////////////////////整理EEPROM的地址，重新放置 [V0.0.19.36] +·容量、SOC、协议是可能需要之后改默认值的 +·执行逻辑的过程量也很可能是变动值 + ParaMem里的值最好要升级即改 + + [0x0000~0x01FF]——不会因任何动作，而初始化的值 +·bmsMem.E2_485Addr 485通讯地址 0x0000 1 位置不变 +·Update_Index IAP标志位 0x0001 1 位置不变 +·bmsMem.ee_uv AFE欠压保护值 0x0004 1 位置不变 +·bmsMem.cadcZero 零点校准 0x0008 4 旧位置(2, 0, 8) +·bmsMem.cadcGain 增益校准 0x000C 4 旧位置(3, 0, 8) +·待增加：BMS生产批次，PACK生产批次 + + [0x0200~0x03FF]——程序升级不会变动的值，但可以通过特定屏幕的特殊按钮，初始化为程序里想要的初始值 +·capacity_Ah 容量Ah 0x0200 2 旧位置(7, 1, 2) +·bmsMem.soc SOC 0x0202 1 旧位置(0,64, 1) +·protocol 协议选择 0x0203 1 旧位置(7, 0, 1) +·待增加：累计容量、循环次数 + + [0x0400~0x07FF]——程序升级就会刷新此处存放数据，一般都是过程量 +·paraMem.act_bal_… 主动均衡参数 0x0400 4 位置不变 +·paraMem.sleep_… 定时休眠参数 0x0420 2 位置不变 +·在Flash里也找个地方存放该值，（但因为需要单独参数读写，所以最好放在EEPROM里） + 程序烧录后，uf_FLASH_Init()函数读EEPROM值和Flash新烧录的值比对，若不同就将Flash里的值写入EEPROM中 +·待增加：SOH计算系数：当cycCount小于等于_a_次时，SOH保持100%，当cycCount大于_a_且小于等于最大限制_b_时，SOH=99-(99-c)*(cycCount-a)/(b-a)，SOH最低降到_c_% + +////////////////////优化Para写操作时的define，不局限在0x04 +#define EE_PARA_WRITE adrh,adrl,len + + +7.8 +////////////////////EEPROM存放数据的范围 [V0.0.19.37] +·当初始化读EEPROM的数据时，要检验是否在适用范围内 + +·当通过通信/屏幕写入数据时，要检验是否在适用范围内 + bmsMem.E2_485Addr在if(bmsMem.write_Addr !=0)以外，还要判断是否在可选范围内 + bmsMem.soc在if(bmsMem.write_Soc !=0)以外，还要判断是否在可选范围内 + +·ee_uv的写入地址错了 +·清除前的电流增益值的写入写成了读出 +·容量的初始化值，不会在第一次读非法值就写入100 + + +////////////////////SOC=0的报文是 [V0.0.19.38] +Adr 10 [00 4a 00 01 02 00 00] crc1 crc2 +在程序里特意做补丁，如果是特定的这个报文，直接和bmsMem.write_soc一样的操作，写SOC=0 + + +////////////////////休眠功能，之前都写少了一部分，就是电流更新！ [V0.0.19.39] + //存在充电或放电，休眠起始点更新 + if((bmsMem.packCurrent <= (-2000)) || (bmsMem.packCurrent >= 2000)) + { + if((paraMem.sleep_min_disable & 0x8000) == 0) //启用 + { + sleeptimecount=RTC_GetCounter(); + sleep_flag = 0; + } + } + + +////////////////////电量低于10%，触发强充 [V0.0.19.40] +·原触发禁放功能的变量，现在也触发强充(之后可写入时再改分开) + +////////////////////增加锦浪协议和Pylon电总协议 [V0.35.0.0] +·锦浪有强充标志，补上 +·Pylon电总的强充禁放标志都要补上 + +////////////////////协议里的温度值应该取canMem[0]. [V0.0.19.41] +·平均温度，应该取canMem[0].temp而不是TemperatureAverage +·最高最低温度，应该取canMem[0].TempMax…… + +////////////////////协议里的电压值应该取canMem[0]. [V0.0.19.42] +·最高最低电压，应该取canMem[0].VolMax…… + +////////////////////汇总最高最低温度电压 的序号 的计算，已修正 [V0.0.19.43] + + +////////////////////当电池放电时，限流状态关闭 [V0.0.19.44] +·经实验，放电时若限流板保持开启，会导致限流板的电感特别热 + +////////////////////限压+2A程序，限压*100 [V0.0.19.45] + +////////////////////Pylon电总协议的回复还没加上，现在已加 [V0.0.19.46] + +////////////////////上位机选协议相关-锦浪协议 [V0.0.19.47] + + +7.15 +////////////////////EEPROM特定清除按钮，范围减少只有0x0200-0x03FF [V0.0.19.48] +这部分保存电池的基本信息，包括满充容量、SOC、当前协议、累计容量、循环次数…… +在出货前最好清零，为了 + + + +////////////////////读旧电流值 [V0.0.19.49] +·初始化获取电流校准值前，没有进行容量、SOC、协议选择的写入 +·先获得现在地址的校准值，若是无效值，说明此前没校准过/是旧程序 +·再读取旧地址的校准值，若存在，则赋值给新校准值的地址，并把旧地址的电流校准值清空 +·赋值 + + +////////////////////当电池SOC在15%以上，电池电压降到50V，并持续2分钟，SOC需重置校准到15%（低于15%不做处理） [0.0.19.50] +当总电压小于等于50V且SOC大于15%，Cali_Soc_Flag = 1; 启用延时；若总电压恢复到50V以上或SOC已经小于15%，Cali_Soc_flag = 0; 重新计时 +延时持续2*60*100个10ms后，说明持续了2分钟，此时若SOC大于15，让bmsMem.soc = 15; + + +////////////////////AFE写入时，不跳电流 [V0.0.19.51] +·之前在更新AFE时，电流值会跳动，导致有电流值显示，容易影响100%跳99% +·当更新AFE操作执行后，置标志位1，使之后执行的计算赋值电流时值直接=0，再下一秒就按照正常执行 + + +////////////////////Flash_A/B中也存放EEPROM里的ParaMem参数变量 [V0.0.19.52] +·因为修改Flash会把其余位置更新为0xFF，所以Flash相关操作要一起做 + 初始化时Flash更新到结构体，AFE和para一起做 + 在写入数据后，AFE和para更新也要一起做 +·如果升级程序，会通过更新Flash_A/B的方式更新ParaMem的值 +·平时改在ParaMem里的参数，会通过先改Flash值再改EEPROM的值操作 + +·原来在uf_I2C1_Init()的读默认值操作，和在MODBUS1_F10_Rx()的记录写Para地址并在Config_WritePara()进行烧录EEPROM操作相关，都没用了删掉，变量也删掉 +·AFE_UpdateConfig()函数更名为AFE_UpdatePara() + + +****初始化参数**** +////////////////////100A+6.0.0(默认) +////////////////////50mV192us +70 0f 6e ee 62 c6 7d 87 af 78 64 c3 [08] [0b] [03] [0a] 50 64 46 ec f6 64 46 ec f6 [f5] +41 37 02 05 41 37 fb fe [69] [69] 08 08 1e [23] +[64] 05 58 02 +40 02 a0 01 [e8] [03] [e8] [03] + +////////////////////150A+6.0.0 +////////////////////50mV192us +70 0f 6e ee 62 c6 7d 87 af 78 64 c3 [08] [0b] [03] [0a] 50 64 46 ec f6 64 46 ec f6 [f5] +41 37 02 05 41 37 fb fe [9b] [9b] 08 08 1e [c1] +[96] 05 58 02 +40 02 a0 01 [dc] [05] [dc] [05] + +////////////////////200A+6.0.P +////////////////////80mV192us +70 0f 6e ee 62 c6 7d 87 af 78 64 c3 [18] [1b] [13] [1a] 50 64 46 ec f6 64 46 ec f6 [24] +41 37 02 05 41 37 fb fe [cd] [cd] 08 08 1e [f8] +[c8] 05 58 02 +40 02 a0 01 [d0] [07] [d0] [07] + + +////////////////////休眠默认启用+24*60min [V0.0.19.53] +·休眠最大可设32767min=546h=22d +·24*60=1440=0x05A0 + + +////////////////////满充的总压判定-6V，防止有些性能稍差的电池无法充满 [V0.0.19.54] + + + + +8.8 +////////////////////重新整理GPIO初始化电平 + +////////////////////限流关闭逻辑优化 [V0.0.19.55] +·之前控制限流关闭的充电报警，只囊括了MCU本身的充电报警， + AFE的充电过流保护、充电过压保护、充电高温/低温保护等都应当可以关闭限流，在CHG_LIMIT_Ctrl()函数里 +if(((bmsMem.bStatus1 & 0x51) != 0) || ((bmsMem.bStatus2 & 0x83) != 0) || ((bmsMem.temperaStatus & 0x15) != 0)) + +////////////////////更完善的预充逻辑 [V0.0.19.56] +·预充因为短路引起 +1.短路报警刚发生时： + 关闭所有MOS，启动预充。 +2.短路报警持续显示时： + 充放MOS保持关闭，预充电路保持开启，注意此时的实时电流。 + 正常预充过程中，电流会越来越小。当连续4s有超过1.9A的电流，判断应该是真短路，关闭预充电路，并保持关闭充放MOS，显示“预充失败”。 +3.短路报警消失后： + 充放MOS保持关闭，预充MOS从开启变为关闭，测量负载端电压。 + 若负载端电压约等于电池电压 + 预充结束，开启充放MOS + 若负载端电压仍低于电池电压（可能性应该较小） + 充放MOS保持关闭 + 启动预充，继续给负载端充电，每持续4s后关闭预充进行1次检测 + 若检测到，负载端电压约等于电池电压，预充结束，开启充放MOS + 若持续10次检测到，负载端电压仍然低于电池电压，充放MSO保持关闭，显示“预充失败” +*8.16补充：预充电流值=电池总压/30欧姆，短路判断在这之上-0.1A即可，4s暂时不改 + 预充失败放入报警记录,屏幕显示是PCHG_Fail，预充失败会亮报警灯和屏幕显示报警 +*8.20补充：短路判断不用电流值算了，现在是： + 预充开启后先充1s然后关上，检测负载电压，若低于10V(测试看到的短路情况是5V)说明是真短路，显示预充失败 + 预充计时变量的赋值优化了下，会在判断启动预充的时候初始化 + +////////////////////预充状态和预充失败显示 [V0.0.19.57] +·预充状态：bStatus3 bit5 + bmsMem.bStatus3 = temp[2] & 0xdb; //bit2、bit5用在其他地方 + bmsMem.bStatus3 |= 0x0020; //预充状态开启 +·预充MOS状态：bStatus3 bit2 (屏蔽原来AFE的预充MOS状态，放入MCU控制的) + bmsMem.bStatus3 = temp[2] & 0xdb; //bit2、bit5用在其他地方 + bmsMem.bStatus3 |= 0x0004; //预充MOS打开 +·预充失败：bStatus2 bit5 + bmsMem.bStatus2 |= 0x0020; //预充失败 +*8.30补充：轮询数据的报警状态判断，要增加预充失败报警 + + + + +////////////////////屏幕reset按键相关，不需要移动电流校准值了 + +////////////////////bmsMem限流变量去掉write_ + +////////////////////packStatus内容修改，删去EEPROM写入失败标志，缩减EEPROM更新标志为1bit + + + + +////////////////////增加禁放强充标志的释放值，20% [V0.0.19.58] +·Deye的特殊值：<=5%启动强充>=10%释放，是Deye特有，和标准版分开来 + 标准版：<10%启动>20%释放 +·之前协议里只有启用没有强充标志的释放，现在把强充加上 + +////////////////////没有禁放标志的协议，也可以通过改动放电限流值来进行禁放 [V0.0.19.59] +·这样所有协议都至少带禁放功能了 + +////////////////////Pylon电总内容更新：逆变器充放电限压限流 [V0.0.19.60] + +////////////////////Pylon CAN协议的最大最小温度/10,单位1K而不是0.1K [V0.0.19.61] + + + + +////////////////////在SOC<99时，达到满充过压条件，会跳转屏幕报警页后再校准SOC，已修复 [V0.0.19.62] +·把单体过压的跳转单独拎出来，在满充校准之后进行判定 + +////////////////////轮询汇总后计算最值时，要进行在线的判断 [V0.0.19.63] + + +****初始化参数**** +【短路改为50mV0us，最大程度保护板子】 +////////////////////100A+6.0.0(默认) +70 0f 6e ee 62 c6 7d 87 af 78 64 c3 [08] [0b] [00] [0a] 50 64 46 ec f6 64 46 ec f6 [d4] +41 37 02 05 41 37 fb fe [69] [69] 08 08 1e [23] +[64] 05 58 02 +40 02 a0 01 [e8] [03] [e8] [03] + +////////////////////150A+6.0.0 +70 0f 6e ee 62 c6 7d 87 af 78 64 c3 [08] [0b] [00] [0a] 50 64 46 ec f6 64 46 ec f6 [d4] +41 37 02 05 41 37 fb fe [9b] [9b] 08 08 1e [c1] +[96] 05 58 02 +40 02 a0 01 [dc] [05] [dc] [05] + +////////////////////200A+6.0.P +70 0f 6e ee 62 c6 7d 87 af 78 64 c3 [18] [1b] [00] [1a] 50 64 46 ec f6 64 46 ec f6 [f2] +41 37 02 05 41 37 fb fe [cd] [cd] 08 08 1e [f8] +[c8] 05 58 02 +40 02 a0 01 [d0] [07] [d0] [07] + + + + +9.4 +////////////////////在休眠前存在报警，休眠后也会关闭报警灯 [V0.0.19.64] + + +9.10 +////////////////////增加盛弘协议 [V0.36.0.0] +函数、调用、上位机选择 + + +9.11 +////////////////////MOS故障判定持续30s [V0.0.19.65] +·只修改MOS故障判定时间30s，故障释放仍然3s + + +9.18 +///////////////////屏幕协议选择的优化 [V0.0.19.66] + + +9.19 +///////////////////清空IAP底层标志位的操作，优化为根据EEPROM的值操作 [V0.0.19.67] + + +9.24 +////////////////////在换协议后，更新CAN波特率 [V0.0.19.68] + + +9.27 +///////////////////删记录之前，判断是否有可删除的记录 [V0.0.19.69] +///////////////////上位机/屏幕删记录后，屏幕也会更新 [V0.0.19.70] + + + + +8.12 +////////////////////屏幕设置参数，参考美国版屏幕 [V0.0.20.00] +*9.12 短路参数50mV0us配合最新预充；过压保护和过压释放电压只修改电压相关，其他的延时都不变 + + +8.13 +////////////////////报警记录上限100条 [V0.0.20.01] +·屏幕上屏蔽101和102的代码还要加上 + + +////////////////////报警记录重新整理，包含单芯电压和温度 [V0.0.20.02] +·屏幕上只显示是什么报警，如果EE_SOE结构体变化，程序里自己改动即可，不担心兼容问题 +·上位机通过功能码0xdd求取报警记录： +——发送报文不改动，根据对回复的判断，采用不同的解析方式 + 上位机: SlaveID DD addrH addrL 00 00 CRCL CRCH + BMS回复:SlaveID DD addrH addrL DATA0~51 CRCL CRCH +·addr=0x1000+k*0x40 + 50条：0x1000~0x1C40 + 100条：0x1000~0x28C0 +·EEPROM一个扇区是0x40=64个uint8类型大小， + 目前已用52个，还剩12个是不够放单芯电压的 + 重新整理wrBuf[64] +*9.2 存储格式更正，使具体数据可以正常在上位机显示 + + +////////////////////能通过判断兼容之前的报警记录格式 [V0.0.20.03] + +////////////////////屏幕时间格式 [V0.0.20.04] + + + + +////////////////////计算循环次数 [V0.0.20.05] +·每当充电让rcc增加1Ah,累积容量也增加1Ah +·累计容量超过总容量的90%，增加一次循环次数 + +////////////////////计算SOH和paraMem里的过程变量 [V0.0.20.06] +·在循环次数<=200次时，保持SOH=100% +·在循环次数>200次时，SOH从99%开始降低，当达到最大6000次时，对应SOH=70%，再下降也不会超过6000次了 +·SOH值不需要存储，只需要随时根据当前循环次数和计算过程变量来得出即可 + +////////////////////上位机读写循环次数、paraMem里的过程变量 [V0.0.20.07] +·循环次数通过采集可以读出来，主要就是写入——干脆直接修改原值算了，就当只能上位机可写，写超过最大值也会改成最大值 +·SOH不可写，但是存在并因为各种参数而改动——和packStatus挤一挤，能够采集到，也只有packStatus这里可以挤 +·ParaMem的过程变量只要对应好位置即可 + + + + +////////////////////SN号的使用，和屏幕显示版本号和SN号 [V0.0.20.08] +·版本号共2x9位，再加上一个crc8校验码，存放在EEPROM中 + 若crc校验出错，则值为0，上位机读出该值不显示，但屏幕正常显示(不好空着) +·屏幕地址： + 电池ID 02C0 + BMS ID 02CD + 硬件版本 02D6 + 软件版本 02DE +*9.11 SN号不需要0x30+ + + +////////////////////上位机读写SN号 [V0.0.20.09] +·上位机读0x55中的长度增加，将SN号都囊括 + 若收到的SN号值都是0，就清空不显示 +·收到写入的SN号后，在回复时写入EEPROM +·将F10的回复做一个判断，根据功能码来做存储 + + +////////////////////屏幕设置参数增加范围判断 [V0.0.20.10] +·若设置保护值，默认同步修改释放值 +·若设置释放值，不能超过保护值 +·涉及参数：单体过压和释放、单体欠压和释放、充电低温/高温和释放、放电低温/高温和释放 + + + + +////////////////////上位机连主机，获取在线信息 [V0.0.20.11] +·上位机向主机间隔请求并机信息，应当是个结构体 +·接主机1口，若上位机切换询问地址，主机可能会当成对自己连接的从机信息的求取，故要把对主机请求从机信息的功能码改动，以做区分 + + +////////////////////程序已超过59K，标志消除对应地址变为128K [V0.0.20.12] + + +////////////////////上位机显示屏幕版本号，仍保持原来的1字节 [V0.0.20.13] +·0xFF=1111 1111 + 2进制里，最高两位表示型号，01对应035，10对应043，11对应070(或就当特殊种来用，070先只处理前8个位置)，00预留暂表示不含屏幕(如果要用也要避开0x00.0x01.0x02.0x03这些) + 2进制的剩下6位表示序号Index，范围0~63，显示为1~64。 + 注意！没写过的时候，显示按04301来，得出的值是【0x80=1000 0000】。而读出0xFF不算数，即070的情况下，序号只能1~63 +·版本号和屏幕号的位置不能动，这涉及到上位机的读取，动了就和以前的上位机不兼容 +01 56 00 01 00 00 01 41 4b a2 + + + + +////////////////////参数初始化按钮变更 [V0.0.20.14] +·参数初始化按钮 +0x01A4 图标颜色 +0x0125->0x01A5 指令地址 + +////////////////////屏幕写SOC [V0.0.20.15] +·SOC校准 +0X0126 SOC输入和显示 + + + + +////////////////////优化屏幕选协议部分 [V0.0.20.16] + +////////////////////屏幕进行电流校准 [V0.0.20.17] +·只显示 +0X01A8~01A9 数据变量 pack电流值 +·增益系数，可改 +0X01A1~01A2 数据变量 增益系数 +·按钮 +0X012A 变量图标 零点校准 +0X012B 增量调节 +0X012C 变量图标 增益校准 +0X012D 增量调节 + + + + +////////////////////切换语言 [V0.0.20.18] +·语言切换 +0X01A0 变量图标 +0X0127 菜单的2个语言的按钮 +·报文 +A5 5A 06 83 01 27 01 00 00/01[中文/英文] + +////////////////////优化屏幕参数初始化参数 [V0.0.20.19] +·短路电流固定50mV0us +·过压和过压释放都只改变自身值，在一起的延迟时间等不影响 + + +【都在前面加上了】 +////////////////////盛弘CAN协议 +////////////////////休眠时报警灯灭 +////////////////////MOS故障的判断改为30s，恢复判断保持3s +////////////////////屏幕选择协议优化 +////////////////////清除IAP标志位优化 +////////////////////上位机清除记录后，屏幕也刷新显示 + + +////////////////////报警记录100条，屏幕左上角显示最新所在，50->100 + + +9.19 +////////////////////一屏多机+按钮分配地址 +·注意：因为已经有和上位机的通信逻辑， + 若存在上位机的轮询报文或者单独请求从机数据的报文，此时若正在屏幕读取从机数据时 +·程序 +新增变量1： +extern uint8_t sdwa_RdData_Index;//屏幕显示数据的地址，默认是自身addr，只有addr=1可以变化为其他地址 +extern uint8_t sdwa_RdRecord_Flg;//屏幕只可以查看自身记录；当记录更新/清空/收到清空指令/进记录页面/上下翻动时，才会读EEPROM更新一次屏幕记录内容 + +extern uint8_t sdwa_WrAddr; //屏幕通过主机写从机地址的值 +extern uint8_t sdwa_WrAddr_Flg; //屏幕通过主机写从机地址的标志 0不在写 1尝试中 2成功 3失败 + +extern uint8_t assignAddr_State; //按钮分配地址的状态 0未开始 1进行中 2结束 +extern uint8_t assignAddr_Step; //自动分配地址当前步骤 + +新增变量2：（不在global.h中） +uint8_t modbusCurF03RxFlag;//主机收到03回复 接收正确标记 +uint8_t modbusCurF10RxFlag;//主机收到10回复 接收正确标记 + +uint8_t modbusCurStatus; //主机当前执行的功能——每当变化，会初始化收发状态 0:基础轮询 1：屏幕持续读从机 2:上位机持续读从机 3:主机写从机地址 4:自动分配地址 + +uint8_t sdwa_WrAddr_Failcount; //连续写地址失败的计数 +uint8_t assignAddr_Failcount; //连续分配地址失败的计数 + +uint8_t bAlarmFlagOld_slave; //主机屏幕显示从机报警的跳转 +uint8_t assignAddr_Flag; //分配地址完成的显示 + +#define PIN_ADDR_IN GPIO_Pin_8 //自动分配地址输入脚IO1 +#define PIN_ADDR_OUT GPIO_Pin_9 //自动分配地址输出脚IO2 + + +新增函数1： +//分配地址 +extern void IO2_OUTSet(void); //分配中先置高让下一个变99，再置低变PACK_NUM+1 +extern void IO2_OUTReset(void);//正常置低 +extern uint8_t IO1_IN(void); //检测输入电平 +extern void IO1_TIM_Moni(void);//根据不同的原地址和输入电平，选择要修改的特定地址 + +extern void MODBUS_Poll_Init(void); //轮询汇总初始化，只有主机数据 +extern void MODBUS_MASTER_F03_Rx(void); //处理从机对读指令的回复 +extern void MODBUS_MASTER_F10_Rx(void); //处理从机对写指令的回复 +extern void MODBUS_MASTER_Polling_Tx(void);//主机轮询获总数据 +extern void MODBUS_AutoAssign_Tx(void); //主机自动分配地址 + +extern void MODBUS_Screen_RdSlave_Tx(void); //主机因屏幕读从机数据 +extern void MODBUS_Screen_WrSlaveAddr_Tx(void);//主机因屏幕写从机地址 + +新增函数2：（不在global.h中） +void SDWA_ShowAlarm_Slave(void) //读取的从机报警数据的显示 + +////////////////////一屏多显 屏幕地址 +0x01A6 PACK页跳转总数据页按钮 +0x0270 单板数据回PACK页按钮 + +////////////////////一屏多机优化，不在线的从机，不可进行点击跳转 + +////////////////////上位机多显和屏幕多显兼容 +·当屏亮，而上位机在通过主机看从机，屏幕查看地址返回原值 +·当网口1超过10s不再收到上位机报文，将上位机求取对象地址初始化 + +////////////////////增加总容量的屏幕可改 +地址01AA + + + + +////////////////////循环次数重启恢复，需要加上old值来判断写入 + + + + +9.23 +////////////////////全自动分配地址=自动变主从机+自动分配地址 +·新增变量1： +extern uint8_t assignAddr_relay; //主机开机后延时2s再开始通信，等待地址变化 +extern uint8_t assignAddr_485num; //分配地址后的在线个数，若存在从机才进行下发队列标志 +extern uint8_t assignAddr_WrIndex_Flg; //主机执行下发队列标志数的标志 + +uint16_t bmsMem.can_ArrayIndex; // 主机下发队列序号，与自动分配地址相关 +uint16_t paraMem.addr_FREE_Flg; //0x11 地址手动控制标志，默认0 + +·新增变量2： +#define PIN_ADDR_RANK GPIO_Pin_7 //自动分配地址输入脚IO3，当输入低电平时，说明自身是从机 +uint16_t ADDR_Moni_Count; //自动分配地址前，因为短接脚而该改变自身的地址 每次10ms +uint8_t IO1_INH_Count; +uint8_t IO1_INL_Count; + +uint8_t modbusCurSlaveLastAddr; //最后一个在线从机的地址 + +uint8_t assignAddr_485num; //分配地址后的在线个数，若存在从机(此值>2)才下发队列标志 +uint16_t assignAddr_random; //主机完成分配后生成的随机数(PACK_NUM+1~65535),用来识别队列 +uint8_t assignAddr_WrIndex_Flg;//主机执行下发队列标志数的标志 + +·新增函数： +extern uint16_t get_random(void); + +extern uint8_t IO3_IN(void); //检测输入电平 +extern void ADDR_Rank_Moni(void); //根据IO3的不同电平，确定自身是主机/从机 + +extern void MODBUS_WrIndex_Tx(void); //主机广播下发队列标志 +extern void MODBUS_WrIndex_Rx(void); //从机接收该次分配地址的队列标志 + + +·暂时需要把轮询时间改为1s，后期可以测试下0.4s的效果 + +·启动情况分为： +【√】1.主机刚启动时，等待2s后启动分配(等待可能的地址变化) +【√】2.主机轮询完，连续2次(约40s)发现有掉线地址，比如地址4在线，但地址3不在线，启动分配 +【√】3.主机轮询完，连续6次(约2min)找不到任何从机，启动分配 +【√】4.主机已在正常轮询，此时有增加新从机(地址都是2)， + 若轮询到[分配标志]为0的从机，说明总线上有了没经过分配的从机，在该轮结束后启动分配 +【√】5.主机已在正常轮询，此时有增加从其他地方拆来的从机(地址任意但肯定在2~PACK_NUM内) + 若轮询到[分配标志]是旧程序中的bmsMem.E2_485Addr的值:2~PACK_NUM，在该轮结束后启动分配 + 若轮询到[分配标志]和当前主机上次下发的[分配标志]不同的从机，在该轮结束后启动分配 + （若是旧程序地址1，会和主机打架总线整个会受影响，而且不会轮询该地址，所以不考虑） +【√】6.原来是从机的BMS，地址刚变成1时，启动分配 + 比如把前面几个BMS板拆了，比如拆掉前3个后，原地址4会变1，而此时地址5及以后的值不变，需要启动分配 + *[分配标志]：轮询数据中新增一个变量，内容是主机分配地址后广播的随机数，范围在PACK_NUM+1~65535(避免和旧程序中的地址值相撞) + +////////////////////在换协议后，更新CAN波特率（前面已加） + + +////////////////////地址变化逻辑 +·开机后，会首先默认读出存在EEPROM里的地址 +·从机若被分配过地址，会在被分配后存储该地址，若再次上电时保持IO3短接状态，便暂时维持该地址 +·主从机都会将队列标志存储，若自身地址被更改，该队列标志清零，否则重启后仍保留上次的队列标志 +优点：可以固定搭配后，减少开机后等待时间 + +////////////////////一屏多机的主机显示从机，满充过压报警不显示 + + +9.30 +////////////////////删记录相关x2（前面已加） + +////////////////////进入参数设置的密码x2 + + +已经加上的优化 +////////////////////屏幕点击恢复出厂参数/修改欠压值时，需要把欠压强制复位也消掉 +////////////////////轮询若发现对【在线总个数以外的地址】有回复但是乱码，多次后启动自动分配 +////////////////////开机后的在线个数及时更新 [分配地址功能] +////////////////////报警记录个数的显示统一为100及以下 + +////////////////////报警记录屏幕显示的兼容，改以旧记录的特点为判断条件 + +要加上的优化 +//////////////////// +//////////////////// +//////////////////// +//////////////////// +//////////////////// +10.8 +////////////////////除旭尊外都删去急停 [V0.0.19.71] +·DI执行函数和引脚定义 ——> 删去 +·带急停的注释相关 ——> 删去 +·temperaStatus & 0x4 ——> 删去 +·temperaStatus & 0x7 ——> 改为0x3 +·status_byte4 & 0x7 ——> 改为0x3 + +////////////////////时钟超时做故障但是可以正常使用，把相应影响的部分同步增加修改 [V0.0.19.72] +·导致卡死的函数是RTC_WaitForSynchro(); //等待RTC寄存器同步，都要对应改为新的带超时返回的函数RTC_GetSynchro() +·当超时失败时，报警标志LSEErrFlag=1 +·影响下列操作： + 上位机写时间，不执行也不进行回复(要不要加上Modbus初始化) + 屏幕不进行时间显示 +·此时要出现的屏幕报警记录会一直记录2000-00-00 00:00:00，也直接不显示 +·休眠和欠压功能原来在RTC里，如果遇到LSE故障，要移动到定时器里启用 + +10.11 +////////////////////晶振问题再优化 +·晶振等待时间从250延长到1000 +·写时间要进行一系列写操作，或可能超出等待时间，不再参与问题判断 +·但若RTC_Get()函数里，通过RTC_GetCounter获得的时钟一直不走，证明RTC功能异常， + 判定标志位=1 + + +////////////////////增加温度线初始化后，采集一次数据获得平均温度用来生成默认的并机数据 + +////////////////////把MODBUS_Init()拆分为MODBUS_Init()和MODBUS_Poll_Init() + + +10.17 +////////////////////写时间操作函数还原 [V0.0.19.73] + +////////////////////时间校准的优化 [V0.0.19.74] +·会在启动休眠时，把休眠起始时间=当前值-(原时间-原休眠起始值)，使不影响休眠的正常运行 +·会在正在欠压强制复位时，把复位倒计时=300s-(原时间-原复位起始值)，使不影响休眠的正常运行 +·晶振存在问题的判断：①开机的初始化超时了也没退出来 ②将高低频动作不匹配：高频时钟持续10s，低频的RTC也不走动作 + +////////////////////Config_WritePara()改名ParaChange() +////////////////////优化：每秒屏幕更新时，也同时更新记录最新所在序号 + + + + +10.22 +////////////////////预充逻辑再优化 [V0.0.19.75] +1.连续3次短路报警(每次间隔<=5s)，直接锁定充放MOS，显示“预充失败” +2.当短路报警消失、进行预充关闭判断时，若此时仍存在电流(>=100mA)，则不符合关闭条件，继续预充(每4s检测一次，直到10次检测结束后仍未正常，显示“预充失败”) +3.负载端电压检测重新写，更贴近实际电压 +·新增变量： +uint8_t scOccurFlag; //短路出现过的标志 +uint8_t scRepeatTime; //等待短路倒计时，最大2s =>对应短路消失后2s内未再次出现，说明正常 +uint8_t scRepeatCount; //短路重复的计数，最大2次 =>对应连续3次出现短路 =>会在第三次短路去执行预充函数时，直接执行预充失败相关 + + +////////////////////同步V3结构体，防止上位机读写位置冲突 +////////////////////预充参数可设 [V0.0.19.76] +·新增变量： +pchg_enable 0/1 //预充功能是否开启 +pchg_scShow 0/1 //预充开启后，AFE短路报警是否显示(是否保留旧现象_习惯) + +pchg_dif_V 12 //预充完成的压差判定，只有负载和电池的压差小于该值，才认为这次预充结束(太小不容易充上来，太大) +pchg_T,pchgNum 4,10 //短路消失时继续预充，预充的持续时间和持续次数，次数溢出后说明当前很难带起负载，显示“预充失败” +scWait_T,scWaitNum+1 5,3 //短路消失且预充完成后，防范下一次短路的等待时间和等待次数，次数溢出后说明已连续短路多次，显示“短路锁定” + +·AFE短路保护可隐藏，可选择 + 短路对应bStatus1,bit5 + 所以，bStatus1 & 0x7 -> bStatus1 & 0x5 + +////////////////////增加短路锁定 [V0.0.19.77] +·在“预充失败”以外，新增“短路锁定”的显示，此时bit4、bit5标志位都置1，上位机在一个框里显示 +·控制亮灯，因为关预充时会只有“短路锁定” +·控制屏幕显示Fault +·报警记录内容解读+1 +·生成报警记录的条件+1 + 且短路生成记录需要判断是否不隐藏 +·主机轮询从机报警时候 + 预充失败bStatus2,bit5 + 短路锁定bStatus2,bit4 + 所以，status_byte2 & 0xe -> status_byte2 & 0xf + + +////////////////////MOS控制指令，长期和一次性的 [V0.0.19.78] +uint16_t CTRL_Order; //一次性 +uint16_t paraMem.ctrl_disable; //长期 + +////////////////////轮询对从机报警的再次询问，满充时的充电过压不列入条件 + +////////////////////强制欠压时，当欠压值被其他方式修改不再是500mV，就释放强制欠压 + + + + + + + + +10.21 增加若干优化 +////////////////////[分配地址]·开机后的在线个数及时更新 +////////////////////补丁：报警记录个数的显示统一为100及以下 + + +10.24 增加若干优化 +////////////////////协议里传输当前SOH + +////////////////////屏幕PACK在线页，显示轮询中/分配中 + +////////////////////上位机修改了欠压值，也会停止欠压强制复位功能 + +////////////////////重新检查删除记录的清空大小 + + + + +////////////////////软硬件版本号放入EEPROM +//软件；读出和程序的不同，就换当前这个写入EEPROM +//硬件：读出是0xff,默认写6.1.0，否则就是这个数 + +////////////////////欠压2700和2900 +70 0f 6e ee 62 c6 [87] [91] af 78 64 c3 08 0b 00 0a 50 64 46 ec f6 64 46 ec f6 [57] + + +****焰能屏幕优化相关 +////////////////////增加温度线初始化后，采集一次数据获得平均温度用来生成默认的并机数据 + +////////////////////[分配地址]·自动分配地址条件4 + +////////////////////[一屏多机+分配地址]·虚地址也显示，即不考虑从机的范围 +////////////////////[分配地址]·虚地址持续10s无任何改动，则恢复原地址 +////////////////////[分配地址]·写地址代码放入while循环里，加快反应速度 +////////////////////[一屏多机]·从机地址数据也应该每秒更新显示 +////////////////////[一屏多机]·屏幕显示Addr更新更及时 +////////////////////[一屏多机]·主机显示从机的过压保护，要单拎出来判断 + + +////////////////////[分配地址·自动]自动变化地址，要进行地址写入 + + + + +10.28 +////////////////////PACK_SN根据客户需求，可输入字母和数字，不包括符号 + + +10.29 +////////////////////限流启动后，运行灯常亮 + + +10.30 +////////////////////当电压低于45V时，默认优先走限流 +·当电压低于45V时，一旦出现100mA以上电流，开启限流持续10min + + + + + + + + +11.18 +////////////////////Flash的初始值修正 +·SOH计算参数添加默认值 + +////////////////////oldrcc_Ah的同步减少优化 +·不然只会和rcc_Ah同步增加而不会同步减少 + +////////////////////Delay_ms的优化，防止万一和中断冲突，导致卡死 +·增加超时退出 + +////////////////////勾选Free导致协议变化的问题 +·MEMORY_UpdateEEPROM函数增加延时 + + + + +////////////////////屏幕显示限流状态(balanceStatus & 0x10) +·当进行充电显示时，若此时在限流中，则显示限流而不是充电 + + + + +////////////////////适配RCT6的2K一页 [Vx.x.22.0] +·芯片选型RCT6,J-Link的下载速度选择High_density_512K +·启动文件换成/CORE/startup_stm32f10x_hd.s，魔术棒的C/C++里要改成STM32F10X_HD +·FlashAB的1024改为2048 +·main函数和程序开始改为0x1800 + + + + +////////////////////时间刚写入后，获取的休眠起始点很可能无效(为0) [Vx.x.22.1] +·通过判断使准备好后再进行休眠判断，使不会误入休眠状态 + + +////////////////////RTC时间备份 [Vx.x.22.2] +·若遇到了某些意外情况，导致RTC寄存器里的时间消失(BKP_DR1也不再是0x5050)，则执行写入备份时间的程序 +·备份时间默认是2023-06-25，但是也会时刻备份：每次开机(且时间正常)时/待机每过1h记录一次/充放电开始时记录一次/充放电时每5min记录一次 + + +////////////////////若干统一更新 [Vx.x.22.3] +[优化]累积容量的单位改为0.1Ah +[优化]计算1循环次数对应的容量时，需先判断百分比参数是否为0(毕竟是可读写的参数) +[优化]初始化时，在读出累积容量后进行一次转化循环次数的判断 +[优化]上位机修改循环次数时，同时会清空累积容量 + + +////////////////////补充更新(按道理该有的但是实际没有的) [Vx.x.22.4] +·补充[Vx.x.19.78]：充放MOS关闭标志启用的代码 +·补充[Vx.x.19.72]：充放电更新休眠起始点，加RTC是否正常的判断 +·补充：先删去45V启动限流这一步，删去充电过流不启动限流的逻辑 + + +////////////////////屏幕在设置短路时间时，若点击Exit，会使短路电压改为50mV，已修复 [Vx.x.22.5] +·同时把其他写入的可能超范围的参数，值规范下，超出范围的不处理 +·强制欠压复位是写到500mV，但如果是自己改到500mV，会出现5100mV的情况 + ——修复：在EEPROM存的欠压值，在读取出后就写入0xff，避免对手动写的干扰 + + +//优化屏幕代码书写 +·去掉一些多余的括号和空格 +·【补全】短路锁定相关显示 +·【补全】报警记录若时间全0，说明是RTC失效，此时不显示时间 + + +////////////////////优化屏幕参数写入范围 [Vx.x.22.6] +·考虑写入极限值，会触发报警闪烁，在所有可能的参数上增加限制 +·欠压原来写入不了500mV，现已修改 + + +12.31 +////////////////////若连续2次监测到不在充电状态后，停止限流 [Vx.x.22.7] + + +1.3 +////////////////////屏幕协议选择 [Vx.x.22.8] +·因为屏幕0x0345、0x0346被占用，所以协议需要跳过这两项 +·被占用是被用于一屏多显主页的跳转按钮的显示 + +////////////////////充放MOS控制信号位反了，已改正 [Vx.x.22.9] + + + + +3.5 +////////////////////当并机时，若有某从机出现(过压以外的)报警，该从机下线 [Vx.x.22.10] +·协议里：对应减去该从机的限流值、总容量值、并机个数、电池串数等 +·并机数据汇总里，除报警记录以外的数值都要修改计算范围 + +·屏幕显示总数据里的总容量，也改为*在线数量OnlineNum +·发送给上位机的数据，Online[0]的值从并机个数，改为正常工作个数 +·最新新增byte2的0x10，短路锁定，有部分报警判断没加，这里已完善 + +·Growatt改动16为bmsMem.ucCellNum +·Sigineer改动16为bmsMem.ucCellNum +·Sacolar改动16为bmsMem.ucCellNum +·DONNERGY改动16为bmsMem.ucCellNum + + +////////////////////总压判断-8V+5V [Vx.x.22.11] + + + + +3.13 +////////////////////增加禁充逻辑 [Vx.x.22.12] +·当SOC=100%时，充电限流=0 + +·电总协议里的充/放电允许位，判断条件写错了，已改正 + + +////////////////////根据并机数据修改限流值 [Vx.x.22.13] +·逻辑： +主机在轮询完成、处理并机数据时，对每个在线PACK的soc单独进行判断，调控充电限流值和放电限流值 +比如，4台PACK并机，其中3台在线，1台因报警下线。 + 当在线的PACK， + 3台都是soc=100%，充电限流值=0； + 1台soc=100%,2台soc<=99%，充电限流值=100A*2； + 3台都是soc<=99%，充电限流值=100A*3。 + +·禁充+禁放强充标志，仍然保留通过平均SOC控制(否则会很复杂) + + +////////////////////参与设定禁充禁放强充标志的soc值，可设 [Vx.x.22.14] +①启用禁充的标志+SOCx2 +②启用禁放的标志和SOCx2 +③启用强充的标志和SOCx2 +uint16_t requestFlg_enable; +uint8_t chg_forbid_Soc; +uint8_t chg_forbid_reSoc; +uint8_t dsg_forbid_Soc; +uint8_t dsg_forbid_reSoc; +uint8_t dsg_force_Soc; +uint8_t dsg_force_reSoc; + +·并机报警掉线功能，在传递给上位机的online[0]的内容，没有注意区分只有1个电池的情况，已完善 + + + + +3.20 +////////////////////满充时，不仅BMS不报警，也不向逆变器上传过压报警 [Vx.x.22.15] +//BIT5 cell ov +if((canMem[0].status_byte1 & 0x01) !=0) +{ + if(canMem[0].soc < 99) + { + protectByte1 |= 0x20; + } + else + { + protectByte1 &= 0xDF; + } +} +else +{ + protectByte1 &= 0xDF; +} + +3.24 +////////////////////屏幕选协议的代码没有全部优化，目前已完善 + + +3.26 +////////////////////小电流延迟显示时间，从3s改为5s [Vx.x.22.16] + + +////////////////////一直以来，屏显报警都是直接读EEPROM，有则显示。优化为和个数挂钩 [Vx.x.22.17] +·if(read_index < soe.num+3)优化为if(read_index < soe.num)，else内容改动 + + +////////////////////上位机切换语言，Free方框消失，是跳转页码错误，已改正 [Vx.x.22.18] + + +////////////////////检查上位机控制MOS标志位时，发现预充允许没有完整，增加paraMem的临时控制位 [Vx.x.22.19] +if(((CTRL_Order & 0x04) == 0) && ((paraMem.ctrl_disable & 0x04) == 0)) + +*有个写成了||，应该改成&& + + +////////////////////设容量优化 [Vx.x.22.20] +·之前缺了更新bmsMem.rcc + + + + +宁化时代要求 +////////////////////休眠功能 [+1] +·paraMem + //20240513 长时间待机定时休眠 + uint16_t sleep_min_disable; //0x10 纯定时休眠 bit15不执行休眠1使能 bit0~14休眠时间 + //20250402 低电压待机定时休眠 + uint16_t sleep_vol_disable2;//0x11 低电压休眠 bit15不执行休眠2使能 bit0~14休眠延时 +·执行逻辑更改 + 倒计时仍然根据时间；启用条件判断变复杂。 +·注意RTC和不走RTC的都要加 + +////////////////////整理ParaMem的参数，少量改动“未发布部分”以满足需求 + + +////////////////////真短路保护/预充失败触发后，延迟5min解除 [+2] +·真短路释放延时：5min，暂不可设 +·RTC和定时器版都要写 + + +////////////////////修改满充判断逻辑 [+3] +·paraMem增加参数： +uint8_t fcc_methods; //满充方式使能 bit0 单芯过压 bit1 总体过压 bit3 逆变器限压+小电流 bit4 满充电压+截止电流 +uint8_t fcc_cur; //截止电流默认5A，单位0.1A +uint16_t fcc_vol; //满充电压默认56V，单位0.1V + +·满充方式4启用时，若同时满足电压和电流，关闭充电MOS，停止充电 +·增加标志位 bmsMem.bStatus2 & 0x0100 ，表示满充停止充电 + +////////////////////paraMem参数cyc_改为sohcali_ + + +////////////////////增加总压保护 [+4] +·增加参数 +uint16_t pack_ovv; //总体过压保护默认57.6V 单位0.1V +uint16_t pack_ovrv; //总体过压保护释放默认54V 单位0.1V +uint16_t pack_uvv; //总体欠压保护默认45.6V 单位0.1V +uint16_t pack_uvrv; //总体欠压保护释放默认49.6V 单位0.1V +uint8_t pack_ovt; //总体过压保护延时默认1s 单位1s +uint8_t pack_uvt; //总体过压保护延时默认1s 单位1s +·总体过压关充电MOS，总体欠压关放电MOS +·补上了总体过压执行满充 + + +////////////////////增加放电过流2保护 [+5] +·增加参数 +uint16_t mcu_occ2; //放电过流2保护电流 250A 单位A +uint16_t mcu_occ2_t; //放电过流2保护延时 30*10ms 单位10ms + +·因为执行放电过流2的0.3s保护，改CTL设置为关放电MOS，然后通过定时器启动(走急停的流程) + + +////////////////////增加环境温度保护 [+6] +·环境温度指的是MCU温度 + +·增加参数 + int8_t am_otc; //0x27 环境充电高温 + int8_t am_otcr; // 环境充电高温释放 + int8_t am_utc; //0x28 环境充电低温 + int8_t am_utcr; // 环境充电低温释放 + int8_t am_otd; //0x29 环境放电高温 + int8_t am_otdr; // 环境放电高温释放 + int8_t am_utd; //0x2A 环境放电低温 + int8_t am_utdr; // 环境放电低温释放 + +·【注意MOS温度保护的设值，要比环境温度大】 + + +////////////////////补全新增保护的显示、并机和记录逻辑 [+7] +·因为并机收集的只有bStatus1/2/3和temperaStatus，所以新增的保护和报警都要尽量放在这里 + 标志位位置相比之前有改动，需要整体看一下 + +·单体过压保护和总体过压保护，若在SOC不高时都会屏幕弹出提醒 + +·并机采集必然被改动， + 并机状态改为uint16_t，内容对应改动 + +·预充使用了CTRL引脚控制MOS开关，那就不能让放电过流2使用CTRL引脚，改为定时器立刻写入关闭放电MOS控制，同时在1s一次的写入控制时保持 + +·满充条件4关闭充电，并机需要知道，放入bStatus & 0x0800 + +·记录相关补全，注意存储的标志位只有0xff + 报警不记录，但有7个保护需要记录但是标志位不在0x00ff范围里 + 这7个使用packStatus位置 + +·满充判定4，增加充电状态的判断 + +·休眠两种方式要同时可用 + 1、待机时间超过 24 小时（无通信、无充放电 ，无市电），即进入休眠状态 + 2、最低单体电压低于休眠电压，且同时满足无通信、无保护、无均衡、无电流，才开始休眠计时 + 把休眠1时间改为小时单位，占用0x7F00 + 休眠时间2时间改为0x00FF，分钟单位 + + +////////////////////增加报警 [+8] +·增加报警标志： +MOS温度告警*4，电芯温度告警*4，环境温度告警*4，电压告警*4，电流告警*3 +·增加参数： + //20250408 + uint16_t alarm_cov; //0x30 单体过压告警 + uint16_t alarm_cuv; //0x31 单体欠压告警 + uint16_t alarm_pov; //0x32 总体过压告警 + uint16_t alarm_puv; //0x33 总体欠压告警 + + uint8_t alarm_occ; //0x34 充电过流告警 + uint8_t alarm_ocd1; // 放电过流1告警 + + int8_t alarm_mcu_otc; //0x35 电芯充电高温告警 + int8_t alarm_mcu_utc; // 电芯充电低温告警 + int8_t alarm_mcu_otd; //0x36 电芯放电高温告警 + int8_t alarm_mcu_utd; // 电芯放电低温告警 + + int8_t alarm_am_otc; //0x37 环境充电高温告警 + int8_t alarm_am_utc; // 环境充电低温告警 + int8_t alarm_am_otd; //0x38 环境放电高温告警 + int8_t alarm_am_utd; // 环境放电低温告警 + + int8_t alarm_afe_otc; //0x39 MOS充电高温告警 + int8_t alarm_afe_utc; // MOS充电低温告警 + int8_t alarm_afe_otd; //0x3A MOS放电高温告警 + int8_t alarm_afe_utd; // MOS放电低温告警 + +·【逆变器协议里的报警和新增的保护，由任世兴负责】 + + +////////////////////增加报警的闪烁 [+9] + +////////////////////补充优化 [+10] +·bStatus3的充放电状态由mcu给的 +·休眠参数值改动 + + +////////////////////保护解除时，也同步解除告警 +·告警解除不是因为恢复到了告警值以上，而是恢复到保护释放值以上 + +////////////////////新增电流保护超限锁定 [+11] +·充电过流/放电过流1/放电过流2/短路保护 +·对于浪涌保护，也执行5次锁定，也等待60s，修改执行结果为浪涌短路状态保持 + +·上位机写入解除锁定：使用一次性写入的位置 +bit4 用于解锁电流次数超限锁定 + + +////////////////////在设定参数时，新增对应关系 [+12] +①当设定充/放电过流告警电流时，逆变器充/放电限流=告警电流减10A。 +②当设定总体过放告警电压时，逆变器放电限压=告警电压。 + + +////////////////////屏幕改动MCU电流保护值时，会同步调控AFE电流保护值 [+13] + +////////////////////改动Flash和屏幕初始化时的默认值 + + +////////////////////告警和保护的触发，解除，单独放在文件Status.c里 [+14] + + +////////////////////各种保护的特殊解除项 [+15] +·单体过压 + SOC<96%，放电电流>3A +·单体欠压 + 接入充电器(进入充电状态) +·总体过充 + SOC<96%，放电电流>3A +·总体过放 + 接入充电器(进入充电状态) +·充电过流 + 放电电流>2A +·放电过流1 + 充电电流>2A +·放电过流2 + 充电电流>2A +·真短路保护 + 充电电流>1A，负载断开 + +////////////////////单体过压和欠压由MCU控制 +·思路： + 上位机大批量读写要连续发两条报文来读写寄存器， + + 第一条是原报文33/10且内容保持不变(只不过因为上位机画面优化而有些改为固定值)，新增f3/f4发送新增的功能参数 + 单片机在收到33/10报文，准备更新afe参数值时， + 该程序会单独把原有的单体过压和单体欠压保护值改为固定不可启动的值(500mV=0x19*20,5115mV=0x3FF*5)，且延时拉到最大 + 然后把实际保护值放入paraMem的参数位置(在第二天报文的更新EEPROM值时进行存储)， + + 第二条是新的f3/f4报文，收到后按内容放入paraMem的对应位置 + +*bmsMem结构体不用改变，强制恢复欠压值的操作也不需要改动， + 因为一直到Flash里存放的值，都和原来一样，只有更新给AFE的值变化 + MCU程序里有根据过压欠压值执行保护和保护释放的执行代码，有关闭MOS的执行代码，单体过压和欠压标志位不接受AFE的更新 + +*paraMem已有部分基本不需要变动， + 新增部分根据地址来读写 + +////////////////////单体过压/欠压的保护的特殊解除项 + + +////////////////////增加开路电压法 [+17] +·增加参数： +uint16_t ocv_cpBuf[15]; +uint16_t ocv_dpBuf[15]; +uint16_t ocv_min_enable; +uint8_t ocv_caliRange_soc; +uint8_t ocv_caliRange_T; + + +////////////////////锁定最大次数，暂不做可设 + +////////////////////休眠方案2的位置朝后移，两种休眠分开也不能影响已有的位置 + +////////////////////和上位机通信时的一次性总读写参数，注意要放在一起 + + +////////////////////逆变器协议内容更新 [+18] +·报警向逆变器发送报警标志，和保护区分开 +·单体过压和总体过压不上报 +·SMK协议无报警和保护 + +古顶=硕日轻微改动 + + + + +/** 宁化时代 **/ +*单体过压不触发？ +——电压保护的特殊解除项，应该多等待几轮才能触发，暂时是>1 +——电压保护条件满足清零计数变量，之前未加现在已加上 + +*过流保护后立刻显示MOS故障？ +充放电状态的赋值对象是bStatus3，之前是2现在已改 + +*屏幕上显示保护记录，增加新增的保护 +(启动记录的放电过流2有个5写成了3，已改) + +·协议内告警和保护有点要改的 +/** [V3.00.00.12]+[6.2.P] **/ + + + + +////////////////////程序发给客户后，对程序的检查 +·满充条件4会关闭MOS，但没有明确释放条件，参考过压的释放条件，现在增加了满充条件4的释放条件 [+1] + +·出现单体过压或总体过压告警后，充电请求电流下降为40A，之前没写，现在已加 [+2] + +·修改总体欠压告警电压后，逆变器放电限压值=该值，之前变量名写成了Cur电流，现在已改 [+3] + + +////////////////////程序发给客户后，对程序的检查2 +·并机数据canMem结构体的标志位没改为uint16_t，现在已改 [+4] + +·发生单体/总体过压告警后，逆变器限流值改为固定40A，原来是对应小波动，现在改为和禁充类似的标志位，此时限流值总共为40A [+5] + +·客户需要更及时的逆变器限流改动，原来主机和并机总值的计算，还有状态判断是轮询一轮结束后执行，现在放在1s一次的函数进行判断，及时更新 [+6] + +·真短路保护的自动恢复，之前没写只写了特殊解除，现在已加 [+7] + +·预充超时失败与真短路分开状态，并改为和真短路保护一样在5min后自动解除，解除时注意打开Ctrl引脚。有特殊解除项，但没有次数超限锁定 [+8] + +·浪涌短路和预充过充的参数有问题需要调换flash里的默认值 [+9] + +·屏幕强制解除欠压时，修改的是过压保护值，但是因为不写给AFE了不会自动初始化状态，所以需要通过代码将过压保护关掉，又因为修改为500mV所以打不开 [+10] + +·总体过压/欠压的保护位，应该是bStatus1不是bStatus2，已改 [+11] + +·SOC=100%时，单体过压告警/保护，总体过压告警/保护，灯和屏幕都不显示 [+12] + +·当真短路和预充失败时，MCU也会维持MOS关闭 [+13] + +·放电过流2，原来的启用判断，电流写成充电电流判断，bStatus1写成了2，现在已改 [+14] + +·当主机在因为屏幕/上位机去单独读某个从机的整体数据时，同步更新canMem结构体对应的值 [+15] + +·环境温度保护，应该在temperaStatus而不是balanceStatus，现在已改 [+16] + + +////////////////////检查所有保护和报警标志位的正确，包括次数超限锁定 +·浪涌短路跳转预充的判断里，应该是BIT6但写成了BIT10，现在已改 + +·真短路保护和预充失败，去掉特殊解除项：负载移除，因为板子做不到检测该条件 + +*已通过断开B+线的方式，测出真短路保护超5次后锁定，正常执行 + +·真短路保护的解除，应该先判断是否在锁定中，减少不必要的计数 + +·充电过流锁定时，会关闭放电MOS？——之前写了锁定标志也会关MOS，且标志位不对，这里改正后注释到，因为没必要再因此关闭 + + +////////////////////预充逻辑的思考和测试 +·连接逆变器空开闭合，执行浪涌短路保护： + (出现后8s自动解除，若连续出现5次执行锁定) +·预充第1s，判断正在真短路，执行真短路保护： + (出现后就锁定不可解除) +·在浪涌短路解除后，预充连续40s还是没有成功打开逆变器，执行预充超时失败 + (出现后5min自动解除，若连续出现5次执行锁定) + +////////////////////原“真短路保护次数超限锁定”，改为“预充超时失败次数超限锁定”， +·真短路在出现后不可解除，预充超时失败改为5次后锁定 + + +////////////////////定时的变量检查，特别是休眠 +·休眠2，定时器版之前忘加了；应该在唤醒时也更新休眠2的起始点 + + +////////////////////开路电压法重启后也可用 +·开路电压法没有做关机后也保存定时起点的功能 +·开路电压法对电流的看法，放到1A以内而不是0.1A + +////////////////////开路电压法，必须是在之前真的充放电后，才执行校准，且只执行一次不需要重启 +·OCV_choice是待机状态0/1，不启动计时 +·执行一次后，刷新OCV_choice=1，除非有充放电否则不再计时 + + +////////////////////预充逻辑，尽量成为和原逻辑相同 +·同时有个scr_Moni_Count = SCR_MON_CNT;写成了UVOff_MON_CNT，现在已改 + +·之前的真短路定时恢复不需要定时器函数和RTC函数，现在已删去 + + + + +////////////////////为了能够节省轮询时间，将PACK_NUM改为可设 [+26] +·默认2台，可改范围1-20 +·当PACK_NUM=1时，主机不会轮询。 +·3.4网口的超时初始化，等待时间需根据PACK_NUM调整，1=》固定30s 2~20=》PACK_NUM*1.5s+2s +·地址在赋值和改动PACK_NUM时，需要检测是否符合Addr<=PACK_NUM，不符合时，恢复到2(若PACK_NUM=1则恢复到1) + +·定义一个值作为PACK_NUM的最大值，全程序内通用，目前对应20 + 自动分配地址的虚地址地址不是PACK_NUM+1，而是这个值+1 + + +////////////////////测试需要，把真短路也改为5min自动释放，连续三次后锁定 +·标志位和浪涌短路共用一个 + + +////////////////////对于并机总数，做出如下优化： [+29][+30] +·只对主机轮询个数有效，在设置自身地址时，仍然在1~20都可以 +·改为在paraMem里，能整体读写 +·当地址是从机时，可以写入这个值，但是是在成为主机时生效 + +并联轮询总数： +单独使用 +并机2台 + + +////////////////////真短路五次锁定，实测未锁定，排查原因，已优化 [+31] + + +////////////////////主机分配地址受自身的并机总数影响 [+32] +·主要是从机不会因为自身的该值，而改动自身地址，实际可被分配的范围仍然是2~20，可手动改的范围仍然是1~20 +·主机轮询和分配地址都受并机总数影响 + + +////////////////////休眠问题和总体欠压校准问题 [+33] + + +以下都是[+34] +////////////////////改动充电过压报警后电流40A，变为40A*没有保护的个数 + + +////////////////////开路电压法的改动 +·判定开启静置倒计时的电流是3A +·校准倒计时设定默认值30min + +·校准之后会更新静置倒计时恢复原值，使得在静置时一直会校准SOC +·不再需要记录旧状态，只要在静置状态下，一直定时校准 +·不再区分充放电曲线，程序只使用DP值，所以EEPROM不再需要记录状态，而时间始终存在和持续更新 + +·不允许OCV校准时，OCV_step=0 +·允许OCV校准时， + 正在充放电，OCV_step=0，但是会每隔30min记录一次时间 + 刚开机没有时间/刚从充放电状态回来，OCV_step:0->3， + 若刚从充放电状态回来 + +·倒计时起点，在EEPROM保存异常时更新；在从充放电状态回到静置状态时更新 + 正在充放电时，每30min更新一次， + +·单芯值，小数点后一位进行四舍五入 + + +////////////////////放电请求电流：当PACK电压=放电请求电压时，BMS发送禁放指令 +·此时就算soc在20%以上，也会禁放 + + +////////////////////取消MOS充放电低温的告警和保护的判断赋值，参数暂时保留，标志位的执行暂时保留 [+35] + + +////////////////////浪涌短路默认参数110mV 64us [+36] +·把AFE过流参数调到30mV40mV30mV(200A的设置)然后保持固定值，SDWA的同步改动我也去掉，上位机的之后去掉 +·110mV 64us +70 0e 6e d0 62 a8 8c 9b af 78 64 c3 18 1b 21 1a 50 64 46 ec f6 64 46 ec f6 60 + + +////////////////////SOC与容量 [+37] +·原总容量，现在名称改为[额定容量]：bmsMem.fcc->bmsMem.ncc (nominal:名义上的) +·新建[满充容量]：fcc，断电可保存，精确到1mAS +·在RTC晶振正常时，若12h内关机，也可以记住开始时间和是否要计时 + 在RTC晶振异常时，若12h内关机，开机后需要重新开始欠压到过压且中间不关机，才能校准总容量 + +·逻辑：若刚开始充电时，SOC=0/1%，则允许校准满充容量，同步计时12h超过则不再校准。 + 若12h内，满足了满充判定的任一条件而使SOC=100%，在基本停止充电(电流<2A)后执行容量校准：赋值[满充容量]=此时的剩余容量并保存。 + 若12h外，满足了满充判定的任一条件而使SOC=100%，不会变动满充容量。 + 剩余容量可以一直增长，若超过了原来的满充容量，SOC保持100%不再增长。 + +·上位机显示[额定容量]和[剩余容量]，在充满时剩余容量=[总容量]。 +·上位机或屏幕写入容量时，既更新[额定容量]，也更新[满充容量]，[剩余容量]=[满充容量]*SOC，但不影响此前的满放充电置位的校准标志 + 上位机或屏幕写入SOC时，会将该标志清零 + +·计算SOC时，因为满充容量精量化，SOC每1%对应的是1mAS级别，所以要 + 只要还有0.1AH都向上显示1% + 在rcc>=fcc/100*99+0.1AH的值后，SOC固定为100% + +·[满充容量]保存在EEPROM，单位mAS + [满充容量校准等待时间]保存在EEPROM，使晶振正常时重启不影响进程 + +·发给逆变器/屏幕显示的并机总容量，暂时还是*额定容量，后面提出了再改 +·发给逆变器的并机剩余容量，暂时也还是*额定容量 + + +6.4 +////////////////////满充前SOC最高锁定99% [+38] + + + + +** 下面是标准版更新：[V3.36.22.21]~[V3.36.22.28] ** +5.13 +////////////////////3.4口可以和V3上位机通信 [Vx.x.22.21] +·建立通信时，主机的轮询暂停（主机发现有其他报文，也会主动暂停） + + +6.16 +////////////////////将禁放强充判断增加"="，防止设置0%时出现问题 [Vx.x.22.22] + + +////////////////////未放空维持1%，就像未充满维持99%类似 [Vx.x.22.23] +·因为宁化时代增加了总容量可变，所以未放空是在0.1Ah~0.5Ag徘徊 + + +////////////////////更新温度值表 [Vx.x.22.24] +·温度线的范围从-40~110改为-55~125 +·板贴温度更精确(不过原来的也可以用，非极限值的实际差距不大0.1左右) + + +////////////////////更新预充压差从12V改为19V [Vx.x.22.25] (之前已加) + + +6.30 +////////////////////协议内容矫正 [Vx.x.22.26] (之前已加) +·Growatt.485协议，CV_Vol = bmsMem.inverter_chgVolLimit * 10; + + +7.3 +////////////////////所有逆变器协议，注释上报均衡 [Vx.x.22.27] + + +7.16 +////////////////////整理canMem一类结构体 [Vx.x.22.28] +·cur和temp的赋值，需要加上转换：(int16_t) +·同时把最大最小温度的变量类型改回uint16_t，都是K氏温度 + + +7.24 +////////////////////屏幕显示屏幕版本号优化 [Vx.x.22.29] +·可兼容028xx，从0x04开始 +·如果屏幕版本号为0，不显示 + + +8.5 +////////////////////屏幕显示软件版本号有误，已优化 [Vx.x.22.30] + + + + + + +** 宁化时代更新：[+39~+41] ** +[+39]强制关总体欠压优化： +·宁化的单体欠压和总体欠压，都由MCU自身执行 +·原有“强制关单体欠压”的执行相关，删去： + 恢复默认参数时，关闭功能；修改单体欠压保护值时，关闭功能； + 对单体欠压参数=25的恢复 + +·新逻辑：当按下强制关欠压后，总体欠压和单体欠压保护的标志位保持置0 + 倒计时结束可恢复，重启可恢复 + +[+40]关闭满充校准总容量设置_真正起效： + 之前的关闭设置没有实际启用，现在改为可用 + ·关闭后，rcc不能能超过fcc + ·关闭后，fcc=ncc + +[+41]出现总体过压或单体过压的时候，充电限流固定40A，改动为： + 100A板子的限流值应为20A + + + + +[++1]为了适配更广泛的客户： +*宁化时代参数，但所有电流相关改为100A对应值 +bmsMem +70 0e 6e d0 62 a8 8c 9b af 78 64 c3 18 1b 00 1a 50 64 46 ec f6 64 46 ec f6 96 +3c 37 00 05 41 3c ec f1 69 69 01 01 3c 85 +64 05 3c 00 +40 02 e8 01 e8 03 e8 03 +paraMem +40 02 1c 02 c8 01 f0 01 01 01 82 00 04 00 46 41 ec f1 46 41 ec f1 60 60 02 00 00 00 00 00 00 00 c0 0d ea 0b 30 02 e8 01 50 64 37 05 3c f1 41 f1 41 f1 5f f1 5f f1 +*一系列设定： + 1.关闭SOC电压定时校准 + 2.关闭满充校准总容量 + 3.并机16台 +paraMem +40 02 1c 02 c8 01 f0 01 01 01 82 00 04 00 46 41 ec f1 46 41 ec f1 60 60 [10] 00 00 00 00 00 00 00 c0 0d ea 0b 30 02 e8 01 50 64 37 05 3c f1 41 f1 41 f1 5f f1 5f f1 + + + +**标准更新** +11.19 +////////////////////Growatt CAN优化 [Vx.x.23.1] + + +////////////////////新预充 [Vx.x.23.2] + + +////////////////////屏幕亮度范围20~40都可识别 [Vx.x.23.3] + + + + +11.20 +////////////////////宁化时代版，屏幕设置总个数有问题，无法有效设置 +·原来存EEPROM，后面做成上位机可设的paraMem，需要改存储方式 + +////////////////////增加电流告警自动释放 + + + + +**标准更新** +////////////////////对于关闭预充时，也要在AFE短路时测试是否是真短路 [Vx.x.23.3] + + +11.27 +////////////////////原[Vx.x.23.2]的新预充逻辑，实测会有问题，暂搁置并使用原有逻辑，把8s后直接退出预充 +·原有预充逻辑，但AFE短路结束后直接退出预充 +·退出预充后可能立刻触发AFE短路，这里要将AFE短路多次锁定的判断参数在预充结束时同步更新 + + + + +**标准更新12.5** +////////////////////AFE温度保护值问题 [Vx.x.23.6] + + +////////////////////过流报警释放问题 + + + + +**** 硬件6.3.L **** +//均衡控制，PA8换到PC1 √ + +//PB12做输入，PB13做输出默认低 √ + +//PC10/PC11做蓝牙通信，参考驻启程序 √ +//PC12做蓝牙复位脚，参考驻启程序 √ + +//调整优先级，参考最近给恒格改的 √ +//优先级分组函数放出来 √ + +//先把限流操作内容清空，留给之后写详细控制 √ + + +1.13 +//蓝牙完善 +·主动上传数据共5包 +·读写的参数暂时就1个；回复增加ProtocolName；格式为未来多个参数的读写做准备；更进一步规范格式，""和{}/[]都要检查 +·在正在连接时改名称，需在+++后等待0.5s + + +1.15 +移植功能： +//长按开机/复位/关机 +·开机后，当KEY收到2s高电平，控制POWER保持输出高电平 +·按键再次按下后，若摁了2s执行复位，若继续摁了4s执行关机 + +·LED状态： + 开机时，所有灯全亮，然后在while循环中变成实际状态 + 执行复位但还没有执行关机时，所有灯闪烁后全亮一会 + 执行关机，所有灯熄灭 + +·复位包括：CAN，串口x4，蓝牙模块，各种保护/报警/故障标志，看门狗 +·关机包括：灯全灭，MOS全关，限流/均衡/预充全关，通信停止 + +·如果系统卡住了，那岂不是关不了机？——加上看门狗 + + +1.19 +//PA8用于输出PWM波以控制限流 +·PWM频率20kHz，占空比50%-95% +·限流10A + +·基准电压暂时换53V，最好能取到52V时候的 + 53.5V 94.0f + 53.0V 92.8f +·改为100.00单位试试，0.1f的波动值有点大 +·将PWM波的微调，放到计算电流函数里，能立刻反应——需要看效果 + +·根据电流差值调整占空比，变化越大电流波动越大 + 似乎占空比改动后，对电流的影响会持续1.2s——改成2s反应1次试试 +·需要测试当电流小于10A以后，PWM波会怎么样 + + +1.20 +//蓝牙-屏幕版本号在存在时才上报 + + +1.21 +//优化： +·CAN错误中断加上 +·休眠后，串口超时初始化的倒计时也关闭 + +·报警记录的地址，要判断是否正常 + +·自动分配地址，定时器里对地址的变化，暂不执行写入EEPROM，之后用write_Addr写进去 +·自动分配地址，把时序安排好，主机收到回复后间隔1次再发下一个分配，从机回复和置IO2都直接在while循环里 +·地址为虚地址时，快速闪烁而不是常亮 + + +·之后做优化代码量，和封装函数 + + +1.22 +//晶振还是要用外部晶振，才能用纽扣电池供电 + +1.30 +//之前把清空队列标志操作，和根据地址输出IO1电平功能，放到了(write_Addr != 0)的判断里，现在放出来 + + + + +/**硬件6.3.LW**/ + +//通信新蓝牙MBO26A： +·AT命令后跟着的是=0x0d 0x0a +·波特率9600 +·连接/断开发的数据是+CONNECTED和+DISCONN +·最大字节数244 +//蓝牙字节数上限小，分包更多 + +//引脚： +·PC13 电源维持 +·PC0 按键状态检测 + +·PB12 LED1电量灯 + +·PB9 限流PWM波 + +·PC1 外接电阻检测，以控制地址变化 + + +2.27 +//限流因停止充电而停止，之前注释了，现在恢复 + + +2.27 +//按钮分长按和短按模式，根据实际需要选择 + +//自动分配地址功能，相关执行代码只有在启用时才执行 + +//小板增加蓝牙/WIFI/4G所有代码，可根据实际需要选择执行其中一个 + + +2.28 +//4G通信完善 +*该芯片开机等待只需0.8s + +//Flash参数改100A的 + + +3.2 +//4G通信完善 +·该芯片开机等待虽说只需0.8s，但实际发AT+CSQ在开机时会回复99，需要延时通信 +·还差最后2个函数的正常通信内容、事件相关、参数表 +事件 +休眠 +读写函数 +服务函数大框架 + +定时上报属性删减， +原版： + LTE_CombineStr("\"ChgLimitStatus\":%s,", Status[ChgLimitStatus]); //14+4 + 5 + LTE_CombineStr("\"BalanceStatus\":%s,", Status[BalanceStatus]); //13+4 + 5 + //特殊状态 + LTE_CombineStr("\"LockOCC\":%s,", Status[LockOCC]); //7+4 + 5 + LTE_CombineStr("\"LockOCD1\":%s,", Status[LockOCD1]); //8+4 + 5 + LTE_CombineStr("\"LockOCD2\":%s,", Status[LockOCD2]); //8+4 + 5 + LTE_CombineStr("\"LockSP\":%s,", Status[LockSP]); //6+4 + 5 + LTE_CombineStr("\"LockSC\":%s,", Status[LockSC]); //6+4 + 5 + LTE_CombineStr("\"ChgMosFault\":%s,", Status[ChgMosFault]); //11+4 + 5 + LTE_CombineStr("\"DsgMosFault\":%s,", Status[DsgMosFault]); //11+4 + 5 + LTE_CombineStr("\"DOStatus\":%s,", Status[DOStatus]); //8+4 + 5 + LTE_CombineStr("\"ForceOffUV\":%s,", Status[ForceOffUV]); //10+4 + 5 + //保护 + LTE_CombineStr("\"PackOV\":%s,", Status[PackOV]); //6+4 + 5 + LTE_CombineStr("\"PackUV\":%s,", Status[PackUV]); //6+4 + 5 + LTE_CombineStr("\"CellOV\":%s,", Status[CellOV]); //6+4 + 5 + LTE_CombineStr("\"CellUV\":%s,", Status[CellUV]); //6+4 + 5 + LTE_CombineStr("\"PF\":%s,", Status[PF]); //2+4 + 5 + LTE_CombineStr("\"L0V\":%s,", Status[L0V]); //3+4 + 5 + LTE_CombineStr("\"OCC\":%s,", Status[OCC]); //3+4 + 5 + LTE_CombineStr("\"OCD1\":%s,", Status[OCD1]); //4+4 + 5 + LTE_CombineStr("\"OCD2\":%s,", Status[OCD2]); //4+4 + 5 + LTE_CombineStr("\"SP\":%s,", Status[SP]); //2+4 + 5 + LTE_CombineStr("\"SC\":%s,", Status[SC]); //2+4 + 5 + LTE_CombineStr("\"McuOTC\":%s,", Status[McuOTC]); //6+4 + 5 + LTE_CombineStr("\"McuOTD\":%s,", Status[McuOTD]); //6+4 + 5 + LTE_CombineStr("\"McuUTC\":%s,", Status[McuUTC]); //6+4 + 5 + LTE_CombineStr("\"McuUTD\":%s,", Status[McuUTD]); //6+4 + 5 + LTE_CombineStr("\"AmbientOTC\":%s,", Status[AmbientOTC]); //10+4 + 5 + LTE_CombineStr("\"AmbientOTD\":%s,", Status[AmbientOTD]); //10+4 + 5 + LTE_CombineStr("\"AmbientUTC\":%s,", Status[AmbientUTC]); //10+4 + 5 + LTE_CombineStr("\"AmbientUTD\":%s,", Status[AmbientUTD]); //10+4 + 5 + LTE_CombineStr("\"MosOTC\":%s,", Status[MosOTC]); //6+4 + 5 + LTE_CombineStr("\"MosOTD\":%s,", Status[MosOTD]); //6+4 + 5 + LTE_CombineStr("\"MosUTC\":%s,", Status[MosUTC]); //6+4 + 5 + LTE_CombineStr("\"MosUTD\":%s,", Status[MosUTD]); //6+4 + 5 + //报警 + LTE_CombineStr("\"PackOVWarning\":%s,", Status[PackOVWarning]); //6+4 + 5 + LTE_CombineStr("\"PackUVWarning\":%s,", Status[PackUVWarning]); //6+4 + 5 + LTE_CombineStr("\"CellOVWarning\":%s,", Status[CellOVWarning]); //6+4 + 5 + LTE_CombineStr("\"CellUVWarning\":%s,", Status[CellUVWarning]); //6+4 + 5 + LTE_CombineStr("\"OCCWarning\":%s,", Status[OCCWarning]); //3+4 + 5 + LTE_CombineStr("\"OCDWarning\":%s,", Status[OCDWarning]); //3+4 + 5 + LTE_CombineStr("\"McuOTCWarning\":%s,", Status[McuOTCWarning]); //6+7+4 + 5 + LTE_CombineStr("\"McuOTDWarning\":%s,", Status[McuOTDWarning]); //6+7+4 + 5 + LTE_CombineStr("\"McuUTCWarning\":%s,", Status[McuUTCWarning]); //6+7+4 + 5 + LTE_CombineStr("\"McuUTDWarning\":%s,", Status[McuUTDWarning]); //6+7+4 + 5 + LTE_CombineStr("\"AmbientOTCWarning\":%s,", Status[AmbientOTCWarning]); //10+7+4 + 5 + LTE_CombineStr("\"AmbientOTDWarning\":%s,", Status[AmbientOTDWarning]); //10+7+4 + 5 + LTE_CombineStr("\"AmbientUTCWarning\":%s,", Status[AmbientUTCWarning]); //10+7+4 + 5 + LTE_CombineStr("\"AmbientUTDWarning\":%s,", Status[AmbientUTDWarning]); //10+7+4 + 5 + LTE_CombineStr("\"MosOTCWarning\":%s,", Status[MosOTCWarning]); //6+7+4 + 5 + LTE_CombineStr("\"MosOTDWarning\":%s,", Status[MosOTDWarning]); //6+7+4 + 5 +// LTE_CombineStr("\"MosUTCWarning\":%s,", Status[MosUTCWarning]); //6+7+4 + 5 +// LTE_CombineStr("\"MosUTDWarning\":%s,", Status[MosUTDWarning]); //6+7+4 + 5 + +改为： + if(ChgLimitStatus) LTE_CombineStr("\"ChgLimitStatus\":true,"); //14+4 + 5 + if(BalanceStatus) LTE_CombineStr("\"BalanceStatus\":true,"); //13+4 + 5 + //特殊状态 + if(LockOCC) LTE_CombineStr("\"LockOCC\":true,"); //7+4 + 5 + if(LockOCD1) LTE_CombineStr("\"LockOCD1\":true,"); //8+4 + 5 + if(LockOCD2) LTE_CombineStr("\"LockOCD2\":true,"); //8+4 + 5 + if(LockSP) LTE_CombineStr("\"LockSP\":true,"); //6+4 + 5 + if(LockSC) LTE_CombineStr("\"LockSC\":true,"); //6+4 + 5 + if(ChgMosFault) LTE_CombineStr("\"ChgMosFault\":true,"); //11+4 + 5 + if(DsgMosFault) LTE_CombineStr("\"DsgMosFault\":true,"); //11+4 + 5 + if(DOStatus) LTE_CombineStr("\"DOStatus\":true,"); //8+4 + 5 + if(ForceOffUV) LTE_CombineStr("\"ForceOffUV\":true,"); //10+4 + 5 + //保护 + if(PackOV) LTE_CombineStr("\"PackOV\":true,"); //6+4 + 5 + if(PackUV) LTE_CombineStr("\"PackUV\":true,"); //6+4 + 5 + if(CellOV) LTE_CombineStr("\"CellOV\":true,"); //6+4 + 5 + if(CellUV) LTE_CombineStr("\"CellUV\":true,"); //6+4 + 5 + if(PF) LTE_CombineStr("\"PF\":true,"); //2+4 + 5 + if(L0V) LTE_CombineStr("\"L0V\":true,"); //3+4 + 5 + if(OCC) LTE_CombineStr("\"OCC\":true,"); //3+4 + 5 + if(OCD1) LTE_CombineStr("\"OCD1\":true,"); //4+4 + 5 + if(OCD2) LTE_CombineStr("\"OCD2\":true,"); //4+4 + 5 + if(SP) LTE_CombineStr("\"SP\":true,"); //2+4 + 5 + if(SC) LTE_CombineStr("\"SC\":true,"); //2+4 + 5 + if(McuOTC) LTE_CombineStr("\"McuOTC\":true,"); //6+4 + 5 + if(McuOTD) LTE_CombineStr("\"McuOTD\":true,"); //6+4 + 5 + if(McuUTC) LTE_CombineStr("\"McuUTC\":true,"); //6+4 + 5 + if(McuUTD) LTE_CombineStr("\"McuUTD\":true,"); //6+4 + 5 + if(AmbientOTC) LTE_CombineStr("\"AmbientOTC\":true,"); //10+4 + 5 + if(AmbientOTD) LTE_CombineStr("\"AmbientOTD\":true,"); //10+4 + 5 + if(AmbientUTC) LTE_CombineStr("\"AmbientUTC\":true,"); //10+4 + 5 + if(AmbientUTD) LTE_CombineStr("\"AmbientUTD\":true,"); //10+4 + 5 + if(MosOTC) LTE_CombineStr("\"MosOTC\":true,"); //6+4 + 5 + if(MosOTD) LTE_CombineStr("\"MosOTD\":true,"); //6+4 + 5 + //if(MosUTC) LTE_CombineStr("\"MosUTC\":true,"); //6+4 + 5 + //if(MosUTD) LTE_CombineStr("\"MosUTD\":true,"); //6+4 + 5 + //报警 + if(PackOVWarning) LTE_CombineStr("\"PackOVWarning\":true,"); //6+4 + 5 + if(PackUVWarning) LTE_CombineStr("\"PackUVWarning\":true,"); //6+4 + 5 + if(CellOVWarning) LTE_CombineStr("\"CellOVWarning\":true,"); //6+4 + 5 + if(CellUVWarning) LTE_CombineStr("\"CellUVWarning\":true,"); //6+4 + 5 + if(OCCWarning) LTE_CombineStr("\"OCCWarning\":true,"); //3+4 + 5 + if(OCDWarning) LTE_CombineStr("\"OCDWarning\":true,"); //3+4 + 5 + if(McuOTCWarning) LTE_CombineStr("\"McuOTCWarning\":true,"); //6+7+4 + 5 + if(McuOTDWarning) LTE_CombineStr("\"McuOTDWarning\":true,"); //6+7+4 + 5 + if(McuUTCWarning) LTE_CombineStr("\"McuUTCWarning\":true,"); //6+7+4 + 5 + if(McuUTDWarning) LTE_CombineStr("\"McuUTDWarning\":true,"); //6+7+4 + 5 + if(AmbientOTCWarning) LTE_CombineStr("\"AmbientOTCWarning\":true,"); //10+7+4 + 5 + if(AmbientOTDWarning) LTE_CombineStr("\"AmbientOTDWarning\":true,"); //10+7+4 + 5 + if(AmbientUTCWarning) LTE_CombineStr("\"AmbientUTCWarning\":true,"); //10+7+4 + 5 + if(AmbientUTDWarning) LTE_CombineStr("\"AmbientUTDWarning\":true,"); //10+7+4 + 5 + if(MosOTCWarning) LTE_CombineStr("\"MosOTCWarning\":true,"); //6+7+4 + 5 + if(MosOTDWarning) LTE_CombineStr("\"MosOTDWarning\":true,"); //6+7+4 + 5 + //if(MosUTCWarning) LTE_CombineStr("\"MosUTCWarning\":true,"); //6+7+4 + 5 + //if(MosUTDWarning) LTE_CombineStr("\"MosUTDWarning\":true,"); //6+7+4 + 5 + + +3.5 +//浪涌短路锁定，报警灯常亮显示 + +//均衡状态不做事件 + + +3.9 +//增加默认更新： +////////////////////钰泰均衡控制逻辑 + +////////////////////钰泰均衡控制关闭的脉冲改短，防止超过了50us + +////////////////////上位机可读协议，通过选择协议0，会把当前协议读出 + +////////////////////浪涌短路锁定，报警灯常亮显示 + +////////////////////默认关异常高压保护，防止误报 +宁化100A：70 [1e] 6e d0 62 a8 8c 9b af 78 64 c3 18 1b 00 1a 50 64 46 ec f6 64 46 ec f6 [f8] +宁化100A：70 [1e] 6e d0 62 a8 8c 9b af 78 64 c3 18 1b 21 1a 50 64 46 ec f6 64 46 ec f6 [0e] + + +3.18 +////////////////////限流优化 +·初始占空比=（电池电压+1V）/默认充电器电压60V * 100% +·非充电状态关闭限流，等待8s + + +3.20 +////////////////////4G优化 +//根据家储更新驻启的4G后，驻启又在测试中增加了一些更新，现在同步到家储里 + +////////////////////适配新IAP_V2.5 + +////////////////////OCV只减不增 + + +////////////////////优化代码量 +Program Size: Code=125592 RO-data=6808 RW-data=1504 ZI-data=12160 +125592+6808+1504 = 133904 = 130K超出上限120K + +·不选择三选一小板的代码量 +Program Size: Code=87534 RO-data=5962 RW-data=1300 ZI-data=7004 +87534+5962+1300 = 94796 = 92K +133904-94796 = 39108 >38K + +·Pylon电总协议应该以字符串格式填写，但是目前是硬写的 +Program Size: Code=84898 RO-data=5962 RW-data=1300 ZI-data=7004 +84898+5962+1300 = 92160 +94796-92160 = 2636 >2K + +·【优化方案】 +①合并大量重复的参数处理逻辑，采用表驱动方式重构： +定义参数信息结构体： + + +·写函数改良： +Program Size: Code=126948 RO-data=6804 RW-data=1520 ZI-data=12160 +126948+6804+1520 = 135272 +Program Size: Code=123196 RO-data=7552 RW-data=1524 ZI-data=12164 +123196+7552+1524 = 132272 +135272-132272 = 3000 +·读函数改良 +Program Size: Code=123196 RO-data=7552 RW-data=1524 ZI-data=12164 +123196+7552+1524 = 132272 +Program Size: Code=121096 RO-data=7556 RW-data=1524 ZI-data=12164 +121096+7556+1524 = 130176 +132272-130176 = 2096 + +·在LTE_4G_IT_Update()和LTE_4G_IQ_Transmit()中，大量if(LTE_status == xxx)结构 + 建立状态函数指针数组，循环调用判断 +·字符串常量重复， + 一致的统一使用宏定义，相似的抽取出一个通用函数使用宏定义 + + +////////////////////另外，采样电阻是8个2mΩ +对应电流=电压*4 +//AFE保护值要改为60mV 70mV 60mV(保存时的固定值) +//Flash保存值： +//异常高压已关闭 +原值：70 1e 6e d0 62 a8 8c 9b af 78 64 c3 18 1b 00 1a 50 64 46 ec f6 64 46 ec f6 f8 +新值：70 1e 6e d0 62 a8 8c 9b af 78 64 c3 48 4b 00 4a 50 64 46 ec f6 64 46 ec f6 46 +//增益校准参数默认值已改7000 + + +////////////////////OTA升级 +·IAP标志使用IIC存储，因为换了板子所以不需要兼容旧IAP，不用考虑擦除跳转标志 +·但是写跳转标志的操作可以保留，这样能兼容直接烧写Flash时无法跳转用户程序的问题 + + +////////////////////减少已有协议 +原有： +Program Size: Code=122080 RO-data=7556 RW-data=1544 ZI-data=12160 +122080+7556+1544 = 131180 +去掉全部协议后： +Program Size: Code=98212 RO-data=7552 RW-data=1540 ZI-data=12164 +98212+7552+1540 = 107304 = 104K +131180-107304 = 23876 + +启用Sol-Ark,Growatt,Pylon,Voltronic +Program Size: Code=103472 RO-data=7556 RW-data=1540 ZI-data=12164 +103472+7556+1540 = 112568 +再启用德业，锦浪 +Program Size: Code=104840 RO-data=7556 RW-data=1544 ZI-data=12160 +103472+7556+1544 = 112572 = 109K +对应序号：1.3.11.12.14.37 + + +////////////////////低压休眠是关闭电源 +·若开启1min无任何充电电流，会继续进入低压休眠 + ——低压休眠时间调1min +·低压休眠条件删去均衡判断，删去充放电判断，删去对其他报警的判断 + 只判断是否有充电电流 + + +////////////////////开机后，5V运行灯亮 +·长按后灯亮，表示开始运行 + + +////////////////////加热逻辑，和华富一样 +·充电低温加热释放+2,欠压禁止加热 +·控制引脚是PC6 + + +////////////////////IAP跳转时，若初始LED灯置高，会在短按时也瞬闪一下 +·长按版，初始LED默认置低，之后再置高即可 +·关机前留给复位的过程 + + +////////////////////复位功能先不启用 + +////////////////////报警灯灭的比较晚，最好在运行灯那里一起执行 + +{"request_id":"gca20ac1f929j4c51834","params":["Protocol","InverterChgVol","InverterDsgVol","InverterChgCur","InverterDsgCur","POV_Vol","POVR_Vol","PUV_Vol","PUVR_Vol","COV_Vol","COVR_Vol","CUV_Vol","CUVR_Vol","SC_Cur","SC_Delay","OCC_Cur","OCC_Delay","OCD1_Cur","OCD1_Delay","OTC_Temp","OTCR_Temp","OTD_Temp","OTDR_Temp","UTC_Temp","UTCR_Temp","UTD_Temp","UTDR_Temp","SOC","CYC","Capacity"]} + +Program Size: Code=107008 RO-data=7556 RW-data=1552 ZI-data=14376 + + +////////////////////3.23新版打回，从8个2mΩ改为9个1mΩ +//对应电流=电压*9 +//增益校准参数默认值改10000 +//AFE保护值要改为30mV 40mV 30mV(保存时的固定值) +//Flash保存值： +70 1e 6e d0 62 a8 8c 9b af 78 64 c3 18 1b 00 1a 50 64 46 ec f6 64 46 ec f6 f8 + + +///////////////////事件和各种回复，都有计数，超时则返回 +·上报完成后则清零计数 + + +///////////////////事件上报删去预警 + + +///////////////////4G通信数组增大到1000 +Program Size: Code=106676 RO-data=7552 RW-data=1556 ZI-data=17524 +106676+7552+1556 = 115784 + + +///////////////////HardFault_Handler()重启 +(长按版会关机) + + +////////////////////Wh版屏幕，要同时兼容VTc和SDWn，所以部分地址要改 +部分超出0x3FF但是VTc还要支持的地址： +0x05A9 +0x05AA +0x05B5 +0x05B6 + +部分改为两者兼容的地址： +0x05A0 -> 0x0366 +0x05A3 -> 0x0361 +0x05A4 -> 0x0100(原地址) +0x05A5 -> 0x0362 +0x05A7 -> 0x0364 +0x05A8 -> 0x0365 +0x05B1 -> 0x0371 +0x05B2 -> 0x0372 +0x05B3 -> 0x0373 +0x05B4 -> 0x0374 +0x05B8 -> 0x0375 +0x05B9 -> 0x0376 +0x05BA -> 0x0377 +0x05BB -> 0x0378 + +参考旭尊RE版， +不加变色，时间显示不用空3个空格，报警记录仍然1页3条， +首页没有总消耗功率,充放电状态图标用原版 + +Program Size: Code=107980 RO-data=7552 RW-data=1556 ZI-data=16708 +107980+7552+1556 = 117088 =114K + + +////////////////////因为有时候会触发重启，所以考虑将长按按钮才置电源高，改为读Flash标志 +Flash标志存于第128+2K，第128K存OTA信息了，第128+4K存原有程序了 + + +4.2 +//预充逻辑更新： +·开机预充： +开机保持MOS关闭，预充1s(可设)后释放，并打开MOS +·开放电MOS前开预充： +当放电MOS此前关闭，要打开时，先维持不要打开，预充8s(可设)后释放，并打开放电MOS +·浪涌短路改为普通保护，会亮灯会提醒会上报事件 + + +4.6 +//屏幕点亮不能退出休眠？ + 因为加了休眠判断，现已删去 +//退出休眠后4G不上线？ + 因为休眠时加了4G休眠，但退出休眠时没有加退出4G休眠 + +//150A参数 +70 1e 6e d0 62 a8 87 91 af 78 64 bb 18 1b 10 1a 50 64 46 ec f6 64 46 ec f6 8f 3c 37 00 05 41 3c ec f1 9b 9b 01 01 1e 89 96 05 3c 00 +30 02 1c 02 cc 01 e5 01 01 01 a0 00 04 00 46 41 ec f1 46 41 ec f1 60 60 10 00 00 00 00 00 00 00 de 0d f0 0a 2b 02 e0 01 8c 8c 37 05 3c f1 41 f1 41 f1 5f f1 5f f1 + + +4.7 +//屏幕显示时间要timecount-8h + 中国固定T8时区 +//OCV校准用3A不对，需要改0.5A +//看门狗时间放长到16s，并把喂狗提前 +//因为是长按，软件重启时要保持MOS控制不能启动预充 + +//使用强制关闭欠压的倒计时文本，显示4G当前状态 + + +4.13 +//增加平台执行电流校准 + + +4.14 +//增加4G掉线定期检查，防止在线后却没有实际发送任何内容 + + +4.15 +//对检查订阅的步骤，增加超时计算，连续3次无响应则执行下一步 +//若在回复处理函数中持续累积次数，在4G模块不回复时会无法继续累加 + + +4.16 +//加热继电器改为可选开关功能，默认不带，不影响充电低温保护直接执行 + + +4.20 +//4G模块通信太快会导致4G异常 + + +4.22 +//上位机改SN号后，上报的主题里的SN号没有更新——要在修改SN号之后更新SN号的字符串，并且使可继续通信 +//屏幕在4G无回复时显示Null + + +//单芯电压纠正 +·上报4G/蓝牙/WIFI的单芯电压，若超出5119mV，更正显示负值 +·逆变器协议里，需要单芯电压的也改为输出cellVol[] +·汇总数据过程，仍保留原值，但收到并处理时，存入另外的变量里 +//保护记录中，单芯电压范围0~4095 + + +//OCV校准，校准检查+静置电流改0.5A+等待时间改4h+关机时间不算 + +//增加更多4G报文显示在屏幕，囊括connect +//优化LTE_lastFlag为LTE_ResendDelay，延后时间改2s，并且把ERROR里的计数改/2 + + +4.27 +//OCV时间存储恢复 +//并机数据更新函数，放计算SOC后面 +//Pylon电总协议，温度补充 + + +4.28 +//并机计算负值电芯电压，[0]的值没赋值，恢复 +//SDWA屏幕显示，不能显示负值，小于的直接显示0 + + +5.6 +//参数检查 + 把paraMem.fcc_改为paraMem.soc100_ + paraMem.ctrl_disable只控制bit0/1/2 +//写SN号时更新函数调用错了，已改 + + +5.8 +//发现屏幕写逆变器值，有3个重启后会变回去 +·因为和告警电流的联系，导致一直更新 +·其实不需要将paraMem写入EEPROM，问题也是出在这里，已经超出了1次写的最大长度 +·staPack.bits.eepromUpdate保留，可后续用于显示写EEPROM错误，目前只显示写AFE的EEPROM错误 + + +5.12 +//4G报文优化： +屏幕显示rssi值和network值 +CGREG收到2，不算异常，等待3s后才再次询问 +CFUN=0/1之后，要等3s后询问 + +CSQ回复ERROR，持续20s就重启4G模块(因为这个不太应该的) +屏幕显示报文，有的长度太长改短一点 + + +5.12 +//4G报文优化： +屏幕显示rssi值和network值 +CGREG收到2，不算异常，等待3s后才再次询问 +CFUN=0/1之后，要等3s后询问 + +CSQ回复ERROR，持续20s就重启4G模块(因为这个不太应该的) +屏幕显示报文，有的长度太长改短一点 + +network改net + + +5.13 +//自动分配启动条件优化 +当从机回复轮询，收到的字节数比正常多，记录1次 + +//协议改为24个，其中6个实际可用 + +//移植陶晶驰屏幕相关 + +//自动分配地址优化 +1.自动分配地址，时序从0.5s改1s发1次，毕竟是写地址要更新的 +2.自动分配地址启动条件，增加轮询收到回复，但无法解析，超过10次执行自动分配 + + +//屏幕的24个协议，序号对应 + 1."Sol-Ark", 2."GoodWe", 30."Megarevo", 12."Pylon", + 11."Deye", 7."MUST", 37."solis", 3."Growatt", + 4."Aiswei", 35."Afore", 27."Victron", 6."Sorotec", + + 5."SMA", *."Sunways", 23."Luxpower", 24."Schneider", + *"AlpSolarr", 13."SRNE", 14."Voltronic", 32."COSUPER", + 17."SMK", 31."SAKO", 18."SNADI", 21."invt", + + +//屏幕显示充放电剩余时间，最少是5*0.1A而不是500*0.1A + + + + + + + +预计更新： +//屏幕显示4G当前状态，改一个新值存储，不占用原值 +//屏幕改陶晶驰相关 +//屏幕协议用新版本 +//4G模块无回复时是否还要加延时？ + + +//未来优化： +·CAN错误中断加上 +·4G当前状态，显示在上位机 + diff --git a/STM32F10x_FWLIB/inc/misc.h b/STM32F10x_FWLIB/inc/misc.h new file mode 100644 index 0000000..03e25e6 --- /dev/null +++ b/STM32F10x_FWLIB/inc/misc.h @@ -0,0 +1,218 @@ +/** + ****************************************************************************** + * @file misc.h + * @author MCD Application Team + * @version V3.6.2 + * @date 17-September-2021 + * @brief This file contains all the functions prototypes for the miscellaneous + * firmware library functions (add-on to CMSIS functions). + ****************************************************************************** + * @attention + * + * Copyright (c) 2012 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MISC_H +#define __MISC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup MISC + * @{ + */ + +/** @defgroup MISC_Exported_Types + * @{ + */ + +/** + * @brief NVIC Init Structure definition + */ + +typedef struct +{ + uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. + This parameter can be a value of @ref IRQn_Type + (For the complete STM32 Devices IRQ Channels list, please + refer to stm32f10x.h file) */ + + uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel + specified in NVIC_IRQChannel. This parameter can be a value + between 0 and 15 as described in the table @ref NVIC_Priority_Table */ + + uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified + in NVIC_IRQChannel. This parameter can be a value + between 0 and 15 as described in the table @ref NVIC_Priority_Table */ + + FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel + will be enabled or disabled. + This parameter can be set either to ENABLE or DISABLE */ +} NVIC_InitTypeDef; + +/** + * @} + */ + +/** @defgroup NVIC_Priority_Table + * @{ + */ + +/** +@code + The table below gives the allowed values of the pre-emption priority and subpriority according + to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function + ============================================================================================================================ + NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description + ============================================================================================================================ + NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority + | | | 4 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority + | | | 3 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority + | | | 2 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority + | | | 1 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority + | | | 0 bits for subpriority + ============================================================================================================================ +@endcode +*/ + +/** + * @} + */ + +/** @defgroup MISC_Exported_Constants + * @{ + */ + +/** @defgroup Vector_Table_Base + * @{ + */ + +#define NVIC_VectTab_RAM ((uint32_t)0x20000000) +#define NVIC_VectTab_FLASH ((uint32_t)0x08000000) +#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ + ((VECTTAB) == NVIC_VectTab_FLASH)) +/** + * @} + */ + +/** @defgroup System_Low_Power + * @{ + */ + +#define NVIC_LP_SEVONPEND ((uint8_t)0x10) +#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) +#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) +#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ + ((LP) == NVIC_LP_SLEEPDEEP) || \ + ((LP) == NVIC_LP_SLEEPONEXIT)) +/** + * @} + */ + +/** @defgroup Preemption_Priority_Group + * @{ + */ + +#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority + 4 bits for subpriority */ +#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority + 3 bits for subpriority */ +#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority + 2 bits for subpriority */ +#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority + 1 bits for subpriority */ +#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority + 0 bits for subpriority */ + +#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ + ((GROUP) == NVIC_PriorityGroup_1) || \ + ((GROUP) == NVIC_PriorityGroup_2) || \ + ((GROUP) == NVIC_PriorityGroup_3) || \ + ((GROUP) == NVIC_PriorityGroup_4)) + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) + +/** + * @} + */ + +/** @defgroup SysTick_clock_source + * @{ + */ + +#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) +#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ + ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup MISC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Exported_Functions + * @{ + */ + +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); +void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); +void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); +void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); + +#ifdef __cplusplus +} +#endif + +#endif /* __MISC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/STM32F10x_FWLIB/inc/stm32f10x_adc.h b/STM32F10x_FWLIB/inc/stm32f10x_adc.h new file mode 100644 index 0000000..c357a39 --- /dev/null +++ b/STM32F10x_FWLIB/inc/stm32f10x_adc.h @@ -0,0 +1,481 @@ +/** + ****************************************************************************** + * @file stm32f10x_adc.h + * @author MCD Application Team + * @version V3.6.2 + * @date 17-September-2021 + * @brief This file contains all the functions prototypes for the ADC firmware + * library. + ****************************************************************************** + * @attention + * + * Copyright (c) 2012 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_ADC_H +#define __STM32F10x_ADC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup ADC + * @{ + */ + +/** @defgroup ADC_Exported_Types + * @{ + */ + +/** + * @brief ADC Init structure definition + */ + +typedef struct +{ + uint32_t ADC_Mode; /*!< Configures the ADC to operate in independent or + dual mode. + This parameter can be a value of @ref ADC_mode */ + + FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion is performed in + Scan (multichannels) or Single (one channel) mode. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in + Continuous or Single mode. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog + to digital conversion of regular channels. This parameter + can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */ + + uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right. + This parameter can be a value of @ref ADC_data_align */ + + uint8_t ADC_NbrOfChannel; /*!< Specifies the number of ADC channels that will be converted + using the sequencer for regular channel group. + This parameter must range from 1 to 16. */ +}ADC_InitTypeDef; +/** + * @} + */ + +/** @defgroup ADC_Exported_Constants + * @{ + */ + +#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ + ((PERIPH) == ADC2) || \ + ((PERIPH) == ADC3)) + +#define IS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ + ((PERIPH) == ADC3)) + +/** @defgroup ADC_mode + * @{ + */ + +#define ADC_Mode_Independent ((uint32_t)0x00000000) +#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000) +#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000) +#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000) +#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000) +#define ADC_Mode_InjecSimult ((uint32_t)0x00050000) +#define ADC_Mode_RegSimult ((uint32_t)0x00060000) +#define ADC_Mode_FastInterl ((uint32_t)0x00070000) +#define ADC_Mode_SlowInterl ((uint32_t)0x00080000) +#define ADC_Mode_AlterTrig ((uint32_t)0x00090000) + +#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \ + ((MODE) == ADC_Mode_RegInjecSimult) || \ + ((MODE) == ADC_Mode_RegSimult_AlterTrig) || \ + ((MODE) == ADC_Mode_InjecSimult_FastInterl) || \ + ((MODE) == ADC_Mode_InjecSimult_SlowInterl) || \ + ((MODE) == ADC_Mode_InjecSimult) || \ + ((MODE) == ADC_Mode_RegSimult) || \ + ((MODE) == ADC_Mode_FastInterl) || \ + ((MODE) == ADC_Mode_SlowInterl) || \ + ((MODE) == ADC_Mode_AlterTrig)) +/** + * @} + */ + +/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion + * @{ + */ + +#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000) /*!< For ADC1 and ADC2 */ + +#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) /*!< For ADC1, ADC2 and ADC3 */ +#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) /*!< For ADC1, ADC2 and ADC3 */ + +#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000) /*!< For ADC3 only */ +#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000) /*!< For ADC3 only */ +#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000) /*!< For ADC3 only */ +#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000) /*!< For ADC3 only */ +#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000) /*!< For ADC3 only */ +#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000) /*!< For ADC3 only */ + +#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \ + ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO) || \ + ((REGTRIG) == ADC_ExternalTrigConv_None) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3)) +/** + * @} + */ + +/** @defgroup ADC_data_align + * @{ + */ + +#define ADC_DataAlign_Right ((uint32_t)0x00000000) +#define ADC_DataAlign_Left ((uint32_t)0x00000800) +#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \ + ((ALIGN) == ADC_DataAlign_Left)) +/** + * @} + */ + +/** @defgroup ADC_channels + * @{ + */ + +#define ADC_Channel_0 ((uint8_t)0x00) +#define ADC_Channel_1 ((uint8_t)0x01) +#define ADC_Channel_2 ((uint8_t)0x02) +#define ADC_Channel_3 ((uint8_t)0x03) +#define ADC_Channel_4 ((uint8_t)0x04) +#define ADC_Channel_5 ((uint8_t)0x05) +#define ADC_Channel_6 ((uint8_t)0x06) +#define ADC_Channel_7 ((uint8_t)0x07) +#define ADC_Channel_8 ((uint8_t)0x08) +#define ADC_Channel_9 ((uint8_t)0x09) +#define ADC_Channel_10 ((uint8_t)0x0A) +#define ADC_Channel_11 ((uint8_t)0x0B) +#define ADC_Channel_12 ((uint8_t)0x0C) +#define ADC_Channel_13 ((uint8_t)0x0D) +#define ADC_Channel_14 ((uint8_t)0x0E) +#define ADC_Channel_15 ((uint8_t)0x0F) +#define ADC_Channel_16 ((uint8_t)0x10) +#define ADC_Channel_17 ((uint8_t)0x11) + +#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) +#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) + +#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \ + ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \ + ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \ + ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \ + ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \ + ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \ + ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \ + ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \ + ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17)) +/** + * @} + */ + +/** @defgroup ADC_sampling_time + * @{ + */ + +#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00) +#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01) +#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02) +#define ADC_SampleTime_28Cycles5 ((uint8_t)0x03) +#define ADC_SampleTime_41Cycles5 ((uint8_t)0x04) +#define ADC_SampleTime_55Cycles5 ((uint8_t)0x05) +#define ADC_SampleTime_71Cycles5 ((uint8_t)0x06) +#define ADC_SampleTime_239Cycles5 ((uint8_t)0x07) +#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \ + ((TIME) == ADC_SampleTime_7Cycles5) || \ + ((TIME) == ADC_SampleTime_13Cycles5) || \ + ((TIME) == ADC_SampleTime_28Cycles5) || \ + ((TIME) == ADC_SampleTime_41Cycles5) || \ + ((TIME) == ADC_SampleTime_55Cycles5) || \ + ((TIME) == ADC_SampleTime_71Cycles5) || \ + ((TIME) == ADC_SampleTime_239Cycles5)) +/** + * @} + */ + +/** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion + * @{ + */ + +#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) /*!< For ADC1 and ADC2 */ + +#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) /*!< For ADC1, ADC2 and ADC3 */ +#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) /*!< For ADC1, ADC2 and ADC3 */ +#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) /*!< For ADC1, ADC2 and ADC3 */ + +#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000) /*!< For ADC3 only */ +#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000) /*!< For ADC3 only */ +#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000) /*!< For ADC3 only */ +#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000) /*!< For ADC3 only */ +#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000) /*!< For ADC3 only */ + +#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_None) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4)) +/** + * @} + */ + +/** @defgroup ADC_injected_channel_selection + * @{ + */ + +#define ADC_InjectedChannel_1 ((uint8_t)0x14) +#define ADC_InjectedChannel_2 ((uint8_t)0x18) +#define ADC_InjectedChannel_3 ((uint8_t)0x1C) +#define ADC_InjectedChannel_4 ((uint8_t)0x20) +#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \ + ((CHANNEL) == ADC_InjectedChannel_2) || \ + ((CHANNEL) == ADC_InjectedChannel_3) || \ + ((CHANNEL) == ADC_InjectedChannel_4)) +/** + * @} + */ + +/** @defgroup ADC_analog_watchdog_selection + * @{ + */ + +#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) +#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) +#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) +#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) +#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) +#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) +#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) + +#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_None)) +/** + * @} + */ + +/** @defgroup ADC_interrupts_definition + * @{ + */ + +#define ADC_IT_EOC ((uint16_t)0x0220) +#define ADC_IT_AWD ((uint16_t)0x0140) +#define ADC_IT_JEOC ((uint16_t)0x0480) + +#define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00)) + +#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \ + ((IT) == ADC_IT_JEOC)) +/** + * @} + */ + +/** @defgroup ADC_flags_definition + * @{ + */ + +#define ADC_FLAG_AWD ((uint8_t)0x01) +#define ADC_FLAG_EOC ((uint8_t)0x02) +#define ADC_FLAG_JEOC ((uint8_t)0x04) +#define ADC_FLAG_JSTRT ((uint8_t)0x08) +#define ADC_FLAG_STRT ((uint8_t)0x10) +#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xE0) == 0x00) && ((FLAG) != 0x00)) +#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \ + ((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \ + ((FLAG) == ADC_FLAG_STRT)) +/** + * @} + */ + +/** @defgroup ADC_thresholds + * @{ + */ + +#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF) + +/** + * @} + */ + +/** @defgroup ADC_injected_offset + * @{ + */ + +#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF) + +/** + * @} + */ + +/** @defgroup ADC_injected_length + * @{ + */ + +#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4)) + +/** + * @} + */ + +/** @defgroup ADC_injected_rank + * @{ + */ + +#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4)) + +/** + * @} + */ + + +/** @defgroup ADC_regular_length + * @{ + */ + +#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10)) +/** + * @} + */ + +/** @defgroup ADC_regular_rank + * @{ + */ + +#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10)) + +/** + * @} + */ + +/** @defgroup ADC_regular_discontinuous_mode_number + * @{ + */ + +#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8)) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup ADC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup ADC_Exported_Functions + * @{ + */ + +void ADC_DeInit(ADC_TypeDef* ADCx); +void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct); +void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); +void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState); +void ADC_ResetCalibration(ADC_TypeDef* ADCx); +FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx); +void ADC_StartCalibration(ADC_TypeDef* ADCx); +FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx); +void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx); +void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number); +void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx); +uint32_t ADC_GetDualModeConversionValue(void); +void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv); +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx); +void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length); +void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel); +void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog); +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold); +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel); +void ADC_TempSensorVrefintCmd(FunctionalState NewState); +FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); +void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); +ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT); +void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F10x_ADC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/STM32F10x_FWLIB/inc/stm32f10x_bkp.h b/STM32F10x_FWLIB/inc/stm32f10x_bkp.h new file mode 100644 index 0000000..2eeb73b --- /dev/null +++ b/STM32F10x_FWLIB/inc/stm32f10x_bkp.h @@ -0,0 +1,193 @@ +/** + ****************************************************************************** + * @file stm32f10x_bkp.h + * @author MCD Application Team + * @version V3.6.2 + * @date 17-September-2021 + * @brief This file contains all the functions prototypes for the BKP firmware + * library. + ****************************************************************************** + * @attention + * + * Copyright (c) 2012 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_BKP_H +#define __STM32F10x_BKP_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup BKP + * @{ + */ + +/** @defgroup BKP_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup BKP_Exported_Constants + * @{ + */ + +/** @defgroup Tamper_Pin_active_level + * @{ + */ + +#define BKP_TamperPinLevel_High ((uint16_t)0x0000) +#define BKP_TamperPinLevel_Low ((uint16_t)0x0001) +#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \ + ((LEVEL) == BKP_TamperPinLevel_Low)) +/** + * @} + */ + +/** @defgroup RTC_output_source_to_output_on_the_Tamper_pin + * @{ + */ + +#define BKP_RTCOutputSource_None ((uint16_t)0x0000) +#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080) +#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100) +#define BKP_RTCOutputSource_Second ((uint16_t)0x0300) +#define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \ + ((SOURCE) == BKP_RTCOutputSource_CalibClock) || \ + ((SOURCE) == BKP_RTCOutputSource_Alarm) || \ + ((SOURCE) == BKP_RTCOutputSource_Second)) +/** + * @} + */ + +/** @defgroup Data_Backup_Register + * @{ + */ + +#define BKP_DR1 ((uint16_t)0x0004) +#define BKP_DR2 ((uint16_t)0x0008) +#define BKP_DR3 ((uint16_t)0x000C) +#define BKP_DR4 ((uint16_t)0x0010) +#define BKP_DR5 ((uint16_t)0x0014) +#define BKP_DR6 ((uint16_t)0x0018) +#define BKP_DR7 ((uint16_t)0x001C) +#define BKP_DR8 ((uint16_t)0x0020) +#define BKP_DR9 ((uint16_t)0x0024) +#define BKP_DR10 ((uint16_t)0x0028) +#define BKP_DR11 ((uint16_t)0x0040) +#define BKP_DR12 ((uint16_t)0x0044) +#define BKP_DR13 ((uint16_t)0x0048) +#define BKP_DR14 ((uint16_t)0x004C) +#define BKP_DR15 ((uint16_t)0x0050) +#define BKP_DR16 ((uint16_t)0x0054) +#define BKP_DR17 ((uint16_t)0x0058) +#define BKP_DR18 ((uint16_t)0x005C) +#define BKP_DR19 ((uint16_t)0x0060) +#define BKP_DR20 ((uint16_t)0x0064) +#define BKP_DR21 ((uint16_t)0x0068) +#define BKP_DR22 ((uint16_t)0x006C) +#define BKP_DR23 ((uint16_t)0x0070) +#define BKP_DR24 ((uint16_t)0x0074) +#define BKP_DR25 ((uint16_t)0x0078) +#define BKP_DR26 ((uint16_t)0x007C) +#define BKP_DR27 ((uint16_t)0x0080) +#define BKP_DR28 ((uint16_t)0x0084) +#define BKP_DR29 ((uint16_t)0x0088) +#define BKP_DR30 ((uint16_t)0x008C) +#define BKP_DR31 ((uint16_t)0x0090) +#define BKP_DR32 ((uint16_t)0x0094) +#define BKP_DR33 ((uint16_t)0x0098) +#define BKP_DR34 ((uint16_t)0x009C) +#define BKP_DR35 ((uint16_t)0x00A0) +#define BKP_DR36 ((uint16_t)0x00A4) +#define BKP_DR37 ((uint16_t)0x00A8) +#define BKP_DR38 ((uint16_t)0x00AC) +#define BKP_DR39 ((uint16_t)0x00B0) +#define BKP_DR40 ((uint16_t)0x00B4) +#define BKP_DR41 ((uint16_t)0x00B8) +#define BKP_DR42 ((uint16_t)0x00BC) + +#define IS_BKP_DR(DR) (((DR) == BKP_DR1) || ((DR) == BKP_DR2) || ((DR) == BKP_DR3) || \ + ((DR) == BKP_DR4) || ((DR) == BKP_DR5) || ((DR) == BKP_DR6) || \ + ((DR) == BKP_DR7) || ((DR) == BKP_DR8) || ((DR) == BKP_DR9) || \ + ((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \ + ((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \ + ((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \ + ((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \ + ((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \ + ((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \ + ((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \ + ((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \ + ((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \ + ((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \ + ((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42)) + +#define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup BKP_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup BKP_Exported_Functions + * @{ + */ + +void BKP_DeInit(void); +void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel); +void BKP_TamperPinCmd(FunctionalState NewState); +void BKP_ITConfig(FunctionalState NewState); +void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource); +void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue); +void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data); +uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR); +FlagStatus BKP_GetFlagStatus(void); +void BKP_ClearFlag(void); +ITStatus BKP_GetITStatus(void); +void BKP_ClearITPendingBit(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_BKP_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/STM32F10x_FWLIB/inc/stm32f10x_can.h b/STM32F10x_FWLIB/inc/stm32f10x_can.h new file mode 100644 index 0000000..75f7717 --- /dev/null +++ b/STM32F10x_FWLIB/inc/stm32f10x_can.h @@ -0,0 +1,695 @@ +/** + ****************************************************************************** + * @file stm32f10x_can.h + * @author MCD Application Team + * @version V3.6.2 + * @date 17-September-2021 + * @brief This file contains all the functions prototypes for the CAN firmware + * library. + ****************************************************************************** + * @attention + * + * Copyright (c) 2012 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_CAN_H +#define __STM32F10x_CAN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CAN + * @{ + */ + +/** @defgroup CAN_Exported_Types + * @{ + */ + +#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \ + ((PERIPH) == CAN2)) + +/** + * @brief CAN init structure definition + */ + +typedef struct +{ + uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum. + It ranges from 1 to 1024. */ + + uint8_t CAN_Mode; /*!< Specifies the CAN operating mode. + This parameter can be a value of + @ref CAN_operating_mode */ + + uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta + the CAN hardware is allowed to lengthen or + shorten a bit to perform resynchronization. + This parameter can be a value of + @ref CAN_synchronisation_jump_width */ + + uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit + Segment 1. This parameter can be a value of + @ref CAN_time_quantum_in_bit_segment_1 */ + + uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit + Segment 2. + This parameter can be a value of + @ref CAN_time_quantum_in_bit_segment_2 */ + + FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered + communication mode. This parameter can be set + either to ENABLE or DISABLE. */ + + FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off + management. This parameter can be set either + to ENABLE or DISABLE. */ + + FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode. + This parameter can be set either to ENABLE or + DISABLE. */ + + FunctionalState CAN_NART; /*!< Enable or disable the no-automatic + retransmission mode. This parameter can be + set either to ENABLE or DISABLE. */ + + FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode. + This parameter can be set either to ENABLE + or DISABLE. */ + + FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority. + This parameter can be set either to ENABLE + or DISABLE. */ +} CAN_InitTypeDef; + +/** + * @brief CAN filter init structure definition + */ + +typedef struct +{ + uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit + configuration, first one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit + configuration, second one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, + according to the mode (MSBs for a 32-bit configuration, + first one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, + according to the mode (LSBs for a 32-bit configuration, + second one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter. + This parameter can be a value of @ref CAN_filter_FIFO */ + + uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */ + + uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized. + This parameter can be a value of @ref CAN_filter_mode */ + + uint8_t CAN_FilterScale; /*!< Specifies the filter scale. + This parameter can be a value of @ref CAN_filter_scale */ + + FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter. + This parameter can be set either to ENABLE or DISABLE. */ +} CAN_FilterInitTypeDef; + +/** + * @brief CAN Tx message structure definition + */ + +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t IDE; /*!< Specifies the type of identifier for the message that + will be transmitted. This parameter can be a value + of @ref CAN_identifier_type */ + + uint8_t RTR; /*!< Specifies the type of frame for the message that will + be transmitted. This parameter can be a value of + @ref CAN_remote_transmission_request */ + + uint8_t DLC; /*!< Specifies the length of the frame that will be + transmitted. This parameter can be a value between + 0 to 8 */ + + uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 + to 0xFF. */ +} CanTxMsg; + +/** + * @brief CAN Rx message structure definition + */ + +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t IDE; /*!< Specifies the type of identifier for the message that + will be received. This parameter can be a value of + @ref CAN_identifier_type */ + + uint8_t RTR; /*!< Specifies the type of frame for the received message. + This parameter can be a value of + @ref CAN_remote_transmission_request */ + + uint8_t DLC; /*!< Specifies the length of the frame that will be received. + This parameter can be a value between 0 to 8 */ + + uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to + 0xFF. */ + + uint8_t FMI; /*!< Specifies the index of the filter the message stored in + the mailbox passes through. This parameter can be a + value between 0 to 0xFF */ +} CanRxMsg; + +/** + * @} + */ + +/** @defgroup CAN_Exported_Constants + * @{ + */ + +/** @defgroup CAN_sleep_constants + * @{ + */ + +#define CAN_InitStatus_Failed ((uint8_t)0x00) /*!< CAN initialization failed */ +#define CAN_InitStatus_Success ((uint8_t)0x01) /*!< CAN initialization OK */ + +/** + * @} + */ + +/** @defgroup CAN_Mode + * @{ + */ + +#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */ +#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */ +#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */ +#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */ + +#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \ + ((MODE) == CAN_Mode_LoopBack)|| \ + ((MODE) == CAN_Mode_Silent) || \ + ((MODE) == CAN_Mode_Silent_LoopBack)) +/** + * @} + */ + + +/** + * @defgroup CAN_Operating_Mode + * @{ + */ +#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /*!< Initialization mode */ +#define CAN_OperatingMode_Normal ((uint8_t)0x01) /*!< Normal mode */ +#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /*!< sleep mode */ + + +#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\ + ((MODE) == CAN_OperatingMode_Normal)|| \ + ((MODE) == CAN_OperatingMode_Sleep)) +/** + * @} + */ + +/** + * @defgroup CAN_Mode_Status + * @{ + */ + +#define CAN_ModeStatus_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */ +#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /*!< CAN entering the specific mode Succeed */ + + +/** + * @} + */ + +/** @defgroup CAN_synchronisation_jump_width + * @{ + */ + +#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */ +#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */ +#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */ + +#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \ + ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq)) +/** + * @} + */ + +/** @defgroup CAN_time_quantum_in_bit_segment_1 + * @{ + */ + +#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */ +#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */ +#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */ +#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */ +#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */ +#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */ +#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */ +#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */ +#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */ +#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */ +#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */ +#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */ +#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */ +#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */ +#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */ + +#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq) +/** + * @} + */ + +/** @defgroup CAN_time_quantum_in_bit_segment_2 + * @{ + */ + +#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */ +#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */ +#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */ +#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */ +#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */ +#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */ +#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */ + +#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq) + +/** + * @} + */ + +/** @defgroup CAN_clock_prescaler + * @{ + */ + +#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024)) + +/** + * @} + */ + +/** @defgroup CAN_filter_number + * @{ + */ +#ifndef STM32F10X_CL + #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13) +#else + #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27) +#endif /* STM32F10X_CL */ +/** + * @} + */ + +/** @defgroup CAN_filter_mode + * @{ + */ + +#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< identifier/mask mode */ +#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */ + +#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \ + ((MODE) == CAN_FilterMode_IdList)) +/** + * @} + */ + +/** @defgroup CAN_filter_scale + * @{ + */ + +#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */ +#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */ + +#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \ + ((SCALE) == CAN_FilterScale_32bit)) + +/** + * @} + */ + +/** @defgroup CAN_filter_FIFO + * @{ + */ + +#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ +#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ +#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \ + ((FIFO) == CAN_FilterFIFO1)) +/** + * @} + */ + +/** @defgroup Start_bank_filter_for_slave_CAN + * @{ + */ +#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27)) +/** + * @} + */ + +/** @defgroup CAN_Tx + * @{ + */ + +#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) +#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF)) +#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF)) +#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) + +/** + * @} + */ + +/** @defgroup CAN_identifier_type + * @{ + */ + +#define CAN_Id_Standard ((uint32_t)0x00000000) /*!< Standard Id */ +#define CAN_Id_Extended ((uint32_t)0x00000004) /*!< Extended Id */ +#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \ + ((IDTYPE) == CAN_Id_Extended)) +/** + * @} + */ + +/** @defgroup CAN_remote_transmission_request + * @{ + */ + +#define CAN_RTR_Data ((uint32_t)0x00000000) /*!< Data frame */ +#define CAN_RTR_Remote ((uint32_t)0x00000002) /*!< Remote frame */ +#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote)) + +/** + * @} + */ + +/** @defgroup CAN_transmit_constants + * @{ + */ + +#define CAN_TxStatus_Failed ((uint8_t)0x00)/*!< CAN transmission failed */ +#define CAN_TxStatus_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */ +#define CAN_TxStatus_Pending ((uint8_t)0x02) /*!< CAN transmission pending */ +#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */ + +/** + * @} + */ + +/** @defgroup CAN_receive_FIFO_number_constants + * @{ + */ + +#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */ +#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */ + +#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) + +/** + * @} + */ + +/** @defgroup CAN_sleep_constants + * @{ + */ + +#define CAN_Sleep_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */ +#define CAN_Sleep_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */ + +/** + * @} + */ + +/** @defgroup CAN_wake_up_constants + * @{ + */ + +#define CAN_WakeUp_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */ +#define CAN_WakeUp_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */ + +/** + * @} + */ + +/** + * @defgroup CAN_Error_Code_constants + * @{ + */ + +#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /*!< No Error */ +#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */ +#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /*!< Form Error */ +#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */ +#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */ +#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */ +#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */ +#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /*!< Software Set Error */ + + +/** + * @} + */ + +/** @defgroup CAN_flags + * @{ + */ +/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() + and CAN_ClearFlag() functions. */ +/* If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagStatus() function. */ + +/* Transmit Flags */ +#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */ +#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */ +#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */ + +/* Receive Flags */ +#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */ +#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag */ +#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag */ +#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */ +#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag */ +#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag */ + +/* Operating Mode Flags */ +#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */ +#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */ +/* Note: When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible. + In this case the SLAK bit can be polled.*/ + +/* Error Flags */ +#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /*!< Error Warning Flag */ +#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /*!< Error Passive Flag */ +#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /*!< Bus-Off Flag */ +#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */ + +#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \ + ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \ + ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \ + ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \ + ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \ + ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \ + ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \ + ((FLAG) == CAN_FLAG_SLAK )) + +#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \ + ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \ + ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\ + ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \ + ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK)) +/** + * @} + */ + + +/** @defgroup CAN_interrupts + * @{ + */ + + + +#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/ + +/* Receive Interrupts */ +#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/ +#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/ +#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/ +#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/ +#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/ +#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/ + +/* Operating Mode Interrupts */ +#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/ +#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/ + +/* Error Interrupts */ +#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/ +#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/ +#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/ +#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/ +#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/ + +/* Flags named as Interrupts : kept only for FW compatibility */ +#define CAN_IT_RQCP0 CAN_IT_TME +#define CAN_IT_RQCP1 CAN_IT_TME +#define CAN_IT_RQCP2 CAN_IT_TME + + +#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\ + ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\ + ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\ + ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\ + ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ + ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ + ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) + +#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\ + ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\ + ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\ + ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ + ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ + ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) + +/** + * @} + */ + +/** @defgroup CAN_Legacy + * @{ + */ +#define CANINITFAILED CAN_InitStatus_Failed +#define CANINITOK CAN_InitStatus_Success +#define CAN_FilterFIFO0 CAN_Filter_FIFO0 +#define CAN_FilterFIFO1 CAN_Filter_FIFO1 +#define CAN_ID_STD CAN_Id_Standard +#define CAN_ID_EXT CAN_Id_Extended +#define CAN_RTR_DATA CAN_RTR_Data +#define CAN_RTR_REMOTE CAN_RTR_Remote +#define CANTXFAILE CAN_TxStatus_Failed +#define CANTXOK CAN_TxStatus_Ok +#define CANTXPENDING CAN_TxStatus_Pending +#define CAN_NO_MB CAN_TxStatus_NoMailBox +#define CANSLEEPFAILED CAN_Sleep_Failed +#define CANSLEEPOK CAN_Sleep_Ok +#define CANWAKEUPFAILED CAN_WakeUp_Failed +#define CANWAKEUPOK CAN_WakeUp_Ok + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup CAN_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions + * @{ + */ +/* Function used to set the CAN configuration to the default reset state *****/ +void CAN_DeInit(CAN_TypeDef* CANx); + +/* Initialization and Configuration functions *********************************/ +uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct); +void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct); +void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct); +void CAN_SlaveStartBank(uint8_t CAN_BankNumber); +void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState); +void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState); + +/* Transmit functions *********************************************************/ +uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage); +uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox); +void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox); + +/* Receive functions **********************************************************/ +void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage); +void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber); +uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber); + + +/* Operation modes functions **************************************************/ +uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode); +uint8_t CAN_Sleep(CAN_TypeDef* CANx); +uint8_t CAN_WakeUp(CAN_TypeDef* CANx); + +/* Error management functions *************************************************/ +uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx); +uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx); +uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx); + +/* Interrupts and flags management functions **********************************/ +void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState); +FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG); +void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG); +ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT); +void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_CAN_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/STM32F10x_FWLIB/inc/stm32f10x_cec.h b/STM32F10x_FWLIB/inc/stm32f10x_cec.h new file mode 100644 index 0000000..1e6b75e --- /dev/null +++ b/STM32F10x_FWLIB/inc/stm32f10x_cec.h @@ -0,0 +1,208 @@ +/** + ****************************************************************************** + * @file stm32f10x_cec.h + * @author MCD Application Team + * @version V3.6.2 + * @date 17-September-2021 + * @brief This file contains all the functions prototypes for the CEC firmware + * library. + ****************************************************************************** + * @attention + * + * Copyright (c) 2012 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_CEC_H +#define __STM32F10x_CEC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CEC + * @{ + */ + + +/** @defgroup CEC_Exported_Types + * @{ + */ + +/** + * @brief CEC Init structure definition + */ +typedef struct +{ + uint16_t CEC_BitTimingMode; /*!< Configures the CEC Bit Timing Error Mode. + This parameter can be a value of @ref CEC_BitTiming_Mode */ + uint16_t CEC_BitPeriodMode; /*!< Configures the CEC Bit Period Error Mode. + This parameter can be a value of @ref CEC_BitPeriod_Mode */ +}CEC_InitTypeDef; + +/** + * @} + */ + +/** @defgroup CEC_Exported_Constants + * @{ + */ + +/** @defgroup CEC_BitTiming_Mode + * @{ + */ +#define CEC_BitTimingStdMode ((uint16_t)0x00) /*!< Bit timing error Standard Mode */ +#define CEC_BitTimingErrFreeMode CEC_CFGR_BTEM /*!< Bit timing error Free Mode */ + +#define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BitTimingStdMode) || \ + ((MODE) == CEC_BitTimingErrFreeMode)) +/** + * @} + */ + +/** @defgroup CEC_BitPeriod_Mode + * @{ + */ +#define CEC_BitPeriodStdMode ((uint16_t)0x00) /*!< Bit period error Standard Mode */ +#define CEC_BitPeriodFlexibleMode CEC_CFGR_BPEM /*!< Bit period error Flexible Mode */ + +#define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BitPeriodStdMode) || \ + ((MODE) == CEC_BitPeriodFlexibleMode)) +/** + * @} + */ + + +/** @defgroup CEC_interrupts_definition + * @{ + */ +#define CEC_IT_TERR CEC_CSR_TERR +#define CEC_IT_TBTRF CEC_CSR_TBTRF +#define CEC_IT_RERR CEC_CSR_RERR +#define CEC_IT_RBTF CEC_CSR_RBTF +#define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TERR) || ((IT) == CEC_IT_TBTRF) || \ + ((IT) == CEC_IT_RERR) || ((IT) == CEC_IT_RBTF)) +/** + * @} + */ + + +/** @defgroup CEC_Own_Address + * @{ + */ +#define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10) +/** + * @} + */ + +/** @defgroup CEC_Prescaler + * @{ + */ +#define IS_CEC_PRESCALER(PRESCALER) ((PRESCALER) <= 0x3FFF) + +/** + * @} + */ + +/** @defgroup CEC_flags_definition + * @{ + */ + +/** + * @brief ESR register flags + */ +#define CEC_FLAG_BTE ((uint32_t)0x10010000) +#define CEC_FLAG_BPE ((uint32_t)0x10020000) +#define CEC_FLAG_RBTFE ((uint32_t)0x10040000) +#define CEC_FLAG_SBE ((uint32_t)0x10080000) +#define CEC_FLAG_ACKE ((uint32_t)0x10100000) +#define CEC_FLAG_LINE ((uint32_t)0x10200000) +#define CEC_FLAG_TBTFE ((uint32_t)0x10400000) + +/** + * @brief CSR register flags + */ +#define CEC_FLAG_TEOM ((uint32_t)0x00000002) +#define CEC_FLAG_TERR ((uint32_t)0x00000004) +#define CEC_FLAG_TBTRF ((uint32_t)0x00000008) +#define CEC_FLAG_RSOM ((uint32_t)0x00000010) +#define CEC_FLAG_REOM ((uint32_t)0x00000020) +#define CEC_FLAG_RERR ((uint32_t)0x00000040) +#define CEC_FLAG_RBTF ((uint32_t)0x00000080) + +#define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF03) == 0x00) && ((FLAG) != 0x00)) + +#define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_BTE) || ((FLAG) == CEC_FLAG_BPE) || \ + ((FLAG) == CEC_FLAG_RBTFE) || ((FLAG)== CEC_FLAG_SBE) || \ + ((FLAG) == CEC_FLAG_ACKE) || ((FLAG) == CEC_FLAG_LINE) || \ + ((FLAG) == CEC_FLAG_TBTFE) || ((FLAG) == CEC_FLAG_TEOM) || \ + ((FLAG) == CEC_FLAG_TERR) || ((FLAG) == CEC_FLAG_TBTRF) || \ + ((FLAG) == CEC_FLAG_RSOM) || ((FLAG) == CEC_FLAG_REOM) || \ + ((FLAG) == CEC_FLAG_RERR) || ((FLAG) == CEC_FLAG_RBTF)) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup CEC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup CEC_Exported_Functions + * @{ + */ +void CEC_DeInit(void); +void CEC_Init(CEC_InitTypeDef* CEC_InitStruct); +void CEC_Cmd(FunctionalState NewState); +void CEC_ITConfig(FunctionalState NewState); +void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress); +void CEC_SetPrescaler(uint16_t CEC_Prescaler); +void CEC_SendDataByte(uint8_t Data); +uint8_t CEC_ReceiveDataByte(void); +void CEC_StartOfMessage(void); +void CEC_EndOfMessageCmd(FunctionalState NewState); +FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG); +void CEC_ClearFlag(uint32_t CEC_FLAG); +ITStatus CEC_GetITStatus(uint8_t CEC_IT); +void CEC_ClearITPendingBit(uint16_t CEC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_CEC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/STM32F10x_FWLIB/inc/stm32f10x_crc.h b/STM32F10x_FWLIB/inc/stm32f10x_crc.h new file mode 100644 index 0000000..9f89cd2 --- /dev/null +++ b/STM32F10x_FWLIB/inc/stm32f10x_crc.h @@ -0,0 +1,92 @@ +/** + ****************************************************************************** + * @file stm32f10x_crc.h + * @author MCD Application Team + * @version V3.6.2 + * @date 17-September-2021 + * @brief This file contains all the functions prototypes for the CRC firmware + * library. + ****************************************************************************** + * @attention + * + * Copyright (c) 2012 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_CRC_H +#define __STM32F10x_CRC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CRC + * @{ + */ + +/** @defgroup CRC_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Exported_Functions + * @{ + */ + +void CRC_ResetDR(void); +uint32_t CRC_CalcCRC(uint32_t Data); +uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); +uint32_t CRC_GetCRC(void); +void CRC_SetIDRegister(uint8_t IDValue); +uint8_t CRC_GetIDRegister(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_CRC_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/STM32F10x_FWLIB/inc/stm32f10x_dac.h b/STM32F10x_FWLIB/inc/stm32f10x_dac.h new file mode 100644 index 0000000..bca0216 --- /dev/null +++ b/STM32F10x_FWLIB/inc/stm32f10x_dac.h @@ -0,0 +1,315 @@ +/** + ****************************************************************************** + * @file stm32f10x_dac.h + * @author MCD Application Team + * @version V3.6.2 + * @date 17-September-2021 + * @brief This file contains all the functions prototypes for the DAC firmware + * library. + ****************************************************************************** + * @attention + * + * Copyright (c) 2012 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_DAC_H +#define __STM32F10x_DAC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DAC + * @{ + */ + +/** @defgroup DAC_Exported_Types + * @{ + */ + +/** + * @brief DAC Init structure definition + */ + +typedef struct +{ + uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. + This parameter can be a value of @ref DAC_trigger_selection */ + + uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves + are generated, or whether no wave is generated. + This parameter can be a value of @ref DAC_wave_generation */ + + uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or + the maximum amplitude triangle generation for the DAC channel. + This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */ + + uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. + This parameter can be a value of @ref DAC_output_buffer */ +}DAC_InitTypeDef; + +/** + * @} + */ + +/** @defgroup DAC_Exported_Constants + * @{ + */ + +/** @defgroup DAC_trigger_selection + * @{ + */ + +#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register + has been loaded, and not by external trigger */ +#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel + only in High-density devices*/ +#define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel + only in Connectivity line, Medium-density and Low-density Value Line devices */ +#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T15_TRGO ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel + only in Medium-density and Low-density Value Line devices*/ +#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */ + +#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \ + ((TRIGGER) == DAC_Trigger_T6_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T8_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T7_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T5_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T2_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T4_TRGO) || \ + ((TRIGGER) == DAC_Trigger_Ext_IT9) || \ + ((TRIGGER) == DAC_Trigger_Software)) + +/** + * @} + */ + +/** @defgroup DAC_wave_generation + * @{ + */ + +#define DAC_WaveGeneration_None ((uint32_t)0x00000000) +#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040) +#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080) +#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \ + ((WAVE) == DAC_WaveGeneration_Noise) || \ + ((WAVE) == DAC_WaveGeneration_Triangle)) +/** + * @} + */ + +/** @defgroup DAC_lfsrunmask_triangleamplitude + * @{ + */ + +#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ +#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ +#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */ +#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */ +#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */ +#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */ +#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */ +#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */ +#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */ +#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */ +#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */ +#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */ +#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */ +#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */ + +#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \ + ((VALUE) == DAC_TriangleAmplitude_1) || \ + ((VALUE) == DAC_TriangleAmplitude_3) || \ + ((VALUE) == DAC_TriangleAmplitude_7) || \ + ((VALUE) == DAC_TriangleAmplitude_15) || \ + ((VALUE) == DAC_TriangleAmplitude_31) || \ + ((VALUE) == DAC_TriangleAmplitude_63) || \ + ((VALUE) == DAC_TriangleAmplitude_127) || \ + ((VALUE) == DAC_TriangleAmplitude_255) || \ + ((VALUE) == DAC_TriangleAmplitude_511) || \ + ((VALUE) == DAC_TriangleAmplitude_1023) || \ + ((VALUE) == DAC_TriangleAmplitude_2047) || \ + ((VALUE) == DAC_TriangleAmplitude_4095)) +/** + * @} + */ + +/** @defgroup DAC_output_buffer + * @{ + */ + +#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000) +#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002) +#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \ + ((STATE) == DAC_OutputBuffer_Disable)) +/** + * @} + */ + +/** @defgroup DAC_Channel_selection + * @{ + */ + +#define DAC_Channel_1 ((uint32_t)0x00000000) +#define DAC_Channel_2 ((uint32_t)0x00000010) +#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \ + ((CHANNEL) == DAC_Channel_2)) +/** + * @} + */ + +/** @defgroup DAC_data_alignment + * @{ + */ + +#define DAC_Align_12b_R ((uint32_t)0x00000000) +#define DAC_Align_12b_L ((uint32_t)0x00000004) +#define DAC_Align_8b_R ((uint32_t)0x00000008) +#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \ + ((ALIGN) == DAC_Align_12b_L) || \ + ((ALIGN) == DAC_Align_8b_R)) +/** + * @} + */ + +/** @defgroup DAC_wave_generation + * @{ + */ + +#define DAC_Wave_Noise ((uint32_t)0x00000040) +#define DAC_Wave_Triangle ((uint32_t)0x00000080) +#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \ + ((WAVE) == DAC_Wave_Triangle)) +/** + * @} + */ + +/** @defgroup DAC_data + * @{ + */ + +#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) +/** + * @} + */ +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +/** @defgroup DAC_interrupts_definition + * @{ + */ + +#define DAC_IT_DMAUDR ((uint32_t)0x00002000) +#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) + +/** + * @} + */ + +/** @defgroup DAC_flags_definition + * @{ + */ + +#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000) +#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR)) + +/** + * @} + */ +#endif + +/** + * @} + */ + +/** @defgroup DAC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup DAC_Exported_Functions + * @{ + */ + +void DAC_DeInit(void); +void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct); +void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct); +void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState); +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState); +#endif +void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState); +void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState); +void DAC_DualSoftwareTriggerCmd(FunctionalState NewState); +void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState); +void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data); +void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data); +void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1); +uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel); +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG); +void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG); +ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT); +void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F10x_DAC_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/STM32F10x_FWLIB/inc/stm32f10x_dbgmcu.h b/STM32F10x_FWLIB/inc/stm32f10x_dbgmcu.h new file mode 100644 index 0000000..00872bf --- /dev/null +++ b/STM32F10x_FWLIB/inc/stm32f10x_dbgmcu.h @@ -0,0 +1,117 @@ +/** + ****************************************************************************** + * @file stm32f10x_dbgmcu.h + * @author MCD Application Team + * @version V3.6.2 + * @date 17-September-2021 + * @brief This file contains all the functions prototypes for the DBGMCU + * firmware library. + ****************************************************************************** + * @attention + * + * Copyright (c) 2012 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_DBGMCU_H +#define __STM32F10x_DBGMCU_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DBGMCU + * @{ + */ + +/** @defgroup DBGMCU_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup DBGMCU_Exported_Constants + * @{ + */ + +#define DBGMCU_SLEEP ((uint32_t)0x00000001) +#define DBGMCU_STOP ((uint32_t)0x00000002) +#define DBGMCU_STANDBY ((uint32_t)0x00000004) +#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100) +#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200) +#define DBGMCU_TIM1_STOP ((uint32_t)0x00000400) +#define DBGMCU_TIM2_STOP ((uint32_t)0x00000800) +#define DBGMCU_TIM3_STOP ((uint32_t)0x00001000) +#define DBGMCU_TIM4_STOP ((uint32_t)0x00002000) +#define DBGMCU_CAN1_STOP ((uint32_t)0x00004000) +#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) +#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) +#define DBGMCU_TIM8_STOP ((uint32_t)0x00020000) +#define DBGMCU_TIM5_STOP ((uint32_t)0x00040000) +#define DBGMCU_TIM6_STOP ((uint32_t)0x00080000) +#define DBGMCU_TIM7_STOP ((uint32_t)0x00100000) +#define DBGMCU_CAN2_STOP ((uint32_t)0x00200000) +#define DBGMCU_TIM15_STOP ((uint32_t)0x00400000) +#define DBGMCU_TIM16_STOP ((uint32_t)0x00800000) +#define DBGMCU_TIM17_STOP ((uint32_t)0x01000000) +#define DBGMCU_TIM12_STOP ((uint32_t)0x02000000) +#define DBGMCU_TIM13_STOP ((uint32_t)0x04000000) +#define DBGMCU_TIM14_STOP ((uint32_t)0x08000000) +#define DBGMCU_TIM9_STOP ((uint32_t)0x10000000) +#define DBGMCU_TIM10_STOP ((uint32_t)0x20000000) +#define DBGMCU_TIM11_STOP ((uint32_t)0x40000000) + +#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0x800000F8) == 0x00) && ((PERIPH) != 0x00)) +/** + * @} + */ + +/** @defgroup DBGMCU_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup DBGMCU_Exported_Functions + * @{ + */ + +uint32_t DBGMCU_GetREVID(void); +uint32_t DBGMCU_GetDEVID(void); +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_DBGMCU_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/STM32F10x_FWLIB/inc/stm32f10x_dma.h b/STM32F10x_FWLIB/inc/stm32f10x_dma.h new file mode 100644 index 0000000..f1a8cf9 --- /dev/null +++ b/STM32F10x_FWLIB/inc/stm32f10x_dma.h @@ -0,0 +1,437 @@ +/** + ****************************************************************************** + * @file stm32f10x_dma.h + * @author MCD Application Team + * @version V3.6.2 + * @date 17-September-2021 + * @brief This file contains all the functions prototypes for the DMA firmware + * library. + ****************************************************************************** + * @attention + * + * Copyright (c) 2012 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_DMA_H +#define __STM32F10x_DMA_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +/** @defgroup DMA_Exported_Types + * @{ + */ + +/** + * @brief DMA Init structure definition + */ + +typedef struct +{ + uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */ + + uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */ + + uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination. + This parameter can be a value of @ref DMA_data_transfer_direction */ + + uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel. + The data unit is equal to the configuration set in DMA_PeripheralDataSize + or DMA_MemoryDataSize members depending in the transfer direction. */ + + uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not. + This parameter can be a value of @ref DMA_peripheral_incremented_mode */ + + uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not. + This parameter can be a value of @ref DMA_memory_incremented_mode */ + + uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_peripheral_data_size */ + + uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width. + This parameter can be a value of @ref DMA_memory_data_size */ + + uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx. + This parameter can be a value of @ref DMA_circular_normal_mode. + @note: The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Channel */ + + uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx. + This parameter can be a value of @ref DMA_priority_level */ + + uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer. + This parameter can be a value of @ref DMA_memory_to_memory */ +}DMA_InitTypeDef; + +/** + * @} + */ + +/** @defgroup DMA_Exported_Constants + * @{ + */ + +#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \ + ((PERIPH) == DMA1_Channel2) || \ + ((PERIPH) == DMA1_Channel3) || \ + ((PERIPH) == DMA1_Channel4) || \ + ((PERIPH) == DMA1_Channel5) || \ + ((PERIPH) == DMA1_Channel6) || \ + ((PERIPH) == DMA1_Channel7) || \ + ((PERIPH) == DMA2_Channel1) || \ + ((PERIPH) == DMA2_Channel2) || \ + ((PERIPH) == DMA2_Channel3) || \ + ((PERIPH) == DMA2_Channel4) || \ + ((PERIPH) == DMA2_Channel5)) + +/** @defgroup DMA_data_transfer_direction + * @{ + */ + +#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) +#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) +#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \ + ((DIR) == DMA_DIR_PeripheralSRC)) +/** + * @} + */ + +/** @defgroup DMA_peripheral_incremented_mode + * @{ + */ + +#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) +#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) +#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \ + ((STATE) == DMA_PeripheralInc_Disable)) +/** + * @} + */ + +/** @defgroup DMA_memory_incremented_mode + * @{ + */ + +#define DMA_MemoryInc_Enable ((uint32_t)0x00000080) +#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) +#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \ + ((STATE) == DMA_MemoryInc_Disable)) +/** + * @} + */ + +/** @defgroup DMA_peripheral_data_size + * @{ + */ + +#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) +#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) +#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) +#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \ + ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \ + ((SIZE) == DMA_PeripheralDataSize_Word)) +/** + * @} + */ + +/** @defgroup DMA_memory_data_size + * @{ + */ + +#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) +#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) +#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) +#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \ + ((SIZE) == DMA_MemoryDataSize_HalfWord) || \ + ((SIZE) == DMA_MemoryDataSize_Word)) +/** + * @} + */ + +/** @defgroup DMA_circular_normal_mode + * @{ + */ + +#define DMA_Mode_Circular ((uint32_t)0x00000020) +#define DMA_Mode_Normal ((uint32_t)0x00000000) +#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal)) +/** + * @} + */ + +/** @defgroup DMA_priority_level + * @{ + */ + +#define DMA_Priority_VeryHigh ((uint32_t)0x00003000) +#define DMA_Priority_High ((uint32_t)0x00002000) +#define DMA_Priority_Medium ((uint32_t)0x00001000) +#define DMA_Priority_Low ((uint32_t)0x00000000) +#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \ + ((PRIORITY) == DMA_Priority_High) || \ + ((PRIORITY) == DMA_Priority_Medium) || \ + ((PRIORITY) == DMA_Priority_Low)) +/** + * @} + */ + +/** @defgroup DMA_memory_to_memory + * @{ + */ + +#define DMA_M2M_Enable ((uint32_t)0x00004000) +#define DMA_M2M_Disable ((uint32_t)0x00000000) +#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable)) + +/** + * @} + */ + +/** @defgroup DMA_interrupts_definition + * @{ + */ + +#define DMA_IT_TC ((uint32_t)0x00000002) +#define DMA_IT_HT ((uint32_t)0x00000004) +#define DMA_IT_TE ((uint32_t)0x00000008) +#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00)) + +#define DMA1_IT_GL1 ((uint32_t)0x00000001) +#define DMA1_IT_TC1 ((uint32_t)0x00000002) +#define DMA1_IT_HT1 ((uint32_t)0x00000004) +#define DMA1_IT_TE1 ((uint32_t)0x00000008) +#define DMA1_IT_GL2 ((uint32_t)0x00000010) +#define DMA1_IT_TC2 ((uint32_t)0x00000020) +#define DMA1_IT_HT2 ((uint32_t)0x00000040) +#define DMA1_IT_TE2 ((uint32_t)0x00000080) +#define DMA1_IT_GL3 ((uint32_t)0x00000100) +#define DMA1_IT_TC3 ((uint32_t)0x00000200) +#define DMA1_IT_HT3 ((uint32_t)0x00000400) +#define DMA1_IT_TE3 ((uint32_t)0x00000800) +#define DMA1_IT_GL4 ((uint32_t)0x00001000) +#define DMA1_IT_TC4 ((uint32_t)0x00002000) +#define DMA1_IT_HT4 ((uint32_t)0x00004000) +#define DMA1_IT_TE4 ((uint32_t)0x00008000) +#define DMA1_IT_GL5 ((uint32_t)0x00010000) +#define DMA1_IT_TC5 ((uint32_t)0x00020000) +#define DMA1_IT_HT5 ((uint32_t)0x00040000) +#define DMA1_IT_TE5 ((uint32_t)0x00080000) +#define DMA1_IT_GL6 ((uint32_t)0x00100000) +#define DMA1_IT_TC6 ((uint32_t)0x00200000) +#define DMA1_IT_HT6 ((uint32_t)0x00400000) +#define DMA1_IT_TE6 ((uint32_t)0x00800000) +#define DMA1_IT_GL7 ((uint32_t)0x01000000) +#define DMA1_IT_TC7 ((uint32_t)0x02000000) +#define DMA1_IT_HT7 ((uint32_t)0x04000000) +#define DMA1_IT_TE7 ((uint32_t)0x08000000) + +#define DMA2_IT_GL1 ((uint32_t)0x10000001) +#define DMA2_IT_TC1 ((uint32_t)0x10000002) +#define DMA2_IT_HT1 ((uint32_t)0x10000004) +#define DMA2_IT_TE1 ((uint32_t)0x10000008) +#define DMA2_IT_GL2 ((uint32_t)0x10000010) +#define DMA2_IT_TC2 ((uint32_t)0x10000020) +#define DMA2_IT_HT2 ((uint32_t)0x10000040) +#define DMA2_IT_TE2 ((uint32_t)0x10000080) +#define DMA2_IT_GL3 ((uint32_t)0x10000100) +#define DMA2_IT_TC3 ((uint32_t)0x10000200) +#define DMA2_IT_HT3 ((uint32_t)0x10000400) +#define DMA2_IT_TE3 ((uint32_t)0x10000800) +#define DMA2_IT_GL4 ((uint32_t)0x10001000) +#define DMA2_IT_TC4 ((uint32_t)0x10002000) +#define DMA2_IT_HT4 ((uint32_t)0x10004000) +#define DMA2_IT_TE4 ((uint32_t)0x10008000) +#define DMA2_IT_GL5 ((uint32_t)0x10010000) +#define DMA2_IT_TC5 ((uint32_t)0x10020000) +#define DMA2_IT_HT5 ((uint32_t)0x10040000) +#define DMA2_IT_TE5 ((uint32_t)0x10080000) + +#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00)) + +#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \ + ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \ + ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \ + ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \ + ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \ + ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \ + ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \ + ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \ + ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \ + ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \ + ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \ + ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \ + ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \ + ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \ + ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \ + ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \ + ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \ + ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \ + ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \ + ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \ + ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \ + ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \ + ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \ + ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5)) + +/** + * @} + */ + +/** @defgroup DMA_flags_definition + * @{ + */ +#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) +#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) +#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) +#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) +#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) +#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) +#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) +#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) +#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) +#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) +#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) +#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) +#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) +#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) +#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) +#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) +#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) +#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) +#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) +#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) +#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) +#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) +#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) +#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) +#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) +#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) +#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) +#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) + +#define DMA2_FLAG_GL1 ((uint32_t)0x10000001) +#define DMA2_FLAG_TC1 ((uint32_t)0x10000002) +#define DMA2_FLAG_HT1 ((uint32_t)0x10000004) +#define DMA2_FLAG_TE1 ((uint32_t)0x10000008) +#define DMA2_FLAG_GL2 ((uint32_t)0x10000010) +#define DMA2_FLAG_TC2 ((uint32_t)0x10000020) +#define DMA2_FLAG_HT2 ((uint32_t)0x10000040) +#define DMA2_FLAG_TE2 ((uint32_t)0x10000080) +#define DMA2_FLAG_GL3 ((uint32_t)0x10000100) +#define DMA2_FLAG_TC3 ((uint32_t)0x10000200) +#define DMA2_FLAG_HT3 ((uint32_t)0x10000400) +#define DMA2_FLAG_TE3 ((uint32_t)0x10000800) +#define DMA2_FLAG_GL4 ((uint32_t)0x10001000) +#define DMA2_FLAG_TC4 ((uint32_t)0x10002000) +#define DMA2_FLAG_HT4 ((uint32_t)0x10004000) +#define DMA2_FLAG_TE4 ((uint32_t)0x10008000) +#define DMA2_FLAG_GL5 ((uint32_t)0x10010000) +#define DMA2_FLAG_TC5 ((uint32_t)0x10020000) +#define DMA2_FLAG_HT5 ((uint32_t)0x10040000) +#define DMA2_FLAG_TE5 ((uint32_t)0x10080000) + +#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00)) + +#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \ + ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \ + ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \ + ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \ + ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \ + ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \ + ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \ + ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \ + ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \ + ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \ + ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \ + ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \ + ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \ + ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \ + ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \ + ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \ + ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \ + ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \ + ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \ + ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \ + ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \ + ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \ + ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \ + ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5)) +/** + * @} + */ + +/** @defgroup DMA_Buffer_Size + * @{ + */ + +#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup DMA_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions + * @{ + */ + +void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx); +void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct); +void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); +void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState); +void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); +void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber); +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx); +FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG); +void DMA_ClearFlag(uint32_t DMAy_FLAG); +ITStatus DMA_GetITStatus(uint32_t DMAy_IT); +void DMA_ClearITPendingBit(uint32_t DMAy_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F10x_DMA_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/STM32F10x_FWLIB/inc/stm32f10x_exti.h b/STM32F10x_FWLIB/inc/stm32f10x_exti.h new file mode 100644 index 0000000..fd0f81c --- /dev/null +++ b/STM32F10x_FWLIB/inc/stm32f10x_exti.h @@ -0,0 +1,182 @@ +/** + ****************************************************************************** + * @file stm32f10x_exti.h + * @author MCD Application Team + * @version V3.6.2 + * @date 17-September-2021 + * @brief This file contains all the functions prototypes for the EXTI firmware + * library. + ****************************************************************************** + * @attention + * + * Copyright (c) 2012 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_EXTI_H +#define __STM32F10x_EXTI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup EXTI + * @{ + */ + +/** @defgroup EXTI_Exported_Types + * @{ + */ + +/** + * @brief EXTI mode enumeration + */ + +typedef enum +{ + EXTI_Mode_Interrupt = 0x00, + EXTI_Mode_Event = 0x04 +}EXTIMode_TypeDef; + +#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) + +/** + * @brief EXTI Trigger enumeration + */ + +typedef enum +{ + EXTI_Trigger_Rising = 0x08, + EXTI_Trigger_Falling = 0x0C, + EXTI_Trigger_Rising_Falling = 0x10 +}EXTITrigger_TypeDef; + +#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \ + ((TRIGGER) == EXTI_Trigger_Falling) || \ + ((TRIGGER) == EXTI_Trigger_Rising_Falling)) +/** + * @brief EXTI Init Structure definition + */ + +typedef struct +{ + uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled. + This parameter can be any combination of @ref EXTI_Lines */ + + EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTIMode_TypeDef */ + + EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTITrigger_TypeDef */ + + FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ +}EXTI_InitTypeDef; + +/** + * @} + */ + +/** @defgroup EXTI_Exported_Constants + * @{ + */ + +/** @defgroup EXTI_Lines + * @{ + */ + +#define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */ +#define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */ +#define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */ +#define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */ +#define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */ +#define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */ +#define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */ +#define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */ +#define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */ +#define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */ +#define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */ +#define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */ +#define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */ +#define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */ +#define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */ +#define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */ +#define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */ +#define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */ +#define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS + Wakeup from suspend event */ +#define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ + +#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00)) +#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \ + ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \ + ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \ + ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \ + ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \ + ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \ + ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \ + ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \ + ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \ + ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19)) + + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup EXTI_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup EXTI_Exported_Functions + * @{ + */ + +void EXTI_DeInit(void); +void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); +void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); +void EXTI_ClearFlag(uint32_t EXTI_Line); +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); +void EXTI_ClearITPendingBit(uint32_t EXTI_Line); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_EXTI_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/STM32F10x_FWLIB/inc/stm32f10x_flash.h b/STM32F10x_FWLIB/inc/stm32f10x_flash.h new file mode 100644 index 0000000..6fe1f74 --- /dev/null +++ b/STM32F10x_FWLIB/inc/stm32f10x_flash.h @@ -0,0 +1,424 @@ +/** + ****************************************************************************** + * @file stm32f10x_flash.h + * @author MCD Application Team + * @version V3.6.2 + * @date 17-September-2021 + * @brief This file contains all the functions prototypes for the FLASH + * firmware library. + ****************************************************************************** + * @attention + * + * Copyright (c) 2012 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_FLASH_H +#define __STM32F10x_FLASH_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +/** @defgroup FLASH_Exported_Types + * @{ + */ + +/** + * @brief FLASH Status + */ + +typedef enum +{ + FLASH_BUSY = 1, + FLASH_ERROR_PG, + FLASH_ERROR_WRP, + FLASH_COMPLETE, + FLASH_TIMEOUT +}FLASH_Status; + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Constants + * @{ + */ + +/** @defgroup Flash_Latency + * @{ + */ + +#define FLASH_Latency_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */ +#define FLASH_Latency_1 ((uint32_t)0x00000001) /*!< FLASH One Latency cycle */ +#define FLASH_Latency_2 ((uint32_t)0x00000002) /*!< FLASH Two Latency cycles */ +#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \ + ((LATENCY) == FLASH_Latency_1) || \ + ((LATENCY) == FLASH_Latency_2)) +/** + * @} + */ + +/** @defgroup Half_Cycle_Enable_Disable + * @{ + */ + +#define FLASH_HalfCycleAccess_Enable ((uint32_t)0x00000008) /*!< FLASH Half Cycle Enable */ +#define FLASH_HalfCycleAccess_Disable ((uint32_t)0x00000000) /*!< FLASH Half Cycle Disable */ +#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \ + ((STATE) == FLASH_HalfCycleAccess_Disable)) +/** + * @} + */ + +/** @defgroup Prefetch_Buffer_Enable_Disable + * @{ + */ + +#define FLASH_PrefetchBuffer_Enable ((uint32_t)0x00000010) /*!< FLASH Prefetch Buffer Enable */ +#define FLASH_PrefetchBuffer_Disable ((uint32_t)0x00000000) /*!< FLASH Prefetch Buffer Disable */ +#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \ + ((STATE) == FLASH_PrefetchBuffer_Disable)) +/** + * @} + */ + +/** @defgroup Option_Bytes_Write_Protection + * @{ + */ + +/* Values to be used with STM32 Low and Medium density devices */ +#define FLASH_WRProt_Pages0to3 ((uint32_t)0x00000001) /*!< STM32 Low and Medium density devices: Write protection of page 0 to 3 */ +#define FLASH_WRProt_Pages4to7 ((uint32_t)0x00000002) /*!< STM32 Low and Medium density devices: Write protection of page 4 to 7 */ +#define FLASH_WRProt_Pages8to11 ((uint32_t)0x00000004) /*!< STM32 Low and Medium density devices: Write protection of page 8 to 11 */ +#define FLASH_WRProt_Pages12to15 ((uint32_t)0x00000008) /*!< STM32 Low and Medium density devices: Write protection of page 12 to 15 */ +#define FLASH_WRProt_Pages16to19 ((uint32_t)0x00000010) /*!< STM32 Low and Medium density devices: Write protection of page 16 to 19 */ +#define FLASH_WRProt_Pages20to23 ((uint32_t)0x00000020) /*!< STM32 Low and Medium density devices: Write protection of page 20 to 23 */ +#define FLASH_WRProt_Pages24to27 ((uint32_t)0x00000040) /*!< STM32 Low and Medium density devices: Write protection of page 24 to 27 */ +#define FLASH_WRProt_Pages28to31 ((uint32_t)0x00000080) /*!< STM32 Low and Medium density devices: Write protection of page 28 to 31 */ + +/* Values to be used with STM32 Medium-density devices */ +#define FLASH_WRProt_Pages32to35 ((uint32_t)0x00000100) /*!< STM32 Medium-density devices: Write protection of page 32 to 35 */ +#define FLASH_WRProt_Pages36to39 ((uint32_t)0x00000200) /*!< STM32 Medium-density devices: Write protection of page 36 to 39 */ +#define FLASH_WRProt_Pages40to43 ((uint32_t)0x00000400) /*!< STM32 Medium-density devices: Write protection of page 40 to 43 */ +#define FLASH_WRProt_Pages44to47 ((uint32_t)0x00000800) /*!< STM32 Medium-density devices: Write protection of page 44 to 47 */ +#define FLASH_WRProt_Pages48to51 ((uint32_t)0x00001000) /*!< STM32 Medium-density devices: Write protection of page 48 to 51 */ +#define FLASH_WRProt_Pages52to55 ((uint32_t)0x00002000) /*!< STM32 Medium-density devices: Write protection of page 52 to 55 */ +#define FLASH_WRProt_Pages56to59 ((uint32_t)0x00004000) /*!< STM32 Medium-density devices: Write protection of page 56 to 59 */ +#define FLASH_WRProt_Pages60to63 ((uint32_t)0x00008000) /*!< STM32 Medium-density devices: Write protection of page 60 to 63 */ +#define FLASH_WRProt_Pages64to67 ((uint32_t)0x00010000) /*!< STM32 Medium-density devices: Write protection of page 64 to 67 */ +#define FLASH_WRProt_Pages68to71 ((uint32_t)0x00020000) /*!< STM32 Medium-density devices: Write protection of page 68 to 71 */ +#define FLASH_WRProt_Pages72to75 ((uint32_t)0x00040000) /*!< STM32 Medium-density devices: Write protection of page 72 to 75 */ +#define FLASH_WRProt_Pages76to79 ((uint32_t)0x00080000) /*!< STM32 Medium-density devices: Write protection of page 76 to 79 */ +#define FLASH_WRProt_Pages80to83 ((uint32_t)0x00100000) /*!< STM32 Medium-density devices: Write protection of page 80 to 83 */ +#define FLASH_WRProt_Pages84to87 ((uint32_t)0x00200000) /*!< STM32 Medium-density devices: Write protection of page 84 to 87 */ +#define FLASH_WRProt_Pages88to91 ((uint32_t)0x00400000) /*!< STM32 Medium-density devices: Write protection of page 88 to 91 */ +#define FLASH_WRProt_Pages92to95 ((uint32_t)0x00800000) /*!< STM32 Medium-density devices: Write protection of page 92 to 95 */ +#define FLASH_WRProt_Pages96to99 ((uint32_t)0x01000000) /*!< STM32 Medium-density devices: Write protection of page 96 to 99 */ +#define FLASH_WRProt_Pages100to103 ((uint32_t)0x02000000) /*!< STM32 Medium-density devices: Write protection of page 100 to 103 */ +#define FLASH_WRProt_Pages104to107 ((uint32_t)0x04000000) /*!< STM32 Medium-density devices: Write protection of page 104 to 107 */ +#define FLASH_WRProt_Pages108to111 ((uint32_t)0x08000000) /*!< STM32 Medium-density devices: Write protection of page 108 to 111 */ +#define FLASH_WRProt_Pages112to115 ((uint32_t)0x10000000) /*!< STM32 Medium-density devices: Write protection of page 112 to 115 */ +#define FLASH_WRProt_Pages116to119 ((uint32_t)0x20000000) /*!< STM32 Medium-density devices: Write protection of page 115 to 119 */ +#define FLASH_WRProt_Pages120to123 ((uint32_t)0x40000000) /*!< STM32 Medium-density devices: Write protection of page 120 to 123 */ +#define FLASH_WRProt_Pages124to127 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 124 to 127 */ + +/* Values to be used with STM32 High-density and STM32F10X Connectivity line devices */ +#define FLASH_WRProt_Pages0to1 ((uint32_t)0x00000001) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 0 to 1 */ +#define FLASH_WRProt_Pages2to3 ((uint32_t)0x00000002) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 2 to 3 */ +#define FLASH_WRProt_Pages4to5 ((uint32_t)0x00000004) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 4 to 5 */ +#define FLASH_WRProt_Pages6to7 ((uint32_t)0x00000008) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 6 to 7 */ +#define FLASH_WRProt_Pages8to9 ((uint32_t)0x00000010) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 8 to 9 */ +#define FLASH_WRProt_Pages10to11 ((uint32_t)0x00000020) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 10 to 11 */ +#define FLASH_WRProt_Pages12to13 ((uint32_t)0x00000040) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 12 to 13 */ +#define FLASH_WRProt_Pages14to15 ((uint32_t)0x00000080) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 14 to 15 */ +#define FLASH_WRProt_Pages16to17 ((uint32_t)0x00000100) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 16 to 17 */ +#define FLASH_WRProt_Pages18to19 ((uint32_t)0x00000200) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 18 to 19 */ +#define FLASH_WRProt_Pages20to21 ((uint32_t)0x00000400) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 20 to 21 */ +#define FLASH_WRProt_Pages22to23 ((uint32_t)0x00000800) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 22 to 23 */ +#define FLASH_WRProt_Pages24to25 ((uint32_t)0x00001000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 24 to 25 */ +#define FLASH_WRProt_Pages26to27 ((uint32_t)0x00002000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 26 to 27 */ +#define FLASH_WRProt_Pages28to29 ((uint32_t)0x00004000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 28 to 29 */ +#define FLASH_WRProt_Pages30to31 ((uint32_t)0x00008000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 30 to 31 */ +#define FLASH_WRProt_Pages32to33 ((uint32_t)0x00010000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 32 to 33 */ +#define FLASH_WRProt_Pages34to35 ((uint32_t)0x00020000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 34 to 35 */ +#define FLASH_WRProt_Pages36to37 ((uint32_t)0x00040000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 36 to 37 */ +#define FLASH_WRProt_Pages38to39 ((uint32_t)0x00080000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 38 to 39 */ +#define FLASH_WRProt_Pages40to41 ((uint32_t)0x00100000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 40 to 41 */ +#define FLASH_WRProt_Pages42to43 ((uint32_t)0x00200000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 42 to 43 */ +#define FLASH_WRProt_Pages44to45 ((uint32_t)0x00400000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 44 to 45 */ +#define FLASH_WRProt_Pages46to47 ((uint32_t)0x00800000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 46 to 47 */ +#define FLASH_WRProt_Pages48to49 ((uint32_t)0x01000000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 48 to 49 */ +#define FLASH_WRProt_Pages50to51 ((uint32_t)0x02000000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 50 to 51 */ +#define FLASH_WRProt_Pages52to53 ((uint32_t)0x04000000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 52 to 53 */ +#define FLASH_WRProt_Pages54to55 ((uint32_t)0x08000000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 54 to 55 */ +#define FLASH_WRProt_Pages56to57 ((uint32_t)0x10000000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 56 to 57 */ +#define FLASH_WRProt_Pages58to59 ((uint32_t)0x20000000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 58 to 59 */ +#define FLASH_WRProt_Pages60to61 ((uint32_t)0x40000000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 60 to 61 */ +#define FLASH_WRProt_Pages62to127 ((uint32_t)0x80000000) /*!< STM32 Connectivity line devices: Write protection of page 62 to 127 */ +#define FLASH_WRProt_Pages62to255 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 62 to 255 */ +#define FLASH_WRProt_Pages62to511 ((uint32_t)0x80000000) /*!< STM32 XL-density devices: Write protection of page 62 to 511 */ + +#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */ + +#define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000)) + +#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF)) + +#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806)) + +/** + * @} + */ + +/** @defgroup Option_Bytes_IWatchdog + * @{ + */ + +#define OB_IWDG_SW ((uint16_t)0x0001) /*!< Software IWDG selected */ +#define OB_IWDG_HW ((uint16_t)0x0000) /*!< Hardware IWDG selected */ +#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) + +/** + * @} + */ + +/** @defgroup Option_Bytes_nRST_STOP + * @{ + */ + +#define OB_STOP_NoRST ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */ +#define OB_STOP_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */ +#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) + +/** + * @} + */ + +/** @defgroup Option_Bytes_nRST_STDBY + * @{ + */ + +#define OB_STDBY_NoRST ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */ +#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) + +#ifdef STM32F10X_XL +/** + * @} + */ +/** @defgroup FLASH_Boot + * @{ + */ +#define FLASH_BOOT_Bank1 ((uint16_t)0x0000) /*!< At startup, if boot pins are set in boot from user Flash position + and this parameter is selected the device will boot from Bank1(Default) */ +#define FLASH_BOOT_Bank2 ((uint16_t)0x0001) /*!< At startup, if boot pins are set in boot from user Flash position + and this parameter is selected the device will boot from Bank 2 or Bank 1, + depending on the activation of the bank */ +#define IS_FLASH_BOOT(BOOT) (((BOOT) == FLASH_BOOT_Bank1) || ((BOOT) == FLASH_BOOT_Bank2)) +#endif +/** + * @} + */ +/** @defgroup FLASH_Interrupts + * @{ + */ +#ifdef STM32F10X_XL +#define FLASH_IT_BANK2_ERROR ((uint32_t)0x80000400) /*!< FPEC BANK2 error interrupt source */ +#define FLASH_IT_BANK2_EOP ((uint32_t)0x80001000) /*!< End of FLASH BANK2 Operation Interrupt source */ + +#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */ +#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */ + +#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC BANK1 error interrupt source */ +#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH BANK1 Operation Interrupt source */ +#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0x7FFFEBFF) == 0x00000000) && (((IT) != 0x00000000))) +#else +#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC error interrupt source */ +#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH Operation Interrupt source */ +#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */ +#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */ + +#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000))) +#endif + +/** + * @} + */ + +/** @defgroup FLASH_Flags + * @{ + */ +#ifdef STM32F10X_XL +#define FLASH_FLAG_BANK2_BSY ((uint32_t)0x80000001) /*!< FLASH BANK2 Busy flag */ +#define FLASH_FLAG_BANK2_EOP ((uint32_t)0x80000020) /*!< FLASH BANK2 End of Operation flag */ +#define FLASH_FLAG_BANK2_PGERR ((uint32_t)0x80000004) /*!< FLASH BANK2 Program error flag */ +#define FLASH_FLAG_BANK2_WRPRTERR ((uint32_t)0x80000010) /*!< FLASH BANK2 Write protected error flag */ + +#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/ +#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */ +#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */ +#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */ + +#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */ +#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */ +#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */ +#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ +#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */ + +#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0x7FFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000)) +#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \ + ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \ + ((FLAG) == FLASH_FLAG_OPTERR)|| \ + ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \ + ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \ + ((FLAG) == FLASH_FLAG_BANK2_BSY) || ((FLAG) == FLASH_FLAG_BANK2_EOP) || \ + ((FLAG) == FLASH_FLAG_BANK2_PGERR) || ((FLAG) == FLASH_FLAG_BANK2_WRPRTERR)) +#else +#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */ +#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */ +#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */ +#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ +#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */ + +#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/ +#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */ +#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */ +#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */ + +#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000)) +#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \ + ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \ + ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \ + ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \ + ((FLAG) == FLASH_FLAG_OPTERR)) +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions + * @{ + */ + +/*------------ Functions used for all STM32F10x devices -----*/ +void FLASH_SetLatency(uint32_t FLASH_Latency); +void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess); +void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer); +void FLASH_Unlock(void); +void FLASH_Lock(void); +FLASH_Status FLASH_ErasePage(uint32_t Page_Address); +FLASH_Status FLASH_EraseAllPages(void); +FLASH_Status FLASH_EraseOptionBytes(void); +FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); +FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); +FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data); +FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages); +FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState); +FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY); +uint32_t FLASH_GetUserOptionByte(void); +uint32_t FLASH_GetWriteProtectionOptionByte(void); +FlagStatus FLASH_GetReadOutProtectionStatus(void); +FlagStatus FLASH_GetPrefetchBufferStatus(void); +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); +void FLASH_ClearFlag(uint32_t FLASH_FLAG); +FLASH_Status FLASH_GetStatus(void); +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); + +/*------------ New function used for all STM32F10x devices -----*/ +void FLASH_UnlockBank1(void); +void FLASH_LockBank1(void); +FLASH_Status FLASH_EraseAllBank1Pages(void); +FLASH_Status FLASH_GetBank1Status(void); +FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout); + +#ifdef STM32F10X_XL +/*---- New Functions used only with STM32F10x_XL density devices -----*/ +void FLASH_UnlockBank2(void); +void FLASH_LockBank2(void); +FLASH_Status FLASH_EraseAllBank2Pages(void); +FLASH_Status FLASH_GetBank2Status(void); +FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout); +FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_FLASH_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/STM32F10x_FWLIB/inc/stm32f10x_fsmc.h b/STM32F10x_FWLIB/inc/stm32f10x_fsmc.h new file mode 100644 index 0000000..467bd8e --- /dev/null +++ b/STM32F10x_FWLIB/inc/stm32f10x_fsmc.h @@ -0,0 +1,731 @@ +/** + ****************************************************************************** + * @file stm32f10x_fsmc.h + * @author MCD Application Team + * @version V3.6.2 + * @date 17-September-2021 + * @brief This file contains all the functions prototypes for the FSMC firmware + * library. + ****************************************************************************** + * @attention + * + * Copyright (c) 2012 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_FSMC_H +#define __STM32F10x_FSMC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup FSMC + * @{ + */ + +/** @defgroup FSMC_Exported_Types + * @{ + */ + +/** + * @brief Timing parameters For NOR/SRAM Banks + */ + +typedef struct +{ + uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure + the duration of the address setup time. + This parameter can be a value between 0 and 0xF. + @note: It is not used with synchronous NOR Flash memories. */ + + uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure + the duration of the address hold time. + This parameter can be a value between 0 and 0xF. + @note: It is not used with synchronous NOR Flash memories.*/ + + uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure + the duration of the data setup time. + This parameter can be a value between 0 and 0xFF. + @note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */ + + uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure + the duration of the bus turnaround. + This parameter can be a value between 0 and 0xF. + @note: It is only used for multiplexed NOR Flash memories. */ + + uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles. + This parameter can be a value between 1 and 0xF. + @note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */ + + uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue + to the memory before getting the first data. + The value of this parameter depends on the memory type as shown below: + - It must be set to 0 in case of a CRAM + - It is don't care in asynchronous NOR, SRAM or ROM accesses + - It may assume a value between 0 and 0xF in NOR Flash memories + with synchronous burst mode enable */ + + uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode. + This parameter can be a value of @ref FSMC_Access_Mode */ +}FSMC_NORSRAMTimingInitTypeDef; + +/** + * @brief FSMC NOR/SRAM Init structure definition + */ + +typedef struct +{ + uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used. + This parameter can be a value of @ref FSMC_NORSRAM_Bank */ + + uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are + multiplexed on the databus or not. + This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ + + uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to + the corresponding memory bank. + This parameter can be a value of @ref FSMC_Memory_Type */ + + uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. + This parameter can be a value of @ref FSMC_Data_Width */ + + uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, + valid only with synchronous burst Flash memories. + This parameter can be a value of @ref FSMC_Burst_Access_Mode */ + + uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, + valid only with asynchronous Flash memories. + This parameter can be a value of @ref FSMC_AsynchronousWait */ + + uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing + the Flash memory in burst mode. + This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ + + uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash + memory, valid only when accessing Flash memories in burst mode. + This parameter can be a value of @ref FSMC_Wrap_Mode */ + + uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one + clock cycle before the wait state or during the wait state, + valid only when accessing memories in burst mode. + This parameter can be a value of @ref FSMC_Wait_Timing */ + + uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC. + This parameter can be a value of @ref FSMC_Write_Operation */ + + uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait + signal, valid for Flash memory access in burst mode. + This parameter can be a value of @ref FSMC_Wait_Signal */ + + uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode. + This parameter can be a value of @ref FSMC_Extended_Mode */ + + uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation. + This parameter can be a value of @ref FSMC_Write_Burst */ + + FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/ + + FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/ +}FSMC_NORSRAMInitTypeDef; + +/** + * @brief Timing parameters For FSMC NAND and PCCARD Banks + */ + +typedef struct +{ + uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before + the command assertion for NAND-Flash read or write access + to common/Attribute or I/O memory space (depending on + the memory space timing to be configured). + This parameter can be a value between 0 and 0xFF.*/ + + uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the + command for NAND-Flash read or write access to + common/Attribute or I/O memory space (depending on the + memory space timing to be configured). + This parameter can be a number between 0x00 and 0xFF */ + + uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address + (and data for write access) after the command deassertion + for NAND-Flash read or write access to common/Attribute + or I/O memory space (depending on the memory space timing + to be configured). + This parameter can be a number between 0x00 and 0xFF */ + + uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the + databus is kept in HiZ after the start of a NAND-Flash + write access to common/Attribute or I/O memory space (depending + on the memory space timing to be configured). + This parameter can be a number between 0x00 and 0xFF */ +}FSMC_NAND_PCCARDTimingInitTypeDef; + +/** + * @brief FSMC NAND Init structure definition + */ + +typedef struct +{ + uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used. + This parameter can be a value of @ref FSMC_NAND_Bank */ + + uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank. + This parameter can be any value of @ref FSMC_Wait_feature */ + + uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. + This parameter can be any value of @ref FSMC_Data_Width */ + + uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation. + This parameter can be any value of @ref FSMC_ECC */ + + uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC. + This parameter can be any value of @ref FSMC_ECC_Page_Size */ + + uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between CLE low and RE low. + This parameter can be a value between 0 and 0xFF. */ + + uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between ALE low and RE low. + This parameter can be a number between 0x0 and 0xFF */ + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ +}FSMC_NANDInitTypeDef; + +/** + * @brief FSMC PCCARD Init structure definition + */ + +typedef struct +{ + uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank. + This parameter can be any value of @ref FSMC_Wait_feature */ + + uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between CLE low and RE low. + This parameter can be a value between 0 and 0xFF. */ + + uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between ALE low and RE low. + This parameter can be a number between 0x0 and 0xFF */ + + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */ +}FSMC_PCCARDInitTypeDef; + +/** + * @} + */ + +/** @defgroup FSMC_Exported_Constants + * @{ + */ + +/** @defgroup FSMC_NORSRAM_Bank + * @{ + */ +#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000) +#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002) +#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004) +#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006) +/** + * @} + */ + +/** @defgroup FSMC_NAND_Bank + * @{ + */ +#define FSMC_Bank2_NAND ((uint32_t)0x00000010) +#define FSMC_Bank3_NAND ((uint32_t)0x00000100) +/** + * @} + */ + +/** @defgroup FSMC_PCCARD_Bank + * @{ + */ +#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000) +/** + * @} + */ + +#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \ + ((BANK) == FSMC_Bank1_NORSRAM2) || \ + ((BANK) == FSMC_Bank1_NORSRAM3) || \ + ((BANK) == FSMC_Bank1_NORSRAM4)) + +#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ + ((BANK) == FSMC_Bank3_NAND)) + +#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ + ((BANK) == FSMC_Bank3_NAND) || \ + ((BANK) == FSMC_Bank4_PCCARD)) + +#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ + ((BANK) == FSMC_Bank3_NAND) || \ + ((BANK) == FSMC_Bank4_PCCARD)) + +/** @defgroup NOR_SRAM_Controller + * @{ + */ + +/** @defgroup FSMC_Data_Address_Bus_Multiplexing + * @{ + */ + +#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000) +#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002) +#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \ + ((MUX) == FSMC_DataAddressMux_Enable)) + +/** + * @} + */ + +/** @defgroup FSMC_Memory_Type + * @{ + */ + +#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000) +#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004) +#define FSMC_MemoryType_NOR ((uint32_t)0x00000008) +#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \ + ((MEMORY) == FSMC_MemoryType_PSRAM)|| \ + ((MEMORY) == FSMC_MemoryType_NOR)) + +/** + * @} + */ + +/** @defgroup FSMC_Data_Width + * @{ + */ + +#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000) +#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010) +#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \ + ((WIDTH) == FSMC_MemoryDataWidth_16b)) + +/** + * @} + */ + +/** @defgroup FSMC_Burst_Access_Mode + * @{ + */ + +#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000) +#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100) +#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \ + ((STATE) == FSMC_BurstAccessMode_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_AsynchronousWait + * @{ + */ +#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000) +#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000) +#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \ + ((STATE) == FSMC_AsynchronousWait_Enable)) + +/** + * @} + */ + +/** @defgroup FSMC_Wait_Signal_Polarity + * @{ + */ + +#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000) +#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200) +#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \ + ((POLARITY) == FSMC_WaitSignalPolarity_High)) + +/** + * @} + */ + +/** @defgroup FSMC_Wrap_Mode + * @{ + */ + +#define FSMC_WrapMode_Disable ((uint32_t)0x00000000) +#define FSMC_WrapMode_Enable ((uint32_t)0x00000400) +#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \ + ((MODE) == FSMC_WrapMode_Enable)) + +/** + * @} + */ + +/** @defgroup FSMC_Wait_Timing + * @{ + */ + +#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000) +#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) +#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \ + ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState)) + +/** + * @} + */ + +/** @defgroup FSMC_Write_Operation + * @{ + */ + +#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000) +#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000) +#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \ + ((OPERATION) == FSMC_WriteOperation_Enable)) + +/** + * @} + */ + +/** @defgroup FSMC_Wait_Signal + * @{ + */ + +#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000) +#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000) +#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \ + ((SIGNAL) == FSMC_WaitSignal_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_Extended_Mode + * @{ + */ + +#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000) +#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000) + +#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \ + ((MODE) == FSMC_ExtendedMode_Enable)) + +/** + * @} + */ + +/** @defgroup FSMC_Write_Burst + * @{ + */ + +#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000) +#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000) +#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \ + ((BURST) == FSMC_WriteBurst_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_Address_Setup_Time + * @{ + */ + +#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF) + +/** + * @} + */ + +/** @defgroup FSMC_Address_Hold_Time + * @{ + */ + +#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF) + +/** + * @} + */ + +/** @defgroup FSMC_Data_Setup_Time + * @{ + */ + +#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF)) + +/** + * @} + */ + +/** @defgroup FSMC_Bus_Turn_around_Duration + * @{ + */ + +#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF) + +/** + * @} + */ + +/** @defgroup FSMC_CLK_Division + * @{ + */ + +#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF) + +/** + * @} + */ + +/** @defgroup FSMC_Data_Latency + * @{ + */ + +#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF) + +/** + * @} + */ + +/** @defgroup FSMC_Access_Mode + * @{ + */ + +#define FSMC_AccessMode_A ((uint32_t)0x00000000) +#define FSMC_AccessMode_B ((uint32_t)0x10000000) +#define FSMC_AccessMode_C ((uint32_t)0x20000000) +#define FSMC_AccessMode_D ((uint32_t)0x30000000) +#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \ + ((MODE) == FSMC_AccessMode_B) || \ + ((MODE) == FSMC_AccessMode_C) || \ + ((MODE) == FSMC_AccessMode_D)) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup NAND_PCCARD_Controller + * @{ + */ + +/** @defgroup FSMC_Wait_feature + * @{ + */ + +#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000) +#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002) +#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \ + ((FEATURE) == FSMC_Waitfeature_Enable)) + +/** + * @} + */ + + +/** @defgroup FSMC_ECC + * @{ + */ + +#define FSMC_ECC_Disable ((uint32_t)0x00000000) +#define FSMC_ECC_Enable ((uint32_t)0x00000040) +#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \ + ((STATE) == FSMC_ECC_Enable)) + +/** + * @} + */ + +/** @defgroup FSMC_ECC_Page_Size + * @{ + */ + +#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000) +#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000) +#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000) +#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000) +#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000) +#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000) +#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_512Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_8192Bytes)) + +/** + * @} + */ + +/** @defgroup FSMC_TCLR_Setup_Time + * @{ + */ + +#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_TAR_Setup_Time + * @{ + */ + +#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_Setup_Time + * @{ + */ + +#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_Wait_Setup_Time + * @{ + */ + +#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_Hold_Setup_Time + * @{ + */ + +#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_HiZ_Setup_Time + * @{ + */ + +#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_Interrupt_sources + * @{ + */ + +#define FSMC_IT_RisingEdge ((uint32_t)0x00000008) +#define FSMC_IT_Level ((uint32_t)0x00000010) +#define FSMC_IT_FallingEdge ((uint32_t)0x00000020) +#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000)) +#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \ + ((IT) == FSMC_IT_Level) || \ + ((IT) == FSMC_IT_FallingEdge)) +/** + * @} + */ + +/** @defgroup FSMC_Flags + * @{ + */ + +#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001) +#define FSMC_FLAG_Level ((uint32_t)0x00000002) +#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004) +#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040) +#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \ + ((FLAG) == FSMC_FLAG_Level) || \ + ((FLAG) == FSMC_FLAG_FallingEdge) || \ + ((FLAG) == FSMC_FLAG_FEMPT)) + +#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000)) + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FSMC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup FSMC_Exported_Functions + * @{ + */ + +void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank); +void FSMC_NANDDeInit(uint32_t FSMC_Bank); +void FSMC_PCCARDDeInit(void); +void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); +void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); +void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); +void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); +void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); +void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); +void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState); +void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState); +void FSMC_PCCARDCmd(FunctionalState NewState); +void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState); +uint32_t FSMC_GetECC(uint32_t FSMC_Bank); +void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState); +FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); +void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); +ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT); +void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F10x_FSMC_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/STM32F10x_FWLIB/inc/stm32f10x_gpio.h b/STM32F10x_FWLIB/inc/stm32f10x_gpio.h new file mode 100644 index 0000000..8911e6b --- /dev/null +++ b/STM32F10x_FWLIB/inc/stm32f10x_gpio.h @@ -0,0 +1,383 @@ +/** + ****************************************************************************** + * @file stm32f10x_gpio.h + * @author MCD Application Team + * @version V3.6.2 + * @date 17-September-2021 + * @brief This file contains all the functions prototypes for the GPIO + * firmware library. + ****************************************************************************** + * @attention + * + * Copyright (c) 2012 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_GPIO_H +#define __STM32F10x_GPIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + +/** @defgroup GPIO_Exported_Types + * @{ + */ + +#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \ + ((PERIPH) == GPIOB) || \ + ((PERIPH) == GPIOC) || \ + ((PERIPH) == GPIOD) || \ + ((PERIPH) == GPIOE) || \ + ((PERIPH) == GPIOF) || \ + ((PERIPH) == GPIOG)) + +/** + * @brief Output Maximum frequency selection + */ + +typedef enum +{ + GPIO_Speed_10MHz = 1, + GPIO_Speed_2MHz, + GPIO_Speed_50MHz +}GPIOSpeed_TypeDef; +#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || \ + ((SPEED) == GPIO_Speed_50MHz)) + +/** + * @brief Configuration Mode enumeration + */ + +typedef enum +{ GPIO_Mode_AIN = 0x0, + GPIO_Mode_IN_FLOATING = 0x04, + GPIO_Mode_IPD = 0x28, + GPIO_Mode_IPU = 0x48, + GPIO_Mode_Out_OD = 0x14, + GPIO_Mode_Out_PP = 0x10, + GPIO_Mode_AF_OD = 0x1C, + GPIO_Mode_AF_PP = 0x18 +}GPIOMode_TypeDef; + +#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || \ + ((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || \ + ((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || \ + ((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP)) + +/** + * @brief GPIO Init structure definition + */ + +typedef struct +{ + uint16_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins_define */ + + GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIOSpeed_TypeDef */ + + GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIOMode_TypeDef */ +}GPIO_InitTypeDef; + + +/** + * @brief Bit_SET and Bit_RESET enumeration + */ + +typedef enum +{ Bit_RESET = 0, + Bit_SET +}BitAction; + +#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET)) + +/** + * @} + */ + +/** @defgroup GPIO_Exported_Constants + * @{ + */ + +/** @defgroup GPIO_pins_define + * @{ + */ + +#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */ +#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */ +#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */ +#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */ +#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */ +#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */ +#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */ +#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */ +#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */ +#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */ +#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */ +#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */ +#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */ +#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */ +#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */ +#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */ +#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */ + +#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00)) + +#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \ + ((PIN) == GPIO_Pin_1) || \ + ((PIN) == GPIO_Pin_2) || \ + ((PIN) == GPIO_Pin_3) || \ + ((PIN) == GPIO_Pin_4) || \ + ((PIN) == GPIO_Pin_5) || \ + ((PIN) == GPIO_Pin_6) || \ + ((PIN) == GPIO_Pin_7) || \ + ((PIN) == GPIO_Pin_8) || \ + ((PIN) == GPIO_Pin_9) || \ + ((PIN) == GPIO_Pin_10) || \ + ((PIN) == GPIO_Pin_11) || \ + ((PIN) == GPIO_Pin_12) || \ + ((PIN) == GPIO_Pin_13) || \ + ((PIN) == GPIO_Pin_14) || \ + ((PIN) == GPIO_Pin_15)) + +/** + * @} + */ + +/** @defgroup GPIO_Remap_define + * @{ + */ + +#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /*!< SPI1 Alternate Function mapping */ +#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /*!< I2C1 Alternate Function mapping */ +#define GPIO_Remap_USART1 ((uint32_t)0x00000004) /*!< USART1 Alternate Function mapping */ +#define GPIO_Remap_USART2 ((uint32_t)0x00000008) /*!< USART2 Alternate Function mapping */ +#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /*!< USART3 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /*!< USART3 Full Alternate Function mapping */ +#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /*!< TIM1 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /*!< TIM1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /*!< TIM2 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /*!< TIM2 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /*!< TIM2 Full Alternate Function mapping */ +#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /*!< TIM3 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /*!< TIM3 Full Alternate Function mapping */ +#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /*!< TIM4 Alternate Function mapping */ +#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /*!< CAN1 Alternate Function mapping */ +#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /*!< CAN1 Alternate Function mapping */ +#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /*!< PD01 Alternate Function mapping */ +#define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /*!< LSI connected to TIM5 Channel4 input capture for calibration */ +#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /*!< ADC1 External Trigger Injected Conversion remapping */ +#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /*!< ADC1 External Trigger Regular Conversion remapping */ +#define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /*!< ADC2 External Trigger Injected Conversion remapping */ +#define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /*!< ADC2 External Trigger Regular Conversion remapping */ +#define GPIO_Remap_ETH ((uint32_t)0x00200020) /*!< Ethernet remapping (only for Connectivity line devices) */ +#define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /*!< CAN2 remapping (only for Connectivity line devices) */ +#define GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100) /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */ +#define GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200) /*!< JTAG-DP Disabled and SW-DP Enabled */ +#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */ +#define GPIO_Remap_SPI3 ((uint32_t)0x00201100) /*!< SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */ +#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /*!< Ethernet PTP output or USB OTG SOF (Start of Frame) connected + to TIM2 Internal Trigger 1 for calibration + (only for Connectivity line devices) */ +#define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /*!< Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */ + +#define GPIO_Remap_TIM15 ((uint32_t)0x80000001) /*!< TIM15 Alternate Function mapping (only for Value line devices) */ +#define GPIO_Remap_TIM16 ((uint32_t)0x80000002) /*!< TIM16 Alternate Function mapping (only for Value line devices) */ +#define GPIO_Remap_TIM17 ((uint32_t)0x80000004) /*!< TIM17 Alternate Function mapping (only for Value line devices) */ +#define GPIO_Remap_CEC ((uint32_t)0x80000008) /*!< CEC Alternate Function mapping (only for Value line devices) */ +#define GPIO_Remap_TIM1_DMA ((uint32_t)0x80000010) /*!< TIM1 DMA requests mapping (only for Value line devices) */ + +#define GPIO_Remap_TIM9 ((uint32_t)0x80000020) /*!< TIM9 Alternate Function mapping (only for XL-density devices) */ +#define GPIO_Remap_TIM10 ((uint32_t)0x80000040) /*!< TIM10 Alternate Function mapping (only for XL-density devices) */ +#define GPIO_Remap_TIM11 ((uint32_t)0x80000080) /*!< TIM11 Alternate Function mapping (only for XL-density devices) */ +#define GPIO_Remap_TIM13 ((uint32_t)0x80000100) /*!< TIM13 Alternate Function mapping (only for High density Value line and XL-density devices) */ +#define GPIO_Remap_TIM14 ((uint32_t)0x80000200) /*!< TIM14 Alternate Function mapping (only for High density Value line and XL-density devices) */ +#define GPIO_Remap_FSMC_NADV ((uint32_t)0x80000400) /*!< FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices) */ + +#define GPIO_Remap_TIM67_DAC_DMA ((uint32_t)0x80000800) /*!< TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices) */ +#define GPIO_Remap_TIM12 ((uint32_t)0x80001000) /*!< TIM12 Alternate Function mapping (only for High density Value line devices) */ +#define GPIO_Remap_MISC ((uint32_t)0x80002000) /*!< Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping, + only for High density Value line devices) */ + +#define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \ + ((REMAP) == GPIO_Remap_USART1) || ((REMAP) == GPIO_Remap_USART2) || \ + ((REMAP) == GPIO_PartialRemap_USART3) || ((REMAP) == GPIO_FullRemap_USART3) || \ + ((REMAP) == GPIO_PartialRemap_TIM1) || ((REMAP) == GPIO_FullRemap_TIM1) || \ + ((REMAP) == GPIO_PartialRemap1_TIM2) || ((REMAP) == GPIO_PartialRemap2_TIM2) || \ + ((REMAP) == GPIO_FullRemap_TIM2) || ((REMAP) == GPIO_PartialRemap_TIM3) || \ + ((REMAP) == GPIO_FullRemap_TIM3) || ((REMAP) == GPIO_Remap_TIM4) || \ + ((REMAP) == GPIO_Remap1_CAN1) || ((REMAP) == GPIO_Remap2_CAN1) || \ + ((REMAP) == GPIO_Remap_PD01) || ((REMAP) == GPIO_Remap_TIM5CH4_LSI) || \ + ((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || \ + ((REMAP) == GPIO_Remap_ADC2_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC2_ETRGREG) || \ + ((REMAP) == GPIO_Remap_ETH) ||((REMAP) == GPIO_Remap_CAN2) || \ + ((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable) || \ + ((REMAP) == GPIO_Remap_SWJ_Disable)|| ((REMAP) == GPIO_Remap_SPI3) || \ + ((REMAP) == GPIO_Remap_TIM2ITR1_PTP_SOF) || ((REMAP) == GPIO_Remap_PTP_PPS) || \ + ((REMAP) == GPIO_Remap_TIM15) || ((REMAP) == GPIO_Remap_TIM16) || \ + ((REMAP) == GPIO_Remap_TIM17) || ((REMAP) == GPIO_Remap_CEC) || \ + ((REMAP) == GPIO_Remap_TIM1_DMA) || ((REMAP) == GPIO_Remap_TIM9) || \ + ((REMAP) == GPIO_Remap_TIM10) || ((REMAP) == GPIO_Remap_TIM11) || \ + ((REMAP) == GPIO_Remap_TIM13) || ((REMAP) == GPIO_Remap_TIM14) || \ + ((REMAP) == GPIO_Remap_FSMC_NADV) || ((REMAP) == GPIO_Remap_TIM67_DAC_DMA) || \ + ((REMAP) == GPIO_Remap_TIM12) || ((REMAP) == GPIO_Remap_MISC)) + +/** + * @} + */ + +/** @defgroup GPIO_Port_Sources + * @{ + */ + +#define GPIO_PortSourceGPIOA ((uint8_t)0x00) +#define GPIO_PortSourceGPIOB ((uint8_t)0x01) +#define GPIO_PortSourceGPIOC ((uint8_t)0x02) +#define GPIO_PortSourceGPIOD ((uint8_t)0x03) +#define GPIO_PortSourceGPIOE ((uint8_t)0x04) +#define GPIO_PortSourceGPIOF ((uint8_t)0x05) +#define GPIO_PortSourceGPIOG ((uint8_t)0x06) +#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOE)) + +#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOE) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOF) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOG)) + +/** + * @} + */ + +/** @defgroup GPIO_Pin_sources + * @{ + */ + +#define GPIO_PinSource0 ((uint8_t)0x00) +#define GPIO_PinSource1 ((uint8_t)0x01) +#define GPIO_PinSource2 ((uint8_t)0x02) +#define GPIO_PinSource3 ((uint8_t)0x03) +#define GPIO_PinSource4 ((uint8_t)0x04) +#define GPIO_PinSource5 ((uint8_t)0x05) +#define GPIO_PinSource6 ((uint8_t)0x06) +#define GPIO_PinSource7 ((uint8_t)0x07) +#define GPIO_PinSource8 ((uint8_t)0x08) +#define GPIO_PinSource9 ((uint8_t)0x09) +#define GPIO_PinSource10 ((uint8_t)0x0A) +#define GPIO_PinSource11 ((uint8_t)0x0B) +#define GPIO_PinSource12 ((uint8_t)0x0C) +#define GPIO_PinSource13 ((uint8_t)0x0D) +#define GPIO_PinSource14 ((uint8_t)0x0E) +#define GPIO_PinSource15 ((uint8_t)0x0F) + +#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \ + ((PINSOURCE) == GPIO_PinSource1) || \ + ((PINSOURCE) == GPIO_PinSource2) || \ + ((PINSOURCE) == GPIO_PinSource3) || \ + ((PINSOURCE) == GPIO_PinSource4) || \ + ((PINSOURCE) == GPIO_PinSource5) || \ + ((PINSOURCE) == GPIO_PinSource6) || \ + ((PINSOURCE) == GPIO_PinSource7) || \ + ((PINSOURCE) == GPIO_PinSource8) || \ + ((PINSOURCE) == GPIO_PinSource9) || \ + ((PINSOURCE) == GPIO_PinSource10) || \ + ((PINSOURCE) == GPIO_PinSource11) || \ + ((PINSOURCE) == GPIO_PinSource12) || \ + ((PINSOURCE) == GPIO_PinSource13) || \ + ((PINSOURCE) == GPIO_PinSource14) || \ + ((PINSOURCE) == GPIO_PinSource15)) + +/** + * @} + */ + +/** @defgroup Ethernet_Media_Interface + * @{ + */ +#define GPIO_ETH_MediaInterface_MII ((u32)0x00000000) +#define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001) + +#define IS_GPIO_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == GPIO_ETH_MediaInterface_MII) || \ + ((INTERFACE) == GPIO_ETH_MediaInterface_RMII)) + +/** + * @} + */ +/** + * @} + */ + +/** @defgroup GPIO_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup GPIO_Exported_Functions + * @{ + */ + +void GPIO_DeInit(GPIO_TypeDef* GPIOx); +void GPIO_AFIODeInit(void); +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx); +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); +void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); +void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); +void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); +void GPIO_EventOutputCmd(FunctionalState NewState); +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState); +void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); +void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_GPIO_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/STM32F10x_FWLIB/inc/stm32f10x_i2c.h b/STM32F10x_FWLIB/inc/stm32f10x_i2c.h new file mode 100644 index 0000000..c661002 --- /dev/null +++ b/STM32F10x_FWLIB/inc/stm32f10x_i2c.h @@ -0,0 +1,682 @@ +/** + ****************************************************************************** + * @file stm32f10x_i2c.h + * @author MCD Application Team + * @version V3.6.2 + * @date 17-September-2021 + * @brief This file contains all the functions prototypes for the I2C firmware + * library. + ****************************************************************************** + * @attention + * + * Copyright (c) 2012 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_I2C_H +#define __STM32F10x_I2C_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/** @defgroup I2C_Exported_Types + * @{ + */ + +/** + * @brief I2C Init structure definition + */ + +typedef struct +{ + uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency. + This parameter must be set to a value lower than 400kHz */ + + uint16_t I2C_Mode; /*!< Specifies the I2C mode. + This parameter can be a value of @ref I2C_mode */ + + uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle. + This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ + + uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement. + This parameter can be a value of @ref I2C_acknowledgement */ + + uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged. + This parameter can be a value of @ref I2C_acknowledged_address */ +}I2C_InitTypeDef; + +/** + * @} + */ + + +/** @defgroup I2C_Exported_Constants + * @{ + */ + +#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \ + ((PERIPH) == I2C2)) +/** @defgroup I2C_mode + * @{ + */ + +#define I2C_Mode_I2C ((uint16_t)0x0000) +#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) +#define I2C_Mode_SMBusHost ((uint16_t)0x000A) +#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \ + ((MODE) == I2C_Mode_SMBusDevice) || \ + ((MODE) == I2C_Mode_SMBusHost)) +/** + * @} + */ + +/** @defgroup I2C_duty_cycle_in_fast_mode + * @{ + */ + +#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */ +#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */ +#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \ + ((CYCLE) == I2C_DutyCycle_2)) +/** + * @} + */ + +/** @defgroup I2C_acknowledgement + * @{ + */ + +#define I2C_Ack_Enable ((uint16_t)0x0400) +#define I2C_Ack_Disable ((uint16_t)0x0000) +#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \ + ((STATE) == I2C_Ack_Disable)) +/** + * @} + */ + +/** @defgroup I2C_transfer_direction + * @{ + */ + +#define I2C_Direction_Transmitter ((uint8_t)0x00) +#define I2C_Direction_Receiver ((uint8_t)0x01) +#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \ + ((DIRECTION) == I2C_Direction_Receiver)) +/** + * @} + */ + +/** @defgroup I2C_acknowledged_address + * @{ + */ + +#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) +#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) +#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \ + ((ADDRESS) == I2C_AcknowledgedAddress_10bit)) +/** + * @} + */ + +/** @defgroup I2C_registers + * @{ + */ + +#define I2C_Register_CR1 ((uint8_t)0x00) +#define I2C_Register_CR2 ((uint8_t)0x04) +#define I2C_Register_OAR1 ((uint8_t)0x08) +#define I2C_Register_OAR2 ((uint8_t)0x0C) +#define I2C_Register_DR ((uint8_t)0x10) +#define I2C_Register_SR1 ((uint8_t)0x14) +#define I2C_Register_SR2 ((uint8_t)0x18) +#define I2C_Register_CCR ((uint8_t)0x1C) +#define I2C_Register_TRISE ((uint8_t)0x20) +#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \ + ((REGISTER) == I2C_Register_CR2) || \ + ((REGISTER) == I2C_Register_OAR1) || \ + ((REGISTER) == I2C_Register_OAR2) || \ + ((REGISTER) == I2C_Register_DR) || \ + ((REGISTER) == I2C_Register_SR1) || \ + ((REGISTER) == I2C_Register_SR2) || \ + ((REGISTER) == I2C_Register_CCR) || \ + ((REGISTER) == I2C_Register_TRISE)) +/** + * @} + */ + +/** @defgroup I2C_SMBus_alert_pin_level + * @{ + */ + +#define I2C_SMBusAlert_Low ((uint16_t)0x2000) +#define I2C_SMBusAlert_High ((uint16_t)0xDFFF) +#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \ + ((ALERT) == I2C_SMBusAlert_High)) +/** + * @} + */ + +/** @defgroup I2C_PEC_position + * @{ + */ + +#define I2C_PECPosition_Next ((uint16_t)0x0800) +#define I2C_PECPosition_Current ((uint16_t)0xF7FF) +#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \ + ((POSITION) == I2C_PECPosition_Current)) +/** + * @} + */ + +/** @defgroup I2C_NCAK_position + * @{ + */ + +#define I2C_NACKPosition_Next ((uint16_t)0x0800) +#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) +#define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \ + ((POSITION) == I2C_NACKPosition_Current)) +/** + * @} + */ + +/** @defgroup I2C_interrupts_definition + * @{ + */ + +#define I2C_IT_BUF ((uint16_t)0x0400) +#define I2C_IT_EVT ((uint16_t)0x0200) +#define I2C_IT_ERR ((uint16_t)0x0100) +#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00)) +/** + * @} + */ + +/** @defgroup I2C_interrupts_definition + * @{ + */ + +#define I2C_IT_SMBALERT ((uint32_t)0x01008000) +#define I2C_IT_TIMEOUT ((uint32_t)0x01004000) +#define I2C_IT_PECERR ((uint32_t)0x01001000) +#define I2C_IT_OVR ((uint32_t)0x01000800) +#define I2C_IT_AF ((uint32_t)0x01000400) +#define I2C_IT_ARLO ((uint32_t)0x01000200) +#define I2C_IT_BERR ((uint32_t)0x01000100) +#define I2C_IT_TXE ((uint32_t)0x06000080) +#define I2C_IT_RXNE ((uint32_t)0x06000040) +#define I2C_IT_STOPF ((uint32_t)0x02000010) +#define I2C_IT_ADD10 ((uint32_t)0x02000008) +#define I2C_IT_BTF ((uint32_t)0x02000004) +#define I2C_IT_ADDR ((uint32_t)0x02000002) +#define I2C_IT_SB ((uint32_t)0x02000001) + +#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00)) + +#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \ + ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \ + ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \ + ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \ + ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \ + ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \ + ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB)) +/** + * @} + */ + +/** @defgroup I2C_flags_definition + * @{ + */ + +/** + * @brief SR2 register flags + */ + +#define I2C_FLAG_DUALF ((uint32_t)0x00800000) +#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) +#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) +#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) +#define I2C_FLAG_TRA ((uint32_t)0x00040000) +#define I2C_FLAG_BUSY ((uint32_t)0x00020000) +#define I2C_FLAG_MSL ((uint32_t)0x00010000) + +/** + * @brief SR1 register flags + */ + +#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) +#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) +#define I2C_FLAG_PECERR ((uint32_t)0x10001000) +#define I2C_FLAG_OVR ((uint32_t)0x10000800) +#define I2C_FLAG_AF ((uint32_t)0x10000400) +#define I2C_FLAG_ARLO ((uint32_t)0x10000200) +#define I2C_FLAG_BERR ((uint32_t)0x10000100) +#define I2C_FLAG_TXE ((uint32_t)0x10000080) +#define I2C_FLAG_RXNE ((uint32_t)0x10000040) +#define I2C_FLAG_STOPF ((uint32_t)0x10000010) +#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) +#define I2C_FLAG_BTF ((uint32_t)0x10000004) +#define I2C_FLAG_ADDR ((uint32_t)0x10000002) +#define I2C_FLAG_SB ((uint32_t)0x10000001) + +#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00)) + +#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \ + ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \ + ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \ + ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \ + ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \ + ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \ + ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \ + ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \ + ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \ + ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \ + ((FLAG) == I2C_FLAG_SB)) +/** + * @} + */ + +/** @defgroup I2C_Events + * @{ + */ + +/*======================================== + + I2C Master Events (Events grouped in order of communication) + ==========================================*/ +/** + * @brief Communication start + * + * After sending the START condition (I2C_GenerateSTART() function) the master + * has to wait for this event. It means that the Start condition has been correctly + * released on the I2C bus (the bus is free, no other devices is communicating). + * + */ +/* --EV5 */ +#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ + +/** + * @brief Address Acknowledge + * + * After checking on EV5 (start condition correctly released on the bus), the + * master sends the address of the slave(s) with which it will communicate + * (I2C_Send7bitAddress() function, it also determines the direction of the communication: + * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges + * his address. If an acknowledge is sent on the bus, one of the following events will + * be set: + * + * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED + * event is set. + * + * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED + * is set + * + * 3) In case of 10-Bit addressing mode, the master (just after generating the START + * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() + * function). Then master should wait on EV9. It means that the 10-bit addressing + * header has been correctly sent on the bus. Then master should send the second part of + * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master + * should wait for event EV6. + * + */ + +/* --EV6 */ +#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ +#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ +/* --EV9 */ +#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ + +/** + * @brief Communication events + * + * If a communication is established (START condition generated and slave address + * acknowledged) then the master has to check on one of the following events for + * communication procedures: + * + * 1) Master Receiver mode: The master has to wait on the event EV7 then to read + * the data received from the slave (I2C_ReceiveData() function). + * + * 2) Master Transmitter mode: The master has to send data (I2C_SendData() + * function) then to wait on event EV8 or EV8_2. + * These two events are similar: + * - EV8 means that the data has been written in the data register and is + * being shifted out. + * - EV8_2 means that the data has been physically shifted out and output + * on the bus. + * In most cases, using EV8 is sufficient for the application. + * Using EV8_2 leads to a slower communication but ensure more reliable test. + * EV8_2 is also more suitable than EV8 for testing on the last data transmission + * (before Stop condition generation). + * + * @note In case the user software does not guarantee that this event EV7 is + * managed before the current byte end of transfer, then user may check on EV7 + * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)). + * In this case the communication may be slower. + * + */ + +/* Master RECEIVER mode -----------------------------*/ +/* --EV7 */ +#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ + +/* Master TRANSMITTER mode --------------------------*/ +/* --EV8 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ +/* --EV8_2 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ + + +/*======================================== + + I2C Slave Events (Events grouped in order of communication) + ==========================================*/ + +/** + * @brief Communication start events + * + * Wait on one of these events at the start of the communication. It means that + * the I2C peripheral detected a Start condition on the bus (generated by master + * device) followed by the peripheral address. The peripheral generates an ACK + * condition on the bus (if the acknowledge feature is enabled through function + * I2C_AcknowledgeConfig()) and the events listed above are set : + * + * 1) In normal case (only one address managed by the slave), when the address + * sent by the master matches the own address of the peripheral (configured by + * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set + * (where XXX could be TRANSMITTER or RECEIVER). + * + * 2) In case the address sent by the master matches the second address of the + * peripheral (configured by the function I2C_OwnAddress2Config() and enabled + * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED + * (where XXX could be TRANSMITTER or RECEIVER) are set. + * + * 3) In case the address sent by the master is General Call (address 0x00) and + * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) + * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. + * + */ + +/* --EV1 (all the events below are variants of EV1) */ +/* 1) Case of One Single Address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ + +/* 2) Case of Dual address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ + +/* 3) Case of General Call enabled for the slave */ +#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ + +/** + * @brief Communication events + * + * Wait on one of these events when EV1 has already been checked and: + * + * - Slave RECEIVER mode: + * - EV2: When the application is expecting a data byte to be received. + * - EV4: When the application is expecting the end of the communication: master + * sends a stop condition and data transmission is stopped. + * + * - Slave Transmitter mode: + * - EV3: When a byte has been transmitted by the slave and the application is expecting + * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and + * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be + * used when the user software doesn't guarantee the EV3 is managed before the + * current byte end of transfer. + * - EV3_2: When the master sends a NACK in order to tell slave that data transmission + * shall end (before sending the STOP condition). In this case slave has to stop sending + * data bytes and expect a Stop condition on the bus. + * + * @note In case the user software does not guarantee that the event EV2 is + * managed before the current byte end of transfer, then user may check on EV2 + * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)). + * In this case the communication may be slower. + * + */ + +/* Slave RECEIVER mode --------------------------*/ +/* --EV2 */ +#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ +/* --EV4 */ +#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ + +/* Slave TRANSMITTER mode -----------------------*/ +/* --EV3 */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ +/* --EV3_2 */ +#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ + +/*=========================== End of Events Description ==========================================*/ + +#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \ + ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \ + ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \ + ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \ + ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \ + ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \ + ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \ + ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \ + ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \ + ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \ + ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \ + ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \ + ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \ + ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \ + ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE)) +/** + * @} + */ + +/** @defgroup I2C_own_address1 + * @{ + */ + +#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF) +/** + * @} + */ + +/** @defgroup I2C_clock_speed + * @{ + */ + +#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000)) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup I2C_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions + * @{ + */ + +void I2C_DeInit(I2C_TypeDef* I2Cx); +void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); +void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address); +void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState); +void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data); +uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx); +void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction); +uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register); +void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition); +void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert); +void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition); +void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState); +uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx); +void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle); + +/** + * @brief + **************************************************************************************** + * + * I2C State Monitoring Functions + * + **************************************************************************************** + * This I2C driver provides three different ways for I2C state monitoring + * depending on the application requirements and constraints: + * + * + * 1) Basic state monitoring: + * Using I2C_CheckEvent() function: + * It compares the status registers (SR1 and SR2) content to a given event + * (can be the combination of one or more flags). + * It returns SUCCESS if the current status includes the given flags + * and returns ERROR if one or more flags are missing in the current status. + * - When to use: + * - This function is suitable for most applications as well as for startup + * activity since the events are fully described in the product reference manual + * (RM0008). + * - It is also suitable for users who need to define their own events. + * - Limitations: + * - If an error occurs (ie. error flags are set besides to the monitored flags), + * the I2C_CheckEvent() function may return SUCCESS despite the communication + * hold or corrupted real state. + * In this case, it is advised to use error interrupts to monitor the error + * events and handle them in the interrupt IRQ handler. + * + * @note + * For error management, it is advised to use the following functions: + * - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). + * - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. + * Where x is the peripheral instance (I2C1, I2C2 ...) + * - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler() + * in order to determine which error occurred. + * - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() + * and/or I2C_GenerateStop() in order to clear the error flag and source, + * and return to correct communication status. + * + * + * 2) Advanced state monitoring: + * Using the function I2C_GetLastEvent() which returns the image of both status + * registers in a single word (uint32_t) (Status Register 2 value is shifted left + * by 16 bits and concatenated to Status Register 1). + * - When to use: + * - This function is suitable for the same applications above but it allows to + * overcome the limitations of I2C_GetFlagStatus() function (see below). + * The returned value could be compared to events already defined in the + * library (stm32f10x_i2c.h) or to custom values defined by user. + * - This function is suitable when multiple flags are monitored at the same time. + * - At the opposite of I2C_CheckEvent() function, this function allows user to + * choose when an event is accepted (when all events flags are set and no + * other flags are set or just when the needed flags are set like + * I2C_CheckEvent() function). + * - Limitations: + * - User may need to define his own events. + * - Same remark concerning the error management is applicable for this + * function if user decides to check only regular communication flags (and + * ignores error flags). + * + * + * 3) Flag-based state monitoring: + * Using the function I2C_GetFlagStatus() which simply returns the status of + * one single flag (ie. I2C_FLAG_RXNE ...). + * - When to use: + * - This function could be used for specific applications or in debug phase. + * - It is suitable when only one flag checking is needed (most I2C events + * are monitored through multiple flags). + * - Limitations: + * - When calling this function, the Status register is accessed. Some flags are + * cleared when the status register is accessed. So checking the status + * of one Flag, may clear other ones. + * - Function may need to be called twice or more in order to monitor one + * single event. + * + */ + +/** + * + * 1) Basic state monitoring + ******************************************************************************* + */ +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); +/** + * + * 2) Advanced state monitoring + ******************************************************************************* + */ +uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); +/** + * + * 3) Flag-based state monitoring + ******************************************************************************* + */ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); +/** + * + ******************************************************************************* + */ + +void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); +ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT); +void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F10x_I2C_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/STM32F10x_FWLIB/inc/stm32f10x_iwdg.h b/STM32F10x_FWLIB/inc/stm32f10x_iwdg.h new file mode 100644 index 0000000..76e3949 --- /dev/null +++ b/STM32F10x_FWLIB/inc/stm32f10x_iwdg.h @@ -0,0 +1,138 @@ +/** + ****************************************************************************** + * @file stm32f10x_iwdg.h + * @author MCD Application Team + * @version V3.6.2 + * @date 17-September-2021 + * @brief This file contains all the functions prototypes for the IWDG + * firmware library. + ****************************************************************************** + * @attention + * + * Copyright (c) 2012 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_IWDG_H +#define __STM32F10x_IWDG_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup IWDG + * @{ + */ + +/** @defgroup IWDG_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup IWDG_Exported_Constants + * @{ + */ + +/** @defgroup IWDG_WriteAccess + * @{ + */ + +#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) +#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) +#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \ + ((ACCESS) == IWDG_WriteAccess_Disable)) +/** + * @} + */ + +/** @defgroup IWDG_prescaler + * @{ + */ + +#define IWDG_Prescaler_4 ((uint8_t)0x00) +#define IWDG_Prescaler_8 ((uint8_t)0x01) +#define IWDG_Prescaler_16 ((uint8_t)0x02) +#define IWDG_Prescaler_32 ((uint8_t)0x03) +#define IWDG_Prescaler_64 ((uint8_t)0x04) +#define IWDG_Prescaler_128 ((uint8_t)0x05) +#define IWDG_Prescaler_256 ((uint8_t)0x06) +#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \ + ((PRESCALER) == IWDG_Prescaler_8) || \ + ((PRESCALER) == IWDG_Prescaler_16) || \ + ((PRESCALER) == IWDG_Prescaler_32) || \ + ((PRESCALER) == IWDG_Prescaler_64) || \ + ((PRESCALER) == IWDG_Prescaler_128)|| \ + ((PRESCALER) == IWDG_Prescaler_256)) +/** + * @} + */ + +/** @defgroup IWDG_Flag + * @{ + */ + +#define IWDG_FLAG_PVU ((uint16_t)0x0001) +#define IWDG_FLAG_RVU ((uint16_t)0x0002) +#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU)) +#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup IWDG_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup IWDG_Exported_Functions + * @{ + */ + +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); +void IWDG_SetReload(uint16_t Reload); +void IWDG_ReloadCounter(void); +void IWDG_Enable(void); +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_IWDG_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/STM32F10x_FWLIB/inc/stm32f10x_pwr.h b/STM32F10x_FWLIB/inc/stm32f10x_pwr.h new file mode 100644 index 0000000..927aa81 --- /dev/null +++ b/STM32F10x_FWLIB/inc/stm32f10x_pwr.h @@ -0,0 +1,154 @@ +/** + ****************************************************************************** + * @file stm32f10x_pwr.h + * @author MCD Application Team + * @version V3.6.2 + * @date 17-September-2021 + * @brief This file contains all the functions prototypes for the PWR firmware + * library. + ****************************************************************************** + * @attention + * + * Copyright (c) 2012 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_PWR_H +#define __STM32F10x_PWR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup PWR + * @{ + */ + +/** @defgroup PWR_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup PWR_Exported_Constants + * @{ + */ + +/** @defgroup PVD_detection_level + * @{ + */ + +#define PWR_PVDLevel_2V2 ((uint32_t)0x00000000) +#define PWR_PVDLevel_2V3 ((uint32_t)0x00000020) +#define PWR_PVDLevel_2V4 ((uint32_t)0x00000040) +#define PWR_PVDLevel_2V5 ((uint32_t)0x00000060) +#define PWR_PVDLevel_2V6 ((uint32_t)0x00000080) +#define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0) +#define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0) +#define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0) +#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| \ + ((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| \ + ((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| \ + ((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9)) +/** + * @} + */ + +/** @defgroup Regulator_state_is_STOP_mode + * @{ + */ + +#define PWR_Regulator_ON ((uint32_t)0x00000000) +#define PWR_Regulator_LowPower ((uint32_t)0x00000001) +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \ + ((REGULATOR) == PWR_Regulator_LowPower)) +/** + * @} + */ + +/** @defgroup STOP_mode_entry + * @{ + */ + +#define PWR_STOPEntry_WFI ((uint8_t)0x01) +#define PWR_STOPEntry_WFE ((uint8_t)0x02) +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE)) + +/** + * @} + */ + +/** @defgroup PWR_Flag + * @{ + */ + +#define PWR_FLAG_WU ((uint32_t)0x00000001) +#define PWR_FLAG_SB ((uint32_t)0x00000002) +#define PWR_FLAG_PVDO ((uint32_t)0x00000004) +#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ + ((FLAG) == PWR_FLAG_PVDO)) + +#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB)) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup PWR_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup PWR_Exported_Functions + * @{ + */ + +void PWR_DeInit(void); +void PWR_BackupAccessCmd(FunctionalState NewState); +void PWR_PVDCmd(FunctionalState NewState); +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); +void PWR_WakeUpPinCmd(FunctionalState NewState); +void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); +void PWR_EnterSTANDBYMode(void); +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); +void PWR_ClearFlag(uint32_t PWR_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_PWR_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/STM32F10x_FWLIB/inc/stm32f10x_rcc.h b/STM32F10x_FWLIB/inc/stm32f10x_rcc.h new file mode 100644 index 0000000..64c4677 --- /dev/null +++ b/STM32F10x_FWLIB/inc/stm32f10x_rcc.h @@ -0,0 +1,725 @@ +/** + ****************************************************************************** + * @file stm32f10x_rcc.h + * @author MCD Application Team + * @version V3.6.2 + * @date 17-September-2021 + * @brief This file contains all the functions prototypes for the RCC firmware + * library. + ****************************************************************************** + * @attention + * + * Copyright (c) 2012 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_RCC_H +#define __STM32F10x_RCC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/** @defgroup RCC_Exported_Types + * @{ + */ + +typedef struct +{ + uint32_t SYSCLK_Frequency; /*!< returns SYSCLK clock frequency expressed in Hz */ + uint32_t HCLK_Frequency; /*!< returns HCLK clock frequency expressed in Hz */ + uint32_t PCLK1_Frequency; /*!< returns PCLK1 clock frequency expressed in Hz */ + uint32_t PCLK2_Frequency; /*!< returns PCLK2 clock frequency expressed in Hz */ + uint32_t ADCCLK_Frequency; /*!< returns ADCCLK clock frequency expressed in Hz */ +}RCC_ClocksTypeDef; + +/** + * @} + */ + +/** @defgroup RCC_Exported_Constants + * @{ + */ + +/** @defgroup HSE_configuration + * @{ + */ + +#define RCC_HSE_OFF ((uint32_t)0x00000000) +#define RCC_HSE_ON ((uint32_t)0x00010000) +#define RCC_HSE_Bypass ((uint32_t)0x00040000) +#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ + ((HSE) == RCC_HSE_Bypass)) + +/** + * @} + */ + +/** @defgroup PLL_entry_clock_source + * @{ + */ + +#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000) + +#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_CL) + #define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000) + #define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000) + #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ + ((SOURCE) == RCC_PLLSource_HSE_Div1) || \ + ((SOURCE) == RCC_PLLSource_HSE_Div2)) +#else + #define RCC_PLLSource_PREDIV1 ((uint32_t)0x00010000) + #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ + ((SOURCE) == RCC_PLLSource_PREDIV1)) +#endif /* STM32F10X_CL */ + +/** + * @} + */ + +/** @defgroup PLL_multiplication_factor + * @{ + */ +#ifndef STM32F10X_CL + #define RCC_PLLMul_2 ((uint32_t)0x00000000) + #define RCC_PLLMul_3 ((uint32_t)0x00040000) + #define RCC_PLLMul_4 ((uint32_t)0x00080000) + #define RCC_PLLMul_5 ((uint32_t)0x000C0000) + #define RCC_PLLMul_6 ((uint32_t)0x00100000) + #define RCC_PLLMul_7 ((uint32_t)0x00140000) + #define RCC_PLLMul_8 ((uint32_t)0x00180000) + #define RCC_PLLMul_9 ((uint32_t)0x001C0000) + #define RCC_PLLMul_10 ((uint32_t)0x00200000) + #define RCC_PLLMul_11 ((uint32_t)0x00240000) + #define RCC_PLLMul_12 ((uint32_t)0x00280000) + #define RCC_PLLMul_13 ((uint32_t)0x002C0000) + #define RCC_PLLMul_14 ((uint32_t)0x00300000) + #define RCC_PLLMul_15 ((uint32_t)0x00340000) + #define RCC_PLLMul_16 ((uint32_t)0x00380000) + #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \ + ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ + ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ + ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ + ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \ + ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \ + ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \ + ((MUL) == RCC_PLLMul_16)) + +#else + #define RCC_PLLMul_4 ((uint32_t)0x00080000) + #define RCC_PLLMul_5 ((uint32_t)0x000C0000) + #define RCC_PLLMul_6 ((uint32_t)0x00100000) + #define RCC_PLLMul_7 ((uint32_t)0x00140000) + #define RCC_PLLMul_8 ((uint32_t)0x00180000) + #define RCC_PLLMul_9 ((uint32_t)0x001C0000) + #define RCC_PLLMul_6_5 ((uint32_t)0x00340000) + + #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ + ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ + ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ + ((MUL) == RCC_PLLMul_6_5)) +#endif /* STM32F10X_CL */ +/** + * @} + */ + +/** @defgroup PREDIV1_division_factor + * @{ + */ +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) + #define RCC_PREDIV1_Div1 ((uint32_t)0x00000000) + #define RCC_PREDIV1_Div2 ((uint32_t)0x00000001) + #define RCC_PREDIV1_Div3 ((uint32_t)0x00000002) + #define RCC_PREDIV1_Div4 ((uint32_t)0x00000003) + #define RCC_PREDIV1_Div5 ((uint32_t)0x00000004) + #define RCC_PREDIV1_Div6 ((uint32_t)0x00000005) + #define RCC_PREDIV1_Div7 ((uint32_t)0x00000006) + #define RCC_PREDIV1_Div8 ((uint32_t)0x00000007) + #define RCC_PREDIV1_Div9 ((uint32_t)0x00000008) + #define RCC_PREDIV1_Div10 ((uint32_t)0x00000009) + #define RCC_PREDIV1_Div11 ((uint32_t)0x0000000A) + #define RCC_PREDIV1_Div12 ((uint32_t)0x0000000B) + #define RCC_PREDIV1_Div13 ((uint32_t)0x0000000C) + #define RCC_PREDIV1_Div14 ((uint32_t)0x0000000D) + #define RCC_PREDIV1_Div15 ((uint32_t)0x0000000E) + #define RCC_PREDIV1_Div16 ((uint32_t)0x0000000F) + + #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \ + ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \ + ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \ + ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \ + ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \ + ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \ + ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \ + ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16)) +#endif +/** + * @} + */ + + +/** @defgroup PREDIV1_clock_source + * @{ + */ +#ifdef STM32F10X_CL +/* PREDIV1 clock source (for STM32 connectivity line devices) */ + #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) + #define RCC_PREDIV1_Source_PLL2 ((uint32_t)0x00010000) + + #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE) || \ + ((SOURCE) == RCC_PREDIV1_Source_PLL2)) +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +/* PREDIV1 clock source (for STM32 Value line devices) */ + #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) + + #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE)) +#endif +/** + * @} + */ + +#ifdef STM32F10X_CL +/** @defgroup PREDIV2_division_factor + * @{ + */ + + #define RCC_PREDIV2_Div1 ((uint32_t)0x00000000) + #define RCC_PREDIV2_Div2 ((uint32_t)0x00000010) + #define RCC_PREDIV2_Div3 ((uint32_t)0x00000020) + #define RCC_PREDIV2_Div4 ((uint32_t)0x00000030) + #define RCC_PREDIV2_Div5 ((uint32_t)0x00000040) + #define RCC_PREDIV2_Div6 ((uint32_t)0x00000050) + #define RCC_PREDIV2_Div7 ((uint32_t)0x00000060) + #define RCC_PREDIV2_Div8 ((uint32_t)0x00000070) + #define RCC_PREDIV2_Div9 ((uint32_t)0x00000080) + #define RCC_PREDIV2_Div10 ((uint32_t)0x00000090) + #define RCC_PREDIV2_Div11 ((uint32_t)0x000000A0) + #define RCC_PREDIV2_Div12 ((uint32_t)0x000000B0) + #define RCC_PREDIV2_Div13 ((uint32_t)0x000000C0) + #define RCC_PREDIV2_Div14 ((uint32_t)0x000000D0) + #define RCC_PREDIV2_Div15 ((uint32_t)0x000000E0) + #define RCC_PREDIV2_Div16 ((uint32_t)0x000000F0) + + #define IS_RCC_PREDIV2(PREDIV2) (((PREDIV2) == RCC_PREDIV2_Div1) || ((PREDIV2) == RCC_PREDIV2_Div2) || \ + ((PREDIV2) == RCC_PREDIV2_Div3) || ((PREDIV2) == RCC_PREDIV2_Div4) || \ + ((PREDIV2) == RCC_PREDIV2_Div5) || ((PREDIV2) == RCC_PREDIV2_Div6) || \ + ((PREDIV2) == RCC_PREDIV2_Div7) || ((PREDIV2) == RCC_PREDIV2_Div8) || \ + ((PREDIV2) == RCC_PREDIV2_Div9) || ((PREDIV2) == RCC_PREDIV2_Div10) || \ + ((PREDIV2) == RCC_PREDIV2_Div11) || ((PREDIV2) == RCC_PREDIV2_Div12) || \ + ((PREDIV2) == RCC_PREDIV2_Div13) || ((PREDIV2) == RCC_PREDIV2_Div14) || \ + ((PREDIV2) == RCC_PREDIV2_Div15) || ((PREDIV2) == RCC_PREDIV2_Div16)) +/** + * @} + */ + + +/** @defgroup PLL2_multiplication_factor + * @{ + */ + + #define RCC_PLL2Mul_8 ((uint32_t)0x00000600) + #define RCC_PLL2Mul_9 ((uint32_t)0x00000700) + #define RCC_PLL2Mul_10 ((uint32_t)0x00000800) + #define RCC_PLL2Mul_11 ((uint32_t)0x00000900) + #define RCC_PLL2Mul_12 ((uint32_t)0x00000A00) + #define RCC_PLL2Mul_13 ((uint32_t)0x00000B00) + #define RCC_PLL2Mul_14 ((uint32_t)0x00000C00) + #define RCC_PLL2Mul_16 ((uint32_t)0x00000E00) + #define RCC_PLL2Mul_20 ((uint32_t)0x00000F00) + + #define IS_RCC_PLL2_MUL(MUL) (((MUL) == RCC_PLL2Mul_8) || ((MUL) == RCC_PLL2Mul_9) || \ + ((MUL) == RCC_PLL2Mul_10) || ((MUL) == RCC_PLL2Mul_11) || \ + ((MUL) == RCC_PLL2Mul_12) || ((MUL) == RCC_PLL2Mul_13) || \ + ((MUL) == RCC_PLL2Mul_14) || ((MUL) == RCC_PLL2Mul_16) || \ + ((MUL) == RCC_PLL2Mul_20)) +/** + * @} + */ + + +/** @defgroup PLL3_multiplication_factor + * @{ + */ + + #define RCC_PLL3Mul_8 ((uint32_t)0x00006000) + #define RCC_PLL3Mul_9 ((uint32_t)0x00007000) + #define RCC_PLL3Mul_10 ((uint32_t)0x00008000) + #define RCC_PLL3Mul_11 ((uint32_t)0x00009000) + #define RCC_PLL3Mul_12 ((uint32_t)0x0000A000) + #define RCC_PLL3Mul_13 ((uint32_t)0x0000B000) + #define RCC_PLL3Mul_14 ((uint32_t)0x0000C000) + #define RCC_PLL3Mul_16 ((uint32_t)0x0000E000) + #define RCC_PLL3Mul_20 ((uint32_t)0x0000F000) + + #define IS_RCC_PLL3_MUL(MUL) (((MUL) == RCC_PLL3Mul_8) || ((MUL) == RCC_PLL3Mul_9) || \ + ((MUL) == RCC_PLL3Mul_10) || ((MUL) == RCC_PLL3Mul_11) || \ + ((MUL) == RCC_PLL3Mul_12) || ((MUL) == RCC_PLL3Mul_13) || \ + ((MUL) == RCC_PLL3Mul_14) || ((MUL) == RCC_PLL3Mul_16) || \ + ((MUL) == RCC_PLL3Mul_20)) +/** + * @} + */ + +#endif /* STM32F10X_CL */ + + +/** @defgroup System_clock_source + * @{ + */ + +#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) +#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) +#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) +#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ + ((SOURCE) == RCC_SYSCLKSource_HSE) || \ + ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) +/** + * @} + */ + +/** @defgroup AHB_clock_source + * @{ + */ + +#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) +#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) +#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) +#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) +#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) +#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) +#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) +#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) +#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) +#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ + ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ + ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ + ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ + ((HCLK) == RCC_SYSCLK_Div512)) +/** + * @} + */ + +/** @defgroup APB1_APB2_clock_source + * @{ + */ + +#define RCC_HCLK_Div1 ((uint32_t)0x00000000) +#define RCC_HCLK_Div2 ((uint32_t)0x00000400) +#define RCC_HCLK_Div4 ((uint32_t)0x00000500) +#define RCC_HCLK_Div8 ((uint32_t)0x00000600) +#define RCC_HCLK_Div16 ((uint32_t)0x00000700) +#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ + ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ + ((PCLK) == RCC_HCLK_Div16)) +/** + * @} + */ + +/** @defgroup RCC_Interrupt_source + * @{ + */ + +#define RCC_IT_LSIRDY ((uint8_t)0x01) +#define RCC_IT_LSERDY ((uint8_t)0x02) +#define RCC_IT_HSIRDY ((uint8_t)0x04) +#define RCC_IT_HSERDY ((uint8_t)0x08) +#define RCC_IT_PLLRDY ((uint8_t)0x10) +#define RCC_IT_CSS ((uint8_t)0x80) + +#ifndef STM32F10X_CL + #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00)) + #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ + ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ + ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS)) + #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00)) +#else + #define RCC_IT_PLL2RDY ((uint8_t)0x20) + #define RCC_IT_PLL3RDY ((uint8_t)0x40) + #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00)) + #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ + ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ + ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \ + ((IT) == RCC_IT_PLL2RDY) || ((IT) == RCC_IT_PLL3RDY)) + #define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00) +#endif /* STM32F10X_CL */ + + +/** + * @} + */ + +#ifndef STM32F10X_CL +/** @defgroup USB_Device_clock_source + * @{ + */ + + #define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00) + #define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01) + + #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \ + ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1)) +/** + * @} + */ +#else +/** @defgroup USB_OTG_FS_clock_source + * @{ + */ + #define RCC_OTGFSCLKSource_PLLVCO_Div3 ((uint8_t)0x00) + #define RCC_OTGFSCLKSource_PLLVCO_Div2 ((uint8_t)0x01) + + #define IS_RCC_OTGFSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div3) || \ + ((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div2)) +/** + * @} + */ +#endif /* STM32F10X_CL */ + + +#ifdef STM32F10X_CL +/** @defgroup I2S2_clock_source + * @{ + */ + #define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00) + #define RCC_I2S2CLKSource_PLL3_VCO ((uint8_t)0x01) + + #define IS_RCC_I2S2CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || \ + ((SOURCE) == RCC_I2S2CLKSource_PLL3_VCO)) +/** + * @} + */ + +/** @defgroup I2S3_clock_source + * @{ + */ + #define RCC_I2S3CLKSource_SYSCLK ((uint8_t)0x00) + #define RCC_I2S3CLKSource_PLL3_VCO ((uint8_t)0x01) + + #define IS_RCC_I2S3CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S3CLKSource_SYSCLK) || \ + ((SOURCE) == RCC_I2S3CLKSource_PLL3_VCO)) +/** + * @} + */ +#endif /* STM32F10X_CL */ + + +/** @defgroup ADC_clock_source + * @{ + */ + +#define RCC_PCLK2_Div2 ((uint32_t)0x00000000) +#define RCC_PCLK2_Div4 ((uint32_t)0x00004000) +#define RCC_PCLK2_Div6 ((uint32_t)0x00008000) +#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) +#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \ + ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8)) +/** + * @} + */ + +/** @defgroup LSE_configuration + * @{ + */ + +#define RCC_LSE_OFF ((uint8_t)0x00) +#define RCC_LSE_ON ((uint8_t)0x01) +#define RCC_LSE_Bypass ((uint8_t)0x04) +#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ + ((LSE) == RCC_LSE_Bypass)) +/** + * @} + */ + +/** @defgroup RTC_clock_source + * @{ + */ + +#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) +#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) +#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300) +#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ + ((SOURCE) == RCC_RTCCLKSource_LSI) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div128)) +/** + * @} + */ + +/** @defgroup AHB_peripheral + * @{ + */ + +#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) +#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002) +#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) +#define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010) +#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040) + +#ifndef STM32F10X_CL + #define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100) + #define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400) + #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00)) +#else + #define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000) + #define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000) + #define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000) + #define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000) + + #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFE2FA8) == 0x00) && ((PERIPH) != 0x00)) + #define IS_RCC_AHB_PERIPH_RESET(PERIPH) ((((PERIPH) & 0xFFFFAFFF) == 0x00) && ((PERIPH) != 0x00)) +#endif /* STM32F10X_CL */ +/** + * @} + */ + +/** @defgroup APB2_peripheral + * @{ + */ + +#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) +#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) +#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008) +#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) +#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020) +#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040) +#define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080) +#define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100) +#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) +#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400) +#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) +#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) +#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000) +#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) +#define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000) +#define RCC_APB2Periph_TIM15 ((uint32_t)0x00010000) +#define RCC_APB2Periph_TIM16 ((uint32_t)0x00020000) +#define RCC_APB2Periph_TIM17 ((uint32_t)0x00040000) +#define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000) +#define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000) +#define RCC_APB2Periph_TIM11 ((uint32_t)0x00200000) + +#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC00002) == 0x00) && ((PERIPH) != 0x00)) +/** + * @} + */ + +/** @defgroup APB1_peripheral + * @{ + */ + +#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) +#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) +#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) +#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) +#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) +#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) +#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040) +#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080) +#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100) +#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) +#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) +#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) +#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) +#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) +#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) +#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) +#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) +#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) +#define RCC_APB1Periph_USB ((uint32_t)0x00800000) +#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) +#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) +#define RCC_APB1Periph_BKP ((uint32_t)0x08000000) +#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) +#define RCC_APB1Periph_DAC ((uint32_t)0x20000000) +#define RCC_APB1Periph_CEC ((uint32_t)0x40000000) + +#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x81013600) == 0x00) && ((PERIPH) != 0x00)) + +/** + * @} + */ + +/** @defgroup Clock_source_to_output_on_MCO_pin + * @{ + */ + +#define RCC_MCO_NoClock ((uint8_t)0x00) +#define RCC_MCO_SYSCLK ((uint8_t)0x04) +#define RCC_MCO_HSI ((uint8_t)0x05) +#define RCC_MCO_HSE ((uint8_t)0x06) +#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07) + +#ifndef STM32F10X_CL + #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ + ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ + ((MCO) == RCC_MCO_PLLCLK_Div2)) +#else + #define RCC_MCO_PLL2CLK ((uint8_t)0x08) + #define RCC_MCO_PLL3CLK_Div2 ((uint8_t)0x09) + #define RCC_MCO_XT1 ((uint8_t)0x0A) + #define RCC_MCO_PLL3CLK ((uint8_t)0x0B) + + #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ + ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ + ((MCO) == RCC_MCO_PLLCLK_Div2) || ((MCO) == RCC_MCO_PLL2CLK) || \ + ((MCO) == RCC_MCO_PLL3CLK_Div2) || ((MCO) == RCC_MCO_XT1) || \ + ((MCO) == RCC_MCO_PLL3CLK)) +#endif /* STM32F10X_CL */ + +/** + * @} + */ + +/** @defgroup RCC_Flag + * @{ + */ + +#define RCC_FLAG_HSIRDY ((uint8_t)0x21) +#define RCC_FLAG_HSERDY ((uint8_t)0x31) +#define RCC_FLAG_PLLRDY ((uint8_t)0x39) +#define RCC_FLAG_LSERDY ((uint8_t)0x41) +#define RCC_FLAG_LSIRDY ((uint8_t)0x61) +#define RCC_FLAG_PINRST ((uint8_t)0x7A) +#define RCC_FLAG_PORRST ((uint8_t)0x7B) +#define RCC_FLAG_SFTRST ((uint8_t)0x7C) +#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) +#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) +#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) + +#ifndef STM32F10X_CL + #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ + ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ + ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ + ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ + ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ + ((FLAG) == RCC_FLAG_LPWRRST)) +#else + #define RCC_FLAG_PLL2RDY ((uint8_t)0x3B) + #define RCC_FLAG_PLL3RDY ((uint8_t)0x3D) + #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ + ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ + ((FLAG) == RCC_FLAG_PLL2RDY) || ((FLAG) == RCC_FLAG_PLL3RDY) || \ + ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ + ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ + ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ + ((FLAG) == RCC_FLAG_LPWRRST)) +#endif /* STM32F10X_CL */ + +#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup RCC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup RCC_Exported_Functions + * @{ + */ + +void RCC_DeInit(void); +void RCC_HSEConfig(uint32_t RCC_HSE); +ErrorStatus RCC_WaitForHSEStartUp(void); +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); +void RCC_HSICmd(FunctionalState NewState); +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); +void RCC_PLLCmd(FunctionalState NewState); + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) + void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div); +#endif + +#ifdef STM32F10X_CL + void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div); + void RCC_PLL2Config(uint32_t RCC_PLL2Mul); + void RCC_PLL2Cmd(FunctionalState NewState); + void RCC_PLL3Config(uint32_t RCC_PLL3Mul); + void RCC_PLL3Cmd(FunctionalState NewState); +#endif /* STM32F10X_CL */ + +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); +uint8_t RCC_GetSYSCLKSource(void); +void RCC_HCLKConfig(uint32_t RCC_SYSCLK); +void RCC_PCLK1Config(uint32_t RCC_HCLK); +void RCC_PCLK2Config(uint32_t RCC_HCLK); +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); + +#ifndef STM32F10X_CL + void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource); +#else + void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource); +#endif /* STM32F10X_CL */ + +void RCC_ADCCLKConfig(uint32_t RCC_PCLK2); + +#ifdef STM32F10X_CL + void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource); + void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource); +#endif /* STM32F10X_CL */ + +void RCC_LSEConfig(uint8_t RCC_LSE); +void RCC_LSICmd(FunctionalState NewState); +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); +void RCC_RTCCLKCmd(FunctionalState NewState); +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); +void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); + +#ifdef STM32F10X_CL +void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); +#endif /* STM32F10X_CL */ + +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_BackupResetCmd(FunctionalState NewState); +void RCC_ClockSecuritySystemCmd(FunctionalState NewState); +void RCC_MCOConfig(uint8_t RCC_MCO); +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); +void RCC_ClearFlag(void); +ITStatus RCC_GetITStatus(uint8_t RCC_IT); +void RCC_ClearITPendingBit(uint8_t RCC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_RCC_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/STM32F10x_FWLIB/inc/stm32f10x_rtc.h b/STM32F10x_FWLIB/inc/stm32f10x_rtc.h new file mode 100644 index 0000000..021dc30 --- /dev/null +++ b/STM32F10x_FWLIB/inc/stm32f10x_rtc.h @@ -0,0 +1,133 @@ +/** + ****************************************************************************** + * @file stm32f10x_rtc.h + * @author MCD Application Team + * @version V3.6.2 + * @date 17-September-2021 + * @brief This file contains all the functions prototypes for the RTC firmware + * library. + ****************************************************************************** + * @attention + * + * Copyright (c) 2012 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_RTC_H +#define __STM32F10x_RTC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup RTC + * @{ + */ + +/** @defgroup RTC_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup RTC_Exported_Constants + * @{ + */ + +/** @defgroup RTC_interrupts_define + * @{ + */ + +#define RTC_IT_OW ((uint16_t)0x0004) /*!< Overflow interrupt */ +#define RTC_IT_ALR ((uint16_t)0x0002) /*!< Alarm interrupt */ +#define RTC_IT_SEC ((uint16_t)0x0001) /*!< Second interrupt */ +#define IS_RTC_IT(IT) ((((IT) & (uint16_t)0xFFF8) == 0x00) && ((IT) != 0x00)) +#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_OW) || ((IT) == RTC_IT_ALR) || \ + ((IT) == RTC_IT_SEC)) +/** + * @} + */ + +/** @defgroup RTC_interrupts_flags + * @{ + */ + +#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /*!< RTC Operation OFF flag */ +#define RTC_FLAG_RSF ((uint16_t)0x0008) /*!< Registers Synchronized flag */ +#define RTC_FLAG_OW ((uint16_t)0x0004) /*!< Overflow flag */ +#define RTC_FLAG_ALR ((uint16_t)0x0002) /*!< Alarm flag */ +#define RTC_FLAG_SEC ((uint16_t)0x0001) /*!< Second flag */ +#define IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFF0) == 0x00) && ((FLAG) != 0x00)) +#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RTOFF) || ((FLAG) == RTC_FLAG_RSF) || \ + ((FLAG) == RTC_FLAG_OW) || ((FLAG) == RTC_FLAG_ALR) || \ + ((FLAG) == RTC_FLAG_SEC)) +#define IS_RTC_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFFF) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup RTC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup RTC_Exported_Functions + * @{ + */ + +void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState); +void RTC_EnterConfigMode(void); +void RTC_ExitConfigMode(void); +uint32_t RTC_GetCounter(void); +void RTC_SetCounter(uint32_t CounterValue); +void RTC_SetPrescaler(uint32_t PrescalerValue); +void RTC_SetAlarm(uint32_t AlarmValue); +uint32_t RTC_GetDivider(void); +void RTC_WaitForLastTask(void); +void RTC_WaitForSynchro(void); +FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG); +void RTC_ClearFlag(uint16_t RTC_FLAG); +ITStatus RTC_GetITStatus(uint16_t RTC_IT); +void RTC_ClearITPendingBit(uint16_t RTC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_RTC_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/STM32F10x_FWLIB/inc/stm32f10x_sdio.h b/STM32F10x_FWLIB/inc/stm32f10x_sdio.h new file mode 100644 index 0000000..02bfb32 --- /dev/null +++ b/STM32F10x_FWLIB/inc/stm32f10x_sdio.h @@ -0,0 +1,529 @@ +/** + ****************************************************************************** + * @file stm32f10x_sdio.h + * @author MCD Application Team + * @version V3.6.2 + * @date 17-September-2021 + * @brief This file contains all the functions prototypes for the SDIO firmware + * library. + ****************************************************************************** + * @attention + * + * Copyright (c) 2012 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_SDIO_H +#define __STM32F10x_SDIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup SDIO + * @{ + */ + +/** @defgroup SDIO_Exported_Types + * @{ + */ + +typedef struct +{ + uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref SDIO_Clock_Edge */ + + uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is + enabled or disabled. + This parameter can be a value of @ref SDIO_Clock_Bypass */ + + uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or + disabled when the bus is idle. + This parameter can be a value of @ref SDIO_Clock_Power_Save */ + + uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width. + This parameter can be a value of @ref SDIO_Bus_Wide */ + + uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled. + This parameter can be a value of @ref SDIO_Hardware_Flow_Control */ + + uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller. + This parameter can be a value between 0x00 and 0xFF. */ + +} SDIO_InitTypeDef; + +typedef struct +{ + uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent + to a card as part of a command message. If a command + contains an argument, it must be loaded into this register + before writing the command to the command register */ + + uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */ + + uint32_t SDIO_Response; /*!< Specifies the SDIO response type. + This parameter can be a value of @ref SDIO_Response_Type */ + + uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled. + This parameter can be a value of @ref SDIO_Wait_Interrupt_State */ + + uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM) + is enabled or disabled. + This parameter can be a value of @ref SDIO_CPSM_State */ +} SDIO_CmdInitTypeDef; + +typedef struct +{ + uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ + + uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */ + + uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer. + This parameter can be a value of @ref SDIO_Data_Block_Size */ + + uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer + is a read or write. + This parameter can be a value of @ref SDIO_Transfer_Direction */ + + uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode. + This parameter can be a value of @ref SDIO_Transfer_Type */ + + uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM) + is enabled or disabled. + This parameter can be a value of @ref SDIO_DPSM_State */ +} SDIO_DataInitTypeDef; + +/** + * @} + */ + +/** @defgroup SDIO_Exported_Constants + * @{ + */ + +/** @defgroup SDIO_Clock_Edge + * @{ + */ + +#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000) +#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000) +#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \ + ((EDGE) == SDIO_ClockEdge_Falling)) +/** + * @} + */ + +/** @defgroup SDIO_Clock_Bypass + * @{ + */ + +#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000) +#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400) +#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \ + ((BYPASS) == SDIO_ClockBypass_Enable)) +/** + * @} + */ + +/** @defgroup SDIO_Clock_Power_Save + * @{ + */ + +#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000) +#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200) +#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \ + ((SAVE) == SDIO_ClockPowerSave_Enable)) +/** + * @} + */ + +/** @defgroup SDIO_Bus_Wide + * @{ + */ + +#define SDIO_BusWide_1b ((uint32_t)0x00000000) +#define SDIO_BusWide_4b ((uint32_t)0x00000800) +#define SDIO_BusWide_8b ((uint32_t)0x00001000) +#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \ + ((WIDE) == SDIO_BusWide_8b)) + +/** + * @} + */ + +/** @defgroup SDIO_Hardware_Flow_Control + * @{ + */ + +#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000) +#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000) +#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \ + ((CONTROL) == SDIO_HardwareFlowControl_Enable)) +/** + * @} + */ + +/** @defgroup SDIO_Power_State + * @{ + */ + +#define SDIO_PowerState_OFF ((uint32_t)0x00000000) +#define SDIO_PowerState_ON ((uint32_t)0x00000003) +#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON)) +/** + * @} + */ + + +/** @defgroup SDIO_Interrupt_sources + * @{ + */ + +#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001) +#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002) +#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004) +#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008) +#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010) +#define SDIO_IT_RXOVERR ((uint32_t)0x00000020) +#define SDIO_IT_CMDREND ((uint32_t)0x00000040) +#define SDIO_IT_CMDSENT ((uint32_t)0x00000080) +#define SDIO_IT_DATAEND ((uint32_t)0x00000100) +#define SDIO_IT_STBITERR ((uint32_t)0x00000200) +#define SDIO_IT_DBCKEND ((uint32_t)0x00000400) +#define SDIO_IT_CMDACT ((uint32_t)0x00000800) +#define SDIO_IT_TXACT ((uint32_t)0x00001000) +#define SDIO_IT_RXACT ((uint32_t)0x00002000) +#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000) +#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000) +#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000) +#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000) +#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000) +#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000) +#define SDIO_IT_TXDAVL ((uint32_t)0x00100000) +#define SDIO_IT_RXDAVL ((uint32_t)0x00200000) +#define SDIO_IT_SDIOIT ((uint32_t)0x00400000) +#define SDIO_IT_CEATAEND ((uint32_t)0x00800000) +#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00)) +/** + * @} + */ + +/** @defgroup SDIO_Command_Index + * @{ + */ + +#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40) +/** + * @} + */ + +/** @defgroup SDIO_Response_Type + * @{ + */ + +#define SDIO_Response_No ((uint32_t)0x00000000) +#define SDIO_Response_Short ((uint32_t)0x00000040) +#define SDIO_Response_Long ((uint32_t)0x000000C0) +#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \ + ((RESPONSE) == SDIO_Response_Short) || \ + ((RESPONSE) == SDIO_Response_Long)) +/** + * @} + */ + +/** @defgroup SDIO_Wait_Interrupt_State + * @{ + */ + +#define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */ +#define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */ +#define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */ +#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \ + ((WAIT) == SDIO_Wait_Pend)) +/** + * @} + */ + +/** @defgroup SDIO_CPSM_State + * @{ + */ + +#define SDIO_CPSM_Disable ((uint32_t)0x00000000) +#define SDIO_CPSM_Enable ((uint32_t)0x00000400) +#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable)) +/** + * @} + */ + +/** @defgroup SDIO_Response_Registers + * @{ + */ + +#define SDIO_RESP1 ((uint32_t)0x00000000) +#define SDIO_RESP2 ((uint32_t)0x00000004) +#define SDIO_RESP3 ((uint32_t)0x00000008) +#define SDIO_RESP4 ((uint32_t)0x0000000C) +#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \ + ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4)) +/** + * @} + */ + +/** @defgroup SDIO_Data_Length + * @{ + */ + +#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF) +/** + * @} + */ + +/** @defgroup SDIO_Data_Block_Size + * @{ + */ + +#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000) +#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010) +#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020) +#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030) +#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040) +#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050) +#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060) +#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070) +#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080) +#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090) +#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0) +#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0) +#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0) +#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0) +#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0) +#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \ + ((SIZE) == SDIO_DataBlockSize_2b) || \ + ((SIZE) == SDIO_DataBlockSize_4b) || \ + ((SIZE) == SDIO_DataBlockSize_8b) || \ + ((SIZE) == SDIO_DataBlockSize_16b) || \ + ((SIZE) == SDIO_DataBlockSize_32b) || \ + ((SIZE) == SDIO_DataBlockSize_64b) || \ + ((SIZE) == SDIO_DataBlockSize_128b) || \ + ((SIZE) == SDIO_DataBlockSize_256b) || \ + ((SIZE) == SDIO_DataBlockSize_512b) || \ + ((SIZE) == SDIO_DataBlockSize_1024b) || \ + ((SIZE) == SDIO_DataBlockSize_2048b) || \ + ((SIZE) == SDIO_DataBlockSize_4096b) || \ + ((SIZE) == SDIO_DataBlockSize_8192b) || \ + ((SIZE) == SDIO_DataBlockSize_16384b)) +/** + * @} + */ + +/** @defgroup SDIO_Transfer_Direction + * @{ + */ + +#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000) +#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002) +#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \ + ((DIR) == SDIO_TransferDir_ToSDIO)) +/** + * @} + */ + +/** @defgroup SDIO_Transfer_Type + * @{ + */ + +#define SDIO_TransferMode_Block ((uint32_t)0x00000000) +#define SDIO_TransferMode_Stream ((uint32_t)0x00000004) +#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \ + ((MODE) == SDIO_TransferMode_Block)) +/** + * @} + */ + +/** @defgroup SDIO_DPSM_State + * @{ + */ + +#define SDIO_DPSM_Disable ((uint32_t)0x00000000) +#define SDIO_DPSM_Enable ((uint32_t)0x00000001) +#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable)) +/** + * @} + */ + +/** @defgroup SDIO_Flags + * @{ + */ + +#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001) +#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002) +#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004) +#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008) +#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010) +#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020) +#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040) +#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080) +#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100) +#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200) +#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400) +#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800) +#define SDIO_FLAG_TXACT ((uint32_t)0x00001000) +#define SDIO_FLAG_RXACT ((uint32_t)0x00002000) +#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000) +#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000) +#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000) +#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000) +#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000) +#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000) +#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000) +#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000) +#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000) +#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000) +#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \ + ((FLAG) == SDIO_FLAG_DCRCFAIL) || \ + ((FLAG) == SDIO_FLAG_CTIMEOUT) || \ + ((FLAG) == SDIO_FLAG_DTIMEOUT) || \ + ((FLAG) == SDIO_FLAG_TXUNDERR) || \ + ((FLAG) == SDIO_FLAG_RXOVERR) || \ + ((FLAG) == SDIO_FLAG_CMDREND) || \ + ((FLAG) == SDIO_FLAG_CMDSENT) || \ + ((FLAG) == SDIO_FLAG_DATAEND) || \ + ((FLAG) == SDIO_FLAG_STBITERR) || \ + ((FLAG) == SDIO_FLAG_DBCKEND) || \ + ((FLAG) == SDIO_FLAG_CMDACT) || \ + ((FLAG) == SDIO_FLAG_TXACT) || \ + ((FLAG) == SDIO_FLAG_RXACT) || \ + ((FLAG) == SDIO_FLAG_TXFIFOHE) || \ + ((FLAG) == SDIO_FLAG_RXFIFOHF) || \ + ((FLAG) == SDIO_FLAG_TXFIFOF) || \ + ((FLAG) == SDIO_FLAG_RXFIFOF) || \ + ((FLAG) == SDIO_FLAG_TXFIFOE) || \ + ((FLAG) == SDIO_FLAG_RXFIFOE) || \ + ((FLAG) == SDIO_FLAG_TXDAVL) || \ + ((FLAG) == SDIO_FLAG_RXDAVL) || \ + ((FLAG) == SDIO_FLAG_SDIOIT) || \ + ((FLAG) == SDIO_FLAG_CEATAEND)) + +#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00)) + +#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \ + ((IT) == SDIO_IT_DCRCFAIL) || \ + ((IT) == SDIO_IT_CTIMEOUT) || \ + ((IT) == SDIO_IT_DTIMEOUT) || \ + ((IT) == SDIO_IT_TXUNDERR) || \ + ((IT) == SDIO_IT_RXOVERR) || \ + ((IT) == SDIO_IT_CMDREND) || \ + ((IT) == SDIO_IT_CMDSENT) || \ + ((IT) == SDIO_IT_DATAEND) || \ + ((IT) == SDIO_IT_STBITERR) || \ + ((IT) == SDIO_IT_DBCKEND) || \ + ((IT) == SDIO_IT_CMDACT) || \ + ((IT) == SDIO_IT_TXACT) || \ + ((IT) == SDIO_IT_RXACT) || \ + ((IT) == SDIO_IT_TXFIFOHE) || \ + ((IT) == SDIO_IT_RXFIFOHF) || \ + ((IT) == SDIO_IT_TXFIFOF) || \ + ((IT) == SDIO_IT_RXFIFOF) || \ + ((IT) == SDIO_IT_TXFIFOE) || \ + ((IT) == SDIO_IT_RXFIFOE) || \ + ((IT) == SDIO_IT_TXDAVL) || \ + ((IT) == SDIO_IT_RXDAVL) || \ + ((IT) == SDIO_IT_SDIOIT) || \ + ((IT) == SDIO_IT_CEATAEND)) + +#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00)) + +/** + * @} + */ + +/** @defgroup SDIO_Read_Wait_Mode + * @{ + */ + +#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001) +#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000) +#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \ + ((MODE) == SDIO_ReadWaitMode_DATA2)) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup SDIO_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup SDIO_Exported_Functions + * @{ + */ + +void SDIO_DeInit(void); +void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct); +void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct); +void SDIO_ClockCmd(FunctionalState NewState); +void SDIO_SetPowerState(uint32_t SDIO_PowerState); +uint32_t SDIO_GetPowerState(void); +void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState); +void SDIO_DMACmd(FunctionalState NewState); +void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct); +void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct); +uint8_t SDIO_GetCommandResponse(void); +uint32_t SDIO_GetResponse(uint32_t SDIO_RESP); +void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct); +void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct); +uint32_t SDIO_GetDataCounter(void); +uint32_t SDIO_ReadData(void); +void SDIO_WriteData(uint32_t Data); +uint32_t SDIO_GetFIFOCount(void); +void SDIO_StartSDIOReadWait(FunctionalState NewState); +void SDIO_StopSDIOReadWait(FunctionalState NewState); +void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode); +void SDIO_SetSDIOOperation(FunctionalState NewState); +void SDIO_SendSDIOSuspendCmd(FunctionalState NewState); +void SDIO_CommandCompletionCmd(FunctionalState NewState); +void SDIO_CEATAITCmd(FunctionalState NewState); +void SDIO_SendCEATACmd(FunctionalState NewState); +FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG); +void SDIO_ClearFlag(uint32_t SDIO_FLAG); +ITStatus SDIO_GetITStatus(uint32_t SDIO_IT); +void SDIO_ClearITPendingBit(uint32_t SDIO_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_SDIO_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/STM32F10x_FWLIB/inc/stm32f10x_spi.h b/STM32F10x_FWLIB/inc/stm32f10x_spi.h new file mode 100644 index 0000000..c2f17c9 --- /dev/null +++ b/STM32F10x_FWLIB/inc/stm32f10x_spi.h @@ -0,0 +1,485 @@ +/** + ****************************************************************************** + * @file stm32f10x_spi.h + * @author MCD Application Team + * @version V3.6.2 + * @date 17-September-2021 + * @brief This file contains all the functions prototypes for the SPI firmware + * library. + ****************************************************************************** + * @attention + * + * Copyright (c) 2012 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_SPI_H +#define __STM32F10x_SPI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + +/** @defgroup SPI_Exported_Types + * @{ + */ + +/** + * @brief SPI Init structure definition + */ + +typedef struct +{ + uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode. + This parameter can be a value of @ref SPI_data_direction */ + + uint16_t SPI_Mode; /*!< Specifies the SPI operating mode. + This parameter can be a value of @ref SPI_mode */ + + uint16_t SPI_DataSize; /*!< Specifies the SPI data size. + This parameter can be a value of @ref SPI_data_size */ + + uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_Clock_Polarity */ + + uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_Clock_Phase */ + + uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by + hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref SPI_Slave_Select_management */ + + uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_BaudRate_Prescaler. + @note The communication clock is derived from the master + clock. The slave clock does not need to be set. */ + + uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_MSB_LSB_transmission */ + + uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */ +}SPI_InitTypeDef; + +/** + * @brief I2S Init structure definition + */ + +typedef struct +{ + + uint16_t I2S_Mode; /*!< Specifies the I2S operating mode. + This parameter can be a value of @ref I2S_Mode */ + + uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication. + This parameter can be a value of @ref I2S_Standard */ + + uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication. + This parameter can be a value of @ref I2S_Data_Format */ + + uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. + This parameter can be a value of @ref I2S_MCLK_Output */ + + uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication. + This parameter can be a value of @ref I2S_Audio_Frequency */ + + uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock. + This parameter can be a value of @ref I2S_Clock_Polarity */ +}I2S_InitTypeDef; + +/** + * @} + */ + +/** @defgroup SPI_Exported_Constants + * @{ + */ + +#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \ + ((PERIPH) == SPI2) || \ + ((PERIPH) == SPI3)) + +#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \ + ((PERIPH) == SPI3)) + +/** @defgroup SPI_data_direction + * @{ + */ + +#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) +#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) +#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) +#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) +#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ + ((MODE) == SPI_Direction_2Lines_RxOnly) || \ + ((MODE) == SPI_Direction_1Line_Rx) || \ + ((MODE) == SPI_Direction_1Line_Tx)) +/** + * @} + */ + +/** @defgroup SPI_mode + * @{ + */ + +#define SPI_Mode_Master ((uint16_t)0x0104) +#define SPI_Mode_Slave ((uint16_t)0x0000) +#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ + ((MODE) == SPI_Mode_Slave)) +/** + * @} + */ + +/** @defgroup SPI_data_size + * @{ + */ + +#define SPI_DataSize_16b ((uint16_t)0x0800) +#define SPI_DataSize_8b ((uint16_t)0x0000) +#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \ + ((DATASIZE) == SPI_DataSize_8b)) +/** + * @} + */ + +/** @defgroup SPI_Clock_Polarity + * @{ + */ + +#define SPI_CPOL_Low ((uint16_t)0x0000) +#define SPI_CPOL_High ((uint16_t)0x0002) +#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ + ((CPOL) == SPI_CPOL_High)) +/** + * @} + */ + +/** @defgroup SPI_Clock_Phase + * @{ + */ + +#define SPI_CPHA_1Edge ((uint16_t)0x0000) +#define SPI_CPHA_2Edge ((uint16_t)0x0001) +#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ + ((CPHA) == SPI_CPHA_2Edge)) +/** + * @} + */ + +/** @defgroup SPI_Slave_Select_management + * @{ + */ + +#define SPI_NSS_Soft ((uint16_t)0x0200) +#define SPI_NSS_Hard ((uint16_t)0x0000) +#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ + ((NSS) == SPI_NSS_Hard)) +/** + * @} + */ + +/** @defgroup SPI_BaudRate_Prescaler + * @{ + */ + +#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) +#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) +#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) +#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) +#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) +#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) +#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) +#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) +#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_4) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_8) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_16) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_32) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_64) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_128) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_256)) +/** + * @} + */ + +/** @defgroup SPI_MSB_LSB_transmission + * @{ + */ + +#define SPI_FirstBit_MSB ((uint16_t)0x0000) +#define SPI_FirstBit_LSB ((uint16_t)0x0080) +#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ + ((BIT) == SPI_FirstBit_LSB)) +/** + * @} + */ + +/** @defgroup I2S_Mode + * @{ + */ + +#define I2S_Mode_SlaveTx ((uint16_t)0x0000) +#define I2S_Mode_SlaveRx ((uint16_t)0x0100) +#define I2S_Mode_MasterTx ((uint16_t)0x0200) +#define I2S_Mode_MasterRx ((uint16_t)0x0300) +#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \ + ((MODE) == I2S_Mode_SlaveRx) || \ + ((MODE) == I2S_Mode_MasterTx) || \ + ((MODE) == I2S_Mode_MasterRx) ) +/** + * @} + */ + +/** @defgroup I2S_Standard + * @{ + */ + +#define I2S_Standard_Phillips ((uint16_t)0x0000) +#define I2S_Standard_MSB ((uint16_t)0x0010) +#define I2S_Standard_LSB ((uint16_t)0x0020) +#define I2S_Standard_PCMShort ((uint16_t)0x0030) +#define I2S_Standard_PCMLong ((uint16_t)0x00B0) +#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \ + ((STANDARD) == I2S_Standard_MSB) || \ + ((STANDARD) == I2S_Standard_LSB) || \ + ((STANDARD) == I2S_Standard_PCMShort) || \ + ((STANDARD) == I2S_Standard_PCMLong)) +/** + * @} + */ + +/** @defgroup I2S_Data_Format + * @{ + */ + +#define I2S_DataFormat_16b ((uint16_t)0x0000) +#define I2S_DataFormat_16bextended ((uint16_t)0x0001) +#define I2S_DataFormat_24b ((uint16_t)0x0003) +#define I2S_DataFormat_32b ((uint16_t)0x0005) +#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \ + ((FORMAT) == I2S_DataFormat_16bextended) || \ + ((FORMAT) == I2S_DataFormat_24b) || \ + ((FORMAT) == I2S_DataFormat_32b)) +/** + * @} + */ + +/** @defgroup I2S_MCLK_Output + * @{ + */ + +#define I2S_MCLKOutput_Enable ((uint16_t)0x0200) +#define I2S_MCLKOutput_Disable ((uint16_t)0x0000) +#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \ + ((OUTPUT) == I2S_MCLKOutput_Disable)) +/** + * @} + */ + +/** @defgroup I2S_Audio_Frequency + * @{ + */ + +#define I2S_AudioFreq_192k ((uint32_t)192000) +#define I2S_AudioFreq_96k ((uint32_t)96000) +#define I2S_AudioFreq_48k ((uint32_t)48000) +#define I2S_AudioFreq_44k ((uint32_t)44100) +#define I2S_AudioFreq_32k ((uint32_t)32000) +#define I2S_AudioFreq_22k ((uint32_t)22050) +#define I2S_AudioFreq_16k ((uint32_t)16000) +#define I2S_AudioFreq_11k ((uint32_t)11025) +#define I2S_AudioFreq_8k ((uint32_t)8000) +#define I2S_AudioFreq_Default ((uint32_t)2) + +#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \ + ((FREQ) <= I2S_AudioFreq_192k)) || \ + ((FREQ) == I2S_AudioFreq_Default)) +/** + * @} + */ + +/** @defgroup I2S_Clock_Polarity + * @{ + */ + +#define I2S_CPOL_Low ((uint16_t)0x0000) +#define I2S_CPOL_High ((uint16_t)0x0008) +#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \ + ((CPOL) == I2S_CPOL_High)) +/** + * @} + */ + +/** @defgroup SPI_I2S_DMA_transfer_requests + * @{ + */ + +#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) +#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) +#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00)) +/** + * @} + */ + +/** @defgroup SPI_NSS_internal_software_management + * @{ + */ + +#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) +#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) +#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ + ((INTERNAL) == SPI_NSSInternalSoft_Reset)) +/** + * @} + */ + +/** @defgroup SPI_CRC_Transmit_Receive + * @{ + */ + +#define SPI_CRC_Tx ((uint8_t)0x00) +#define SPI_CRC_Rx ((uint8_t)0x01) +#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx)) +/** + * @} + */ + +/** @defgroup SPI_direction_transmit_receive + * @{ + */ + +#define SPI_Direction_Rx ((uint16_t)0xBFFF) +#define SPI_Direction_Tx ((uint16_t)0x4000) +#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \ + ((DIRECTION) == SPI_Direction_Tx)) +/** + * @} + */ + +/** @defgroup SPI_I2S_interrupts_definition + * @{ + */ + +#define SPI_I2S_IT_TXE ((uint8_t)0x71) +#define SPI_I2S_IT_RXNE ((uint8_t)0x60) +#define SPI_I2S_IT_ERR ((uint8_t)0x50) +#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \ + ((IT) == SPI_I2S_IT_RXNE) || \ + ((IT) == SPI_I2S_IT_ERR)) +#define SPI_I2S_IT_OVR ((uint8_t)0x56) +#define SPI_IT_MODF ((uint8_t)0x55) +#define SPI_IT_CRCERR ((uint8_t)0x54) +#define I2S_IT_UDR ((uint8_t)0x53) +#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR)) +#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \ + ((IT) == I2S_IT_UDR) || ((IT) == SPI_IT_CRCERR) || \ + ((IT) == SPI_IT_MODF) || ((IT) == SPI_I2S_IT_OVR)) +/** + * @} + */ + +/** @defgroup SPI_I2S_flags_definition + * @{ + */ + +#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) +#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) +#define I2S_FLAG_CHSIDE ((uint16_t)0x0004) +#define I2S_FLAG_UDR ((uint16_t)0x0008) +#define SPI_FLAG_CRCERR ((uint16_t)0x0010) +#define SPI_FLAG_MODF ((uint16_t)0x0020) +#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) +#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) +#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR)) +#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \ + ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \ + ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \ + ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)) +/** + * @} + */ + +/** @defgroup SPI_CRC_polynomial + * @{ + */ + +#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup SPI_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup SPI_Exported_Functions + * @{ + */ + +void SPI_I2S_DeInit(SPI_TypeDef* SPIx); +void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); +void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); +void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); +void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); +void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); +void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data); +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx); +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); +void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); +void SPI_TransmitCRC(SPI_TypeDef* SPIx); +void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); +uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); +void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); +void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); +void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F10x_SPI_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/STM32F10x_FWLIB/inc/stm32f10x_tim.h b/STM32F10x_FWLIB/inc/stm32f10x_tim.h new file mode 100644 index 0000000..cb98002 --- /dev/null +++ b/STM32F10x_FWLIB/inc/stm32f10x_tim.h @@ -0,0 +1,1162 @@ +/** + ****************************************************************************** + * @file stm32f10x_tim.h + * @author MCD Application Team + * @version V3.6.2 + * @date 17-September-2021 + * @brief This file contains all the functions prototypes for the TIM firmware + * library. + ****************************************************************************** + * @attention + * + * Copyright (c) 2012 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_TIM_H +#define __STM32F10x_TIM_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup TIM + * @{ + */ + +/** @defgroup TIM_Exported_Types + * @{ + */ + +/** + * @brief TIM Time Base Init structure definition + * @note This structure is used with all TIMx except for TIM6 and TIM7. + */ + +typedef struct +{ + uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t TIM_CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint16_t TIM_Period; /*!< Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter must be a number between 0x0000 and 0xFFFF. */ + + uint16_t TIM_ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_Clock_Division_CKD */ + + uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + This parameter must be a number between 0x00 and 0xFF. + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_TimeBaseInitTypeDef; + +/** + * @brief TIM Output Compare Init structure definition + */ + +typedef struct +{ + uint16_t TIM_OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_state */ + + uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_N_state + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t TIM_OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_OCInitTypeDef; + +/** + * @brief TIM Input Capture Init structure definition + */ + +typedef struct +{ + + uint16_t TIM_Channel; /*!< Specifies the TIM channel. + This parameter can be a value of @ref TIM_Channel */ + + uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint16_t TIM_ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint16_t TIM_ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between 0x0 and 0xF */ +} TIM_ICInitTypeDef; + +/** + * @brief BDTR structure definition + * @note This structure is used only with TIM1 and TIM8. + */ + +typedef struct +{ + + uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode. + This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */ + + uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state. + This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters. + This parameter can be a value of @ref Lock_level */ + + uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the + switching-on of the outputs. + This parameter can be a number between 0x00 and 0xFF */ + + uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not. + This parameter can be a value of @ref Break_Input_enable_disable */ + + uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. + This parameter can be a value of @ref Break_Polarity */ + + uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. + This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ +} TIM_BDTRInitTypeDef; + +/** @defgroup TIM_Exported_constants + * @{ + */ + +#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM6) || \ + ((PERIPH) == TIM7) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM9) || \ + ((PERIPH) == TIM10)|| \ + ((PERIPH) == TIM11)|| \ + ((PERIPH) == TIM12)|| \ + ((PERIPH) == TIM13)|| \ + ((PERIPH) == TIM14)|| \ + ((PERIPH) == TIM15)|| \ + ((PERIPH) == TIM16)|| \ + ((PERIPH) == TIM17)) + +/* LIST1: TIM 1 and 8 */ +#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM8)) + +/* LIST2: TIM 1, 8, 15 16 and 17 */ +#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM15)|| \ + ((PERIPH) == TIM16)|| \ + ((PERIPH) == TIM17)) + +/* LIST3: TIM 1, 2, 3, 4, 5 and 8 */ +#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM8)) + +/* LIST4: TIM 1, 2, 3, 4, 5, 8, 15, 16 and 17 */ +#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM15)|| \ + ((PERIPH) == TIM16)|| \ + ((PERIPH) == TIM17)) + +/* LIST5: TIM 1, 2, 3, 4, 5, 8 and 15 */ +#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM15)) + +/* LIST6: TIM 1, 2, 3, 4, 5, 8, 9, 12 and 15 */ +#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM9) || \ + ((PERIPH) == TIM12)|| \ + ((PERIPH) == TIM15)) + +/* LIST7: TIM 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 and 15 */ +#define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM6) || \ + ((PERIPH) == TIM7) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM9) || \ + ((PERIPH) == TIM12)|| \ + ((PERIPH) == TIM15)) + +/* LIST8: TIM 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17 */ +#define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM9) || \ + ((PERIPH) == TIM10)|| \ + ((PERIPH) == TIM11)|| \ + ((PERIPH) == TIM12)|| \ + ((PERIPH) == TIM13)|| \ + ((PERIPH) == TIM14)|| \ + ((PERIPH) == TIM15)|| \ + ((PERIPH) == TIM16)|| \ + ((PERIPH) == TIM17)) + +/* LIST9: TIM 1, 2, 3, 4, 5, 6, 7, 8, 15, 16, and 17 */ +#define IS_TIM_LIST9_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM6) || \ + ((PERIPH) == TIM7) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM15)|| \ + ((PERIPH) == TIM16)|| \ + ((PERIPH) == TIM17)) + +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_and_PWM_modes + * @{ + */ + +#define TIM_OCMode_Timing ((uint16_t)0x0000) +#define TIM_OCMode_Active ((uint16_t)0x0010) +#define TIM_OCMode_Inactive ((uint16_t)0x0020) +#define TIM_OCMode_Toggle ((uint16_t)0x0030) +#define TIM_OCMode_PWM1 ((uint16_t)0x0060) +#define TIM_OCMode_PWM2 ((uint16_t)0x0070) +#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \ + ((MODE) == TIM_OCMode_Active) || \ + ((MODE) == TIM_OCMode_Inactive) || \ + ((MODE) == TIM_OCMode_Toggle)|| \ + ((MODE) == TIM_OCMode_PWM1) || \ + ((MODE) == TIM_OCMode_PWM2)) +#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \ + ((MODE) == TIM_OCMode_Active) || \ + ((MODE) == TIM_OCMode_Inactive) || \ + ((MODE) == TIM_OCMode_Toggle)|| \ + ((MODE) == TIM_OCMode_PWM1) || \ + ((MODE) == TIM_OCMode_PWM2) || \ + ((MODE) == TIM_ForcedAction_Active) || \ + ((MODE) == TIM_ForcedAction_InActive)) +/** + * @} + */ + +/** @defgroup TIM_One_Pulse_Mode + * @{ + */ + +#define TIM_OPMode_Single ((uint16_t)0x0008) +#define TIM_OPMode_Repetitive ((uint16_t)0x0000) +#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \ + ((MODE) == TIM_OPMode_Repetitive)) +/** + * @} + */ + +/** @defgroup TIM_Channel + * @{ + */ + +#define TIM_Channel_1 ((uint16_t)0x0000) +#define TIM_Channel_2 ((uint16_t)0x0004) +#define TIM_Channel_3 ((uint16_t)0x0008) +#define TIM_Channel_4 ((uint16_t)0x000C) +#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ + ((CHANNEL) == TIM_Channel_2) || \ + ((CHANNEL) == TIM_Channel_3) || \ + ((CHANNEL) == TIM_Channel_4)) +#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ + ((CHANNEL) == TIM_Channel_2)) +#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ + ((CHANNEL) == TIM_Channel_2) || \ + ((CHANNEL) == TIM_Channel_3)) +/** + * @} + */ + +/** @defgroup TIM_Clock_Division_CKD + * @{ + */ + +#define TIM_CKD_DIV1 ((uint16_t)0x0000) +#define TIM_CKD_DIV2 ((uint16_t)0x0100) +#define TIM_CKD_DIV4 ((uint16_t)0x0200) +#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \ + ((DIV) == TIM_CKD_DIV2) || \ + ((DIV) == TIM_CKD_DIV4)) +/** + * @} + */ + +/** @defgroup TIM_Counter_Mode + * @{ + */ + +#define TIM_CounterMode_Up ((uint16_t)0x0000) +#define TIM_CounterMode_Down ((uint16_t)0x0010) +#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) +#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) +#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) +#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \ + ((MODE) == TIM_CounterMode_Down) || \ + ((MODE) == TIM_CounterMode_CenterAligned1) || \ + ((MODE) == TIM_CounterMode_CenterAligned2) || \ + ((MODE) == TIM_CounterMode_CenterAligned3)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Polarity + * @{ + */ + +#define TIM_OCPolarity_High ((uint16_t)0x0000) +#define TIM_OCPolarity_Low ((uint16_t)0x0002) +#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \ + ((POLARITY) == TIM_OCPolarity_Low)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Polarity + * @{ + */ + +#define TIM_OCNPolarity_High ((uint16_t)0x0000) +#define TIM_OCNPolarity_Low ((uint16_t)0x0008) +#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \ + ((POLARITY) == TIM_OCNPolarity_Low)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_state + * @{ + */ + +#define TIM_OutputState_Disable ((uint16_t)0x0000) +#define TIM_OutputState_Enable ((uint16_t)0x0001) +#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \ + ((STATE) == TIM_OutputState_Enable)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_state + * @{ + */ + +#define TIM_OutputNState_Disable ((uint16_t)0x0000) +#define TIM_OutputNState_Enable ((uint16_t)0x0004) +#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \ + ((STATE) == TIM_OutputNState_Enable)) +/** + * @} + */ + +/** @defgroup TIM_Capture_Compare_state + * @{ + */ + +#define TIM_CCx_Enable ((uint16_t)0x0001) +#define TIM_CCx_Disable ((uint16_t)0x0000) +#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \ + ((CCX) == TIM_CCx_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Capture_Compare_N_state + * @{ + */ + +#define TIM_CCxN_Enable ((uint16_t)0x0004) +#define TIM_CCxN_Disable ((uint16_t)0x0000) +#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \ + ((CCXN) == TIM_CCxN_Disable)) +/** + * @} + */ + +/** @defgroup Break_Input_enable_disable + * @{ + */ + +#define TIM_Break_Enable ((uint16_t)0x1000) +#define TIM_Break_Disable ((uint16_t)0x0000) +#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \ + ((STATE) == TIM_Break_Disable)) +/** + * @} + */ + +/** @defgroup Break_Polarity + * @{ + */ + +#define TIM_BreakPolarity_Low ((uint16_t)0x0000) +#define TIM_BreakPolarity_High ((uint16_t)0x2000) +#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \ + ((POLARITY) == TIM_BreakPolarity_High)) +/** + * @} + */ + +/** @defgroup TIM_AOE_Bit_Set_Reset + * @{ + */ + +#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) +#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) +#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \ + ((STATE) == TIM_AutomaticOutput_Disable)) +/** + * @} + */ + +/** @defgroup Lock_level + * @{ + */ + +#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) +#define TIM_LOCKLevel_1 ((uint16_t)0x0100) +#define TIM_LOCKLevel_2 ((uint16_t)0x0200) +#define TIM_LOCKLevel_3 ((uint16_t)0x0300) +#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \ + ((LEVEL) == TIM_LOCKLevel_1) || \ + ((LEVEL) == TIM_LOCKLevel_2) || \ + ((LEVEL) == TIM_LOCKLevel_3)) +/** + * @} + */ + +/** @defgroup OSSI_Off_State_Selection_for_Idle_mode_state + * @{ + */ + +#define TIM_OSSIState_Enable ((uint16_t)0x0400) +#define TIM_OSSIState_Disable ((uint16_t)0x0000) +#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \ + ((STATE) == TIM_OSSIState_Disable)) +/** + * @} + */ + +/** @defgroup OSSR_Off_State_Selection_for_Run_mode_state + * @{ + */ + +#define TIM_OSSRState_Enable ((uint16_t)0x0800) +#define TIM_OSSRState_Disable ((uint16_t)0x0000) +#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \ + ((STATE) == TIM_OSSRState_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Idle_State + * @{ + */ + +#define TIM_OCIdleState_Set ((uint16_t)0x0100) +#define TIM_OCIdleState_Reset ((uint16_t)0x0000) +#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \ + ((STATE) == TIM_OCIdleState_Reset)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Idle_State + * @{ + */ + +#define TIM_OCNIdleState_Set ((uint16_t)0x0200) +#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) +#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \ + ((STATE) == TIM_OCNIdleState_Reset)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Polarity + * @{ + */ + +#define TIM_ICPolarity_Rising ((uint16_t)0x0000) +#define TIM_ICPolarity_Falling ((uint16_t)0x0002) +#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) +#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ + ((POLARITY) == TIM_ICPolarity_Falling)) +#define IS_TIM_IC_POLARITY_LITE(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ + ((POLARITY) == TIM_ICPolarity_Falling)|| \ + ((POLARITY) == TIM_ICPolarity_BothEdge)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Selection + * @{ + */ + +#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC2, IC1, IC4 or IC3, respectively. */ +#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ +#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \ + ((SELECTION) == TIM_ICSelection_IndirectTI) || \ + ((SELECTION) == TIM_ICSelection_TRC)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Prescaler + * @{ + */ + +#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */ +#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */ +#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */ +#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */ +#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ + ((PRESCALER) == TIM_ICPSC_DIV2) || \ + ((PRESCALER) == TIM_ICPSC_DIV4) || \ + ((PRESCALER) == TIM_ICPSC_DIV8)) +/** + * @} + */ + +/** @defgroup TIM_interrupt_sources + * @{ + */ + +#define TIM_IT_Update ((uint16_t)0x0001) +#define TIM_IT_CC1 ((uint16_t)0x0002) +#define TIM_IT_CC2 ((uint16_t)0x0004) +#define TIM_IT_CC3 ((uint16_t)0x0008) +#define TIM_IT_CC4 ((uint16_t)0x0010) +#define TIM_IT_COM ((uint16_t)0x0020) +#define TIM_IT_Trigger ((uint16_t)0x0040) +#define TIM_IT_Break ((uint16_t)0x0080) +#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000)) + +#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \ + ((IT) == TIM_IT_CC1) || \ + ((IT) == TIM_IT_CC2) || \ + ((IT) == TIM_IT_CC3) || \ + ((IT) == TIM_IT_CC4) || \ + ((IT) == TIM_IT_COM) || \ + ((IT) == TIM_IT_Trigger) || \ + ((IT) == TIM_IT_Break)) +/** + * @} + */ + +/** @defgroup TIM_DMA_Base_address + * @{ + */ + +#define TIM_DMABase_CR1 ((uint16_t)0x0000) +#define TIM_DMABase_CR2 ((uint16_t)0x0001) +#define TIM_DMABase_SMCR ((uint16_t)0x0002) +#define TIM_DMABase_DIER ((uint16_t)0x0003) +#define TIM_DMABase_SR ((uint16_t)0x0004) +#define TIM_DMABase_EGR ((uint16_t)0x0005) +#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) +#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) +#define TIM_DMABase_CCER ((uint16_t)0x0008) +#define TIM_DMABase_CNT ((uint16_t)0x0009) +#define TIM_DMABase_PSC ((uint16_t)0x000A) +#define TIM_DMABase_ARR ((uint16_t)0x000B) +#define TIM_DMABase_RCR ((uint16_t)0x000C) +#define TIM_DMABase_CCR1 ((uint16_t)0x000D) +#define TIM_DMABase_CCR2 ((uint16_t)0x000E) +#define TIM_DMABase_CCR3 ((uint16_t)0x000F) +#define TIM_DMABase_CCR4 ((uint16_t)0x0010) +#define TIM_DMABase_BDTR ((uint16_t)0x0011) +#define TIM_DMABase_DCR ((uint16_t)0x0012) +#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ + ((BASE) == TIM_DMABase_CR2) || \ + ((BASE) == TIM_DMABase_SMCR) || \ + ((BASE) == TIM_DMABase_DIER) || \ + ((BASE) == TIM_DMABase_SR) || \ + ((BASE) == TIM_DMABase_EGR) || \ + ((BASE) == TIM_DMABase_CCMR1) || \ + ((BASE) == TIM_DMABase_CCMR2) || \ + ((BASE) == TIM_DMABase_CCER) || \ + ((BASE) == TIM_DMABase_CNT) || \ + ((BASE) == TIM_DMABase_PSC) || \ + ((BASE) == TIM_DMABase_ARR) || \ + ((BASE) == TIM_DMABase_RCR) || \ + ((BASE) == TIM_DMABase_CCR1) || \ + ((BASE) == TIM_DMABase_CCR2) || \ + ((BASE) == TIM_DMABase_CCR3) || \ + ((BASE) == TIM_DMABase_CCR4) || \ + ((BASE) == TIM_DMABase_BDTR) || \ + ((BASE) == TIM_DMABase_DCR)) +/** + * @} + */ + +/** @defgroup TIM_DMA_Burst_Length + * @{ + */ + +#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) +#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) +#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) +#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) +#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) +#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) +#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) +#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) +#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) +#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) +#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) +#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) +#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) +#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) +#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) +#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) +#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) +#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) +#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \ + ((LENGTH) == TIM_DMABurstLength_2Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_3Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_4Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_5Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_6Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_7Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_8Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_9Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_10Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_11Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_12Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_13Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_14Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_15Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_16Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_17Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_18Transfers)) +/** + * @} + */ + +/** @defgroup TIM_DMA_sources + * @{ + */ + +#define TIM_DMA_Update ((uint16_t)0x0100) +#define TIM_DMA_CC1 ((uint16_t)0x0200) +#define TIM_DMA_CC2 ((uint16_t)0x0400) +#define TIM_DMA_CC3 ((uint16_t)0x0800) +#define TIM_DMA_CC4 ((uint16_t)0x1000) +#define TIM_DMA_COM ((uint16_t)0x2000) +#define TIM_DMA_Trigger ((uint16_t)0x4000) +#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) + +/** + * @} + */ + +/** @defgroup TIM_External_Trigger_Prescaler + * @{ + */ + +#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) +#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) +#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) +#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) +#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \ + ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \ + ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \ + ((PRESCALER) == TIM_ExtTRGPSC_DIV8)) +/** + * @} + */ + +/** @defgroup TIM_Internal_Trigger_Selection + * @{ + */ + +#define TIM_TS_ITR0 ((uint16_t)0x0000) +#define TIM_TS_ITR1 ((uint16_t)0x0010) +#define TIM_TS_ITR2 ((uint16_t)0x0020) +#define TIM_TS_ITR3 ((uint16_t)0x0030) +#define TIM_TS_TI1F_ED ((uint16_t)0x0040) +#define TIM_TS_TI1FP1 ((uint16_t)0x0050) +#define TIM_TS_TI2FP2 ((uint16_t)0x0060) +#define TIM_TS_ETRF ((uint16_t)0x0070) +#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ + ((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3) || \ + ((SELECTION) == TIM_TS_TI1F_ED) || \ + ((SELECTION) == TIM_TS_TI1FP1) || \ + ((SELECTION) == TIM_TS_TI2FP2) || \ + ((SELECTION) == TIM_TS_ETRF)) +#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ + ((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3)) +/** + * @} + */ + +/** @defgroup TIM_TIx_External_Clock_Source + * @{ + */ + +#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) +#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) +#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) +#define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || \ + ((SOURCE) == TIM_TIxExternalCLK1Source_TI2) || \ + ((SOURCE) == TIM_TIxExternalCLK1Source_TI1ED)) +/** + * @} + */ + +/** @defgroup TIM_External_Trigger_Polarity + * @{ + */ +#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) +#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) +#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \ + ((POLARITY) == TIM_ExtTRGPolarity_NonInverted)) +/** + * @} + */ + +/** @defgroup TIM_Prescaler_Reload_Mode + * @{ + */ + +#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) +#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) +#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \ + ((RELOAD) == TIM_PSCReloadMode_Immediate)) +/** + * @} + */ + +/** @defgroup TIM_Forced_Action + * @{ + */ + +#define TIM_ForcedAction_Active ((uint16_t)0x0050) +#define TIM_ForcedAction_InActive ((uint16_t)0x0040) +#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \ + ((ACTION) == TIM_ForcedAction_InActive)) +/** + * @} + */ + +/** @defgroup TIM_Encoder_Mode + * @{ + */ + +#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) +#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) +#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) +#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \ + ((MODE) == TIM_EncoderMode_TI2) || \ + ((MODE) == TIM_EncoderMode_TI12)) +/** + * @} + */ + + +/** @defgroup TIM_Event_Source + * @{ + */ + +#define TIM_EventSource_Update ((uint16_t)0x0001) +#define TIM_EventSource_CC1 ((uint16_t)0x0002) +#define TIM_EventSource_CC2 ((uint16_t)0x0004) +#define TIM_EventSource_CC3 ((uint16_t)0x0008) +#define TIM_EventSource_CC4 ((uint16_t)0x0010) +#define TIM_EventSource_COM ((uint16_t)0x0020) +#define TIM_EventSource_Trigger ((uint16_t)0x0040) +#define TIM_EventSource_Break ((uint16_t)0x0080) +#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000)) + +/** + * @} + */ + +/** @defgroup TIM_Update_Source + * @{ + */ + +#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow + or the setting of UG bit, or an update generation + through the slave mode controller. */ +#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */ +#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \ + ((SOURCE) == TIM_UpdateSource_Regular)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Preload_State + * @{ + */ + +#define TIM_OCPreload_Enable ((uint16_t)0x0008) +#define TIM_OCPreload_Disable ((uint16_t)0x0000) +#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \ + ((STATE) == TIM_OCPreload_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Fast_State + * @{ + */ + +#define TIM_OCFast_Enable ((uint16_t)0x0004) +#define TIM_OCFast_Disable ((uint16_t)0x0000) +#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \ + ((STATE) == TIM_OCFast_Disable)) + +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Clear_State + * @{ + */ + +#define TIM_OCClear_Enable ((uint16_t)0x0080) +#define TIM_OCClear_Disable ((uint16_t)0x0000) +#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \ + ((STATE) == TIM_OCClear_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Trigger_Output_Source + * @{ + */ + +#define TIM_TRGOSource_Reset ((uint16_t)0x0000) +#define TIM_TRGOSource_Enable ((uint16_t)0x0010) +#define TIM_TRGOSource_Update ((uint16_t)0x0020) +#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) +#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) +#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) +#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) +#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) +#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \ + ((SOURCE) == TIM_TRGOSource_Enable) || \ + ((SOURCE) == TIM_TRGOSource_Update) || \ + ((SOURCE) == TIM_TRGOSource_OC1) || \ + ((SOURCE) == TIM_TRGOSource_OC1Ref) || \ + ((SOURCE) == TIM_TRGOSource_OC2Ref) || \ + ((SOURCE) == TIM_TRGOSource_OC3Ref) || \ + ((SOURCE) == TIM_TRGOSource_OC4Ref)) +/** + * @} + */ + +/** @defgroup TIM_Slave_Mode + * @{ + */ + +#define TIM_SlaveMode_Reset ((uint16_t)0x0004) +#define TIM_SlaveMode_Gated ((uint16_t)0x0005) +#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) +#define TIM_SlaveMode_External1 ((uint16_t)0x0007) +#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \ + ((MODE) == TIM_SlaveMode_Gated) || \ + ((MODE) == TIM_SlaveMode_Trigger) || \ + ((MODE) == TIM_SlaveMode_External1)) +/** + * @} + */ + +/** @defgroup TIM_Master_Slave_Mode + * @{ + */ + +#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) +#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) +#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \ + ((STATE) == TIM_MasterSlaveMode_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Flags + * @{ + */ + +#define TIM_FLAG_Update ((uint16_t)0x0001) +#define TIM_FLAG_CC1 ((uint16_t)0x0002) +#define TIM_FLAG_CC2 ((uint16_t)0x0004) +#define TIM_FLAG_CC3 ((uint16_t)0x0008) +#define TIM_FLAG_CC4 ((uint16_t)0x0010) +#define TIM_FLAG_COM ((uint16_t)0x0020) +#define TIM_FLAG_Trigger ((uint16_t)0x0040) +#define TIM_FLAG_Break ((uint16_t)0x0080) +#define TIM_FLAG_CC1OF ((uint16_t)0x0200) +#define TIM_FLAG_CC2OF ((uint16_t)0x0400) +#define TIM_FLAG_CC3OF ((uint16_t)0x0800) +#define TIM_FLAG_CC4OF ((uint16_t)0x1000) +#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \ + ((FLAG) == TIM_FLAG_CC1) || \ + ((FLAG) == TIM_FLAG_CC2) || \ + ((FLAG) == TIM_FLAG_CC3) || \ + ((FLAG) == TIM_FLAG_CC4) || \ + ((FLAG) == TIM_FLAG_COM) || \ + ((FLAG) == TIM_FLAG_Trigger) || \ + ((FLAG) == TIM_FLAG_Break) || \ + ((FLAG) == TIM_FLAG_CC1OF) || \ + ((FLAG) == TIM_FLAG_CC2OF) || \ + ((FLAG) == TIM_FLAG_CC3OF) || \ + ((FLAG) == TIM_FLAG_CC4OF)) + + +#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Filer_Value + * @{ + */ + +#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) +/** + * @} + */ + +/** @defgroup TIM_External_Trigger_Filter + * @{ + */ + +#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF) +/** + * @} + */ + +/** @defgroup TIM_Legacy + * @{ + */ + +#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer +#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers +#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers +#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers +#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers +#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers +#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers +#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers +#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers +#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers +#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers +#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers +#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers +#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers +#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers +#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers +#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers +#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions + * @{ + */ + +void TIM_DeInit(TIM_TypeDef* TIMx); +void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); +void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); +void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct); +void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState); +void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource); +void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); +void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState); +void TIM_InternalClockConfig(TIM_TypeDef* TIMx); +void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); +void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter); +void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); +void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); +void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode); +void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); +void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); +void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); +void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); +void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); +void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource); +void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode); +void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); +void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); +void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); +void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter); +void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload); +void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1); +void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2); +void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3); +void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4); +void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD); +uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx); +uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx); +uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx); +uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx); +uint16_t TIM_GetCounter(TIM_TypeDef* TIMx); +uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx); +FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); +void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); +ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT); +void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F10x_TIM_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/STM32F10x_FWLIB/inc/stm32f10x_usart.h b/STM32F10x_FWLIB/inc/stm32f10x_usart.h new file mode 100644 index 0000000..24a819c --- /dev/null +++ b/STM32F10x_FWLIB/inc/stm32f10x_usart.h @@ -0,0 +1,421 @@ +/** + ****************************************************************************** + * @file stm32f10x_usart.h + * @author MCD Application Team + * @version V3.6.2 + * @date 17-September-2021 + * @brief This file contains all the functions prototypes for the USART + * firmware library. + ****************************************************************************** + * @attention + * + * Copyright (c) 2012 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_USART_H +#define __STM32F10x_USART_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup USART + * @{ + */ + +/** @defgroup USART_Exported_Types + * @{ + */ + +/** + * @brief USART Init Structure definition + */ + +typedef struct +{ + uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate. + The baud rate is computed using the following formula: + - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate))) + - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */ + + uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USART_Word_Length */ + + uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_Stop_Bits */ + + uint16_t USART_Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref USART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_Mode */ + + uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref USART_Hardware_Flow_Control */ +} USART_InitTypeDef; + +/** + * @brief USART Clock Init Structure definition + */ + +typedef struct +{ + + uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled. + This parameter can be a value of @ref USART_Clock */ + + uint16_t USART_CPOL; /*!< Specifies the steady state value of the serial clock. + This parameter can be a value of @ref USART_Clock_Polarity */ + + uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_Clock_Phase */ + + uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_Last_Bit */ +} USART_ClockInitTypeDef; + +/** + * @} + */ + +/** @defgroup USART_Exported_Constants + * @{ + */ + +#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \ + ((PERIPH) == USART2) || \ + ((PERIPH) == USART3) || \ + ((PERIPH) == UART4) || \ + ((PERIPH) == UART5)) + +#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \ + ((PERIPH) == USART2) || \ + ((PERIPH) == USART3)) + +#define IS_USART_1234_PERIPH(PERIPH) (((PERIPH) == USART1) || \ + ((PERIPH) == USART2) || \ + ((PERIPH) == USART3) || \ + ((PERIPH) == UART4)) +/** @defgroup USART_Word_Length + * @{ + */ + +#define USART_WordLength_8b ((uint16_t)0x0000) +#define USART_WordLength_9b ((uint16_t)0x1000) + +#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \ + ((LENGTH) == USART_WordLength_9b)) +/** + * @} + */ + +/** @defgroup USART_Stop_Bits + * @{ + */ + +#define USART_StopBits_1 ((uint16_t)0x0000) +#define USART_StopBits_0_5 ((uint16_t)0x1000) +#define USART_StopBits_2 ((uint16_t)0x2000) +#define USART_StopBits_1_5 ((uint16_t)0x3000) +#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \ + ((STOPBITS) == USART_StopBits_0_5) || \ + ((STOPBITS) == USART_StopBits_2) || \ + ((STOPBITS) == USART_StopBits_1_5)) +/** + * @} + */ + +/** @defgroup USART_Parity + * @{ + */ + +#define USART_Parity_No ((uint16_t)0x0000) +#define USART_Parity_Even ((uint16_t)0x0400) +#define USART_Parity_Odd ((uint16_t)0x0600) +#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \ + ((PARITY) == USART_Parity_Even) || \ + ((PARITY) == USART_Parity_Odd)) +/** + * @} + */ + +/** @defgroup USART_Mode + * @{ + */ + +#define USART_Mode_Rx ((uint16_t)0x0004) +#define USART_Mode_Tx ((uint16_t)0x0008) +#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00)) +/** + * @} + */ + +/** @defgroup USART_Hardware_Flow_Control + * @{ + */ +#define USART_HardwareFlowControl_None ((uint16_t)0x0000) +#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) +#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) +#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) +#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\ + (((CONTROL) == USART_HardwareFlowControl_None) || \ + ((CONTROL) == USART_HardwareFlowControl_RTS) || \ + ((CONTROL) == USART_HardwareFlowControl_CTS) || \ + ((CONTROL) == USART_HardwareFlowControl_RTS_CTS)) +/** + * @} + */ + +/** @defgroup USART_Clock + * @{ + */ +#define USART_Clock_Disable ((uint16_t)0x0000) +#define USART_Clock_Enable ((uint16_t)0x0800) +#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \ + ((CLOCK) == USART_Clock_Enable)) +/** + * @} + */ + +/** @defgroup USART_Clock_Polarity + * @{ + */ + +#define USART_CPOL_Low ((uint16_t)0x0000) +#define USART_CPOL_High ((uint16_t)0x0400) +#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High)) + +/** + * @} + */ + +/** @defgroup USART_Clock_Phase + * @{ + */ + +#define USART_CPHA_1Edge ((uint16_t)0x0000) +#define USART_CPHA_2Edge ((uint16_t)0x0200) +#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge)) + +/** + * @} + */ + +/** @defgroup USART_Last_Bit + * @{ + */ + +#define USART_LastBit_Disable ((uint16_t)0x0000) +#define USART_LastBit_Enable ((uint16_t)0x0100) +#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \ + ((LASTBIT) == USART_LastBit_Enable)) +/** + * @} + */ + +/** @defgroup USART_Interrupt_definition + * @{ + */ + +#define USART_IT_PE ((uint16_t)0x0028) +#define USART_IT_TXE ((uint16_t)0x0727) +#define USART_IT_TC ((uint16_t)0x0626) +#define USART_IT_RXNE ((uint16_t)0x0525) +#define USART_IT_ORE_RX ((uint16_t)0x0325) /* In case interrupt is generated if the RXNEIE bit is set */ +#define USART_IT_IDLE ((uint16_t)0x0424) +#define USART_IT_LBD ((uint16_t)0x0846) +#define USART_IT_CTS ((uint16_t)0x096A) +#define USART_IT_ERR ((uint16_t)0x0060) +#define USART_IT_ORE_ER ((uint16_t)0x0360) /* In case interrupt is generated if the EIE bit is set */ +#define USART_IT_NE ((uint16_t)0x0260) +#define USART_IT_FE ((uint16_t)0x0160) + +/** @defgroup USART_Legacy + * @{ + */ +#define USART_IT_ORE USART_IT_ORE_ER +/** + * @} + */ + +#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ + ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ + ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ + ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR)) + +#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ + ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ + ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ + ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \ + ((IT) == USART_IT_ORE_RX) || ((IT) == USART_IT_ORE_ER) || \ + ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE)) + +#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ + ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS)) +/** + * @} + */ + +/** @defgroup USART_DMA_Requests + * @{ + */ + +#define USART_DMAReq_Tx ((uint16_t)0x0080) +#define USART_DMAReq_Rx ((uint16_t)0x0040) +#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00)) + +/** + * @} + */ + +/** @defgroup USART_WakeUp_methods + * @{ + */ + +#define USART_WakeUp_IdleLine ((uint16_t)0x0000) +#define USART_WakeUp_AddressMark ((uint16_t)0x0800) +#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \ + ((WAKEUP) == USART_WakeUp_AddressMark)) +/** + * @} + */ + +/** @defgroup USART_LIN_Break_Detection_Length + * @{ + */ + +#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) +#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) +#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \ + (((LENGTH) == USART_LINBreakDetectLength_10b) || \ + ((LENGTH) == USART_LINBreakDetectLength_11b)) +/** + * @} + */ + +/** @defgroup USART_IrDA_Low_Power + * @{ + */ + +#define USART_IrDAMode_LowPower ((uint16_t)0x0004) +#define USART_IrDAMode_Normal ((uint16_t)0x0000) +#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \ + ((MODE) == USART_IrDAMode_Normal)) +/** + * @} + */ + +/** @defgroup USART_Flags + * @{ + */ + +#define USART_FLAG_CTS ((uint16_t)0x0200) +#define USART_FLAG_LBD ((uint16_t)0x0100) +#define USART_FLAG_TXE ((uint16_t)0x0080) +#define USART_FLAG_TC ((uint16_t)0x0040) +#define USART_FLAG_RXNE ((uint16_t)0x0020) +#define USART_FLAG_IDLE ((uint16_t)0x0010) +#define USART_FLAG_ORE ((uint16_t)0x0008) +#define USART_FLAG_NE ((uint16_t)0x0004) +#define USART_FLAG_FE ((uint16_t)0x0002) +#define USART_FLAG_PE ((uint16_t)0x0001) +#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \ + ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \ + ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \ + ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \ + ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE)) + +#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00)) + +#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21)) +#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF) +#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup USART_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup USART_Exported_Functions + * @{ + */ + +void USART_DeInit(USART_TypeDef* USARTx); +void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct); +void USART_StructInit(USART_InitTypeDef* USART_InitStruct); +void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct); +void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct); +void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); +void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); +void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address); +void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp); +void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength); +void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_SendData(USART_TypeDef* USARTx, uint16_t Data); +uint16_t USART_ReceiveData(USART_TypeDef* USARTx); +void USART_SendBreak(USART_TypeDef* USARTx); +void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime); +void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler); +void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode); +void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState); +FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); +void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); +ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); +void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_USART_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/STM32F10x_FWLIB/inc/stm32f10x_wwdg.h b/STM32F10x_FWLIB/inc/stm32f10x_wwdg.h new file mode 100644 index 0000000..0c1a951 --- /dev/null +++ b/STM32F10x_FWLIB/inc/stm32f10x_wwdg.h @@ -0,0 +1,113 @@ +/** + ****************************************************************************** + * @file stm32f10x_wwdg.h + * @author MCD Application Team + * @version V3.6.2 + * @date 17-September-2021 + * @brief This file contains all the functions prototypes for the WWDG firmware + * library. + ****************************************************************************** + * @attention + * + * Copyright (c) 2012 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_WWDG_H +#define __STM32F10x_WWDG_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup WWDG + * @{ + */ + +/** @defgroup WWDG_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup WWDG_Exported_Constants + * @{ + */ + +/** @defgroup WWDG_Prescaler + * @{ + */ + +#define WWDG_Prescaler_1 ((uint32_t)0x00000000) +#define WWDG_Prescaler_2 ((uint32_t)0x00000080) +#define WWDG_Prescaler_4 ((uint32_t)0x00000100) +#define WWDG_Prescaler_8 ((uint32_t)0x00000180) +#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \ + ((PRESCALER) == WWDG_Prescaler_2) || \ + ((PRESCALER) == WWDG_Prescaler_4) || \ + ((PRESCALER) == WWDG_Prescaler_8)) +#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F) +#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F)) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup WWDG_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup WWDG_Exported_Functions + * @{ + */ + +void WWDG_DeInit(void); +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); +void WWDG_SetWindowValue(uint8_t WindowValue); +void WWDG_EnableIT(void); +void WWDG_SetCounter(uint8_t Counter); +void WWDG_Enable(uint8_t Counter); +FlagStatus WWDG_GetFlagStatus(void); +void WWDG_ClearFlag(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_WWDG_H */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/STM32F10x_FWLIB/src/misc.c b/STM32F10x_FWLIB/src/misc.c new file mode 100644 index 0000000..2b9e2ea --- /dev/null +++ b/STM32F10x_FWLIB/src/misc.c @@ -0,0 +1,223 @@ +/** + ****************************************************************************** + * @file misc.c + * @author MCD Application Team + * @version V3.6.2 + * @date 17-September-2021 + * @brief This file provides all the miscellaneous firmware functions (add-on + * to CMSIS functions). + ****************************************************************************** + * @attention + * + * Copyright (c) 2012 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "misc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup MISC + * @brief MISC driver modules + * @{ + */ + +/** @defgroup MISC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Private_Defines + * @{ + */ + +#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) +/** + * @} + */ + +/** @defgroup MISC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Private_Functions + * @{ + */ + +/** + * @brief Configures the priority grouping: pre-emption priority and subpriority. + * @param NVIC_PriorityGroup: specifies the priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority + * 4 bits for subpriority + * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority + * 3 bits for subpriority + * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority + * 2 bits for subpriority + * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority + * 1 bits for subpriority + * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority + * 0 bits for subpriority + * @retval None + */ +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ + SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; +} + +/** + * @brief Initializes the NVIC peripheral according to the specified + * parameters in the NVIC_InitStruct. + * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains + * the configuration information for the specified NVIC peripheral. + * @retval None + */ +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) +{ + uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); + assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); + + if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) + { + /* Compute the Corresponding IRQ Priority --------------------------------*/ + tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08; + tmppre = (0x4 - tmppriority); + tmpsub = tmpsub >> tmppriority; + + tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; + tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub; + tmppriority = tmppriority << 0x04; + + NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority; + + /* Enable the Selected IRQ Channels --------------------------------------*/ + NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = + (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); + } + else + { + /* Disable the Selected IRQ Channels -------------------------------------*/ + NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = + (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); + } +} + +/** + * @brief Sets the vector table location and Offset. + * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory. + * This parameter can be one of the following values: + * @arg NVIC_VectTab_RAM + * @arg NVIC_VectTab_FLASH + * @param Offset: Vector Table base offset field. This value must be a multiple + * of 0x200. + * @retval None + */ +void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset) +{ + /* Check the parameters */ + assert_param(IS_NVIC_VECTTAB(NVIC_VectTab)); + assert_param(IS_NVIC_OFFSET(Offset)); + + SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); +} + +/** + * @brief Selects the condition for the system to enter low power mode. + * @param LowPowerMode: Specifies the new mode for the system to enter low power mode. + * This parameter can be one of the following values: + * @arg NVIC_LP_SEVONPEND + * @arg NVIC_LP_SLEEPDEEP + * @arg NVIC_LP_SLEEPONEXIT + * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_NVIC_LP(LowPowerMode)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + SCB->SCR |= LowPowerMode; + } + else + { + SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); + } +} + +/** + * @brief Configures the SysTick clock source. + * @param SysTick_CLKSource: specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source. + * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source. + * @retval None + */ +void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); + if (SysTick_CLKSource == SysTick_CLKSource_HCLK) + { + SysTick->CTRL |= SysTick_CLKSource_HCLK; + } + else + { + SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/STM32F10x_FWLIB/src/stm32f10x_adc.c b/STM32F10x_FWLIB/src/stm32f10x_adc.c new file mode 100644 index 0000000..5e814d4 --- /dev/null +++ b/STM32F10x_FWLIB/src/stm32f10x_adc.c @@ -0,0 +1,1305 @@ +/** + ****************************************************************************** + * @file stm32f10x_adc.c + * @author MCD Application Team + * @version V3.6.2 + * @date 17-September-2021 + * @brief This file provides all the ADC firmware functions. + ****************************************************************************** + * @attention + * + * Copyright (c) 2012 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_adc.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup ADC + * @brief ADC driver modules + * @{ + */ + +/** @defgroup ADC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup ADC_Private_Defines + * @{ + */ + +/* ADC DISCNUM mask */ +#define CR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF) + +/* ADC DISCEN mask */ +#define CR1_DISCEN_Set ((uint32_t)0x00000800) +#define CR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF) + +/* ADC JAUTO mask */ +#define CR1_JAUTO_Set ((uint32_t)0x00000400) +#define CR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF) + +/* ADC JDISCEN mask */ +#define CR1_JDISCEN_Set ((uint32_t)0x00001000) +#define CR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF) + +/* ADC AWDCH mask */ +#define CR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0) + +/* ADC Analog watchdog enable mode mask */ +#define CR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF) + +/* CR1 register Mask */ +#define CR1_CLEAR_Mask ((uint32_t)0xFFF0FEFF) + +/* ADC ADON mask */ +#define CR2_ADON_Set ((uint32_t)0x00000001) +#define CR2_ADON_Reset ((uint32_t)0xFFFFFFFE) + +/* ADC DMA mask */ +#define CR2_DMA_Set ((uint32_t)0x00000100) +#define CR2_DMA_Reset ((uint32_t)0xFFFFFEFF) + +/* ADC RSTCAL mask */ +#define CR2_RSTCAL_Set ((uint32_t)0x00000008) + +/* ADC CAL mask */ +#define CR2_CAL_Set ((uint32_t)0x00000004) + +/* ADC SWSTART mask */ +#define CR2_SWSTART_Set ((uint32_t)0x00400000) + +/* ADC EXTTRIG mask */ +#define CR2_EXTTRIG_Set ((uint32_t)0x00100000) +#define CR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF) + +/* ADC Software start mask */ +#define CR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000) +#define CR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF) + +/* ADC JEXTSEL mask */ +#define CR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF) + +/* ADC JEXTTRIG mask */ +#define CR2_JEXTTRIG_Set ((uint32_t)0x00008000) +#define CR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF) + +/* ADC JSWSTART mask */ +#define CR2_JSWSTART_Set ((uint32_t)0x00200000) + +/* ADC injected software start mask */ +#define CR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000) +#define CR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF) + +/* ADC TSPD mask */ +#define CR2_TSVREFE_Set ((uint32_t)0x00800000) +#define CR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF) + +/* CR2 register Mask */ +#define CR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD) + +/* ADC SQx mask */ +#define SQR3_SQ_Set ((uint32_t)0x0000001F) +#define SQR2_SQ_Set ((uint32_t)0x0000001F) +#define SQR1_SQ_Set ((uint32_t)0x0000001F) + +/* SQR1 register Mask */ +#define SQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF) + +/* ADC JSQx mask */ +#define JSQR_JSQ_Set ((uint32_t)0x0000001F) + +/* ADC JL mask */ +#define JSQR_JL_Set ((uint32_t)0x00300000) +#define JSQR_JL_Reset ((uint32_t)0xFFCFFFFF) + +/* ADC SMPx mask */ +#define SMPR1_SMP_Set ((uint32_t)0x00000007) +#define SMPR2_SMP_Set ((uint32_t)0x00000007) + +/* ADC JDRx registers offset */ +#define JDR_Offset ((uint8_t)0x28) + +/* ADC1 DR register base address */ +#define DR_ADDRESS ((uint32_t)0x4001244C) + +/** + * @} + */ + +/** @defgroup ADC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup ADC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup ADC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup ADC_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the ADCx peripheral registers to their default reset values. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval None + */ +void ADC_DeInit(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + if (ADCx == ADC1) + { + /* Enable ADC1 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE); + /* Release ADC1 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE); + } + else if (ADCx == ADC2) + { + /* Enable ADC2 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE); + /* Release ADC2 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE); + } + else + { + if (ADCx == ADC3) + { + /* Enable ADC3 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, ENABLE); + /* Release ADC3 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, DISABLE); + } + } +} + +/** + * @brief Initializes the ADCx peripheral according to the specified parameters + * in the ADC_InitStruct. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains + * the configuration information for the specified ADC peripheral. + * @retval None + */ +void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct) +{ + uint32_t tmpreg1 = 0; + uint8_t tmpreg2 = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_MODE(ADC_InitStruct->ADC_Mode)); + assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode)); + assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode)); + assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv)); + assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); + assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfChannel)); + + /*---------------------------- ADCx CR1 Configuration -----------------*/ + /* Get the ADCx CR1 value */ + tmpreg1 = ADCx->CR1; + /* Clear DUALMOD and SCAN bits */ + tmpreg1 &= CR1_CLEAR_Mask; + /* Configure ADCx: Dual mode and scan conversion mode */ + /* Set DUALMOD bits according to ADC_Mode value */ + /* Set SCAN bit according to ADC_ScanConvMode value */ + tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8)); + /* Write to ADCx CR1 */ + ADCx->CR1 = tmpreg1; + + /*---------------------------- ADCx CR2 Configuration -----------------*/ + /* Get the ADCx CR2 value */ + tmpreg1 = ADCx->CR2; + /* Clear CONT, ALIGN and EXTSEL bits */ + tmpreg1 &= CR2_CLEAR_Mask; + /* Configure ADCx: external trigger event and continuous conversion mode */ + /* Set ALIGN bit according to ADC_DataAlign value */ + /* Set EXTSEL bits according to ADC_ExternalTrigConv value */ + /* Set CONT bit according to ADC_ContinuousConvMode value */ + tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | + ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); + /* Write to ADCx CR2 */ + ADCx->CR2 = tmpreg1; + + /*---------------------------- ADCx SQR1 Configuration -----------------*/ + /* Get the ADCx SQR1 value */ + tmpreg1 = ADCx->SQR1; + /* Clear L bits */ + tmpreg1 &= SQR1_CLEAR_Mask; + /* Configure ADCx: regular channel sequence length */ + /* Set L bits according to ADC_NbrOfChannel value */ + tmpreg2 |= (uint8_t) (ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1); + tmpreg1 |= (uint32_t)tmpreg2 << 20; + /* Write to ADCx SQR1 */ + ADCx->SQR1 = tmpreg1; +} + +/** + * @brief Fills each ADC_InitStruct member with its default value. + * @param ADC_InitStruct : pointer to an ADC_InitTypeDef structure which will be initialized. + * @retval None + */ +void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) +{ + /* Reset ADC init structure parameters values */ + /* Initialize the ADC_Mode member */ + ADC_InitStruct->ADC_Mode = ADC_Mode_Independent; + /* initialize the ADC_ScanConvMode member */ + ADC_InitStruct->ADC_ScanConvMode = DISABLE; + /* Initialize the ADC_ContinuousConvMode member */ + ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; + /* Initialize the ADC_ExternalTrigConv member */ + ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; + /* Initialize the ADC_DataAlign member */ + ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; + /* Initialize the ADC_NbrOfChannel member */ + ADC_InitStruct->ADC_NbrOfChannel = 1; +} + +/** + * @brief Enables or disables the specified ADC peripheral. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the ADCx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the ADON bit to wake up the ADC from power down mode */ + ADCx->CR2 |= CR2_ADON_Set; + } + else + { + /* Disable the selected ADC peripheral */ + ADCx->CR2 &= CR2_ADON_Reset; + } +} + +/** + * @brief Enables or disables the specified ADC DMA request. + * @param ADCx: where x can be 1 or 3 to select the ADC peripheral. + * Note: ADC2 hasn't a DMA capability. + * @param NewState: new state of the selected ADC DMA transfer. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_DMA_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC DMA request */ + ADCx->CR2 |= CR2_DMA_Set; + } + else + { + /* Disable the selected ADC DMA request */ + ADCx->CR2 &= CR2_DMA_Reset; + } +} + +/** + * @brief Enables or disables the specified ADC interrupts. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg ADC_IT_EOC: End of conversion interrupt mask + * @arg ADC_IT_AWD: Analog watchdog interrupt mask + * @arg ADC_IT_JEOC: End of injected conversion interrupt mask + * @param NewState: new state of the specified ADC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState) +{ + uint8_t itmask = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_ADC_IT(ADC_IT)); + /* Get the ADC IT index */ + itmask = (uint8_t)ADC_IT; + if (NewState != DISABLE) + { + /* Enable the selected ADC interrupts */ + ADCx->CR1 |= itmask; + } + else + { + /* Disable the selected ADC interrupts */ + ADCx->CR1 &= (~(uint32_t)itmask); + } +} + +/** + * @brief Resets the selected ADC calibration registers. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval None + */ +void ADC_ResetCalibration(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Resets the selected ADC calibration registers */ + ADCx->CR2 |= CR2_RSTCAL_Set; +} + +/** + * @brief Gets the selected ADC reset calibration registers status. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval The new state of ADC reset calibration registers (SET or RESET). + */ +FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Check the status of RSTCAL bit */ + if ((ADCx->CR2 & CR2_RSTCAL_Set) != (uint32_t)RESET) + { + /* RSTCAL bit is set */ + bitstatus = SET; + } + else + { + /* RSTCAL bit is reset */ + bitstatus = RESET; + } + /* Return the RSTCAL bit status */ + return bitstatus; +} + +/** + * @brief Starts the selected ADC calibration process. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval None + */ +void ADC_StartCalibration(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Enable the selected ADC calibration process */ + ADCx->CR2 |= CR2_CAL_Set; +} + +/** + * @brief Gets the selected ADC calibration status. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval The new state of ADC calibration (SET or RESET). + */ +FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Check the status of CAL bit */ + if ((ADCx->CR2 & CR2_CAL_Set) != (uint32_t)RESET) + { + /* CAL bit is set: calibration on going */ + bitstatus = SET; + } + else + { + /* CAL bit is reset: end of calibration */ + bitstatus = RESET; + } + /* Return the CAL bit status */ + return bitstatus; +} + +/** + * @brief Enables or disables the selected ADC software start conversion . + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC software start conversion. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC conversion on external event and start the selected + ADC conversion */ + ADCx->CR2 |= CR2_EXTTRIG_SWSTART_Set; + } + else + { + /* Disable the selected ADC conversion on external event and stop the selected + ADC conversion */ + ADCx->CR2 &= CR2_EXTTRIG_SWSTART_Reset; + } +} + +/** + * @brief Gets the selected ADC Software start conversion Status. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval The new state of ADC software start conversion (SET or RESET). + */ +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Check the status of SWSTART bit */ + if ((ADCx->CR2 & CR2_SWSTART_Set) != (uint32_t)RESET) + { + /* SWSTART bit is set */ + bitstatus = SET; + } + else + { + /* SWSTART bit is reset */ + bitstatus = RESET; + } + /* Return the SWSTART bit status */ + return bitstatus; +} + +/** + * @brief Configures the discontinuous mode for the selected ADC regular + * group channel. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param Number: specifies the discontinuous mode regular channel + * count value. This number must be between 1 and 8. + * @retval None + */ +void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number)); + /* Get the old register value */ + tmpreg1 = ADCx->CR1; + /* Clear the old discontinuous mode channel count */ + tmpreg1 &= CR1_DISCNUM_Reset; + /* Set the discontinuous mode channel count */ + tmpreg2 = Number - 1; + tmpreg1 |= tmpreg2 << 13; + /* Store the new register value */ + ADCx->CR1 = tmpreg1; +} + +/** + * @brief Enables or disables the discontinuous mode on regular group + * channel for the specified ADC + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC discontinuous mode + * on regular group channel. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC regular discontinuous mode */ + ADCx->CR1 |= CR1_DISCEN_Set; + } + else + { + /* Disable the selected ADC regular discontinuous mode */ + ADCx->CR1 &= CR1_DISCEN_Reset; + } +} + +/** + * @brief Configures for the selected ADC regular channel its corresponding + * rank in the sequencer and its sample time. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_Channel: the ADC channel to configure. + * This parameter can be one of the following values: + * @arg ADC_Channel_0: ADC Channel0 selected + * @arg ADC_Channel_1: ADC Channel1 selected + * @arg ADC_Channel_2: ADC Channel2 selected + * @arg ADC_Channel_3: ADC Channel3 selected + * @arg ADC_Channel_4: ADC Channel4 selected + * @arg ADC_Channel_5: ADC Channel5 selected + * @arg ADC_Channel_6: ADC Channel6 selected + * @arg ADC_Channel_7: ADC Channel7 selected + * @arg ADC_Channel_8: ADC Channel8 selected + * @arg ADC_Channel_9: ADC Channel9 selected + * @arg ADC_Channel_10: ADC Channel10 selected + * @arg ADC_Channel_11: ADC Channel11 selected + * @arg ADC_Channel_12: ADC Channel12 selected + * @arg ADC_Channel_13: ADC Channel13 selected + * @arg ADC_Channel_14: ADC Channel14 selected + * @arg ADC_Channel_15: ADC Channel15 selected + * @arg ADC_Channel_16: ADC Channel16 selected + * @arg ADC_Channel_17: ADC Channel17 selected + * @param Rank: The rank in the regular group sequencer. This parameter must be between 1 to 16. + * @param ADC_SampleTime: The sample time value to be set for the selected channel. + * This parameter can be one of the following values: + * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles + * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles + * @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles + * @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles + * @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles + * @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles + * @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles + * @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles + * @retval None + */ +void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CHANNEL(ADC_Channel)); + assert_param(IS_ADC_REGULAR_RANK(Rank)); + assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); + /* if ADC_Channel_10 ... ADC_Channel_17 is selected */ + if (ADC_Channel > ADC_Channel_9) + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR1; + /* Calculate the mask to clear */ + tmpreg2 = SMPR1_SMP_Set << (3 * (ADC_Channel - 10)); + /* Clear the old channel sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); + /* Set the new channel sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SMPR1 = tmpreg1; + } + else /* ADC_Channel include in ADC_Channel_[0..9] */ + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR2; + /* Calculate the mask to clear */ + tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel); + /* Clear the old channel sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + /* Set the new channel sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SMPR2 = tmpreg1; + } + /* For Rank 1 to 6 */ + if (Rank < 7) + { + /* Get the old register value */ + tmpreg1 = ADCx->SQR3; + /* Calculate the mask to clear */ + tmpreg2 = SQR3_SQ_Set << (5 * (Rank - 1)); + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SQR3 = tmpreg1; + } + /* For Rank 7 to 12 */ + else if (Rank < 13) + { + /* Get the old register value */ + tmpreg1 = ADCx->SQR2; + /* Calculate the mask to clear */ + tmpreg2 = SQR2_SQ_Set << (5 * (Rank - 7)); + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SQR2 = tmpreg1; + } + /* For Rank 13 to 16 */ + else + { + /* Get the old register value */ + tmpreg1 = ADCx->SQR1; + /* Calculate the mask to clear */ + tmpreg2 = SQR1_SQ_Set << (5 * (Rank - 13)); + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SQR1 = tmpreg1; + } +} + +/** + * @brief Enables or disables the ADCx conversion through external trigger. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC external trigger start of conversion. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC conversion on external event */ + ADCx->CR2 |= CR2_EXTTRIG_Set; + } + else + { + /* Disable the selected ADC conversion on external event */ + ADCx->CR2 &= CR2_EXTTRIG_Reset; + } +} + +/** + * @brief Returns the last ADCx conversion result data for regular channel. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval The Data conversion value. + */ +uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Return the selected ADC conversion value */ + return (uint16_t) ADCx->DR; +} + +/** + * @brief Returns the last ADC1 and ADC2 conversion result data in dual mode. + * @retval The Data conversion value. + */ +uint32_t ADC_GetDualModeConversionValue(void) +{ + /* Return the dual mode conversion value */ + return (*(__IO uint32_t *) DR_ADDRESS); +} + +/** + * @brief Enables or disables the selected ADC automatic injected group + * conversion after regular one. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC auto injected conversion + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC automatic injected group conversion */ + ADCx->CR1 |= CR1_JAUTO_Set; + } + else + { + /* Disable the selected ADC automatic injected group conversion */ + ADCx->CR1 &= CR1_JAUTO_Reset; + } +} + +/** + * @brief Enables or disables the discontinuous mode for injected group + * channel for the specified ADC + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC discontinuous mode + * on injected group channel. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC injected discontinuous mode */ + ADCx->CR1 |= CR1_JDISCEN_Set; + } + else + { + /* Disable the selected ADC injected discontinuous mode */ + ADCx->CR1 &= CR1_JDISCEN_Reset; + } +} + +/** + * @brief Configures the ADCx external trigger for injected channels conversion. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion. + * This parameter can be one of the following values: + * @arg ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected (for ADC1, ADC2 and ADC3) + * @arg ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected (for ADC1, ADC2 and ADC3) + * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected (for ADC1 and ADC2) + * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected (for ADC1 and ADC2) + * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected (for ADC1 and ADC2) + * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected (for ADC1 and ADC2) + * @arg ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4: External interrupt line 15 or Timer8 + * capture compare4 event selected (for ADC1 and ADC2) + * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected (for ADC3 only) + * @arg ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected (for ADC3 only) + * @arg ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected (for ADC3 only) + * @arg ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected (for ADC3 only) + * @arg ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected (for ADC3 only) + * @arg ADC_ExternalTrigInjecConv_None: Injected conversion started by software and not + * by external trigger (for ADC1, ADC2 and ADC3) + * @retval None + */ +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv)); + /* Get the old register value */ + tmpreg = ADCx->CR2; + /* Clear the old external event selection for injected group */ + tmpreg &= CR2_JEXTSEL_Reset; + /* Set the external event selection for injected group */ + tmpreg |= ADC_ExternalTrigInjecConv; + /* Store the new register value */ + ADCx->CR2 = tmpreg; +} + +/** + * @brief Enables or disables the ADCx injected channels conversion through + * external trigger + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC external trigger start of + * injected conversion. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC external event selection for injected group */ + ADCx->CR2 |= CR2_JEXTTRIG_Set; + } + else + { + /* Disable the selected ADC external event selection for injected group */ + ADCx->CR2 &= CR2_JEXTTRIG_Reset; + } +} + +/** + * @brief Enables or disables the selected ADC start of the injected + * channels conversion. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC software start injected conversion. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC conversion for injected group on external event and start the selected + ADC injected conversion */ + ADCx->CR2 |= CR2_JEXTTRIG_JSWSTART_Set; + } + else + { + /* Disable the selected ADC conversion on external event for injected group and stop the selected + ADC injected conversion */ + ADCx->CR2 &= CR2_JEXTTRIG_JSWSTART_Reset; + } +} + +/** + * @brief Gets the selected ADC Software start injected conversion Status. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval The new state of ADC software start injected conversion (SET or RESET). + */ +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Check the status of JSWSTART bit */ + if ((ADCx->CR2 & CR2_JSWSTART_Set) != (uint32_t)RESET) + { + /* JSWSTART bit is set */ + bitstatus = SET; + } + else + { + /* JSWSTART bit is reset */ + bitstatus = RESET; + } + /* Return the JSWSTART bit status */ + return bitstatus; +} + +/** + * @brief Configures for the selected ADC injected channel its corresponding + * rank in the sequencer and its sample time. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_Channel: the ADC channel to configure. + * This parameter can be one of the following values: + * @arg ADC_Channel_0: ADC Channel0 selected + * @arg ADC_Channel_1: ADC Channel1 selected + * @arg ADC_Channel_2: ADC Channel2 selected + * @arg ADC_Channel_3: ADC Channel3 selected + * @arg ADC_Channel_4: ADC Channel4 selected + * @arg ADC_Channel_5: ADC Channel5 selected + * @arg ADC_Channel_6: ADC Channel6 selected + * @arg ADC_Channel_7: ADC Channel7 selected + * @arg ADC_Channel_8: ADC Channel8 selected + * @arg ADC_Channel_9: ADC Channel9 selected + * @arg ADC_Channel_10: ADC Channel10 selected + * @arg ADC_Channel_11: ADC Channel11 selected + * @arg ADC_Channel_12: ADC Channel12 selected + * @arg ADC_Channel_13: ADC Channel13 selected + * @arg ADC_Channel_14: ADC Channel14 selected + * @arg ADC_Channel_15: ADC Channel15 selected + * @arg ADC_Channel_16: ADC Channel16 selected + * @arg ADC_Channel_17: ADC Channel17 selected + * @param Rank: The rank in the injected group sequencer. This parameter must be between 1 and 4. + * @param ADC_SampleTime: The sample time value to be set for the selected channel. + * This parameter can be one of the following values: + * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles + * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles + * @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles + * @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles + * @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles + * @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles + * @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles + * @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles + * @retval None + */ +void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CHANNEL(ADC_Channel)); + assert_param(IS_ADC_INJECTED_RANK(Rank)); + assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); + /* if ADC_Channel_10 ... ADC_Channel_17 is selected */ + if (ADC_Channel > ADC_Channel_9) + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR1; + /* Calculate the mask to clear */ + tmpreg2 = SMPR1_SMP_Set << (3*(ADC_Channel - 10)); + /* Clear the old channel sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10)); + /* Set the new channel sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SMPR1 = tmpreg1; + } + else /* ADC_Channel include in ADC_Channel_[0..9] */ + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR2; + /* Calculate the mask to clear */ + tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel); + /* Clear the old channel sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + /* Set the new channel sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SMPR2 = tmpreg1; + } + /* Rank configuration */ + /* Get the old register value */ + tmpreg1 = ADCx->JSQR; + /* Get JL value: Number = JL+1 */ + tmpreg3 = (tmpreg1 & JSQR_JL_Set)>> 20; + /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */ + tmpreg2 = JSQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + /* Clear the old JSQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + /* Set the JSQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->JSQR = tmpreg1; +} + +/** + * @brief Configures the sequencer length for injected channels + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param Length: The sequencer length. + * This parameter must be a number between 1 to 4. + * @retval None + */ +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_INJECTED_LENGTH(Length)); + + /* Get the old register value */ + tmpreg1 = ADCx->JSQR; + /* Clear the old injected sequnence lenght JL bits */ + tmpreg1 &= JSQR_JL_Reset; + /* Set the injected sequnence lenght JL bits */ + tmpreg2 = Length - 1; + tmpreg1 |= tmpreg2 << 20; + /* Store the new register value */ + ADCx->JSQR = tmpreg1; +} + +/** + * @brief Set the injected channels conversion value offset + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_InjectedChannel: the ADC injected channel to set its offset. + * This parameter can be one of the following values: + * @arg ADC_InjectedChannel_1: Injected Channel1 selected + * @arg ADC_InjectedChannel_2: Injected Channel2 selected + * @arg ADC_InjectedChannel_3: Injected Channel3 selected + * @arg ADC_InjectedChannel_4: Injected Channel4 selected + * @param Offset: the offset value for the selected ADC injected channel + * This parameter must be a 12bit value. + * @retval None + */ +void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); + assert_param(IS_ADC_OFFSET(Offset)); + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel; + + /* Set the selected injected channel data offset */ + *(__IO uint32_t *) tmp = (uint32_t)Offset; +} + +/** + * @brief Returns the ADC injected channel conversion result + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_InjectedChannel: the converted ADC injected channel. + * This parameter can be one of the following values: + * @arg ADC_InjectedChannel_1: Injected Channel1 selected + * @arg ADC_InjectedChannel_2: Injected Channel2 selected + * @arg ADC_InjectedChannel_3: Injected Channel3 selected + * @arg ADC_InjectedChannel_4: Injected Channel4 selected + * @retval The Data conversion value. + */ +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel + JDR_Offset; + + /* Returns the selected injected channel conversion data value */ + return (uint16_t) (*(__IO uint32_t*) tmp); +} + +/** + * @brief Enables or disables the analog watchdog on single/all regular + * or injected channels + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration. + * This parameter can be one of the following values: + * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel + * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel + * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel + * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel + * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel + * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels + * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog + * @retval None + */ +void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog)); + /* Get the old register value */ + tmpreg = ADCx->CR1; + /* Clear AWDEN, AWDENJ and AWDSGL bits */ + tmpreg &= CR1_AWDMode_Reset; + /* Set the analog watchdog enable mode */ + tmpreg |= ADC_AnalogWatchdog; + /* Store the new register value */ + ADCx->CR1 = tmpreg; +} + +/** + * @brief Configures the high and low thresholds of the analog watchdog. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param HighThreshold: the ADC analog watchdog High threshold value. + * This parameter must be a 12bit value. + * @param LowThreshold: the ADC analog watchdog Low threshold value. + * This parameter must be a 12bit value. + * @retval None + */ +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, + uint16_t LowThreshold) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_THRESHOLD(HighThreshold)); + assert_param(IS_ADC_THRESHOLD(LowThreshold)); + /* Set the ADCx high threshold */ + ADCx->HTR = HighThreshold; + /* Set the ADCx low threshold */ + ADCx->LTR = LowThreshold; +} + +/** + * @brief Configures the analog watchdog guarded single channel + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_Channel: the ADC channel to configure for the analog watchdog. + * This parameter can be one of the following values: + * @arg ADC_Channel_0: ADC Channel0 selected + * @arg ADC_Channel_1: ADC Channel1 selected + * @arg ADC_Channel_2: ADC Channel2 selected + * @arg ADC_Channel_3: ADC Channel3 selected + * @arg ADC_Channel_4: ADC Channel4 selected + * @arg ADC_Channel_5: ADC Channel5 selected + * @arg ADC_Channel_6: ADC Channel6 selected + * @arg ADC_Channel_7: ADC Channel7 selected + * @arg ADC_Channel_8: ADC Channel8 selected + * @arg ADC_Channel_9: ADC Channel9 selected + * @arg ADC_Channel_10: ADC Channel10 selected + * @arg ADC_Channel_11: ADC Channel11 selected + * @arg ADC_Channel_12: ADC Channel12 selected + * @arg ADC_Channel_13: ADC Channel13 selected + * @arg ADC_Channel_14: ADC Channel14 selected + * @arg ADC_Channel_15: ADC Channel15 selected + * @arg ADC_Channel_16: ADC Channel16 selected + * @arg ADC_Channel_17: ADC Channel17 selected + * @retval None + */ +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CHANNEL(ADC_Channel)); + /* Get the old register value */ + tmpreg = ADCx->CR1; + /* Clear the Analog watchdog channel select bits */ + tmpreg &= CR1_AWDCH_Reset; + /* Set the Analog watchdog channel */ + tmpreg |= ADC_Channel; + /* Store the new register value */ + ADCx->CR1 = tmpreg; +} + +/** + * @brief Enables or disables the temperature sensor and Vrefint channel. + * @param NewState: new state of the temperature sensor. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_TempSensorVrefintCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the temperature sensor and Vrefint channel*/ + ADC1->CR2 |= CR2_TSVREFE_Set; + } + else + { + /* Disable the temperature sensor and Vrefint channel*/ + ADC1->CR2 &= CR2_TSVREFE_Reset; + } +} + +/** + * @brief Checks whether the specified ADC flag is set or not. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ADC_FLAG_AWD: Analog watchdog flag + * @arg ADC_FLAG_EOC: End of conversion flag + * @arg ADC_FLAG_JEOC: End of injected group conversion flag + * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag + * @arg ADC_FLAG_STRT: Start of regular group conversion flag + * @retval The new state of ADC_FLAG (SET or RESET). + */ +FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_GET_FLAG(ADC_FLAG)); + /* Check the status of the specified ADC flag */ + if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET) + { + /* ADC_FLAG is set */ + bitstatus = SET; + } + else + { + /* ADC_FLAG is reset */ + bitstatus = RESET; + } + /* Return the ADC_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the ADCx's pending flags. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg ADC_FLAG_AWD: Analog watchdog flag + * @arg ADC_FLAG_EOC: End of conversion flag + * @arg ADC_FLAG_JEOC: End of injected group conversion flag + * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag + * @arg ADC_FLAG_STRT: Start of regular group conversion flag + * @retval None + */ +void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG)); + /* Clear the selected ADC flags */ + ADCx->SR = ~(uint32_t)ADC_FLAG; +} + +/** + * @brief Checks whether the specified ADC interrupt has occurred or not. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_IT: specifies the ADC interrupt source to check. + * This parameter can be one of the following values: + * @arg ADC_IT_EOC: End of conversion interrupt mask + * @arg ADC_IT_AWD: Analog watchdog interrupt mask + * @arg ADC_IT_JEOC: End of injected conversion interrupt mask + * @retval The new state of ADC_IT (SET or RESET). + */ +ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t itmask = 0, enablestatus = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_GET_IT(ADC_IT)); + /* Get the ADC IT index */ + itmask = ADC_IT >> 8; + /* Get the ADC_IT enable bit status */ + enablestatus = (ADCx->CR1 & (uint8_t)ADC_IT) ; + /* Check the status of the specified ADC interrupt */ + if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus) + { + /* ADC_IT is set */ + bitstatus = SET; + } + else + { + /* ADC_IT is reset */ + bitstatus = RESET; + } + /* Return the ADC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the ADCx's interrupt pending bits. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_IT: specifies the ADC interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg ADC_IT_EOC: End of conversion interrupt mask + * @arg ADC_IT_AWD: Analog watchdog interrupt mask + * @arg ADC_IT_JEOC: End of injected conversion interrupt mask + * @retval None + */ +void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT) +{ + uint8_t itmask = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_IT(ADC_IT)); + /* Get the ADC IT index */ + itmask = (uint8_t)(ADC_IT >> 8); + /* Clear the selected ADC interrupt pending bits */ + ADCx->SR = ~(uint32_t)itmask; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/STM32F10x_FWLIB/src/stm32f10x_bkp.c b/STM32F10x_FWLIB/src/stm32f10x_bkp.c new file mode 100644 index 0000000..26f36dc --- /dev/null +++ b/STM32F10x_FWLIB/src/stm32f10x_bkp.c @@ -0,0 +1,306 @@ +/** + ****************************************************************************** + * @file stm32f10x_bkp.c + * @author MCD Application Team + * @version V3.6.2 + * @date 17-September-2021 + * @brief This file provides all the BKP firmware functions. + ****************************************************************************** + * @attention + * + * Copyright (c) 2012 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_bkp.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup BKP + * @brief BKP driver modules + * @{ + */ + +/** @defgroup BKP_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup BKP_Private_Defines + * @{ + */ + +/* ------------ BKP registers bit address in the alias region --------------- */ +#define BKP_OFFSET (BKP_BASE - PERIPH_BASE) + +/* --- CR Register ----*/ + +/* Alias word address of TPAL bit */ +#define CR_OFFSET (BKP_OFFSET + 0x30) +#define TPAL_BitNumber 0x01 +#define CR_TPAL_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4)) + +/* Alias word address of TPE bit */ +#define TPE_BitNumber 0x00 +#define CR_TPE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4)) + +/* --- CSR Register ---*/ + +/* Alias word address of TPIE bit */ +#define CSR_OFFSET (BKP_OFFSET + 0x34) +#define TPIE_BitNumber 0x02 +#define CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4)) + +/* Alias word address of TIF bit */ +#define TIF_BitNumber 0x09 +#define CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4)) + +/* Alias word address of TEF bit */ +#define TEF_BitNumber 0x08 +#define CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4)) + +/* ---------------------- BKP registers bit mask ------------------------ */ + +/* RTCCR register bit mask */ +#define RTCCR_CAL_MASK ((uint16_t)0xFF80) +#define RTCCR_MASK ((uint16_t)0xFC7F) + +/** + * @} + */ + + +/** @defgroup BKP_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup BKP_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup BKP_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup BKP_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the BKP peripheral registers to their default reset values. + * @param None + * @retval None + */ +void BKP_DeInit(void) +{ + RCC_BackupResetCmd(ENABLE); + RCC_BackupResetCmd(DISABLE); +} + +/** + * @brief Configures the Tamper Pin active level. + * @param BKP_TamperPinLevel: specifies the Tamper Pin active level. + * This parameter can be one of the following values: + * @arg BKP_TamperPinLevel_High: Tamper pin active on high level + * @arg BKP_TamperPinLevel_Low: Tamper pin active on low level + * @retval None + */ +void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel) +{ + /* Check the parameters */ + assert_param(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel)); + *(__IO uint32_t *) CR_TPAL_BB = BKP_TamperPinLevel; +} + +/** + * @brief Enables or disables the Tamper Pin activation. + * @param NewState: new state of the Tamper Pin activation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void BKP_TamperPinCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_TPE_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the Tamper Pin Interrupt. + * @param NewState: new state of the Tamper Pin Interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void BKP_ITConfig(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CSR_TPIE_BB = (uint32_t)NewState; +} + +/** + * @brief Select the RTC output source to output on the Tamper pin. + * @param BKP_RTCOutputSource: specifies the RTC output source. + * This parameter can be one of the following values: + * @arg BKP_RTCOutputSource_None: no RTC output on the Tamper pin. + * @arg BKP_RTCOutputSource_CalibClock: output the RTC clock with frequency + * divided by 64 on the Tamper pin. + * @arg BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse signal on + * the Tamper pin. + * @arg BKP_RTCOutputSource_Second: output the RTC Second pulse signal on + * the Tamper pin. + * @retval None + */ +void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource) +{ + uint16_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_BKP_RTC_OUTPUT_SOURCE(BKP_RTCOutputSource)); + tmpreg = BKP->RTCCR; + /* Clear CCO, ASOE and ASOS bits */ + tmpreg &= RTCCR_MASK; + + /* Set CCO, ASOE and ASOS bits according to BKP_RTCOutputSource value */ + tmpreg |= BKP_RTCOutputSource; + /* Store the new value */ + BKP->RTCCR = tmpreg; +} + +/** + * @brief Sets RTC Clock Calibration value. + * @param CalibrationValue: specifies the RTC Clock Calibration value. + * This parameter must be a number between 0 and 0x7F. + * @retval None + */ +void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue) +{ + uint16_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_BKP_CALIBRATION_VALUE(CalibrationValue)); + tmpreg = BKP->RTCCR; + /* Clear CAL[6:0] bits */ + tmpreg &= RTCCR_CAL_MASK; + /* Set CAL[6:0] bits according to CalibrationValue value */ + tmpreg |= CalibrationValue; + /* Store the new value */ + BKP->RTCCR = tmpreg; +} + +/** + * @brief Writes user data to the specified Data Backup Register. + * @param BKP_DR: specifies the Data Backup Register. + * This parameter can be BKP_DRx where x:[1, 42] + * @param Data: data to write + * @retval None + */ +void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_BKP_DR(BKP_DR)); + + tmp = (uint32_t)BKP_BASE; + tmp += BKP_DR; + + *(__IO uint32_t *) tmp = Data; +} + +/** + * @brief Reads data from the specified Data Backup Register. + * @param BKP_DR: specifies the Data Backup Register. + * This parameter can be BKP_DRx where x:[1, 42] + * @retval The content of the specified Data Backup Register + */ +uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_BKP_DR(BKP_DR)); + + tmp = (uint32_t)BKP_BASE; + tmp += BKP_DR; + + return (*(__IO uint16_t *) tmp); +} + +/** + * @brief Checks whether the Tamper Pin Event flag is set or not. + * @param None + * @retval The new state of the Tamper Pin Event flag (SET or RESET). + */ +FlagStatus BKP_GetFlagStatus(void) +{ + return (FlagStatus)(*(__IO uint32_t *) CSR_TEF_BB); +} + +/** + * @brief Clears Tamper Pin Event pending flag. + * @param None + * @retval None + */ +void BKP_ClearFlag(void) +{ + /* Set CTE bit to clear Tamper Pin Event flag */ + BKP->CSR |= BKP_CSR_CTE; +} + +/** + * @brief Checks whether the Tamper Pin Interrupt has occurred or not. + * @param None + * @retval The new state of the Tamper Pin Interrupt (SET or RESET). + */ +ITStatus BKP_GetITStatus(void) +{ + return (ITStatus)(*(__IO uint32_t *) CSR_TIF_BB); +} + +/** + * @brief Clears Tamper Pin Interrupt pending bit. + * @param None + * @retval None + */ +void BKP_ClearITPendingBit(void) +{ + /* Set CTI bit to clear Tamper Pin Interrupt pending bit */ + BKP->CSR |= BKP_CSR_CTI; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/STM32F10x_FWLIB/src/stm32f10x_can.c b/STM32F10x_FWLIB/src/stm32f10x_can.c new file mode 100644 index 0000000..a65561a --- /dev/null +++ b/STM32F10x_FWLIB/src/stm32f10x_can.c @@ -0,0 +1,1413 @@ +/** + ****************************************************************************** + * @file stm32f10x_can.c + * @author MCD Application Team + * @version V3.6.2 + * @date 17-September-2021 + * @brief This file provides all the CAN firmware functions. + ****************************************************************************** + * @attention + * + * Copyright (c) 2012 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_can.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup CAN + * @brief CAN driver modules + * @{ + */ + +/** @defgroup CAN_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup CAN_Private_Defines + * @{ + */ + +/* CAN Master Control Register bits */ + +#define MCR_DBF ((uint32_t)0x00010000) /* software master reset */ + +/* CAN Mailbox Transmit Request */ +#define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */ + +/* CAN Filter Master Register bits */ +#define FMR_FINIT ((uint32_t)0x00000001) /* Filter init mode */ + +/* Time out for INAK bit */ +#define INAK_TIMEOUT ((uint32_t)0x0000FFFF) +/* Time out for SLAK bit */ +#define SLAK_TIMEOUT ((uint32_t)0x0000FFFF) + + + +/* Flags in TSR register */ +#define CAN_FLAGS_TSR ((uint32_t)0x08000000) +/* Flags in RF1R register */ +#define CAN_FLAGS_RF1R ((uint32_t)0x04000000) +/* Flags in RF0R register */ +#define CAN_FLAGS_RF0R ((uint32_t)0x02000000) +/* Flags in MSR register */ +#define CAN_FLAGS_MSR ((uint32_t)0x01000000) +/* Flags in ESR register */ +#define CAN_FLAGS_ESR ((uint32_t)0x00F00000) + +/* Mailboxes definition */ +#define CAN_TXMAILBOX_0 ((uint8_t)0x00) +#define CAN_TXMAILBOX_1 ((uint8_t)0x01) +#define CAN_TXMAILBOX_2 ((uint8_t)0x02) + + + +#define CAN_MODE_MASK ((uint32_t) 0x00000003) +/** + * @} + */ + +/** @defgroup CAN_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup CAN_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup CAN_Private_FunctionPrototypes + * @{ + */ + +static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit); + +/** + * @} + */ + +/** @defgroup CAN_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the CAN peripheral registers to their default reset values. + * @param CANx: where x can be 1 or 2 to select the CAN peripheral. + * @retval None. + */ +void CAN_DeInit(CAN_TypeDef* CANx) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + if (CANx == CAN1) + { + /* Enable CAN1 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE); + /* Release CAN1 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE); + } + else + { + /* Enable CAN2 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE); + /* Release CAN2 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE); + } +} + +/** + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_InitStruct. + * @param CANx: where x can be 1 or 2 to to select the CAN + * peripheral. + * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that + * contains the configuration information for the + * CAN peripheral. + * @retval Constant indicates initialization succeed which will be + * CAN_InitStatus_Failed or CAN_InitStatus_Success. + */ +uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct) +{ + uint8_t InitStatus = CAN_InitStatus_Failed; + uint32_t wait_ack = 0x00000000; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP)); + assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode)); + assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW)); + assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1)); + assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2)); + assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler)); + + /* Exit from sleep mode */ + CANx->MCR &= (~(uint32_t)CAN_MCR_SLEEP); + + /* Request initialisation */ + CANx->MCR |= CAN_MCR_INRQ ; + + /* Wait the acknowledge */ + while (((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT)) + { + wait_ack++; + } + + /* Check acknowledge */ + if ((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) + { + InitStatus = CAN_InitStatus_Failed; + } + else + { + /* Set the time triggered communication mode */ + if (CAN_InitStruct->CAN_TTCM == ENABLE) + { + CANx->MCR |= CAN_MCR_TTCM; + } + else + { + CANx->MCR &= ~(uint32_t)CAN_MCR_TTCM; + } + + /* Set the automatic bus-off management */ + if (CAN_InitStruct->CAN_ABOM == ENABLE) + { + CANx->MCR |= CAN_MCR_ABOM; + } + else + { + CANx->MCR &= ~(uint32_t)CAN_MCR_ABOM; + } + + /* Set the automatic wake-up mode */ + if (CAN_InitStruct->CAN_AWUM == ENABLE) + { + CANx->MCR |= CAN_MCR_AWUM; + } + else + { + CANx->MCR &= ~(uint32_t)CAN_MCR_AWUM; + } + + /* Set the no automatic retransmission */ + if (CAN_InitStruct->CAN_NART == ENABLE) + { + CANx->MCR |= CAN_MCR_NART; + } + else + { + CANx->MCR &= ~(uint32_t)CAN_MCR_NART; + } + + /* Set the receive FIFO locked mode */ + if (CAN_InitStruct->CAN_RFLM == ENABLE) + { + CANx->MCR |= CAN_MCR_RFLM; + } + else + { + CANx->MCR &= ~(uint32_t)CAN_MCR_RFLM; + } + + /* Set the transmit FIFO priority */ + if (CAN_InitStruct->CAN_TXFP == ENABLE) + { + CANx->MCR |= CAN_MCR_TXFP; + } + else + { + CANx->MCR &= ~(uint32_t)CAN_MCR_TXFP; + } + + /* Set the bit timing register */ + CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | \ + ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | \ + ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | \ + ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | \ + ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1); + + /* Request leave initialisation */ + CANx->MCR &= ~(uint32_t)CAN_MCR_INRQ; + + /* Wait the acknowledge */ + wait_ack = 0; + + while (((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT)) + { + wait_ack++; + } + + /* ...and check acknowledged */ + if ((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) + { + InitStatus = CAN_InitStatus_Failed; + } + else + { + InitStatus = CAN_InitStatus_Success ; + } + } + + /* At this step, return the status of initialization */ + return InitStatus; +} + +/** + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_FilterInitStruct. + * @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef + * structure that contains the configuration + * information. + * @retval None. + */ +void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct) +{ + uint32_t filter_number_bit_pos = 0; + /* Check the parameters */ + assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber)); + assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode)); + assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale)); + assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment)); + assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation)); + + filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber; + + /* Initialisation mode for the filter */ + CAN1->FMR |= FMR_FINIT; + + /* Filter Deactivation */ + CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos; + + /* Filter Scale */ + if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit) + { + /* 16-bit scale for the filter */ + CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos; + + /* First 16-bit identifier and First 16-bit mask */ + /* Or First 16-bit identifier and Second 16-bit identifier */ + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); + + /* Second 16-bit identifier and Second 16-bit mask */ + /* Or Third 16-bit identifier and Fourth 16-bit identifier */ + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh); + } + + if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit) + { + /* 32-bit scale for the filter */ + CAN1->FS1R |= filter_number_bit_pos; + /* 32-bit identifier or First 32-bit identifier */ + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); + /* 32-bit mask or Second 32-bit identifier */ + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow); + } + + /* Filter Mode */ + if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask) + { + /*Id/Mask mode for the filter*/ + CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos; + } + else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ + { + /*Identifier list mode for the filter*/ + CAN1->FM1R |= (uint32_t)filter_number_bit_pos; + } + + /* Filter FIFO assignment */ + if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0) + { + /* FIFO 0 assignation for the filter */ + CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos; + } + + if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1) + { + /* FIFO 1 assignation for the filter */ + CAN1->FFA1R |= (uint32_t)filter_number_bit_pos; + } + + /* Filter activation */ + if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE) + { + CAN1->FA1R |= filter_number_bit_pos; + } + + /* Leave the initialisation mode for the filter */ + CAN1->FMR &= ~FMR_FINIT; +} + +/** + * @brief Fills each CAN_InitStruct member with its default value. + * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure which + * will be initialized. + * @retval None. + */ +void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct) +{ + /* Reset CAN init structure parameters values */ + + /* Initialize the time triggered communication mode */ + CAN_InitStruct->CAN_TTCM = DISABLE; + + /* Initialize the automatic bus-off management */ + CAN_InitStruct->CAN_ABOM = DISABLE; + + /* Initialize the automatic wake-up mode */ + CAN_InitStruct->CAN_AWUM = DISABLE; + + /* Initialize the no automatic retransmission */ + CAN_InitStruct->CAN_NART = DISABLE; + + /* Initialize the receive FIFO locked mode */ + CAN_InitStruct->CAN_RFLM = DISABLE; + + /* Initialize the transmit FIFO priority */ + CAN_InitStruct->CAN_TXFP = DISABLE; + + /* Initialize the CAN_Mode member */ + CAN_InitStruct->CAN_Mode = CAN_Mode_Normal; + + /* Initialize the CAN_SJW member */ + CAN_InitStruct->CAN_SJW = CAN_SJW_1tq; + + /* Initialize the CAN_BS1 member */ + CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq; + + /* Initialize the CAN_BS2 member */ + CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq; + + /* Initialize the CAN_Prescaler member */ + CAN_InitStruct->CAN_Prescaler = 1; +} + +/** + * @brief Select the start bank filter for slave CAN. + * @note This function applies only to STM32 Connectivity line devices. + * @param CAN_BankNumber: Select the start slave bank filter from 1..27. + * @retval None. + */ +void CAN_SlaveStartBank(uint8_t CAN_BankNumber) +{ + /* Check the parameters */ + assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber)); + + /* Enter Initialisation mode for the filter */ + CAN1->FMR |= FMR_FINIT; + + /* Select the start slave bank */ + CAN1->FMR &= (uint32_t)0xFFFFC0F1 ; + CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8; + + /* Leave Initialisation mode for the filter */ + CAN1->FMR &= ~FMR_FINIT; +} + +/** + * @brief Enables or disables the DBG Freeze for CAN. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param NewState: new state of the CAN peripheral. This parameter can + * be: ENABLE or DISABLE. + * @retval None. + */ +void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable Debug Freeze */ + CANx->MCR |= MCR_DBF; + } + else + { + /* Disable Debug Freeze */ + CANx->MCR &= ~MCR_DBF; + } +} + + +/** + * @brief Enables or disabes the CAN Time TriggerOperation communication mode. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param NewState : Mode new state , can be one of @ref FunctionalState. + * @note when enabled, Time stamp (TIME[15:0]) value is sent in the last + * two data bytes of the 8-byte message: TIME[7:0] in data byte 6 + * and TIME[15:8] in data byte 7 + * @note DLC must be programmed as 8 in order Time Stamp (2 bytes) to be + * sent over the CAN bus. + * @retval None + */ +void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the TTCM mode */ + CANx->MCR |= CAN_MCR_TTCM; + + /* Set TGT bits */ + CANx->sTxMailBox[0].TDTR |= ((uint32_t)CAN_TDT0R_TGT); + CANx->sTxMailBox[1].TDTR |= ((uint32_t)CAN_TDT1R_TGT); + CANx->sTxMailBox[2].TDTR |= ((uint32_t)CAN_TDT2R_TGT); + } + else + { + /* Disable the TTCM mode */ + CANx->MCR &= (uint32_t)(~(uint32_t)CAN_MCR_TTCM); + + /* Reset TGT bits */ + CANx->sTxMailBox[0].TDTR &= ((uint32_t)~CAN_TDT0R_TGT); + CANx->sTxMailBox[1].TDTR &= ((uint32_t)~CAN_TDT1R_TGT); + CANx->sTxMailBox[2].TDTR &= ((uint32_t)~CAN_TDT2R_TGT); + } +} +/** + * @brief Initiates the transmission of a message. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param TxMessage: pointer to a structure which contains CAN Id, CAN + * DLC and CAN data. + * @retval The number of the mailbox that is used for transmission + * or CAN_TxStatus_NoMailBox if there is no empty mailbox. + */ +uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage) +{ + uint8_t transmit_mailbox = 0; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_IDTYPE(TxMessage->IDE)); + assert_param(IS_CAN_RTR(TxMessage->RTR)); + assert_param(IS_CAN_DLC(TxMessage->DLC)); + + /* Select one empty transmit mailbox */ + if ((CANx->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) + { + transmit_mailbox = 0; + } + else if ((CANx->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) + { + transmit_mailbox = 1; + } + else if ((CANx->TSR&CAN_TSR_TME2) == CAN_TSR_TME2) + { + transmit_mailbox = 2; + } + else + { + transmit_mailbox = CAN_TxStatus_NoMailBox; + } + + if (transmit_mailbox != CAN_TxStatus_NoMailBox) + { + /* Set up the Id */ + CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ; + if (TxMessage->IDE == CAN_Id_Standard) + { + assert_param(IS_CAN_STDID(TxMessage->StdId)); + CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | \ + TxMessage->RTR); + } + else + { + assert_param(IS_CAN_EXTID(TxMessage->ExtId)); + CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId << 3) | \ + TxMessage->IDE | \ + TxMessage->RTR); + } + + /* Set up the DLC */ + TxMessage->DLC &= (uint8_t)0x0000000F; + CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0; + CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC; + + /* Set up the data field */ + CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) | + ((uint32_t)TxMessage->Data[2] << 16) | + ((uint32_t)TxMessage->Data[1] << 8) | + ((uint32_t)TxMessage->Data[0])); + CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) | + ((uint32_t)TxMessage->Data[6] << 16) | + ((uint32_t)TxMessage->Data[5] << 8) | + ((uint32_t)TxMessage->Data[4])); + /* Request transmission */ + CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ; + } + return transmit_mailbox; +} + +/** + * @brief Checks the transmission of a message. + * @param CANx: where x can be 1 or 2 to to select the + * CAN peripheral. + * @param TransmitMailbox: the number of the mailbox that is used for + * transmission. + * @retval CAN_TxStatus_Ok if the CAN driver transmits the message, CAN_TxStatus_Failed + * in an other case. + */ +uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox) +{ + uint32_t state = 0; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox)); + + switch (TransmitMailbox) + { + case (CAN_TXMAILBOX_0): + state = CANx->TSR & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0); + break; + case (CAN_TXMAILBOX_1): + state = CANx->TSR & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1); + break; + case (CAN_TXMAILBOX_2): + state = CANx->TSR & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2); + break; + default: + state = CAN_TxStatus_Failed; + break; + } + switch (state) + { + /* transmit pending */ + case (0x0): state = CAN_TxStatus_Pending; + break; + /* transmit failed */ + case (CAN_TSR_RQCP0 | CAN_TSR_TME0): state = CAN_TxStatus_Failed; + break; + case (CAN_TSR_RQCP1 | CAN_TSR_TME1): state = CAN_TxStatus_Failed; + break; + case (CAN_TSR_RQCP2 | CAN_TSR_TME2): state = CAN_TxStatus_Failed; + break; + /* transmit succeeded */ + case (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0):state = CAN_TxStatus_Ok; + break; + case (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1):state = CAN_TxStatus_Ok; + break; + case (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2):state = CAN_TxStatus_Ok; + break; + default: state = CAN_TxStatus_Failed; + break; + } + return (uint8_t) state; +} + +/** + * @brief Cancels a transmit request. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param Mailbox: Mailbox number. + * @retval None. + */ +void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox)); + /* abort transmission */ + switch (Mailbox) + { + case (CAN_TXMAILBOX_0): CANx->TSR |= CAN_TSR_ABRQ0; + break; + case (CAN_TXMAILBOX_1): CANx->TSR |= CAN_TSR_ABRQ1; + break; + case (CAN_TXMAILBOX_2): CANx->TSR |= CAN_TSR_ABRQ2; + break; + default: + break; + } +} + + +/** + * @brief Receives a message. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. + * @param RxMessage: pointer to a structure receive message which contains + * CAN Id, CAN DLC, CAN datas and FMI number. + * @retval None. + */ +void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FIFO(FIFONumber)); + /* Get the Id */ + RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR; + if (RxMessage->IDE == CAN_Id_Standard) + { + RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21); + } + else + { + RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3); + } + + RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR; + /* Get the DLC */ + RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR; + /* Get the FMI */ + RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8); + /* Get the data field */ + RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR; + RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8); + RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16); + RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24); + RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR; + RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8); + RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16); + RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24); + /* Release the FIFO */ + /* Release FIFO0 */ + if (FIFONumber == CAN_FIFO0) + { + CANx->RF0R |= CAN_RF0R_RFOM0; + } + /* Release FIFO1 */ + else /* FIFONumber == CAN_FIFO1 */ + { + CANx->RF1R |= CAN_RF1R_RFOM1; + } +} + +/** + * @brief Releases the specified FIFO. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1. + * @retval None. + */ +void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FIFO(FIFONumber)); + /* Release FIFO0 */ + if (FIFONumber == CAN_FIFO0) + { + CANx->RF0R |= CAN_RF0R_RFOM0; + } + /* Release FIFO1 */ + else /* FIFONumber == CAN_FIFO1 */ + { + CANx->RF1R |= CAN_RF1R_RFOM1; + } +} + +/** + * @brief Returns the number of pending messages. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. + * @retval NbMessage : which is the number of pending message. + */ +uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber) +{ + uint8_t message_pending=0; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FIFO(FIFONumber)); + if (FIFONumber == CAN_FIFO0) + { + message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03); + } + else if (FIFONumber == CAN_FIFO1) + { + message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03); + } + else + { + message_pending = 0; + } + return message_pending; +} + + +/** + * @brief Select the CAN Operation mode. + * @param CAN_OperatingMode : CAN Operating Mode. This parameter can be one + * of @ref CAN_OperatingMode_TypeDef enumeration. + * @retval status of the requested mode which can be + * - CAN_ModeStatus_Failed CAN failed entering the specific mode + * - CAN_ModeStatus_Success CAN Succeed entering the specific mode + + */ +uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode) +{ + uint8_t status = CAN_ModeStatus_Failed; + + /* Timeout for INAK or also for SLAK bits*/ + uint32_t timeout = INAK_TIMEOUT; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode)); + + if (CAN_OperatingMode == CAN_OperatingMode_Initialization) + { + /* Request initialisation */ + CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_SLEEP)) | CAN_MCR_INRQ); + + /* Wait the acknowledge */ + while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) && (timeout != 0)) + { + timeout--; + } + if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) + { + status = CAN_ModeStatus_Failed; + } + else + { + status = CAN_ModeStatus_Success; + } + } + else if (CAN_OperatingMode == CAN_OperatingMode_Normal) + { + /* Request leave initialisation and sleep mode and enter Normal mode */ + CANx->MCR &= (uint32_t)(~(CAN_MCR_SLEEP|CAN_MCR_INRQ)); + + /* Wait the acknowledge */ + while (((CANx->MSR & CAN_MODE_MASK) != 0) && (timeout!=0)) + { + timeout--; + } + if ((CANx->MSR & CAN_MODE_MASK) != 0) + { + status = CAN_ModeStatus_Failed; + } + else + { + status = CAN_ModeStatus_Success; + } + } + else if (CAN_OperatingMode == CAN_OperatingMode_Sleep) + { + /* Request Sleep mode */ + CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); + + /* Wait the acknowledge */ + while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) && (timeout!=0)) + { + timeout--; + } + if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) + { + status = CAN_ModeStatus_Failed; + } + else + { + status = CAN_ModeStatus_Success; + } + } + else + { + status = CAN_ModeStatus_Failed; + } + + return (uint8_t) status; +} + +/** + * @brief Enters the low power mode. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @retval status: CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed in an + * other case. + */ +uint8_t CAN_Sleep(CAN_TypeDef* CANx) +{ + uint8_t sleepstatus = CAN_Sleep_Failed; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Request Sleep mode */ + CANx->MCR = (((CANx->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); + + /* Sleep mode status */ + if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK) + { + /* Sleep mode not entered */ + sleepstatus = CAN_Sleep_Ok; + } + /* return sleep mode status */ + return (uint8_t)sleepstatus; +} + +/** + * @brief Wakes the CAN up. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @retval status: CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed in an + * other case. + */ +uint8_t CAN_WakeUp(CAN_TypeDef* CANx) +{ + uint32_t wait_slak = SLAK_TIMEOUT; + uint8_t wakeupstatus = CAN_WakeUp_Failed; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Wake up request */ + CANx->MCR &= ~(uint32_t)CAN_MCR_SLEEP; + + /* Sleep mode status */ + while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00)) + { + wait_slak--; + } + if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK) + { + /* wake up done : Sleep mode exited */ + wakeupstatus = CAN_WakeUp_Ok; + } + /* return wakeup status */ + return (uint8_t)wakeupstatus; +} + + +/** + * @brief Returns the CANx's last error code (LEC). + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @retval CAN_ErrorCode: specifies the Error code : + * - CAN_ERRORCODE_NoErr No Error + * - CAN_ERRORCODE_StuffErr Stuff Error + * - CAN_ERRORCODE_FormErr Form Error + * - CAN_ERRORCODE_ACKErr Acknowledgment Error + * - CAN_ERRORCODE_BitRecessiveErr Bit Recessive Error + * - CAN_ERRORCODE_BitDominantErr Bit Dominant Error + * - CAN_ERRORCODE_CRCErr CRC Error + * - CAN_ERRORCODE_SoftwareSetErr Software Set Error + */ + +uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx) +{ + uint8_t errorcode=0; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Get the error code*/ + errorcode = (((uint8_t)CANx->ESR) & (uint8_t)CAN_ESR_LEC); + + /* Return the error code*/ + return errorcode; +} +/** + * @brief Returns the CANx Receive Error Counter (REC). + * @note In case of an error during reception, this counter is incremented + * by 1 or by 8 depending on the error condition as defined by the CAN + * standard. After every successful reception, the counter is + * decremented by 1 or reset to 120 if its value was higher than 128. + * When the counter value exceeds 127, the CAN controller enters the + * error passive state. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @retval CAN Receive Error Counter. + */ +uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx) +{ + uint8_t counter=0; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Get the Receive Error Counter*/ + counter = (uint8_t)((CANx->ESR & CAN_ESR_REC)>> 24); + + /* Return the Receive Error Counter*/ + return counter; +} + + +/** + * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC). + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @retval LSB of the 9-bit CAN Transmit Error Counter. + */ +uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx) +{ + uint8_t counter=0; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */ + counter = (uint8_t)((CANx->ESR & CAN_ESR_TEC)>> 16); + + /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */ + return counter; +} + + +/** + * @brief Enables or disables the specified CANx interrupts. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled. + * This parameter can be: + * - CAN_IT_TME, + * - CAN_IT_FMP0, + * - CAN_IT_FF0, + * - CAN_IT_FOV0, + * - CAN_IT_FMP1, + * - CAN_IT_FF1, + * - CAN_IT_FOV1, + * - CAN_IT_EWG, + * - CAN_IT_EPV, + * - CAN_IT_LEC, + * - CAN_IT_ERR, + * - CAN_IT_WKU or + * - CAN_IT_SLK. + * @param NewState: new state of the CAN interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None. + */ +void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_IT(CAN_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected CANx interrupt */ + CANx->IER |= CAN_IT; + } + else + { + /* Disable the selected CANx interrupt */ + CANx->IER &= ~CAN_IT; + } +} +/** + * @brief Checks whether the specified CAN flag is set or not. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_FLAG: specifies the flag to check. + * This parameter can be one of the following flags: + * - CAN_FLAG_EWG + * - CAN_FLAG_EPV + * - CAN_FLAG_BOF + * - CAN_FLAG_RQCP0 + * - CAN_FLAG_RQCP1 + * - CAN_FLAG_RQCP2 + * - CAN_FLAG_FMP1 + * - CAN_FLAG_FF1 + * - CAN_FLAG_FOV1 + * - CAN_FLAG_FMP0 + * - CAN_FLAG_FF0 + * - CAN_FLAG_FOV0 + * - CAN_FLAG_WKU + * - CAN_FLAG_SLAK + * - CAN_FLAG_LEC + * @retval The new state of CAN_FLAG (SET or RESET). + */ +FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_GET_FLAG(CAN_FLAG)); + + + if((CAN_FLAG & CAN_FLAGS_ESR) != (uint32_t)RESET) + { + /* Check the status of the specified CAN flag */ + if ((CANx->ESR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + else if((CAN_FLAG & CAN_FLAGS_MSR) != (uint32_t)RESET) + { + /* Check the status of the specified CAN flag */ + if ((CANx->MSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + else if((CAN_FLAG & CAN_FLAGS_TSR) != (uint32_t)RESET) + { + /* Check the status of the specified CAN flag */ + if ((CANx->TSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + else if((CAN_FLAG & CAN_FLAGS_RF0R) != (uint32_t)RESET) + { + /* Check the status of the specified CAN flag */ + if ((CANx->RF0R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + else /* If(CAN_FLAG & CAN_FLAGS_RF1R != (uint32_t)RESET) */ + { + /* Check the status of the specified CAN flag */ + if ((uint32_t)(CANx->RF1R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + } + /* Return the CAN_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the CAN's pending flags. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_FLAG: specifies the flag to clear. + * This parameter can be one of the following flags: + * - CAN_FLAG_RQCP0 + * - CAN_FLAG_RQCP1 + * - CAN_FLAG_RQCP2 + * - CAN_FLAG_FF1 + * - CAN_FLAG_FOV1 + * - CAN_FLAG_FF0 + * - CAN_FLAG_FOV0 + * - CAN_FLAG_WKU + * - CAN_FLAG_SLAK + * - CAN_FLAG_LEC + * @retval None. + */ +void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG) +{ + uint32_t flagtmp=0; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG)); + + if (CAN_FLAG == CAN_FLAG_LEC) /* ESR register */ + { + /* Clear the selected CAN flags */ + CANx->ESR = (uint32_t)RESET; + } + else /* MSR or TSR or RF0R or RF1R */ + { + flagtmp = CAN_FLAG & 0x000FFFFF; + + if ((CAN_FLAG & CAN_FLAGS_RF0R)!=(uint32_t)RESET) + { + /* Receive Flags */ + CANx->RF0R = (uint32_t)(flagtmp); + } + else if ((CAN_FLAG & CAN_FLAGS_RF1R)!=(uint32_t)RESET) + { + /* Receive Flags */ + CANx->RF1R = (uint32_t)(flagtmp); + } + else if ((CAN_FLAG & CAN_FLAGS_TSR)!=(uint32_t)RESET) + { + /* Transmit Flags */ + CANx->TSR = (uint32_t)(flagtmp); + } + else /* If((CAN_FLAG & CAN_FLAGS_MSR)!=(uint32_t)RESET) */ + { + /* Operating mode Flags */ + CANx->MSR = (uint32_t)(flagtmp); + } + } +} + +/** + * @brief Checks whether the specified CANx interrupt has occurred or not. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_IT: specifies the CAN interrupt source to check. + * This parameter can be one of the following flags: + * - CAN_IT_TME + * - CAN_IT_FMP0 + * - CAN_IT_FF0 + * - CAN_IT_FOV0 + * - CAN_IT_FMP1 + * - CAN_IT_FF1 + * - CAN_IT_FOV1 + * - CAN_IT_WKU + * - CAN_IT_SLK + * - CAN_IT_EWG + * - CAN_IT_EPV + * - CAN_IT_BOF + * - CAN_IT_LEC + * - CAN_IT_ERR + * @retval The current state of CAN_IT (SET or RESET). + */ +ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT) +{ + ITStatus itstatus = RESET; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_IT(CAN_IT)); + + /* check the enable interrupt bit */ + if((CANx->IER & CAN_IT) != RESET) + { + /* in case the Interrupt is enabled, .... */ + switch (CAN_IT) + { + case CAN_IT_TME: + /* Check CAN_TSR_RQCPx bits */ + itstatus = CheckITStatus(CANx->TSR, CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2); + break; + case CAN_IT_FMP0: + /* Check CAN_RF0R_FMP0 bit */ + itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FMP0); + break; + case CAN_IT_FF0: + /* Check CAN_RF0R_FULL0 bit */ + itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FULL0); + break; + case CAN_IT_FOV0: + /* Check CAN_RF0R_FOVR0 bit */ + itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FOVR0); + break; + case CAN_IT_FMP1: + /* Check CAN_RF1R_FMP1 bit */ + itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FMP1); + break; + case CAN_IT_FF1: + /* Check CAN_RF1R_FULL1 bit */ + itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FULL1); + break; + case CAN_IT_FOV1: + /* Check CAN_RF1R_FOVR1 bit */ + itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FOVR1); + break; + case CAN_IT_WKU: + /* Check CAN_MSR_WKUI bit */ + itstatus = CheckITStatus(CANx->MSR, CAN_MSR_WKUI); + break; + case CAN_IT_SLK: + /* Check CAN_MSR_SLAKI bit */ + itstatus = CheckITStatus(CANx->MSR, CAN_MSR_SLAKI); + break; + case CAN_IT_EWG: + /* Check CAN_ESR_EWGF bit */ + itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF); + break; + case CAN_IT_EPV: + /* Check CAN_ESR_EPVF bit */ + itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EPVF); + break; + case CAN_IT_BOF: + /* Check CAN_ESR_BOFF bit */ + itstatus = CheckITStatus(CANx->ESR, CAN_ESR_BOFF); + break; + case CAN_IT_LEC: + /* Check CAN_ESR_LEC bit */ + itstatus = CheckITStatus(CANx->ESR, CAN_ESR_LEC); + break; + case CAN_IT_ERR: + /* Check CAN_MSR_ERRI bit */ + itstatus = CheckITStatus(CANx->MSR, CAN_MSR_ERRI); + break; + default : + /* in case of error, return RESET */ + itstatus = RESET; + break; + } + } + else + { + /* in case the Interrupt is not enabled, return RESET */ + itstatus = RESET; + } + + /* Return the CAN_IT status */ + return itstatus; +} + +/** + * @brief Clears the CANx's interrupt pending bits. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_IT: specifies the interrupt pending bit to clear. + * - CAN_IT_TME + * - CAN_IT_FF0 + * - CAN_IT_FOV0 + * - CAN_IT_FF1 + * - CAN_IT_FOV1 + * - CAN_IT_WKU + * - CAN_IT_SLK + * - CAN_IT_EWG + * - CAN_IT_EPV + * - CAN_IT_BOF + * - CAN_IT_LEC + * - CAN_IT_ERR + * @retval None. + */ +void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_CLEAR_IT(CAN_IT)); + + switch (CAN_IT) + { + case CAN_IT_TME: + /* Clear CAN_TSR_RQCPx (rc_w1)*/ + CANx->TSR = CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2; + break; + case CAN_IT_FF0: + /* Clear CAN_RF0R_FULL0 (rc_w1)*/ + CANx->RF0R = CAN_RF0R_FULL0; + break; + case CAN_IT_FOV0: + /* Clear CAN_RF0R_FOVR0 (rc_w1)*/ + CANx->RF0R = CAN_RF0R_FOVR0; + break; + case CAN_IT_FF1: + /* Clear CAN_RF1R_FULL1 (rc_w1)*/ + CANx->RF1R = CAN_RF1R_FULL1; + break; + case CAN_IT_FOV1: + /* Clear CAN_RF1R_FOVR1 (rc_w1)*/ + CANx->RF1R = CAN_RF1R_FOVR1; + break; + case CAN_IT_WKU: + /* Clear CAN_MSR_WKUI (rc_w1)*/ + CANx->MSR = CAN_MSR_WKUI; + break; + case CAN_IT_SLK: + /* Clear CAN_MSR_SLAKI (rc_w1)*/ + CANx->MSR = CAN_MSR_SLAKI; + break; + case CAN_IT_EWG: + /* Clear CAN_MSR_ERRI (rc_w1) */ + CANx->MSR = CAN_MSR_ERRI; + /* Note : the corresponding Flag is cleared by hardware depending + of the CAN Bus status*/ + break; + case CAN_IT_EPV: + /* Clear CAN_MSR_ERRI (rc_w1) */ + CANx->MSR = CAN_MSR_ERRI; + /* Note : the corresponding Flag is cleared by hardware depending + of the CAN Bus status*/ + break; + case CAN_IT_BOF: + /* Clear CAN_MSR_ERRI (rc_w1) */ + CANx->MSR = CAN_MSR_ERRI; + /* Note : the corresponding Flag is cleared by hardware depending + of the CAN Bus status*/ + break; + case CAN_IT_LEC: + /* Clear LEC bits */ + CANx->ESR = RESET; + /* Clear CAN_MSR_ERRI (rc_w1) */ + CANx->MSR = CAN_MSR_ERRI; + break; + case CAN_IT_ERR: + /*Clear LEC bits */ + CANx->ESR = RESET; + /* Clear CAN_MSR_ERRI (rc_w1) */ + CANx->MSR = CAN_MSR_ERRI; + /* Note : BOFF, EPVF and EWGF Flags are cleared by hardware depending + of the CAN Bus status*/ + break; + default : + break; + } +} + +/** + * @brief Checks whether the CAN interrupt has occurred or not. + * @param CAN_Reg: specifies the CAN interrupt register to check. + * @param It_Bit: specifies the interrupt source bit to check. + * @retval The new state of the CAN Interrupt (SET or RESET). + */ +static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit) +{ + ITStatus pendingbitstatus = RESET; + + if ((CAN_Reg & It_Bit) != (uint32_t)RESET) + { + /* CAN_IT is set */ + pendingbitstatus = SET; + } + else + { + /* CAN_IT is reset */ + pendingbitstatus = RESET; + } + return pendingbitstatus; +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/STM32F10x_FWLIB/src/stm32f10x_cec.c b/STM32F10x_FWLIB/src/stm32f10x_cec.c new file mode 100644 index 0000000..8324c68 --- /dev/null +++ b/STM32F10x_FWLIB/src/stm32f10x_cec.c @@ -0,0 +1,431 @@ +/** + ****************************************************************************** + * @file stm32f10x_cec.c + * @author MCD Application Team + * @version V3.6.2 + * @date 17-September-2021 + * @brief This file provides all the CEC firmware functions. + ****************************************************************************** + * @attention + * + * Copyright (c) 2012 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_cec.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup CEC + * @brief CEC driver modules + * @{ + */ + +/** @defgroup CEC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + + +/** @defgroup CEC_Private_Defines + * @{ + */ + +/* ------------ CEC registers bit address in the alias region ----------- */ +#define CEC_OFFSET (CEC_BASE - PERIPH_BASE) + +/* --- CFGR Register ---*/ + +/* Alias word address of PE bit */ +#define CFGR_OFFSET (CEC_OFFSET + 0x00) +#define PE_BitNumber 0x00 +#define CFGR_PE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (PE_BitNumber * 4)) + +/* Alias word address of IE bit */ +#define IE_BitNumber 0x01 +#define CFGR_IE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (IE_BitNumber * 4)) + +/* --- CSR Register ---*/ + +/* Alias word address of TSOM bit */ +#define CSR_OFFSET (CEC_OFFSET + 0x10) +#define TSOM_BitNumber 0x00 +#define CSR_TSOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TSOM_BitNumber * 4)) + +/* Alias word address of TEOM bit */ +#define TEOM_BitNumber 0x01 +#define CSR_TEOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEOM_BitNumber * 4)) + +#define CFGR_CLEAR_Mask (uint8_t)(0xF3) /* CFGR register Mask */ +#define FLAG_Mask ((uint32_t)0x00FFFFFF) /* CEC FLAG mask */ + +/** + * @} + */ + + +/** @defgroup CEC_Private_Macros + * @{ + */ + +/** + * @} + */ + + +/** @defgroup CEC_Private_Variables + * @{ + */ + +/** + * @} + */ + + +/** @defgroup CEC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + + +/** @defgroup CEC_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the CEC peripheral registers to their default reset + * values. + * @param None + * @retval None + */ +void CEC_DeInit(void) +{ + /* Enable CEC reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE); + /* Release CEC from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE); +} + + +/** + * @brief Initializes the CEC peripheral according to the specified + * parameters in the CEC_InitStruct. + * @param CEC_InitStruct: pointer to an CEC_InitTypeDef structure that + * contains the configuration information for the specified + * CEC peripheral. + * @retval None + */ +void CEC_Init(CEC_InitTypeDef* CEC_InitStruct) +{ + uint16_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(CEC_InitStruct->CEC_BitTimingMode)); + assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(CEC_InitStruct->CEC_BitPeriodMode)); + + /*---------------------------- CEC CFGR Configuration -----------------*/ + /* Get the CEC CFGR value */ + tmpreg = CEC->CFGR; + + /* Clear BTEM and BPEM bits */ + tmpreg &= CFGR_CLEAR_Mask; + + /* Configure CEC: Bit Timing Error and Bit Period Error */ + tmpreg |= (uint16_t)(CEC_InitStruct->CEC_BitTimingMode | CEC_InitStruct->CEC_BitPeriodMode); + + /* Write to CEC CFGR register*/ + CEC->CFGR = tmpreg; + +} + +/** + * @brief Enables or disables the specified CEC peripheral. + * @param NewState: new state of the CEC peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void CEC_Cmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CFGR_PE_BB = (uint32_t)NewState; + + if(NewState == DISABLE) + { + /* Wait until the PE bit is cleared by hardware (Idle Line detected) */ + while((CEC->CFGR & CEC_CFGR_PE) != (uint32_t)RESET) + { + } + } +} + +/** + * @brief Enables or disables the CEC interrupt. + * @param NewState: new state of the CEC interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void CEC_ITConfig(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CFGR_IE_BB = (uint32_t)NewState; +} + +/** + * @brief Defines the Own Address of the CEC device. + * @param CEC_OwnAddress: The CEC own address + * @retval None + */ +void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress) +{ + /* Check the parameters */ + assert_param(IS_CEC_ADDRESS(CEC_OwnAddress)); + + /* Set the CEC own address */ + CEC->OAR = CEC_OwnAddress; +} + +/** + * @brief Sets the CEC prescaler value. + * @param CEC_Prescaler: CEC prescaler new value + * @retval None + */ +void CEC_SetPrescaler(uint16_t CEC_Prescaler) +{ + /* Check the parameters */ + assert_param(IS_CEC_PRESCALER(CEC_Prescaler)); + + /* Set the Prescaler value*/ + CEC->PRES = CEC_Prescaler; +} + +/** + * @brief Transmits single data through the CEC peripheral. + * @param Data: the data to transmit. + * @retval None + */ +void CEC_SendDataByte(uint8_t Data) +{ + /* Transmit Data */ + CEC->TXD = Data ; +} + + +/** + * @brief Returns the most recent received data by the CEC peripheral. + * @param None + * @retval The received data. + */ +uint8_t CEC_ReceiveDataByte(void) +{ + /* Receive Data */ + return (uint8_t)(CEC->RXD); +} + +/** + * @brief Starts a new message. + * @param None + * @retval None + */ +void CEC_StartOfMessage(void) +{ + /* Starts of new message */ + *(__IO uint32_t *) CSR_TSOM_BB = (uint32_t)0x1; +} + +/** + * @brief Transmits message with or without an EOM bit. + * @param NewState: new state of the CEC Tx End Of Message. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void CEC_EndOfMessageCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* The data byte will be transmitted with or without an EOM bit*/ + *(__IO uint32_t *) CSR_TEOM_BB = (uint32_t)NewState; +} + +/** + * @brief Gets the CEC flag status + * @param CEC_FLAG: specifies the CEC flag to check. + * This parameter can be one of the following values: + * @arg CEC_FLAG_BTE: Bit Timing Error + * @arg CEC_FLAG_BPE: Bit Period Error + * @arg CEC_FLAG_RBTFE: Rx Block Transfer Finished Error + * @arg CEC_FLAG_SBE: Start Bit Error + * @arg CEC_FLAG_ACKE: Block Acknowledge Error + * @arg CEC_FLAG_LINE: Line Error + * @arg CEC_FLAG_TBTFE: Tx Block Transfer Finished Error + * @arg CEC_FLAG_TEOM: Tx End Of Message + * @arg CEC_FLAG_TERR: Tx Error + * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished + * @arg CEC_FLAG_RSOM: Rx Start Of Message + * @arg CEC_FLAG_REOM: Rx End Of Message + * @arg CEC_FLAG_RERR: Rx Error + * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished + * @retval The new state of CEC_FLAG (SET or RESET) + */ +FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t cecreg = 0, cecbase = 0; + + /* Check the parameters */ + assert_param(IS_CEC_GET_FLAG(CEC_FLAG)); + + /* Get the CEC peripheral base address */ + cecbase = (uint32_t)(CEC_BASE); + + /* Read flag register index */ + cecreg = CEC_FLAG >> 28; + + /* Get bit[23:0] of the flag */ + CEC_FLAG &= FLAG_Mask; + + if(cecreg != 0) + { + /* Flag in CEC ESR Register */ + CEC_FLAG = (uint32_t)(CEC_FLAG >> 16); + + /* Get the CEC ESR register address */ + cecbase += 0xC; + } + else + { + /* Get the CEC CSR register address */ + cecbase += 0x10; + } + + if(((*(__IO uint32_t *)cecbase) & CEC_FLAG) != (uint32_t)RESET) + { + /* CEC_FLAG is set */ + bitstatus = SET; + } + else + { + /* CEC_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the CEC_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the CEC's pending flags. + * @param CEC_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg CEC_FLAG_TERR: Tx Error + * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished + * @arg CEC_FLAG_RSOM: Rx Start Of Message + * @arg CEC_FLAG_REOM: Rx End Of Message + * @arg CEC_FLAG_RERR: Rx Error + * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished + * @retval None + */ +void CEC_ClearFlag(uint32_t CEC_FLAG) +{ + uint32_t tmp = 0x0; + + /* Check the parameters */ + assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG)); + + tmp = CEC->CSR & 0x2; + + /* Clear the selected CEC flags */ + CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_FLAG) & 0xFFFFFFFC) | tmp); +} + +/** + * @brief Checks whether the specified CEC interrupt has occurred or not. + * @param CEC_IT: specifies the CEC interrupt source to check. + * This parameter can be one of the following values: + * @arg CEC_IT_TERR: Tx Error + * @arg CEC_IT_TBTF: Tx Block Transfer Finished + * @arg CEC_IT_RERR: Rx Error + * @arg CEC_IT_RBTF: Rx Block Transfer Finished + * @retval The new state of CEC_IT (SET or RESET). + */ +ITStatus CEC_GetITStatus(uint8_t CEC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_CEC_GET_IT(CEC_IT)); + + /* Get the CEC IT enable bit status */ + enablestatus = (CEC->CFGR & (uint8_t)CEC_CFGR_IE) ; + + /* Check the status of the specified CEC interrupt */ + if (((CEC->CSR & CEC_IT) != (uint32_t)RESET) && enablestatus) + { + /* CEC_IT is set */ + bitstatus = SET; + } + else + { + /* CEC_IT is reset */ + bitstatus = RESET; + } + /* Return the CEC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the CEC's interrupt pending bits. + * @param CEC_IT: specifies the CEC interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg CEC_IT_TERR: Tx Error + * @arg CEC_IT_TBTF: Tx Block Transfer Finished + * @arg CEC_IT_RERR: Rx Error + * @arg CEC_IT_RBTF: Rx Block Transfer Finished + * @retval None + */ +void CEC_ClearITPendingBit(uint16_t CEC_IT) +{ + uint32_t tmp = 0x0; + + /* Check the parameters */ + assert_param(IS_CEC_GET_IT(CEC_IT)); + + tmp = CEC->CSR & 0x2; + + /* Clear the selected CEC interrupt pending bits */ + CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_IT) & 0xFFFFFFFC) | tmp); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/STM32F10x_FWLIB/src/stm32f10x_crc.c b/STM32F10x_FWLIB/src/stm32f10x_crc.c new file mode 100644 index 0000000..641c491 --- /dev/null +++ b/STM32F10x_FWLIB/src/stm32f10x_crc.c @@ -0,0 +1,158 @@ +/** + ****************************************************************************** + * @file stm32f10x_crc.c + * @author MCD Application Team + * @version V3.6.2 + * @date 17-September-2021 + * @brief This file provides all the CRC firmware functions. + ****************************************************************************** + * @attention + * + * Copyright (c) 2012 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_crc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup CRC + * @brief CRC driver modules + * @{ + */ + +/** @defgroup CRC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Private_Defines + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Private_Functions + * @{ + */ + +/** + * @brief Resets the CRC Data register (DR). + * @param None + * @retval None + */ +void CRC_ResetDR(void) +{ + /* Reset CRC generator */ + CRC->CR = CRC_CR_RESET; +} + +/** + * @brief Computes the 32-bit CRC of a given data word(32-bit). + * @param Data: data word(32-bit) to compute its CRC + * @retval 32-bit CRC + */ +uint32_t CRC_CalcCRC(uint32_t Data) +{ + CRC->DR = Data; + + return (CRC->DR); +} + +/** + * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). + * @param pBuffer: pointer to the buffer containing the data to be computed + * @param BufferLength: length of the buffer to be computed + * @retval 32-bit CRC + */ +uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) +{ + uint32_t index = 0; + + for(index = 0; index < BufferLength; index++) + { + CRC->DR = pBuffer[index]; + } + return (CRC->DR); +} + +/** + * @brief Returns the current CRC value. + * @param None + * @retval 32-bit CRC + */ +uint32_t CRC_GetCRC(void) +{ + return (CRC->DR); +} + +/** + * @brief Stores a 8-bit data in the Independent Data(ID) register. + * @param IDValue: 8-bit value to be stored in the ID register + * @retval None + */ +void CRC_SetIDRegister(uint8_t IDValue) +{ + CRC->IDR = IDValue; +} + +/** + * @brief Returns the 8-bit data stored in the Independent Data(ID) register + * @param None + * @retval 8-bit value of the ID register + */ +uint8_t CRC_GetIDRegister(void) +{ + return (CRC->IDR); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/STM32F10x_FWLIB/src/stm32f10x_dac.c b/STM32F10x_FWLIB/src/stm32f10x_dac.c new file mode 100644 index 0000000..65674fd --- /dev/null +++ b/STM32F10x_FWLIB/src/stm32f10x_dac.c @@ -0,0 +1,569 @@ +/** + ****************************************************************************** + * @file stm32f10x_dac.c + * @author MCD Application Team + * @version V3.6.2 + * @date 17-September-2021 + * @brief This file provides all the DAC firmware functions. + ****************************************************************************** + * @attention + * + * Copyright (c) 2012 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_dac.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup DAC + * @brief DAC driver modules + * @{ + */ + +/** @defgroup DAC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup DAC_Private_Defines + * @{ + */ + +/* CR register Mask */ +#define CR_CLEAR_MASK ((uint32_t)0x00000FFE) + +/* DAC Dual Channels SWTRIG masks */ +#define DUAL_SWTRIG_SET ((uint32_t)0x00000003) +#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC) + +/* DHR registers offsets */ +#define DHR12R1_OFFSET ((uint32_t)0x00000008) +#define DHR12R2_OFFSET ((uint32_t)0x00000014) +#define DHR12RD_OFFSET ((uint32_t)0x00000020) + +/* DOR register offset */ +#define DOR_OFFSET ((uint32_t)0x0000002C) +/** + * @} + */ + +/** @defgroup DAC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup DAC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup DAC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup DAC_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the DAC peripheral registers to their default reset values. + * @param None + * @retval None + */ +void DAC_DeInit(void) +{ + /* Enable DAC reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE); + /* Release DAC from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE); +} + +/** + * @brief Initializes the DAC peripheral according to the specified + * parameters in the DAC_InitStruct. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that + * contains the configuration information for the specified DAC channel. + * @retval None + */ +void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + /* Check the DAC parameters */ + assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger)); + assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration)); + assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude)); + assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer)); +/*---------------------------- DAC CR Configuration --------------------------*/ + /* Get the DAC CR value */ + tmpreg1 = DAC->CR; + /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ + tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel); + /* Configure for the selected DAC channel: buffer output, trigger, wave generation, + mask/amplitude for wave generation */ + /* Set TSELx and TENx bits according to DAC_Trigger value */ + /* Set WAVEx bits according to DAC_WaveGeneration value */ + /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ + /* Set BOFFx bit according to DAC_OutputBuffer value */ + tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration | + DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer); + /* Calculate CR register value depending on DAC_Channel */ + tmpreg1 |= tmpreg2 << DAC_Channel; + /* Write to DAC CR */ + DAC->CR = tmpreg1; +} + +/** + * @brief Fills each DAC_InitStruct member with its default value. + * @param DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct) +{ +/*--------------- Reset DAC init structure parameters values -----------------*/ + /* Initialize the DAC_Trigger member */ + DAC_InitStruct->DAC_Trigger = DAC_Trigger_None; + /* Initialize the DAC_WaveGeneration member */ + DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None; + /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */ + DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0; + /* Initialize the DAC_OutputBuffer member */ + DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable; +} + +/** + * @brief Enables or disables the specified DAC channel. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param NewState: new state of the DAC channel. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected DAC channel */ + DAC->CR |= (DAC_CR_EN1 << DAC_Channel); + } + else + { + /* Disable the selected DAC channel */ + DAC->CR &= ~(DAC_CR_EN1 << DAC_Channel); + } +} +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +/** + * @brief Enables or disables the specified DAC interrupts. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. + * This parameter can be the following values: + * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask + * @param NewState: new state of the specified DAC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_DAC_IT(DAC_IT)); + + if (NewState != DISABLE) + { + /* Enable the selected DAC interrupts */ + DAC->CR |= (DAC_IT << DAC_Channel); + } + else + { + /* Disable the selected DAC interrupts */ + DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel)); + } +} +#endif + +/** + * @brief Enables or disables the specified DAC channel DMA request. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param NewState: new state of the selected DAC channel DMA request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected DAC channel DMA request */ + DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel); + } + else + { + /* Disable the selected DAC channel DMA request */ + DAC->CR &= ~(DAC_CR_DMAEN1 << DAC_Channel); + } +} + +/** + * @brief Enables or disables the selected DAC channel software trigger. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param NewState: new state of the selected DAC channel software trigger. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable software trigger for the selected DAC channel */ + DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4); + } + else + { + /* Disable software trigger for the selected DAC channel */ + DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4)); + } +} + +/** + * @brief Enables or disables simultaneously the two DAC channels software + * triggers. + * @param NewState: new state of the DAC channels software triggers. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_DualSoftwareTriggerCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable software trigger for both DAC channels */ + DAC->SWTRIGR |= DUAL_SWTRIG_SET ; + } + else + { + /* Disable software trigger for both DAC channels */ + DAC->SWTRIGR &= DUAL_SWTRIG_RESET; + } +} + +/** + * @brief Enables or disables the selected DAC channel wave generation. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_Wave: Specifies the wave type to enable or disable. + * This parameter can be one of the following values: + * @arg DAC_Wave_Noise: noise wave generation + * @arg DAC_Wave_Triangle: triangle wave generation + * @param NewState: new state of the selected DAC channel wave generation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_WAVE(DAC_Wave)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected wave generation for the selected DAC channel */ + DAC->CR |= DAC_Wave << DAC_Channel; + } + else + { + /* Disable the selected wave generation for the selected DAC channel */ + DAC->CR &= ~(DAC_Wave << DAC_Channel); + } +} + +/** + * @brief Set the specified data holding register value for DAC channel1. + * @param DAC_Align: Specifies the data alignment for DAC channel1. + * This parameter can be one of the following values: + * @arg DAC_Align_8b_R: 8bit right data alignment selected + * @arg DAC_Align_12b_L: 12bit left data alignment selected + * @arg DAC_Align_12b_R: 12bit right data alignment selected + * @param Data : Data to be loaded in the selected data holding register. + * @retval None + */ +void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(DAC_Align)); + assert_param(IS_DAC_DATA(Data)); + + tmp = (uint32_t)DAC_BASE; + tmp += DHR12R1_OFFSET + DAC_Align; + + /* Set the DAC channel1 selected data holding register */ + *(__IO uint32_t *) tmp = Data; +} + +/** + * @brief Set the specified data holding register value for DAC channel2. + * @param DAC_Align: Specifies the data alignment for DAC channel2. + * This parameter can be one of the following values: + * @arg DAC_Align_8b_R: 8bit right data alignment selected + * @arg DAC_Align_12b_L: 12bit left data alignment selected + * @arg DAC_Align_12b_R: 12bit right data alignment selected + * @param Data : Data to be loaded in the selected data holding register. + * @retval None + */ +void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(DAC_Align)); + assert_param(IS_DAC_DATA(Data)); + + tmp = (uint32_t)DAC_BASE; + tmp += DHR12R2_OFFSET + DAC_Align; + + /* Set the DAC channel2 selected data holding register */ + *(__IO uint32_t *)tmp = Data; +} + +/** + * @brief Set the specified data holding register value for dual channel + * DAC. + * @param DAC_Align: Specifies the data alignment for dual channel DAC. + * This parameter can be one of the following values: + * @arg DAC_Align_8b_R: 8bit right data alignment selected + * @arg DAC_Align_12b_L: 12bit left data alignment selected + * @arg DAC_Align_12b_R: 12bit right data alignment selected + * @param Data2: Data for DAC Channel2 to be loaded in the selected data + * holding register. + * @param Data1: Data for DAC Channel1 to be loaded in the selected data + * holding register. + * @retval None + */ +void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1) +{ + uint32_t data = 0, tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(DAC_Align)); + assert_param(IS_DAC_DATA(Data1)); + assert_param(IS_DAC_DATA(Data2)); + + /* Calculate and set dual DAC data holding register value */ + if (DAC_Align == DAC_Align_8b_R) + { + data = ((uint32_t)Data2 << 8) | Data1; + } + else + { + data = ((uint32_t)Data2 << 16) | Data1; + } + + tmp = (uint32_t)DAC_BASE; + tmp += DHR12RD_OFFSET + DAC_Align; + + /* Set the dual DAC selected data holding register */ + *(__IO uint32_t *)tmp = data; +} + +/** + * @brief Returns the last data output value of the selected DAC channel. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @retval The selected DAC channel data output value. + */ +uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + + tmp = (uint32_t) DAC_BASE ; + tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2); + + /* Returns the DAC channel data output register value */ + return (uint16_t) (*(__IO uint32_t*) tmp); +} + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +/** + * @brief Checks whether the specified DAC flag is set or not. + * @param DAC_Channel: thee selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_FLAG: specifies the flag to check. + * This parameter can be only of the following value: + * @arg DAC_FLAG_DMAUDR: DMA underrun flag + * @retval The new state of DAC_FLAG (SET or RESET). + */ +FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_FLAG(DAC_FLAG)); + + /* Check the status of the specified DAC flag */ + if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET) + { + /* DAC_FLAG is set */ + bitstatus = SET; + } + else + { + /* DAC_FLAG is reset */ + bitstatus = RESET; + } + /* Return the DAC_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the DAC channelx's pending flags. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_FLAG: specifies the flag to clear. + * This parameter can be of the following value: + * @arg DAC_FLAG_DMAUDR: DMA underrun flag + * @retval None + */ +void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_FLAG(DAC_FLAG)); + + /* Clear the selected DAC flags */ + DAC->SR = (DAC_FLAG << DAC_Channel); +} + +/** + * @brief Checks whether the specified DAC interrupt has occurred or not. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_IT: specifies the DAC interrupt source to check. + * This parameter can be the following values: + * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask + * @retval The new state of DAC_IT (SET or RESET). + */ +ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_IT(DAC_IT)); + + /* Get the DAC_IT enable bit status */ + enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ; + + /* Check the status of the specified DAC interrupt */ + if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus) + { + /* DAC_IT is set */ + bitstatus = SET; + } + else + { + /* DAC_IT is reset */ + bitstatus = RESET; + } + /* Return the DAC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the DAC channelx's interrupt pending bits. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_IT: specifies the DAC interrupt pending bit to clear. + * This parameter can be the following values: + * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask + * @retval None + */ +void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_IT(DAC_IT)); + + /* Clear the selected DAC interrupt pending bits */ + DAC->SR = (DAC_IT << DAC_Channel); +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/STM32F10x_FWLIB/src/stm32f10x_dbgmcu.c b/STM32F10x_FWLIB/src/stm32f10x_dbgmcu.c new file mode 100644 index 0000000..4d9ae28 --- /dev/null +++ b/STM32F10x_FWLIB/src/stm32f10x_dbgmcu.c @@ -0,0 +1,160 @@ +/** + ****************************************************************************** + * @file stm32f10x_dbgmcu.c + * @author MCD Application Team + * @version V3.6.2 + * @date 17-September-2021 + * @brief This file provides all the DBGMCU firmware functions. + ****************************************************************************** + * @attention + * + * Copyright (c) 2012 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_dbgmcu.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup DBGMCU + * @brief DBGMCU driver modules + * @{ + */ + +/** @defgroup DBGMCU_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup DBGMCU_Private_Defines + * @{ + */ + +#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) +/** + * @} + */ + +/** @defgroup DBGMCU_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup DBGMCU_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup DBGMCU_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup DBGMCU_Private_Functions + * @{ + */ + +/** + * @brief Returns the device revision identifier. + * @param None + * @retval Device revision identifier + */ +uint32_t DBGMCU_GetREVID(void) +{ + return(DBGMCU->IDCODE >> 16); +} + +/** + * @brief Returns the device identifier. + * @param None + * @retval Device identifier + */ +uint32_t DBGMCU_GetDEVID(void) +{ + return(DBGMCU->IDCODE & IDCODE_DEVID_MASK); +} + +/** + * @brief Configures the specified peripheral and low power mode behavior + * when the MCU under Debug mode. + * @param DBGMCU_Periph: specifies the peripheral and low power mode. + * This parameter can be any combination of the following values: + * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode + * @arg DBGMCU_STOP: Keep debugger connection during STOP mode + * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode + * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted + * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted + * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted + * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted + * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted + * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted + * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted + * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted + * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted + * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted + * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted + * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted + * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted + * @arg DBGMCU_CAN2_STOP: Debug CAN2 stopped when Core is halted + * @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted + * @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted + * @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted + * @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted + * @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted + * @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted + * @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted + * @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted + * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted + * @param NewState: new state of the specified peripheral in Debug mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + DBGMCU->CR |= DBGMCU_Periph; + } + else + { + DBGMCU->CR &= ~DBGMCU_Periph; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/STM32F10x_FWLIB/src/stm32f10x_dma.c b/STM32F10x_FWLIB/src/stm32f10x_dma.c new file mode 100644 index 0000000..2d73c8a --- /dev/null +++ b/STM32F10x_FWLIB/src/stm32f10x_dma.c @@ -0,0 +1,712 @@ +/** + ****************************************************************************** + * @file stm32f10x_dma.c + * @author MCD Application Team + * @version V3.6.2 + * @date 17-September-2021 + * @brief This file provides all the DMA firmware functions. + ****************************************************************************** + * @attention + * + * Copyright (c) 2012 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_dma.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup DMA + * @brief DMA driver modules + * @{ + */ + +/** @defgroup DMA_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + +/** @defgroup DMA_Private_Defines + * @{ + */ + + +/* DMA1 Channelx interrupt pending bit masks */ +#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1)) +#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2)) +#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3)) +#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4)) +#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5)) +#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6)) +#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7)) + +/* DMA2 Channelx interrupt pending bit masks */ +#define DMA2_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1)) +#define DMA2_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2)) +#define DMA2_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3)) +#define DMA2_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4)) +#define DMA2_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5)) + +/* DMA2 FLAG mask */ +#define FLAG_Mask ((uint32_t)0x10000000) + +/* DMA registers Masks */ +#define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F) + +/** + * @} + */ + +/** @defgroup DMA_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup DMA_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup DMA_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup DMA_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the DMAy Channelx registers to their default reset + * values. + * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and + * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * @retval None + */ +void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + + /* Disable the selected DMAy Channelx */ + DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN); + + /* Reset DMAy Channelx control register */ + DMAy_Channelx->CCR = 0; + + /* Reset DMAy Channelx remaining bytes register */ + DMAy_Channelx->CNDTR = 0; + + /* Reset DMAy Channelx peripheral address register */ + DMAy_Channelx->CPAR = 0; + + /* Reset DMAy Channelx memory address register */ + DMAy_Channelx->CMAR = 0; + + if (DMAy_Channelx == DMA1_Channel1) + { + /* Reset interrupt pending bits for DMA1 Channel1 */ + DMA1->IFCR |= DMA1_Channel1_IT_Mask; + } + else if (DMAy_Channelx == DMA1_Channel2) + { + /* Reset interrupt pending bits for DMA1 Channel2 */ + DMA1->IFCR |= DMA1_Channel2_IT_Mask; + } + else if (DMAy_Channelx == DMA1_Channel3) + { + /* Reset interrupt pending bits for DMA1 Channel3 */ + DMA1->IFCR |= DMA1_Channel3_IT_Mask; + } + else if (DMAy_Channelx == DMA1_Channel4) + { + /* Reset interrupt pending bits for DMA1 Channel4 */ + DMA1->IFCR |= DMA1_Channel4_IT_Mask; + } + else if (DMAy_Channelx == DMA1_Channel5) + { + /* Reset interrupt pending bits for DMA1 Channel5 */ + DMA1->IFCR |= DMA1_Channel5_IT_Mask; + } + else if (DMAy_Channelx == DMA1_Channel6) + { + /* Reset interrupt pending bits for DMA1 Channel6 */ + DMA1->IFCR |= DMA1_Channel6_IT_Mask; + } + else if (DMAy_Channelx == DMA1_Channel7) + { + /* Reset interrupt pending bits for DMA1 Channel7 */ + DMA1->IFCR |= DMA1_Channel7_IT_Mask; + } + else if (DMAy_Channelx == DMA2_Channel1) + { + /* Reset interrupt pending bits for DMA2 Channel1 */ + DMA2->IFCR |= DMA2_Channel1_IT_Mask; + } + else if (DMAy_Channelx == DMA2_Channel2) + { + /* Reset interrupt pending bits for DMA2 Channel2 */ + DMA2->IFCR |= DMA2_Channel2_IT_Mask; + } + else if (DMAy_Channelx == DMA2_Channel3) + { + /* Reset interrupt pending bits for DMA2 Channel3 */ + DMA2->IFCR |= DMA2_Channel3_IT_Mask; + } + else if (DMAy_Channelx == DMA2_Channel4) + { + /* Reset interrupt pending bits for DMA2 Channel4 */ + DMA2->IFCR |= DMA2_Channel4_IT_Mask; + } + else + { + if (DMAy_Channelx == DMA2_Channel5) + { + /* Reset interrupt pending bits for DMA2 Channel5 */ + DMA2->IFCR |= DMA2_Channel5_IT_Mask; + } + } +} + +/** + * @brief Initializes the DMAy Channelx according to the specified + * parameters in the DMA_InitStruct. + * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and + * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that + * contains the configuration information for the specified DMA Channel. + * @retval None + */ +void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR)); + assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize)); + assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc)); + assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); + assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize)); + assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize)); + assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode)); + assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority)); + assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M)); + +/*--------------------------- DMAy Channelx CCR Configuration -----------------*/ + /* Get the DMAy_Channelx CCR value */ + tmpreg = DMAy_Channelx->CCR; + /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ + tmpreg &= CCR_CLEAR_Mask; + /* Configure DMAy Channelx: data transfer, data size, priority level and mode */ + /* Set DIR bit according to DMA_DIR value */ + /* Set CIRC bit according to DMA_Mode value */ + /* Set PINC bit according to DMA_PeripheralInc value */ + /* Set MINC bit according to DMA_MemoryInc value */ + /* Set PSIZE bits according to DMA_PeripheralDataSize value */ + /* Set MSIZE bits according to DMA_MemoryDataSize value */ + /* Set PL bits according to DMA_Priority value */ + /* Set the MEM2MEM bit according to DMA_M2M value */ + tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | + DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | + DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | + DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; + + /* Write to DMAy Channelx CCR */ + DMAy_Channelx->CCR = tmpreg; + +/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/ + /* Write to DMAy Channelx CNDTR */ + DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize; + +/*--------------------------- DMAy Channelx CPAR Configuration ----------------*/ + /* Write to DMAy Channelx CPAR */ + DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr; + +/*--------------------------- DMAy Channelx CMAR Configuration ----------------*/ + /* Write to DMAy Channelx CMAR */ + DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr; +} + +/** + * @brief Fills each DMA_InitStruct member with its default value. + * @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct) +{ +/*-------------- Reset DMA init structure parameters values ------------------*/ + /* Initialize the DMA_PeripheralBaseAddr member */ + DMA_InitStruct->DMA_PeripheralBaseAddr = 0; + /* Initialize the DMA_MemoryBaseAddr member */ + DMA_InitStruct->DMA_MemoryBaseAddr = 0; + /* Initialize the DMA_DIR member */ + DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; + /* Initialize the DMA_BufferSize member */ + DMA_InitStruct->DMA_BufferSize = 0; + /* Initialize the DMA_PeripheralInc member */ + DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; + /* Initialize the DMA_MemoryInc member */ + DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; + /* Initialize the DMA_PeripheralDataSize member */ + DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + /* Initialize the DMA_MemoryDataSize member */ + DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + /* Initialize the DMA_Mode member */ + DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; + /* Initialize the DMA_Priority member */ + DMA_InitStruct->DMA_Priority = DMA_Priority_Low; + /* Initialize the DMA_M2M member */ + DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; +} + +/** + * @brief Enables or disables the specified DMAy Channelx. + * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and + * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * @param NewState: new state of the DMAy Channelx. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMAy Channelx */ + DMAy_Channelx->CCR |= DMA_CCR1_EN; + } + else + { + /* Disable the selected DMAy Channelx */ + DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN); + } +} + +/** + * @brief Enables or disables the specified DMAy Channelx interrupts. + * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and + * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * @param DMA_IT: specifies the DMA interrupts sources to be enabled + * or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @param NewState: new state of the specified DMA interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + assert_param(IS_DMA_CONFIG_IT(DMA_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected DMA interrupts */ + DMAy_Channelx->CCR |= DMA_IT; + } + else + { + /* Disable the selected DMA interrupts */ + DMAy_Channelx->CCR &= ~DMA_IT; + } +} + +/** + * @brief Sets the number of data units in the current DMAy Channelx transfer. + * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and + * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * @param DataNumber: The number of data units in the current DMAy Channelx + * transfer. + * @note This function can only be used when the DMAy_Channelx is disabled. + * @retval None. + */ +void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + +/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/ + /* Write to DMAy Channelx CNDTR */ + DMAy_Channelx->CNDTR = DataNumber; +} + +/** + * @brief Returns the number of remaining data units in the current + * DMAy Channelx transfer. + * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and + * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * @retval The number of remaining data units in the current DMAy Channelx + * transfer. + */ +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + /* Return the number of remaining data units for DMAy Channelx */ + return ((uint16_t)(DMAy_Channelx->CNDTR)); +} + +/** + * @brief Checks whether the specified DMAy Channelx flag is set or not. + * @param DMAy_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. + * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. + * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. + * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. + * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. + * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. + * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. + * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. + * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. + * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. + * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. + * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. + * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. + * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. + * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. + * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. + * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. + * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. + * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. + * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. + * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag. + * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. + * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. + * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag. + * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag. + * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. + * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. + * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag. + * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag. + * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag. + * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag. + * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag. + * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag. + * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag. + * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag. + * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag. + * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag. + * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag. + * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag. + * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag. + * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag. + * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag. + * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag. + * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag. + * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag. + * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag. + * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag. + * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag. + * @retval The new state of DMAy_FLAG (SET or RESET). + */ +FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_DMA_GET_FLAG(DMAy_FLAG)); + + /* Calculate the used DMAy */ + if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET) + { + /* Get DMA2 ISR register value */ + tmpreg = DMA2->ISR ; + } + else + { + /* Get DMA1 ISR register value */ + tmpreg = DMA1->ISR ; + } + + /* Check the status of the specified DMAy flag */ + if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET) + { + /* DMAy_FLAG is set */ + bitstatus = SET; + } + else + { + /* DMAy_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the DMAy_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the DMAy Channelx's pending flags. + * @param DMAy_FLAG: specifies the flag to clear. + * This parameter can be any combination (for the same DMA) of the following values: + * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. + * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. + * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. + * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. + * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. + * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. + * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. + * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. + * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. + * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. + * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. + * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. + * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. + * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. + * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. + * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. + * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. + * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. + * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. + * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. + * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag. + * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. + * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. + * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag. + * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag. + * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. + * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. + * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag. + * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag. + * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag. + * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag. + * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag. + * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag. + * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag. + * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag. + * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag. + * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag. + * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag. + * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag. + * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag. + * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag. + * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag. + * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag. + * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag. + * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag. + * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag. + * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag. + * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag. + * @retval None + */ +void DMA_ClearFlag(uint32_t DMAy_FLAG) +{ + /* Check the parameters */ + assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG)); + + /* Calculate the used DMAy */ + if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET) + { + /* Clear the selected DMAy flags */ + DMA2->IFCR = DMAy_FLAG; + } + else + { + /* Clear the selected DMAy flags */ + DMA1->IFCR = DMAy_FLAG; + } +} + +/** + * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not. + * @param DMAy_IT: specifies the DMAy interrupt source to check. + * This parameter can be one of the following values: + * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. + * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. + * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. + * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. + * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. + * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. + * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. + * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. + * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. + * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. + * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. + * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. + * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. + * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. + * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. + * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. + * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. + * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. + * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. + * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. + * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt. + * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt. + * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt. + * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt. + * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt. + * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt. + * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt. + * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt. + * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt. + * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt. + * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt. + * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt. + * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt. + * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt. + * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt. + * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt. + * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt. + * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt. + * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt. + * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt. + * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt. + * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt. + * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt. + * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt. + * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt. + * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt. + * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt. + * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt. + * @retval The new state of DMAy_IT (SET or RESET). + */ +ITStatus DMA_GetITStatus(uint32_t DMAy_IT) +{ + ITStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_DMA_GET_IT(DMAy_IT)); + + /* Calculate the used DMA */ + if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET) + { + /* Get DMA2 ISR register value */ + tmpreg = DMA2->ISR; + } + else + { + /* Get DMA1 ISR register value */ + tmpreg = DMA1->ISR; + } + + /* Check the status of the specified DMAy interrupt */ + if ((tmpreg & DMAy_IT) != (uint32_t)RESET) + { + /* DMAy_IT is set */ + bitstatus = SET; + } + else + { + /* DMAy_IT is reset */ + bitstatus = RESET; + } + /* Return the DMA_IT status */ + return bitstatus; +} + +/** + * @brief Clears the DMAy Channelx's interrupt pending bits. + * @param DMAy_IT: specifies the DMAy interrupt pending bit to clear. + * This parameter can be any combination (for the same DMA) of the following values: + * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. + * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. + * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. + * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. + * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. + * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. + * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. + * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. + * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. + * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. + * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. + * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. + * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. + * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. + * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. + * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. + * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. + * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. + * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. + * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. + * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt. + * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt. + * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt. + * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt. + * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt. + * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt. + * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt. + * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt. + * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt. + * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt. + * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt. + * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt. + * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt. + * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt. + * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt. + * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt. + * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt. + * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt. + * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt. + * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt. + * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt. + * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt. + * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt. + * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt. + * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt. + * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt. + * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt. + * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt. + * @retval None + */ +void DMA_ClearITPendingBit(uint32_t DMAy_IT) +{ + /* Check the parameters */ + assert_param(IS_DMA_CLEAR_IT(DMAy_IT)); + + /* Calculate the used DMAy */ + if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET) + { + /* Clear the selected DMAy interrupt pending bits */ + DMA2->IFCR = DMAy_IT; + } + else + { + /* Clear the selected DMAy interrupt pending bits */ + DMA1->IFCR = DMAy_IT; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/STM32F10x_FWLIB/src/stm32f10x_exti.c b/STM32F10x_FWLIB/src/stm32f10x_exti.c new file mode 100644 index 0000000..85a81d5 --- /dev/null +++ b/STM32F10x_FWLIB/src/stm32f10x_exti.c @@ -0,0 +1,267 @@ +/** + ****************************************************************************** + * @file stm32f10x_exti.c + * @author MCD Application Team + * @version V3.6.2 + * @date 17-September-2021 + * @brief This file provides all the EXTI firmware functions. + ****************************************************************************** + * @attention + * + * Copyright (c) 2012 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_exti.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup EXTI + * @brief EXTI driver modules + * @{ + */ + +/** @defgroup EXTI_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup EXTI_Private_Defines + * @{ + */ + +#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */ + +/** + * @} + */ + +/** @defgroup EXTI_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup EXTI_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup EXTI_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup EXTI_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the EXTI peripheral registers to their default reset values. + * @param None + * @retval None + */ +void EXTI_DeInit(void) +{ + EXTI->IMR = 0x00000000; + EXTI->EMR = 0x00000000; + EXTI->RTSR = 0x00000000; + EXTI->FTSR = 0x00000000; + EXTI->PR = 0x000FFFFF; +} + +/** + * @brief Initializes the EXTI peripheral according to the specified + * parameters in the EXTI_InitStruct. + * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure + * that contains the configuration information for the EXTI peripheral. + * @retval None + */ +void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) +{ + uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode)); + assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger)); + assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); + assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd)); + + tmp = (uint32_t)EXTI_BASE; + + if (EXTI_InitStruct->EXTI_LineCmd != DISABLE) + { + /* Clear EXTI line configuration */ + EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line; + + tmp += EXTI_InitStruct->EXTI_Mode; + + *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; + + /* Clear Rising Falling edge configuration */ + EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line; + + /* Select the trigger for the selected external interrupts */ + if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) + { + /* Rising Falling edge */ + EXTI->RTSR |= EXTI_InitStruct->EXTI_Line; + EXTI->FTSR |= EXTI_InitStruct->EXTI_Line; + } + else + { + tmp = (uint32_t)EXTI_BASE; + tmp += EXTI_InitStruct->EXTI_Trigger; + + *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; + } + } + else + { + tmp += EXTI_InitStruct->EXTI_Mode; + + /* Disable the selected external lines */ + *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line; + } +} + +/** + * @brief Fills each EXTI_InitStruct member with its reset value. + * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct) +{ + EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; + EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; + EXTI_InitStruct->EXTI_LineCmd = DISABLE; +} + +/** + * @brief Generates a Software interrupt. + * @param EXTI_Line: specifies the EXTI lines to be enabled or disabled. + * This parameter can be any combination of EXTI_Linex where x can be (0..19). + * @retval None + */ +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->SWIER |= EXTI_Line; +} + +/** + * @brief Checks whether the specified EXTI line flag is set or not. + * @param EXTI_Line: specifies the EXTI line flag to check. + * This parameter can be: + * @arg EXTI_Linex: External interrupt line x where x(0..19) + * @retval The new state of EXTI_Line (SET or RESET). + */ +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_GET_EXTI_LINE(EXTI_Line)); + + if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the EXTI's line pending flags. + * @param EXTI_Line: specifies the EXTI lines flags to clear. + * This parameter can be any combination of EXTI_Linex where x can be (0..19). + * @retval None + */ +void EXTI_ClearFlag(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->PR = EXTI_Line; +} + +/** + * @brief Checks whether the specified EXTI line is asserted or not. + * @param EXTI_Line: specifies the EXTI line to check. + * This parameter can be: + * @arg EXTI_Linex: External interrupt line x where x(0..19) + * @retval The new state of EXTI_Line (SET or RESET). + */ +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + /* Check the parameters */ + assert_param(IS_GET_EXTI_LINE(EXTI_Line)); + + enablestatus = EXTI->IMR & EXTI_Line; + if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the EXTI's line pending bits. + * @param EXTI_Line: specifies the EXTI lines to clear. + * This parameter can be any combination of EXTI_Linex where x can be (0..19). + * @retval None + */ +void EXTI_ClearITPendingBit(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->PR = EXTI_Line; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/STM32F10x_FWLIB/src/stm32f10x_flash.c b/STM32F10x_FWLIB/src/stm32f10x_flash.c new file mode 100644 index 0000000..9263dbe --- /dev/null +++ b/STM32F10x_FWLIB/src/stm32f10x_flash.c @@ -0,0 +1,1677 @@ +/** + ****************************************************************************** + * @file stm32f10x_flash.c + * @author MCD Application Team + * @version V3.6.2 + * @date 17-September-2021 + * @brief This file provides all the FLASH firmware functions. + ****************************************************************************** + * @attention + * + * Copyright (c) 2012 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_flash.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup FLASH + * @brief FLASH driver modules + * @{ + */ + +/** @defgroup FLASH_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup FLASH_Private_Defines + * @{ + */ + +/* Flash Access Control Register bits */ +#define ACR_LATENCY_Mask ((uint32_t)0x00000038) +#define ACR_HLFCYA_Mask ((uint32_t)0xFFFFFFF7) +#define ACR_PRFTBE_Mask ((uint32_t)0xFFFFFFEF) + +/* Flash Access Control Register bits */ +#define ACR_PRFTBS_Mask ((uint32_t)0x00000020) + +/* Flash Control Register bits */ +#define CR_PG_Set ((uint32_t)0x00000001) +#define CR_PG_Reset ((uint32_t)0x00001FFE) +#define CR_PER_Set ((uint32_t)0x00000002) +#define CR_PER_Reset ((uint32_t)0x00001FFD) +#define CR_MER_Set ((uint32_t)0x00000004) +#define CR_MER_Reset ((uint32_t)0x00001FFB) +#define CR_OPTPG_Set ((uint32_t)0x00000010) +#define CR_OPTPG_Reset ((uint32_t)0x00001FEF) +#define CR_OPTER_Set ((uint32_t)0x00000020) +#define CR_OPTER_Reset ((uint32_t)0x00001FDF) +#define CR_STRT_Set ((uint32_t)0x00000040) +#define CR_LOCK_Set ((uint32_t)0x00000080) + +/* FLASH Mask */ +#define RDPRT_Mask ((uint32_t)0x00000002) +#define WRP0_Mask ((uint32_t)0x000000FF) +#define WRP1_Mask ((uint32_t)0x0000FF00) +#define WRP2_Mask ((uint32_t)0x00FF0000) +#define WRP3_Mask ((uint32_t)0xFF000000) +#define OB_USER_BFB2 ((uint16_t)0x0008) + +/* FLASH BANK address */ +#define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF) + +/* Delay definition */ +#define EraseTimeout ((uint32_t)0x000B0000) +#define ProgramTimeout ((uint32_t)0x00002000) +/** + * @} + */ + +/** @defgroup FLASH_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup FLASH_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup FLASH_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup FLASH_Private_Functions + * @{ + */ + +/** +@code + + This driver provides functions to configure and program the Flash memory of all STM32F10x devices, + including the latest STM32F10x_XL density devices. + + STM32F10x_XL devices feature up to 1 Mbyte with dual bank architecture for read-while-write (RWW) capability: + - bank1: fixed size of 512 Kbytes (256 pages of 2Kbytes each) + - bank2: up to 512 Kbytes (up to 256 pages of 2Kbytes each) + While other STM32F10x devices features only one bank with memory up to 512 Kbytes. + + In version V3.3.0, some functions were updated and new ones were added to support + STM32F10x_XL devices. Thus some functions manages all devices, while other are + dedicated for XL devices only. + + The table below presents the list of available functions depending on the used STM32F10x devices. + + *************************************************** + * Legacy functions used for all STM32F10x devices * + *************************************************** + +----------------------------------------------------------------------------------------------------------------------------------+ + | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments | + | | devices | devices | | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_SetLatency | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_HalfCycleAccessCmd | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_PrefetchBufferCmd | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_Unlock | Yes | Yes | - For STM32F10X_XL devices: unlock Bank1 and Bank2. | + | | | | - For other devices: unlock Bank1 and it is equivalent | + | | | | to FLASH_UnlockBank1 function. | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_Lock | Yes | Yes | - For STM32F10X_XL devices: lock Bank1 and Bank2. | + | | | | - For other devices: lock Bank1 and it is equivalent | + | | | | to FLASH_LockBank1 function. | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_ErasePage | Yes | Yes | - For STM32F10x_XL devices: erase a page in Bank1 and Bank2 | + | | | | - For other devices: erase a page in Bank1 | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_EraseAllPages | Yes | Yes | - For STM32F10x_XL devices: erase all pages in Bank1 and Bank2 | + | | | | - For other devices: erase all pages in Bank1 | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_EraseOptionBytes | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_ProgramWord | Yes | Yes | Updated to program up to 1MByte (depending on the used device) | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_ProgramHalfWord | Yes | Yes | Updated to program up to 1MByte (depending on the used device) | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_ProgramOptionByteData | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_EnableWriteProtection | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_ReadOutProtection | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_UserOptionByteConfig | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_GetUserOptionByte | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_GetWriteProtectionOptionByte | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_GetReadOutProtectionStatus | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_GetPrefetchBufferStatus | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_ITConfig | Yes | Yes | - For STM32F10x_XL devices: enable Bank1 and Bank2's interrupts| + | | | | - For other devices: enable Bank1's interrupts | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_GetFlagStatus | Yes | Yes | - For STM32F10x_XL devices: return Bank1 and Bank2's flag status| + | | | | - For other devices: return Bank1's flag status | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_ClearFlag | Yes | Yes | - For STM32F10x_XL devices: clear Bank1 and Bank2's flag | + | | | | - For other devices: clear Bank1's flag | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_GetStatus | Yes | Yes | - Return the status of Bank1 (for all devices) | + | | | | equivalent to FLASH_GetBank1Status function | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_WaitForLastOperation | Yes | Yes | - Wait for Bank1 last operation (for all devices) | + | | | | equivalent to: FLASH_WaitForLastBank1Operation function | + +----------------------------------------------------------------------------------------------------------------------------------+ + + ************************************************************************************************************************ + * New functions used for all STM32F10x devices to manage Bank1: * + * - These functions are mainly useful for STM32F10x_XL density devices, to have separate control for Bank1 and bank2 * + * - For other devices, these functions are optional (covered by functions listed above) * + ************************************************************************************************************************ + +----------------------------------------------------------------------------------------------------------------------------------+ + | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments | + | | devices | devices | | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_UnlockBank1 | Yes | Yes | - Unlock Bank1 | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_LockBank1 | Yes | Yes | - Lock Bank1 | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_EraseAllBank1Pages | Yes | Yes | - Erase all pages in Bank1 | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_GetBank1Status | Yes | Yes | - Return the status of Bank1 | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_WaitForLastBank1Operation | Yes | Yes | - Wait for Bank1 last operation | + +----------------------------------------------------------------------------------------------------------------------------------+ + + ***************************************************************************** + * New Functions used only with STM32F10x_XL density devices to manage Bank2 * + ***************************************************************************** + +----------------------------------------------------------------------------------------------------------------------------------+ + | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments | + | | devices | devices | | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_UnlockBank2 | Yes | No | - Unlock Bank2 | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_LockBank2 | Yes | No | - Lock Bank2 | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_EraseAllBank2Pages | Yes | No | - Erase all pages in Bank2 | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_GetBank2Status | Yes | No | - Return the status of Bank2 | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_WaitForLastBank2Operation | Yes | No | - Wait for Bank2 last operation | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_BootConfig | Yes | No | - Configure to boot from Bank1 or Bank2 | + +----------------------------------------------------------------------------------------------------------------------------------+ +@endcode +*/ + + +/** + * @brief Sets the code latency value. + * @note This function can be used for all STM32F10x devices. + * @param FLASH_Latency: specifies the FLASH Latency value. + * This parameter can be one of the following values: + * @arg FLASH_Latency_0: FLASH Zero Latency cycle + * @arg FLASH_Latency_1: FLASH One Latency cycle + * @arg FLASH_Latency_2: FLASH Two Latency cycles + * @retval None + */ +void FLASH_SetLatency(uint32_t FLASH_Latency) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_FLASH_LATENCY(FLASH_Latency)); + + /* Read the ACR register */ + tmpreg = FLASH->ACR; + + /* Sets the Latency value */ + tmpreg &= ACR_LATENCY_Mask; + tmpreg |= FLASH_Latency; + + /* Write the ACR register */ + FLASH->ACR = tmpreg; +} + +/** + * @brief Enables or disables the Half cycle flash access. + * @note This function can be used for all STM32F10x devices. + * @param FLASH_HalfCycleAccess: specifies the FLASH Half cycle Access mode. + * This parameter can be one of the following values: + * @arg FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable + * @arg FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable + * @retval None + */ +void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess) +{ + /* Check the parameters */ + assert_param(IS_FLASH_HALFCYCLEACCESS_STATE(FLASH_HalfCycleAccess)); + + /* Enable or disable the Half cycle access */ + FLASH->ACR &= ACR_HLFCYA_Mask; + FLASH->ACR |= FLASH_HalfCycleAccess; +} + +/** + * @brief Enables or disables the Prefetch Buffer. + * @note This function can be used for all STM32F10x devices. + * @param FLASH_PrefetchBuffer: specifies the Prefetch buffer status. + * This parameter can be one of the following values: + * @arg FLASH_PrefetchBuffer_Enable: FLASH Prefetch Buffer Enable + * @arg FLASH_PrefetchBuffer_Disable: FLASH Prefetch Buffer Disable + * @retval None + */ +void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer) +{ + /* Check the parameters */ + assert_param(IS_FLASH_PREFETCHBUFFER_STATE(FLASH_PrefetchBuffer)); + + /* Enable or disable the Prefetch Buffer */ + FLASH->ACR &= ACR_PRFTBE_Mask; + FLASH->ACR |= FLASH_PrefetchBuffer; +} + +/** + * @brief Unlocks the FLASH Program Erase Controller. + * @note This function can be used for all STM32F10x devices. + * - For STM32F10X_XL devices this function unlocks Bank1 and Bank2. + * - For all other devices it unlocks Bank1 and it is equivalent + * to FLASH_UnlockBank1 function.. + * @param None + * @retval None + */ +void FLASH_Unlock(void) +{ + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + +#ifdef STM32F10X_XL + /* Authorize the FPEC of Bank2 Access */ + FLASH->KEYR2 = FLASH_KEY1; + FLASH->KEYR2 = FLASH_KEY2; +#endif /* STM32F10X_XL */ +} +/** + * @brief Unlocks the FLASH Bank1 Program Erase Controller. + * @note This function can be used for all STM32F10x devices. + * - For STM32F10X_XL devices this function unlocks Bank1. + * - For all other devices it unlocks Bank1 and it is + * equivalent to FLASH_Unlock function. + * @param None + * @retval None + */ +void FLASH_UnlockBank1(void) +{ + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; +} + +#ifdef STM32F10X_XL +/** + * @brief Unlocks the FLASH Bank2 Program Erase Controller. + * @note This function can be used only for STM32F10X_XL density devices. + * @param None + * @retval None + */ +void FLASH_UnlockBank2(void) +{ + /* Authorize the FPEC of Bank2 Access */ + FLASH->KEYR2 = FLASH_KEY1; + FLASH->KEYR2 = FLASH_KEY2; + +} +#endif /* STM32F10X_XL */ + +/** + * @brief Locks the FLASH Program Erase Controller. + * @note This function can be used for all STM32F10x devices. + * - For STM32F10X_XL devices this function Locks Bank1 and Bank2. + * - For all other devices it Locks Bank1 and it is equivalent + * to FLASH_LockBank1 function. + * @param None + * @retval None + */ +void FLASH_Lock(void) +{ + /* Set the Lock Bit to lock the FPEC and the CR of Bank1 */ + FLASH->CR |= CR_LOCK_Set; + +#ifdef STM32F10X_XL + /* Set the Lock Bit to lock the FPEC and the CR of Bank2 */ + FLASH->CR2 |= CR_LOCK_Set; +#endif /* STM32F10X_XL */ +} + +/** + * @brief Locks the FLASH Bank1 Program Erase Controller. + * @note this function can be used for all STM32F10x devices. + * - For STM32F10X_XL devices this function Locks Bank1. + * - For all other devices it Locks Bank1 and it is equivalent + * to FLASH_Lock function. + * @param None + * @retval None + */ +void FLASH_LockBank1(void) +{ + /* Set the Lock Bit to lock the FPEC and the CR of Bank1 */ + FLASH->CR |= CR_LOCK_Set; +} + +#ifdef STM32F10X_XL +/** + * @brief Locks the FLASH Bank2 Program Erase Controller. + * @note This function can be used only for STM32F10X_XL density devices. + * @param None + * @retval None + */ +void FLASH_LockBank2(void) +{ + /* Set the Lock Bit to lock the FPEC and the CR of Bank2 */ + FLASH->CR2 |= CR_LOCK_Set; +} +#endif /* STM32F10X_XL */ + +/** + * @brief Erases a specified FLASH page. + * @note This function can be used for all STM32F10x devices. + * @param Page_Address: The page address to be erased. + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ErasePage(uint32_t Page_Address) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Page_Address)); + +#ifdef STM32F10X_XL + if(Page_Address < FLASH_BANK1_END_ADDRESS) + { + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase the page */ + FLASH->CR|= CR_PER_Set; + FLASH->AR = Page_Address; + FLASH->CR|= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(EraseTimeout); + + /* Disable the PER Bit */ + FLASH->CR &= CR_PER_Reset; + } + } + else + { + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase the page */ + FLASH->CR2|= CR_PER_Set; + FLASH->AR2 = Page_Address; + FLASH->CR2|= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(EraseTimeout); + + /* Disable the PER Bit */ + FLASH->CR2 &= CR_PER_Reset; + } + } +#else + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase the page */ + FLASH->CR|= CR_PER_Set; + FLASH->AR = Page_Address; + FLASH->CR|= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + + /* Disable the PER Bit */ + FLASH->CR &= CR_PER_Reset; + } +#endif /* STM32F10X_XL */ + + /* Return the Erase Status */ + return status; +} + +/** + * @brief Erases all FLASH pages. + * @note This function can be used for all STM32F10x devices. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseAllPages(void) +{ + FLASH_Status status = FLASH_COMPLETE; + +#ifdef STM32F10X_XL + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase all pages */ + FLASH->CR |= CR_MER_Set; + FLASH->CR |= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(EraseTimeout); + + /* Disable the MER Bit */ + FLASH->CR &= CR_MER_Reset; + } + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase all pages */ + FLASH->CR2 |= CR_MER_Set; + FLASH->CR2 |= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(EraseTimeout); + + /* Disable the MER Bit */ + FLASH->CR2 &= CR_MER_Reset; + } +#else + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase all pages */ + FLASH->CR |= CR_MER_Set; + FLASH->CR |= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + + /* Disable the MER Bit */ + FLASH->CR &= CR_MER_Reset; + } +#endif /* STM32F10X_XL */ + + /* Return the Erase Status */ + return status; +} + +/** + * @brief Erases all Bank1 FLASH pages. + * @note This function can be used for all STM32F10x devices. + * - For STM32F10X_XL devices this function erases all Bank1 pages. + * - For all other devices it erases all Bank1 pages and it is equivalent + * to FLASH_EraseAllPages function. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseAllBank1Pages(void) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase all pages */ + FLASH->CR |= CR_MER_Set; + FLASH->CR |= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(EraseTimeout); + + /* Disable the MER Bit */ + FLASH->CR &= CR_MER_Reset; + } + /* Return the Erase Status */ + return status; +} + +#ifdef STM32F10X_XL +/** + * @brief Erases all Bank2 FLASH pages. + * @note This function can be used only for STM32F10x_XL density devices. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseAllBank2Pages(void) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase all pages */ + FLASH->CR2 |= CR_MER_Set; + FLASH->CR2 |= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(EraseTimeout); + + /* Disable the MER Bit */ + FLASH->CR2 &= CR_MER_Reset; + } + /* Return the Erase Status */ + return status; +} +#endif /* STM32F10X_XL */ + +/** + * @brief Erases the FLASH option bytes. + * @note This functions erases all option bytes except the Read protection (RDP). + * @note This function can be used for all STM32F10x devices. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseOptionBytes(void) +{ + uint16_t rdptmp = RDP_Key; + + FLASH_Status status = FLASH_COMPLETE; + + /* Get the actual read protection Option Byte value */ + if(FLASH_GetReadOutProtectionStatus() != RESET) + { + rdptmp = 0x00; + } + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + /* Authorize the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + + /* if the previous operation is completed, proceed to erase the option bytes */ + FLASH->CR |= CR_OPTER_Set; + FLASH->CR |= CR_STRT_Set; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the erase operation is completed, disable the OPTER Bit */ + FLASH->CR &= CR_OPTER_Reset; + + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= CR_OPTPG_Set; + /* Restore the last read protection Option Byte value */ + OB->RDP = (uint16_t)rdptmp; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + else + { + if (status != FLASH_TIMEOUT) + { + /* Disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + } + /* Return the erase status */ + return status; +} + +/** + * @brief Programs a word at a specified address. + * @note This function can be used for all STM32F10x devices. + * @param Address: specifies the address to be programmed. + * @param Data: specifies the data to be programmed. + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + +#ifdef STM32F10X_XL + if(Address < FLASH_BANK1_END_ADDRESS - 2) + { + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(ProgramTimeout); + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new first + half word */ + FLASH->CR |= CR_PG_Set; + + *(__IO uint16_t*)Address = (uint16_t)Data; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new second + half word */ + tmp = Address + 2; + + *(__IO uint16_t*) tmp = Data >> 16; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + else + { + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + } + } + else if(Address == (FLASH_BANK1_END_ADDRESS - 1)) + { + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new first + half word */ + FLASH->CR |= CR_PG_Set; + + *(__IO uint16_t*)Address = (uint16_t)Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(ProgramTimeout); + + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + else + { + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new second + half word */ + FLASH->CR2 |= CR_PG_Set; + tmp = Address + 2; + + *(__IO uint16_t*) tmp = Data >> 16; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(ProgramTimeout); + + /* Disable the PG Bit */ + FLASH->CR2 &= CR_PG_Reset; + } + else + { + /* Disable the PG Bit */ + FLASH->CR2 &= CR_PG_Reset; + } + } + else + { + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new first + half word */ + FLASH->CR2 |= CR_PG_Set; + + *(__IO uint16_t*)Address = (uint16_t)Data; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new second + half word */ + tmp = Address + 2; + + *(__IO uint16_t*) tmp = Data >> 16; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(ProgramTimeout); + + /* Disable the PG Bit */ + FLASH->CR2 &= CR_PG_Reset; + } + else + { + /* Disable the PG Bit */ + FLASH->CR2 &= CR_PG_Reset; + } + } + } +#else + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new first + half word */ + FLASH->CR |= CR_PG_Set; + + *(__IO uint16_t*)Address = (uint16_t)Data; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new second + half word */ + tmp = Address + 2; + + *(__IO uint16_t*) tmp = Data >> 16; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + else + { + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + } +#endif /* STM32F10X_XL */ + + /* Return the Program Status */ + return status; +} + +/** + * @brief Programs a half word at a specified address. + * @note This function can be used for all STM32F10x devices. + * @param Address: specifies the address to be programmed. + * @param Data: specifies the data to be programmed. + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + +#ifdef STM32F10X_XL + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(Address < FLASH_BANK1_END_ADDRESS) + { + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new data */ + FLASH->CR |= CR_PG_Set; + + *(__IO uint16_t*)Address = Data; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(ProgramTimeout); + + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + } + else + { + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new data */ + FLASH->CR2 |= CR_PG_Set; + + *(__IO uint16_t*)Address = Data; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(ProgramTimeout); + + /* Disable the PG Bit */ + FLASH->CR2 &= CR_PG_Reset; + } + } +#else + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new data */ + FLASH->CR |= CR_PG_Set; + + *(__IO uint16_t*)Address = Data; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } +#endif /* STM32F10X_XL */ + + /* Return the Program Status */ + return status; +} + +/** + * @brief Programs a half word at a specified Option Byte Data address. + * @note This function can be used for all STM32F10x devices. + * @param Address: specifies the address to be programmed. + * This parameter can be 0x1FFFF804 or 0x1FFFF806. + * @param Data: specifies the data to be programmed. + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Check the parameters */ + assert_param(IS_OB_DATA_ADDRESS(Address)); + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* Authorize the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + /* Enables the Option Bytes Programming operation */ + FLASH->CR |= CR_OPTPG_Set; + *(__IO uint16_t*)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + /* Return the Option Byte Data Program Status */ + return status; +} + +/** + * @brief Write protects the desired pages + * @note This function can be used for all STM32F10x devices. + * @param FLASH_Pages: specifies the address of the pages to be write protected. + * This parameter can be: + * @arg For @b STM32_Low-density_devices: value between FLASH_WRProt_Pages0to3 and FLASH_WRProt_Pages28to31 + * @arg For @b STM32_Medium-density_devices: value between FLASH_WRProt_Pages0to3 + * and FLASH_WRProt_Pages124to127 + * @arg For @b STM32_High-density_devices: value between FLASH_WRProt_Pages0to1 and + * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to255 + * @arg For @b STM32_Connectivity_line_devices: value between FLASH_WRProt_Pages0to1 and + * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to127 + * @arg For @b STM32_XL-density_devices: value between FLASH_WRProt_Pages0to1 and + * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to511 + * @arg FLASH_WRProt_AllPages + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages) +{ + uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF; + + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_FLASH_WRPROT_PAGE(FLASH_Pages)); + + FLASH_Pages = (uint32_t)(~FLASH_Pages); + WRP0_Data = (uint16_t)(FLASH_Pages & WRP0_Mask); + WRP1_Data = (uint16_t)((FLASH_Pages & WRP1_Mask) >> 8); + WRP2_Data = (uint16_t)((FLASH_Pages & WRP2_Mask) >> 16); + WRP3_Data = (uint16_t)((FLASH_Pages & WRP3_Mask) >> 24); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* Authorizes the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + FLASH->CR |= CR_OPTPG_Set; + if(WRP0_Data != 0xFF) + { + OB->WRP0 = WRP0_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + } + if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF)) + { + OB->WRP1 = WRP1_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + } + if((status == FLASH_COMPLETE) && (WRP2_Data != 0xFF)) + { + OB->WRP2 = WRP2_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + } + + if((status == FLASH_COMPLETE)&& (WRP3_Data != 0xFF)) + { + OB->WRP3 = WRP3_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + } + + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + /* Return the write protection operation Status */ + return status; +} + +/** + * @brief Enables or disables the read out protection. + * @note If the user has already programmed the other option bytes before calling + * this function, he must re-program them since this function erases all option bytes. + * @note This function can be used for all STM32F10x devices. + * @param Newstate: new state of the ReadOut Protection. + * This parameter can be: ENABLE or DISABLE. + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + /* Authorizes the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + FLASH->CR |= CR_OPTER_Set; + FLASH->CR |= CR_STRT_Set; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + /* if the erase operation is completed, disable the OPTER Bit */ + FLASH->CR &= CR_OPTER_Reset; + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= CR_OPTPG_Set; + if(NewState != DISABLE) + { + OB->RDP = 0x00; + } + else + { + OB->RDP = RDP_Key; + } + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + else + { + if(status != FLASH_TIMEOUT) + { + /* Disable the OPTER Bit */ + FLASH->CR &= CR_OPTER_Reset; + } + } + } + /* Return the protection operation Status */ + return status; +} + +/** + * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. + * @note This function can be used for all STM32F10x devices. + * @param OB_IWDG: Selects the IWDG mode + * This parameter can be one of the following values: + * @arg OB_IWDG_SW: Software IWDG selected + * @arg OB_IWDG_HW: Hardware IWDG selected + * @param OB_STOP: Reset event when entering STOP mode. + * This parameter can be one of the following values: + * @arg OB_STOP_NoRST: No reset generated when entering in STOP + * @arg OB_STOP_RST: Reset generated when entering in STOP + * @param OB_STDBY: Reset event when entering Standby mode. + * This parameter can be one of the following values: + * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY + * @arg OB_STDBY_RST: Reset generated when entering in STANDBY + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_OB_IWDG_SOURCE(OB_IWDG)); + assert_param(IS_OB_STOP_SOURCE(OB_STOP)); + assert_param(IS_OB_STDBY_SOURCE(OB_STDBY)); + + /* Authorize the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= CR_OPTPG_Set; + + OB->USER = OB_IWDG | (uint16_t)(OB_STOP | (uint16_t)(OB_STDBY | ((uint16_t)0xF8))); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + /* Return the Option Byte program Status */ + return status; +} + +#ifdef STM32F10X_XL +/** + * @brief Configures to boot from Bank1 or Bank2. + * @note This function can be used only for STM32F10x_XL density devices. + * @param FLASH_BOOT: select the FLASH Bank to boot from. + * This parameter can be one of the following values: + * @arg FLASH_BOOT_Bank1: At startup, if boot pins are set in boot from user Flash + * position and this parameter is selected the device will boot from Bank1(Default). + * @arg FLASH_BOOT_Bank2: At startup, if boot pins are set in boot from user Flash + * position and this parameter is selected the device will boot from Bank2 or Bank1, + * depending on the activation of the bank. The active banks are checked in + * the following order: Bank2, followed by Bank1. + * The active bank is recognized by the value programmed at the base address + * of the respective bank (corresponding to the initial stack pointer value + * in the interrupt vector table). + * For more information, please refer to AN2606 from www.st.com. + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT) +{ + FLASH_Status status = FLASH_COMPLETE; + assert_param(IS_FLASH_BOOT(FLASH_BOOT)); + /* Authorize the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= CR_OPTPG_Set; + + if(FLASH_BOOT == FLASH_BOOT_Bank1) + { + OB->USER |= OB_USER_BFB2; + } + else + { + OB->USER &= (uint16_t)(~(uint16_t)(OB_USER_BFB2)); + } + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + /* Return the Option Byte program Status */ + return status; +} +#endif /* STM32F10X_XL */ + +/** + * @brief Returns the FLASH User Option Bytes values. + * @note This function can be used for all STM32F10x devices. + * @param None + * @retval The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1) + * and RST_STDBY(Bit2). + */ +uint32_t FLASH_GetUserOptionByte(void) +{ + /* Return the User Option Byte */ + return (uint32_t)(FLASH->OBR >> 2); +} + +/** + * @brief Returns the FLASH Write Protection Option Bytes Register value. + * @note This function can be used for all STM32F10x devices. + * @param None + * @retval The FLASH Write Protection Option Bytes Register value + */ +uint32_t FLASH_GetWriteProtectionOptionByte(void) +{ + /* Return the Flash write protection Register value */ + return (uint32_t)(FLASH->WRPR); +} + +/** + * @brief Checks whether the FLASH Read Out Protection Status is set or not. + * @note This function can be used for all STM32F10x devices. + * @param None + * @retval FLASH ReadOut Protection Status(SET or RESET) + */ +FlagStatus FLASH_GetReadOutProtectionStatus(void) +{ + FlagStatus readoutstatus = RESET; + if ((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) + { + readoutstatus = SET; + } + else + { + readoutstatus = RESET; + } + return readoutstatus; +} + +/** + * @brief Checks whether the FLASH Prefetch Buffer status is set or not. + * @note This function can be used for all STM32F10x devices. + * @param None + * @retval FLASH Prefetch Buffer Status (SET or RESET). + */ +FlagStatus FLASH_GetPrefetchBufferStatus(void) +{ + FlagStatus bitstatus = RESET; + + if ((FLASH->ACR & ACR_PRFTBS_Mask) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */ + return bitstatus; +} + +/** + * @brief Enables or disables the specified FLASH interrupts. + * @note This function can be used for all STM32F10x devices. + * - For STM32F10X_XL devices, enables or disables the specified FLASH interrupts + for Bank1 and Bank2. + * - For other devices it enables or disables the specified FLASH interrupts for Bank1. + * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg FLASH_IT_ERROR: FLASH Error Interrupt + * @arg FLASH_IT_EOP: FLASH end of operation Interrupt + * @param NewState: new state of the specified Flash interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) +{ +#ifdef STM32F10X_XL + /* Check the parameters */ + assert_param(IS_FLASH_IT(FLASH_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if((FLASH_IT & 0x80000000) != 0x0) + { + if(NewState != DISABLE) + { + /* Enable the interrupt sources */ + FLASH->CR2 |= (FLASH_IT & 0x7FFFFFFF); + } + else + { + /* Disable the interrupt sources */ + FLASH->CR2 &= ~(uint32_t)(FLASH_IT & 0x7FFFFFFF); + } + } + else + { + if(NewState != DISABLE) + { + /* Enable the interrupt sources */ + FLASH->CR |= FLASH_IT; + } + else + { + /* Disable the interrupt sources */ + FLASH->CR &= ~(uint32_t)FLASH_IT; + } + } +#else + /* Check the parameters */ + assert_param(IS_FLASH_IT(FLASH_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if(NewState != DISABLE) + { + /* Enable the interrupt sources */ + FLASH->CR |= FLASH_IT; + } + else + { + /* Disable the interrupt sources */ + FLASH->CR &= ~(uint32_t)FLASH_IT; + } +#endif /* STM32F10X_XL */ +} + +/** + * @brief Checks whether the specified FLASH flag is set or not. + * @note This function can be used for all STM32F10x devices. + * - For STM32F10X_XL devices, this function checks whether the specified + * Bank1 or Bank2 flag is set or not. + * - For other devices, it checks whether the specified Bank1 flag is + * set or not. + * @param FLASH_FLAG: specifies the FLASH flag to check. + * This parameter can be one of the following values: + * @arg FLASH_FLAG_BSY: FLASH Busy flag + * @arg FLASH_FLAG_PGERR: FLASH Program error flag + * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag + * @arg FLASH_FLAG_EOP: FLASH End of Operation flag + * @arg FLASH_FLAG_OPTERR: FLASH Option Byte error flag + * @retval The new state of FLASH_FLAG (SET or RESET). + */ +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) +{ + FlagStatus bitstatus = RESET; + +#ifdef STM32F10X_XL + /* Check the parameters */ + assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ; + if(FLASH_FLAG == FLASH_FLAG_OPTERR) + { + if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((FLASH_FLAG & 0x80000000) != 0x0) + { + if((FLASH->SR2 & FLASH_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + } +#else + /* Check the parameters */ + assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ; + if(FLASH_FLAG == FLASH_FLAG_OPTERR) + { + if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } +#endif /* STM32F10X_XL */ + + /* Return the new state of FLASH_FLAG (SET or RESET) */ + return bitstatus; +} + +/** + * @brief Clears the FLASH's pending flags. + * @note This function can be used for all STM32F10x devices. + * - For STM32F10X_XL devices, this function clears Bank1 or Bank2抯 pending flags + * - For other devices, it clears Bank1抯 pending flags. + * @param FLASH_FLAG: specifies the FLASH flags to clear. + * This parameter can be any combination of the following values: + * @arg FLASH_FLAG_PGERR: FLASH Program error flag + * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag + * @arg FLASH_FLAG_EOP: FLASH End of Operation flag + * @retval None + */ +void FLASH_ClearFlag(uint32_t FLASH_FLAG) +{ +#ifdef STM32F10X_XL + /* Check the parameters */ + assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ; + + if((FLASH_FLAG & 0x80000000) != 0x0) + { + /* Clear the flags */ + FLASH->SR2 = FLASH_FLAG; + } + else + { + /* Clear the flags */ + FLASH->SR = FLASH_FLAG; + } + +#else + /* Check the parameters */ + assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ; + + /* Clear the flags */ + FLASH->SR = FLASH_FLAG; +#endif /* STM32F10X_XL */ +} + +/** + * @brief Returns the FLASH Status. + * @note This function can be used for all STM32F10x devices, it is equivalent + * to FLASH_GetBank1Status function. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE + */ +FLASH_Status FLASH_GetStatus(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) + { + flashstatus = FLASH_BUSY; + } + else + { + if((FLASH->SR & FLASH_FLAG_PGERR) != 0) + { + flashstatus = FLASH_ERROR_PG; + } + else + { + if((FLASH->SR & FLASH_FLAG_WRPRTERR) != 0 ) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + } + /* Return the Flash Status */ + return flashstatus; +} + +/** + * @brief Returns the FLASH Bank1 Status. + * @note This function can be used for all STM32F10x devices, it is equivalent + * to FLASH_GetStatus function. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE + */ +FLASH_Status FLASH_GetBank1Status(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->SR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY) + { + flashstatus = FLASH_BUSY; + } + else + { + if((FLASH->SR & FLASH_FLAG_BANK1_PGERR) != 0) + { + flashstatus = FLASH_ERROR_PG; + } + else + { + if((FLASH->SR & FLASH_FLAG_BANK1_WRPRTERR) != 0 ) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + } + /* Return the Flash Status */ + return flashstatus; +} + +#ifdef STM32F10X_XL +/** + * @brief Returns the FLASH Bank2 Status. + * @note This function can be used for STM32F10x_XL density devices. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE + */ +FLASH_Status FLASH_GetBank2Status(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->SR2 & (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) + { + flashstatus = FLASH_BUSY; + } + else + { + if((FLASH->SR2 & (FLASH_FLAG_BANK2_PGERR & 0x7FFFFFFF)) != 0) + { + flashstatus = FLASH_ERROR_PG; + } + else + { + if((FLASH->SR2 & (FLASH_FLAG_BANK2_WRPRTERR & 0x7FFFFFFF)) != 0 ) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + } + /* Return the Flash Status */ + return flashstatus; +} +#endif /* STM32F10X_XL */ +/** + * @brief Waits for a Flash operation to complete or a TIMEOUT to occur. + * @note This function can be used for all STM32F10x devices, + * it is equivalent to FLASH_WaitForLastBank1Operation. + * - For STM32F10X_XL devices this function waits for a Bank1 Flash operation + * to complete or a TIMEOUT to occur. + * - For all other devices it waits for a Flash operation to complete + * or a TIMEOUT to occur. + * @param Timeout: FLASH programming Timeout + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check for the Flash Status */ + status = FLASH_GetBank1Status(); + /* Wait for a Flash operation to complete or a TIMEOUT to occur */ + while((status == FLASH_BUSY) && (Timeout != 0x00)) + { + status = FLASH_GetBank1Status(); + Timeout--; + } + if(Timeout == 0x00 ) + { + status = FLASH_TIMEOUT; + } + /* Return the operation status */ + return status; +} + +/** + * @brief Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur. + * @note This function can be used for all STM32F10x devices, + * it is equivalent to FLASH_WaitForLastOperation. + * @param Timeout: FLASH programming Timeout + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check for the Flash Status */ + status = FLASH_GetBank1Status(); + /* Wait for a Flash operation to complete or a TIMEOUT to occur */ + while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00)) + { + status = FLASH_GetBank1Status(); + Timeout--; + } + if(Timeout == 0x00 ) + { + status = FLASH_TIMEOUT; + } + /* Return the operation status */ + return status; +} + +#ifdef STM32F10X_XL +/** + * @brief Waits for a Flash operation on Bank2 to complete or a TIMEOUT to occur. + * @note This function can be used only for STM32F10x_XL density devices. + * @param Timeout: FLASH programming Timeout + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check for the Flash Status */ + status = FLASH_GetBank2Status(); + /* Wait for a Flash operation to complete or a TIMEOUT to occur */ + while((status == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) && (Timeout != 0x00)) + { + status = FLASH_GetBank2Status(); + Timeout--; + } + if(Timeout == 0x00 ) + { + status = FLASH_TIMEOUT; + } + /* Return the operation status */ + return status; +} +#endif /* STM32F10X_XL */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/STM32F10x_FWLIB/src/stm32f10x_fsmc.c b/STM32F10x_FWLIB/src/stm32f10x_fsmc.c new file mode 100644 index 0000000..8410495 --- /dev/null +++ b/STM32F10x_FWLIB/src/stm32f10x_fsmc.c @@ -0,0 +1,864 @@ +/** + ****************************************************************************** + * @file stm32f10x_fsmc.c + * @author MCD Application Team + * @version V3.6.2 + * @date 17-September-2021 + * @brief This file provides all the FSMC firmware functions. + ****************************************************************************** + * @attention + * + * Copyright (c) 2012 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_fsmc.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup FSMC + * @brief FSMC driver modules + * @{ + */ + +/** @defgroup FSMC_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + +/** @defgroup FSMC_Private_Defines + * @{ + */ + +/* --------------------- FSMC registers bit mask ---------------------------- */ + +/* FSMC BCRx Mask */ +#define BCR_MBKEN_Set ((uint32_t)0x00000001) +#define BCR_MBKEN_Reset ((uint32_t)0x000FFFFE) +#define BCR_FACCEN_Set ((uint32_t)0x00000040) + +/* FSMC PCRx Mask */ +#define PCR_PBKEN_Set ((uint32_t)0x00000004) +#define PCR_PBKEN_Reset ((uint32_t)0x000FFFFB) +#define PCR_ECCEN_Set ((uint32_t)0x00000040) +#define PCR_ECCEN_Reset ((uint32_t)0x000FFFBF) +#define PCR_MemoryType_NAND ((uint32_t)0x00000008) +/** + * @} + */ + +/** @defgroup FSMC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup FSMC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup FSMC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup FSMC_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default + * reset values. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 + * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 + * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 + * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 + * @retval None + */ +void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank) +{ + /* Check the parameter */ + assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); + + /* FSMC_Bank1_NORSRAM1 */ + if(FSMC_Bank == FSMC_Bank1_NORSRAM1) + { + FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB; + } + /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */ + else + { + FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; + } + FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF; + FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF; +} + +/** + * @brief Deinitializes the FSMC NAND Banks registers to their default reset values. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @retval None + */ +void FSMC_NANDDeInit(uint32_t FSMC_Bank) +{ + /* Check the parameter */ + assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + /* Set the FSMC_Bank2 registers to their reset values */ + FSMC_Bank2->PCR2 = 0x00000018; + FSMC_Bank2->SR2 = 0x00000040; + FSMC_Bank2->PMEM2 = 0xFCFCFCFC; + FSMC_Bank2->PATT2 = 0xFCFCFCFC; + } + /* FSMC_Bank3_NAND */ + else + { + /* Set the FSMC_Bank3 registers to their reset values */ + FSMC_Bank3->PCR3 = 0x00000018; + FSMC_Bank3->SR3 = 0x00000040; + FSMC_Bank3->PMEM3 = 0xFCFCFCFC; + FSMC_Bank3->PATT3 = 0xFCFCFCFC; + } +} + +/** + * @brief Deinitializes the FSMC PCCARD Bank registers to their default reset values. + * @param None + * @retval None + */ +void FSMC_PCCARDDeInit(void) +{ + /* Set the FSMC_Bank4 registers to their reset values */ + FSMC_Bank4->PCR4 = 0x00000018; + FSMC_Bank4->SR4 = 0x00000000; + FSMC_Bank4->PMEM4 = 0xFCFCFCFC; + FSMC_Bank4->PATT4 = 0xFCFCFCFC; + FSMC_Bank4->PIO4 = 0xFCFCFCFC; +} + +/** + * @brief Initializes the FSMC NOR/SRAM Banks according to the specified + * parameters in the FSMC_NORSRAMInitStruct. + * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef + * structure that contains the configuration information for + * the FSMC NOR/SRAM specified Banks. + * @retval None + */ +void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) +{ + /* Check the parameters */ + assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank)); + assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux)); + assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType)); + assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth)); + assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode)); + assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait)); + assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity)); + assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode)); + assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive)); + assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation)); + assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal)); + assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode)); + assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst)); + assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime)); + assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime)); + assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime)); + assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration)); + assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision)); + assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency)); + assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); + + /* Bank1 NOR/SRAM control register configuration */ + FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = + (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux | + FSMC_NORSRAMInitStruct->FSMC_MemoryType | + FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth | + FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode | + FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait | + FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity | + FSMC_NORSRAMInitStruct->FSMC_WrapMode | + FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive | + FSMC_NORSRAMInitStruct->FSMC_WriteOperation | + FSMC_NORSRAMInitStruct->FSMC_WaitSignal | + FSMC_NORSRAMInitStruct->FSMC_ExtendedMode | + FSMC_NORSRAMInitStruct->FSMC_WriteBurst; + + if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR) + { + FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set; + } + + /* Bank1 NOR/SRAM timing register configuration */ + FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = + (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) | + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode; + + + /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */ + if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable) + { + assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime)); + assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime)); + assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime)); + assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision)); + assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency)); + assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode)); + FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = + (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime | + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )| + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) | + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) | + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) | + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode; + } + else + { + FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF; + } +} + +/** + * @brief Initializes the FSMC NAND Banks according to the specified + * parameters in the FSMC_NANDInitStruct. + * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef + * structure that contains the configuration information for the FSMC + * NAND specified Banks. + * @retval None + */ +void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) +{ + uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; + + /* Check the parameters */ + assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank)); + assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature)); + assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth)); + assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC)); + assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize)); + assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime)); + assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime)); + assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); + assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); + + /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */ + tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature | + PCR_MemoryType_NAND | + FSMC_NANDInitStruct->FSMC_MemoryDataWidth | + FSMC_NANDInitStruct->FSMC_ECC | + FSMC_NANDInitStruct->FSMC_ECCPageSize | + (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )| + (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13); + + /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */ + tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | + (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */ + tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | + (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND) + { + /* FSMC_Bank2_NAND registers configuration */ + FSMC_Bank2->PCR2 = tmppcr; + FSMC_Bank2->PMEM2 = tmppmem; + FSMC_Bank2->PATT2 = tmppatt; + } + else + { + /* FSMC_Bank3_NAND registers configuration */ + FSMC_Bank3->PCR3 = tmppcr; + FSMC_Bank3->PMEM3 = tmppmem; + FSMC_Bank3->PATT3 = tmppatt; + } +} + +/** + * @brief Initializes the FSMC PCCARD Bank according to the specified + * parameters in the FSMC_PCCARDInitStruct. + * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef + * structure that contains the configuration information for the FSMC + * PCCARD Bank. + * @retval None + */ +void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) +{ + /* Check the parameters */ + assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature)); + assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime)); + assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime)); + + assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); + + assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); + assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime)); + + /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */ + FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature | + FSMC_MemoryDataWidth_16b | + (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) | + (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13); + + /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */ + FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | + (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */ + FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | + (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */ + FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime | + (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24); +} + +/** + * @brief Fills each FSMC_NORSRAMInitStruct member with its default value. + * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef + * structure which will be initialized. + * @retval None + */ +void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) +{ + /* Reset NOR/SRAM Init structure parameters values */ + FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1; + FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable; + FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM; + FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; + FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable; + FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; +} + +/** + * @brief Fills each FSMC_NANDInitStruct member with its default value. + * @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef + * structure which will be initialized. + * @retval None + */ +void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) +{ + /* Reset NAND Init structure parameters values */ + FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND; + FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; + FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; + FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable; + FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes; + FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0; + FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; +} + +/** + * @brief Fills each FSMC_PCCARDInitStruct member with its default value. + * @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef + * structure which will be initialized. + * @retval None + */ +void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) +{ + /* Reset PCCARD Init structure parameters values */ + FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; + FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0; + FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0; + FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; +} + +/** + * @brief Enables or disables the specified NOR/SRAM Memory Bank. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 + * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 + * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 + * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 + * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState) +{ + assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */ + FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set; + } + else + { + /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */ + FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset; + } +} + +/** + * @brief Enables or disables the specified NAND Memory Bank. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState) +{ + assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 |= PCR_PBKEN_Set; + } + else + { + FSMC_Bank3->PCR3 |= PCR_PBKEN_Set; + } + } + else + { + /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset; + } + else + { + FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset; + } + } +} + +/** + * @brief Enables or disables the PCCARD Memory Bank. + * @param NewState: new state of the PCCARD Memory Bank. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FSMC_PCCARDCmd(FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */ + FSMC_Bank4->PCR4 |= PCR_PBKEN_Set; + } + else + { + /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */ + FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset; + } +} + +/** + * @brief Enables or disables the FSMC NAND ECC feature. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @param NewState: new state of the FSMC NAND ECC feature. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState) +{ + assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 |= PCR_ECCEN_Set; + } + else + { + FSMC_Bank3->PCR3 |= PCR_ECCEN_Set; + } + } + else + { + /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset; + } + else + { + FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset; + } + } +} + +/** + * @brief Returns the error correction code register value. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @retval The Error Correction Code (ECC) value. + */ +uint32_t FSMC_GetECC(uint32_t FSMC_Bank) +{ + uint32_t eccval = 0x00000000; + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + /* Get the ECCR2 register value */ + eccval = FSMC_Bank2->ECCR2; + } + else + { + /* Get the ECCR3 register value */ + eccval = FSMC_Bank3->ECCR3; + } + /* Return the error correction code value */ + return(eccval); +} + +/** + * @brief Enables or disables the specified FSMC interrupts. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. + * @arg FSMC_IT_Level: Level edge detection interrupt. + * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. + * @param NewState: new state of the specified FSMC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState) +{ + assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); + assert_param(IS_FSMC_IT(FSMC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected FSMC_Bank2 interrupts */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->SR2 |= FSMC_IT; + } + /* Enable the selected FSMC_Bank3 interrupts */ + else if (FSMC_Bank == FSMC_Bank3_NAND) + { + FSMC_Bank3->SR3 |= FSMC_IT; + } + /* Enable the selected FSMC_Bank4 interrupts */ + else + { + FSMC_Bank4->SR4 |= FSMC_IT; + } + } + else + { + /* Disable the selected FSMC_Bank2 interrupts */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + + FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT; + } + /* Disable the selected FSMC_Bank3 interrupts */ + else if (FSMC_Bank == FSMC_Bank3_NAND) + { + FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT; + } + /* Disable the selected FSMC_Bank4 interrupts */ + else + { + FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT; + } + } +} + +/** + * @brief Checks whether the specified FSMC flag is set or not. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag. + * @arg FSMC_FLAG_Level: Level detection Flag. + * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag. + * @arg FSMC_FLAG_FEMPT: Fifo empty Flag. + * @retval The new state of FSMC_FLAG (SET or RESET). + */ +FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpsr = 0x00000000; + + /* Check the parameters */ + assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); + assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG)); + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + tmpsr = FSMC_Bank2->SR2; + } + else if(FSMC_Bank == FSMC_Bank3_NAND) + { + tmpsr = FSMC_Bank3->SR3; + } + /* FSMC_Bank4_PCCARD*/ + else + { + tmpsr = FSMC_Bank4->SR4; + } + + /* Get the flag status */ + if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET ) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the FSMC's pending flags. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag. + * @arg FSMC_FLAG_Level: Level detection Flag. + * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag. + * @retval None + */ +void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); + assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ; + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->SR2 &= ~FSMC_FLAG; + } + else if(FSMC_Bank == FSMC_Bank3_NAND) + { + FSMC_Bank3->SR3 &= ~FSMC_FLAG; + } + /* FSMC_Bank4_PCCARD*/ + else + { + FSMC_Bank4->SR4 &= ~FSMC_FLAG; + } +} + +/** + * @brief Checks whether the specified FSMC interrupt has occurred or not. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_IT: specifies the FSMC interrupt source to check. + * This parameter can be one of the following values: + * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. + * @arg FSMC_IT_Level: Level edge detection interrupt. + * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. + * @retval The new state of FSMC_IT (SET or RESET). + */ +ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; + + /* Check the parameters */ + assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); + assert_param(IS_FSMC_GET_IT(FSMC_IT)); + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + tmpsr = FSMC_Bank2->SR2; + } + else if(FSMC_Bank == FSMC_Bank3_NAND) + { + tmpsr = FSMC_Bank3->SR3; + } + /* FSMC_Bank4_PCCARD*/ + else + { + tmpsr = FSMC_Bank4->SR4; + } + + itstatus = tmpsr & FSMC_IT; + + itenable = tmpsr & (FSMC_IT >> 3); + if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the FSMC's interrupt pending bits. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. + * @arg FSMC_IT_Level: Level edge detection interrupt. + * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. + * @retval None + */ +void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT) +{ + /* Check the parameters */ + assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); + assert_param(IS_FSMC_IT(FSMC_IT)); + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3); + } + else if(FSMC_Bank == FSMC_Bank3_NAND) + { + FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3); + } + /* FSMC_Bank4_PCCARD*/ + else + { + FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3); + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/STM32F10x_FWLIB/src/stm32f10x_gpio.c b/STM32F10x_FWLIB/src/stm32f10x_gpio.c new file mode 100644 index 0000000..9befc20 --- /dev/null +++ b/STM32F10x_FWLIB/src/stm32f10x_gpio.c @@ -0,0 +1,648 @@ +/** + ****************************************************************************** + * @file stm32f10x_gpio.c + * @author MCD Application Team + * @version V3.6.2 + * @date 17-September-2021 + * @brief This file provides all the GPIO firmware functions. + ****************************************************************************** + * @attention + * + * Copyright (c) 2012 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_gpio.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup GPIO + * @brief GPIO driver modules + * @{ + */ + +/** @defgroup GPIO_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup GPIO_Private_Defines + * @{ + */ + +/* ------------ RCC registers bit address in the alias region ----------------*/ +#define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE) + +/* --- EVENTCR Register -----*/ + +/* Alias word address of EVOE bit */ +#define EVCR_OFFSET (AFIO_OFFSET + 0x00) +#define EVOE_BitNumber ((uint8_t)0x07) +#define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4)) + + +/* --- MAPR Register ---*/ +/* Alias word address of MII_RMII_SEL bit */ +#define MAPR_OFFSET (AFIO_OFFSET + 0x04) +#define MII_RMII_SEL_BitNumber ((u8)0x17) +#define MAPR_MII_RMII_SEL_BB (PERIPH_BB_BASE + (MAPR_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4)) + + +#define EVCR_PORTPINCONFIG_MASK ((uint16_t)0xFF80) +#define LSB_MASK ((uint16_t)0xFFFF) +#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) +#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF) +#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) +#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) +/** + * @} + */ + +/** @defgroup GPIO_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup GPIO_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup GPIO_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup GPIO_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the GPIOx peripheral registers to their default reset values. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @retval None + */ +void GPIO_DeInit(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + if (GPIOx == GPIOA) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE); + } + else if (GPIOx == GPIOB) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE); + } + else if (GPIOx == GPIOC) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE); + } + else if (GPIOx == GPIOD) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE); + } + else if (GPIOx == GPIOE) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE); + } + else if (GPIOx == GPIOF) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, DISABLE); + } + else + { + if (GPIOx == GPIOG) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE); + } + } +} + +/** + * @brief Deinitializes the Alternate Functions (remap, event control + * and EXTI configuration) registers to their default reset values. + * @param None + * @retval None + */ +void GPIO_AFIODeInit(void) +{ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE); +} + +/** + * @brief Initializes the GPIOx peripheral according to the specified + * parameters in the GPIO_InitStruct. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that + * contains the configuration information for the specified GPIO peripheral. + * @retval None + */ +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) +{ + uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; + uint32_t tmpreg = 0x00, pinmask = 0x00; + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); + assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); + +/*---------------------------- GPIO Mode Configuration -----------------------*/ + currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); + if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00) + { + /* Check the parameters */ + assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed)); + /* Output mode */ + currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed; + } +/*---------------------------- GPIO CRL Configuration ------------------------*/ + /* Configure the eight low port pins */ + if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00) + { + tmpreg = GPIOx->CRL; + for (pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = ((uint32_t)0x01) << pinpos; + /* Get the port pins position */ + currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; + if (currentpin == pos) + { + pos = pinpos << 2; + /* Clear the corresponding low control register bits */ + pinmask = ((uint32_t)0x0F) << pos; + tmpreg &= ~pinmask; + /* Write the mode configuration in the corresponding bits */ + tmpreg |= (currentmode << pos); + /* Reset the corresponding ODR bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BRR = (((uint32_t)0x01) << pinpos); + } + else + { + /* Set the corresponding ODR bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSRR = (((uint32_t)0x01) << pinpos); + } + } + } + } + GPIOx->CRL = tmpreg; + } +/*---------------------------- GPIO CRH Configuration ------------------------*/ + /* Configure the eight high port pins */ + if (GPIO_InitStruct->GPIO_Pin > 0x00FF) + { + tmpreg = GPIOx->CRH; + for (pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = (((uint32_t)0x01) << (pinpos + 0x08)); + /* Get the port pins position */ + currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos); + if (currentpin == pos) + { + pos = pinpos << 2; + /* Clear the corresponding high control register bits */ + pinmask = ((uint32_t)0x0F) << pos; + tmpreg &= ~pinmask; + /* Write the mode configuration in the corresponding bits */ + tmpreg |= (currentmode << pos); + /* Reset the corresponding ODR bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BRR = (((uint32_t)0x01) << (pinpos + 0x08)); + } + /* Set the corresponding ODR bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSRR = (((uint32_t)0x01) << (pinpos + 0x08)); + } + } + } + GPIOx->CRH = tmpreg; + } +} + +/** + * @brief Fills each GPIO_InitStruct member with its default value. + * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) +{ + /* Reset GPIO init structure parameters values */ + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; + GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; +} + +/** + * @brief Reads the specified input port pin. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * @retval The input port pin value. + */ +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + return bitstatus; +} + +/** + * @brief Reads the specified GPIO input data port. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @retval GPIO input data port value. + */ +uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + return ((uint16_t)GPIOx->IDR); +} + +/** + * @brief Reads the specified output data port bit. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * @retval The output port pin value. + */ +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + return bitstatus; +} + +/** + * @brief Reads the specified GPIO output data port. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @retval GPIO output data port value. + */ +uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + return ((uint16_t)GPIOx->ODR); +} + +/** + * @brief Sets the selected data port bits. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + GPIOx->BSRR = GPIO_Pin; +} + +/** + * @brief Clears the selected data port bits. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + GPIOx->BRR = GPIO_Pin; +} + +/** + * @brief Sets or clears the selected data port bit. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to be written. + * This parameter can be one of GPIO_Pin_x where x can be (0..15). + * @param BitVal: specifies the value to be written to the selected bit. + * This parameter can be one of the BitAction enum values: + * @arg Bit_RESET: to clear the port pin + * @arg Bit_SET: to set the port pin + * @retval None + */ +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_BIT_ACTION(BitVal)); + + if (BitVal != Bit_RESET) + { + GPIOx->BSRR = GPIO_Pin; + } + else + { + GPIOx->BRR = GPIO_Pin; + } +} + +/** + * @brief Writes data to the specified GPIO data port. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param PortVal: specifies the value to be written to the port output data register. + * @retval None + */ +void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + GPIOx->ODR = PortVal; +} + +/** + * @brief Locks GPIO Pins configuration registers. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint32_t tmp = 0x00010000; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + tmp |= GPIO_Pin; + /* Set LCKK bit */ + GPIOx->LCKR = tmp; + /* Reset LCKK bit */ + GPIOx->LCKR = GPIO_Pin; + /* Set LCKK bit */ + GPIOx->LCKR = tmp; + /* Read LCKK bit*/ + tmp = GPIOx->LCKR; + /* Read LCKK bit*/ + tmp = GPIOx->LCKR; +} + +/** + * @brief Selects the GPIO pin used as Event output. + * @param GPIO_PortSource: selects the GPIO port to be used as source + * for Event output. + * This parameter can be GPIO_PortSourceGPIOx where x can be (A..E). + * @param GPIO_PinSource: specifies the pin for the Event output. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + * @retval None + */ +void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) +{ + uint32_t tmpreg = 0x00; + /* Check the parameters */ + assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(GPIO_PortSource)); + assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); + + tmpreg = AFIO->EVCR; + /* Clear the PORT[6:4] and PIN[3:0] bits */ + tmpreg &= EVCR_PORTPINCONFIG_MASK; + tmpreg |= (uint32_t)GPIO_PortSource << 0x04; + tmpreg |= GPIO_PinSource; + AFIO->EVCR = tmpreg; +} + +/** + * @brief Enables or disables the Event Output. + * @param NewState: new state of the Event output. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void GPIO_EventOutputCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) EVCR_EVOE_BB = (uint32_t)NewState; +} + +/** + * @brief Changes the mapping of the specified pin. + * @param GPIO_Remap: selects the pin to remap. + * This parameter can be one of the following values: + * @arg GPIO_Remap_SPI1 : SPI1 Alternate Function mapping + * @arg GPIO_Remap_I2C1 : I2C1 Alternate Function mapping + * @arg GPIO_Remap_USART1 : USART1 Alternate Function mapping + * @arg GPIO_Remap_USART2 : USART2 Alternate Function mapping + * @arg GPIO_PartialRemap_USART3 : USART3 Partial Alternate Function mapping + * @arg GPIO_FullRemap_USART3 : USART3 Full Alternate Function mapping + * @arg GPIO_PartialRemap_TIM1 : TIM1 Partial Alternate Function mapping + * @arg GPIO_FullRemap_TIM1 : TIM1 Full Alternate Function mapping + * @arg GPIO_PartialRemap1_TIM2 : TIM2 Partial1 Alternate Function mapping + * @arg GPIO_PartialRemap2_TIM2 : TIM2 Partial2 Alternate Function mapping + * @arg GPIO_FullRemap_TIM2 : TIM2 Full Alternate Function mapping + * @arg GPIO_PartialRemap_TIM3 : TIM3 Partial Alternate Function mapping + * @arg GPIO_FullRemap_TIM3 : TIM3 Full Alternate Function mapping + * @arg GPIO_Remap_TIM4 : TIM4 Alternate Function mapping + * @arg GPIO_Remap1_CAN1 : CAN1 Alternate Function mapping + * @arg GPIO_Remap2_CAN1 : CAN1 Alternate Function mapping + * @arg GPIO_Remap_PD01 : PD01 Alternate Function mapping + * @arg GPIO_Remap_TIM5CH4_LSI : LSI connected to TIM5 Channel4 input capture for calibration + * @arg GPIO_Remap_ADC1_ETRGINJ : ADC1 External Trigger Injected Conversion remapping + * @arg GPIO_Remap_ADC1_ETRGREG : ADC1 External Trigger Regular Conversion remapping + * @arg GPIO_Remap_ADC2_ETRGINJ : ADC2 External Trigger Injected Conversion remapping + * @arg GPIO_Remap_ADC2_ETRGREG : ADC2 External Trigger Regular Conversion remapping + * @arg GPIO_Remap_ETH : Ethernet remapping (only for Connectivity line devices) + * @arg GPIO_Remap_CAN2 : CAN2 remapping (only for Connectivity line devices) + * @arg GPIO_Remap_SWJ_NoJTRST : Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST + * @arg GPIO_Remap_SWJ_JTAGDisable : JTAG-DP Disabled and SW-DP Enabled + * @arg GPIO_Remap_SWJ_Disable : Full SWJ Disabled (JTAG-DP + SW-DP) + * @arg GPIO_Remap_SPI3 : SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) + * When the SPI3/I2S3 is remapped using this function, the SWJ is configured + * to Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST. + * @arg GPIO_Remap_TIM2ITR1_PTP_SOF : Ethernet PTP output or USB OTG SOF (Start of Frame) connected + * to TIM2 Internal Trigger 1 for calibration (only for Connectivity line devices) + * If the GPIO_Remap_TIM2ITR1_PTP_SOF is enabled the TIM2 ITR1 is connected to + * Ethernet PTP output. When Reset TIM2 ITR1 is connected to USB OTG SOF output. + * @arg GPIO_Remap_PTP_PPS : Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) + * @arg GPIO_Remap_TIM15 : TIM15 Alternate Function mapping (only for Value line devices) + * @arg GPIO_Remap_TIM16 : TIM16 Alternate Function mapping (only for Value line devices) + * @arg GPIO_Remap_TIM17 : TIM17 Alternate Function mapping (only for Value line devices) + * @arg GPIO_Remap_CEC : CEC Alternate Function mapping (only for Value line devices) + * @arg GPIO_Remap_TIM1_DMA : TIM1 DMA requests mapping (only for Value line devices) + * @arg GPIO_Remap_TIM9 : TIM9 Alternate Function mapping (only for XL-density devices) + * @arg GPIO_Remap_TIM10 : TIM10 Alternate Function mapping (only for XL-density devices) + * @arg GPIO_Remap_TIM11 : TIM11 Alternate Function mapping (only for XL-density devices) + * @arg GPIO_Remap_TIM13 : TIM13 Alternate Function mapping (only for High density Value line and XL-density devices) + * @arg GPIO_Remap_TIM14 : TIM14 Alternate Function mapping (only for High density Value line and XL-density devices) + * @arg GPIO_Remap_FSMC_NADV : FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices) + * @arg GPIO_Remap_TIM67_DAC_DMA : TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices) + * @arg GPIO_Remap_TIM12 : TIM12 Alternate Function mapping (only for High density Value line devices) + * @arg GPIO_Remap_MISC : Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping, + * only for High density Value line devices) + * @param NewState: new state of the port pin remapping. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState) +{ + uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_REMAP(GPIO_Remap)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if((GPIO_Remap & 0x80000000) == 0x80000000) + { + tmpreg = AFIO->MAPR2; + } + else + { + tmpreg = AFIO->MAPR; + } + + tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10; + tmp = GPIO_Remap & LSB_MASK; + + if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) + { + tmpreg &= DBGAFR_SWJCFG_MASK; + AFIO->MAPR &= DBGAFR_SWJCFG_MASK; + } + else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) + { + tmp1 = ((uint32_t)0x03) << tmpmask; + tmpreg &= ~tmp1; + tmpreg |= ~DBGAFR_SWJCFG_MASK; + } + else + { + tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15)*0x10)); + tmpreg |= ~DBGAFR_SWJCFG_MASK; + } + + if (NewState != DISABLE) + { + tmpreg |= (tmp << ((GPIO_Remap >> 0x15)*0x10)); + } + + if((GPIO_Remap & 0x80000000) == 0x80000000) + { + AFIO->MAPR2 = tmpreg; + } + else + { + AFIO->MAPR = tmpreg; + } +} + +/** + * @brief Selects the GPIO pin used as EXTI Line. + * @param GPIO_PortSource: selects the GPIO port to be used as source for EXTI lines. + * This parameter can be GPIO_PortSourceGPIOx where x can be (A..G). + * @param GPIO_PinSource: specifies the EXTI line to be configured. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + * @retval None + */ +void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) +{ + uint32_t tmp = 0x00; + /* Check the parameters */ + assert_param(IS_GPIO_EXTI_PORT_SOURCE(GPIO_PortSource)); + assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); + + tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)); + AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp; + AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03))); +} + +/** + * @brief Selects the Ethernet media interface. + * @note This function applies only to STM32 Connectivity line devices. + * @param GPIO_ETH_MediaInterface: specifies the Media Interface mode. + * This parameter can be one of the following values: + * @arg GPIO_ETH_MediaInterface_MII: MII mode + * @arg GPIO_ETH_MediaInterface_RMII: RMII mode + * @retval None + */ +void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface) +{ + assert_param(IS_GPIO_ETH_MEDIA_INTERFACE(GPIO_ETH_MediaInterface)); + + /* Configure MII_RMII selection bit */ + *(__IO uint32_t *) MAPR_MII_RMII_SEL_BB = GPIO_ETH_MediaInterface; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/STM32F10x_FWLIB/src/stm32f10x_i2c.c b/STM32F10x_FWLIB/src/stm32f10x_i2c.c new file mode 100644 index 0000000..539c96c --- /dev/null +++ b/STM32F10x_FWLIB/src/stm32f10x_i2c.c @@ -0,0 +1,1329 @@ +/** + ****************************************************************************** + * @file stm32f10x_i2c.c + * @author MCD Application Team + * @version V3.6.2 + * @date 17-September-2021 + * @brief This file provides all the I2C firmware functions. + ****************************************************************************** + * @attention + * + * Copyright (c) 2012 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_i2c.h" +#include "stm32f10x_rcc.h" + + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup I2C + * @brief I2C driver modules + * @{ + */ + +/** @defgroup I2C_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup I2C_Private_Defines + * @{ + */ + +/* I2C SPE mask */ +#define CR1_PE_Set ((uint16_t)0x0001) +#define CR1_PE_Reset ((uint16_t)0xFFFE) + +/* I2C START mask */ +#define CR1_START_Set ((uint16_t)0x0100) +#define CR1_START_Reset ((uint16_t)0xFEFF) + +/* I2C STOP mask */ +#define CR1_STOP_Set ((uint16_t)0x0200) +#define CR1_STOP_Reset ((uint16_t)0xFDFF) + +/* I2C ACK mask */ +#define CR1_ACK_Set ((uint16_t)0x0400) +#define CR1_ACK_Reset ((uint16_t)0xFBFF) + +/* I2C ENGC mask */ +#define CR1_ENGC_Set ((uint16_t)0x0040) +#define CR1_ENGC_Reset ((uint16_t)0xFFBF) + +/* I2C SWRST mask */ +#define CR1_SWRST_Set ((uint16_t)0x8000) +#define CR1_SWRST_Reset ((uint16_t)0x7FFF) + +/* I2C PEC mask */ +#define CR1_PEC_Set ((uint16_t)0x1000) +#define CR1_PEC_Reset ((uint16_t)0xEFFF) + +/* I2C ENPEC mask */ +#define CR1_ENPEC_Set ((uint16_t)0x0020) +#define CR1_ENPEC_Reset ((uint16_t)0xFFDF) + +/* I2C ENARP mask */ +#define CR1_ENARP_Set ((uint16_t)0x0010) +#define CR1_ENARP_Reset ((uint16_t)0xFFEF) + +/* I2C NOSTRETCH mask */ +#define CR1_NOSTRETCH_Set ((uint16_t)0x0080) +#define CR1_NOSTRETCH_Reset ((uint16_t)0xFF7F) + +/* I2C registers Masks */ +#define CR1_CLEAR_Mask ((uint16_t)0xFBF5) + +/* I2C DMAEN mask */ +#define CR2_DMAEN_Set ((uint16_t)0x0800) +#define CR2_DMAEN_Reset ((uint16_t)0xF7FF) + +/* I2C LAST mask */ +#define CR2_LAST_Set ((uint16_t)0x1000) +#define CR2_LAST_Reset ((uint16_t)0xEFFF) + +/* I2C FREQ mask */ +#define CR2_FREQ_Reset ((uint16_t)0xFFC0) + +/* I2C ADD0 mask */ +#define OAR1_ADD0_Set ((uint16_t)0x0001) +#define OAR1_ADD0_Reset ((uint16_t)0xFFFE) + +/* I2C ENDUAL mask */ +#define OAR2_ENDUAL_Set ((uint16_t)0x0001) +#define OAR2_ENDUAL_Reset ((uint16_t)0xFFFE) + +/* I2C ADD2 mask */ +#define OAR2_ADD2_Reset ((uint16_t)0xFF01) + +/* I2C F/S mask */ +#define CCR_FS_Set ((uint16_t)0x8000) + +/* I2C CCR mask */ +#define CCR_CCR_Set ((uint16_t)0x0FFF) + +/* I2C FLAG mask */ +#define FLAG_Mask ((uint32_t)0x00FFFFFF) + +/* I2C Interrupt Enable mask */ +#define ITEN_Mask ((uint32_t)0x07000000) + +/** + * @} + */ + +/** @defgroup I2C_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup I2C_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup I2C_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup I2C_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the I2Cx peripheral registers to their default reset values. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @retval None + */ +void I2C_DeInit(I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + if (I2Cx == I2C1) + { + /* Enable I2C1 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE); + /* Release I2C1 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE); + } + else + { + /* Enable I2C2 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE); + /* Release I2C2 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE); + } +} + +/** + * @brief Initializes the I2Cx peripheral according to the specified + * parameters in the I2C_InitStruct. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure that + * contains the configuration information for the specified I2C peripheral. + * @retval None + */ +void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct) +{ + uint16_t tmpreg = 0, freqrange = 0; + uint16_t result = 0x04; + uint32_t pclk1 = 8000000; + RCC_ClocksTypeDef rcc_clocks; + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed)); + assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode)); + assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle)); + assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1)); + assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack)); + assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress)); + +/*---------------------------- I2Cx CR2 Configuration ------------------------*/ + /* Get the I2Cx CR2 value */ + tmpreg = I2Cx->CR2; + /* Clear frequency FREQ[5:0] bits */ + tmpreg &= CR2_FREQ_Reset; + /* Get pclk1 frequency value */ + RCC_GetClocksFreq(&rcc_clocks); + pclk1 = rcc_clocks.PCLK1_Frequency; + /* Set frequency bits depending on pclk1 value */ + freqrange = (uint16_t)(pclk1 / 1000000); + tmpreg |= freqrange; + /* Write to I2Cx CR2 */ + I2Cx->CR2 = tmpreg; + +/*---------------------------- I2Cx CCR Configuration ------------------------*/ + /* Disable the selected I2C peripheral to configure TRISE */ + I2Cx->CR1 &= CR1_PE_Reset; + /* Reset tmpreg value */ + /* Clear F/S, DUTY and CCR[11:0] bits */ + tmpreg = 0; + + /* Configure speed in standard mode */ + if (I2C_InitStruct->I2C_ClockSpeed <= 100000) + { + /* Standard mode speed calculate */ + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1)); + /* Test if CCR value is under 0x4*/ + if (result < 0x04) + { + /* Set minimum allowed value */ + result = 0x04; + } + /* Set speed value for standard mode */ + tmpreg |= result; + /* Set Maximum Rise Time for standard mode */ + I2Cx->TRISE = freqrange + 1; + } + /* Configure speed in fast mode */ + else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/ + { + if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2) + { + /* Fast mode speed calculate: Tlow/Thigh = 2 */ + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3)); + } + else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/ + { + /* Fast mode speed calculate: Tlow/Thigh = 16/9 */ + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25)); + /* Set DUTY bit */ + result |= I2C_DutyCycle_16_9; + } + + /* Test if CCR value is under 0x1*/ + if ((result & CCR_CCR_Set) == 0) + { + /* Set minimum allowed value */ + result |= (uint16_t)0x0001; + } + /* Set speed value and set F/S bit for fast mode */ + tmpreg |= (uint16_t)(result | CCR_FS_Set); + /* Set Maximum Rise Time for fast mode */ + I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); + } + + /* Write to I2Cx CCR */ + I2Cx->CCR = tmpreg; + /* Enable the selected I2C peripheral */ + I2Cx->CR1 |= CR1_PE_Set; + +/*---------------------------- I2Cx CR1 Configuration ------------------------*/ + /* Get the I2Cx CR1 value */ + tmpreg = I2Cx->CR1; + /* Clear ACK, SMBTYPE and SMBUS bits */ + tmpreg &= CR1_CLEAR_Mask; + /* Configure I2Cx: mode and acknowledgement */ + /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */ + /* Set ACK bit according to I2C_Ack value */ + tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack); + /* Write to I2Cx CR1 */ + I2Cx->CR1 = tmpreg; + +/*---------------------------- I2Cx OAR1 Configuration -----------------------*/ + /* Set I2Cx Own Address1 and acknowledged address */ + I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1); +} + +/** + * @brief Fills each I2C_InitStruct member with its default value. + * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized. + * @retval None + */ +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct) +{ +/*---------------- Reset I2C init structure parameters values ----------------*/ + /* initialize the I2C_ClockSpeed member */ + I2C_InitStruct->I2C_ClockSpeed = 5000; + /* Initialize the I2C_Mode member */ + I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; + /* Initialize the I2C_DutyCycle member */ + I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2; + /* Initialize the I2C_OwnAddress1 member */ + I2C_InitStruct->I2C_OwnAddress1 = 0; + /* Initialize the I2C_Ack member */ + I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; + /* Initialize the I2C_AcknowledgedAddress member */ + I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; +} + +/** + * @brief Enables or disables the specified I2C peripheral. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2Cx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C peripheral */ + I2Cx->CR1 |= CR1_PE_Set; + } + else + { + /* Disable the selected I2C peripheral */ + I2Cx->CR1 &= CR1_PE_Reset; + } +} + +/** + * @brief Enables or disables the specified I2C DMA requests. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C DMA transfer. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C DMA requests */ + I2Cx->CR2 |= CR2_DMAEN_Set; + } + else + { + /* Disable the selected I2C DMA requests */ + I2Cx->CR2 &= CR2_DMAEN_Reset; + } +} + +/** + * @brief Specifies if the next DMA transfer will be the last one. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C DMA last transfer. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Next DMA transfer is the last transfer */ + I2Cx->CR2 |= CR2_LAST_Set; + } + else + { + /* Next DMA transfer is not the last transfer */ + I2Cx->CR2 &= CR2_LAST_Reset; + } +} + +/** + * @brief Generates I2Cx communication START condition. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C START condition generation. + * This parameter can be: ENABLE or DISABLE. + * @retval None. + */ +void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Generate a START condition */ + I2Cx->CR1 |= CR1_START_Set; + } + else + { + /* Disable the START condition generation */ + I2Cx->CR1 &= CR1_START_Reset; + } +} + +/** + * @brief Generates I2Cx communication STOP condition. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C STOP condition generation. + * This parameter can be: ENABLE or DISABLE. + * @retval None. + */ +void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Generate a STOP condition */ + I2Cx->CR1 |= CR1_STOP_Set; + } + else + { + /* Disable the STOP condition generation */ + I2Cx->CR1 &= CR1_STOP_Reset; + } +} + +/** + * @brief Enables or disables the specified I2C acknowledge feature. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C Acknowledgement. + * This parameter can be: ENABLE or DISABLE. + * @retval None. + */ +void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the acknowledgement */ + I2Cx->CR1 |= CR1_ACK_Set; + } + else + { + /* Disable the acknowledgement */ + I2Cx->CR1 &= CR1_ACK_Reset; + } +} + +/** + * @brief Configures the specified I2C own address2. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param Address: specifies the 7bit I2C own address2. + * @retval None. + */ +void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address) +{ + uint16_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + /* Get the old register value */ + tmpreg = I2Cx->OAR2; + + /* Reset I2Cx Own address2 bit [7:1] */ + tmpreg &= OAR2_ADD2_Reset; + + /* Set I2Cx Own address2 */ + tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE); + + /* Store the new register value */ + I2Cx->OAR2 = tmpreg; +} + +/** + * @brief Enables or disables the specified I2C dual addressing mode. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C dual addressing mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable dual addressing mode */ + I2Cx->OAR2 |= OAR2_ENDUAL_Set; + } + else + { + /* Disable dual addressing mode */ + I2Cx->OAR2 &= OAR2_ENDUAL_Reset; + } +} + +/** + * @brief Enables or disables the specified I2C general call feature. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C General call. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable generall call */ + I2Cx->CR1 |= CR1_ENGC_Set; + } + else + { + /* Disable generall call */ + I2Cx->CR1 &= CR1_ENGC_Reset; + } +} + +/** + * @brief Enables or disables the specified I2C interrupts. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg I2C_IT_BUF: Buffer interrupt mask + * @arg I2C_IT_EVT: Event interrupt mask + * @arg I2C_IT_ERR: Error interrupt mask + * @param NewState: new state of the specified I2C interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_I2C_CONFIG_IT(I2C_IT)); + + if (NewState != DISABLE) + { + /* Enable the selected I2C interrupts */ + I2Cx->CR2 |= I2C_IT; + } + else + { + /* Disable the selected I2C interrupts */ + I2Cx->CR2 &= (uint16_t)~I2C_IT; + } +} + +/** + * @brief Sends a data byte through the I2Cx peripheral. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param Data: Byte to be transmitted.. + * @retval None + */ +void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + /* Write in the DR register the data to be sent */ + I2Cx->DR = Data; +} + +/** + * @brief Returns the most recent received data by the I2Cx peripheral. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @retval The value of the received data. + */ +uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + /* Return the data in the DR register */ + return (uint8_t)I2Cx->DR; +} + +/** + * @brief Transmits the address byte to select the slave device. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param Address: specifies the slave address which will be transmitted + * @param I2C_Direction: specifies whether the I2C device will be a + * Transmitter or a Receiver. This parameter can be one of the following values + * @arg I2C_Direction_Transmitter: Transmitter mode + * @arg I2C_Direction_Receiver: Receiver mode + * @retval None. + */ +void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_DIRECTION(I2C_Direction)); + /* Test on the direction to set/reset the read/write bit */ + if (I2C_Direction != I2C_Direction_Transmitter) + { + /* Set the address bit0 for read */ + Address |= OAR1_ADD0_Set; + } + else + { + /* Reset the address bit0 for write */ + Address &= OAR1_ADD0_Reset; + } + /* Send the address */ + I2Cx->DR = Address; +} + +/** + * @brief Reads the specified I2C register and returns its value. + * @param I2C_Register: specifies the register to read. + * This parameter can be one of the following values: + * @arg I2C_Register_CR1: CR1 register. + * @arg I2C_Register_CR2: CR2 register. + * @arg I2C_Register_OAR1: OAR1 register. + * @arg I2C_Register_OAR2: OAR2 register. + * @arg I2C_Register_DR: DR register. + * @arg I2C_Register_SR1: SR1 register. + * @arg I2C_Register_SR2: SR2 register. + * @arg I2C_Register_CCR: CCR register. + * @arg I2C_Register_TRISE: TRISE register. + * @retval The value of the read register. + */ +uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_REGISTER(I2C_Register)); + + tmp = (uint32_t) I2Cx; + tmp += I2C_Register; + + /* Return the selected register value */ + return (*(__IO uint16_t *) tmp); +} + +/** + * @brief Enables or disables the specified I2C software reset. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C software reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Peripheral under reset */ + I2Cx->CR1 |= CR1_SWRST_Set; + } + else + { + /* Peripheral not under reset */ + I2Cx->CR1 &= CR1_SWRST_Reset; + } +} + +/** + * @brief Selects the specified I2C NACK position in master receiver mode. + * This function is useful in I2C Master Receiver mode when the number + * of data to be received is equal to 2. In this case, this function + * should be called (with parameter I2C_NACKPosition_Next) before data + * reception starts,as described in the 2-byte reception procedure + * recommended in Reference Manual in Section: Master receiver. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_NACKPosition: specifies the NACK position. + * This parameter can be one of the following values: + * @arg I2C_NACKPosition_Next: indicates that the next byte will be the last + * received byte. + * @arg I2C_NACKPosition_Current: indicates that current byte is the last + * received byte. + * + * @note This function configures the same bit (POS) as I2C_PECPositionConfig() + * but is intended to be used in I2C mode while I2C_PECPositionConfig() + * is intended to used in SMBUS mode. + * + * @retval None + */ +void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_NACK_POSITION(I2C_NACKPosition)); + + /* Check the input parameter */ + if (I2C_NACKPosition == I2C_NACKPosition_Next) + { + /* Next byte in shift register is the last received byte */ + I2Cx->CR1 |= I2C_NACKPosition_Next; + } + else + { + /* Current byte in shift register is the last received byte */ + I2Cx->CR1 &= I2C_NACKPosition_Current; + } +} + +/** + * @brief Drives the SMBusAlert pin high or low for the specified I2C. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_SMBusAlert: specifies SMBAlert pin level. + * This parameter can be one of the following values: + * @arg I2C_SMBusAlert_Low: SMBAlert pin driven low + * @arg I2C_SMBusAlert_High: SMBAlert pin driven high + * @retval None + */ +void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert)); + if (I2C_SMBusAlert == I2C_SMBusAlert_Low) + { + /* Drive the SMBusAlert pin Low */ + I2Cx->CR1 |= I2C_SMBusAlert_Low; + } + else + { + /* Drive the SMBusAlert pin High */ + I2Cx->CR1 &= I2C_SMBusAlert_High; + } +} + +/** + * @brief Enables or disables the specified I2C PEC transfer. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C PEC transmission. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C PEC transmission */ + I2Cx->CR1 |= CR1_PEC_Set; + } + else + { + /* Disable the selected I2C PEC transmission */ + I2Cx->CR1 &= CR1_PEC_Reset; + } +} + +/** + * @brief Selects the specified I2C PEC position. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_PECPosition: specifies the PEC position. + * This parameter can be one of the following values: + * @arg I2C_PECPosition_Next: indicates that the next byte is PEC + * @arg I2C_PECPosition_Current: indicates that current byte is PEC + * + * @note This function configures the same bit (POS) as I2C_NACKPositionConfig() + * but is intended to be used in SMBUS mode while I2C_NACKPositionConfig() + * is intended to used in I2C mode. + * + * @retval None + */ +void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition)); + if (I2C_PECPosition == I2C_PECPosition_Next) + { + /* Next byte in shift register is PEC */ + I2Cx->CR1 |= I2C_PECPosition_Next; + } + else + { + /* Current byte in shift register is PEC */ + I2Cx->CR1 &= I2C_PECPosition_Current; + } +} + +/** + * @brief Enables or disables the PEC value calculation of the transferred bytes. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2Cx PEC value calculation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C PEC calculation */ + I2Cx->CR1 |= CR1_ENPEC_Set; + } + else + { + /* Disable the selected I2C PEC calculation */ + I2Cx->CR1 &= CR1_ENPEC_Reset; + } +} + +/** + * @brief Returns the PEC value for the specified I2C. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @retval The PEC value. + */ +uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + /* Return the selected I2C PEC value */ + return ((I2Cx->SR2) >> 8); +} + +/** + * @brief Enables or disables the specified I2C ARP. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2Cx ARP. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C ARP */ + I2Cx->CR1 |= CR1_ENARP_Set; + } + else + { + /* Disable the selected I2C ARP */ + I2Cx->CR1 &= CR1_ENARP_Reset; + } +} + +/** + * @brief Enables or disables the specified I2C Clock stretching. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2Cx Clock stretching. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState == DISABLE) + { + /* Enable the selected I2C Clock stretching */ + I2Cx->CR1 |= CR1_NOSTRETCH_Set; + } + else + { + /* Disable the selected I2C Clock stretching */ + I2Cx->CR1 &= CR1_NOSTRETCH_Reset; + } +} + +/** + * @brief Selects the specified I2C fast mode duty cycle. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_DutyCycle: specifies the fast mode duty cycle. + * This parameter can be one of the following values: + * @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2 + * @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9 + * @retval None + */ +void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle)); + if (I2C_DutyCycle != I2C_DutyCycle_16_9) + { + /* I2C fast mode Tlow/Thigh=2 */ + I2Cx->CCR &= I2C_DutyCycle_2; + } + else + { + /* I2C fast mode Tlow/Thigh=16/9 */ + I2Cx->CCR |= I2C_DutyCycle_16_9; + } +} + + + +/** + * @brief + **************************************************************************************** + * + * I2C State Monitoring Functions + * + **************************************************************************************** + * This I2C driver provides three different ways for I2C state monitoring + * depending on the application requirements and constraints: + * + * + * 1) Basic state monitoring: + * Using I2C_CheckEvent() function: + * It compares the status registers (SR1 and SR2) content to a given event + * (can be the combination of one or more flags). + * It returns SUCCESS if the current status includes the given flags + * and returns ERROR if one or more flags are missing in the current status. + * - When to use: + * - This function is suitable for most applications as well as for startup + * activity since the events are fully described in the product reference manual + * (RM0008). + * - It is also suitable for users who need to define their own events. + * - Limitations: + * - If an error occurs (ie. error flags are set besides to the monitored flags), + * the I2C_CheckEvent() function may return SUCCESS despite the communication + * hold or corrupted real state. + * In this case, it is advised to use error interrupts to monitor the error + * events and handle them in the interrupt IRQ handler. + * + * @note + * For error management, it is advised to use the following functions: + * - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). + * - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. + * Where x is the peripheral instance (I2C1, I2C2 ...) + * - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler() + * in order to determine which error occured. + * - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() + * and/or I2C_GenerateStop() in order to clear the error flag and source, + * and return to correct communication status. + * + * + * 2) Advanced state monitoring: + * Using the function I2C_GetLastEvent() which returns the image of both status + * registers in a single word (uint32_t) (Status Register 2 value is shifted left + * by 16 bits and concatenated to Status Register 1). + * - When to use: + * - This function is suitable for the same applications above but it allows to + * overcome the mentioned limitation of I2C_GetFlagStatus() function. + * The returned value could be compared to events already defined in the + * library (stm32f10x_i2c.h) or to custom values defined by user. + * - This function is suitable when multiple flags are monitored at the same time. + * - At the opposite of I2C_CheckEvent() function, this function allows user to + * choose when an event is accepted (when all events flags are set and no + * other flags are set or just when the needed flags are set like + * I2C_CheckEvent() function). + * - Limitations: + * - User may need to define his own events. + * - Same remark concerning the error management is applicable for this + * function if user decides to check only regular communication flags (and + * ignores error flags). + * + * + * 3) Flag-based state monitoring: + * Using the function I2C_GetFlagStatus() which simply returns the status of + * one single flag (ie. I2C_FLAG_RXNE ...). + * - When to use: + * - This function could be used for specific applications or in debug phase. + * - It is suitable when only one flag checking is needed (most I2C events + * are monitored through multiple flags). + * - Limitations: + * - When calling this function, the Status register is accessed. Some flags are + * cleared when the status register is accessed. So checking the status + * of one Flag, may clear other ones. + * - Function may need to be called twice or more in order to monitor one + * single event. + * + * For detailed description of Events, please refer to section I2C_Events in + * stm32f10x_i2c.h file. + * + */ + +/** + * + * 1) Basic state monitoring + ******************************************************************************* + */ + +/** + * @brief Checks whether the last I2Cx Event is equal to the one passed + * as parameter. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_EVENT: specifies the event to be checked. + * This parameter can be one of the following values: + * @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED : EV1 + * @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED : EV1 + * @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED : EV1 + * @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED : EV1 + * @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED : EV1 + * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED : EV2 + * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) : EV2 + * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) : EV2 + * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED : EV3 + * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) : EV3 + * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) : EV3 + * @arg I2C_EVENT_SLAVE_ACK_FAILURE : EV3_2 + * @arg I2C_EVENT_SLAVE_STOP_DETECTED : EV4 + * @arg I2C_EVENT_MASTER_MODE_SELECT : EV5 + * @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED : EV6 + * @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED : EV6 + * @arg I2C_EVENT_MASTER_BYTE_RECEIVED : EV7 + * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING : EV8 + * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8_2 + * @arg I2C_EVENT_MASTER_MODE_ADDRESS10 : EV9 + * + * @note: For detailed description of Events, please refer to section + * I2C_Events in stm32f10x_i2c.h file. + * + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Last event is equal to the I2C_EVENT + * - ERROR: Last event is different from the I2C_EVENT + */ +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_EVENT(I2C_EVENT)); + + /* Read the I2Cx status register */ + flag1 = I2Cx->SR1; + flag2 = I2Cx->SR2; + flag2 = flag2 << 16; + + /* Get the last event value from I2C status register */ + lastevent = (flag1 | flag2) & FLAG_Mask; + + /* Check whether the last event contains the I2C_EVENT */ + if ((lastevent & I2C_EVENT) == I2C_EVENT) + { + /* SUCCESS: last event is equal to I2C_EVENT */ + status = SUCCESS; + } + else + { + /* ERROR: last event is different from I2C_EVENT */ + status = ERROR; + } + /* Return status */ + return status; +} + +/** + * + * 2) Advanced state monitoring + ******************************************************************************* + */ + +/** + * @brief Returns the last I2Cx Event. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * + * @note: For detailed description of Events, please refer to section + * I2C_Events in stm32f10x_i2c.h file. + * + * @retval The last event + */ +uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + /* Read the I2Cx status register */ + flag1 = I2Cx->SR1; + flag2 = I2Cx->SR2; + flag2 = flag2 << 16; + + /* Get the last event value from I2C status register */ + lastevent = (flag1 | flag2) & FLAG_Mask; + + /* Return status */ + return lastevent; +} + +/** + * + * 3) Flag-based state monitoring + ******************************************************************************* + */ + +/** + * @brief Checks whether the specified I2C flag is set or not. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg I2C_FLAG_DUALF: Dual flag (Slave mode) + * @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode) + * @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode) + * @arg I2C_FLAG_GENCALL: General call header flag (Slave mode) + * @arg I2C_FLAG_TRA: Transmitter/Receiver flag + * @arg I2C_FLAG_BUSY: Bus busy flag + * @arg I2C_FLAG_MSL: Master/Slave flag + * @arg I2C_FLAG_SMBALERT: SMBus Alert flag + * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag + * @arg I2C_FLAG_PECERR: PEC error in reception flag + * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) + * @arg I2C_FLAG_AF: Acknowledge failure flag + * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) + * @arg I2C_FLAG_BERR: Bus error flag + * @arg I2C_FLAG_TXE: Data register empty flag (Transmitter) + * @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag + * @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode) + * @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode) + * @arg I2C_FLAG_BTF: Byte transfer finished flag + * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) "ADSL" + * Address matched flag (Slave mode)"ENDA" + * @arg I2C_FLAG_SB: Start bit flag (Master mode) + * @retval The new state of I2C_FLAG (SET or RESET). + */ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) +{ + FlagStatus bitstatus = RESET; + __IO uint32_t i2creg = 0, i2cxbase = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_GET_FLAG(I2C_FLAG)); + + /* Get the I2Cx peripheral base address */ + i2cxbase = (uint32_t)I2Cx; + + /* Read flag register index */ + i2creg = I2C_FLAG >> 28; + + /* Get bit[23:0] of the flag */ + I2C_FLAG &= FLAG_Mask; + + if(i2creg != 0) + { + /* Get the I2Cx SR1 register address */ + i2cxbase += 0x14; + } + else + { + /* Flag in I2Cx SR2 Register */ + I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); + /* Get the I2Cx SR2 register address */ + i2cxbase += 0x18; + } + + if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) + { + /* I2C_FLAG is set */ + bitstatus = SET; + } + else + { + /* I2C_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the I2C_FLAG status */ + return bitstatus; +} + + + +/** + * @brief Clears the I2Cx's pending flags. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg I2C_FLAG_SMBALERT: SMBus Alert flag + * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag + * @arg I2C_FLAG_PECERR: PEC error in reception flag + * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) + * @arg I2C_FLAG_AF: Acknowledge failure flag + * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) + * @arg I2C_FLAG_BERR: Bus error flag + * + * @note + * - STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation + * to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral). + * - ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the + * second byte of the address in DR register. + * - BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a + * read/write to I2C_DR register (I2C_SendData()). + * - ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to + * I2C_SR2 register ((void)(I2Cx->SR2)). + * - SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1 + * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR + * register (I2C_SendData()). + * @retval None + */ +void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) +{ + uint32_t flagpos = 0; + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG)); + /* Get the I2C flag position */ + flagpos = I2C_FLAG & FLAG_Mask; + /* Clear the selected I2C flag */ + I2Cx->SR1 = (uint16_t)~flagpos; +} + +/** + * @brief Checks whether the specified I2C interrupt has occurred or not. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_IT: specifies the interrupt source to check. + * This parameter can be one of the following values: + * @arg I2C_IT_SMBALERT: SMBus Alert flag + * @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag + * @arg I2C_IT_PECERR: PEC error in reception flag + * @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode) + * @arg I2C_IT_AF: Acknowledge failure flag + * @arg I2C_IT_ARLO: Arbitration lost flag (Master mode) + * @arg I2C_IT_BERR: Bus error flag + * @arg I2C_IT_TXE: Data register empty flag (Transmitter) + * @arg I2C_IT_RXNE: Data register not empty (Receiver) flag + * @arg I2C_IT_STOPF: Stop detection flag (Slave mode) + * @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode) + * @arg I2C_IT_BTF: Byte transfer finished flag + * @arg I2C_IT_ADDR: Address sent flag (Master mode) "ADSL" + * Address matched flag (Slave mode)"ENDAD" + * @arg I2C_IT_SB: Start bit flag (Master mode) + * @retval The new state of I2C_IT (SET or RESET). + */ +ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_GET_IT(I2C_IT)); + + /* Check if the interrupt source is enabled or not */ + enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CR2)) ; + + /* Get bit[23:0] of the flag */ + I2C_IT &= FLAG_Mask; + + /* Check the status of the specified I2C flag */ + if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus) + { + /* I2C_IT is set */ + bitstatus = SET; + } + else + { + /* I2C_IT is reset */ + bitstatus = RESET; + } + /* Return the I2C_IT status */ + return bitstatus; +} + +/** + * @brief Clears the I2Cx抯 interrupt pending bits. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg I2C_IT_SMBALERT: SMBus Alert interrupt + * @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt + * @arg I2C_IT_PECERR: PEC error in reception interrupt + * @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode) + * @arg I2C_IT_AF: Acknowledge failure interrupt + * @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode) + * @arg I2C_IT_BERR: Bus error interrupt + * + * @note + * - STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to + * I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral). + * - ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second + * byte of the address in I2C_DR register. + * - BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_SR1 register (I2C_GetITStatus()) followed by a + * read/write to I2C_DR register (I2C_SendData()). + * - ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to + * I2C_SR2 register ((void)(I2Cx->SR2)). + * - SB (Start Bit) is cleared by software sequence: a read operation to + * I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to + * I2C_DR register (I2C_SendData()). + * @retval None + */ +void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT) +{ + uint32_t flagpos = 0; + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_CLEAR_IT(I2C_IT)); + /* Get the I2C flag position */ + flagpos = I2C_IT & FLAG_Mask; + /* Clear the selected I2C flag */ + I2Cx->SR1 = (uint16_t)~flagpos; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/STM32F10x_FWLIB/src/stm32f10x_iwdg.c b/STM32F10x_FWLIB/src/stm32f10x_iwdg.c new file mode 100644 index 0000000..dffe0cf --- /dev/null +++ b/STM32F10x_FWLIB/src/stm32f10x_iwdg.c @@ -0,0 +1,188 @@ +/** + ****************************************************************************** + * @file stm32f10x_iwdg.c + * @author MCD Application Team + * @version V3.6.2 + * @date 17-September-2021 + * @brief This file provides all the IWDG firmware functions. + ****************************************************************************** + * @attention + * + * Copyright (c) 2012 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_iwdg.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup IWDG + * @brief IWDG driver modules + * @{ + */ + +/** @defgroup IWDG_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup IWDG_Private_Defines + * @{ + */ + +/* ---------------------- IWDG registers bit mask ----------------------------*/ + +/* KR register bit mask */ +#define KR_KEY_Reload ((uint16_t)0xAAAA) +#define KR_KEY_Enable ((uint16_t)0xCCCC) + +/** + * @} + */ + +/** @defgroup IWDG_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup IWDG_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup IWDG_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup IWDG_Private_Functions + * @{ + */ + +/** + * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers. + * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers. + * This parameter can be one of the following values: + * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers + * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers + * @retval None + */ +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) +{ + /* Check the parameters */ + assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess)); + IWDG->KR = IWDG_WriteAccess; +} + +/** + * @brief Sets IWDG Prescaler value. + * @param IWDG_Prescaler: specifies the IWDG Prescaler value. + * This parameter can be one of the following values: + * @arg IWDG_Prescaler_4: IWDG prescaler set to 4 + * @arg IWDG_Prescaler_8: IWDG prescaler set to 8 + * @arg IWDG_Prescaler_16: IWDG prescaler set to 16 + * @arg IWDG_Prescaler_32: IWDG prescaler set to 32 + * @arg IWDG_Prescaler_64: IWDG prescaler set to 64 + * @arg IWDG_Prescaler_128: IWDG prescaler set to 128 + * @arg IWDG_Prescaler_256: IWDG prescaler set to 256 + * @retval None + */ +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) +{ + /* Check the parameters */ + assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler)); + IWDG->PR = IWDG_Prescaler; +} + +/** + * @brief Sets IWDG Reload value. + * @param Reload: specifies the IWDG Reload value. + * This parameter must be a number between 0 and 0x0FFF. + * @retval None + */ +void IWDG_SetReload(uint16_t Reload) +{ + /* Check the parameters */ + assert_param(IS_IWDG_RELOAD(Reload)); + IWDG->RLR = Reload; +} + +/** + * @brief Reloads IWDG counter with value defined in the reload register + * (write access to IWDG_PR and IWDG_RLR registers disabled). + * @param None + * @retval None + */ +void IWDG_ReloadCounter(void) +{ + IWDG->KR = KR_KEY_Reload; +} + +/** + * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled). + * @param None + * @retval None + */ +void IWDG_Enable(void) +{ + IWDG->KR = KR_KEY_Enable; +} + +/** + * @brief Checks whether the specified IWDG flag is set or not. + * @param IWDG_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg IWDG_FLAG_PVU: Prescaler Value Update on going + * @arg IWDG_FLAG_RVU: Reload Value Update on going + * @retval The new state of IWDG_FLAG (SET or RESET). + */ +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_IWDG_FLAG(IWDG_FLAG)); + if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/STM32F10x_FWLIB/src/stm32f10x_pwr.c b/STM32F10x_FWLIB/src/stm32f10x_pwr.c new file mode 100644 index 0000000..5b2499a --- /dev/null +++ b/STM32F10x_FWLIB/src/stm32f10x_pwr.c @@ -0,0 +1,304 @@ +/** + ****************************************************************************** + * @file stm32f10x_pwr.c + * @author MCD Application Team + * @version V3.6.2 + * @date 17-September-2021 + * @brief This file provides all the PWR firmware functions. + ****************************************************************************** + * @attention + * + * Copyright (c) 2012 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_pwr.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup PWR + * @brief PWR driver modules + * @{ + */ + +/** @defgroup PWR_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup PWR_Private_Defines + * @{ + */ + +/* --------- PWR registers bit address in the alias region ---------- */ +#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) + +/* --- CR Register ---*/ + +/* Alias word address of DBP bit */ +#define CR_OFFSET (PWR_OFFSET + 0x00) +#define DBP_BitNumber 0x08 +#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) + +/* Alias word address of PVDE bit */ +#define PVDE_BitNumber 0x04 +#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4)) + +/* --- CSR Register ---*/ + +/* Alias word address of EWUP bit */ +#define CSR_OFFSET (PWR_OFFSET + 0x04) +#define EWUP_BitNumber 0x08 +#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4)) + +/* ------------------ PWR registers bit mask ------------------------ */ + +/* CR register bit mask */ +#define CR_DS_MASK ((uint32_t)0xFFFFFFFC) +#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F) + + +/** + * @} + */ + +/** @defgroup PWR_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup PWR_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup PWR_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup PWR_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the PWR peripheral registers to their default reset values. + * @param None + * @retval None + */ +void PWR_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); +} + +/** + * @brief Enables or disables access to the RTC and backup registers. + * @param NewState: new state of the access to the RTC and backup registers. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_BackupAccessCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the Power Voltage Detector(PVD). + * @param NewState: new state of the PVD. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_PVDCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState; +} + +/** + * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). + * @param PWR_PVDLevel: specifies the PVD detection level + * This parameter can be one of the following values: + * @arg PWR_PVDLevel_2V2: PVD detection level set to 2.2V + * @arg PWR_PVDLevel_2V3: PVD detection level set to 2.3V + * @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V + * @arg PWR_PVDLevel_2V5: PVD detection level set to 2.5V + * @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V + * @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V + * @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V + * @arg PWR_PVDLevel_2V9: PVD detection level set to 2.9V + * @retval None + */ +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel)); + tmpreg = PWR->CR; + /* Clear PLS[7:5] bits */ + tmpreg &= CR_PLS_MASK; + /* Set PLS[7:5] bits according to PWR_PVDLevel value */ + tmpreg |= PWR_PVDLevel; + /* Store the new value */ + PWR->CR = tmpreg; +} + +/** + * @brief Enables or disables the WakeUp Pin functionality. + * @param NewState: new state of the WakeUp Pin functionality. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_WakeUpPinCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState; +} + +/** + * @brief Enters STOP mode. + * @param PWR_Regulator: specifies the regulator state in STOP mode. + * This parameter can be one of the following values: + * @arg PWR_Regulator_ON: STOP mode with regulator ON + * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode + * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction + * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction + * @retval None + */ +void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(PWR_Regulator)); + assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); + + /* Select the regulator state in STOP mode ---------------------------------*/ + tmpreg = PWR->CR; + /* Clear PDDS and LPDS bits */ + tmpreg &= CR_DS_MASK; + /* Set LPDS bit according to PWR_Regulator value */ + tmpreg |= PWR_Regulator; + /* Store the new value */ + PWR->CR = tmpreg; + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP; + + /* Select STOP mode entry --------------------------------------------------*/ + if(PWR_STOPEntry == PWR_STOPEntry_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __WFE(); + } + + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP); +} + +/** + * @brief Enters STANDBY mode. + * @note The Wakeup flag (WUF) need to be cleared at application level before to call this function + * @param None + * @retval None + */ +void PWR_EnterSTANDBYMode(void) +{ + /* Select STANDBY mode */ + PWR->CR |= PWR_CR_PDDS; + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP; +/* This option is used to ensure that store operations are completed */ +#if defined ( __CC_ARM ) + __force_stores(); +#endif + /* Request Wait For Interrupt */ + __WFI(); +} + +/** + * @brief Checks whether the specified PWR flag is set or not. + * @param PWR_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag + * @arg PWR_FLAG_SB: StandBy flag + * @arg PWR_FLAG_PVDO: PVD Output + * @retval The new state of PWR_FLAG (SET or RESET). + */ +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_PWR_GET_FLAG(PWR_FLAG)); + + if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the PWR's pending flags. + * @param PWR_FLAG: specifies the flag to clear. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag + * @arg PWR_FLAG_SB: StandBy flag + * @retval None + */ +void PWR_ClearFlag(uint32_t PWR_FLAG) +{ + /* Check the parameters */ + assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); + + PWR->CR |= PWR_FLAG << 2; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/STM32F10x_FWLIB/src/stm32f10x_rcc.c b/STM32F10x_FWLIB/src/stm32f10x_rcc.c new file mode 100644 index 0000000..d7d5455 --- /dev/null +++ b/STM32F10x_FWLIB/src/stm32f10x_rcc.c @@ -0,0 +1,1469 @@ +/** + ****************************************************************************** + * @file stm32f10x_rcc.c + * @author MCD Application Team + * @version V3.6.2 + * @date 17-September-2021 + * @brief This file provides all the RCC firmware functions. + ****************************************************************************** + * @attention + * + * Copyright (c) 2012 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup RCC + * @brief RCC driver modules + * @{ + */ + +/** @defgroup RCC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup RCC_Private_Defines + * @{ + */ + +/* ------------ RCC registers bit address in the alias region ----------- */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) + +/* --- CR Register ---*/ + +/* Alias word address of HSION bit */ +#define CR_OFFSET (RCC_OFFSET + 0x00) +#define HSION_BitNumber 0x00 +#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) + +/* Alias word address of PLLON bit */ +#define PLLON_BitNumber 0x18 +#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) + +#ifdef STM32F10X_CL + /* Alias word address of PLL2ON bit */ + #define PLL2ON_BitNumber 0x1A + #define CR_PLL2ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL2ON_BitNumber * 4)) + + /* Alias word address of PLL3ON bit */ + #define PLL3ON_BitNumber 0x1C + #define CR_PLL3ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL3ON_BitNumber * 4)) +#endif /* STM32F10X_CL */ + +/* Alias word address of CSSON bit */ +#define CSSON_BitNumber 0x13 +#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) + +/* --- CFGR Register ---*/ + +/* Alias word address of USBPRE bit */ +#define CFGR_OFFSET (RCC_OFFSET + 0x04) + +#ifndef STM32F10X_CL + #define USBPRE_BitNumber 0x16 + #define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4)) +#else + #define OTGFSPRE_BitNumber 0x16 + #define CFGR_OTGFSPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (OTGFSPRE_BitNumber * 4)) +#endif /* STM32F10X_CL */ + +/* --- BDCR Register ---*/ + +/* Alias word address of RTCEN bit */ +#define BDCR_OFFSET (RCC_OFFSET + 0x20) +#define RTCEN_BitNumber 0x0F +#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4)) + +/* Alias word address of BDRST bit */ +#define BDRST_BitNumber 0x10 +#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) + +/* --- CSR Register ---*/ + +/* Alias word address of LSION bit */ +#define CSR_OFFSET (RCC_OFFSET + 0x24) +#define LSION_BitNumber 0x00 +#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) + +#ifdef STM32F10X_CL +/* --- CFGR2 Register ---*/ + + /* Alias word address of I2S2SRC bit */ + #define CFGR2_OFFSET (RCC_OFFSET + 0x2C) + #define I2S2SRC_BitNumber 0x11 + #define CFGR2_I2S2SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S2SRC_BitNumber * 4)) + + /* Alias word address of I2S3SRC bit */ + #define I2S3SRC_BitNumber 0x12 + #define CFGR2_I2S3SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S3SRC_BitNumber * 4)) +#endif /* STM32F10X_CL */ + +/* ---------------------- RCC registers bit mask ------------------------ */ + +/* CR register bit mask */ +#define CR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) +#define CR_HSEBYP_Set ((uint32_t)0x00040000) +#define CR_HSEON_Reset ((uint32_t)0xFFFEFFFF) +#define CR_HSEON_Set ((uint32_t)0x00010000) +#define CR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) + +/* CFGR register bit mask */ +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) + #define CFGR_PLL_Mask ((uint32_t)0xFFC2FFFF) +#else + #define CFGR_PLL_Mask ((uint32_t)0xFFC0FFFF) +#endif /* STM32F10X_CL */ + +#define CFGR_PLLMull_Mask ((uint32_t)0x003C0000) +#define CFGR_PLLSRC_Mask ((uint32_t)0x00010000) +#define CFGR_PLLXTPRE_Mask ((uint32_t)0x00020000) +#define CFGR_SWS_Mask ((uint32_t)0x0000000C) +#define CFGR_SW_Mask ((uint32_t)0xFFFFFFFC) +#define CFGR_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) +#define CFGR_HPRE_Set_Mask ((uint32_t)0x000000F0) +#define CFGR_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF) +#define CFGR_PPRE1_Set_Mask ((uint32_t)0x00000700) +#define CFGR_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF) +#define CFGR_PPRE2_Set_Mask ((uint32_t)0x00003800) +#define CFGR_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF) +#define CFGR_ADCPRE_Set_Mask ((uint32_t)0x0000C000) + +/* CSR register bit mask */ +#define CSR_RMVF_Set ((uint32_t)0x01000000) + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) +/* CFGR2 register bit mask */ + #define CFGR2_PREDIV1SRC ((uint32_t)0x00010000) + #define CFGR2_PREDIV1 ((uint32_t)0x0000000F) +#endif +#ifdef STM32F10X_CL + #define CFGR2_PREDIV2 ((uint32_t)0x000000F0) + #define CFGR2_PLL2MUL ((uint32_t)0x00000F00) + #define CFGR2_PLL3MUL ((uint32_t)0x0000F000) +#endif /* STM32F10X_CL */ + +/* RCC Flag Mask */ +#define FLAG_Mask ((uint8_t)0x1F) + +/* CIR register byte 2 (Bits[15:8]) base address */ +#define CIR_BYTE2_ADDRESS ((uint32_t)0x40021009) + +/* CIR register byte 3 (Bits[23:16]) base address */ +#define CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A) + +/* CFGR register byte 4 (Bits[31:24]) base address */ +#define CFGR_BYTE4_ADDRESS ((uint32_t)0x40021007) + +/* BDCR register base address */ +#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET) + +/** + * @} + */ + +/** @defgroup RCC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup RCC_Private_Variables + * @{ + */ + +static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; +static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8}; + +/** + * @} + */ + +/** @defgroup RCC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup RCC_Private_Functions + * @{ + */ + +/** + * @brief Resets the RCC clock configuration to the default reset state. + * @param None + * @retval None + */ +void RCC_DeInit(void) +{ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ +#ifndef STM32F10X_CL + RCC->CFGR &= (uint32_t)0xF8FF0000; +#else + RCC->CFGR &= (uint32_t)0xF0FF0000; +#endif /* STM32F10X_CL */ + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ + RCC->CFGR &= (uint32_t)0xFF80FFFF; + +#ifdef STM32F10X_CL + /* Reset PLL2ON and PLL3ON bits */ + RCC->CR &= (uint32_t)0xEBFFFFFF; + + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x00FF0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#else + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; +#endif /* STM32F10X_CL */ + +} + +/** + * @brief Configures the External High Speed oscillator (HSE). + * @note HSE can not be stopped if it is used directly or through the PLL as system clock. + * @param RCC_HSE: specifies the new state of the HSE. + * This parameter can be one of the following values: + * @arg RCC_HSE_OFF: HSE oscillator OFF + * @arg RCC_HSE_ON: HSE oscillator ON + * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock + * @retval None + */ +void RCC_HSEConfig(uint32_t RCC_HSE) +{ + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_HSE)); + /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ + /* Reset HSEON bit */ + RCC->CR &= CR_HSEON_Reset; + /* Reset HSEBYP bit */ + RCC->CR &= CR_HSEBYP_Reset; + /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */ + switch(RCC_HSE) + { + case RCC_HSE_ON: + /* Set HSEON bit */ + RCC->CR |= CR_HSEON_Set; + break; + + case RCC_HSE_Bypass: + /* Set HSEBYP and HSEON bits */ + RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set; + break; + + default: + break; + } +} + +/** + * @brief Waits for HSE start-up. + * @param None + * @retval An ErrorStatus enumuration value: + * - SUCCESS: HSE oscillator is stable and ready to use + * - ERROR: HSE oscillator not yet ready + */ +ErrorStatus RCC_WaitForHSEStartUp(void) +{ + __IO uint32_t StartUpCounter = 0; + ErrorStatus status = ERROR; + FlagStatus HSEStatus = RESET; + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); + StartUpCounter++; + } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET)); + + if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + return (status); +} + +/** + * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. + * @param HSICalibrationValue: specifies the calibration trimming value. + * This parameter must be a number between 0 and 0x1F. + * @retval None + */ +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue)); + tmpreg = RCC->CR; + /* Clear HSITRIM[4:0] bits */ + tmpreg &= CR_HSITRIM_Mask; + /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */ + tmpreg |= (uint32_t)HSICalibrationValue << 3; + /* Store the new value */ + RCC->CR = tmpreg; +} + +/** + * @brief Enables or disables the Internal High Speed oscillator (HSI). + * @note HSI can not be stopped if it is used directly or through the PLL as system clock. + * @param NewState: new state of the HSI. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_HSICmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState; +} + +/** + * @brief Configures the PLL clock source and multiplication factor. + * @note This function must be used only when the PLL is disabled. + * @param RCC_PLLSource: specifies the PLL entry clock source. + * For @b STM32_Connectivity_line_devices or @b STM32_Value_line_devices, + * this parameter can be one of the following values: + * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry + * @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry + * For @b other_STM32_devices, this parameter can be one of the following values: + * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry + * @arg RCC_PLLSource_HSE_Div1: HSE oscillator clock selected as PLL clock entry + * @arg RCC_PLLSource_HSE_Div2: HSE oscillator clock divided by 2 selected as PLL clock entry + * @param RCC_PLLMul: specifies the PLL multiplication factor. + * For @b STM32_Connectivity_line_devices, this parameter can be RCC_PLLMul_x where x:{[4,9], 6_5} + * For @b other_STM32_devices, this parameter can be RCC_PLLMul_x where x:[2,16] + * @retval None + */ +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource)); + assert_param(IS_RCC_PLL_MUL(RCC_PLLMul)); + + tmpreg = RCC->CFGR; + /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ + tmpreg &= CFGR_PLL_Mask; + /* Set the PLL configuration bits */ + tmpreg |= RCC_PLLSource | RCC_PLLMul; + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Enables or disables the PLL. + * @note The PLL can not be disabled if it is used as system clock. + * @param NewState: new state of the PLL. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_PLLCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState; +} + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) +/** + * @brief Configures the PREDIV1 division factor. + * @note + * - This function must be used only when the PLL is disabled. + * - This function applies only to STM32 Connectivity line and Value line + * devices. + * @param RCC_PREDIV1_Source: specifies the PREDIV1 clock source. + * This parameter can be one of the following values: + * @arg RCC_PREDIV1_Source_HSE: HSE selected as PREDIV1 clock + * @arg RCC_PREDIV1_Source_PLL2: PLL2 selected as PREDIV1 clock + * @note + * For @b STM32_Value_line_devices this parameter is always RCC_PREDIV1_Source_HSE + * @param RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor. + * This parameter can be RCC_PREDIV1_Divx where x:[1,16] + * @retval None + */ +void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PREDIV1_SOURCE(RCC_PREDIV1_Source)); + assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div)); + + tmpreg = RCC->CFGR2; + /* Clear PREDIV1[3:0] and PREDIV1SRC bits */ + tmpreg &= ~(CFGR2_PREDIV1 | CFGR2_PREDIV1SRC); + /* Set the PREDIV1 clock source and division factor */ + tmpreg |= RCC_PREDIV1_Source | RCC_PREDIV1_Div ; + /* Store the new value */ + RCC->CFGR2 = tmpreg; +} +#endif + +#ifdef STM32F10X_CL +/** + * @brief Configures the PREDIV2 division factor. + * @note + * - This function must be used only when both PLL2 and PLL3 are disabled. + * - This function applies only to STM32 Connectivity line devices. + * @param RCC_PREDIV2_Div: specifies the PREDIV2 clock division factor. + * This parameter can be RCC_PREDIV2_Divx where x:[1,16] + * @retval None + */ +void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PREDIV2(RCC_PREDIV2_Div)); + + tmpreg = RCC->CFGR2; + /* Clear PREDIV2[3:0] bits */ + tmpreg &= ~CFGR2_PREDIV2; + /* Set the PREDIV2 division factor */ + tmpreg |= RCC_PREDIV2_Div; + /* Store the new value */ + RCC->CFGR2 = tmpreg; +} + +/** + * @brief Configures the PLL2 multiplication factor. + * @note + * - This function must be used only when the PLL2 is disabled. + * - This function applies only to STM32 Connectivity line devices. + * @param RCC_PLL2Mul: specifies the PLL2 multiplication factor. + * This parameter can be RCC_PLL2Mul_x where x:{[8,14], 16, 20} + * @retval None + */ +void RCC_PLL2Config(uint32_t RCC_PLL2Mul) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PLL2_MUL(RCC_PLL2Mul)); + + tmpreg = RCC->CFGR2; + /* Clear PLL2Mul[3:0] bits */ + tmpreg &= ~CFGR2_PLL2MUL; + /* Set the PLL2 configuration bits */ + tmpreg |= RCC_PLL2Mul; + /* Store the new value */ + RCC->CFGR2 = tmpreg; +} + + +/** + * @brief Enables or disables the PLL2. + * @note + * - The PLL2 can not be disabled if it is used indirectly as system clock + * (i.e. it is used as PLL clock entry that is used as System clock). + * - This function applies only to STM32 Connectivity line devices. + * @param NewState: new state of the PLL2. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_PLL2Cmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CR_PLL2ON_BB = (uint32_t)NewState; +} + + +/** + * @brief Configures the PLL3 multiplication factor. + * @note + * - This function must be used only when the PLL3 is disabled. + * - This function applies only to STM32 Connectivity line devices. + * @param RCC_PLL3Mul: specifies the PLL3 multiplication factor. + * This parameter can be RCC_PLL3Mul_x where x:{[8,14], 16, 20} + * @retval None + */ +void RCC_PLL3Config(uint32_t RCC_PLL3Mul) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PLL3_MUL(RCC_PLL3Mul)); + + tmpreg = RCC->CFGR2; + /* Clear PLL3Mul[3:0] bits */ + tmpreg &= ~CFGR2_PLL3MUL; + /* Set the PLL3 configuration bits */ + tmpreg |= RCC_PLL3Mul; + /* Store the new value */ + RCC->CFGR2 = tmpreg; +} + + +/** + * @brief Enables or disables the PLL3. + * @note This function applies only to STM32 Connectivity line devices. + * @param NewState: new state of the PLL3. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_PLL3Cmd(FunctionalState NewState) +{ + /* Check the parameters */ + + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_PLL3ON_BB = (uint32_t)NewState; +} +#endif /* STM32F10X_CL */ + +/** + * @brief Configures the system clock (SYSCLK). + * @param RCC_SYSCLKSource: specifies the clock source used as system clock. + * This parameter can be one of the following values: + * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock + * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock + * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock + * @retval None + */ +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource)); + tmpreg = RCC->CFGR; + /* Clear SW[1:0] bits */ + tmpreg &= CFGR_SW_Mask; + /* Set SW[1:0] bits according to RCC_SYSCLKSource value */ + tmpreg |= RCC_SYSCLKSource; + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Returns the clock source used as system clock. + * @param None + * @retval The clock source used as system clock. The returned value can + * be one of the following: + * - 0x00: HSI used as system clock + * - 0x04: HSE used as system clock + * - 0x08: PLL used as system clock + */ +uint8_t RCC_GetSYSCLKSource(void) +{ + return ((uint8_t)(RCC->CFGR & CFGR_SWS_Mask)); +} + +/** + * @brief Configures the AHB clock (HCLK). + * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from + * the system clock (SYSCLK). + * This parameter can be one of the following values: + * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK + * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2 + * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4 + * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8 + * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16 + * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64 + * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128 + * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256 + * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512 + * @retval None + */ +void RCC_HCLKConfig(uint32_t RCC_SYSCLK) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_HCLK(RCC_SYSCLK)); + tmpreg = RCC->CFGR; + /* Clear HPRE[3:0] bits */ + tmpreg &= CFGR_HPRE_Reset_Mask; + /* Set HPRE[3:0] bits according to RCC_SYSCLK value */ + tmpreg |= RCC_SYSCLK; + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Configures the Low Speed APB clock (PCLK1). + * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from + * the AHB clock (HCLK). + * This parameter can be one of the following values: + * @arg RCC_HCLK_Div1: APB1 clock = HCLK + * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2 + * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4 + * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8 + * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16 + * @retval None + */ +void RCC_PCLK1Config(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_PCLK(RCC_HCLK)); + tmpreg = RCC->CFGR; + /* Clear PPRE1[2:0] bits */ + tmpreg &= CFGR_PPRE1_Reset_Mask; + /* Set PPRE1[2:0] bits according to RCC_HCLK value */ + tmpreg |= RCC_HCLK; + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Configures the High Speed APB clock (PCLK2). + * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from + * the AHB clock (HCLK). + * This parameter can be one of the following values: + * @arg RCC_HCLK_Div1: APB2 clock = HCLK + * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2 + * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4 + * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8 + * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16 + * @retval None + */ +void RCC_PCLK2Config(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_PCLK(RCC_HCLK)); + tmpreg = RCC->CFGR; + /* Clear PPRE2[2:0] bits */ + tmpreg &= CFGR_PPRE2_Reset_Mask; + /* Set PPRE2[2:0] bits according to RCC_HCLK value */ + tmpreg |= RCC_HCLK << 3; + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Enables or disables the specified RCC interrupts. + * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled. + * + * For @b STM32_Connectivity_line_devices, this parameter can be any combination + * of the following values + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: PLL ready interrupt + * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt + * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt + * + * For @b other_STM32_devices, this parameter can be any combination of the + * following values + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: PLL ready interrupt + * + * @param NewState: new state of the specified RCC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_IT(RCC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Perform Byte access to RCC_CIR bits to enable the selected interrupts */ + *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT; + } + else + { + /* Perform Byte access to RCC_CIR bits to disable the selected interrupts */ + *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; + } +} + +#ifndef STM32F10X_CL +/** + * @brief Configures the USB clock (USBCLK). + * @param RCC_USBCLKSource: specifies the USB clock source. This clock is + * derived from the PLL output. + * This parameter can be one of the following values: + * @arg RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB + * clock source + * @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source + * @retval None + */ +void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource)); + + *(__IO uint32_t *) CFGR_USBPRE_BB = RCC_USBCLKSource; +} +#else +/** + * @brief Configures the USB OTG FS clock (OTGFSCLK). + * This function applies only to STM32 Connectivity line devices. + * @param RCC_OTGFSCLKSource: specifies the USB OTG FS clock source. + * This clock is derived from the PLL output. + * This parameter can be one of the following values: + * @arg RCC_OTGFSCLKSource_PLLVCO_Div3: PLL VCO clock divided by 2 selected as USB OTG FS clock source + * @arg RCC_OTGFSCLKSource_PLLVCO_Div2: PLL VCO clock divided by 2 selected as USB OTG FS clock source + * @retval None + */ +void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_OTGFSCLK_SOURCE(RCC_OTGFSCLKSource)); + + *(__IO uint32_t *) CFGR_OTGFSPRE_BB = RCC_OTGFSCLKSource; +} +#endif /* STM32F10X_CL */ + +/** + * @brief Configures the ADC clock (ADCCLK). + * @param RCC_PCLK2: defines the ADC clock divider. This clock is derived from + * the APB2 clock (PCLK2). + * This parameter can be one of the following values: + * @arg RCC_PCLK2_Div2: ADC clock = PCLK2/2 + * @arg RCC_PCLK2_Div4: ADC clock = PCLK2/4 + * @arg RCC_PCLK2_Div6: ADC clock = PCLK2/6 + * @arg RCC_PCLK2_Div8: ADC clock = PCLK2/8 + * @retval None + */ +void RCC_ADCCLKConfig(uint32_t RCC_PCLK2) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_ADCCLK(RCC_PCLK2)); + tmpreg = RCC->CFGR; + /* Clear ADCPRE[1:0] bits */ + tmpreg &= CFGR_ADCPRE_Reset_Mask; + /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */ + tmpreg |= RCC_PCLK2; + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +#ifdef STM32F10X_CL +/** + * @brief Configures the I2S2 clock source(I2S2CLK). + * @note + * - This function must be called before enabling I2S2 APB clock. + * - This function applies only to STM32 Connectivity line devices. + * @param RCC_I2S2CLKSource: specifies the I2S2 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2S2CLKSource_SYSCLK: system clock selected as I2S2 clock entry + * @arg RCC_I2S2CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S2 clock entry + * @retval None + */ +void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_I2S2CLK_SOURCE(RCC_I2S2CLKSource)); + + *(__IO uint32_t *) CFGR2_I2S2SRC_BB = RCC_I2S2CLKSource; +} + +/** + * @brief Configures the I2S3 clock source(I2S2CLK). + * @note + * - This function must be called before enabling I2S3 APB clock. + * - This function applies only to STM32 Connectivity line devices. + * @param RCC_I2S3CLKSource: specifies the I2S3 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2S3CLKSource_SYSCLK: system clock selected as I2S3 clock entry + * @arg RCC_I2S3CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S3 clock entry + * @retval None + */ +void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_I2S3CLK_SOURCE(RCC_I2S3CLKSource)); + + *(__IO uint32_t *) CFGR2_I2S3SRC_BB = RCC_I2S3CLKSource; +} +#endif /* STM32F10X_CL */ + +/** + * @brief Configures the External Low Speed oscillator (LSE). + * @note LSEON is cleared regardless of the function's argument value. + * @param RCC_LSE: specifies the new state of the LSE. + * This parameter can be one of the following values: + * @arg RCC_LSE_OFF: LSE oscillator OFF + * @arg RCC_LSE_ON: LSE oscillator ON + * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock + * @retval None + */ +void RCC_LSEConfig(uint8_t RCC_LSE) +{ + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_LSE)); + /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/ + /* Reset LSEON bit */ + *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; + /* Reset LSEBYP bit */ + *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; + /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */ + switch(RCC_LSE) + { + case RCC_LSE_ON: + /* Set LSEON bit */ + *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON; + break; + + case RCC_LSE_Bypass: + /* Set LSEBYP and LSEON bits */ + *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON; + break; + + default: + break; + } +} + +/** + * @brief Enables or disables the Internal Low Speed oscillator (LSI). + * @note LSI can not be disabled if the IWDG is running. + * @param NewState: new state of the LSI. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_LSICmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState; +} + +/** + * @brief Configures the RTC clock (RTCCLK). + * @note Once the RTC clock is selected it can't be changed unless the Backup domain is reset. + * @param RCC_RTCCLKSource: specifies the RTC clock source. + * This parameter can be one of the following values: + * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock + * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock + * @arg RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128 selected as RTC clock + * @retval None + */ +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource)); + /* Select the RTC clock source */ + RCC->BDCR |= RCC_RTCCLKSource; +} + +/** + * @brief Enables or disables the RTC clock. + * @note This function must be used only after the RTC clock was selected using the RCC_RTCCLKConfig function. + * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_RTCCLKCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState; +} + +/** + * @brief Returns the frequencies of different on chip clocks. + * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold + * the clocks frequencies. + * @note The result of this function could be not correct when using + * fractional value for HSE crystal. + * @retval None + */ +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0; + +#ifdef STM32F10X_CL + uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + uint32_t prediv1factor = 0; +#endif + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & CFGR_SWS_Mask; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock */ + RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock */ + + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & CFGR_PLLMull_Mask; + pllsource = RCC->CFGR & CFGR_PLLSRC_Mask; + +#ifndef STM32F10X_CL + pllmull = ( pllmull >> 18) + 2; + + if (pllsource == 0x00) + {/* HSI oscillator clock divided by 2 selected as PLL clock entry */ + RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull; + } + else + { + #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull; + #else + /* HSE selected as PLL clock entry */ + if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET) + {/* HSE oscillator clock divided by 2 */ + RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull; + } + else + { + RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull; + } + #endif + } +#else + pllmull = pllmull >> 18; + + if (pllmull != 0x0D) + { + pllmull += 2; + } + else + { /* PLL multiplication factor = PLL input clock * 6.5 */ + pllmull = 13 / 2; + } + + if (pllsource == 0x00) + {/* HSI oscillator clock divided by 2 selected as PLL clock entry */ + RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull; + } + else + {/* PREDIV1 selected as PLL clock entry */ + + /* Get PREDIV1 clock source and division factor */ + prediv1source = RCC->CFGR2 & CFGR2_PREDIV1SRC; + prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1; + + if (prediv1source == 0) + { /* HSE oscillator clock selected as PREDIV1 clock entry */ + RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull; + } + else + {/* PLL2 clock selected as PREDIV1 clock entry */ + + /* Get PREDIV2 division factor and PLL2 multiplication factor */ + prediv2factor = ((RCC->CFGR2 & CFGR2_PREDIV2) >> 4) + 1; + pll2mull = ((RCC->CFGR2 & CFGR2_PLL2MUL) >> 8 ) + 2; + RCC_Clocks->SYSCLK_Frequency = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; + } + } +#endif /* STM32F10X_CL */ + break; + + default: + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + break; + } + + /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/ + /* Get HCLK prescaler */ + tmp = RCC->CFGR & CFGR_HPRE_Set_Mask; + tmp = tmp >> 4; + presc = APBAHBPrescTable[tmp]; + /* HCLK clock frequency */ + RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; + /* Get PCLK1 prescaler */ + tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask; + tmp = tmp >> 8; + presc = APBAHBPrescTable[tmp]; + /* PCLK1 clock frequency */ + RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + /* Get PCLK2 prescaler */ + tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask; + tmp = tmp >> 11; + presc = APBAHBPrescTable[tmp]; + /* PCLK2 clock frequency */ + RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + /* Get ADCCLK prescaler */ + tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask; + tmp = tmp >> 14; + presc = ADCPrescTable[tmp]; + /* ADCCLK clock frequency */ + RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc; +} + +/** + * @brief Enables or disables the AHB peripheral clock. + * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock. + * + * For @b STM32_Connectivity_line_devices, this parameter can be any combination + * of the following values: + * @arg RCC_AHBPeriph_DMA1 + * @arg RCC_AHBPeriph_DMA2 + * @arg RCC_AHBPeriph_SRAM + * @arg RCC_AHBPeriph_FLITF + * @arg RCC_AHBPeriph_CRC + * @arg RCC_AHBPeriph_OTG_FS + * @arg RCC_AHBPeriph_ETH_MAC + * @arg RCC_AHBPeriph_ETH_MAC_Tx + * @arg RCC_AHBPeriph_ETH_MAC_Rx + * + * For @b other_STM32_devices, this parameter can be any combination of the + * following values: + * @arg RCC_AHBPeriph_DMA1 + * @arg RCC_AHBPeriph_DMA2 + * @arg RCC_AHBPeriph_SRAM + * @arg RCC_AHBPeriph_FLITF + * @arg RCC_AHBPeriph_CRC + * @arg RCC_AHBPeriph_FSMC + * @arg RCC_AHBPeriph_SDIO + * + * @note SRAM and FLITF clock can be disabled only during sleep mode. + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHBENR |= RCC_AHBPeriph; + } + else + { + RCC->AHBENR &= ~RCC_AHBPeriph; + } +} + +/** + * @brief Enables or disables the High Speed APB (APB2) peripheral clock. + * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB, + * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, + * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1, + * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, + * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3, + * RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17, + * RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11 + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB2ENR |= RCC_APB2Periph; + } + else + { + RCC->APB2ENR &= ~RCC_APB2Periph; + } +} + +/** + * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. + * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, + * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, + * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, + * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, + * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, + * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP, + * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC, + * RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14 + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB1ENR |= RCC_APB1Periph; + } + else + { + RCC->APB1ENR &= ~RCC_APB1Periph; + } +} + +#ifdef STM32F10X_CL +/** + * @brief Forces or releases AHB peripheral reset. + * @note This function applies only to STM32 Connectivity line devices. + * @param RCC_AHBPeriph: specifies the AHB peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_AHBPeriph_OTG_FS + * @arg RCC_AHBPeriph_ETH_MAC + * @param NewState: new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB_PERIPH_RESET(RCC_AHBPeriph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHBRSTR |= RCC_AHBPeriph; + } + else + { + RCC->AHBRSTR &= ~RCC_AHBPeriph; + } +} +#endif /* STM32F10X_CL */ + +/** + * @brief Forces or releases High Speed APB (APB2) peripheral reset. + * @param RCC_APB2Periph: specifies the APB2 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB, + * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, + * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1, + * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, + * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3, + * RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17, + * RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11 + * @param NewState: new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB2RSTR |= RCC_APB2Periph; + } + else + { + RCC->APB2RSTR &= ~RCC_APB2Periph; + } +} + +/** + * @brief Forces or releases Low Speed APB (APB1) peripheral reset. + * @param RCC_APB1Periph: specifies the APB1 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, + * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, + * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, + * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, + * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, + * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP, + * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC, + * RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14 + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB1RSTR |= RCC_APB1Periph; + } + else + { + RCC->APB1RSTR &= ~RCC_APB1Periph; + } +} + +/** + * @brief Forces or releases the Backup domain reset. + * @param NewState: new state of the Backup domain reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_BackupResetCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the Clock Security System. + * @param NewState: new state of the Clock Security System.. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_ClockSecuritySystemCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState; +} + +/** + * @brief Selects the clock source to output on MCO pin. + * @param RCC_MCO: specifies the clock source to output. + * + * For @b STM32_Connectivity_line_devices, this parameter can be one of the + * following values: + * @arg RCC_MCO_NoClock: No clock selected + * @arg RCC_MCO_SYSCLK: System clock selected + * @arg RCC_MCO_HSI: HSI oscillator clock selected + * @arg RCC_MCO_HSE: HSE oscillator clock selected + * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected + * @arg RCC_MCO_PLL2CLK: PLL2 clock selected + * @arg RCC_MCO_PLL3CLK_Div2: PLL3 clock divided by 2 selected + * @arg RCC_MCO_XT1: External 3-25 MHz oscillator clock selected + * @arg RCC_MCO_PLL3CLK: PLL3 clock selected + * + * For @b other_STM32_devices, this parameter can be one of the following values: + * @arg RCC_MCO_NoClock: No clock selected + * @arg RCC_MCO_SYSCLK: System clock selected + * @arg RCC_MCO_HSI: HSI oscillator clock selected + * @arg RCC_MCO_HSE: HSE oscillator clock selected + * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected + * + * @retval None + */ +void RCC_MCOConfig(uint8_t RCC_MCO) +{ + /* Check the parameters */ + assert_param(IS_RCC_MCO(RCC_MCO)); + + /* Perform Byte access to MCO bits to select the MCO source */ + *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCO; +} + +/** + * @brief Checks whether the specified RCC flag is set or not. + * @param RCC_FLAG: specifies the flag to check. + * + * For @b STM32_Connectivity_line_devices, this parameter can be one of the + * following values: + * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready + * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready + * @arg RCC_FLAG_PLLRDY: PLL clock ready + * @arg RCC_FLAG_PLL2RDY: PLL2 clock ready + * @arg RCC_FLAG_PLL3RDY: PLL3 clock ready + * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready + * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready + * @arg RCC_FLAG_PINRST: Pin reset + * @arg RCC_FLAG_PORRST: POR/PDR reset + * @arg RCC_FLAG_SFTRST: Software reset + * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset + * @arg RCC_FLAG_WWDGRST: Window Watchdog reset + * @arg RCC_FLAG_LPWRRST: Low Power reset + * + * For @b other_STM32_devices, this parameter can be one of the following values: + * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready + * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready + * @arg RCC_FLAG_PLLRDY: PLL clock ready + * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready + * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready + * @arg RCC_FLAG_PINRST: Pin reset + * @arg RCC_FLAG_PORRST: POR/PDR reset + * @arg RCC_FLAG_SFTRST: Software reset + * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset + * @arg RCC_FLAG_WWDGRST: Window Watchdog reset + * @arg RCC_FLAG_LPWRRST: Low Power reset + * + * @retval The new state of RCC_FLAG (SET or RESET). + */ +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) +{ + uint32_t tmp = 0; + uint32_t statusreg = 0; + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_RCC_FLAG(RCC_FLAG)); + + /* Get the RCC register index */ + tmp = RCC_FLAG >> 5; + if (tmp == 1) /* The flag to check is in CR register */ + { + statusreg = RCC->CR; + } + else if (tmp == 2) /* The flag to check is in BDCR register */ + { + statusreg = RCC->BDCR; + } + else /* The flag to check is in CSR register */ + { + statusreg = RCC->CSR; + } + + /* Get the flag position */ + tmp = RCC_FLAG & FLAG_Mask; + if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the RCC reset flags. + * @note The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, + * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST + * @param None + * @retval None + */ +void RCC_ClearFlag(void) +{ + /* Set RMVF bit to clear the reset flags */ + RCC->CSR |= CSR_RMVF_Set; +} + +/** + * @brief Checks whether the specified RCC interrupt has occurred or not. + * @param RCC_IT: specifies the RCC interrupt source to check. + * + * For @b STM32_Connectivity_line_devices, this parameter can be one of the + * following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: PLL ready interrupt + * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt + * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt + * @arg RCC_IT_CSS: Clock Security System interrupt + * + * For @b other_STM32_devices, this parameter can be one of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: PLL ready interrupt + * @arg RCC_IT_CSS: Clock Security System interrupt + * + * @retval The new state of RCC_IT (SET or RESET). + */ +ITStatus RCC_GetITStatus(uint8_t RCC_IT) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_RCC_GET_IT(RCC_IT)); + + /* Check the status of the specified RCC interrupt */ + if ((RCC->CIR & RCC_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + /* Return the RCC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the RCC's interrupt pending bits. + * @param RCC_IT: specifies the interrupt pending bit to clear. + * + * For @b STM32_Connectivity_line_devices, this parameter can be any combination + * of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: PLL ready interrupt + * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt + * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt + * @arg RCC_IT_CSS: Clock Security System interrupt + * + * For @b other_STM32_devices, this parameter can be any combination of the + * following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: PLL ready interrupt + * + * @arg RCC_IT_CSS: Clock Security System interrupt + * @retval None + */ +void RCC_ClearITPendingBit(uint8_t RCC_IT) +{ + /* Check the parameters */ + assert_param(IS_RCC_CLEAR_IT(RCC_IT)); + + /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt + pending bits */ + *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/STM32F10x_FWLIB/src/stm32f10x_rtc.c b/STM32F10x_FWLIB/src/stm32f10x_rtc.c new file mode 100644 index 0000000..c1bc9e1 --- /dev/null +++ b/STM32F10x_FWLIB/src/stm32f10x_rtc.c @@ -0,0 +1,350 @@ +/** + ****************************************************************************** + * @file stm32f10x_rtc.c + * @author MCD Application Team + * @version V3.6.2 + * @date 17-September-2021 + * @brief This file provides all the RTC firmware functions. + ****************************************************************************** + * @attention + * + * Copyright (c) 2012 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_rtc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup RTC + * @brief RTC driver modules + * @{ + */ + +/** @defgroup RTC_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + +/** @defgroup RTC_Private_Defines + * @{ + */ +#define RTC_LSB_MASK ((uint32_t)0x0000FFFF) /*!< RTC LSB Mask */ +#define PRLH_MSB_MASK ((uint32_t)0x000F0000) /*!< RTC Prescaler MSB Mask */ + +/** + * @} + */ + +/** @defgroup RTC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup RTC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup RTC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup RTC_Private_Functions + * @{ + */ + +/** + * @brief Enables or disables the specified RTC interrupts. + * @param RTC_IT: specifies the RTC interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg RTC_IT_OW: Overflow interrupt + * @arg RTC_IT_ALR: Alarm interrupt + * @arg RTC_IT_SEC: Second interrupt + * @param NewState: new state of the specified RTC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RTC_IT(RTC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RTC->CRH |= RTC_IT; + } + else + { + RTC->CRH &= (uint16_t)~RTC_IT; + } +} + +/** + * @brief Enters the RTC configuration mode. + * @param None + * @retval None + */ +void RTC_EnterConfigMode(void) +{ + /* Set the CNF flag to enter in the Configuration Mode */ + RTC->CRL |= RTC_CRL_CNF; +} + +/** + * @brief Exits from the RTC configuration mode. + * @param None + * @retval None + */ +void RTC_ExitConfigMode(void) +{ + /* Reset the CNF flag to exit from the Configuration Mode */ + RTC->CRL &= (uint16_t)~((uint16_t)RTC_CRL_CNF); +} + +/** + * @brief Gets the RTC counter value. + * @param None + * @retval RTC counter value. + */ +uint32_t RTC_GetCounter(void) +{ + uint16_t high1 = 0, high2 = 0, low = 0; + + high1 = RTC->CNTH; + low = RTC->CNTL; + high2 = RTC->CNTH; + + if (high1 != high2) + { /* In this case the counter roll over during reading of CNTL and CNTH registers, + read again CNTL register then return the counter value */ + return (((uint32_t) high2 << 16 ) | RTC->CNTL); + } + else + { /* No counter roll over during reading of CNTL and CNTH registers, counter + value is equal to first value of CNTL and CNTH */ + return (((uint32_t) high1 << 16 ) | low); + } +} + +/** + * @brief Sets the RTC counter value. + * @param CounterValue: RTC counter new value. + * @retval None + */ +void RTC_SetCounter(uint32_t CounterValue) +{ + RTC_EnterConfigMode(); + /* Set RTC COUNTER MSB word */ + RTC->CNTH = CounterValue >> 16; + /* Set RTC COUNTER LSB word */ + RTC->CNTL = (CounterValue & RTC_LSB_MASK); + RTC_ExitConfigMode(); +} + +/** + * @brief Sets the RTC prescaler value. + * @param PrescalerValue: RTC prescaler new value. + * @retval None + */ +void RTC_SetPrescaler(uint32_t PrescalerValue) +{ + /* Check the parameters */ + assert_param(IS_RTC_PRESCALER(PrescalerValue)); + + RTC_EnterConfigMode(); + /* Set RTC PRESCALER MSB word */ + RTC->PRLH = (PrescalerValue & PRLH_MSB_MASK) >> 16; + /* Set RTC PRESCALER LSB word */ + RTC->PRLL = (PrescalerValue & RTC_LSB_MASK); + RTC_ExitConfigMode(); +} + +/** + * @brief Sets the RTC alarm value. + * @param AlarmValue: RTC alarm new value. + * @retval None + */ +void RTC_SetAlarm(uint32_t AlarmValue) +{ + RTC_EnterConfigMode(); + /* Set the ALARM MSB word */ + RTC->ALRH = AlarmValue >> 16; + /* Set the ALARM LSB word */ + RTC->ALRL = (AlarmValue & RTC_LSB_MASK); + RTC_ExitConfigMode(); +} + +/** + * @brief Gets the RTC divider value. + * @param None + * @retval RTC Divider value. + */ +uint32_t RTC_GetDivider(void) +{ + uint32_t tmp = 0x00; + tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16; + tmp |= RTC->DIVL; + return tmp; +} + +/** + * @brief Waits until last write operation on RTC registers has finished. + * @note This function must be called before any write to RTC registers. + * @param None + * @retval None + */ +void RTC_WaitForLastTask(void) +{ + /* Loop until RTOFF flag is set */ + while ((RTC->CRL & RTC_FLAG_RTOFF) == (uint16_t)RESET) + { + } +} + +/** + * @brief Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL) + * are synchronized with RTC APB clock. + * @note This function must be called before any read operation after an APB reset + * or an APB clock stop. + * @param None + * @retval None + */ +void RTC_WaitForSynchro(void) +{ + /* Clear RSF flag */ + RTC->CRL &= (uint16_t)~RTC_FLAG_RSF; + /* Loop until RSF flag is set */ + while ((RTC->CRL & RTC_FLAG_RSF) == (uint16_t)RESET) + { + } +} + +/** + * @brief Checks whether the specified RTC flag is set or not. + * @param RTC_FLAG: specifies the flag to check. + * This parameter can be one the following values: + * @arg RTC_FLAG_RTOFF: RTC Operation OFF flag + * @arg RTC_FLAG_RSF: Registers Synchronized flag + * @arg RTC_FLAG_OW: Overflow flag + * @arg RTC_FLAG_ALR: Alarm flag + * @arg RTC_FLAG_SEC: Second flag + * @retval The new state of RTC_FLAG (SET or RESET). + */ +FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_RTC_GET_FLAG(RTC_FLAG)); + + if ((RTC->CRL & RTC_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the RTC's pending flags. + * @param RTC_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg RTC_FLAG_RSF: Registers Synchronized flag. This flag is cleared only after + * an APB reset or an APB Clock stop. + * @arg RTC_FLAG_OW: Overflow flag + * @arg RTC_FLAG_ALR: Alarm flag + * @arg RTC_FLAG_SEC: Second flag + * @retval None + */ +void RTC_ClearFlag(uint16_t RTC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG)); + + /* Clear the corresponding RTC flag */ + RTC->CRL &= (uint16_t)~RTC_FLAG; +} + +/** + * @brief Checks whether the specified RTC interrupt has occurred or not. + * @param RTC_IT: specifies the RTC interrupts sources to check. + * This parameter can be one of the following values: + * @arg RTC_IT_OW: Overflow interrupt + * @arg RTC_IT_ALR: Alarm interrupt + * @arg RTC_IT_SEC: Second interrupt + * @retval The new state of the RTC_IT (SET or RESET). + */ +ITStatus RTC_GetITStatus(uint16_t RTC_IT) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_RTC_GET_IT(RTC_IT)); + + bitstatus = (ITStatus)(RTC->CRL & RTC_IT); + if (((RTC->CRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the RTC's interrupt pending bits. + * @param RTC_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg RTC_IT_OW: Overflow interrupt + * @arg RTC_IT_ALR: Alarm interrupt + * @arg RTC_IT_SEC: Second interrupt + * @retval None + */ +void RTC_ClearITPendingBit(uint16_t RTC_IT) +{ + /* Check the parameters */ + assert_param(IS_RTC_IT(RTC_IT)); + + /* Clear the corresponding RTC pending bit */ + RTC->CRL &= (uint16_t)~RTC_IT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/STM32F10x_FWLIB/src/stm32f10x_sdio.c b/STM32F10x_FWLIB/src/stm32f10x_sdio.c new file mode 100644 index 0000000..7c0bb9b --- /dev/null +++ b/STM32F10x_FWLIB/src/stm32f10x_sdio.c @@ -0,0 +1,796 @@ +/** + ****************************************************************************** + * @file stm32f10x_sdio.c + * @author MCD Application Team + * @version V3.6.2 + * @date 17-September-2021 + * @brief This file provides all the SDIO firmware functions. + ****************************************************************************** + * @attention + * + * Copyright (c) 2012 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_sdio.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup SDIO + * @brief SDIO driver modules + * @{ + */ + +/** @defgroup SDIO_Private_TypesDefinitions + * @{ + */ + +/* ------------ SDIO registers bit address in the alias region ----------- */ +#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) + +/* --- CLKCR Register ---*/ + +/* Alias word address of CLKEN bit */ +#define CLKCR_OFFSET (SDIO_OFFSET + 0x04) +#define CLKEN_BitNumber 0x08 +#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4)) + +/* --- CMD Register ---*/ + +/* Alias word address of SDIOSUSPEND bit */ +#define CMD_OFFSET (SDIO_OFFSET + 0x0C) +#define SDIOSUSPEND_BitNumber 0x0B +#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4)) + +/* Alias word address of ENCMDCOMPL bit */ +#define ENCMDCOMPL_BitNumber 0x0C +#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4)) + +/* Alias word address of NIEN bit */ +#define NIEN_BitNumber 0x0D +#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4)) + +/* Alias word address of ATACMD bit */ +#define ATACMD_BitNumber 0x0E +#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4)) + +/* --- DCTRL Register ---*/ + +/* Alias word address of DMAEN bit */ +#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C) +#define DMAEN_BitNumber 0x03 +#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4)) + +/* Alias word address of RWSTART bit */ +#define RWSTART_BitNumber 0x08 +#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4)) + +/* Alias word address of RWSTOP bit */ +#define RWSTOP_BitNumber 0x09 +#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4)) + +/* Alias word address of RWMOD bit */ +#define RWMOD_BitNumber 0x0A +#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4)) + +/* Alias word address of SDIOEN bit */ +#define SDIOEN_BitNumber 0x0B +#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4)) + +/* ---------------------- SDIO registers bit mask ------------------------ */ + +/* --- CLKCR Register ---*/ + +/* CLKCR register clear mask */ +#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100) + +/* --- PWRCTRL Register ---*/ + +/* SDIO PWRCTRL Mask */ +#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC) + +/* --- DCTRL Register ---*/ + +/* SDIO DCTRL Clear Mask */ +#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08) + +/* --- CMD Register ---*/ + +/* CMD Register clear mask */ +#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800) + +/* SDIO RESP Registers Address */ +#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14)) + +/** + * @} + */ + +/** @defgroup SDIO_Private_Defines + * @{ + */ + +/** + * @} + */ + +/** @defgroup SDIO_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup SDIO_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup SDIO_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup SDIO_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the SDIO peripheral registers to their default reset values. + * @param None + * @retval None + */ +void SDIO_DeInit(void) +{ + SDIO->POWER = 0x00000000; + SDIO->CLKCR = 0x00000000; + SDIO->ARG = 0x00000000; + SDIO->CMD = 0x00000000; + SDIO->DTIMER = 0x00000000; + SDIO->DLEN = 0x00000000; + SDIO->DCTRL = 0x00000000; + SDIO->ICR = 0x00C007FF; + SDIO->MASK = 0x00000000; +} + +/** + * @brief Initializes the SDIO peripheral according to the specified + * parameters in the SDIO_InitStruct. + * @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure + * that contains the configuration information for the SDIO peripheral. + * @retval None + */ +void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge)); + assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass)); + assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave)); + assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide)); + assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl)); + +/*---------------------------- SDIO CLKCR Configuration ------------------------*/ + /* Get the SDIO CLKCR value */ + tmpreg = SDIO->CLKCR; + + /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */ + tmpreg &= CLKCR_CLEAR_MASK; + + /* Set CLKDIV bits according to SDIO_ClockDiv value */ + /* Set PWRSAV bit according to SDIO_ClockPowerSave value */ + /* Set BYPASS bit according to SDIO_ClockBypass value */ + /* Set WIDBUS bits according to SDIO_BusWide value */ + /* Set NEGEDGE bits according to SDIO_ClockEdge value */ + /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */ + tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave | + SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide | + SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl); + + /* Write to SDIO CLKCR */ + SDIO->CLKCR = tmpreg; +} + +/** + * @brief Fills each SDIO_InitStruct member with its default value. + * @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which + * will be initialized. + * @retval None + */ +void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct) +{ + /* SDIO_InitStruct members default value */ + SDIO_InitStruct->SDIO_ClockDiv = 0x00; + SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising; + SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable; + SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; + SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b; + SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; +} + +/** + * @brief Enables or disables the SDIO Clock. + * @param NewState: new state of the SDIO Clock. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_ClockCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState; +} + +/** + * @brief Sets the power status of the controller. + * @param SDIO_PowerState: new state of the Power state. + * This parameter can be one of the following values: + * @arg SDIO_PowerState_OFF + * @arg SDIO_PowerState_ON + * @retval None + */ +void SDIO_SetPowerState(uint32_t SDIO_PowerState) +{ + /* Check the parameters */ + assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState)); + + SDIO->POWER = SDIO_PowerState; +} + +/** + * @brief Gets the power status of the controller. + * @param None + * @retval Power status of the controller. The returned value can + * be one of the following: + * - 0x00: Power OFF + * - 0x02: Power UP + * - 0x03: Power ON + */ +uint32_t SDIO_GetPowerState(void) +{ + return (SDIO->POWER & (~PWR_PWRCTRL_MASK)); +} + +/** + * @brief Enables or disables the SDIO interrupts. + * @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled. + * This parameter can be one or a combination of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide + * bus mode interrupt + * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_IT_TXACT: Data transmit in progress interrupt + * @arg SDIO_IT_RXACT: Data receive in progress interrupt + * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt + * @param NewState: new state of the specified SDIO interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SDIO_IT(SDIO_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the SDIO interrupts */ + SDIO->MASK |= SDIO_IT; + } + else + { + /* Disable the SDIO interrupts */ + SDIO->MASK &= ~SDIO_IT; + } +} + +/** + * @brief Enables or disables the SDIO DMA request. + * @param NewState: new state of the selected SDIO DMA request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_DMACmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState; +} + +/** + * @brief Initializes the SDIO Command according to the specified + * parameters in the SDIO_CmdInitStruct and send the command. + * @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef + * structure that contains the configuration information for the SDIO command. + * @retval None + */ +void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex)); + assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response)); + assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait)); + assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM)); + +/*---------------------------- SDIO ARG Configuration ------------------------*/ + /* Set the SDIO Argument value */ + SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument; + +/*---------------------------- SDIO CMD Configuration ------------------------*/ + /* Get the SDIO CMD value */ + tmpreg = SDIO->CMD; + /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */ + tmpreg &= CMD_CLEAR_MASK; + /* Set CMDINDEX bits according to SDIO_CmdIndex value */ + /* Set WAITRESP bits according to SDIO_Response value */ + /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */ + /* Set CPSMEN bits according to SDIO_CPSM value */ + tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response + | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM; + + /* Write to SDIO CMD */ + SDIO->CMD = tmpreg; +} + +/** + * @brief Fills each SDIO_CmdInitStruct member with its default value. + * @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef + * structure which will be initialized. + * @retval None + */ +void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct) +{ + /* SDIO_CmdInitStruct members default value */ + SDIO_CmdInitStruct->SDIO_Argument = 0x00; + SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00; + SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No; + SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable; +} + +/** + * @brief Returns command index of last command for which response received. + * @param None + * @retval Returns the command index of the last command response received. + */ +uint8_t SDIO_GetCommandResponse(void) +{ + return (uint8_t)(SDIO->RESPCMD); +} + +/** + * @brief Returns response received from the card for the last command. + * @param SDIO_RESP: Specifies the SDIO response register. + * This parameter can be one of the following values: + * @arg SDIO_RESP1: Response Register 1 + * @arg SDIO_RESP2: Response Register 2 + * @arg SDIO_RESP3: Response Register 3 + * @arg SDIO_RESP4: Response Register 4 + * @retval The Corresponding response register value. + */ +uint32_t SDIO_GetResponse(uint32_t SDIO_RESP) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_RESP(SDIO_RESP)); + + tmp = SDIO_RESP_ADDR + SDIO_RESP; + + return (*(__IO uint32_t *) tmp); +} + +/** + * @brief Initializes the SDIO data path according to the specified + * parameters in the SDIO_DataInitStruct. + * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure that + * contains the configuration information for the SDIO command. + * @retval None + */ +void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength)); + assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize)); + assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir)); + assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode)); + assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM)); + +/*---------------------------- SDIO DTIMER Configuration ---------------------*/ + /* Set the SDIO Data TimeOut value */ + SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut; + +/*---------------------------- SDIO DLEN Configuration -----------------------*/ + /* Set the SDIO DataLength value */ + SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength; + +/*---------------------------- SDIO DCTRL Configuration ----------------------*/ + /* Get the SDIO DCTRL value */ + tmpreg = SDIO->DCTRL; + /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */ + tmpreg &= DCTRL_CLEAR_MASK; + /* Set DEN bit according to SDIO_DPSM value */ + /* Set DTMODE bit according to SDIO_TransferMode value */ + /* Set DTDIR bit according to SDIO_TransferDir value */ + /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */ + tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir + | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM; + + /* Write to SDIO DCTRL */ + SDIO->DCTRL = tmpreg; +} + +/** + * @brief Fills each SDIO_DataInitStruct member with its default value. + * @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure which + * will be initialized. + * @retval None + */ +void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct) +{ + /* SDIO_DataInitStruct members default value */ + SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF; + SDIO_DataInitStruct->SDIO_DataLength = 0x00; + SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b; + SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard; + SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block; + SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable; +} + +/** + * @brief Returns number of remaining data bytes to be transferred. + * @param None + * @retval Number of remaining data bytes to be transferred + */ +uint32_t SDIO_GetDataCounter(void) +{ + return SDIO->DCOUNT; +} + +/** + * @brief Read one data word from Rx FIFO. + * @param None + * @retval Data received + */ +uint32_t SDIO_ReadData(void) +{ + return SDIO->FIFO; +} + +/** + * @brief Write one data word to Tx FIFO. + * @param Data: 32-bit data word to write. + * @retval None + */ +void SDIO_WriteData(uint32_t Data) +{ + SDIO->FIFO = Data; +} + +/** + * @brief Returns the number of words left to be written to or read from FIFO. + * @param None + * @retval Remaining number of words. + */ +uint32_t SDIO_GetFIFOCount(void) +{ + return SDIO->FIFOCNT; +} + +/** + * @brief Starts the SD I/O Read Wait operation. + * @param NewState: new state of the Start SDIO Read Wait operation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_StartSDIOReadWait(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState; +} + +/** + * @brief Stops the SD I/O Read Wait operation. + * @param NewState: new state of the Stop SDIO Read Wait operation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_StopSDIOReadWait(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState; +} + +/** + * @brief Sets one of the two options of inserting read wait interval. + * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode. + * This parameter can be: + * @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK + * @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2 + * @retval None + */ +void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode) +{ + /* Check the parameters */ + assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode)); + + *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode; +} + +/** + * @brief Enables or disables the SD I/O Mode Operation. + * @param NewState: new state of SDIO specific operation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_SetSDIOOperation(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the SD I/O Mode suspend command sending. + * @param NewState: new state of the SD I/O Mode suspend command. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_SendSDIOSuspendCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the command completion signal. + * @param NewState: new state of command completion signal. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_CommandCompletionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the CE-ATA interrupt. + * @param NewState: new state of CE-ATA interrupt. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_CEATAITCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1)); +} + +/** + * @brief Sends CE-ATA command (CMD61). + * @param NewState: new state of CE-ATA command. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_SendCEATACmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState; +} + +/** + * @brief Checks whether the specified SDIO flag is set or not. + * @param SDIO_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDIO_FLAG_CTIMEOUT: Command response timeout + * @arg SDIO_FLAG_DTIMEOUT: Data timeout + * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) + * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) + * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide + * bus mode. + * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDIO_FLAG_CMDACT: Command transfer in progress + * @arg SDIO_FLAG_TXACT: Data transmit in progress + * @arg SDIO_FLAG_RXACT: Data receive in progress + * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty + * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full + * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full + * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full + * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty + * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty + * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO + * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO + * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received + * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 + * @retval The new state of SDIO_FLAG (SET or RESET). + */ +FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_SDIO_FLAG(SDIO_FLAG)); + + if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the SDIO's pending flags. + * @param SDIO_FLAG: specifies the flag to clear. + * This parameter can be one or a combination of the following values: + * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDIO_FLAG_CTIMEOUT: Command response timeout + * @arg SDIO_FLAG_DTIMEOUT: Data timeout + * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) + * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) + * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide + * bus mode + * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received + * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 + * @retval None + */ +void SDIO_ClearFlag(uint32_t SDIO_FLAG) +{ + /* Check the parameters */ + assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG)); + + SDIO->ICR = SDIO_FLAG; +} + +/** + * @brief Checks whether the specified SDIO interrupt has occurred or not. + * @param SDIO_IT: specifies the SDIO interrupt source to check. + * This parameter can be one of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide + * bus mode interrupt + * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_IT_TXACT: Data transmit in progress interrupt + * @arg SDIO_IT_RXACT: Data receive in progress interrupt + * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt + * @retval The new state of SDIO_IT (SET or RESET). + */ +ITStatus SDIO_GetITStatus(uint32_t SDIO_IT) +{ + ITStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_SDIO_GET_IT(SDIO_IT)); + if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the SDIO's interrupt pending bits. + * @param SDIO_IT: specifies the interrupt pending bit to clear. + * This parameter can be one or a combination of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide + * bus mode interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 + * @retval None + */ +void SDIO_ClearITPendingBit(uint32_t SDIO_IT) +{ + /* Check the parameters */ + assert_param(IS_SDIO_CLEAR_IT(SDIO_IT)); + + SDIO->ICR = SDIO_IT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/STM32F10x_FWLIB/src/stm32f10x_spi.c b/STM32F10x_FWLIB/src/stm32f10x_spi.c new file mode 100644 index 0000000..b625ae4 --- /dev/null +++ b/STM32F10x_FWLIB/src/stm32f10x_spi.c @@ -0,0 +1,906 @@ +/** + ****************************************************************************** + * @file stm32f10x_spi.c + * @author MCD Application Team + * @version V3.6.2 + * @date 17-September-2021 + * @brief This file provides all the SPI firmware functions. + ****************************************************************************** + * @attention + * + * Copyright (c) 2012 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_spi.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup SPI + * @brief SPI driver modules + * @{ + */ + +/** @defgroup SPI_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + + +/** @defgroup SPI_Private_Defines + * @{ + */ + +/* SPI SPE mask */ +#define CR1_SPE_Set ((uint16_t)0x0040) +#define CR1_SPE_Reset ((uint16_t)0xFFBF) + +/* I2S I2SE mask */ +#define I2SCFGR_I2SE_Set ((uint16_t)0x0400) +#define I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF) + +/* SPI CRCNext mask */ +#define CR1_CRCNext_Set ((uint16_t)0x1000) + +/* SPI CRCEN mask */ +#define CR1_CRCEN_Set ((uint16_t)0x2000) +#define CR1_CRCEN_Reset ((uint16_t)0xDFFF) + +/* SPI SSOE mask */ +#define CR2_SSOE_Set ((uint16_t)0x0004) +#define CR2_SSOE_Reset ((uint16_t)0xFFFB) + +/* SPI registers Masks */ +#define CR1_CLEAR_Mask ((uint16_t)0x3040) +#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040) + +/* SPI or I2S mode selection masks */ +#define SPI_Mode_Select ((uint16_t)0xF7FF) +#define I2S_Mode_Select ((uint16_t)0x0800) + +/* I2S clock source selection masks */ +#define I2S2_CLOCK_SRC ((uint32_t)(0x00020000)) +#define I2S3_CLOCK_SRC ((uint32_t)(0x00040000)) +#define I2S_MUL_MASK ((uint32_t)(0x0000F000)) +#define I2S_DIV_MASK ((uint32_t)(0x000000F0)) + +/** + * @} + */ + +/** @defgroup SPI_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup SPI_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup SPI_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup SPI_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the SPIx peripheral registers to their default + * reset values (Affects also the I2Ss). + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @retval None + */ +void SPI_I2S_DeInit(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + if (SPIx == SPI1) + { + /* Enable SPI1 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); + /* Release SPI1 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); + } + else if (SPIx == SPI2) + { + /* Enable SPI2 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); + /* Release SPI2 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE); + } + else + { + if (SPIx == SPI3) + { + /* Enable SPI3 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE); + /* Release SPI3 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE); + } + } +} + +/** + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the SPI_InitStruct. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that + * contains the configuration information for the specified SPI peripheral. + * @retval None + */ +void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct) +{ + uint16_t tmpreg = 0; + + /* check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Check the SPI parameters */ + assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction)); + assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode)); + assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize)); + assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL)); + assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA)); + assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS)); + assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit)); + assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial)); + +/*---------------------------- SPIx CR1 Configuration ------------------------*/ + /* Get the SPIx CR1 value */ + tmpreg = SPIx->CR1; + /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */ + tmpreg &= CR1_CLEAR_Mask; + /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler + master/salve mode, CPOL and CPHA */ + /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */ + /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */ + /* Set LSBFirst bit according to SPI_FirstBit value */ + /* Set BR bits according to SPI_BaudRatePrescaler value */ + /* Set CPOL bit according to SPI_CPOL value */ + /* Set CPHA bit according to SPI_CPHA value */ + tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | + SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | + SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | + SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); + /* Write to SPIx CR1 */ + SPIx->CR1 = tmpreg; + + /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ + SPIx->I2SCFGR &= SPI_Mode_Select; + +/*---------------------------- SPIx CRCPOLY Configuration --------------------*/ + /* Write to SPIx CRCPOLY */ + SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial; +} + +/** + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the I2S_InitStruct. + * @param SPIx: where x can be 2 or 3 to select the SPI peripheral + * (configured in I2S mode). + * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that + * contains the configuration information for the specified SPI peripheral + * configured in I2S mode. + * @note + * The function calculates the optimal prescaler needed to obtain the most + * accurate audio frequency (depending on the I2S clock source, the PLL values + * and the product configuration). But in case the prescaler value is greater + * than 511, the default value (0x02) will be configured instead. * + * @retval None + */ +void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct) +{ + uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; + uint32_t tmp = 0; + RCC_ClocksTypeDef RCC_Clocks; + uint32_t sourceclock = 0; + + /* Check the I2S parameters */ + assert_param(IS_SPI_23_PERIPH(SPIx)); + assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode)); + assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard)); + assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat)); + assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput)); + assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq)); + assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); + +/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/ + /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ + SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask; + SPIx->I2SPR = 0x0002; + + /* Get the I2SCFGR register value */ + tmpreg = SPIx->I2SCFGR; + + /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/ + if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default) + { + i2sodd = (uint16_t)0; + i2sdiv = (uint16_t)2; + } + /* If the requested audio frequency is not the default, compute the prescaler */ + else + { + /* Check the frame length (For the Prescaler computing) */ + if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b) + { + /* Packet length is 16 bits */ + packetlength = 1; + } + else + { + /* Packet length is 32 bits */ + packetlength = 2; + } + + /* Get the I2S clock source mask depending on the peripheral number */ + if(((uint32_t)SPIx) == SPI2_BASE) + { + /* The mask is relative to I2S2 */ + tmp = I2S2_CLOCK_SRC; + } + else + { + /* The mask is relative to I2S3 */ + tmp = I2S3_CLOCK_SRC; + } + + /* Check the I2S clock source configuration depending on the Device: + Only Connectivity line devices have the PLL3 VCO clock */ +#ifdef STM32F10X_CL + if((RCC->CFGR2 & tmp) != 0) + { + /* Get the configuration bits of RCC PLL3 multiplier */ + tmp = (uint32_t)((RCC->CFGR2 & I2S_MUL_MASK) >> 12); + + /* Get the value of the PLL3 multiplier */ + if((tmp > 5) && (tmp < 15)) + { + /* Multiplier is between 8 and 14 (value 15 is forbidden) */ + tmp += 2; + } + else + { + if (tmp == 15) + { + /* Multiplier is 20 */ + tmp = 20; + } + } + /* Get the PREDIV2 value */ + sourceclock = (uint32_t)(((RCC->CFGR2 & I2S_DIV_MASK) >> 4) + 1); + + /* Calculate the Source Clock frequency based on PLL3 and PREDIV2 values */ + sourceclock = (uint32_t) ((HSE_Value / sourceclock) * tmp * 2); + } + else + { + /* I2S Clock source is System clock: Get System Clock frequency */ + RCC_GetClocksFreq(&RCC_Clocks); + + /* Get the source clock value: based on System Clock value */ + sourceclock = RCC_Clocks.SYSCLK_Frequency; + } +#else /* STM32F10X_HD */ + /* I2S Clock source is System clock: Get System Clock frequency */ + RCC_GetClocksFreq(&RCC_Clocks); + + /* Get the source clock value: based on System Clock value */ + sourceclock = RCC_Clocks.SYSCLK_Frequency; +#endif /* STM32F10X_CL */ + + /* Compute the Real divider depending on the MCLK output state with a floating point */ + if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable) + { + /* MCLK output is enabled */ + tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5); + } + else + { + /* MCLK output is disabled */ + tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5); + } + + /* Remove the floating point */ + tmp = tmp / 10; + + /* Check the parity of the divider */ + i2sodd = (uint16_t)(tmp & (uint16_t)0x0001); + + /* Compute the i2sdiv prescaler */ + i2sdiv = (uint16_t)((tmp - i2sodd) / 2); + + /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ + i2sodd = (uint16_t) (i2sodd << 8); + } + + /* Test if the divider is 1 or 0 or greater than 0xFF */ + if ((i2sdiv < 2) || (i2sdiv > 0xFF)) + { + /* Set the default values */ + i2sdiv = 2; + i2sodd = 0; + } + + /* Write to SPIx I2SPR register the computed value */ + SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput)); + + /* Configure the I2S with the SPI_InitStruct values */ + tmpreg |= (uint16_t)(I2S_Mode_Select | (uint16_t)(I2S_InitStruct->I2S_Mode | \ + (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \ + (uint16_t)I2S_InitStruct->I2S_CPOL)))); + + /* Write to SPIx I2SCFGR */ + SPIx->I2SCFGR = tmpreg; +} + +/** + * @brief Fills each SPI_InitStruct member with its default value. + * @param SPI_InitStruct : pointer to a SPI_InitTypeDef structure which will be initialized. + * @retval None + */ +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct) +{ +/*--------------- Reset SPI init structure parameters values -----------------*/ + /* Initialize the SPI_Direction member */ + SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; + /* initialize the SPI_Mode member */ + SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; + /* initialize the SPI_DataSize member */ + SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; + /* Initialize the SPI_CPOL member */ + SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; + /* Initialize the SPI_CPHA member */ + SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; + /* Initialize the SPI_NSS member */ + SPI_InitStruct->SPI_NSS = SPI_NSS_Hard; + /* Initialize the SPI_BaudRatePrescaler member */ + SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; + /* Initialize the SPI_FirstBit member */ + SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; + /* Initialize the SPI_CRCPolynomial member */ + SPI_InitStruct->SPI_CRCPolynomial = 7; +} + +/** + * @brief Fills each I2S_InitStruct member with its default value. + * @param I2S_InitStruct : pointer to a I2S_InitTypeDef structure which will be initialized. + * @retval None + */ +void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct) +{ +/*--------------- Reset I2S init structure parameters values -----------------*/ + /* Initialize the I2S_Mode member */ + I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx; + + /* Initialize the I2S_Standard member */ + I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips; + + /* Initialize the I2S_DataFormat member */ + I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b; + + /* Initialize the I2S_MCLKOutput member */ + I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable; + + /* Initialize the I2S_AudioFreq member */ + I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default; + + /* Initialize the I2S_CPOL member */ + I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low; +} + +/** + * @brief Enables or disables the specified SPI peripheral. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param NewState: new state of the SPIx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SPI peripheral */ + SPIx->CR1 |= CR1_SPE_Set; + } + else + { + /* Disable the selected SPI peripheral */ + SPIx->CR1 &= CR1_SPE_Reset; + } +} + +/** + * @brief Enables or disables the specified SPI peripheral (in I2S mode). + * @param SPIx: where x can be 2 or 3 to select the SPI peripheral. + * @param NewState: new state of the SPIx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_23_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SPI peripheral (in I2S mode) */ + SPIx->I2SCFGR |= I2SCFGR_I2SE_Set; + } + else + { + /* Disable the selected SPI peripheral (in I2S mode) */ + SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset; + } +} + +/** + * @brief Enables or disables the specified SPI/I2S interrupts. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * - 2 or 3 in I2S mode + * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to be enabled or disabled. + * This parameter can be one of the following values: + * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask + * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask + * @arg SPI_I2S_IT_ERR: Error interrupt mask + * @param NewState: new state of the specified SPI/I2S interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) +{ + uint16_t itpos = 0, itmask = 0 ; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT)); + + /* Get the SPI/I2S IT index */ + itpos = SPI_I2S_IT >> 4; + + /* Set the IT mask */ + itmask = (uint16_t)1 << (uint16_t)itpos; + + if (NewState != DISABLE) + { + /* Enable the selected SPI/I2S interrupt */ + SPIx->CR2 |= itmask; + } + else + { + /* Disable the selected SPI/I2S interrupt */ + SPIx->CR2 &= (uint16_t)~itmask; + } +} + +/** + * @brief Enables or disables the SPIx/I2Sx DMA interface. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * - 2 or 3 in I2S mode + * @param SPI_I2S_DMAReq: specifies the SPI/I2S DMA transfer request to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request + * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request + * @param NewState: new state of the selected SPI/I2S DMA transfer request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq)); + if (NewState != DISABLE) + { + /* Enable the selected SPI/I2S DMA requests */ + SPIx->CR2 |= SPI_I2S_DMAReq; + } + else + { + /* Disable the selected SPI/I2S DMA requests */ + SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq; + } +} + +/** + * @brief Transmits a Data through the SPIx/I2Sx peripheral. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * - 2 or 3 in I2S mode + * @param Data : Data to be transmitted. + * @retval None + */ +void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Write in the DR register the data to be sent */ + SPIx->DR = Data; +} + +/** + * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * - 2 or 3 in I2S mode + * @retval The value of the received data. + */ +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Return the data in the DR register */ + return SPIx->DR; +} + +/** + * @brief Configures internally by software the NSS pin for the selected SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state. + * This parameter can be one of the following values: + * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally + * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally + * @retval None + */ +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft)); + if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) + { + /* Set NSS pin internally by software */ + SPIx->CR1 |= SPI_NSSInternalSoft_Set; + } + else + { + /* Reset NSS pin internally by software */ + SPIx->CR1 &= SPI_NSSInternalSoft_Reset; + } +} + +/** + * @brief Enables or disables the SS output for the selected SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param NewState: new state of the SPIx SS output. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SPI SS output */ + SPIx->CR2 |= CR2_SSOE_Set; + } + else + { + /* Disable the selected SPI SS output */ + SPIx->CR2 &= CR2_SSOE_Reset; + } +} + +/** + * @brief Configures the data size for the selected SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_DataSize: specifies the SPI data size. + * This parameter can be one of the following values: + * @arg SPI_DataSize_16b: Set data frame format to 16bit + * @arg SPI_DataSize_8b: Set data frame format to 8bit + * @retval None + */ +void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_DATASIZE(SPI_DataSize)); + /* Clear DFF bit */ + SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b; + /* Set new DFF bit value */ + SPIx->CR1 |= SPI_DataSize; +} + +/** + * @brief Transmit the SPIx CRC value. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @retval None + */ +void SPI_TransmitCRC(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Enable the selected SPI CRC transmission */ + SPIx->CR1 |= CR1_CRCNext_Set; +} + +/** + * @brief Enables or disables the CRC value calculation of the transferred bytes. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param NewState: new state of the SPIx CRC value calculation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SPI CRC calculation */ + SPIx->CR1 |= CR1_CRCEN_Set; + } + else + { + /* Disable the selected SPI CRC calculation */ + SPIx->CR1 &= CR1_CRCEN_Reset; + } +} + +/** + * @brief Returns the transmit or the receive CRC register value for the specified SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_CRC: specifies the CRC register to be read. + * This parameter can be one of the following values: + * @arg SPI_CRC_Tx: Selects Tx CRC register + * @arg SPI_CRC_Rx: Selects Rx CRC register + * @retval The selected CRC register value.. + */ +uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC) +{ + uint16_t crcreg = 0; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_CRC(SPI_CRC)); + if (SPI_CRC != SPI_CRC_Rx) + { + /* Get the Tx CRC register */ + crcreg = SPIx->TXCRCR; + } + else + { + /* Get the Rx CRC register */ + crcreg = SPIx->RXCRCR; + } + /* Return the selected CRC register */ + return crcreg; +} + +/** + * @brief Returns the CRC Polynomial register value for the specified SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @retval The CRC Polynomial register value. + */ +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Return the CRC polynomial register */ + return SPIx->CRCPR; +} + +/** + * @brief Selects the data transfer direction in bi-directional mode for the specified SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_Direction: specifies the data transfer direction in bi-directional mode. + * This parameter can be one of the following values: + * @arg SPI_Direction_Tx: Selects Tx transmission direction + * @arg SPI_Direction_Rx: Selects Rx receive direction + * @retval None + */ +void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_DIRECTION(SPI_Direction)); + if (SPI_Direction == SPI_Direction_Tx) + { + /* Set the Tx only mode */ + SPIx->CR1 |= SPI_Direction_Tx; + } + else + { + /* Set the Rx only mode */ + SPIx->CR1 &= SPI_Direction_Rx; + } +} + +/** + * @brief Checks whether the specified SPI/I2S flag is set or not. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * - 2 or 3 in I2S mode + * @param SPI_I2S_FLAG: specifies the SPI/I2S flag to check. + * This parameter can be one of the following values: + * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag. + * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag. + * @arg SPI_I2S_FLAG_BSY: Busy flag. + * @arg SPI_I2S_FLAG_OVR: Overrun flag. + * @arg SPI_FLAG_MODF: Mode Fault flag. + * @arg SPI_FLAG_CRCERR: CRC Error flag. + * @arg I2S_FLAG_UDR: Underrun Error flag. + * @arg I2S_FLAG_CHSIDE: Channel Side flag. + * @retval The new state of SPI_I2S_FLAG (SET or RESET). + */ +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG)); + /* Check the status of the specified SPI/I2S flag */ + if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET) + { + /* SPI_I2S_FLAG is set */ + bitstatus = SET; + } + else + { + /* SPI_I2S_FLAG is reset */ + bitstatus = RESET; + } + /* Return the SPI_I2S_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the SPIx CRC Error (CRCERR) flag. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * @param SPI_I2S_FLAG: specifies the SPI flag to clear. + * This function clears only CRCERR flag. + * @note + * - OVR (OverRun error) flag is cleared by software sequence: a read + * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read + * operation to SPI_SR register (SPI_I2S_GetFlagStatus()). + * - UDR (UnderRun error) flag is cleared by a read operation to + * SPI_SR register (SPI_I2S_GetFlagStatus()). + * - MODF (Mode Fault) flag is cleared by software sequence: a read/write + * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a + * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI). + * @retval None + */ +void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG)); + + /* Clear the selected SPI CRC Error (CRCERR) flag */ + SPIx->SR = (uint16_t)~SPI_I2S_FLAG; +} + +/** + * @brief Checks whether the specified SPI/I2S interrupt has occurred or not. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * - 2 or 3 in I2S mode + * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to check. + * This parameter can be one of the following values: + * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt. + * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt. + * @arg SPI_I2S_IT_OVR: Overrun interrupt. + * @arg SPI_IT_MODF: Mode Fault interrupt. + * @arg SPI_IT_CRCERR: CRC Error interrupt. + * @arg I2S_IT_UDR: Underrun Error interrupt. + * @retval The new state of SPI_I2S_IT (SET or RESET). + */ +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itpos = 0, itmask = 0, enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT)); + + /* Get the SPI/I2S IT index */ + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + + /* Get the SPI/I2S IT mask */ + itmask = SPI_I2S_IT >> 4; + + /* Set the IT mask */ + itmask = 0x01 << itmask; + + /* Get the SPI_I2S_IT enable bit status */ + enablestatus = (SPIx->CR2 & itmask) ; + + /* Check the status of the specified SPI/I2S interrupt */ + if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus) + { + /* SPI_I2S_IT is set */ + bitstatus = SET; + } + else + { + /* SPI_I2S_IT is reset */ + bitstatus = RESET; + } + /* Return the SPI_I2S_IT status */ + return bitstatus; +} + +/** + * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear. + * This function clears only CRCERR interrupt pending bit. + * @note + * - OVR (OverRun Error) interrupt pending bit is cleared by software + * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) + * followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()). + * - UDR (UnderRun Error) interrupt pending bit is cleared by a read + * operation to SPI_SR register (SPI_I2S_GetITStatus()). + * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence: + * a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) + * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable + * the SPI). + * @retval None + */ +void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) +{ + uint16_t itpos = 0; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT)); + + /* Get the SPI IT index */ + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + + /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */ + SPIx->SR = (uint16_t)~itpos; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/STM32F10x_FWLIB/src/stm32f10x_tim.c b/STM32F10x_FWLIB/src/stm32f10x_tim.c new file mode 100644 index 0000000..cb2bc30 --- /dev/null +++ b/STM32F10x_FWLIB/src/stm32f10x_tim.c @@ -0,0 +1,2888 @@ +/** + ****************************************************************************** + * @file stm32f10x_tim.c + * @author MCD Application Team + * @version V3.6.2 + * @date 17-September-2021 + * @brief This file provides all the TIM firmware functions. + ****************************************************************************** + * @attention + * + * Copyright (c) 2012 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_tim.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup TIM + * @brief TIM driver modules + * @{ + */ + +/** @defgroup TIM_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_Defines + * @{ + */ + +/* ---------------------- TIM registers bit mask ------------------------ */ +#define SMCR_ETR_Mask ((uint16_t)0x00FF) +#define CCMR_Offset ((uint16_t)0x0018) +#define CCER_CCE_Set ((uint16_t)0x0001) +#define CCER_CCNE_Set ((uint16_t)0x0004) + +/** + * @} + */ + +/** @defgroup TIM_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_FunctionPrototypes + * @{ + */ + +static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +/** + * @} + */ + +/** @defgroup TIM_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the TIMx peripheral registers to their default reset values. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @retval None + */ +void TIM_DeInit(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + if (TIMx == TIM1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); + } + else if (TIMx == TIM2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); + } + else if (TIMx == TIM3) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); + } + else if (TIMx == TIM4) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); + } + else if (TIMx == TIM5) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE); + } + else if (TIMx == TIM6) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE); + } + else if (TIMx == TIM7) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE); + } + else if (TIMx == TIM8) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE); + } + else if (TIMx == TIM9) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE); + } + else if (TIMx == TIM10) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE); + } + else if (TIMx == TIM11) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE); + } + else if (TIMx == TIM12) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE); + } + else if (TIMx == TIM13) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE); + } + else if (TIMx == TIM14) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE); + } + else if (TIMx == TIM15) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE); + } + else if (TIMx == TIM16) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE); + } + else + { + if (TIMx == TIM17) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE); + } + } +} + +/** + * @brief Initializes the TIMx Time Base Unit peripheral according to + * the specified parameters in the TIM_TimeBaseInitStruct. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef + * structure that contains the configuration information for the + * specified TIM peripheral. + * @retval None + */ +void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) +{ + uint16_t tmpcr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode)); + assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision)); + + tmpcr1 = TIMx->CR1; + + if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM2) || (TIMx == TIM3)|| + (TIMx == TIM4) || (TIMx == TIM5)) + { + /* Select the Counter Mode */ + tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS))); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; + } + + if((TIMx != TIM6) && (TIMx != TIM7)) + { + /* Set the clock division */ + tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD)); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; + } + + TIMx->CR1 = tmpcr1; + + /* Set the Autoreload value */ + TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ; + + /* Set the Prescaler value */ + TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; + + if ((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)|| (TIMx == TIM16) || (TIMx == TIM17)) + { + /* Set the Repetition Counter value */ + TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; + } + + /* Generate an update event to reload the Prescaler and the Repetition counter + values immediately */ + TIMx->EGR = TIM_PSCReloadMode_Immediate; +} + +/** + * @brief Initializes the TIMx Channel1 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure + * that contains the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E); + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S)); + + /* Select the Output Compare Mode */ + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P)); + /* Set the Output Compare Polarity */ + tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; + + /* Set the Output State */ + tmpccer |= TIM_OCInitStruct->TIM_OutputState; + + if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)|| + (TIMx == TIM16)|| (TIMx == TIM17)) + { + assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP)); + /* Set the Output N Polarity */ + tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; + + /* Reset the Output N State */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NE)); + /* Set the Output N State */ + tmpccer |= TIM_OCInitStruct->TIM_OutputNState; + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1N)); + + /* Set the Output Idle state */ + tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; + /* Set the Output N Idle state */ + tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel2 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select + * the TIM peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure + * that contains the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E)); + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)); + + /* Select the Output Compare Mode */ + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); + + /* Set the Output State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); + + if((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NP)); + /* Set the Output N Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); + + /* Reset the Output N State */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NE)); + /* Set the Output N State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2N)); + + /* Set the Output Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); + /* Set the Output N Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel3 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure + * that contains the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E)); + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC3S)); + /* Select the Output Compare Mode */ + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); + + /* Set the Output State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); + + if((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NP)); + /* Set the Output N Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); + /* Reset the Output N State */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NE)); + + /* Set the Output N State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N)); + /* Set the Output Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); + /* Set the Output N Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel4 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure + * that contains the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + /* Disable the Channel 2: Reset the CC4E Bit */ + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E)); + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC4S)); + + /* Select the Output Compare Mode */ + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); + + /* Set the Output State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); + + if((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + /* Reset the Output Compare IDLE State */ + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS4)); + /* Set the Output Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Initializes the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure + * that contains the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel)); + assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler)); + assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter)); + + if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || + (TIMx == TIM4) ||(TIMx == TIM5)) + { + assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity)); + } + else + { + assert_param(IS_TIM_IC_POLARITY_LITE(TIM_ICInitStruct->TIM_ICPolarity)); + } + if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + /* TI1 Configuration */ + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) + { + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + /* TI2 Configuration */ + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) + { + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + /* TI3 Configuration */ + TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + /* TI4 Configuration */ + TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/** + * @brief Configures the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct to measure an external PWM signal. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure + * that contains the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + uint16_t icoppositepolarity = TIM_ICPolarity_Rising; + uint16_t icoppositeselection = TIM_ICSelection_DirectTI; + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + /* Select the Opposite Input Polarity */ + if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) + { + icoppositepolarity = TIM_ICPolarity_Falling; + } + else + { + icoppositepolarity = TIM_ICPolarity_Rising; + } + /* Select the Opposite Input */ + if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) + { + icoppositeselection = TIM_ICSelection_IndirectTI; + } + else + { + icoppositeselection = TIM_ICSelection_DirectTI; + } + if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + /* TI1 Configuration */ + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + /* TI2 Configuration */ + TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + /* TI2 Configuration */ + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + /* TI1 Configuration */ + TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/** + * @brief Configures the: Break feature, dead time, Lock level, the OSSI, + * the OSSR State and the AOE(automatic output enable). + * @param TIMx: where x can be 1 or 8 to select the TIM + * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that + * contains the BDTR Register configuration information for the TIM peripheral. + * @retval None + */ +void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState)); + assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState)); + assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel)); + assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break)); + assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity)); + assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput)); + /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | + TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | + TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | + TIM_BDTRInitStruct->TIM_AutomaticOutput; +} + +/** + * @brief Fills each TIM_TimeBaseInitStruct member with its default value. + * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef + * structure which will be initialized. + * @retval None + */ +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) +{ + /* Set the default configuration */ + TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF; + TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; + TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; + TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; +} + +/** + * @brief Fills each TIM_OCInitStruct member with its default value. + * @param TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will + * be initialized. + * @retval None + */ +void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + /* Set the default configuration */ + TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; + TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; + TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; + TIM_OCInitStruct->TIM_Pulse = 0x0000; + TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; + TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; +} + +/** + * @brief Fills each TIM_ICInitStruct member with its default value. + * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will + * be initialized. + * @retval None + */ +void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + /* Set the default configuration */ + TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; + TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; + TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; + TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; + TIM_ICInitStruct->TIM_ICFilter = 0x00; +} + +/** + * @brief Fills each TIM_BDTRInitStruct member with its default value. + * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which + * will be initialized. + * @retval None + */ +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct) +{ + /* Set the default configuration */ + TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; + TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; + TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; + TIM_BDTRInitStruct->TIM_DeadTime = 0x00; + TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; + TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; + TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; +} + +/** + * @brief Enables or disables the specified TIM peripheral. + * @param TIMx: where x can be 1 to 17 to select the TIMx peripheral. + * @param NewState: new state of the TIMx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the TIM Counter */ + TIMx->CR1 |= TIM_CR1_CEN; + } + else + { + /* Disable the TIM Counter */ + TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN)); + } +} + +/** + * @brief Enables or disables the TIM peripheral Main Outputs. + * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral. + * @param NewState: new state of the TIM peripheral Main Outputs. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the TIM Main Output */ + TIMx->BDTR |= TIM_BDTR_MOE; + } + else + { + /* Disable the TIM Main Output */ + TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_BDTR_MOE)); + } +} + +/** + * @brief Enables or disables the specified TIM interrupts. + * @param TIMx: where x can be 1 to 17 to select the TIMx peripheral. + * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg TIM_IT_Update: TIM update Interrupt source + * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source + * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source + * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source + * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source + * @arg TIM_IT_COM: TIM Commutation Interrupt source + * @arg TIM_IT_Trigger: TIM Trigger Interrupt source + * @arg TIM_IT_Break: TIM Break Interrupt source + * @note + * - TIM6 and TIM7 can only generate an update interrupt. + * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1, + * TIM_IT_CC2 or TIM_IT_Trigger. + * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. + * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. + * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. + * @param NewState: new state of the TIM interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_IT(TIM_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Interrupt sources */ + TIMx->DIER |= TIM_IT; + } + else + { + /* Disable the Interrupt sources */ + TIMx->DIER &= (uint16_t)~TIM_IT; + } +} + +/** + * @brief Configures the TIMx event to be generate by software. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param TIM_EventSource: specifies the event source. + * This parameter can be one or more of the following values: + * @arg TIM_EventSource_Update: Timer update Event source + * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source + * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source + * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source + * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source + * @arg TIM_EventSource_COM: Timer COM event source + * @arg TIM_EventSource_Trigger: Timer Trigger Event source + * @arg TIM_EventSource_Break: Timer Break event source + * @note + * - TIM6 and TIM7 can only generate an update event. + * - TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8. + * @retval None + */ +void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource)); + + /* Set the event sources */ + TIMx->EGR = TIM_EventSource; +} + +/** + * @brief Configures the TIMx's DMA interface. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select + * the TIM peripheral. + * @param TIM_DMABase: DMA Base address. + * This parameter can be one of the following values: + * @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR, + * TIM_DMABase_DIER, TIM1_DMABase_SR, TIM_DMABase_EGR, + * TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER, + * TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR, + * TIM_DMABase_RCR, TIM_DMABase_CCR1, TIM_DMABase_CCR2, + * TIM_DMABase_CCR3, TIM_DMABase_CCR4, TIM_DMABase_BDTR, + * TIM_DMABase_DCR. + * @param TIM_DMABurstLength: DMA Burst length. + * This parameter can be one value between: + * TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. + * @retval None + */ +void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); + assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength)); + /* Set the DMA Base and the DMA Burst Length */ + TIMx->DCR = TIM_DMABase | TIM_DMABurstLength; +} + +/** + * @brief Enables or disables the TIMx's DMA Requests. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 15, 16 or 17 + * to select the TIM peripheral. + * @param TIM_DMASource: specifies the DMA Request sources. + * This parameter can be any combination of the following values: + * @arg TIM_DMA_Update: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_Trigger: TIM Trigger DMA source + * @param NewState: new state of the DMA Request sources. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST9_PERIPH(TIMx)); + assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA sources */ + TIMx->DIER |= TIM_DMASource; + } + else + { + /* Disable the DMA sources */ + TIMx->DIER &= (uint16_t)~TIM_DMASource; + } +} + +/** + * @brief Configures the TIMx internal Clock + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 + * to select the TIM peripheral. + * @retval None + */ +void TIM_InternalClockConfig(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + /* Disable slave mode to clock the prescaler directly with the internal clock */ + TIMx->SMCR &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); +} + +/** + * @brief Configures the TIMx Internal Trigger as External Clock + * @param TIMx: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_ITRSource: Trigger source. + * This parameter can be one of the following values: + * @param TIM_TS_ITR0: Internal Trigger 0 + * @param TIM_TS_ITR1: Internal Trigger 1 + * @param TIM_TS_ITR2: Internal Trigger 2 + * @param TIM_TS_ITR3: Internal Trigger 3 + * @retval None + */ +void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource)); + /* Select the Internal Trigger */ + TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); + /* Select the External clock mode1 */ + TIMx->SMCR |= TIM_SlaveMode_External1; +} + +/** + * @brief Configures the TIMx Trigger as External Clock + * @param TIMx: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_TIxExternalCLKSource: Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector + * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1 + * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2 + * @param TIM_ICPolarity: specifies the TIx Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param ICFilter : specifies the filter value. + * This parameter must be a value between 0x0 and 0xF. + * @retval None + */ +void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_TIXCLK_SOURCE(TIM_TIxExternalCLKSource)); + assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity)); + assert_param(IS_TIM_IC_FILTER(ICFilter)); + /* Configure the Timer Input Clock Source */ + if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) + { + TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + else + { + TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + /* Select the Trigger source */ + TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); + /* Select the External clock mode1 */ + TIMx->SMCR |= TIM_SlaveMode_External1; +} + +/** + * @brief Configures the External clock Mode1 + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. + * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. + * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. + * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity: The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. + * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. + * @param ExtTRGFilter: External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); + /* Configure the ETR Clock source */ + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + /* Reset the SMS Bits */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); + /* Select the External clock mode1 */ + tmpsmcr |= TIM_SlaveMode_External1; + /* Select the Trigger selection : ETRF */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS)); + tmpsmcr |= TIM_TS_ETRF; + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Configures the External clock Mode2 + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. + * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. + * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. + * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity: The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. + * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. + * @param ExtTRGFilter: External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); + /* Configure the ETR Clock source */ + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + /* Enable the External clock mode2 */ + TIMx->SMCR |= TIM_SMCR_ECE; +} + +/** + * @brief Configures the TIMx External Trigger (ETR). + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. + * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. + * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. + * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity: The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. + * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. + * @param ExtTRGFilter: External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); + tmpsmcr = TIMx->SMCR; + /* Reset the ETR Bits */ + tmpsmcr &= SMCR_ETR_Mask; + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Configures the TIMx Prescaler. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param Prescaler: specifies the Prescaler Register value + * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode + * This parameter can be one of the following values: + * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event. + * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediately. + * @retval None + */ +void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode)); + /* Set the Prescaler value */ + TIMx->PSC = Prescaler; + /* Set or reset the UG Bit */ + TIMx->EGR = TIM_PSCReloadMode; +} + +/** + * @brief Specifies the TIMx Counter Mode to be used. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_CounterMode: specifies the Counter Mode to be used + * This parameter can be one of the following values: + * @arg TIM_CounterMode_Up: TIM Up Counting Mode + * @arg TIM_CounterMode_Down: TIM Down Counting Mode + * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1 + * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2 + * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3 + * @retval None + */ +void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode) +{ + uint16_t tmpcr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode)); + tmpcr1 = TIMx->CR1; + /* Reset the CMS and DIR Bits */ + tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS))); + /* Set the Counter Mode */ + tmpcr1 |= TIM_CounterMode; + /* Write to TIMx CR1 register */ + TIMx->CR1 = tmpcr1; +} + +/** + * @brief Selects the Input Trigger source + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_InputTriggerSource: The Input Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal Trigger 0 + * @arg TIM_TS_ITR1: Internal Trigger 1 + * @arg TIM_TS_ITR2: Internal Trigger 2 + * @arg TIM_TS_ITR3: Internal Trigger 3 + * @arg TIM_TS_TI1F_ED: TI1 Edge Detector + * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 + * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 + * @arg TIM_TS_ETRF: External Trigger input + * @retval None + */ +void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) +{ + uint16_t tmpsmcr = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource)); + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + /* Reset the TS Bits */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS)); + /* Set the Input Trigger source */ + tmpsmcr |= TIM_InputTriggerSource; + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Configures the TIMx Encoder Interface. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_EncoderMode: specifies the TIMx Encoder Mode. + * This parameter can be one of the following values: + * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level. + * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level. + * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending + * on the level of the other input. + * @param TIM_IC1Polarity: specifies the IC1 Polarity + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Falling: IC Falling edge. + * @arg TIM_ICPolarity_Rising: IC Rising edge. + * @param TIM_IC2Polarity: specifies the IC2 Polarity + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Falling: IC Falling edge. + * @arg TIM_ICPolarity_Rising: IC Rising edge. + * @retval None + */ +void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) +{ + uint16_t tmpsmcr = 0; + uint16_t tmpccmr1 = 0; + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST5_PERIPH(TIMx)); + assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode)); + assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity)); + assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity)); + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = TIMx->CCMR1; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Set the encoder Mode */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); + tmpsmcr |= TIM_EncoderMode; + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S))); + tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0; + + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCER_CC1P)) & ((uint16_t)~((uint16_t)TIM_CCER_CC2P))); + tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmr1; + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Forces the TIMx output 1 waveform to active or inactive level. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC1REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF. + * @retval None + */ +void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC1M Bits */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M); + /* Configure The Forced output Mode */ + tmpccmr1 |= TIM_ForcedAction; + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Forces the TIMx output 2 waveform to active or inactive level. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC2REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF. + * @retval None + */ +void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC2M Bits */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M); + /* Configure The Forced output Mode */ + tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Forces the TIMx output 3 waveform to active or inactive level. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC3REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF. + * @retval None + */ +void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC1M Bits */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M); + /* Configure The Forced output Mode */ + tmpccmr2 |= TIM_ForcedAction; + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Forces the TIMx output 4 waveform to active or inactive level. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC4REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF. + * @retval None + */ +void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC2M Bits */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M); + /* Configure The Forced output Mode */ + tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Enables or disables TIMx peripheral Preload register on ARR. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param NewState: new state of the TIMx peripheral Preload register + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the ARR Preload Bit */ + TIMx->CR1 |= TIM_CR1_ARPE; + } + else + { + /* Reset the ARR Preload Bit */ + TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE); + } +} + +/** + * @brief Selects the TIM peripheral Commutation event. + * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral + * @param NewState: new state of the Commutation event. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the COM Bit */ + TIMx->CR2 |= TIM_CR2_CCUS; + } + else + { + /* Reset the COM Bit */ + TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCUS); + } +} + +/** + * @brief Selects the TIMx peripheral Capture Compare DMA source. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select + * the TIM peripheral. + * @param NewState: new state of the Capture Compare DMA source + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the CCDS Bit */ + TIMx->CR2 |= TIM_CR2_CCDS; + } + else + { + /* Reset the CCDS Bit */ + TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS); + } +} + +/** + * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8 or 15 + * to select the TIMx peripheral + * @param NewState: new state of the Capture Compare Preload Control bit + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST5_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the CCPC Bit */ + TIMx->CR2 |= TIM_CR2_CCPC; + } + else + { + /* Reset the CCPC Bit */ + TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCPC); + } +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR1. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC1PE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr1 |= TIM_OCPreload; + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR2. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select + * the TIM peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC2PE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR3. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC3PE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr2 |= TIM_OCPreload; + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR4. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC4PE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Configures the TIMx Output Compare 1 Fast feature. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC1FE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr1 |= TIM_OCFast; + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Configures the TIMx Output Compare 2 Fast feature. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select + * the TIM peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC2FE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Configures the TIMx Output Compare 3 Fast feature. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + /* Get the TIMx CCMR2 register value */ + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC3FE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr2 |= TIM_OCFast; + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Configures the TIMx Output Compare 4 Fast feature. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + /* Get the TIMx CCMR2 register value */ + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC4FE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Clears or safeguards the OCREF1 signal on an external event + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC1CE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr1 |= TIM_OCClear; + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Clears or safeguards the OCREF2 signal on an external event + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC2CE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Clears or safeguards the OCREF3 signal on an external event + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC3CE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr2 |= TIM_OCClear; + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Clears or safeguards the OCREF4 signal on an external event + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC4CE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Configures the TIMx channel 1 polarity. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_OCPolarity: specifies the OC1 Polarity + * This parameter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + tmpccer = TIMx->CCER; + /* Set or Reset the CC1P Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P); + tmpccer |= TIM_OCPolarity; + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 1N polarity. + * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral. + * @param TIM_OCNPolarity: specifies the OC1N Polarity + * This parameter can be one of the following values: + * @arg TIM_OCNPolarity_High: Output Compare active high + * @arg TIM_OCNPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); + + tmpccer = TIMx->CCER; + /* Set or Reset the CC1NP Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1NP); + tmpccer |= TIM_OCNPolarity; + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx channel 2 polarity. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_OCPolarity: specifies the OC2 Polarity + * This parameter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + tmpccer = TIMx->CCER; + /* Set or Reset the CC2P Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 4); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 2N polarity. + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCNPolarity: specifies the OC2N Polarity + * This parameter can be one of the following values: + * @arg TIM_OCNPolarity_High: Output Compare active high + * @arg TIM_OCNPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); + + tmpccer = TIMx->CCER; + /* Set or Reset the CC2NP Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2NP); + tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx channel 3 polarity. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPolarity: specifies the OC3 Polarity + * This parameter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + tmpccer = TIMx->CCER; + /* Set or Reset the CC3P Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 8); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 3N polarity. + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCNPolarity: specifies the OC3N Polarity + * This parameter can be one of the following values: + * @arg TIM_OCNPolarity_High: Output Compare active high + * @arg TIM_OCNPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); + + tmpccer = TIMx->CCER; + /* Set or Reset the CC3NP Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3NP); + tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx channel 4 polarity. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPolarity: specifies the OC4 Polarity + * This parameter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + tmpccer = TIMx->CCER; + /* Set or Reset the CC4P Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 12); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel x. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_Channel: specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_Channel_1: TIM Channel 1 + * @arg TIM_Channel_2: TIM Channel 2 + * @arg TIM_Channel_3: TIM Channel 3 + * @arg TIM_Channel_4: TIM Channel 4 + * @param TIM_CCx: specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. + * @retval None + */ +void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) +{ + uint16_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_CHANNEL(TIM_Channel)); + assert_param(IS_TIM_CCX(TIM_CCx)); + + tmp = CCER_CCE_Set << TIM_Channel; + + /* Reset the CCxE Bit */ + TIMx->CCER &= (uint16_t)~ tmp; + + /* Set or reset the CCxE Bit */ + TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel xN. + * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral. + * @param TIM_Channel: specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_Channel_1: TIM Channel 1 + * @arg TIM_Channel_2: TIM Channel 2 + * @arg TIM_Channel_3: TIM Channel 3 + * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state. + * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. + * @retval None + */ +void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) +{ + uint16_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel)); + assert_param(IS_TIM_CCXN(TIM_CCxN)); + + tmp = CCER_CCNE_Set << TIM_Channel; + + /* Reset the CCxNE Bit */ + TIMx->CCER &= (uint16_t) ~tmp; + + /* Set or reset the CCxNE Bit */ + TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); +} + +/** + * @brief Selects the TIM Output Compare Mode. + * @note This function disables the selected channel before changing the Output + * Compare Mode. + * User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_Channel: specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_Channel_1: TIM Channel 1 + * @arg TIM_Channel_2: TIM Channel 2 + * @arg TIM_Channel_3: TIM Channel 3 + * @arg TIM_Channel_4: TIM Channel 4 + * @param TIM_OCMode: specifies the TIM Output Compare Mode. + * This parameter can be one of the following values: + * @arg TIM_OCMode_Timing + * @arg TIM_OCMode_Active + * @arg TIM_OCMode_Toggle + * @arg TIM_OCMode_PWM1 + * @arg TIM_OCMode_PWM2 + * @arg TIM_ForcedAction_Active + * @arg TIM_ForcedAction_InActive + * @retval None + */ +void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) +{ + uint32_t tmp = 0; + uint16_t tmp1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_CHANNEL(TIM_Channel)); + assert_param(IS_TIM_OCM(TIM_OCMode)); + + tmp = (uint32_t) TIMx; + tmp += CCMR_Offset; + + tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel; + + /* Disable the Channel: Reset the CCxE Bit */ + TIMx->CCER &= (uint16_t) ~tmp1; + + if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3)) + { + tmp += (TIM_Channel>>1); + + /* Reset the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M); + + /* Configure the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp |= TIM_OCMode; + } + else + { + tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1; + + /* Reset the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M); + + /* Configure the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8); + } +} + +/** + * @brief Enables or Disables the TIMx Update event. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param NewState: new state of the TIMx UDIS bit + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the Update Disable Bit */ + TIMx->CR1 |= TIM_CR1_UDIS; + } + else + { + /* Reset the Update Disable Bit */ + TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS); + } +} + +/** + * @brief Configures the TIMx Update Request Interrupt source. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param TIM_UpdateSource: specifies the Update source. + * This parameter can be one of the following values: + * @arg TIM_UpdateSource_Global: Source of update is the counter overflow/underflow + or the setting of UG bit, or an update generation + through the slave mode controller. + * @arg TIM_UpdateSource_Regular: Source of update is counter overflow/underflow. + * @retval None + */ +void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource)); + if (TIM_UpdateSource != TIM_UpdateSource_Global) + { + /* Set the URS Bit */ + TIMx->CR1 |= TIM_CR1_URS; + } + else + { + /* Reset the URS Bit */ + TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS); + } +} + +/** + * @brief Enables or disables the TIMx's Hall sensor interface. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param NewState: new state of the TIMx Hall sensor interface. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the TI1S Bit */ + TIMx->CR2 |= TIM_CR2_TI1S; + } + else + { + /* Reset the TI1S Bit */ + TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S); + } +} + +/** + * @brief Selects the TIMx's One Pulse Mode. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param TIM_OPMode: specifies the OPM Mode to be used. + * This parameter can be one of the following values: + * @arg TIM_OPMode_Single + * @arg TIM_OPMode_Repetitive + * @retval None + */ +void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_OPM_MODE(TIM_OPMode)); + /* Reset the OPM Bit */ + TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM); + /* Configure the OPM Mode */ + TIMx->CR1 |= TIM_OPMode; +} + +/** + * @brief Selects the TIMx Trigger Output Mode. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_TRGOSource: specifies the Trigger Output source. + * This paramter can be one of the following values: + * + * - For all TIMx + * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO). + * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO). + * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO). + * + * - For all TIMx except TIM6 and TIM7 + * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag + * is to be set, as soon as a capture or compare match occurs (TRGO). + * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO). + * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO). + * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO). + * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO). + * + * @retval None + */ +void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST7_PERIPH(TIMx)); + assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource)); + /* Reset the MMS Bits */ + TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS); + /* Select the TRGO source */ + TIMx->CR2 |= TIM_TRGOSource; +} + +/** + * @brief Selects the TIMx Slave Mode. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_SlaveMode: specifies the Timer Slave Mode. + * This parameter can be one of the following values: + * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes + * the counter and triggers an update of the registers. + * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high. + * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI. + * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter. + * @retval None + */ +void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode)); + /* Reset the SMS Bits */ + TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS); + /* Select the Slave Mode */ + TIMx->SMCR |= TIM_SlaveMode; +} + +/** + * @brief Sets or Resets the TIMx Master/Slave Mode. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode. + * This parameter can be one of the following values: + * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer + * and its slaves (through TRGO). + * @arg TIM_MasterSlaveMode_Disable: No action + * @retval None + */ +void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode)); + /* Reset the MSM Bit */ + TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM); + + /* Set or Reset the MSM Bit */ + TIMx->SMCR |= TIM_MasterSlaveMode; +} + +/** + * @brief Sets the TIMx Counter Register value + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param Counter: specifies the Counter register new value. + * @retval None + */ +void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + /* Set the Counter Register value */ + TIMx->CNT = Counter; +} + +/** + * @brief Sets the TIMx Autoreload Register value + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param Autoreload: specifies the Autoreload register new value. + * @retval None + */ +void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + /* Set the Autoreload Register value */ + TIMx->ARR = Autoreload; +} + +/** + * @brief Sets the TIMx Capture Compare1 Register value + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param Compare1: specifies the Capture Compare1 register new value. + * @retval None + */ +void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + /* Set the Capture Compare1 Register value */ + TIMx->CCR1 = Compare1; +} + +/** + * @brief Sets the TIMx Capture Compare2 Register value + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param Compare2: specifies the Capture Compare2 register new value. + * @retval None + */ +void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + /* Set the Capture Compare2 Register value */ + TIMx->CCR2 = Compare2; +} + +/** + * @brief Sets the TIMx Capture Compare3 Register value + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param Compare3: specifies the Capture Compare3 register new value. + * @retval None + */ +void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + /* Set the Capture Compare3 Register value */ + TIMx->CCR3 = Compare3; +} + +/** + * @brief Sets the TIMx Capture Compare4 Register value + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param Compare4: specifies the Capture Compare4 register new value. + * @retval None + */ +void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + /* Set the Capture Compare4 Register value */ + TIMx->CCR4 = Compare4; +} + +/** + * @brief Sets the TIMx Input Capture 1 prescaler. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + /* Reset the IC1PSC Bits */ + TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC); + /* Set the IC1PSC value */ + TIMx->CCMR1 |= TIM_ICPSC; +} + +/** + * @brief Sets the TIMx Input Capture 2 prescaler. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + /* Reset the IC2PSC Bits */ + TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC); + /* Set the IC2PSC value */ + TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8); +} + +/** + * @brief Sets the TIMx Input Capture 3 prescaler. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + /* Reset the IC3PSC Bits */ + TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC); + /* Set the IC3PSC value */ + TIMx->CCMR2 |= TIM_ICPSC; +} + +/** + * @brief Sets the TIMx Input Capture 4 prescaler. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + /* Reset the IC4PSC Bits */ + TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC); + /* Set the IC4PSC value */ + TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8); +} + +/** + * @brief Sets the TIMx Clock Division value. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select + * the TIM peripheral. + * @param TIM_CKD: specifies the clock division value. + * This parameter can be one of the following value: + * @arg TIM_CKD_DIV1: TDTS = Tck_tim + * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim + * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim + * @retval None + */ +void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_CKD_DIV(TIM_CKD)); + /* Reset the CKD Bits */ + TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD); + /* Set the CKD value */ + TIMx->CR1 |= TIM_CKD; +} + +/** + * @brief Gets the TIMx Input Capture 1 value. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @retval Capture Compare 1 Register value. + */ +uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + /* Get the Capture 1 Register value */ + return TIMx->CCR1; +} + +/** + * @brief Gets the TIMx Input Capture 2 value. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @retval Capture Compare 2 Register value. + */ +uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + /* Get the Capture 2 Register value */ + return TIMx->CCR2; +} + +/** + * @brief Gets the TIMx Input Capture 3 value. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @retval Capture Compare 3 Register value. + */ +uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + /* Get the Capture 3 Register value */ + return TIMx->CCR3; +} + +/** + * @brief Gets the TIMx Input Capture 4 value. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @retval Capture Compare 4 Register value. + */ +uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + /* Get the Capture 4 Register value */ + return TIMx->CCR4; +} + +/** + * @brief Gets the TIMx Counter value. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @retval Counter Register value. + */ +uint16_t TIM_GetCounter(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + /* Get the Counter Register value */ + return TIMx->CNT; +} + +/** + * @brief Gets the TIMx Prescaler value. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @retval Prescaler Register value. + */ +uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + /* Get the Prescaler Register value */ + return TIMx->PSC; +} + +/** + * @brief Checks whether the specified TIM flag is set or not. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param TIM_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg TIM_FLAG_Update: TIM update Flag + * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag + * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag + * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag + * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag + * @arg TIM_FLAG_COM: TIM Commutation Flag + * @arg TIM_FLAG_Trigger: TIM Trigger Flag + * @arg TIM_FLAG_Break: TIM Break Flag + * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag + * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag + * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag + * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag + * @note + * - TIM6 and TIM7 can have only one update flag. + * - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1, + * TIM_FLAG_CC2 or TIM_FLAG_Trigger. + * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1. + * - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15. + * - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. + * @retval The new state of TIM_FLAG (SET or RESET). + */ +FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_GET_FLAG(TIM_FLAG)); + + if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the TIMx's pending flags. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param TIM_FLAG: specifies the flag bit to clear. + * This parameter can be any combination of the following values: + * @arg TIM_FLAG_Update: TIM update Flag + * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag + * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag + * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag + * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag + * @arg TIM_FLAG_COM: TIM Commutation Flag + * @arg TIM_FLAG_Trigger: TIM Trigger Flag + * @arg TIM_FLAG_Break: TIM Break Flag + * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag + * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag + * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag + * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag + * @note + * - TIM6 and TIM7 can have only one update flag. + * - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1, + * TIM_FLAG_CC2 or TIM_FLAG_Trigger. + * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1. + * - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15. + * - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. + * @retval None + */ +void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG)); + + /* Clear the flags */ + TIMx->SR = (uint16_t)~TIM_FLAG; +} + +/** + * @brief Checks whether the TIM interrupt has occurred or not. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param TIM_IT: specifies the TIM interrupt source to check. + * This parameter can be one of the following values: + * @arg TIM_IT_Update: TIM update Interrupt source + * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source + * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source + * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source + * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source + * @arg TIM_IT_COM: TIM Commutation Interrupt source + * @arg TIM_IT_Trigger: TIM Trigger Interrupt source + * @arg TIM_IT_Break: TIM Break Interrupt source + * @note + * - TIM6 and TIM7 can generate only an update interrupt. + * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1, + * TIM_IT_CC2 or TIM_IT_Trigger. + * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. + * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. + * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. + * @retval The new state of the TIM_IT(SET or RESET). + */ +ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itstatus = 0x0, itenable = 0x0; + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_GET_IT(TIM_IT)); + + itstatus = TIMx->SR & TIM_IT; + + itenable = TIMx->DIER & TIM_IT; + if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the TIMx's interrupt pending bits. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param TIM_IT: specifies the pending bit to clear. + * This parameter can be any combination of the following values: + * @arg TIM_IT_Update: TIM1 update Interrupt source + * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source + * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source + * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source + * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source + * @arg TIM_IT_COM: TIM Commutation Interrupt source + * @arg TIM_IT_Trigger: TIM Trigger Interrupt source + * @arg TIM_IT_Break: TIM Break Interrupt source + * @note + * - TIM6 and TIM7 can generate only an update interrupt. + * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1, + * TIM_IT_CC2 or TIM_IT_Trigger. + * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. + * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. + * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. + * @retval None + */ +void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_IT(TIM_IT)); + /* Clear the IT pending Bit */ + TIMx->SR = (uint16_t)~TIM_IT; +} + +/** + * @brief Configure the TI1 as Input. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. + * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. + * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0; + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E); + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + /* Select the Input and set the filter */ + tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F))); + tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + + if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || + (TIMx == TIM4) ||(TIMx == TIM5)) + { + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E); + } + else + { + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E); + } + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI2 as Input. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. + * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. + * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E); + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 4); + /* Select the Input and set the filter */ + tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F))); + tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); + tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); + + if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || + (TIMx == TIM4) ||(TIMx == TIM5)) + { + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E); + } + else + { + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC2E); + } + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI3 as Input. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. + * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. + * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + /* Disable the Channel 3: Reset the CC3E Bit */ + TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E); + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 8); + /* Select the Input and set the filter */ + tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F))); + tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + + if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || + (TIMx == TIM4) ||(TIMx == TIM5)) + { + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E); + } + else + { + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC3E); + } + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI4 as Input. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. + * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. + * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E); + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 12); + /* Select the Input and set the filter */ + tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F))); + tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); + tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); + + if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || + (TIMx == TIM4) ||(TIMx == TIM5)) + { + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E); + } + else + { + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC4NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC4E); + } + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/STM32F10x_FWLIB/src/stm32f10x_usart.c b/STM32F10x_FWLIB/src/stm32f10x_usart.c new file mode 100644 index 0000000..da4407a --- /dev/null +++ b/STM32F10x_FWLIB/src/stm32f10x_usart.c @@ -0,0 +1,1057 @@ +/** + ****************************************************************************** + * @file stm32f10x_usart.c + * @author MCD Application Team + * @version V3.6.2 + * @date 17-September-2021 + * @brief This file provides all the USART firmware functions. + ****************************************************************************** + * @attention + * + * Copyright (c) 2012 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_usart.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup USART + * @brief USART driver modules + * @{ + */ + +/** @defgroup USART_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup USART_Private_Defines + * @{ + */ + +#define CR1_UE_Set ((uint16_t)0x2000) /*!< USART Enable Mask */ +#define CR1_UE_Reset ((uint16_t)0xDFFF) /*!< USART Disable Mask */ + +#define CR1_WAKE_Mask ((uint16_t)0xF7FF) /*!< USART WakeUp Method Mask */ + +#define CR1_RWU_Set ((uint16_t)0x0002) /*!< USART mute mode Enable Mask */ +#define CR1_RWU_Reset ((uint16_t)0xFFFD) /*!< USART mute mode Enable Mask */ +#define CR1_SBK_Set ((uint16_t)0x0001) /*!< USART Break Character send Mask */ +#define CR1_CLEAR_Mask ((uint16_t)0xE9F3) /*!< USART CR1 Mask */ +#define CR2_Address_Mask ((uint16_t)0xFFF0) /*!< USART address Mask */ + +#define CR2_LINEN_Set ((uint16_t)0x4000) /*!< USART LIN Enable Mask */ +#define CR2_LINEN_Reset ((uint16_t)0xBFFF) /*!< USART LIN Disable Mask */ + +#define CR2_LBDL_Mask ((uint16_t)0xFFDF) /*!< USART LIN Break detection Mask */ +#define CR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /*!< USART CR2 STOP Bits Mask */ +#define CR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /*!< USART CR2 Clock Mask */ + +#define CR3_SCEN_Set ((uint16_t)0x0020) /*!< USART SC Enable Mask */ +#define CR3_SCEN_Reset ((uint16_t)0xFFDF) /*!< USART SC Disable Mask */ + +#define CR3_NACK_Set ((uint16_t)0x0010) /*!< USART SC NACK Enable Mask */ +#define CR3_NACK_Reset ((uint16_t)0xFFEF) /*!< USART SC NACK Disable Mask */ + +#define CR3_HDSEL_Set ((uint16_t)0x0008) /*!< USART Half-Duplex Enable Mask */ +#define CR3_HDSEL_Reset ((uint16_t)0xFFF7) /*!< USART Half-Duplex Disable Mask */ + +#define CR3_IRLP_Mask ((uint16_t)0xFFFB) /*!< USART IrDA LowPower mode Mask */ +#define CR3_CLEAR_Mask ((uint16_t)0xFCFF) /*!< USART CR3 Mask */ + +#define CR3_IREN_Set ((uint16_t)0x0002) /*!< USART IrDA Enable Mask */ +#define CR3_IREN_Reset ((uint16_t)0xFFFD) /*!< USART IrDA Disable Mask */ +#define GTPR_LSB_Mask ((uint16_t)0x00FF) /*!< Guard Time Register LSB Mask */ +#define GTPR_MSB_Mask ((uint16_t)0xFF00) /*!< Guard Time Register MSB Mask */ +#define IT_Mask ((uint16_t)0x001F) /*!< USART Interrupt Mask */ + +/* USART OverSampling-8 Mask */ +#define CR1_OVER8_Set ((u16)0x8000) /* USART OVER8 mode Enable Mask */ +#define CR1_OVER8_Reset ((u16)0x7FFF) /* USART OVER8 mode Disable Mask */ + +/* USART One Bit Sampling Mask */ +#define CR3_ONEBITE_Set ((u16)0x0800) /* USART ONEBITE mode Enable Mask */ +#define CR3_ONEBITE_Reset ((u16)0xF7FF) /* USART ONEBITE mode Disable Mask */ + +/** + * @} + */ + +/** @defgroup USART_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup USART_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup USART_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup USART_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the USARTx peripheral registers to their default reset values. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @retval None + */ +void USART_DeInit(USART_TypeDef* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + if (USARTx == USART1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); + } + else if (USARTx == USART2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE); + } + else if (USARTx == USART3) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); + } + else if (USARTx == UART4) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE); + } + else + { + if (USARTx == UART5) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE); + } + } +} + +/** + * @brief Initializes the USARTx peripheral according to the specified + * parameters in the USART_InitStruct . + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure + * that contains the configuration information for the specified USART + * peripheral. + * @retval None + */ +void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct) +{ + uint32_t tmpreg = 0x00, apbclock = 0x00; + uint32_t integerdivider = 0x00; + uint32_t fractionaldivider = 0x00; + uint32_t usartxbase = 0; + RCC_ClocksTypeDef RCC_ClocksStatus; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); + assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength)); + assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits)); + assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity)); + assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode)); + assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl)); + /* The hardware flow control is available only for USART1, USART2 and USART3 */ + if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + usartxbase = (uint32_t)USARTx; + +/*---------------------------- USART CR2 Configuration -----------------------*/ + tmpreg = USARTx->CR2; + /* Clear STOP[13:12] bits */ + tmpreg &= CR2_STOP_CLEAR_Mask; + /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/ + /* Set STOP[13:12] bits according to USART_StopBits value */ + tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; + + /* Write to USART CR2 */ + USARTx->CR2 = (uint16_t)tmpreg; + +/*---------------------------- USART CR1 Configuration -----------------------*/ + tmpreg = USARTx->CR1; + /* Clear M, PCE, PS, TE and RE bits */ + tmpreg &= CR1_CLEAR_Mask; + /* Configure the USART Word Length, Parity and mode ----------------------- */ + /* Set the M bits according to USART_WordLength value */ + /* Set PCE and PS bits according to USART_Parity value */ + /* Set TE and RE bits according to USART_Mode value */ + tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | + USART_InitStruct->USART_Mode; + /* Write to USART CR1 */ + USARTx->CR1 = (uint16_t)tmpreg; + +/*---------------------------- USART CR3 Configuration -----------------------*/ + tmpreg = USARTx->CR3; + /* Clear CTSE and RTSE bits */ + tmpreg &= CR3_CLEAR_Mask; + /* Configure the USART HFC -------------------------------------------------*/ + /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */ + tmpreg |= USART_InitStruct->USART_HardwareFlowControl; + /* Write to USART CR3 */ + USARTx->CR3 = (uint16_t)tmpreg; + +/*---------------------------- USART BRR Configuration -----------------------*/ + /* Configure the USART Baud Rate -------------------------------------------*/ + RCC_GetClocksFreq(&RCC_ClocksStatus); + if (usartxbase == USART1_BASE) + { + apbclock = RCC_ClocksStatus.PCLK2_Frequency; + } + else + { + apbclock = RCC_ClocksStatus.PCLK1_Frequency; + } + + /* Determine the integer part */ + if ((USARTx->CR1 & CR1_OVER8_Set) != 0) + { + /* Integer part computing in case Oversampling mode is 8 Samples */ + integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate))); + } + else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */ + { + /* Integer part computing in case Oversampling mode is 16 Samples */ + integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); + } + tmpreg = (integerdivider / 100) << 4; + + /* Determine the fractional part */ + fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); + + /* Implement the fractional part in the register */ + if ((USARTx->CR1 & CR1_OVER8_Set) != 0) + { + tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07); + } + else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */ + { + tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); + } + + /* Write to USART BRR */ + USARTx->BRR = (uint16_t)tmpreg; +} + +/** + * @brief Fills each USART_InitStruct member with its default value. + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure + * which will be initialized. + * @retval None + */ +void USART_StructInit(USART_InitTypeDef* USART_InitStruct) +{ + /* USART_InitStruct members default value */ + USART_InitStruct->USART_BaudRate = 9600; + USART_InitStruct->USART_WordLength = USART_WordLength_8b; + USART_InitStruct->USART_StopBits = USART_StopBits_1; + USART_InitStruct->USART_Parity = USART_Parity_No ; + USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; +} + +/** + * @brief Initializes the USARTx peripheral Clock according to the + * specified parameters in the USART_ClockInitStruct . + * @param USARTx: where x can be 1, 2, 3 to select the USART peripheral. + * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef + * structure that contains the configuration information for the specified + * USART peripheral. + * @note The Smart Card and Synchronous modes are not available for UART4 and UART5. + * @retval None + */ +void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct) +{ + uint32_t tmpreg = 0x00; + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock)); + assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL)); + assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA)); + assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit)); + +/*---------------------------- USART CR2 Configuration -----------------------*/ + tmpreg = USARTx->CR2; + /* Clear CLKEN, CPOL, CPHA and LBCL bits */ + tmpreg &= CR2_CLOCK_CLEAR_Mask; + /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/ + /* Set CLKEN bit according to USART_Clock value */ + /* Set CPOL bit according to USART_CPOL value */ + /* Set CPHA bit according to USART_CPHA value */ + /* Set LBCL bit according to USART_LastBit value */ + tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | + USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit; + /* Write to USART CR2 */ + USARTx->CR2 = (uint16_t)tmpreg; +} + +/** + * @brief Fills each USART_ClockInitStruct member with its default value. + * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef + * structure which will be initialized. + * @retval None + */ +void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct) +{ + /* USART_ClockInitStruct members default value */ + USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; + USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; + USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; + USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; +} + +/** + * @brief Enables or disables the specified USART peripheral. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param NewState: new state of the USARTx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected USART by setting the UE bit in the CR1 register */ + USARTx->CR1 |= CR1_UE_Set; + } + else + { + /* Disable the selected USART by clearing the UE bit in the CR1 register */ + USARTx->CR1 &= CR1_UE_Reset; + } +} + +/** + * @brief Enables or disables the specified USART interrupts. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) + * @arg USART_IT_LBD: LIN Break detection interrupt + * @arg USART_IT_TXE: Transmit Data Register empty interrupt + * @arg USART_IT_TC: Transmission complete interrupt + * @arg USART_IT_RXNE: Receive Data register not empty interrupt + * @arg USART_IT_IDLE: Idle line detection interrupt + * @arg USART_IT_PE: Parity Error interrupt + * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) + * @param NewState: new state of the specified USARTx interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState) +{ + uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; + uint32_t usartxbase = 0x00; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CONFIG_IT(USART_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + /* The CTS interrupt is not available for UART4 and UART5 */ + if (USART_IT == USART_IT_CTS) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + usartxbase = (uint32_t)USARTx; + + /* Get the USART register index */ + usartreg = (((uint8_t)USART_IT) >> 0x05); + + /* Get the interrupt position */ + itpos = USART_IT & IT_Mask; + itmask = (((uint32_t)0x01) << itpos); + + if (usartreg == 0x01) /* The IT is in CR1 register */ + { + usartxbase += 0x0C; + } + else if (usartreg == 0x02) /* The IT is in CR2 register */ + { + usartxbase += 0x10; + } + else /* The IT is in CR3 register */ + { + usartxbase += 0x14; + } + if (NewState != DISABLE) + { + *(__IO uint32_t*)usartxbase |= itmask; + } + else + { + *(__IO uint32_t*)usartxbase &= ~itmask; + } +} + +/** + * @brief Enables or disables the USART抯 DMA interface. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_DMAReq: specifies the DMA request. + * This parameter can be any combination of the following values: + * @arg USART_DMAReq_Tx: USART DMA transmit request + * @arg USART_DMAReq_Rx: USART DMA receive request + * @param NewState: new state of the DMA Request sources. + * This parameter can be: ENABLE or DISABLE. + * @note The DMA mode is not available for UART5 except in the STM32 + * High density value line devices(STM32F10X_HD_VL). + * @retval None + */ +void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_DMAREQ(USART_DMAReq)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the DMA transfer for selected requests by setting the DMAT and/or + DMAR bits in the USART CR3 register */ + USARTx->CR3 |= USART_DMAReq; + } + else + { + /* Disable the DMA transfer for selected requests by clearing the DMAT and/or + DMAR bits in the USART CR3 register */ + USARTx->CR3 &= (uint16_t)~USART_DMAReq; + } +} + +/** + * @brief Sets the address of the USART node. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_Address: Indicates the address of the USART node. + * @retval None + */ +void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_ADDRESS(USART_Address)); + + /* Clear the USART address */ + USARTx->CR2 &= CR2_Address_Mask; + /* Set the USART address node */ + USARTx->CR2 |= USART_Address; +} + +/** + * @brief Selects the USART WakeUp method. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_WakeUp: specifies the USART wakeup method. + * This parameter can be one of the following values: + * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection + * @arg USART_WakeUp_AddressMark: WakeUp by an address mark + * @retval None + */ +void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_WAKEUP(USART_WakeUp)); + + USARTx->CR1 &= CR1_WAKE_Mask; + USARTx->CR1 |= USART_WakeUp; +} + +/** + * @brief Determines if the USART is in mute mode or not. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param NewState: new state of the USART mute mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the USART mute mode by setting the RWU bit in the CR1 register */ + USARTx->CR1 |= CR1_RWU_Set; + } + else + { + /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */ + USARTx->CR1 &= CR1_RWU_Reset; + } +} + +/** + * @brief Sets the USART LIN Break detection length. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_LINBreakDetectLength: specifies the LIN break detection length. + * This parameter can be one of the following values: + * @arg USART_LINBreakDetectLength_10b: 10-bit break detection + * @arg USART_LINBreakDetectLength_11b: 11-bit break detection + * @retval None + */ +void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength)); + + USARTx->CR2 &= CR2_LBDL_Mask; + USARTx->CR2 |= USART_LINBreakDetectLength; +} + +/** + * @brief Enables or disables the USART抯 LIN mode. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param NewState: new state of the USART LIN mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ + USARTx->CR2 |= CR2_LINEN_Set; + } + else + { + /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */ + USARTx->CR2 &= CR2_LINEN_Reset; + } +} + +/** + * @brief Transmits single data through the USARTx peripheral. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param Data: the data to transmit. + * @retval None + */ +void USART_SendData(USART_TypeDef* USARTx, uint16_t Data) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_DATA(Data)); + + /* Transmit Data */ + USARTx->DR = (Data & (uint16_t)0x01FF); +} + +/** + * @brief Returns the most recent received data by the USARTx peripheral. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @retval The received data. + */ +uint16_t USART_ReceiveData(USART_TypeDef* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Receive Data */ + return (uint16_t)(USARTx->DR & (uint16_t)0x01FF); +} + +/** + * @brief Transmits break characters. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @retval None + */ +void USART_SendBreak(USART_TypeDef* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Send break characters */ + USARTx->CR1 |= CR1_SBK_Set; +} + +/** + * @brief Sets the specified USART guard time. + * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral. + * @param USART_GuardTime: specifies the guard time. + * @note The guard time bits are not available for UART4 and UART5. + * @retval None + */ +void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + + /* Clear the USART Guard time */ + USARTx->GTPR &= GTPR_LSB_Mask; + /* Set the USART guard time */ + USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); +} + +/** + * @brief Sets the system clock prescaler. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_Prescaler: specifies the prescaler clock. + * @note The function is used for IrDA mode with UART4 and UART5. + * @retval None + */ +void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Clear the USART prescaler */ + USARTx->GTPR &= GTPR_MSB_Mask; + /* Set the USART prescaler */ + USARTx->GTPR |= USART_Prescaler; +} + +/** + * @brief Enables or disables the USART抯 Smart Card mode. + * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral. + * @param NewState: new state of the Smart Card mode. + * This parameter can be: ENABLE or DISABLE. + * @note The Smart Card mode is not available for UART4 and UART5. + * @retval None + */ +void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the SC mode by setting the SCEN bit in the CR3 register */ + USARTx->CR3 |= CR3_SCEN_Set; + } + else + { + /* Disable the SC mode by clearing the SCEN bit in the CR3 register */ + USARTx->CR3 &= CR3_SCEN_Reset; + } +} + +/** + * @brief Enables or disables NACK transmission. + * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral. + * @param NewState: new state of the NACK transmission. + * This parameter can be: ENABLE or DISABLE. + * @note The Smart Card mode is not available for UART4 and UART5. + * @retval None + */ +void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the NACK transmission by setting the NACK bit in the CR3 register */ + USARTx->CR3 |= CR3_NACK_Set; + } + else + { + /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */ + USARTx->CR3 &= CR3_NACK_Reset; + } +} + +/** + * @brief Enables or disables the USART抯 Half Duplex communication. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param NewState: new state of the USART Communication. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ + USARTx->CR3 |= CR3_HDSEL_Set; + } + else + { + /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */ + USARTx->CR3 &= CR3_HDSEL_Reset; + } +} + + +/** + * @brief Enables or disables the USART's 8x oversampling mode. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param NewState: new state of the USART one bit sampling method. + * This parameter can be: ENABLE or DISABLE. + * @note + * This function has to be called before calling USART_Init() + * function in order to have correct baudrate Divider value. + * @retval None + */ +void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */ + USARTx->CR1 |= CR1_OVER8_Set; + } + else + { + /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */ + USARTx->CR1 &= CR1_OVER8_Reset; + } +} + +/** + * @brief Enables or disables the USART's one bit sampling method. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param NewState: new state of the USART one bit sampling method. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */ + USARTx->CR3 |= CR3_ONEBITE_Set; + } + else + { + /* Disable tthe one bit method by clearing the ONEBITE bit in the CR3 register */ + USARTx->CR3 &= CR3_ONEBITE_Reset; + } +} + +/** + * @brief Configures the USART's IrDA interface. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_IrDAMode: specifies the IrDA mode. + * This parameter can be one of the following values: + * @arg USART_IrDAMode_LowPower + * @arg USART_IrDAMode_Normal + * @retval None + */ +void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_IRDA_MODE(USART_IrDAMode)); + + USARTx->CR3 &= CR3_IRLP_Mask; + USARTx->CR3 |= USART_IrDAMode; +} + +/** + * @brief Enables or disables the USART's IrDA interface. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param NewState: new state of the IrDA mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the IrDA mode by setting the IREN bit in the CR3 register */ + USARTx->CR3 |= CR3_IREN_Set; + } + else + { + /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */ + USARTx->CR3 &= CR3_IREN_Reset; + } +} + +/** + * @brief Checks whether the specified USART flag is set or not. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) + * @arg USART_FLAG_LBD: LIN Break detection flag + * @arg USART_FLAG_TXE: Transmit data register empty flag + * @arg USART_FLAG_TC: Transmission Complete flag + * @arg USART_FLAG_RXNE: Receive data register not empty flag + * @arg USART_FLAG_IDLE: Idle Line detection flag + * @arg USART_FLAG_ORE: OverRun Error flag + * @arg USART_FLAG_NE: Noise Error flag + * @arg USART_FLAG_FE: Framing Error flag + * @arg USART_FLAG_PE: Parity Error flag + * @retval The new state of USART_FLAG (SET or RESET). + */ +FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_FLAG(USART_FLAG)); + /* The CTS flag is not available for UART4 and UART5 */ + if (USART_FLAG == USART_FLAG_CTS) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the USARTx's pending flags. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5). + * @arg USART_FLAG_LBD: LIN Break detection flag. + * @arg USART_FLAG_TC: Transmission Complete flag. + * @arg USART_FLAG_RXNE: Receive data register not empty flag. + * + * @note + * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) flags are cleared by software + * sequence: a read operation to USART_SR register (USART_GetFlagStatus()) + * followed by a read operation to USART_DR register (USART_ReceiveData()). + * - RXNE flag can be also cleared by a read to the USART_DR register + * (USART_ReceiveData()). + * - TC flag can be also cleared by software sequence: a read operation to + * USART_SR register (USART_GetFlagStatus()) followed by a write operation + * to USART_DR register (USART_SendData()). + * - TXE flag is cleared only by a write to the USART_DR register + * (USART_SendData()). + * @retval None + */ +void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CLEAR_FLAG(USART_FLAG)); + /* The CTS flag is not available for UART4 and UART5 */ + if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + USARTx->SR = (uint16_t)~USART_FLAG; +} + +/** + * @brief Checks whether the specified USART interrupt has occurred or not. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_IT: specifies the USART interrupt source to check. + * This parameter can be one of the following values: + * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) + * @arg USART_IT_LBD: LIN Break detection interrupt + * @arg USART_IT_TXE: Tansmit Data Register empty interrupt + * @arg USART_IT_TC: Transmission complete interrupt + * @arg USART_IT_RXNE: Receive Data register not empty interrupt + * @arg USART_IT_IDLE: Idle line detection interrupt + * @arg USART_IT_ORE_RX : OverRun Error interrupt if the RXNEIE bit is set + * @arg USART_IT_ORE_ER : OverRun Error interrupt if the EIE bit is set + * @arg USART_IT_NE: Noise Error interrupt + * @arg USART_IT_FE: Framing Error interrupt + * @arg USART_IT_PE: Parity Error interrupt + * @retval The new state of USART_IT (SET or RESET). + */ +ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT) +{ + uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_GET_IT(USART_IT)); + /* The CTS interrupt is not available for UART4 and UART5 */ + if (USART_IT == USART_IT_CTS) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + /* Get the USART register index */ + usartreg = (((uint8_t)USART_IT) >> 0x05); + /* Get the interrupt position */ + itmask = USART_IT & IT_Mask; + itmask = (uint32_t)0x01 << itmask; + + if (usartreg == 0x01) /* The IT is in CR1 register */ + { + itmask &= USARTx->CR1; + } + else if (usartreg == 0x02) /* The IT is in CR2 register */ + { + itmask &= USARTx->CR2; + } + else /* The IT is in CR3 register */ + { + itmask &= USARTx->CR3; + } + + bitpos = USART_IT >> 0x08; + bitpos = (uint32_t)0x01 << bitpos; + bitpos &= USARTx->SR; + if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/** + * @brief Clears the USARTx's interrupt pending bits. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_IT: specifies the interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) + * @arg USART_IT_LBD: LIN Break detection interrupt + * @arg USART_IT_TC: Transmission complete interrupt. + * @arg USART_IT_RXNE: Receive Data register not empty interrupt. + * + * @note + * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) pending bits are cleared by + * software sequence: a read operation to USART_SR register + * (USART_GetITStatus()) followed by a read operation to USART_DR register + * (USART_ReceiveData()). + * - RXNE pending bit can be also cleared by a read to the USART_DR register + * (USART_ReceiveData()). + * - TC pending bit can be also cleared by software sequence: a read + * operation to USART_SR register (USART_GetITStatus()) followed by a write + * operation to USART_DR register (USART_SendData()). + * - TXE pending bit is cleared only by a write to the USART_DR register + * (USART_SendData()). + * @retval None + */ +void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT) +{ + uint16_t bitpos = 0x00, itmask = 0x00; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CLEAR_IT(USART_IT)); + /* The CTS interrupt is not available for UART4 and UART5 */ + if (USART_IT == USART_IT_CTS) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + bitpos = USART_IT >> 0x08; + itmask = ((uint16_t)0x01 << (uint16_t)bitpos); + USARTx->SR = (uint16_t)~itmask; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/STM32F10x_FWLIB/src/stm32f10x_wwdg.c b/STM32F10x_FWLIB/src/stm32f10x_wwdg.c new file mode 100644 index 0000000..91137c3 --- /dev/null +++ b/STM32F10x_FWLIB/src/stm32f10x_wwdg.c @@ -0,0 +1,222 @@ +/** + ****************************************************************************** + * @file stm32f10x_wwdg.c + * @author MCD Application Team + * @version V3.6.2 + * @date 17-September-2021 + * @brief This file provides all the WWDG firmware functions. + ****************************************************************************** + * @attention + * + * Copyright (c) 2012 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_wwdg.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup WWDG + * @brief WWDG driver modules + * @{ + */ + +/** @defgroup WWDG_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup WWDG_Private_Defines + * @{ + */ + +/* ----------- WWDG registers bit address in the alias region ----------- */ +#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE) + +/* Alias word address of EWI bit */ +#define CFR_OFFSET (WWDG_OFFSET + 0x04) +#define EWI_BitNumber 0x09 +#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4)) + +/* --------------------- WWDG registers bit mask ------------------------ */ + +/* CR register bit mask */ +#define CR_WDGA_Set ((uint32_t)0x00000080) + +/* CFR register bit mask */ +#define CFR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) +#define CFR_W_Mask ((uint32_t)0xFFFFFF80) +#define BIT_Mask ((uint8_t)0x7F) + +/** + * @} + */ + +/** @defgroup WWDG_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup WWDG_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup WWDG_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup WWDG_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the WWDG peripheral registers to their default reset values. + * @param None + * @retval None + */ +void WWDG_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); +} + +/** + * @brief Sets the WWDG Prescaler. + * @param WWDG_Prescaler: specifies the WWDG Prescaler. + * This parameter can be one of the following values: + * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1 + * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2 + * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4 + * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8 + * @retval None + */ +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler)); + /* Clear WDGTB[1:0] bits */ + tmpreg = WWDG->CFR & CFR_WDGTB_Mask; + /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */ + tmpreg |= WWDG_Prescaler; + /* Store the new value */ + WWDG->CFR = tmpreg; +} + +/** + * @brief Sets the WWDG window value. + * @param WindowValue: specifies the window value to be compared to the downcounter. + * This parameter value must be lower than 0x80. + * @retval None + */ +void WWDG_SetWindowValue(uint8_t WindowValue) +{ + __IO uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_WWDG_WINDOW_VALUE(WindowValue)); + /* Clear W[6:0] bits */ + + tmpreg = WWDG->CFR & CFR_W_Mask; + + /* Set W[6:0] bits according to WindowValue value */ + tmpreg |= WindowValue & (uint32_t) BIT_Mask; + + /* Store the new value */ + WWDG->CFR = tmpreg; +} + +/** + * @brief Enables the WWDG Early Wakeup interrupt(EWI). + * @param None + * @retval None + */ +void WWDG_EnableIT(void) +{ + *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE; +} + +/** + * @brief Sets the WWDG counter value. + * @param Counter: specifies the watchdog counter value. + * This parameter must be a number between 0x40 and 0x7F. + * @retval None + */ +void WWDG_SetCounter(uint8_t Counter) +{ + /* Check the parameters */ + assert_param(IS_WWDG_COUNTER(Counter)); + /* Write to T[6:0] bits to configure the counter value, no need to do + a read-modify-write; writing a 0 to WDGA bit does nothing */ + WWDG->CR = Counter & BIT_Mask; +} + +/** + * @brief Enables WWDG and load the counter value. + * @param Counter: specifies the watchdog counter value. + * This parameter must be a number between 0x40 and 0x7F. + * @retval None + */ +void WWDG_Enable(uint8_t Counter) +{ + /* Check the parameters */ + assert_param(IS_WWDG_COUNTER(Counter)); + WWDG->CR = CR_WDGA_Set | Counter; +} + +/** + * @brief Checks whether the Early Wakeup interrupt flag is set or not. + * @param None + * @retval The new state of the Early Wakeup interrupt flag (SET or RESET) + */ +FlagStatus WWDG_GetFlagStatus(void) +{ + return (FlagStatus)(WWDG->SR); +} + +/** + * @brief Clears Early Wakeup interrupt flag. + * @param None + * @retval None + */ +void WWDG_ClearFlag(void) +{ + WWDG->SR = (uint32_t)RESET; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/USER/BT_BMS_V3.0.uvguix.ASUS b/USER/BT_BMS_V3.0.uvguix.ASUS new file mode 100644 index 0000000..997582b --- /dev/null +++ b/USER/BT_BMS_V3.0.uvguix.ASUS @@ -0,0 +1,3628 @@ + + + + -6.1 + +
    ### uVision Project, (C) Keil Software
    + + + + + + + + + + 38003 + Registers + 132 132 + + + 346 + Code Coverage + 770 160 + + + 204 + Performance Analyzer + 930 + + + + + + 35141 + Event Statistics + + 200 50 700 + + + 1506 + Symbols + + 64 64 64 + + + 1936 + Watch 1 + + 200 133 133 + + + 1937 + Watch 2 + + 200 133 133 + + + 1935 + Call Stack + Locals + + 200 133 133 + + + 2506 + Trace Data + + 75 135 130 95 70 230 200 150 + + + 466 + Source Browser + 500 + 166 + + + + + + + + 0 + 0 + 0 + 50 + 16 + + + + + + + 44 + 2 + 3 + + -1 + -1 + + + -1 + -1 + + + 39 + 434 + 1929 + 992 + + + + 0 + + 562 + 010000000400000001000000010000000100000001000000000000000200000000000000010000000100000000000000280000002800000001000000020000000100000001000000A9453A5C576F726B696E675C50726F6A6563745C4B65696C5C5B4578706F72742050726F6A6563745D5CC6E4CBFBC8CECEF15C5BB6C0C1A2B0E5D7D35DBCD2B4A2362E332E4C575CB3CCD0F25C332E3220D2C6D6B2CEAACCD5BEA7B3DBC6C1C4BB5C424D535F53544D33325F5B56342E302E322E31312B32342B325D28C6C1C4BBCAA3D3E0CAB1BCE4D3C5BBAF292831353041B2CECAFD295C524541444D455C726561646D652E747874000000000A726561646D652E74787400000000C5D4F200FFFFFFFFA7453A5C576F726B696E675C50726F6A6563745C4B65696C5C5B4578706F72742050726F6A6563745D5CC6E4CBFBC8CECEF15C5BB6C0C1A2B0E5D7D35DBCD2B4A2362E332E4C575CB3CCD0F25C332E3220D2C6D6B2CEAACCD5BEA7B3DBC6C1C4BB5C424D535F53544D33325F5B56342E302E322E31312B32342B325D28C6C1C4BBCAA3D3E0CAB1BCE4D3C5BBAF292831353041B2CECAFD295C4D4F55444C455C53637265656E2E63000000000853637265656E2E6300000000FFDC7800FFFFFFFF0100000010000000C5D4F200FFDC7800BECEA100F0A0A100BCA8E1009CC1B600F7B88600D9ADC200A5C2D700B3A6BE00EAD6A300F6FA7D00B5E99D005FC3CF00C1838300CACAD500010000000000000002000000160100006600000000060000A7020000 + + + + 0 + Build + + -1 + -1 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + C40000004F00000070040000BD000000 + + + 16 + C40000006600000070040000D4000000 + + + + 1005 + 1005 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000660000000F01000077020000 + + + 16 + 3C00000053000000FC000000F3000000 + + + + 109 + 109 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000660000000F01000077020000 + + + 16 + 3C000000530000001F0100000F020000 + + + + 1465 + 1465 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000AC0100006D040000FE010000 + + + 16 + 3C0000005300000074020000C1000000 + + + + 1466 + 1466 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000AC0100006D040000FE010000 + + + 16 + 3C0000005300000074020000C1000000 + + + + 1467 + 1467 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000AC0100006D040000FE010000 + + + 16 + 3C0000005300000074020000C1000000 + + + + 1468 + 1468 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000AC0100006D040000FE010000 + + + 16 + 3C0000005300000074020000C1000000 + + + + 1506 + 1506 + 0 + 0 + 0 + 0 + 32767 + 0 + 16384 + 0 + + 16 + B3030000660000006D0400008C010000 + + + 16 + 3C00000053000000FC000000F3000000 + + + + 1913 + 1913 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + C7000000660000006D040000A4000000 + + + 16 + 3C0000005300000074020000C1000000 + + + + 1935 + 1935 + 0 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 03000000AC0100006D040000FE010000 + + + 16 + 3C00000053000000FC000000F3000000 + + + + 1936 + 1936 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000AC0100006D040000FE010000 + + + 16 + 3C00000053000000FC000000F3000000 + + + + 1937 + 1937 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000AC0100006D040000FE010000 + + + 16 + 3C00000053000000FC000000F3000000 + + + + 1939 + 1939 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000AC0100006D040000FE010000 + + + 16 + 3C0000005300000074020000C1000000 + + + + 1940 + 1940 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000AC0100006D040000FE010000 + + + 16 + 3C0000005300000074020000C1000000 + + + + 1941 + 1941 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000AC0100006D040000FE010000 + + + 16 + 3C0000005300000074020000C1000000 + + + + 1942 + 1942 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000AC0100006D040000FE010000 + + + 16 + 3C0000005300000074020000C1000000 + + + + 195 + 195 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000660000000F01000077020000 + + + 16 + 3C000000530000001F0100000F020000 + + + + 196 + 196 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000660000000F01000077020000 + + + 16 + 3C000000530000001F0100000F020000 + + + + 197 + 197 + 1 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 03000000AB020000FD050000F5020000 + + + 16 + 3C0000005300000074020000C1000000 + + + + 198 + 198 + 0 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 00000000950100007004000017020000 + + + 16 + 3C0000005300000074020000C1000000 + + + + 199 + 199 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000AB020000FD050000F5020000 + + + 16 + 3C0000005300000074020000C1000000 + + + + 203 + 203 + 0 + 0 + 0 + 0 + 32767 + 0 + 8192 + 0 + + 16 + C7000000660000006D040000A4000000 + + + 16 + 3C0000005300000074020000C1000000 + + + + 204 + 204 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + C7000000660000006D040000A4000000 + + + 16 + 3C0000005300000074020000C1000000 + + + + 221 + 221 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 00000000000000000000000000000000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 2506 + 2506 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + B3030000660000006D0400008C010000 + + + 16 + 3C00000053000000FC000000F3000000 + + + + 2507 + 2507 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000AC0100006D040000FE010000 + + + 16 + 3C0000005300000074020000C1000000 + + + + 343 + 343 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + C7000000660000006D040000A4000000 + + + 16 + 3C0000005300000074020000C1000000 + + + + 346 + 346 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + C7000000660000006D040000A4000000 + + + 16 + 3C0000005300000074020000C1000000 + + + + 35141 + 35141 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + C7000000660000006D040000A4000000 + + + 16 + 3C00000053000000FC000000F3000000 + + + + 35824 + 35824 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + C7000000660000006D040000A4000000 + + + 16 + 3C0000005300000074020000C1000000 + + + + 35885 + 35885 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + B3030000660000006D0400008C010000 + + + 16 + 3C00000053000000FC000000F3000000 + + + + 35886 + 35886 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + B3030000660000006D0400008C010000 + + + 16 + 3C00000053000000FC000000F3000000 + + + + 35887 + 35887 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + B3030000660000006D0400008C010000 + + + 16 + 3C00000053000000FC000000F3000000 + + + + 35888 + 35888 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + B3030000660000006D0400008C010000 + + + 16 + 3C00000053000000FC000000F3000000 + + + + 35889 + 35889 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + B3030000660000006D0400008C010000 + + + 16 + 3C00000053000000FC000000F3000000 + + + + 35890 + 35890 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + B3030000660000006D0400008C010000 + + + 16 + 3C00000053000000FC000000F3000000 + + + + 35891 + 35891 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + B3030000660000006D0400008C010000 + + + 16 + 3C00000053000000FC000000F3000000 + + + + 35892 + 35892 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + B3030000660000006D0400008C010000 + + + 16 + 3C00000053000000FC000000F3000000 + + + + 35893 + 35893 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + B3030000660000006D0400008C010000 + + + 16 + 3C00000053000000FC000000F3000000 + + + + 35894 + 35894 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + B3030000660000006D0400008C010000 + + + 16 + 3C00000053000000FC000000F3000000 + + + + 35895 + 35895 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + B3030000660000006D0400008C010000 + + + 16 + 3C00000053000000FC000000F3000000 + + + + 35896 + 35896 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + B3030000660000006D0400008C010000 + + + 16 + 3C00000053000000FC000000F3000000 + + + + 35897 + 35897 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + B3030000660000006D0400008C010000 + + + 16 + 3C00000053000000FC000000F3000000 + + + + 35898 + 35898 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + B3030000660000006D0400008C010000 + + + 16 + 3C00000053000000FC000000F3000000 + + + + 35899 + 35899 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + B3030000660000006D0400008C010000 + + + 16 + 3C00000053000000FC000000F3000000 + + + + 35900 + 35900 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + B3030000660000006D0400008C010000 + + + 16 + 3C00000053000000FC000000F3000000 + + + + 35901 + 35901 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + B3030000660000006D0400008C010000 + + + 16 + 3C00000053000000FC000000F3000000 + + + + 35902 + 35902 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + B3030000660000006D0400008C010000 + + + 16 + 3C00000053000000FC000000F3000000 + + + + 35903 + 35903 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + B3030000660000006D0400008C010000 + + + 16 + 3C00000053000000FC000000F3000000 + + + + 35904 + 35904 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + B3030000660000006D0400008C010000 + + + 16 + 3C00000053000000FC000000F3000000 + + + + 35905 + 35905 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + B3030000660000006D0400008C010000 + + + 16 + 3C00000053000000FC000000F3000000 + + + + 38003 + 38003 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000660000000F01000077020000 + + + 16 + 3C000000530000001F0100000F020000 + + + + 38007 + 38007 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000AB020000FD050000F5020000 + + + 16 + 3C0000005300000074020000C1000000 + + + + 436 + 436 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000AB020000FD050000F5020000 + + + 16 + 3C000000530000001F0100000F020000 + + + + 437 + 437 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000AC0100006D040000FE010000 + + + 16 + 3C00000053000000FC000000F3000000 + + + + 440 + 440 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000AC0100006D040000FE010000 + + + 16 + 3C00000053000000FC000000F3000000 + + + + 463 + 463 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000AB020000FD050000F5020000 + + + 16 + 3C000000530000001F0100000F020000 + + + + 466 + 466 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000AB020000FD050000F5020000 + + + 16 + 3C000000530000001F0100000F020000 + + + + 470 + 470 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + C7000000660000006D040000A4000000 + + + 16 + 3C0000005300000074020000C1000000 + + + + 50000 + 50000 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + B3030000660000006D0400008C010000 + + + 16 + 3C00000053000000FC000000F3000000 + + + + 50001 + 50001 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + B3030000660000006D0400008C010000 + + + 16 + 3C00000053000000FC000000F3000000 + + + + 50002 + 50002 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + B3030000660000006D0400008C010000 + + + 16 + 3C00000053000000FC000000F3000000 + + + + 50003 + 50003 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + B3030000660000006D0400008C010000 + + + 16 + 3C00000053000000FC000000F3000000 + + + + 50004 + 50004 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + B3030000660000006D0400008C010000 + + + 16 + 3C00000053000000FC000000F3000000 + + + + 50005 + 50005 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + B3030000660000006D0400008C010000 + + + 16 + 3C00000053000000FC000000F3000000 + + + + 50006 + 50006 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + B3030000660000006D0400008C010000 + + + 16 + 3C00000053000000FC000000F3000000 + + + + 50007 + 50007 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + B3030000660000006D0400008C010000 + + + 16 + 3C00000053000000FC000000F3000000 + + + + 50008 + 50008 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + B3030000660000006D0400008C010000 + + + 16 + 3C00000053000000FC000000F3000000 + + + + 50009 + 50009 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + B3030000660000006D0400008C010000 + + + 16 + 3C00000053000000FC000000F3000000 + + + + 50010 + 50010 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + B3030000660000006D0400008C010000 + + + 16 + 3C00000053000000FC000000F3000000 + + + + 50011 + 50011 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + B3030000660000006D0400008C010000 + + + 16 + 3C00000053000000FC000000F3000000 + + + + 50012 + 50012 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + B3030000660000006D0400008C010000 + + + 16 + 3C00000053000000FC000000F3000000 + + + + 50013 + 50013 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + B3030000660000006D0400008C010000 + + + 16 + 3C00000053000000FC000000F3000000 + + + + 50014 + 50014 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + B3030000660000006D0400008C010000 + + + 16 + 3C00000053000000FC000000F3000000 + + + + 50015 + 50015 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + B3030000660000006D0400008C010000 + + + 16 + 3C00000053000000FC000000F3000000 + + + + 50016 + 50016 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + B3030000660000006D0400008C010000 + + + 16 + 3C00000053000000FC000000F3000000 + + + + 50017 + 50017 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + B3030000660000006D0400008C010000 + + + 16 + 3C00000053000000FC000000F3000000 + + + + 50018 + 50018 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + B3030000660000006D0400008C010000 + + + 16 + 3C00000053000000FC000000F3000000 + + + + 50019 + 50019 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + B3030000660000006D0400008C010000 + + + 16 + 3C00000053000000FC000000F3000000 + + + + 59392 + 59392 + 1 + 0 + 0 + 0 + 966 + 0 + 8192 + 0 + + 16 + 0000000000000000D10300001C000000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 59393 + 0 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 000000000E0300000006000021030000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 59399 + 59399 + 1 + 0 + 0 + 0 + 476 + 0 + 8192 + 1 + + 16 + 000000001C000000E701000038000000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 59400 + 59400 + 0 + 0 + 0 + 0 + 612 + 0 + 8192 + 2 + + 16 + 00000000380000006F02000054000000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 824 + 824 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000AC0100006D040000FE010000 + + + 16 + 3C00000053000000FC000000F3000000 + + + + 3312 + 000000000B000000000000000020000000000000FFFFFFFFFFFFFFFFC4000000BD00000070040000C1000000000000000100000004000000010000000000000000000000FFFFFFFF08000000CB00000057010000CC000000F08B00005A01000079070000D601000045890000FFFF02000B004354616262656450616E650020000000000000C40000006600000070040000D4000000C40000004F00000070040000BD0000000000000040280046080000000B446973617373656D626C7900000000CB00000001000000FFFFFFFFFFFFFFFF14506572666F726D616E636520416E616C797A6572000000005701000001000000FFFFFFFFFFFFFFFF14506572666F726D616E636520416E616C797A657200000000CC00000001000000FFFFFFFFFFFFFFFF0E4C6F67696320416E616C797A657200000000F08B000001000000FFFFFFFFFFFFFFFF0D436F646520436F766572616765000000005A01000001000000FFFFFFFFFFFFFFFF11496E737472756374696F6E205472616365000000007907000001000000FFFFFFFFFFFFFFFF0F53797374656D20416E616C797A657200000000D601000001000000FFFFFFFFFFFFFFFF104576656E742053746174697374696373000000004589000001000000FFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000000000000000000000001000000FFFFFFFFCB00000001000000FFFFFFFFCB000000000000000040000000000000FFFFFFFFFFFFFFFFAC0300004F000000B0030000A5010000000000000200000004000000010000000000000000000000FFFFFFFF2B000000E2050000CA0900002D8C00002E8C00002F8C0000308C0000318C0000328C0000338C0000348C0000358C0000368C0000378C0000388C0000398C00003A8C00003B8C00003C8C00003D8C00003E8C00003F8C0000408C0000418C000050C3000051C3000052C3000053C3000054C3000055C3000056C3000057C3000058C3000059C300005AC300005BC300005CC300005DC300005EC300005FC3000060C3000061C3000062C3000063C3000001800040000000000000B00300006600000070040000BC010000B00300004F00000070040000A501000000000000404100462B0000000753796D626F6C7300000000E205000001000000FFFFFFFFFFFFFFFF0A5472616365204461746100000000CA09000001000000FFFFFFFFFFFFFFFF00000000002D8C000001000000FFFFFFFFFFFFFFFF00000000002E8C000001000000FFFFFFFFFFFFFFFF00000000002F8C000001000000FFFFFFFFFFFFFFFF0000000000308C000001000000FFFFFFFFFFFFFFFF0000000000318C000001000000FFFFFFFFFFFFFFFF0000000000328C000001000000FFFFFFFFFFFFFFFF0000000000338C000001000000FFFFFFFFFFFFFFFF0000000000348C000001000000FFFFFFFFFFFFFFFF0000000000358C000001000000FFFFFFFFFFFFFFFF0000000000368C000001000000FFFFFFFFFFFFFFFF0000000000378C000001000000FFFFFFFFFFFFFFFF0000000000388C000001000000FFFFFFFFFFFFFFFF0000000000398C000001000000FFFFFFFFFFFFFFFF00000000003A8C000001000000FFFFFFFFFFFFFFFF00000000003B8C000001000000FFFFFFFFFFFFFFFF00000000003C8C000001000000FFFFFFFFFFFFFFFF00000000003D8C000001000000FFFFFFFFFFFFFFFF00000000003E8C000001000000FFFFFFFFFFFFFFFF00000000003F8C000001000000FFFFFFFFFFFFFFFF0000000000408C000001000000FFFFFFFFFFFFFFFF0000000000418C000001000000FFFFFFFFFFFFFFFF000000000050C3000001000000FFFFFFFFFFFFFFFF000000000051C3000001000000FFFFFFFFFFFFFFFF000000000052C3000001000000FFFFFFFFFFFFFFFF000000000053C3000001000000FFFFFFFFFFFFFFFF000000000054C3000001000000FFFFFFFFFFFFFFFF000000000055C3000001000000FFFFFFFFFFFFFFFF000000000056C3000001000000FFFFFFFFFFFFFFFF000000000057C3000001000000FFFFFFFFFFFFFFFF000000000058C3000001000000FFFFFFFFFFFFFFFF000000000059C3000001000000FFFFFFFFFFFFFFFF00000000005AC3000001000000FFFFFFFFFFFFFFFF00000000005BC3000001000000FFFFFFFFFFFFFFFF00000000005CC3000001000000FFFFFFFFFFFFFFFF00000000005DC3000001000000FFFFFFFFFFFFFFFF00000000005EC3000001000000FFFFFFFFFFFFFFFF00000000005FC3000001000000FFFFFFFFFFFFFFFF000000000060C3000001000000FFFFFFFFFFFFFFFF000000000061C3000001000000FFFFFFFFFFFFFFFF000000000062C3000001000000FFFFFFFFFFFFFFFF000000000063C3000001000000FFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000000000000000000000001000000FFFFFFFFE205000001000000FFFFFFFFE2050000000000000010000001000000FFFFFFFFFFFFFFFF120100004F000000160100009002000001000000020000100400000001000000FDFEFFFFF2040000FFFFFFFF05000000ED0300006D000000C3000000C40000007394000001800010000001000000000000006600000012010000A7020000000000004F00000012010000900200000000000040410056050000000750726F6A65637401000000ED03000001000000FFFFFFFFFFFFFFFF05426F6F6B73010000006D00000001000000FFFFFFFFFFFFFFFF0946756E6374696F6E7301000000C300000001000000FFFFFFFFFFFFFFFF0954656D706C6174657301000000C400000001000000FFFFFFFFFFFFFFFF09526567697374657273000000007394000001000000FFFFFFFFFFFFFFFF00000000000000000000000000000000000000000000000001000000FFFFFFFFED03000001000000FFFFFFFFED030000000000000080000000000000FFFFFFFFFFFFFFFF0000000091010000700400009501000000000000010000000400000001000000000000000000000000000000000000000000000001000000C6000000FFFFFFFF0F0000008F070000930700009407000095070000960700009007000091070000B5010000B801000038030000B9050000BA050000BB050000BC050000CB0900000180008000000000000000000000AC010000700400002E0200000000000095010000700400001702000000000000404100460F0000001343616C6C20537461636B202B204C6F63616C73000000008F07000001000000FFFFFFFFFFFFFFFF0755415254202331000000009307000001000000FFFFFFFFFFFFFFFF0755415254202332000000009407000001000000FFFFFFFFFFFFFFFF0755415254202333000000009507000001000000FFFFFFFFFFFFFFFF15446562756720287072696E74662920566965776572000000009607000001000000FFFFFFFFFFFFFFFF0757617463682031000000009007000001000000FFFFFFFFFFFFFFFF0757617463682032000000009107000001000000FFFFFFFFFFFFFFFF10547261636520457863657074696F6E7300000000B501000001000000FFFFFFFFFFFFFFFF0E4576656E7420436F756E7465727300000000B801000001000000FFFFFFFFFFFFFFFF09554C494E4B706C7573000000003803000001000000FFFFFFFFFFFFFFFF084D656D6F7279203100000000B905000001000000FFFFFFFFFFFFFFFF084D656D6F7279203200000000BA05000001000000FFFFFFFFFFFFFFFF084D656D6F7279203300000000BB05000001000000FFFFFFFFFFFFFFFF084D656D6F7279203400000000BC05000001000000FFFFFFFFFFFFFFFF105472616365204E617669676174696F6E00000000CB09000001000000FFFFFFFFFFFFFFFFFFFFFFFF0000000001000000000000000000000001000000FFFFFFFF38020000950100003C0200001702000000000000020000000400000000000000000000000000000000000000000000000000000002000000C6000000FFFFFFFF8F07000001000000FFFFFFFF8F07000001000000C6000000000000000080000001000000FFFFFFFFFFFFFFFF00000000900200000006000094020000010000000100001004000000010000004CFEFFFF00010000FFFFFFFF06000000C5000000C7000000B4010000D2010000CF010000779400000180008000000100000000000000AB02000000060000250300000000000094020000000600000E0300000000000040820056060000000C4275696C64204F757470757401000000C500000001000000FFFFFFFFFFFFFFFF0D46696E6420496E2046696C657301000000C700000001000000FFFFFFFFFFFFFFFF0A4572726F72204C69737400000000B401000001000000FFFFFFFFFFFFFFFF0E536F757263652042726F7773657200000000D201000001000000FFFFFFFFFFFFFFFF0E416C6C205265666572656E63657300000000CF01000001000000FFFFFFFFFFFFFFFF0742726F77736572010000007794000001000000FFFFFFFFFFFFFFFF00000000000000000000000000000000000000000000000001000000FFFFFFFFC500000001000000FFFFFFFFC5000000000000000000000000000000 + + + 59392 + File + + 2875 + 00200000010000002800FFFF01001100434D4643546F6F6C426172427574746F6E00E100000000000000000000000000000000000000000000000100000001000000018001E100000000000001000000000000000000000000000000000100000001000000018003E1000000000000020000000000000000000000000000000001000000010000000180CD7F0000000000000300000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018023E100000000040004000000000000000000000000000000000100000001000000018022E100000000040005000000000000000000000000000000000100000001000000018025E10000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001802BE10000000000000700000000000000000000000000000000010000000100000001802CE10000000004000800000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001807A8A0000000000000900000000000000000000000000000000010000000100000001807B8A0000000004000A00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180D3B00000000000000B000000000000000000000000000000000100000001000000018015B10000000004000C0000000000000000000000000000000001000000010000000180F4B00000000004000D000000000000000000000000000000000100000001000000018036B10000000004000E00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FF88000000000400460000000000000000000000000000000001000000010000000180FE880000000004004500000000000000000000000000000000010000000100000001800B810000000004001300000000000000000000000000000000010000000100000001800C810000000004001400000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180F0880000020000000F000000000000000000000000000000000100000001000000FFFF0100120043555646696E64436F6D626F427574746F6EE803000000000000000000000000000000000000000000000001000000010000009600000002002050000000000870616765312E7438960000000000000014000870616765312E7438165343525F53656E64282270616765312E74382E7478740763757272656E74125343525F53656E645F546F74616C496E666F185343525F53656E645F536C6176655F4261736963496E666F057061676531027438104146455F57726974654F6E654279746512535049315F526561645772697465427974650A535049315F4572726F72057370692E680D75665F55415254305F496E69740C75665F535049315F496E69740D75665F55415254335F496E69740A55415254335F496E69740555415254331150494E5F4348475F4C494D49545F50574D074354524C5F4F6E085650524F5F4F66660A736C6565705F666C61670000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018024E10000000000001100000000000000000000000000000000010000000100000001800A810000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6E2280000002000000150000002153746172742F53746F70202644656275672053657373696F6E094374726C2B46350000000000000000000000000100000001000000000000000000000001000000020021802280000000000000150000002153746172742F53746F70202644656275672053657373696F6E094374726C2B4635000000000000000000000000010000000100000000000000000000000100000000002180E0010000000000007500000021456E65726779204D6561737572656D656E742026776974686F75742044656275670000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C488000000000000160000000000000000000000000000000001000000010000000180C988000000000400180000000000000000000000000000000001000000010000000180C788000000000000190000000000000000000000000000000001000000010000002180C8880000000000001700000027264B696C6C20416C6C20427265616B706F696E747320696E2043757272656E7420546172676574000000000000000000000000010000000100000000000000000000000100000003002180C8880000000000001700000027264B696C6C20416C6C20427265616B706F696E747320696E2043757272656E7420546172676574000000000000000000000000010000000100000000000000000000000100000000002180E50100000000000078000000264B696C6C20416C6C20427265616B706F696E747320696E204163746976652050726F6A656374000000000000000000000000010000000100000000000000000000000100000000002180E601000000000000790000002F4B696C6C20416C6C20427265616B706F696E747320696E204D756C74692D50726F6A65637420576F726B73706163650000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000021804C010000020001001A0000000F2650726F6A6563742057696E646F77000000000000000000000000010000000100000000000000000000000100000008002180DD880000000000001A0000000750726F6A656374000000000000000000000000010000000100000000000000000000000100000000002180DC8B0000000000003A00000005426F6F6B73000000000000000000000000010000000100000000000000000000000100000000002180E18B0000000000003B0000000946756E6374696F6E73000000000000000000000000010000000100000000000000000000000100000000002180E28B000000000000400000000954656D706C6174657300000000000000000000000001000000010000000000000000000000010000000000218018890000000000003D0000000E536F757263652042726F777365720000000000000000000000000100000001000000000000000000000001000000000021800000000000000400FFFFFFFF00000000000000000001000000000000000100000000000000000000000100000000002180D988000000000000390000000C4275696C64204F7574707574000000000000000000000000010000000100000000000000000000000100000000002180E38B000000000000410000000B46696E64204F75747075740000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FB7F0000000000001B000000000000000000000000000000000100000001000000000000000446696C65C6030000 + + + 1423 + 2800FFFF01001100434D4643546F6F6C426172427574746F6E00E1000000000000FFFFFFFF000100000000000000010000000000000001000000018001E1000000000000FFFFFFFF000100000000000000010000000000000001000000018003E1000000000000FFFFFFFF0001000000000000000100000000000000010000000180CD7F000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF000000000000000000010000000000000001000000018023E1000000000000FFFFFFFF000100000000000000010000000000000001000000018022E1000000000000FFFFFFFF000100000000000000010000000000000001000000018025E1000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001802BE1000000000000FFFFFFFF00010000000000000001000000000000000100000001802CE1000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001807A8A000000000000FFFFFFFF00010000000000000001000000000000000100000001807B8A000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180D3B0000000000000FFFFFFFF000100000000000000010000000000000001000000018015B1000000000000FFFFFFFF0001000000000000000100000000000000010000000180F4B0000000000000FFFFFFFF000100000000000000010000000000000001000000018036B1000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180FF88000000000000FFFFFFFF0001000000000000000100000000000000010000000180FE88000000000000FFFFFFFF00010000000000000001000000000000000100000001800B81000000000000FFFFFFFF00010000000000000001000000000000000100000001800C81000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180F088000000000000FFFFFFFF0001000000000000000100000000000000010000000180EE7F000000000000FFFFFFFF000100000000000000010000000000000001000000018024E1000000000000FFFFFFFF00010000000000000001000000000000000100000001800A81000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001802280000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180C488000000000000FFFFFFFF0001000000000000000100000000000000010000000180C988000000000000FFFFFFFF0001000000000000000100000000000000010000000180C788000000000000FFFFFFFF0001000000000000000100000000000000010000000180C888000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180DD88000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180FB7F000000000000FFFFFFFF000100000000000000010000000000000001000000 + + + 1423 + 2800FFFF01001100434D4643546F6F6C426172427574746F6E00E100000000000000000000000000000000000000000000000100000001000000018001E100000000000001000000000000000000000000000000000100000001000000018003E1000000000000020000000000000000000000000000000001000000010000000180CD7F0000000000000300000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018023E100000000000004000000000000000000000000000000000100000001000000018022E100000000000005000000000000000000000000000000000100000001000000018025E10000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001802BE10000000000000700000000000000000000000000000000010000000100000001802CE10000000000000800000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001807A8A0000000000000900000000000000000000000000000000010000000100000001807B8A0000000000000A00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180D3B00000000000000B000000000000000000000000000000000100000001000000018015B10000000000000C0000000000000000000000000000000001000000010000000180F4B00000000000000D000000000000000000000000000000000100000001000000018036B10000000000000E00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FF880000000000000F0000000000000000000000000000000001000000010000000180FE880000000000001000000000000000000000000000000000010000000100000001800B810000000000001100000000000000000000000000000000010000000100000001800C810000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180F088000000000000130000000000000000000000000000000001000000010000000180EE7F00000000000014000000000000000000000000000000000100000001000000018024E10000000000001500000000000000000000000000000000010000000100000001800A810000000000001600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018022800000000000001700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C488000000000000180000000000000000000000000000000001000000010000000180C988000000000000190000000000000000000000000000000001000000010000000180C7880000000000001A0000000000000000000000000000000001000000010000000180C8880000000000001B00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180DD880000000000001C00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FB7F0000000000001D000000000000000000000000000000000100000001000000 + + + + 59399 + Build + + 976 + 00200000010000001000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F0000000000001C0000000000000000000000000000000001000000010000000180D07F0000000000001D000000000000000000000000000000000100000001000000018030800000000000001E000000000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6EC7040000000000006A0000000C4261746368204275696C2664000000000000000000000000010000000100000000000000000000000100000004000580C7040000000000006A0000000C4261746368204275696C266400000000000000000000000001000000010000000000000000000000010000000000058046070000000000006B0000000D42617463682052656275696C640000000000000000000000000100000001000000000000000000000001000000000005804707000000000000FFFFFFFF0B426174636820436C65616E0100000000000000000000000100000001000000000000000000000001000000000005809E8A0000000000001F0000000F4261746326682053657475702E2E2E000000000000000000000000010000000100000000000000000000000100000000000180D17F0000000004002000000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001804C8A0000000000002100000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000FFFF01001900434D4643546F6F6C426172436F6D626F426F78427574746F6EBA000000000000000000000000000000000000000000000000010000000100000096000000030020500000000008546172676574203196000000000000000100085461726765742031000000000180EB880000000000002200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C07F000000000000230000000000000000000000000000000001000000010000000180B08A000000000400240000000000000000000000000000000001000000010000000180A8010000000000004E00000000000000000000000000000000010000000100000001807202000000000000530000000000000000000000000000000001000000010000000180BE010000000000005000000000000000000000000000000000010000000100000000000000054275696C64DC010000 + + + 583 + 1000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F000000000000FFFFFFFF0001000000000000000100000000000000010000000180D07F000000000000FFFFFFFF00010000000000000001000000000000000100000001803080000000000000FFFFFFFF00010000000000000001000000000000000100000001809E8A000000000000FFFFFFFF0001000000000000000100000000000000010000000180D17F000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001804C8A000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001806680000000000000FFFFFFFF0001000000000000000100000000000000010000000180EB88000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180C07F000000000000FFFFFFFF0001000000000000000100000000000000010000000180B08A000000000000FFFFFFFF0001000000000000000100000000000000010000000180A801000000000000FFFFFFFF00010000000000000001000000000000000100000001807202000000000000FFFFFFFF0001000000000000000100000000000000010000000180BE01000000000000FFFFFFFF000100000000000000010000000000000001000000 + + + 583 + 1000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F000000000000000000000000000000000000000000000001000000010000000180D07F00000000000001000000000000000000000000000000000100000001000000018030800000000000000200000000000000000000000000000000010000000100000001809E8A000000000000030000000000000000000000000000000001000000010000000180D17F0000000000000400000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001804C8A0000000000000500000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001806680000000000000060000000000000000000000000000000001000000010000000180EB880000000000000700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C07F000000000000080000000000000000000000000000000001000000010000000180B08A000000000000090000000000000000000000000000000001000000010000000180A8010000000000000A000000000000000000000000000000000100000001000000018072020000000000000B0000000000000000000000000000000001000000010000000180BE010000000000000C000000000000000000000000000000000100000001000000 + + + + 59400 + Debug + + 2373 + 00200000000000001900FFFF01001100434D4643546F6F6C426172427574746F6ECC880000000000002500000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018017800000000000002600000000000000000000000000000000010000000100000001801D800000000000002700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001801A800000000000002800000000000000000000000000000000010000000100000001801B80000000000000290000000000000000000000000000000001000000010000000180E57F0000000000002A00000000000000000000000000000000010000000100000001801C800000000000002B00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018000890000000000002C00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180E48B0000000000002D0000000000000000000000000000000001000000010000000180F07F0000000000002E0000000000000000000000000000000001000000010000000180E8880000000000003700000000000000000000000000000000010000000100000001803B010000000000002F0000000000000000000000000000000001000000010000000180BB8A00000000000030000000000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6E0E01000000000000310000000D57617463682057696E646F7773000000000000000000000000010000000100000000000000000000000100000003001380D88B00000000000031000000085761746368202631000000000000000000000000010000000100000000000000000000000100000000001380D98B00000000000031000000085761746368202632000000000000000000000000010000000100000000000000000000000100000000001380CE01000000000000FFFFFFFF0C576174636820416E63686F720100000000000000010000000000000001000000000000000000000001000000000013800F01000000000000320000000E4D656D6F72792057696E646F7773000000000000000000000000010000000100000000000000000000000100000004001380D28B00000000000032000000094D656D6F7279202631000000000000000000000000010000000100000000000000000000000100000000001380D38B00000000000032000000094D656D6F7279202632000000000000000000000000010000000100000000000000000000000100000000001380D48B00000000000032000000094D656D6F7279202633000000000000000000000000010000000100000000000000000000000100000000001380D58B00000000000032000000094D656D6F72792026340000000000000000000000000100000001000000000000000000000001000000000013801001000000000000330000000E53657269616C2057696E646F77730000000000000000000000000100000001000000000000000000000001000000040013809307000000000000330000000855415254202326310000000000000000000000000100000001000000000000000000000001000000000013809407000000000000330000000855415254202326320000000000000000000000000100000001000000000000000000000001000000000013809507000000000000330000000855415254202326330000000000000000000000000100000001000000000000000000000001000000000013809607000000000000330000001626446562756720287072696E746629205669657765720000000000000000000000000100000001000000000000000000000001000000000013803C010000000000007200000010416E616C797369732057696E646F7773000000000000000000000000010000000100000000000000000000000100000004001380658A000000000000340000000F264C6F67696320416E616C797A6572000000000000000000000000010000000100000000000000000000000100000000001380DC7F0000000000003E0000001526506572666F726D616E636520416E616C797A6572000000000000000000000000010000000100000000000000000000000100000000001380E788000000000000380000000E26436F646520436F766572616765000000000000000000000000010000000100000000000000000000000100000000001380CD01000000000000FFFFFFFF0F416E616C7973697320416E63686F7201000000000000000100000000000000010000000000000000000000010000000000138053010000000000003F0000000D54726163652057696E646F77730000000000000000000000000100000001000000000000000000000001000000010013805401000000000000FFFFFFFF115472616365204D656E7520416E63686F720100000000000000010000000000000001000000000000000000000001000000000013802901000000000000350000001553797374656D205669657765722057696E646F77730000000000000000000000000100000001000000000000000000000001000000010013804B01000000000000FFFFFFFF1453797374656D2056696577657220416E63686F720100000000000000010000000000000001000000000000000000000001000000000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000013800189000000000000360000000F26546F6F6C626F782057696E646F7700000000000000000000000001000000010000000000000000000000010000000300138044C5000000000000FFFFFFFF0E5570646174652057696E646F77730100000000000000010000000000000001000000000000000000000001000000000013800000000000000400FFFFFFFF000000000000000000010000000000000001000000000000000000000001000000000013805B01000000000000FFFFFFFF12546F6F6C626F78204D656E75416E63686F72010000000000000001000000000000000100000000000000000000000100000000000000000005446562756764020000 + + + 898 + 1900FFFF01001100434D4643546F6F6C426172427574746F6ECC88000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001801780000000000000FFFFFFFF00010000000000000001000000000000000100000001801D80000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001801A80000000000000FFFFFFFF00010000000000000001000000000000000100000001801B80000000000000FFFFFFFF0001000000000000000100000000000000010000000180E57F000000000000FFFFFFFF00010000000000000001000000000000000100000001801C80000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001800089000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180E48B000000000000FFFFFFFF0001000000000000000100000000000000010000000180F07F000000000000FFFFFFFF0001000000000000000100000000000000010000000180E888000000000000FFFFFFFF00010000000000000001000000000000000100000001803B01000000000000FFFFFFFF0001000000000000000100000000000000010000000180BB8A000000000000FFFFFFFF0001000000000000000100000000000000010000000180D88B000000000000FFFFFFFF0001000000000000000100000000000000010000000180D28B000000000000FFFFFFFF00010000000000000001000000000000000100000001809307000000000000FFFFFFFF0001000000000000000100000000000000010000000180658A000000000000FFFFFFFF0001000000000000000100000000000000010000000180C18A000000000000FFFFFFFF0001000000000000000100000000000000010000000180EE8B000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001800189000000000000FFFFFFFF000100000000000000010000000000000001000000 + + + 898 + 1900FFFF01001100434D4643546F6F6C426172427574746F6ECC880000000000000000000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018017800000000000000100000000000000000000000000000000010000000100000001801D800000000000000200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001801A800000000000000300000000000000000000000000000000010000000100000001801B80000000000000040000000000000000000000000000000001000000010000000180E57F0000000000000500000000000000000000000000000000010000000100000001801C800000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018000890000000000000700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180E48B000000000000080000000000000000000000000000000001000000010000000180F07F000000000000090000000000000000000000000000000001000000010000000180E8880000000000000A00000000000000000000000000000000010000000100000001803B010000000000000B0000000000000000000000000000000001000000010000000180BB8A0000000000000C0000000000000000000000000000000001000000010000000180D88B0000000000000D0000000000000000000000000000000001000000010000000180D28B0000000000000E000000000000000000000000000000000100000001000000018093070000000000000F0000000000000000000000000000000001000000010000000180658A000000000000100000000000000000000000000000000001000000010000000180C18A000000000000110000000000000000000000000000000001000000010000000180EE8B0000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180018900000000000013000000000000000000000000000000000100000001000000 + + + + 0 + 1536 + 864 + + + + 1 + Debug + + -1 + -1 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + C40000004F000000B205000088000000 + + + 16 + 4408000066000000320D00009F000000 + + + + 1005 + 1005 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000066000000BD000000F6020000 + + + 16 + 70000000870000003001000027010000 + + + + 109 + 109 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000066000000BD000000F6020000 + + + 16 + 70000000870000005301000043020000 + + + + 1465 + 1465 + 1 + 0 + 0 + 0 + 32767 + 0 + 16384 + 0 + + 16 + B9050000660000007D070000CD030000 + + + 16 + 4A050000AF010000490700006E040000 + + + + 1466 + 1466 + 0 + 0 + 0 + 0 + 32767 + 0 + 16384 + 0 + + 16 + B9050000660000007D070000CD030000 + + + 16 + 4A050000AF010000490700006E040000 + + + + 1467 + 1467 + 0 + 0 + 0 + 0 + 32767 + 0 + 16384 + 0 + + 16 + B9050000660000007D070000CD030000 + + + 16 + 4A050000AF010000490700006E040000 + + + + 1468 + 1468 + 0 + 0 + 0 + 0 + 32767 + 0 + 16384 + 0 + + 16 + B9050000660000007D070000CD030000 + + + 16 + 4A050000AF010000490700006E040000 + + + + 1506 + 1506 + 0 + 0 + 0 + 0 + 32767 + 0 + 16384 + 0 + + 16 + 4003000066000000FA0300003D020000 + + + 16 + 70000000870000003001000027010000 + + + + 1913 + 1913 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + C700000066000000AF0500006F000000 + + + 16 + 7000000087000000A8020000F5000000 + + + + 1935 + 1935 + 1 + 0 + 0 + 0 + 32767 + 0 + 16384 + 0 + + 16 + B9050000660000007D070000CD030000 + + + 16 + 4A050000AF010000490700006E040000 + + + + 1936 + 1936 + 1 + 0 + 0 + 0 + 32767 + 0 + 16384 + 0 + + 16 + B9050000660000007D070000CD030000 + + + 16 + 4A050000AF010000490700006E040000 + + + + 1937 + 1937 + 1 + 0 + 0 + 0 + 32767 + 0 + 16384 + 0 + + 16 + B9050000660000007D070000CD030000 + + + 16 + 4A050000AF010000490700006E040000 + + + + 1939 + 1939 + 0 + 0 + 0 + 0 + 32767 + 0 + 16384 + 0 + + 16 + B9050000660000007D070000CD030000 + + + 16 + 4A050000AF010000490700006E040000 + + + + 1940 + 1940 + 0 + 0 + 0 + 0 + 32767 + 0 + 16384 + 0 + + 16 + B9050000660000007D070000CD030000 + + + 16 + 4A050000AF010000490700006E040000 + + + + 1941 + 1941 + 0 + 0 + 0 + 0 + 32767 + 0 + 16384 + 0 + + 16 + B9050000660000007D070000CD030000 + + + 16 + 4A050000AF010000490700006E040000 + + + + 1942 + 1942 + 0 + 0 + 0 + 0 + 32767 + 0 + 16384 + 0 + + 16 + B9050000660000007D070000CD030000 + + + 16 + 4A050000AF010000490700006E040000 + + + + 195 + 195 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000066000000BD000000F6020000 + + + 16 + 70000000870000005301000043020000 + + + + 196 + 196 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000066000000BD000000F6020000 + + + 16 + 70000000870000005301000043020000 + + + + 197 + 197 + 0 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 030000002A030000AF050000CD030000 + + + 16 + AF000000FB020000AC04000046030000 + + + + 198 + 198 + 1 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 030000002A030000AF050000CD030000 + + + 16 + AF000000FB020000AC04000046030000 + + + + 199 + 199 + 1 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 030000002A030000AF050000CD030000 + + + 16 + AF000000FB020000AC04000046030000 + + + + 203 + 203 + 1 + 0 + 0 + 0 + 32767 + 0 + 8192 + 0 + + 16 + C400000063000000B205000088000000 + + + 16 + 7000000087000000A8020000F5000000 + + + + 204 + 204 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + C700000066000000AF0500006F000000 + + + 16 + 7000000087000000A8020000F5000000 + + + + 221 + 221 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 00000000000000000000000000000000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 2506 + 2506 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 4003000066000000FA0300003D020000 + + + 16 + 70000000870000003001000027010000 + + + + 2507 + 2507 + 0 + 0 + 0 + 0 + 32767 + 0 + 16384 + 0 + + 16 + B9050000660000007D070000CD030000 + + + 16 + 4A050000AF010000490700006E040000 + + + + 343 + 343 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + C700000066000000AF0500006F000000 + + + 16 + 7000000087000000A8020000F5000000 + + + + 346 + 346 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + C700000066000000AF0500006F000000 + + + 16 + 7000000087000000A8020000F5000000 + + + + 35141 + 35141 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + C700000066000000AF0500006F000000 + + + 16 + 70000000870000003001000027010000 + + + + 35824 + 35824 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + C700000066000000AF0500006F000000 + + + 16 + 7000000087000000A8020000F5000000 + + + + 35885 + 35885 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 4003000066000000FA0300003D020000 + + + 16 + 70000000870000003001000027010000 + + + + 35886 + 35886 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 4003000066000000FA0300003D020000 + + + 16 + 70000000870000003001000027010000 + + + + 35887 + 35887 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 4003000066000000FA0300003D020000 + + + 16 + 70000000870000003001000027010000 + + + + 35888 + 35888 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 4003000066000000FA0300003D020000 + + + 16 + 70000000870000003001000027010000 + + + + 35889 + 35889 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 4003000066000000FA0300003D020000 + + + 16 + 70000000870000003001000027010000 + + + + 35890 + 35890 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 4003000066000000FA0300003D020000 + + + 16 + 70000000870000003001000027010000 + + + + 35891 + 35891 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 4003000066000000FA0300003D020000 + + + 16 + 70000000870000003001000027010000 + + + + 35892 + 35892 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 4003000066000000FA0300003D020000 + + + 16 + 70000000870000003001000027010000 + + + + 35893 + 35893 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 4003000066000000FA0300003D020000 + + + 16 + 70000000870000003001000027010000 + + + + 35894 + 35894 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 4003000066000000FA0300003D020000 + + + 16 + 70000000870000003001000027010000 + + + + 35895 + 35895 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 4003000066000000FA0300003D020000 + + + 16 + 70000000870000003001000027010000 + + + + 35896 + 35896 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 4003000066000000FA0300003D020000 + + + 16 + 70000000870000003001000027010000 + + + + 35897 + 35897 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 4003000066000000FA0300003D020000 + + + 16 + 70000000870000003001000027010000 + + + + 35898 + 35898 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 4003000066000000FA0300003D020000 + + + 16 + 70000000870000003001000027010000 + + + + 35899 + 35899 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 4003000066000000FA0300003D020000 + + + 16 + 70000000870000003001000027010000 + + + + 35900 + 35900 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 4003000066000000FA0300003D020000 + + + 16 + 70000000870000003001000027010000 + + + + 35901 + 35901 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 4003000066000000FA0300003D020000 + + + 16 + 70000000870000003001000027010000 + + + + 35902 + 35902 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 4003000066000000FA0300003D020000 + + + 16 + 70000000870000003001000027010000 + + + + 35903 + 35903 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 4003000066000000FA0300003D020000 + + + 16 + 70000000870000003001000027010000 + + + + 35904 + 35904 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 4003000066000000FA0300003D020000 + + + 16 + 70000000870000003001000027010000 + + + + 35905 + 35905 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 4003000066000000FA0300003D020000 + + + 16 + 70000000870000003001000027010000 + + + + 38003 + 38003 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000066000000BD000000F6020000 + + + 16 + 70000000870000005301000043020000 + + + + 38007 + 38007 + 0 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 030000002A030000AF050000CD030000 + + + 16 + AF000000FB020000AC04000046030000 + + + + 436 + 436 + 0 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 030000002A030000AF050000CD030000 + + + 16 + AF000000FB020000AC04000046030000 + + + + 437 + 437 + 0 + 0 + 0 + 0 + 32767 + 0 + 16384 + 0 + + 16 + B9050000660000007D070000CD030000 + + + 16 + 4A050000AF010000490700006E040000 + + + + 440 + 440 + 0 + 0 + 0 + 0 + 32767 + 0 + 16384 + 0 + + 16 + B9050000660000007D070000CD030000 + + + 16 + 4A050000AF010000490700006E040000 + + + + 463 + 463 + 0 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 030000002A030000AF050000CD030000 + + + 16 + AF000000FB020000AC04000046030000 + + + + 466 + 466 + 0 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 030000002A030000AF050000CD030000 + + + 16 + AF000000FB020000AC04000046030000 + + + + 470 + 470 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + C700000066000000AF0500006F000000 + + + 16 + 7000000087000000A8020000F5000000 + + + + 50000 + 50000 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 4003000066000000FA0300003D020000 + + + 16 + 70000000870000003001000027010000 + + + + 50001 + 50001 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 4003000066000000FA0300003D020000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 50002 + 50002 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 4003000066000000FA0300003D020000 + + + 16 + 70000000870000003001000027010000 + + + + 50003 + 50003 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 4003000066000000FA0300003D020000 + + + 16 + 70000000870000003001000027010000 + + + + 50004 + 50004 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 4003000066000000FA0300003D020000 + + + 16 + 70000000870000003001000027010000 + + + + 50005 + 50005 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 4003000066000000FA0300003D020000 + + + 16 + 70000000870000003001000027010000 + + + + 50006 + 50006 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 4003000066000000FA0300003D020000 + + + 16 + 70000000870000003001000027010000 + + + + 50007 + 50007 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 4003000066000000FA0300003D020000 + + + 16 + 70000000870000003001000027010000 + + + + 50008 + 50008 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 4003000066000000FA0300003D020000 + + + 16 + 70000000870000003001000027010000 + + + + 50009 + 50009 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 4003000066000000FA0300003D020000 + + + 16 + 70000000870000003001000027010000 + + + + 50010 + 50010 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 4003000066000000FA0300003D020000 + + + 16 + 70000000870000003001000027010000 + + + + 50011 + 50011 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 4003000066000000FA0300003D020000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 50012 + 50012 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 4003000066000000FA0300003D020000 + + + 16 + 70000000870000003001000027010000 + + + + 50013 + 50013 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 4003000066000000FA0300003D020000 + + + 16 + 70000000870000003001000027010000 + + + + 50014 + 50014 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 4003000066000000FA0300003D020000 + + + 16 + 70000000870000003001000027010000 + + + + 50015 + 50015 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 4003000066000000FA0300003D020000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 50016 + 50016 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 4003000066000000FA0300003D020000 + + + 16 + 70000000870000003001000027010000 + + + + 50017 + 50017 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 4003000066000000FA0300003D020000 + + + 16 + 70000000870000003001000027010000 + + + + 50018 + 50018 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 4003000066000000FA0300003D020000 + + + 16 + 70000000870000003001000027010000 + + + + 50019 + 50019 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 4003000066000000FA0300003D020000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 59392 + 59392 + 1 + 0 + 0 + 0 + 966 + 0 + 8192 + 0 + + 16 + 0000000000000000D10300001C000000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 59393 + 0 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 00000000E603000080070000F9030000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 59399 + 59399 + 0 + 0 + 0 + 0 + 476 + 0 + 8192 + 1 + + 16 + 000000001C000000E701000038000000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 59400 + 59400 + 1 + 0 + 0 + 0 + 612 + 0 + 8192 + 2 + + 16 + 010000001C0000007002000038000000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 824 + 824 + 0 + 0 + 0 + 0 + 32767 + 0 + 16384 + 0 + + 16 + B9050000660000007D070000CD030000 + + + 16 + 4A050000AF010000490700006E040000 + + + + 3295 + 000000000A000000000000000020000001000000FFFFFFFFFFFFFFFFC400000088000000B20500008C00000001000000010000100400000001000000C9FFFFFFA7010000FFFFFFFF08000000CB00000057010000CC000000F08B00005A01000079070000D601000045890000FFFF02000B004354616262656450616E6500200000010000004408000066000000320D00009F000000C40000004F000000B2050000880000000000000040280056080000000B446973617373656D626C7901000000CB00000001000000FFFFFFFFFFFFFFFF14506572666F726D616E636520416E616C797A6572000000005701000001000000FFFFFFFFFFFFFFFF14506572666F726D616E636520416E616C797A657200000000CC00000001000000FFFFFFFFFFFFFFFF0E4C6F67696320416E616C797A657200000000F08B000001000000FFFFFFFFFFFFFFFF0D436F646520436F766572616765000000005A01000001000000FFFFFFFFFFFFFFFF11496E737472756374696F6E205472616365000000007907000001000000FFFFFFFFFFFFFFFF0F53797374656D20416E616C797A657200000000D601000001000000FFFFFFFFFFFFFFFF104576656E742053746174697374696373000000004589000001000000FFFFFFFFFFFFFFFF00000000000000000000000000000000000000000000000001000000FFFFFFFFCB00000001000000FFFFFFFFCB000000000000000040000000000000FFFFFFFFFFFFFFFF390300004F0000003D03000056020000000000000200000004000000010000000000000000000000FFFFFFFF2B000000E2050000CA0900002D8C00002E8C00002F8C0000308C0000318C0000328C0000338C0000348C0000358C0000368C0000378C0000388C0000398C00003A8C00003B8C00003C8C00003D8C00003E8C00003F8C0000408C0000418C000050C3000051C3000052C3000053C3000054C3000055C3000056C3000057C3000058C3000059C300005AC300005BC300005CC300005DC300005EC300005FC3000060C3000061C3000062C3000063C3000001800040000000000000BD0A0000660000007D0B00006D0200003D0300004F000000FD0300005602000000000000404100462B0000000753796D626F6C7300000000E205000001000000FFFFFFFFFFFFFFFF0A5472616365204461746100000000CA09000001000000FFFFFFFFFFFFFFFF00000000002D8C000001000000FFFFFFFFFFFFFFFF00000000002E8C000001000000FFFFFFFFFFFFFFFF00000000002F8C000001000000FFFFFFFFFFFFFFFF0000000000308C000001000000FFFFFFFFFFFFFFFF0000000000318C000001000000FFFFFFFFFFFFFFFF0000000000328C000001000000FFFFFFFFFFFFFFFF0000000000338C000001000000FFFFFFFFFFFFFFFF0000000000348C000001000000FFFFFFFFFFFFFFFF0000000000358C000001000000FFFFFFFFFFFFFFFF0000000000368C000001000000FFFFFFFFFFFFFFFF0000000000378C000001000000FFFFFFFFFFFFFFFF0000000000388C000001000000FFFFFFFFFFFFFFFF0000000000398C000001000000FFFFFFFFFFFFFFFF00000000003A8C000001000000FFFFFFFFFFFFFFFF00000000003B8C000001000000FFFFFFFFFFFFFFFF00000000003C8C000001000000FFFFFFFFFFFFFFFF00000000003D8C000001000000FFFFFFFFFFFFFFFF00000000003E8C000001000000FFFFFFFFFFFFFFFF00000000003F8C000001000000FFFFFFFFFFFFFFFF0000000000408C000001000000FFFFFFFFFFFFFFFF0000000000418C000001000000FFFFFFFFFFFFFFFF000000000050C3000001000000FFFFFFFFFFFFFFFF000000000051C3000001000000FFFFFFFFFFFFFFFF000000000052C3000001000000FFFFFFFFFFFFFFFF000000000053C3000001000000FFFFFFFFFFFFFFFF000000000054C3000001000000FFFFFFFFFFFFFFFF000000000055C3000001000000FFFFFFFFFFFFFFFF000000000056C3000001000000FFFFFFFFFFFFFFFF000000000057C3000001000000FFFFFFFFFFFFFFFF000000000058C3000001000000FFFFFFFFFFFFFFFF000000000059C3000001000000FFFFFFFFFFFFFFFF00000000005AC3000001000000FFFFFFFFFFFFFFFF00000000005BC3000001000000FFFFFFFFFFFFFFFF00000000005CC3000001000000FFFFFFFFFFFFFFFF00000000005DC3000001000000FFFFFFFFFFFFFFFF00000000005EC3000001000000FFFFFFFFFFFFFFFF00000000005FC3000001000000FFFFFFFFFFFFFFFF000000000060C3000001000000FFFFFFFFFFFFFFFF000000000061C3000001000000FFFFFFFFFFFFFFFF000000000062C3000001000000FFFFFFFFFFFFFFFF000000000063C3000001000000FFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000000000000000000000001000000FFFFFFFFE205000001000000FFFFFFFFE2050000000000000010000001000000FFFFFFFFFFFFFFFFC00000004F000000C40000000F030000010000000200001004000000010000000000000000000000FFFFFFFF05000000ED0300006D000000C3000000C4000000739400000180001000000100000080070000660000004008000026030000000000004F000000C00000000F0300000000000040410056050000000750726F6A65637401000000ED03000001000000FFFFFFFFFFFFFFFF05426F6F6B73000000006D00000001000000FFFFFFFFFFFFFFFF0946756E6374696F6E7300000000C300000001000000FFFFFFFFFFFFFFFF0954656D706C6174657300000000C400000001000000FFFFFFFFFFFFFFFF09526567697374657273010000007394000001000000FFFFFFFFFFFFFFFF00000000000000000000000000000000000000000000000001000000FFFFFFFFED03000001000000FFFFFFFFED030000000000000080000001000000FFFFFFFFFFFFFFFF000000000F030000B2050000130300000100000001000010040000000100000058FDFFFFA700000000000000000000000000000001000000FFFFFFFF07000000C5000000C7000000B4010000D2010000CF01000077940000C600000001800080000001000000800700002A030000320D0000FD0300000000000013030000B2050000E60300000000000040820056070000000C4275696C64204F757470757400000000C500000001000000FFFFFFFFFFFFFFFF0D46696E6420496E2046696C657301000000C700000001000000FFFFFFFFFFFFFFFF0A4572726F72204C69737400000000B401000001000000FFFFFFFFFFFFFFFF0E536F757263652042726F7773657200000000D201000001000000FFFFFFFFFFFFFFFF0E416C6C205265666572656E63657300000000CF01000001000000FFFFFFFFFFFFFFFF0642726F777365000000007794000001000000FFFFFFFFFFFFFFFF07436F6D6D616E6401000000C600000001000000FFFFFFFFFFFFFFFF0100000000000000000000000000000000000000000000000000000001000000FFFFFFFFC500000001000000FFFFFFFFC5000000000000000040000001000000FFFFFFFFFFFFFFFFB20500004F000000B6050000E603000001000000020000100400000001000000C4FCFFFFF501000000000000000000000000000001000000FFFFFFFF0F0000008F070000930700009407000095070000960700009007000091070000B5010000B801000038030000B9050000BA050000BB050000BC050000CB09000001800040000001000000360D000066000000000F0000FD030000B60500004F00000080070000E603000000000000404100560F0000001343616C6C20537461636B202B204C6F63616C73010000008F07000001000000FFFFFFFFFFFFFFFF0755415254202331000000009307000001000000FFFFFFFFFFFFFFFF0755415254202332000000009407000001000000FFFFFFFFFFFFFFFF0755415254202333000000009507000001000000FFFFFFFFFFFFFFFF15446562756720287072696E74662920566965776572000000009607000001000000FFFFFFFFFFFFFFFF0757617463682031010000009007000001000000FFFFFFFFFFFFFFFF0757617463682032010000009107000001000000FFFFFFFFFFFFFFFF10547261636520457863657074696F6E7300000000B501000001000000FFFFFFFFFFFFFFFF0E4576656E7420436F756E7465727300000000B801000001000000FFFFFFFFFFFFFFFF09554C494E4B706C7573000000003803000001000000FFFFFFFFFFFFFFFF084D656D6F7279203101000000B905000001000000FFFFFFFFFFFFFFFF084D656D6F7279203200000000BA05000001000000FFFFFFFFFFFFFFFF084D656D6F7279203300000000BB05000001000000FFFFFFFFFFFFFFFF084D656D6F7279203400000000BC05000001000000FFFFFFFFFFFFFFFF105472616365204E617669676174696F6E00000000CB09000001000000FFFFFFFFFFFFFFFF0500000000000000000000000000000000000000000000000000000001000000FFFFFFFF8F07000001000000FFFFFFFF8F070000000000000000000000000000 + + + 59392 + File + + 2917 + 00200000010000002800FFFF01001100434D4643546F6F6C426172427574746F6E00E100000000000000000000000000000000000000000000000100000001000000018001E100000000000001000000000000000000000000000000000100000001000000018003E1000000000000020000000000000000000000000000000001000000010000000180CD7F0000000000000300000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018023E100000000040004000000000000000000000000000000000100000001000000018022E100000000040005000000000000000000000000000000000100000001000000018025E10000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001802BE10000000004000700000000000000000000000000000000010000000100000001802CE10000000004000800000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001807A8A0000000000000900000000000000000000000000000000010000000100000001807B8A0000000004000A00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180D3B00000000000000B000000000000000000000000000000000100000001000000018015B10000000004000C0000000000000000000000000000000001000000010000000180F4B00000000004000D000000000000000000000000000000000100000001000000018036B10000000004000E00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FF88000000000400460000000000000000000000000000000001000000010000000180FE880000000004004500000000000000000000000000000000010000000100000001800B810000000004001300000000000000000000000000000000010000000100000001800C810000000004001400000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180F0880000020000000F000000000000000000000000000000000100000001000000FFFF0100120043555646696E64436F6D626F427574746F6EE803000000000000000000000000000000000000000000000001000000010000009600000002002050000000000E41542B434D515454544F5049433D960000000000000014000E41542B434D515454544F5049433D0747726F7761747409616C61726D4279746514616C61726D42797465207C3D203078303030323B1669662863616E4D656D5B305D2E736F63203C203939291043414E5F50726F746F636F6C5F534D410D43414E315F53656E64446174610E43414E5F557064617465446174610B74696D65645F44656C61790F4C54455F50696E5253545F466C61670AB1A8CEC4B5C4B4A6C0ED0C4964785F4361706163697479074964785F4359430F626D734D656D2E6D63755F75746372124C54455F34475F5355425F53455450415241124C54455F5265636F72645F7075624461746110696E636964656E745F44617461466C6710696E636964656E745F44617461496E6601560C73706563696669634D6F64650000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018024E10000000000001100000000000000000000000000000000010000000100000001800A810000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6E2280000002000100150000002153746172742F53746F70202644656275672053657373696F6E094374726C2B46350000000000000000000000000100000001000000000000000000000001000000020021802280000000000000150000002153746172742F53746F70202644656275672053657373696F6E094374726C2B4635000000000000000000000000010000000100000000000000000000000100000000002180E0010000000000007500000021456E65726779204D6561737572656D656E742026776974686F75742044656275670000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C488000000000000160000000000000000000000000000000001000000010000000180C988000000000400180000000000000000000000000000000001000000010000000180C788000000000000190000000000000000000000000000000001000000010000002180C8880000000000001700000027264B696C6C20416C6C20427265616B706F696E747320696E2043757272656E7420546172676574000000000000000000000000010000000100000000000000000000000100000003002180C8880000000000001700000027264B696C6C20416C6C20427265616B706F696E747320696E2043757272656E7420546172676574000000000000000000000000010000000100000000000000000000000100000000002180E50100000000000078000000264B696C6C20416C6C20427265616B706F696E747320696E204163746976652050726F6A656374000000000000000000000000010000000100000000000000000000000100000000002180E601000000000000790000002F4B696C6C20416C6C20427265616B706F696E747320696E204D756C74692D50726F6A65637420576F726B73706163650000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000021804C010000020001001A0000000F2650726F6A6563742057696E646F77000000000000000000000000010000000100000000000000000000000100000008002180DD880000000000001A0000000750726F6A656374000000000000000000000000010000000100000000000000000000000100000000002180DC8B0000000000003A00000005426F6F6B73000000000000000000000000010000000100000000000000000000000100000000002180E18B0000000000003B0000000946756E6374696F6E73000000000000000000000000010000000100000000000000000000000100000000002180E28B000000000000400000000954656D706C6174657300000000000000000000000001000000010000000000000000000000010000000000218018890000000000003D0000000E536F757263652042726F777365720000000000000000000000000100000001000000000000000000000001000000000021800000000000000400FFFFFFFF00000000000000000001000000000000000100000000000000000000000100000000002180D988000000000000390000000C4275696C64204F7574707574000000000000000000000000010000000100000000000000000000000100000000002180E38B000000000000410000000B46696E64204F75747075740000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FB7F0000000000001B000000000000000000000000000000000100000001000000000000000446696C65C6030000 + + + 1423 + 2800FFFF01001100434D4643546F6F6C426172427574746F6E00E1000000000000FFFFFFFF000100000000000000010000000000000001000000018001E1000000000000FFFFFFFF000100000000000000010000000000000001000000018003E1000000000000FFFFFFFF0001000000000000000100000000000000010000000180CD7F000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF000000000000000000010000000000000001000000018023E1000000000000FFFFFFFF000100000000000000010000000000000001000000018022E1000000000000FFFFFFFF000100000000000000010000000000000001000000018025E1000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001802BE1000000000000FFFFFFFF00010000000000000001000000000000000100000001802CE1000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001807A8A000000000000FFFFFFFF00010000000000000001000000000000000100000001807B8A000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180D3B0000000000000FFFFFFFF000100000000000000010000000000000001000000018015B1000000000000FFFFFFFF0001000000000000000100000000000000010000000180F4B0000000000000FFFFFFFF000100000000000000010000000000000001000000018036B1000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180FF88000000000000FFFFFFFF0001000000000000000100000000000000010000000180FE88000000000000FFFFFFFF00010000000000000001000000000000000100000001800B81000000000000FFFFFFFF00010000000000000001000000000000000100000001800C81000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180F088000000000000FFFFFFFF0001000000000000000100000000000000010000000180EE7F000000000000FFFFFFFF000100000000000000010000000000000001000000018024E1000000000000FFFFFFFF00010000000000000001000000000000000100000001800A81000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001802280000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180C488000000000000FFFFFFFF0001000000000000000100000000000000010000000180C988000000000000FFFFFFFF0001000000000000000100000000000000010000000180C788000000000000FFFFFFFF0001000000000000000100000000000000010000000180C888000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180DD88000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180FB7F000000000000FFFFFFFF000100000000000000010000000000000001000000 + + + 1423 + 2800FFFF01001100434D4643546F6F6C426172427574746F6E00E100000000000000000000000000000000000000000000000100000001000000018001E100000000000001000000000000000000000000000000000100000001000000018003E1000000000000020000000000000000000000000000000001000000010000000180CD7F0000000000000300000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018023E100000000000004000000000000000000000000000000000100000001000000018022E100000000000005000000000000000000000000000000000100000001000000018025E10000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001802BE10000000000000700000000000000000000000000000000010000000100000001802CE10000000000000800000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001807A8A0000000000000900000000000000000000000000000000010000000100000001807B8A0000000000000A00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180D3B00000000000000B000000000000000000000000000000000100000001000000018015B10000000000000C0000000000000000000000000000000001000000010000000180F4B00000000000000D000000000000000000000000000000000100000001000000018036B10000000000000E00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FF880000000000000F0000000000000000000000000000000001000000010000000180FE880000000000001000000000000000000000000000000000010000000100000001800B810000000000001100000000000000000000000000000000010000000100000001800C810000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180F088000000000000130000000000000000000000000000000001000000010000000180EE7F00000000000014000000000000000000000000000000000100000001000000018024E10000000000001500000000000000000000000000000000010000000100000001800A810000000000001600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018022800000000000001700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C488000000000000180000000000000000000000000000000001000000010000000180C988000000000000190000000000000000000000000000000001000000010000000180C7880000000000001A0000000000000000000000000000000001000000010000000180C8880000000000001B00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180DD880000000000001C00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FB7F0000000000001D000000000000000000000000000000000100000001000000 + + + + 59399 + Build + + 955 + 00200000000000001000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F0000000000001C0000000000000000000000000000000001000000010000000180D07F0000000000001D000000000000000000000000000000000100000001000000018030800000000000001E000000000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6EC7040000000000006A0000000C4261746368204275696C2664000000000000000000000000010000000100000000000000000000000100000004000580C7040000000000006A0000000C4261746368204275696C266400000000000000000000000001000000010000000000000000000000010000000000058046070000000000006B0000000D42617463682052656275696C640000000000000000000000000100000001000000000000000000000001000000000005804707000000000000FFFFFFFF0B426174636820436C65616E0000000000000000010000000000000001000000000000000000000001000000000005809E8A0000000000001F0000000F4261746326682053657475702E2E2E000000000000000000000000010000000100000000000000000000000100000000000180D17F0000000000002000000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001804C8A0000000000002100000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000FFFF01001900434D4643546F6F6C426172436F6D626F426F78427574746F6EBA00000000000000000000000000000000000000000000000001000000010000009600000003002050FFFFFFFF00960000000000000000000180EB880000000000002200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C07F000000000000230000000000000000000000000000000001000000010000000180B08A000000000000240000000000000000000000000000000001000000010000000180A8010000000000004E00000000000000000000000000000000010000000100000001807202000000000000530000000000000000000000000000000001000000010000000180BE010000000000005000000000000000000000000000000000010000000100000000000000054275696C64DC010000 + + + 583 + 1000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F000000000000FFFFFFFF0001000000000000000100000000000000010000000180D07F000000000000FFFFFFFF00010000000000000001000000000000000100000001803080000000000000FFFFFFFF00010000000000000001000000000000000100000001809E8A000000000000FFFFFFFF0001000000000000000100000000000000010000000180D17F000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001804C8A000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001806680000000000000FFFFFFFF0001000000000000000100000000000000010000000180EB88000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180C07F000000000000FFFFFFFF0001000000000000000100000000000000010000000180B08A000000000000FFFFFFFF0001000000000000000100000000000000010000000180A801000000000000FFFFFFFF00010000000000000001000000000000000100000001807202000000000000FFFFFFFF0001000000000000000100000000000000010000000180BE01000000000000FFFFFFFF000100000000000000010000000000000001000000 + + + 583 + 1000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F000000000000000000000000000000000000000000000001000000010000000180D07F00000000000001000000000000000000000000000000000100000001000000018030800000000000000200000000000000000000000000000000010000000100000001809E8A000000000000030000000000000000000000000000000001000000010000000180D17F0000000000000400000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001804C8A0000000000000500000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001806680000000000000060000000000000000000000000000000001000000010000000180EB880000000000000700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C07F000000000000080000000000000000000000000000000001000000010000000180B08A000000000000090000000000000000000000000000000001000000010000000180A8010000000000000A000000000000000000000000000000000100000001000000018072020000000000000B0000000000000000000000000000000001000000010000000180BE010000000000000C000000000000000000000000000000000100000001000000 + + + + 59400 + Debug + + 2362 + 00200000010000001900FFFF01001100434D4643546F6F6C426172427574746F6ECC880000000000002500000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018017800000000000002600000000000000000000000000000000010000000100000001801D800000000004002700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001801A800000000000002800000000000000000000000000000000010000000100000001801B80000000000000290000000000000000000000000000000001000000010000000180E57F0000000000002A00000000000000000000000000000000010000000100000001801C800000000000002B00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018000890000000000002C00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180E48B0000020001002D0000000000000000000000000000000001000000010000000180F07F0000020001002E0000000000000000000000000000000001000000010000000180E8880000020000003700000000000000000000000000000000010000000100000001803B010000020001002F0000000000000000000000000000000001000000010000000180BB8A00000200010030000000000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6E0E01000002000100310000000D57617463682057696E646F7773000000000000000000000000010000000100000000000000000000000100000003001380D88B00000000000031000000085761746368202631000000000000000000000000010000000100000000000000000000000100000000001380D98B00000000000031000000085761746368202632000000000000000000000000010000000100000000000000000000000100000000001380CE01000000000000FFFFFFFF0C576174636820416E63686F720000000000000000010000000000000001000000000000000000000001000000000013800F0100000200010032000000094D656D6F7279202631000000000000000000000000010000000100000000000000000000000100000004001380D28B00000000000032000000094D656D6F7279202631000000000000000000000000010000000100000000000000000000000100000000001380D38B00000000000032000000094D656D6F7279202632000000000000000000000000010000000100000000000000000000000100000000001380D48B00000000000032000000094D656D6F7279202633000000000000000000000000010000000100000000000000000000000100000000001380D58B00000000000032000000094D656D6F72792026340000000000000000000000000100000001000000000000000000000001000000000013801001000002000000330000000855415254202326310000000000000000000000000100000001000000000000000000000001000000040013809307000000000000330000000855415254202326310000000000000000000000000100000001000000000000000000000001000000000013809407000000000000330000000855415254202326320000000000000000000000000100000001000000000000000000000001000000000013809507000000000000330000000855415254202326330000000000000000000000000100000001000000000000000000000001000000000013809607000000000000330000001626446562756720287072696E746629205669657765720000000000000000000000000100000001000000000000000000000001000000000013803C010000000000007200000010416E616C797369732057696E646F7773000000000000000000000000010000000100000000000000000000000100000004001380658A000000000000340000000F264C6F67696320416E616C797A6572000000000000000000000000010000000100000000000000000000000100000000001380DC7F0000000000003E0000001526506572666F726D616E636520416E616C797A6572000000000000000000000000010000000100000000000000000000000100000000001380E788000000000000380000000E26436F646520436F766572616765000000000000000000000000010000000100000000000000000000000100000000001380CD01000000000000FFFFFFFF0F416E616C7973697320416E63686F7200000000000000000100000000000000010000000000000000000000010000000000138053010000000000003F0000000D54726163652057696E646F77730000000000000000000000000100000001000000000000000000000001000000010013805401000000000000FFFFFFFF115472616365204D656E7520416E63686F720000000000000000010000000000000001000000000000000000000001000000000013802901000000000000350000001553797374656D205669657765722057696E646F77730000000000000000000000000100000001000000000000000000000001000000010013804B01000000000000FFFFFFFF1453797374656D2056696577657220416E63686F720000000000000000010000000000000001000000000000000000000001000000000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000013800189000002000000360000000F26546F6F6C626F782057696E646F7700000000000000000000000001000000010000000000000000000000010000000300138044C5000000000000FFFFFFFF0E5570646174652057696E646F77730000000000000000010000000000000001000000000000000000000001000000000013800000000000000400FFFFFFFF000000000000000000010000000000000001000000000000000000000001000000000013805B01000000000000FFFFFFFF12546F6F6C626F78204D656E75416E63686F72000000000000000001000000000000000100000000000000000000000100000000000000000005446562756764020000 + + + 898 + 1900FFFF01001100434D4643546F6F6C426172427574746F6ECC88000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001801780000000000000FFFFFFFF00010000000000000001000000000000000100000001801D80000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001801A80000000000000FFFFFFFF00010000000000000001000000000000000100000001801B80000000000000FFFFFFFF0001000000000000000100000000000000010000000180E57F000000000000FFFFFFFF00010000000000000001000000000000000100000001801C80000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001800089000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180E48B000000000000FFFFFFFF0001000000000000000100000000000000010000000180F07F000000000000FFFFFFFF0001000000000000000100000000000000010000000180E888000000000000FFFFFFFF00010000000000000001000000000000000100000001803B01000000000000FFFFFFFF0001000000000000000100000000000000010000000180BB8A000000000000FFFFFFFF0001000000000000000100000000000000010000000180D88B000000000000FFFFFFFF0001000000000000000100000000000000010000000180D28B000000000000FFFFFFFF00010000000000000001000000000000000100000001809307000000000000FFFFFFFF0001000000000000000100000000000000010000000180658A000000000000FFFFFFFF0001000000000000000100000000000000010000000180C18A000000000000FFFFFFFF0001000000000000000100000000000000010000000180EE8B000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001800189000000000000FFFFFFFF000100000000000000010000000000000001000000 + + + 898 + 1900FFFF01001100434D4643546F6F6C426172427574746F6ECC880000000000000000000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018017800000000000000100000000000000000000000000000000010000000100000001801D800000000000000200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001801A800000000000000300000000000000000000000000000000010000000100000001801B80000000000000040000000000000000000000000000000001000000010000000180E57F0000000000000500000000000000000000000000000000010000000100000001801C800000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018000890000000000000700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180E48B000000000000080000000000000000000000000000000001000000010000000180F07F000000000000090000000000000000000000000000000001000000010000000180E8880000000000000A00000000000000000000000000000000010000000100000001803B010000000000000B0000000000000000000000000000000001000000010000000180BB8A0000000000000C0000000000000000000000000000000001000000010000000180D88B0000000000000D0000000000000000000000000000000001000000010000000180D28B0000000000000E000000000000000000000000000000000100000001000000018093070000000000000F0000000000000000000000000000000001000000010000000180658A000000000000100000000000000000000000000000000001000000010000000180C18A000000000000110000000000000000000000000000000001000000010000000180EE8B0000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180018900000000000013000000000000000000000000000000000100000001000000 + + + + 0 + 1536 + 864 + + + + + + 1 + 0 + + 100 + 1 + + ..\README\readme.txt + 0 + 5000 + 5021 + 0 + + 0 + + + ..\MOUDLE\Screen.c + 4 + 1432 + 1445 + 1 + + 0 + + + + +     diff --git a/USER/BT_BMS_V3.0.uvguix.yue b/USER/BT_BMS_V3.0.uvguix.yue new file mode 100644 index 0000000..9187adb --- /dev/null +++ b/USER/BT_BMS_V3.0.uvguix.yue @@ -0,0 +1,2001 @@ + + + + -6.1 + +
    ### uVision Project, (C) Keil Software
    + + + + + + 38003 + Registers + 140 42 + + + 346 + Code Coverage + 1058 160 + + + 204 + Performance Analyzer + 1218 + + + + + + 1506 + Symbols + + 64 64 64 + + + 1936 + Watch 1 + + 200 133 133 + + + 1937 + Watch 2 + + 200 133 133 + + + 1935 + Call Stack + Locals + + 200 133 133 + + + 2506 + Trace Data + + 75 135 130 95 70 230 200 150 + + + 466 + Source Browser + 500 + 166 + + + + + + + + 0 + 0 + 0 + 50 + 16 + + + + + + + 44 + 2 + 3 + + -32000 + -32000 + + + -1 + -1 + + + 9 + -7 + 1527 + 823 + + + + 0 + + 3881 + 010000000400000001000000010000000100000001000000000000000200000000000000010000000100000000000000280000002800000001000000120000000700000001000000AF433A5C55736572735C7975655C4465736B746F705C3230B4AE32303041CFEEC4BF5C33A1A2B2E2CAD4B4FAC2EB5C424D535F53544D33325F5B56342E302E302E305D28B4AECAFDD0B4C8EBD3C5BBAF2928B3E4B7C5B5E7B8DFCEC2BFB4D7B4CCAC2928C6C1C4BBD5DAB5B2C0FACAB7D3C5BBAF2928C6C1C4BBCAA3D3E0CAB1BCE4D3C5BBAF292832303041B2CECAFD292B5B323030323053465D2B5B56312E302E305D5C555345525C6D61696E2E6300000000066D61696E2E6300000000FFDC7800FFFFFFFFAE433A5C55736572735C7975655C4465736B746F705C3230B4AE32303041CFEEC4BF5C33A1A2B2E2CAD4B4FAC2EB5C424D535F53544D33325F5B56342E302E302E305D28B4AECAFDD0B4C8EBD3C5BBAF2928B3E4B7C5B5E7B8DFCEC2BFB4D7B4CCAC2928C6C1C4BBD5DAB5B2C0FACAB7D3C5BBAF2928C6C1C4BBCAA3D3E0CAB1BCE4D3C5BBAF292832303041B2CECAFD292B5B323030323053465D2B5B56312E302E305D5C4253505C6770696F2E6300000000066770696F2E6300000000BECEA100FFFFFFFFAD433A5C55736572735C7975655C4465736B746F705C3230B4AE32303041CFEEC4BF5C33A1A2B2E2CAD4B4FAC2EB5C424D535F53544D33325F5B56342E302E302E305D28B4AECAFDD0B4C8EBD3C5BBAF2928B3E4B7C5B5E7B8DFCEC2BFB4D7B4CCAC2928C6C1C4BBD5DAB5B2C0FACAB7D3C5BBAF2928C6C1C4BBCAA3D3E0CAB1BCE4D3C5BBAF292832303041B2CECAFD292B5B323030323053465D2B5B56312E302E305D5C4253505C6164632E6300000000056164632E6300000000F0A0A100FFFFFFFFB1433A5C55736572735C7975655C4465736B746F705C3230B4AE32303041CFEEC4BF5C33A1A2B2E2CAD4B4FAC2EB5C424D535F53544D33325F5B56342E302E302E305D28B4AECAFDD0B4C8EBD3C5BBAF2928B3E4B7C5B5E7B8DFCEC2BFB4D7B4CCAC2928C6C1C4BBD5DAB5B2C0FACAB7D3C5BBAF2928C6C1C4BBCAA3D3E0CAB1BCE4D3C5BBAF292832303041B2CECAFD292B5B323030323053465D2B5B56312E302E305D5C555345525C676C6F62616C2E680000000008676C6F62616C2E6800000000BCA8E100FFFFFFFFB3433A5C55736572735C7975655C4465736B746F705C3230B4AE32303041CFEEC4BF5C33A1A2B2E2CAD4B4FAC2EB5C424D535F53544D33325F5B56342E302E302E305D28B4AECAFDD0B4C8EBD3C5BBAF2928B3E4B7C5B5E7B8DFCEC2BFB4D7B4CCAC2928C6C1C4BBD5DAB5B2C0FACAB7D3C5BBAF2928C6C1C4BBCAA3D3E0CAB1BCE4D3C5BBAF292832303041B2CECAFD292B5B323030323053465D2B5B56312E302E305D5C4D4F55444C455C53637265656E2E63000000000853637265656E2E63000000009CC1B600FFFFFFFFAD433A5C55736572735C7975655C4465736B746F705C3230B4AE32303041CFEEC4BF5C33A1A2B2E2CAD4B4FAC2EB5C424D535F53544D33325F5B56342E302E302E305D28B4AECAFDD0B4C8EBD3C5BBAF2928B3E4B7C5B5E7B8DFCEC2BFB4D7B4CCAC2928C6C1C4BBD5DAB5B2C0FACAB7D3C5BBAF2928C6C1C4BBCAA3D3E0CAB1BCE4D3C5BBAF292832303041B2CECAFD292B5B323030323053465D2B5B56312E302E305D5C4253505C6932632E6300000000056932632E6300000000F7B88600FFFFFFFFAD433A5C55736572735C7975655C4465736B746F705C3230B4AE32303041CFEEC4BF5C33A1A2B2E2CAD4B4FAC2EB5C424D535F53544D33325F5B56342E302E302E305D28B4AECAFDD0B4C8EBD3C5BBAF2928B3E4B7C5B5E7B8DFCEC2BFB4D7B4CCAC2928C6C1C4BBD5DAB5B2C0FACAB7D3C5BBAF2928C6C1C4BBCAA3D3E0CAB1BCE4D3C5BBAF292832303041B2CECAFD292B5B323030323053465D2B5B56312E302E305D5C4253505C7370692E6300000000057370692E6300000000D9ADC200FFFFFFFFAF433A5C55736572735C7975655C4465736B746F705C3230B4AE32303041CFEEC4BF5C33A1A2B2E2CAD4B4FAC2EB5C424D535F53544D33325F5B56342E302E302E305D28B4AECAFDD0B4C8EBD3C5BBAF2928B3E4B7C5B5E7B8DFCEC2BFB4D7B4CCAC2928C6C1C4BBD5DAB5B2C0FACAB7D3C5BBAF2928C6C1C4BBCAA3D3E0CAB1BCE4D3C5BBAF292832303041B2CECAFD292B5B323030323053465D2B5B56312E302E305D5C4253505C666C6173682E630000000007666C6173682E6300000000A5C2D700FFFFFFFFB5433A5C55736572735C7975655C4465736B746F705C3230B4AE32303041CFEEC4BF5C33A1A2B2E2CAD4B4FAC2EB5C424D535F53544D33325F5B56342E302E302E305D28B4AECAFDD0B4C8EBD3C5BBAF2928B3E4B7C5B5E7B8DFCEC2BFB4D7B4CCAC2928C6C1C4BBD5DAB5B2C0FACAB7D3C5BBAF2928C6C1C4BBCAA3D3E0CAB1BCE4D3C5BBAF292832303041B2CECAFD292B5B323030323053465D2B5B56312E302E305D5C4D4F55444C455C47617347617567652E63000000000A47617347617567652E6300000000B3A6BE00FFFFFFFFB1433A5C55736572735C7975655C4465736B746F705C3230B4AE32303041CFEEC4BF5C33A1A2B2E2CAD4B4FAC2EB5C424D535F53544D33325F5B56342E302E302E305D28B4AECAFDD0B4C8EBD3C5BBAF2928B3E4B7C5B5E7B8DFCEC2BFB4D7B4CCAC2928C6C1C4BBD5DAB5B2C0FACAB7D3C5BBAF2928C6C1C4BBCAA3D3E0CAB1BCE4D3C5BBAF292832303041B2CECAFD292B5B323030323053465D2B5B56312E302E305D5C555345525C676C6F62616C2E630000000008676C6F62616C2E6300000000EAD6A300FFFFFFFFB3433A5C55736572735C7975655C4465736B746F705C3230B4AE32303041CFEEC4BF5C33A1A2B2E2CAD4B4FAC2EB5C424D535F53544D33325F5B56342E302E302E305D28B4AECAFDD0B4C8EBD3C5BBAF2928B3E4B7C5B5E7B8DFCEC2BFB4D7B4CCAC2928C6C1C4BBD5DAB5B2C0FACAB7D3C5BBAF2928C6C1C4BBCAA3D3E0CAB1BCE4D3C5BBAF292832303041B2CECAFD292B5B323030323053465D2B5B56312E302E305D5C4D4F55444C455C5374617475732E6300000000085374617475732E6300000000F6FA7D00FFFFFFFFB3433A5C55736572735C7975655C4465736B746F705C3230B4AE32303041CFEEC4BF5C33A1A2B2E2CAD4B4FAC2EB5C424D535F53544D33325F5B56342E302E302E305D28B4AECAFDD0B4C8EBD3C5BBAF2928B3E4B7C5B5E7B8DFCEC2BFB4D7B4CCAC2928C6C1C4BBD5DAB5B2C0FACAB7D3C5BBAF2928C6C1C4BBCAA3D3E0CAB1BCE4D3C5BBAF292832303041B2CECAFD292B5B323030323053465D2B5B56312E302E305D5C4D4F55444C455C4837363930432E6300000000084837363930432E6300000000B5E99D00FFFFFFFFBA433A5C55736572735C7975655C4465736B746F705C3230B4AE32303041CFEEC4BF5C33A1A2B2E2CAD4B4FAC2EB5C424D535F53544D33325F5B56342E302E302E305D28B4AECAFDD0B4C8EBD3C5BBAF2928B3E4B7C5B5E7B8DFCEC2BFB4D7B4CCAC2928C6C1C4BBD5DAB5B2C0FACAB7D3C5BBAF2928C6C1C4BBCAA3D3E0CAB1BCE4D3C5BBAF292832303041B2CECAFD292B5B323030323053465D2B5B56312E302E305D5C4D4F55444C455C4146455F5348333637333532302E63000000000F4146455F5348333637333532302E63000000005FC3CF00FFFFFFFFBA433A5C55736572735C7975655C4465736B746F705C3230B4AE32303041CFEEC4BF5C33A1A2B2E2CAD4B4FAC2EB5C424D535F53544D33325F5B56342E302E302E305D28B4AECAFDD0B4C8EBD3C5BBAF2928B3E4B7C5B5E7B8DFCEC2BFB4D7B4CCAC2928C6C1C4BBD5DAB5B2C0FACAB7D3C5BBAF2928C6C1C4BBCAA3D3E0CAB1BCE4D3C5BBAF292832303041B2CECAFD292B5B323030323053465D2B5B56312E302E305D5C4D4F55444C455C4146455F5348333637333532302E68000000000F4146455F5348333637333532302E6800000000C1838300FFFFFFFFC0433A5C55736572735C7975655C4465736B746F705C3230B4AE32303041CFEEC4BF5C33A1A2B2E2CAD4B4FAC2EB5C424D535F53544D33325F5B56342E302E302E305D28B4AECAFDD0B4C8EBD3C5BBAF2928B3E4B7C5B5E7B8DFCEC2BFB4D7B4CCAC2928C6C1C4BBD5DAB5B2C0FACAB7D3C5BBAF2928C6C1C4BBCAA3D3E0CAB1BCE4D3C5BBAF292832303041B2CECAFD292B5B323030323053465D2B5B56312E302E305D5C50524F544F434F4C5C50726F746F636F6C5377697463685F50322E63000000001350726F746F636F6C5377697463685F50322E6300000000CACAD500FFFFFFFFC2433A5C55736572735C7975655C4465736B746F705C3230B4AE32303041CFEEC4BF5C33A1A2B2E2CAD4B4FAC2EB5C424D535F53544D33325F5B56342E302E302E305D28B4AECAFDD0B4C8EBD3C5BBAF2928B3E4B7C5B5E7B8DFCEC2BFB4D7B4CCAC2928C6C1C4BBD5DAB5B2C0FACAB7D3C5BBAF2928C6C1C4BBCAA3D3E0CAB1BCE4D3C5BBAF292832303041B2CECAFD292B5B323030323053465D2B5B56312E302E305D5C4D4F55444C455C52533438355F4D6F646275735F496E7665727465722E63000000001752533438355F4D6F646275735F496E7665727465722E6300000000C5D4F200FFFFFFFFAD433A5C55736572735C7975655C4465736B746F705C3230B4AE32303041CFEEC4BF5C33A1A2B2E2CAD4B4FAC2EB5C424D535F53544D33325F5B56342E302E302E305D28B4AECAFDD0B4C8EBD3C5BBAF2928B3E4B7C5B5E7B8DFCEC2BFB4D7B4CCAC2928C6C1C4BBD5DAB5B2C0FACAB7D3C5BBAF2928C6C1C4BBCAA3D3E0CAB1BCE4D3C5BBAF292832303041B2CECAFD292B5B323030323053465D2B5B56312E302E305D5C4253505C63616E2E63000000000563616E2E6300000000FFDC7800FFFFFFFFAD433A5C55736572735C7975655C4465736B746F705C3230B4AE32303041CFEEC4BF5C33A1A2B2E2CAD4B4FAC2EB5C424D535F53544D33325F5B56342E302E302E305D28B4AECAFDD0B4C8EBD3C5BBAF2928B3E4B7C5B5E7B8DFCEC2BFB4D7B4CCAC2928C6C1C4BBD5DAB5B2C0FACAB7D3C5BBAF2928C6C1C4BBCAA3D3E0CAB1BCE4D3C5BBAF292832303041B2CECAFD292B5B323030323053465D2B5B56312E302E305D5C4253505C70776D2E63000000000570776D2E6300000000BECEA100FFFFFFFF0100000010000000C5D4F200FFDC7800BECEA100F0A0A100BCA8E1009CC1B600F7B88600D9ADC200A5C2D700B3A6BE00EAD6A300F6FA7D00B5E99D005FC3CF00C1838300CACAD500010000000000000002000000C400000066000000000600008B020000 + + + + 0 + Build + + -1 + -1 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + C40000004F00000090050000DD000000 + + + 16 + A2070000390000006A0A0000C7000000 + + + + 1005 + 1005 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000066000000BD0000005B020000 + + + 16 + A20700003900000062080000D7000000 + + + + 109 + 109 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000066000000BD0000005B020000 + + + 16 + A207000039000000BE08000071020000 + + + + 1465 + 1465 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 000000002502000090050000B3020000 + + + 16 + A2070000390000006A0A0000C7000000 + + + + 1466 + 1466 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000280200008D05000086020000 + + + 16 + A2070000390000006A0A0000C7000000 + + + + 1467 + 1467 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000280200008D05000086020000 + + + 16 + A2070000390000006A0A0000C7000000 + + + + 1468 + 1468 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000280200008D05000086020000 + + + 16 + A2070000390000006A0A0000C7000000 + + + + 1506 + 1506 + 0 + 0 + 0 + 0 + 32767 + 0 + 16384 + 0 + + 16 + D3040000660000008D050000D4000000 + + + 16 + A20700003900000062080000D7000000 + + + + 1913 + 1913 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + C40000006300000090050000DD000000 + + + 16 + A2070000390000006A0A0000C7000000 + + + + 1935 + 1935 + 0 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 03000000280200008D0500009A020000 + + + 16 + A20700003900000062080000D7000000 + + + + 1936 + 1936 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000280200008D05000086020000 + + + 16 + A20700003900000062080000D7000000 + + + + 1937 + 1937 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000280200008D05000086020000 + + + 16 + A20700003900000062080000D7000000 + + + + 1939 + 1939 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000280200008D05000086020000 + + + 16 + A2070000390000006A0A0000C7000000 + + + + 1940 + 1940 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000280200008D05000086020000 + + + 16 + A2070000390000006A0A0000C7000000 + + + + 1941 + 1941 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000280200008D05000086020000 + + + 16 + A2070000390000006A0A0000C7000000 + + + + 1942 + 1942 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000280200008D05000086020000 + + + 16 + A2070000390000006A0A0000C7000000 + + + + 195 + 195 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000066000000BD0000005B020000 + + + 16 + A207000039000000BE08000071020000 + + + + 196 + 196 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000066000000BD0000005B020000 + + + 16 + A207000039000000BE08000071020000 + + + + 197 + 197 + 1 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 000000008C0200000006000006030000 + + + 16 + A2070000390000006A0A0000C7000000 + + + + 198 + 198 + 0 + 0 + 0 + 0 + 32767 + 0 + 32768 + 0 + + 16 + 000000001102000090050000B3020000 + + + 16 + A2070000390000006A0A0000C7000000 + + + + 199 + 199 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 030000008F0200008D050000ED020000 + + + 16 + A2070000390000006A0A0000C7000000 + + + + 203 + 203 + 0 + 0 + 0 + 0 + 32767 + 0 + 8192 + 0 + + 16 + C40000006300000090050000DD000000 + + + 16 + A2070000390000006A0A0000C7000000 + + + + 204 + 204 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + C7000000660000008D050000C4000000 + + + 16 + A2070000390000006A0A0000C7000000 + + + + 221 + 221 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 00000000000000000000000000000000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 2506 + 2506 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + D0040000630000009005000021020000 + + + 16 + A20700003900000062080000D7000000 + + + + 2507 + 2507 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000280200008D05000086020000 + + + 16 + A2070000390000006A0A0000C7000000 + + + + 343 + 343 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + C7000000660000008D050000C4000000 + + + 16 + A2070000390000006A0A0000C7000000 + + + + 346 + 346 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + C7000000660000008D050000C4000000 + + + 16 + A2070000390000006A0A0000C7000000 + + + + 35824 + 35824 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + C7000000660000008D050000C4000000 + + + 16 + A2070000390000006A0A0000C7000000 + + + + 35885 + 35885 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + D3040000660000008D05000076010000 + + + 16 + A20700003900000062080000D7000000 + + + + 35886 + 35886 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + D3040000660000008D05000076010000 + + + 16 + A20700003900000062080000D7000000 + + + + 35887 + 35887 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + D3040000660000008D05000076010000 + + + 16 + A20700003900000062080000D7000000 + + + + 35888 + 35888 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + D3040000660000008D05000076010000 + + + 16 + A20700003900000062080000D7000000 + + + + 35889 + 35889 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + D3040000660000008D05000076010000 + + + 16 + A20700003900000062080000D7000000 + + + + 35890 + 35890 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + D3040000660000008D05000076010000 + + + 16 + A20700003900000062080000D7000000 + + + + 35891 + 35891 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + D3040000660000008D05000076010000 + + + 16 + A20700003900000062080000D7000000 + + + + 35892 + 35892 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + D3040000660000008D05000076010000 + + + 16 + A20700003900000062080000D7000000 + + + + 35893 + 35893 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + D3040000660000008D05000076010000 + + + 16 + A20700003900000062080000D7000000 + + + + 35894 + 35894 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + D3040000660000008D05000076010000 + + + 16 + A20700003900000062080000D7000000 + + + + 35895 + 35895 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + D3040000660000008D05000076010000 + + + 16 + A20700003900000062080000D7000000 + + + + 35896 + 35896 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + D3040000660000008D05000076010000 + + + 16 + A20700003900000062080000D7000000 + + + + 35897 + 35897 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + D3040000660000008D05000076010000 + + + 16 + A20700003900000062080000D7000000 + + + + 35898 + 35898 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + D3040000660000008D05000076010000 + + + 16 + A20700003900000062080000D7000000 + + + + 35899 + 35899 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + D3040000660000008D05000076010000 + + + 16 + A20700003900000062080000D7000000 + + + + 35900 + 35900 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + D3040000660000008D05000076010000 + + + 16 + A20700003900000062080000D7000000 + + + + 35901 + 35901 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + D3040000660000008D05000076010000 + + + 16 + A20700003900000062080000D7000000 + + + + 35902 + 35902 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + D3040000660000008D05000076010000 + + + 16 + A20700003900000062080000D7000000 + + + + 35903 + 35903 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + D3040000660000008D05000076010000 + + + 16 + A20700003900000062080000D7000000 + + + + 35904 + 35904 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + D3040000660000008D05000076010000 + + + 16 + A20700003900000062080000D7000000 + + + + 35905 + 35905 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + D3040000660000008D05000076010000 + + + 16 + A20700003900000062080000D7000000 + + + + 38003 + 38003 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0300000066000000BD0000009A020000 + + + 16 + A207000039000000BE08000071020000 + + + + 38007 + 38007 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 000000008C0200009005000006030000 + + + 16 + A2070000390000006A0A0000C7000000 + + + + 436 + 436 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 030000008F0200008D050000ED020000 + + + 16 + A207000039000000BE08000071020000 + + + + 437 + 437 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000280200008D05000086020000 + + + 16 + A20700003900000062080000D7000000 + + + + 440 + 440 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000280200008D05000086020000 + + + 16 + A20700003900000062080000D7000000 + + + + 463 + 463 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 030000008F0200008D050000ED020000 + + + 16 + A207000039000000BE08000071020000 + + + + 466 + 466 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 030000008F0200008D050000ED020000 + + + 16 + A207000039000000BE08000071020000 + + + + 470 + 470 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 0000000025020000900500009F020000 + + + 16 + A2070000390000006A0A0000C7000000 + + + + 50000 + 50000 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + D3040000660000008D05000076010000 + + + 16 + A20700003900000062080000D7000000 + + + + 50001 + 50001 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + D3040000660000008D05000076010000 + + + 16 + A20700003900000062080000D7000000 + + + + 50002 + 50002 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + D3040000660000008D05000076010000 + + + 16 + A20700003900000062080000D7000000 + + + + 50003 + 50003 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + D3040000660000008D05000076010000 + + + 16 + A20700003900000062080000D7000000 + + + + 50004 + 50004 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + D3040000660000008D05000076010000 + + + 16 + A20700003900000062080000D7000000 + + + + 50005 + 50005 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + D3040000660000008D05000076010000 + + + 16 + A20700003900000062080000D7000000 + + + + 50006 + 50006 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + D3040000660000008D05000076010000 + + + 16 + A20700003900000062080000D7000000 + + + + 50007 + 50007 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + D3040000660000008D05000076010000 + + + 16 + A20700003900000062080000D7000000 + + + + 50008 + 50008 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + D3040000660000008D05000076010000 + + + 16 + A20700003900000062080000D7000000 + + + + 50009 + 50009 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + D3040000660000008D05000076010000 + + + 16 + A20700003900000062080000D7000000 + + + + 50010 + 50010 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + D3040000660000008D05000076010000 + + + 16 + A20700003900000062080000D7000000 + + + + 50011 + 50011 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + D3040000660000008D05000076010000 + + + 16 + A20700003900000062080000D7000000 + + + + 50012 + 50012 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + D3040000660000008D05000076010000 + + + 16 + A20700003900000062080000D7000000 + + + + 50013 + 50013 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + D3040000660000008D05000076010000 + + + 16 + A20700003900000062080000D7000000 + + + + 50014 + 50014 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + D3040000660000008D05000076010000 + + + 16 + A20700003900000062080000D7000000 + + + + 50015 + 50015 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + D3040000660000008D05000076010000 + + + 16 + A20700003900000062080000D7000000 + + + + 50016 + 50016 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + D3040000660000008D05000076010000 + + + 16 + A20700003900000062080000D7000000 + + + + 50017 + 50017 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + D3040000660000008D05000076010000 + + + 16 + A20700003900000062080000D7000000 + + + + 50018 + 50018 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + D3040000660000008D05000076010000 + + + 16 + A20700003900000062080000D7000000 + + + + 50019 + 50019 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + D3040000660000008D05000076010000 + + + 16 + A20700003900000062080000D7000000 + + + + 59392 + 59392 + 1 + 0 + 0 + 0 + 32767 + 0 + 8192 + 0 + + 16 + 0000000000000000B70300001C000000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 59393 + 0 + 1 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 00000000060300000006000019030000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 59399 + 59399 + 1 + 0 + 0 + 0 + 32767 + 0 + 8192 + 1 + + 16 + 000000001C000000E701000038000000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 59400 + 59400 + 0 + 0 + 0 + 0 + 32767 + 0 + 8192 + 2 + + 16 + 00000000380000006F02000054000000 + + + 16 + 0A0000000A0000006E0000006E000000 + + + + 824 + 824 + 0 + 0 + 0 + 0 + 32767 + 0 + 4096 + 0 + + 16 + 03000000280200008D05000086020000 + + + 16 + A20700003900000062080000D7000000 + + + + 3276 + 000000000B000000000000000020000000000000FFFFFFFFFFFFFFFFC4000000DD00000090050000E1000000000000000100001004000000010000000000000000000000FFFFFFFF06000000CB00000057010000CC000000F08B00005A01000079070000FFFF02000B004354616262656450616E650020000000000000A2070000390000006A0A0000C7000000C40000004F00000090050000DD0000000000000040280046060000000B446973617373656D626C7900000000CB00000001000000FFFFFFFFFFFFFFFF14506572666F726D616E636520416E616C797A6572000000005701000001000000FFFFFFFFFFFFFFFF14506572666F726D616E636520416E616C797A657200000000CC00000001000000FFFFFFFFFFFFFFFF0E4C6F67696320416E616C797A657200000000F08B000001000000FFFFFFFFFFFFFFFF0D436F646520436F766572616765000000005A01000001000000FFFFFFFFFFFFFFFF11496E737472756374696F6E205472616365000000007907000001000000FFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000000000000000000000001000000FFFFFFFFCB00000001000000FFFFFFFFCB000000000000000040000000000000FFFFFFFFFFFFFFFFCC0400004F000000D004000021020000000000000200001004000000010000000000000000000000FFFFFFFF2B000000E2050000CA0900002D8C00002E8C00002F8C0000308C0000318C0000328C0000338C0000348C0000358C0000368C0000378C0000388C0000398C00003A8C00003B8C00003C8C00003D8C00003E8C00003F8C0000408C0000418C000050C3000051C3000052C3000053C3000054C3000055C3000056C3000057C3000058C3000059C300005AC300005BC300005CC300005DC300005EC300005FC3000060C3000061C3000062C3000063C3000001800040000000000000A20700003900000062080000D7000000D00400004F000000900500002102000000000000404100462B0000000753796D626F6C7300000000E205000001000000FFFFFFFFFFFFFFFF0A5472616365204461746100000000CA09000001000000FFFFFFFFFFFFFFFF00000000002D8C000001000000FFFFFFFFFFFFFFFF00000000002E8C000001000000FFFFFFFFFFFFFFFF00000000002F8C000001000000FFFFFFFFFFFFFFFF0000000000308C000001000000FFFFFFFFFFFFFFFF0000000000318C000001000000FFFFFFFFFFFFFFFF0000000000328C000001000000FFFFFFFFFFFFFFFF0000000000338C000001000000FFFFFFFFFFFFFFFF0000000000348C000001000000FFFFFFFFFFFFFFFF0000000000358C000001000000FFFFFFFFFFFFFFFF0000000000368C000001000000FFFFFFFFFFFFFFFF0000000000378C000001000000FFFFFFFFFFFFFFFF0000000000388C000001000000FFFFFFFFFFFFFFFF0000000000398C000001000000FFFFFFFFFFFFFFFF00000000003A8C000001000000FFFFFFFFFFFFFFFF00000000003B8C000001000000FFFFFFFFFFFFFFFF00000000003C8C000001000000FFFFFFFFFFFFFFFF00000000003D8C000001000000FFFFFFFFFFFFFFFF00000000003E8C000001000000FFFFFFFFFFFFFFFF00000000003F8C000001000000FFFFFFFFFFFFFFFF0000000000408C000001000000FFFFFFFFFFFFFFFF0000000000418C000001000000FFFFFFFFFFFFFFFF000000000050C3000001000000FFFFFFFFFFFFFFFF000000000051C3000001000000FFFFFFFFFFFFFFFF000000000052C3000001000000FFFFFFFFFFFFFFFF000000000053C3000001000000FFFFFFFFFFFFFFFF000000000054C3000001000000FFFFFFFFFFFFFFFF000000000055C3000001000000FFFFFFFFFFFFFFFF000000000056C3000001000000FFFFFFFFFFFFFFFF000000000057C3000001000000FFFFFFFFFFFFFFFF000000000058C3000001000000FFFFFFFFFFFFFFFF000000000059C3000001000000FFFFFFFFFFFFFFFF00000000005AC3000001000000FFFFFFFFFFFFFFFF00000000005BC3000001000000FFFFFFFFFFFFFFFF00000000005CC3000001000000FFFFFFFFFFFFFFFF00000000005DC3000001000000FFFFFFFFFFFFFFFF00000000005EC3000001000000FFFFFFFFFFFFFFFF00000000005FC3000001000000FFFFFFFFFFFFFFFF000000000060C3000001000000FFFFFFFFFFFFFFFF000000000061C3000001000000FFFFFFFFFFFFFFFF000000000062C3000001000000FFFFFFFFFFFFFFFF000000000063C3000001000000FFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000000000000000000000001000000FFFFFFFFE205000001000000FFFFFFFFE2050000000000000010000001000000FFFFFFFFFFFFFFFFC00000004F000000C400000074020000010000000200001004000000010000000000000000000000FFFFFFFF05000000ED0300006D000000C3000000C40000007394000001800010000001000000A20700003900000062080000D7000000000000004F000000C0000000740200000000000040410056050000000750726F6A65637401000000ED03000001000000FFFFFFFFFFFFFFFF05426F6F6B73010000006D00000001000000FFFFFFFFFFFFFFFF0946756E6374696F6E7301000000C300000001000000FFFFFFFFFFFFFFFF0954656D706C6174657301000000C400000001000000FFFFFFFFFFFFFFFF09526567697374657273000000007394000001000000FFFFFFFFFFFFFFFF00000000000000000000000000000000000000000000000001000000FFFFFFFFED03000001000000FFFFFFFFED030000000000000080000000000000FFFFFFFFFFFFFFFF000000000D020000900500001102000000000000010000100400000001000000000000000000000000000000000000000000000001000000C6000000FFFFFFFF100000008F070000930700009407000095070000960700009007000091070000B5010000B801000038030000B9050000BA050000BB050000BC050000CB090000D601000001800080000000000000A20700003900000062080000D7000000000000001102000090050000B30200000000000040410046100000001343616C6C20537461636B202B204C6F63616C73000000008F07000001000000FFFFFFFFFFFFFFFF0755415254202331000000009307000001000000FFFFFFFFFFFFFFFF0755415254202332000000009407000001000000FFFFFFFFFFFFFFFF0755415254202333000000009507000001000000FFFFFFFFFFFFFFFF15446562756720287072696E74662920566965776572000000009607000001000000FFFFFFFFFFFFFFFF0757617463682031000000009007000001000000FFFFFFFFFFFFFFFF0757617463682032000000009107000001000000FFFFFFFFFFFFFFFF10547261636520457863657074696F6E7300000000B501000001000000FFFFFFFFFFFFFFFF0E4576656E7420436F756E7465727300000000B801000001000000FFFFFFFFFFFFFFFF09554C494E4B706C7573000000003803000001000000FFFFFFFFFFFFFFFF084D656D6F7279203100000000B905000001000000FFFFFFFFFFFFFFFF084D656D6F7279203200000000BA05000001000000FFFFFFFFFFFFFFFF084D656D6F7279203300000000BB05000001000000FFFFFFFFFFFFFFFF084D656D6F7279203400000000BC05000001000000FFFFFFFFFFFFFFFF105472616365204E617669676174696F6E00000000CB09000001000000FFFFFFFFFFFFFFFF0F53797374656D20416E616C797A657200000000D601000001000000FFFFFFFFFFFFFFFFFFFFFFFF0000000001000000000000000000000001000000FFFFFFFFC802000011020000CC020000B302000000000000020000000400000000000000000000000000000000000000000000000000000002000000C6000000FFFFFFFF8F07000001000000FFFFFFFF8F07000001000000C6000000000000000080000001000000FFFFFFFFFFFFFFFF00000000740200000006000078020000010000000100001004000000010000000000000000000000FFFFFFFF06000000C5000000C7000000B4010000D2010000CF0100007794000001800080000001000000A2070000390000006A0A0000C7000000000000007802000000060000060300000000000040820056060000000C4275696C64204F757470757401000000C500000001000000FFFFFFFFFFFFFFFF0D46696E6420496E2046696C657300000000C700000001000000FFFFFFFFFFFFFFFF0A4572726F72204C69737400000000B401000001000000FFFFFFFFFFFFFFFF0E536F757263652042726F7773657200000000D201000001000000FFFFFFFFFFFFFFFF1346696E6420416C6C205265666572656E63657300000000CF01000001000000FFFFFFFFFFFFFFFF0742726F77736572000000007794000001000000FFFFFFFFFFFFFFFF00000000000000000000000000000000000000000000000001000000FFFFFFFFC500000001000000FFFFFFFFC5000000000000000000000000000000 + + + 59392 + File + + 2356 + 00200000010000002800FFFF01001100434D4643546F6F6C426172427574746F6E00E100000000000000000000000000000000000000000000000100000001000000018001E100000000000001000000000000000000000000000000000100000001000000018003E1000000000000020000000000000000000000000000000001000000010000000180CD7F0000000000000300000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018023E100000000040004000000000000000000000000000000000100000001000000018022E100000000040005000000000000000000000000000000000100000001000000018025E10000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001802BE10000000004000700000000000000000000000000000000010000000100000001802CE10000000004000800000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001807A8A0000000000000900000000000000000000000000000000010000000100000001807B8A0000000004000A00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180D3B00000000000000B000000000000000000000000000000000100000001000000018015B10000000004000C0000000000000000000000000000000001000000010000000180F4B00000000004000D000000000000000000000000000000000100000001000000018036B10000000004000E00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FF88000000000400460000000000000000000000000000000001000000010000000180FE880000000004004500000000000000000000000000000000010000000100000001800B810000000004001300000000000000000000000000000000010000000100000001800C810000000004001400000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180F0880000020000000F000000000000000000000000000000000100000001000000FFFF0100120043555646696E64436F6D626F427574746F6EE803000000000000000000000000000000000000000000000001000000010000009600000002002050000000000D4D5154545F5253545F666C6167960000000000000013000D4D5154545F5253545F666C61670D4C54455F4C494E4B5F666C616708424C455F436F6E6E0C4146455F4D756C7469706C650773635F6D6F64650D73635F636C6F73655F666C6167076473674374726C074941505F52756E13547269676765725F6166655450726F746563740B44495F54494D5F4D6F6E690E4348475F4C494D49545F4374726C0A4348475F4C494D49545F11E8AEA1E7AE97E69C80E9AB98E69C80E4BD12E8AEA1E7AE97E69C80E9AB98E69C80E4BD3F12E58699E585A5E695B0E68DAEE5A4B1E8B4A5104146455F416C61726D50726F63657373124146455F50726F7465637450726F636573730C5245475F414444525F4F54430D5245475F414444525F4F54435200000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000018024E10000000000001100000000000000000000000000000000010000000100000001800A810000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018022800000020000001500000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C488000000000000160000000000000000000000000000000001000000010000000180C988000000000400180000000000000000000000000000000001000000010000000180C788000000000000190000000000000000000000000000000001000000010000000180C8880000000000001700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6E4C010000020001001A0000000F2650726F6A6563742057696E646F77000000000000000000000000010000000100000000000000000000000100000008002880DD880000000000001A0000000750726F6A656374000000000000000000000000010000000100000000000000000000000100000000002880DC8B0000000000003A00000005426F6F6B73000000000000000000000000010000000100000000000000000000000100000000002880E18B0000000000003B0000000946756E6374696F6E73000000000000000000000000010000000100000000000000000000000100000000002880E28B000000000000400000000954656D706C6174657300000000000000000000000001000000010000000000000000000000010000000000288018890000000000003D0000000E536F757263652042726F777365720000000000000000000000000100000001000000000000000000000001000000000028800000000000000400FFFFFFFF00000000000000000000000000010000000100000000000000000000000100000000002880D988000000000000390000000C4275696C64204F7574707574000000000000000000000000010000000100000000000000000000000100000000002880E38B000000000000410000000B46696E64204F75747075740000000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FB7F0000000000001B000000000000000000000000000000000100000001000000000000000446696C65FF7F0000 + + + 1423 + 2800FFFF01001100434D4643546F6F6C426172427574746F6E00E1000000000000FFFFFFFF000100000000000000010000000000000001000000018001E1000000000000FFFFFFFF000100000000000000010000000000000001000000018003E1000000000000FFFFFFFF0001000000000000000100000000000000010000000180CD7F000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF000000000000000000010000000000000001000000018023E1000000000000FFFFFFFF000100000000000000010000000000000001000000018022E1000000000000FFFFFFFF000100000000000000010000000000000001000000018025E1000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001802BE1000000000000FFFFFFFF00010000000000000001000000000000000100000001802CE1000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001807A8A000000000000FFFFFFFF00010000000000000001000000000000000100000001807B8A000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180D3B0000000000000FFFFFFFF000100000000000000010000000000000001000000018015B1000000000000FFFFFFFF0001000000000000000100000000000000010000000180F4B0000000000000FFFFFFFF000100000000000000010000000000000001000000018036B1000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180FF88000000000000FFFFFFFF0001000000000000000100000000000000010000000180FE88000000000000FFFFFFFF00010000000000000001000000000000000100000001800B81000000000000FFFFFFFF00010000000000000001000000000000000100000001800C81000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180F088000000000000FFFFFFFF0001000000000000000100000000000000010000000180EE7F000000000000FFFFFFFF000100000000000000010000000000000001000000018024E1000000000000FFFFFFFF00010000000000000001000000000000000100000001800A81000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001802280000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180C488000000000000FFFFFFFF0001000000000000000100000000000000010000000180C988000000000000FFFFFFFF0001000000000000000100000000000000010000000180C788000000000000FFFFFFFF0001000000000000000100000000000000010000000180C888000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180DD88000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180FB7F000000000000FFFFFFFF000100000000000000010000000000000001000000 + + + 1423 + 2800FFFF01001100434D4643546F6F6C426172427574746F6E00E100000000000000000000000000000000000000000000000100000001000000018001E100000000000001000000000000000000000000000000000100000001000000018003E1000000000000020000000000000000000000000000000001000000010000000180CD7F0000000000000300000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018023E100000000000004000000000000000000000000000000000100000001000000018022E100000000000005000000000000000000000000000000000100000001000000018025E10000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001802BE10000000000000700000000000000000000000000000000010000000100000001802CE10000000000000800000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001807A8A0000000000000900000000000000000000000000000000010000000100000001807B8A0000000000000A00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180D3B00000000000000B000000000000000000000000000000000100000001000000018015B10000000000000C0000000000000000000000000000000001000000010000000180F4B00000000000000D000000000000000000000000000000000100000001000000018036B10000000000000E00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FF880000000000000F0000000000000000000000000000000001000000010000000180FE880000000000001000000000000000000000000000000000010000000100000001800B810000000000001100000000000000000000000000000000010000000100000001800C810000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180F088000000000000130000000000000000000000000000000001000000010000000180EE7F00000000000014000000000000000000000000000000000100000001000000018024E10000000000001500000000000000000000000000000000010000000100000001800A810000000000001600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018022800000000000001700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C488000000000000180000000000000000000000000000000001000000010000000180C988000000000000190000000000000000000000000000000001000000010000000180C7880000000000001A0000000000000000000000000000000001000000010000000180C8880000000000001B00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180DD880000000000001C00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180FB7F0000000000001D000000000000000000000000000000000100000001000000 + + + + 59399 + Build + + 976 + 00200000010000001000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F0000000000001C0000000000000000000000000000000001000000010000000180D07F0000000000001D000000000000000000000000000000000100000001000000018030800000000000001E000000000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6EC7040000000000006A0000000C4261746368204275696C2664000000000000000000000000010000000100000000000000000000000100000004000580C7040000000000006A0000000C4261746368204275696C266400000000000000000000000001000000010000000000000000000000010000000000058046070000000000006B0000000D42617463682052656275696C640000000000000000000000000100000001000000000000000000000001000000000005804707000000000000FFFFFFFF0B426174636820436C65616E0100000000000000000000000100000001000000000000000000000001000000000005809E8A0000000000001F0000000F4261746326682053657475702E2E2E000000000000000000000000010000000100000000000000000000000100000000000180D17F0000000004002000000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001804C8A0000000000002100000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000FFFF01001900434D4643546F6F6C426172436F6D626F426F78427574746F6EBA000000000000000000000000000000000000000000000000010000000100000096000000030020500000000008546172676574203196000000000000000100085461726765742031000000000180EB880000000000002200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C07F000000000000230000000000000000000000000000000001000000010000000180B08A000000000400240000000000000000000000000000000001000000010000000180A8010000000000004E00000000000000000000000000000000010000000100000001807202000000000000530000000000000000000000000000000001000000010000000180BE010000000000005000000000000000000000000000000000010000000100000000000000054275696C64FF7F0000 + + + 583 + 1000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F000000000000FFFFFFFF0001000000000000000100000000000000010000000180D07F000000000000FFFFFFFF00010000000000000001000000000000000100000001803080000000000000FFFFFFFF00010000000000000001000000000000000100000001809E8A000000000000FFFFFFFF0001000000000000000100000000000000010000000180D17F000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001804C8A000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001806680000000000000FFFFFFFF0001000000000000000100000000000000010000000180EB88000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180C07F000000000000FFFFFFFF0001000000000000000100000000000000010000000180B08A000000000000FFFFFFFF0001000000000000000100000000000000010000000180A801000000000000FFFFFFFF00010000000000000001000000000000000100000001807202000000000000FFFFFFFF0001000000000000000100000000000000010000000180BE01000000000000FFFFFFFF000100000000000000010000000000000001000000 + + + 583 + 1000FFFF01001100434D4643546F6F6C426172427574746F6ECF7F000000000000000000000000000000000000000000000001000000010000000180D07F00000000000001000000000000000000000000000000000100000001000000018030800000000000000200000000000000000000000000000000010000000100000001809E8A000000000000030000000000000000000000000000000001000000010000000180D17F0000000000000400000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001804C8A0000000000000500000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001806680000000000000060000000000000000000000000000000001000000010000000180EB880000000000000700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180C07F000000000000080000000000000000000000000000000001000000010000000180B08A000000000000090000000000000000000000000000000001000000010000000180A8010000000000000A000000000000000000000000000000000100000001000000018072020000000000000B0000000000000000000000000000000001000000010000000180BE010000000000000C000000000000000000000000000000000100000001000000 + + + + 59400 + Debug + + 2373 + 00200000000000001900FFFF01001100434D4643546F6F6C426172427574746F6ECC880000000000002500000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018017800000000000002600000000000000000000000000000000010000000100000001801D800000000000002700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001801A800000000000002800000000000000000000000000000000010000000100000001801B80000000000000290000000000000000000000000000000001000000010000000180E57F0000000000002A00000000000000000000000000000000010000000100000001801C800000000000002B00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018000890000000000002C00000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180E48B0000000000002D0000000000000000000000000000000001000000010000000180F07F0000000000002E0000000000000000000000000000000001000000010000000180E8880000000000003700000000000000000000000000000000010000000100000001803B010000000000002F0000000000000000000000000000000001000000010000000180BB8A00000000000030000000000000000000000000000000000100000001000000FFFF01001500434D4643546F6F6C4261724D656E75427574746F6E0E01000000000000310000000D57617463682057696E646F7773000000000000000000000000010000000100000000000000000000000100000003001380D88B00000000000031000000085761746368202631000000000000000000000000010000000100000000000000000000000100000000001380D98B00000000000031000000085761746368202632000000000000000000000000010000000100000000000000000000000100000000001380CE01000000000000FFFFFFFF0C576174636820416E63686F720100000000000000000000000100000001000000000000000000000001000000000013800F01000000000000320000000E4D656D6F72792057696E646F7773000000000000000000000000010000000100000000000000000000000100000004001380D28B00000000000032000000094D656D6F7279202631000000000000000000000000010000000100000000000000000000000100000000001380D38B00000000000032000000094D656D6F7279202632000000000000000000000000010000000100000000000000000000000100000000001380D48B00000000000032000000094D656D6F7279202633000000000000000000000000010000000100000000000000000000000100000000001380D58B00000000000032000000094D656D6F72792026340000000000000000000000000100000001000000000000000000000001000000000013801001000000000000330000000E53657269616C2057696E646F77730000000000000000000000000100000001000000000000000000000001000000040013809307000000000000330000000855415254202326310000000000000000000000000100000001000000000000000000000001000000000013809407000000000000330000000855415254202326320000000000000000000000000100000001000000000000000000000001000000000013809507000000000000330000000855415254202326330000000000000000000000000100000001000000000000000000000001000000000013809607000000000000330000001626446562756720287072696E746629205669657765720000000000000000000000000100000001000000000000000000000001000000000013803C010000000000003400000010416E616C797369732057696E646F7773000000000000000000000000010000000100000000000000000000000100000004001380658A000000000000340000000F264C6F67696320416E616C797A6572000000000000000000000000010000000100000000000000000000000100000000001380DC7F0000000000003E0000001526506572666F726D616E636520416E616C797A6572000000000000000000000000010000000100000000000000000000000100000000001380E788000000000000380000000E26436F646520436F766572616765000000000000000000000000010000000100000000000000000000000100000000001380CD01000000000000FFFFFFFF0F416E616C7973697320416E63686F7201000000000000000000000001000000010000000000000000000000010000000000138053010000000000003F0000000D54726163652057696E646F77730000000000000000000000000100000001000000000000000000000001000000010013805401000000000000FFFFFFFF115472616365204D656E7520416E63686F720100000000000000000000000100000001000000000000000000000001000000000013802901000000000000350000001553797374656D205669657765722057696E646F77730000000000000000000000000100000001000000000000000000000001000000010013804B01000000000000FFFFFFFF1453797374656D2056696577657220416E63686F720100000000000000000000000100000001000000000000000000000001000000000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000013800189000000000000360000000F26546F6F6C626F782057696E646F7700000000000000000000000001000000010000000000000000000000010000000300138044C5000000000000FFFFFFFF0E5570646174652057696E646F77730100000000000000000000000100000001000000000000000000000001000000000013800000000000000400FFFFFFFF000000000000000000000000000100000001000000000000000000000001000000000013805B01000000000000FFFFFFFF12546F6F6C626F78204D656E75416E63686F720100000000000000000000000100000001000000000000000000000001000000000000000000054465627567FF7F0000 + + + 898 + 1900FFFF01001100434D4643546F6F6C426172427574746F6ECC88000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001801780000000000000FFFFFFFF00010000000000000001000000000000000100000001801D80000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001801A80000000000000FFFFFFFF00010000000000000001000000000000000100000001801B80000000000000FFFFFFFF0001000000000000000100000000000000010000000180E57F000000000000FFFFFFFF00010000000000000001000000000000000100000001801C80000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001800089000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF0000000000000000000100000000000000010000000180E48B000000000000FFFFFFFF0001000000000000000100000000000000010000000180F07F000000000000FFFFFFFF0001000000000000000100000000000000010000000180E888000000000000FFFFFFFF00010000000000000001000000000000000100000001803B01000000000000FFFFFFFF0001000000000000000100000000000000010000000180BB8A000000000000FFFFFFFF0001000000000000000100000000000000010000000180D88B000000000000FFFFFFFF0001000000000000000100000000000000010000000180D28B000000000000FFFFFFFF00010000000000000001000000000000000100000001809307000000000000FFFFFFFF0001000000000000000100000000000000010000000180658A000000000000FFFFFFFF0001000000000000000100000000000000010000000180C18A000000000000FFFFFFFF0001000000000000000100000000000000010000000180EE8B000000000000FFFFFFFF00010000000000000001000000000000000100000001800000000000000000FFFFFFFF00000000000000000001000000000000000100000001800189000000000000FFFFFFFF000100000000000000010000000000000001000000 + + + 898 + 1900FFFF01001100434D4643546F6F6C426172427574746F6ECC880000000000000000000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018017800000000000000100000000000000000000000000000000010000000100000001801D800000000000000200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF00000000000000000000000000010000000100000001801A800000000000000300000000000000000000000000000000010000000100000001801B80000000000000040000000000000000000000000000000001000000010000000180E57F0000000000000500000000000000000000000000000000010000000100000001801C800000000000000600000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF000000000000000000000000000100000001000000018000890000000000000700000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180E48B000000000000080000000000000000000000000000000001000000010000000180F07F000000000000090000000000000000000000000000000001000000010000000180E8880000000000000A00000000000000000000000000000000010000000100000001803B010000000000000B0000000000000000000000000000000001000000010000000180BB8A0000000000000C0000000000000000000000000000000001000000010000000180D88B0000000000000D0000000000000000000000000000000001000000010000000180D28B0000000000000E000000000000000000000000000000000100000001000000018093070000000000000F0000000000000000000000000000000001000000010000000180658A000000000000100000000000000000000000000000000001000000010000000180C18A000000000000110000000000000000000000000000000001000000010000000180EE8B0000000000001200000000000000000000000000000000010000000100000001800000000001000000FFFFFFFF0000000000000000000000000001000000010000000180018900000000000013000000000000000000000000000000000100000001000000 + + + + 0 + 1536 + 864 + + + + + + 1 + 0 + + 100 + 7 + + .\main.c + 6 + 49 + 57 + 1 + + 0 + + + ..\BSP\gpio.c + 0 + 668 + 684 + 1 + + 0 + + + ..\BSP\adc.c + 31 + 191 + 212 + 1 + + 0 + + + ..\USER\global.h + 72 + 186 + 101 + 1 + + 0 + + + ..\MOUDLE\Screen.c + 74 + 1160 + 1177 + 1 + + 0 + + + ..\BSP\i2c.c + 0 + 356 + 379 + 1 + + 0 + + + ..\BSP\spi.c + 0 + 85 + 99 + 1 + + 0 + + + ..\BSP\flash.c + 52 + 81 + 25 + 1 + + 0 + + + ..\MOUDLE\GasGauge.c + 0 + 2 + 12 + 1 + + 0 + + + .\global.c + 34 + 1375 + 1398 + 1 + + 0 + + + ..\MOUDLE\Status.c + 44 + 2166 + 2189 + 1 + + 0 + + + ..\MOUDLE\H7690C.c + 0 + 1371 + 1395 + 1 + + 0 + + + ..\MOUDLE\AFE_SH3673520.c + 20 + 1 + 23 + 1 + + 0 + + + ..\MOUDLE\AFE_SH3673520.h + 0 + 194 + 217 + 1 + + 0 + + + ..\PROTOCOL\ProtocolSwitch_P2.c + 0 + 1 + 1 + 1 + + 0 + + + ..\MOUDLE\RS485_Modbus_Inverter.c + 39 + 143 + 150 + 1 + + 0 + + + ..\BSP\can.c + 51 + 154 + 167 + 1 + + 0 + + + ..\BSP\pwm.c + 0 + 19 + 20 + 1 + + 0 + + + + +     diff --git a/USER/BT_BMS_V3.0.uvoptx b/USER/BT_BMS_V3.0.uvoptx new file mode 100644 index 0000000..7b46dc5 --- /dev/null +++ b/USER/BT_BMS_V3.0.uvoptx @@ -0,0 +1,1512 @@ + + + + 1.0 + +
    ### uVision Project, (C) Keil Software
    + + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + UL2CM3 + -U-O206 -O206 -S8 -C0 -P00 -N00("") -D00(00000000) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO23 -FN1 -FC1000 -FD20000000 -FF0STM32F10x_512 -FL080000 -FS08000000 -FP0($$Device:STM32F103RC$Flash\STM32F10x_512.FLM) + + + 0 + JL2CM3 + -U150711189 -O78 -S4 -ZTIFSpeedSel2000 -A0 -C0 -JU1 -JI-JP0 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(1BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8001 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO31 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_512.FLM -FS08000000 -FL080000 -FP0($$Device:STM32F103RC$Flash\STM32F10x_512.FLM) + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + 0 + DLGUARM + 4榄 + + + + + + 0 + 1 + bmsMem,0x0A + + + 1 + 1 + bmsMem.E2_485Addr + + + 2 + 1 + paraMem + + + 3 + 1 + VersionMem + + + 4 + 1 + BLE_Tx_Buf + + + 5 + 1 + BLE_Rx_Buf + + + 6 + 1 + WIFI_Tx_Buf + + + 7 + 1 + WIFI_Rx_Buf + + + 8 + 1 + LTE_Tx_Buf + + + 9 + 1 + LTE_Rx_Buf + + + 10 + 1 + LTE_Onflag + + + 11 + 1 + LTE_SIMflag + + + 12 + 1 + LTE_Networkflag + + + 13 + 1 + LTE_Onlineflag + + + 14 + 1 + LTE_rssi,0x0A + + + 15 + 1 + LTE_WarmDelay,0x0A + + + 16 + 1 + LTE_Rx_ErrCnt,0x0A + + + 17 + 1 + MQTT_RST_count,0x0A + + + 18 + 1 + LTE_Moni_Count/100,0x0A + + + 19 + 1 + \\BT_BMS_V3\../MOUDLE/H7690C.c\MQTT_READY_flag + + + 20 + 1 + ID_str + + + 21 + 1 + putSrvc_reply_flg + + + 22 + 1 + setPara_reply_flg + + + 23 + 1 + \\BT_BMS_V3\../MOUDLE/MBO26A.c\getPara_reply_flg + + + 24 + 1 + getPara_reply_sumlen,0x0A + + + 25 + 1 + \\BT_BMS_V3\../MOUDLE/H7690C.c\MQTT_READY_flag + + + 26 + 1 + \\BT_BMS_V3\../MOUDLE/H7690C.c\LTE_status + + + 27 + 1 + \\BT_BMS_V3\../MOUDLE/H7690C.c\LTE_step,0x0A + + + 28 + 1 + protocolStrings[protocol-1] + + + 29 + 1 + FirmwareVersion + + + 30 + 1 + \\BT_BMS_V3\../MOUDLE/H7690C.c\MQTT_timed_count,0x0A + + + 31 + 1 + power_old + + + 32 + 1 + PCHG_startCnt + + + 33 + 1 + PCHG_startFlag + + + 34 + 1 + paraMem.pchg_startTime + + + 35 + 1 + loadvol,0x0A + + + 36 + 1 + timecount,0x0A + + + 37 + 1 + canMem[0].cycleCnt + + + 38 + 1 + canMem + + + 39 + 1 + LTE_lastFlag + + + 40 + 1 + OTA_ErrCnt + + + 41 + 1 + \\BT_BMS_V3\../MOUDLE/H7690C.c\LTE_Rx_Buf + + + 42 + 1 + \\BT_BMS_V3\../MOUDLE/H7690C.c\MQTT_ErrCnt + + + 43 + 1 + \\BT_BMS_V3\../MOUDLE/H7690C.c\MQTT_READY_flag + + + 44 + 1 + LTE_OTA_Flag + + + 45 + 1 + modbusBuf + + + 46 + 1 + loadvol,0x0A + + + 47 + 1 + dsgCtrl + + + 48 + 1 + dsgCtrl_old + + + 49 + 1 + PCHG_Flag + + + + + 0 + 2 + CRESET_flag + + + 1 + 2 + CRESET_step + + + 2 + 2 + \\BT_BMS_V3\../MOUDLE/H7690C.c\CFUN_flag + + + 3 + 2 + CFUN_step + + + 4 + 2 + \\BT_BMS_V3\../MOUDLE/H7690C.c\MQTT_RST_flag + + + 5 + 2 + MQTT_RST_step + + + 6 + 2 + CRESET_count,0x0A + + + 7 + 2 + CFUN_count,0x0A + + + 8 + 2 + MQTT_RST_count,0x0A + + + 9 + 2 + LTE_ErrCnt,0x0A + + + 10 + 2 + MQTT_ErrCnt,0x0A + + + 11 + 2 + LTE_rssi,0x0A + + + 12 + 2 + CSQ_flag + + + 13 + 2 + CGREG_flag + + + 14 + 2 + MQTT_START_flag + + + 15 + 2 + MQTT_START_step + + + 16 + 2 + \\BT_BMS_V3\../MOUDLE/H7690C.c\CICCID_flag + + + 17 + 2 + \\BT_BMS_V3\../MOUDLE/H7690C.c\SUBTOPIC_flag + + + 18 + 2 + SUBTOPIC_step + + + 19 + 2 + \\BT_BMS_V3\../MOUDLE/H7690C.c\CALITIME_flag + + + 20 + 2 + CALITIME_step + + + 21 + 2 + \\BT_BMS_V3\../MOUDLE/H7690C.c\MQTT_READY_flag + + + 22 + 2 + \\BT_BMS_V3\../MOUDLE/H7690C.c\LTE_status,0x10 + + + 23 + 2 + \\BT_BMS_V3\../MOUDLE/H7690C.c\LTE_step,0x0A + + + 24 + 2 + \\BT_BMS_V3\../MOUDLE/H7690C.c\LTE_WarmDelay,0x0A + + + 25 + 2 + LTE_Moni_Count/100,0x0A + + + 26 + 2 + incident_flag + + + 27 + 2 + incident_str + + + 28 + 2 + incident_len,0x0A + + + 29 + 2 + incident_time,0x0A + + + 30 + 2 + LTEMem_len,0x0A + + + 31 + 2 + LTEMem_Buf + + + 32 + 2 + MQTT_timed_count,0x0A + + + 33 + 2 + firmware_size,0x0A + + + 34 + 2 + firmware_crc,0x0A + + + 35 + 2 + otaInfo_reply_count + + + 36 + 2 + otaData_reply_count + + + 37 + 2 + ota_code + + + 38 + 2 + rev_page + + + 39 + 2 + ota_wr_data + + + 40 + 2 + \\BT_BMS_V3\../MOUDLE/OTA.c\rev_index,0x0A + + + 41 + 2 + rev_crc + + + 42 + 2 + dataIdx + + + 43 + 2 + ota_wr_data[0] + + + 44 + 2 + ota_wr_data[256] + + + 45 + 2 + ota_wr_data[512] + + + 46 + 2 + ota_wr_data[768] + + + 47 + 2 + ota_wr_data[1024] + + + 48 + 2 + ota_wr_data[1280] + + + 49 + 2 + ota_wr_data[1536] + + + 50 + 2 + ota_wr_data[1792] + + + 51 + 2 + \\BT_BMS_V3\../MOUDLE/OTA.c\rev_index,0x0A + + + 52 + 2 + \\BT_BMS_V3\../MOUDLE/OTA.c\ota_code + + + 53 + 2 + \\BT_BMS_V3\../MOUDLE/OTA.c\rev_crc + + + 54 + 2 + otaData_reply_count,0x0A + + + 55 + 2 + ota_rx_Buf + + + 56 + 2 + data_str + + + 57 + 2 + dataLen,0x0A + + + + + 1 + 0 + 0x08020800 + 0 + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 2 + 10000000 + + + + + + CORE + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\CORE\core_cm3.c + core_cm3.c + 0 + 0 + + + 1 + 2 + 2 + 0 + 0 + 0 + ..\CORE\startup_stm32f10x_hd.s + startup_stm32f10x_hd.s + 0 + 0 + + + + + USER + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + .\main.c + main.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + .\global.c + global.c + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + .\stm32f10x_it.c + stm32f10x_it.c + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + .\system_stm32f10x.c + system_stm32f10x.c + 0 + 0 + + + + + BSP + 1 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + ..\BSP\gpio.c + gpio.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\BSP\tim.c + tim.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\BSP\uart.c + uart.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\BSP\i2c.c + i2c.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\BSP\spi.c + spi.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\BSP\flash.c + flash.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\BSP\rtc.c + rtc.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\BSP\systick.c + systick.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\BSP\can.c + can.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\BSP\adc.c + adc.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\BSP\pwm.c + pwm.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\BSP\wdg.c + wdg.c + 0 + 0 + + + + + MOUDLE + 1 + 0 + 0 + 0 + + 4 + 19 + 1 + 0 + 0 + 0 + ..\MOUDLE\AFE_SH3673520.c + AFE_SH3673520.c + 0 + 0 + + + 4 + 20 + 1 + 0 + 0 + 0 + ..\MOUDLE\RS485_Modbus.c + RS485_Modbus.c + 0 + 0 + + + 4 + 21 + 1 + 0 + 0 + 0 + ..\MOUDLE\RS485_Modbus_Inverter.c + RS485_Modbus_Inverter.c + 0 + 0 + + + 4 + 22 + 1 + 0 + 0 + 0 + ..\MOUDLE\NTC.c + NTC.c + 0 + 0 + + + 4 + 23 + 1 + 0 + 0 + 0 + ..\MOUDLE\Screen.c + Screen.c + 0 + 0 + + + 4 + 24 + 1 + 0 + 0 + 0 + ..\MOUDLE\GasGauge.c + GasGauge.c + 0 + 0 + + + 4 + 25 + 1 + 0 + 0 + 0 + ..\MOUDLE\SOE.c + SOE.c + 0 + 0 + + + 4 + 26 + 1 + 0 + 0 + 0 + ..\MOUDLE\OCV.c + OCV.c + 0 + 0 + + + 4 + 27 + 1 + 0 + 0 + 0 + ..\MOUDLE\Status.c + Status.c + 0 + 0 + + + 4 + 28 + 1 + 0 + 0 + 0 + ..\MOUDLE\MBO26A.c + MBO26A.c + 0 + 0 + + + 4 + 29 + 1 + 0 + 0 + 0 + ..\MOUDLE\YiBang.c + YiBang.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + ..\MOUDLE\H7690C.c + H7690C.c + 0 + 0 + + + 4 + 31 + 1 + 0 + 0 + 0 + ..\MOUDLE\LBS_Transmit.c + LBS_Transmit.c + 0 + 0 + + + 4 + 32 + 1 + 0 + 0 + 0 + ..\MOUDLE\OTA.c + OTA.c + 0 + 0 + + + + + STM32F103x_FWLIB + 0 + 0 + 0 + 0 + + 5 + 33 + 1 + 0 + 0 + 0 + ..\STM32F10x_FWLIB\src\misc.c + misc.c + 0 + 0 + + + 5 + 34 + 1 + 0 + 0 + 0 + ..\STM32F10x_FWLIB\src\stm32f10x_adc.c + stm32f10x_adc.c + 0 + 0 + + + 5 + 35 + 1 + 0 + 0 + 0 + ..\STM32F10x_FWLIB\src\stm32f10x_bkp.c + stm32f10x_bkp.c + 0 + 0 + + + 5 + 36 + 1 + 0 + 0 + 0 + ..\STM32F10x_FWLIB\src\stm32f10x_can.c + stm32f10x_can.c + 0 + 0 + + + 5 + 37 + 1 + 0 + 0 + 0 + ..\STM32F10x_FWLIB\src\stm32f10x_cec.c + stm32f10x_cec.c + 0 + 0 + + + 5 + 38 + 1 + 0 + 0 + 0 + ..\STM32F10x_FWLIB\src\stm32f10x_crc.c + stm32f10x_crc.c + 0 + 0 + + + 5 + 39 + 1 + 0 + 0 + 0 + ..\STM32F10x_FWLIB\src\stm32f10x_dac.c + stm32f10x_dac.c + 0 + 0 + + + 5 + 40 + 1 + 0 + 0 + 0 + ..\STM32F10x_FWLIB\src\stm32f10x_dbgmcu.c + stm32f10x_dbgmcu.c + 0 + 0 + + + 5 + 41 + 1 + 0 + 0 + 0 + ..\STM32F10x_FWLIB\src\stm32f10x_dma.c + stm32f10x_dma.c + 0 + 0 + + + 5 + 42 + 1 + 0 + 0 + 0 + ..\STM32F10x_FWLIB\src\stm32f10x_exti.c + stm32f10x_exti.c + 0 + 0 + + + 5 + 43 + 1 + 0 + 0 + 0 + ..\STM32F10x_FWLIB\src\stm32f10x_flash.c + stm32f10x_flash.c + 0 + 0 + + + 5 + 44 + 1 + 0 + 0 + 0 + ..\STM32F10x_FWLIB\src\stm32f10x_fsmc.c + stm32f10x_fsmc.c + 0 + 0 + + + 5 + 45 + 1 + 0 + 0 + 0 + ..\STM32F10x_FWLIB\src\stm32f10x_gpio.c + stm32f10x_gpio.c + 0 + 0 + + + 5 + 46 + 1 + 0 + 0 + 0 + ..\STM32F10x_FWLIB\src\stm32f10x_i2c.c + stm32f10x_i2c.c + 0 + 0 + + + 5 + 47 + 1 + 0 + 0 + 0 + ..\STM32F10x_FWLIB\src\stm32f10x_iwdg.c + stm32f10x_iwdg.c + 0 + 0 + + + 5 + 48 + 1 + 0 + 0 + 0 + ..\STM32F10x_FWLIB\src\stm32f10x_pwr.c + stm32f10x_pwr.c + 0 + 0 + + + 5 + 49 + 1 + 0 + 0 + 0 + ..\STM32F10x_FWLIB\src\stm32f10x_rcc.c + stm32f10x_rcc.c + 0 + 0 + + + 5 + 50 + 1 + 0 + 0 + 0 + ..\STM32F10x_FWLIB\src\stm32f10x_rtc.c + stm32f10x_rtc.c + 0 + 0 + + + 5 + 51 + 1 + 0 + 0 + 0 + ..\STM32F10x_FWLIB\src\stm32f10x_sdio.c + stm32f10x_sdio.c + 0 + 0 + + + 5 + 52 + 1 + 0 + 0 + 0 + ..\STM32F10x_FWLIB\src\stm32f10x_spi.c + stm32f10x_spi.c + 0 + 0 + + + 5 + 53 + 1 + 0 + 0 + 0 + ..\STM32F10x_FWLIB\src\stm32f10x_tim.c + stm32f10x_tim.c + 0 + 0 + + + 5 + 54 + 1 + 0 + 0 + 0 + ..\STM32F10x_FWLIB\src\stm32f10x_usart.c + stm32f10x_usart.c + 0 + 0 + + + 5 + 55 + 1 + 0 + 0 + 0 + ..\STM32F10x_FWLIB\src\stm32f10x_wwdg.c + stm32f10x_wwdg.c + 0 + 0 + + + + + README + 1 + 0 + 0 + 0 + + 6 + 56 + 5 + 0 + 0 + 0 + ..\README\readme.txt + readme.txt + 0 + 0 + + + + + InverterProtocol + 1 + 0 + 0 + 0 + + 7 + 57 + 1 + 0 + 0 + 0 + ..\PROTOCOL\ProtocolSwitch_P1.c + ProtocolSwitch_P1.c + 0 + 0 + + + 7 + 58 + 1 + 0 + 0 + 0 + ..\PROTOCOL\ProtocolSwitch_P2.c + ProtocolSwitch_P2.c + 0 + 0 + + + +     diff --git a/USER/BT_BMS_V3.0.uvprojx b/USER/BT_BMS_V3.0.uvprojx new file mode 100644 index 0000000..c01ade7 --- /dev/null +++ b/USER/BT_BMS_V3.0.uvprojx @@ -0,0 +1,715 @@ + + + + 2.1 + +
    ### uVision Project, (C) Keil Software
    + + + + Target 1 + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + STM32F103RC + STMicroelectronics + Keil.STM32F1xx_DFP.2.3.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0xC000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_512 -FS08000000 -FL080000 -FP0($$Device:STM32F103RC$Flash\STM32F10x_512.FLM)) + 4230 + $$Device:STM32F103RC$Device\Include\stm32f10x.h + + + + + + + + + + $$Device:STM32F103RC$SVD\STM32F103xx.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + ..\OBJ\ + BT_BMS_V3.0 + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + $K\ARM\ARMCC\bin\fromelf.exe --bin --output=Bin\@L.bin !L + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0xc000 + + + 1 + 0x8000000 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x40000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0xc000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + STM32F10X_HD,USE_STDPERIPH_DRIVER + + ..\USER;..\CORE;..\STM32F10x_FWLIB\inc;..\MOUDLE;..\BSP + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + CORE + + + core_cm3.c + 1 + ..\CORE\core_cm3.c + + + startup_stm32f10x_hd.s + 2 + ..\CORE\startup_stm32f10x_hd.s + + + + + USER + + + main.c + 1 + .\main.c + + + global.c + 1 + .\global.c + + + stm32f10x_it.c + 1 + .\stm32f10x_it.c + + + system_stm32f10x.c + 1 + .\system_stm32f10x.c + + + + + BSP + + + gpio.c + 1 + ..\BSP\gpio.c + + + tim.c + 1 + ..\BSP\tim.c + + + uart.c + 1 + ..\BSP\uart.c + + + i2c.c + 1 + ..\BSP\i2c.c + + + spi.c + 1 + ..\BSP\spi.c + + + flash.c + 1 + ..\BSP\flash.c + + + rtc.c + 1 + ..\BSP\rtc.c + + + systick.c + 1 + ..\BSP\systick.c + + + can.c + 1 + ..\BSP\can.c + + + adc.c + 1 + ..\BSP\adc.c + + + pwm.c + 1 + ..\BSP\pwm.c + + + wdg.c + 1 + ..\BSP\wdg.c + + + + + MOUDLE + + + AFE_SH3673520.c + 1 + ..\MOUDLE\AFE_SH3673520.c + + + RS485_Modbus.c + 1 + ..\MOUDLE\RS485_Modbus.c + + + RS485_Modbus_Inverter.c + 1 + ..\MOUDLE\RS485_Modbus_Inverter.c + + + NTC.c + 1 + ..\MOUDLE\NTC.c + + + Screen.c + 1 + ..\MOUDLE\Screen.c + + + GasGauge.c + 1 + ..\MOUDLE\GasGauge.c + + + SOE.c + 1 + ..\MOUDLE\SOE.c + + + OCV.c + 1 + ..\MOUDLE\OCV.c + + + Status.c + 1 + ..\MOUDLE\Status.c + + + MBO26A.c + 1 + ..\MOUDLE\MBO26A.c + + + YiBang.c + 1 + ..\MOUDLE\YiBang.c + + + H7690C.c + 1 + ..\MOUDLE\H7690C.c + + + LBS_Transmit.c + 1 + ..\MOUDLE\LBS_Transmit.c + + + OTA.c + 1 + ..\MOUDLE\OTA.c + + + + + STM32F103x_FWLIB + + + misc.c + 1 + ..\STM32F10x_FWLIB\src\misc.c + + + stm32f10x_adc.c + 1 + ..\STM32F10x_FWLIB\src\stm32f10x_adc.c + + + stm32f10x_bkp.c + 1 + ..\STM32F10x_FWLIB\src\stm32f10x_bkp.c + + + stm32f10x_can.c + 1 + ..\STM32F10x_FWLIB\src\stm32f10x_can.c + + + stm32f10x_cec.c + 1 + ..\STM32F10x_FWLIB\src\stm32f10x_cec.c + + + stm32f10x_crc.c + 1 + ..\STM32F10x_FWLIB\src\stm32f10x_crc.c + + + stm32f10x_dac.c + 1 + ..\STM32F10x_FWLIB\src\stm32f10x_dac.c + + + stm32f10x_dbgmcu.c + 1 + ..\STM32F10x_FWLIB\src\stm32f10x_dbgmcu.c + + + stm32f10x_dma.c + 1 + ..\STM32F10x_FWLIB\src\stm32f10x_dma.c + + + stm32f10x_exti.c + 1 + ..\STM32F10x_FWLIB\src\stm32f10x_exti.c + + + stm32f10x_flash.c + 1 + ..\STM32F10x_FWLIB\src\stm32f10x_flash.c + + + stm32f10x_fsmc.c + 1 + ..\STM32F10x_FWLIB\src\stm32f10x_fsmc.c + + + stm32f10x_gpio.c + 1 + ..\STM32F10x_FWLIB\src\stm32f10x_gpio.c + + + stm32f10x_i2c.c + 1 + ..\STM32F10x_FWLIB\src\stm32f10x_i2c.c + + + stm32f10x_iwdg.c + 1 + ..\STM32F10x_FWLIB\src\stm32f10x_iwdg.c + + + stm32f10x_pwr.c + 1 + ..\STM32F10x_FWLIB\src\stm32f10x_pwr.c + + + stm32f10x_rcc.c + 1 + ..\STM32F10x_FWLIB\src\stm32f10x_rcc.c + + + stm32f10x_rtc.c + 1 + ..\STM32F10x_FWLIB\src\stm32f10x_rtc.c + + + stm32f10x_sdio.c + 1 + ..\STM32F10x_FWLIB\src\stm32f10x_sdio.c + + + stm32f10x_spi.c + 1 + ..\STM32F10x_FWLIB\src\stm32f10x_spi.c + + + stm32f10x_tim.c + 1 + ..\STM32F10x_FWLIB\src\stm32f10x_tim.c + + + stm32f10x_usart.c + 1 + ..\STM32F10x_FWLIB\src\stm32f10x_usart.c + + + stm32f10x_wwdg.c + 1 + ..\STM32F10x_FWLIB\src\stm32f10x_wwdg.c + + + + + README + + + readme.txt + 5 + ..\README\readme.txt + + + + + InverterProtocol + + + ProtocolSwitch_P1.c + 1 + ..\PROTOCOL\ProtocolSwitch_P1.c + + + ProtocolSwitch_P2.c + 1 + ..\PROTOCOL\ProtocolSwitch_P2.c + + + + + + + + + + + + + +     diff --git a/USER/DebugConfig/Target_1_STM32F103C8.dbgconf b/USER/DebugConfig/Target_1_STM32F103C8.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/USER/DebugConfig/Target_1_STM32F103C8.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/USER/DebugConfig/Target_1_STM32F103C8_1.0.0.dbgconf b/USER/DebugConfig/Target_1_STM32F103C8_1.0.0.dbgconf new file mode 100644 index 0000000..66e10b6 --- /dev/null +++ b/USER/DebugConfig/Target_1_STM32F103C8_1.0.0.dbgconf @@ -0,0 +1,36 @@ +// File: STM32F101_102_103_105_107.dbgconf +// Version: 1.0.0 +// Note: refer to STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx Reference manual (RM0008) +// STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx datasheets + +// <<< Use Configuration Wizard in Context Menu >>> + +// Debug MCU configuration register (DBGMCU_CR) +// Reserved bits must be kept at reset value +// DBG_TIM11_STOP TIM11 counter stopped when core is halted +// DBG_TIM10_STOP TIM10 counter stopped when core is halted +// DBG_TIM9_STOP TIM9 counter stopped when core is halted +// DBG_TIM14_STOP TIM14 counter stopped when core is halted +// DBG_TIM13_STOP TIM13 counter stopped when core is halted +// DBG_TIM12_STOP TIM12 counter stopped when core is halted +// DBG_CAN2_STOP Debug CAN2 stopped when core is halted +// DBG_TIM7_STOP TIM7 counter stopped when core is halted +// DBG_TIM6_STOP TIM6 counter stopped when core is halted +// DBG_TIM5_STOP TIM5 counter stopped when core is halted +// DBG_TIM8_STOP TIM8 counter stopped when core is halted +// DBG_I2C2_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted +// DBG_I2C1_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted +// DBG_CAN1_STOP Debug CAN1 stopped when Core is halted +// DBG_TIM4_STOP TIM4 counter stopped when core is halted +// DBG_TIM3_STOP TIM3 counter stopped when core is halted +// DBG_TIM2_STOP TIM2 counter stopped when core is halted +// DBG_TIM1_STOP TIM1 counter stopped when core is halted +// DBG_WWDG_STOP Debug window watchdog stopped when core is halted +// DBG_IWDG_STOP Debug independent watchdog stopped when core is halted +// DBG_STANDBY Debug standby mode +// DBG_STOP Debug stop mode +// DBG_SLEEP Debug sleep mode +// +DbgMCU_CR = 0x00000007; + +// <<< end of configuration section >>> diff --git a/USER/DebugConfig/Target_1_STM32F103RB.dbgconf b/USER/DebugConfig/Target_1_STM32F103RB.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/USER/DebugConfig/Target_1_STM32F103RB.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/USER/DebugConfig/Target_1_STM32F103RC.dbgconf b/USER/DebugConfig/Target_1_STM32F103RC.dbgconf new file mode 100644 index 0000000..90dabd8 --- /dev/null +++ b/USER/DebugConfig/Target_1_STM32F103RC.dbgconf @@ -0,0 +1,97 @@ +// <<< Use Configuration Wizard in Context Menu >>> +// Debug MCU Configuration +// DBG_SLEEP +// Debug Sleep Mode +// 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled +// 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK +// DBG_STOP +// Debug Stop Mode +// 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks +// 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_STANDBY +// Debug Standby Mode +// 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered. +// 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active +// DBG_IWDG_STOP +// Debug independent watchdog stopped when core is halted +// 0: The watchdog counter clock continues even if the core is halted +// 1: The watchdog counter clock is stopped when the core is halted +// DBG_WWDG_STOP +// Debug window watchdog stopped when core is halted +// 0: The window watchdog counter clock continues even if the core is halted +// 1: The window watchdog counter clock is stopped when the core is halted +// DBG_TIM1_STOP +// Timer 1 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM2_STOP +// Timer 2 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM3_STOP +// Timer 3 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_TIM4_STOP +// Timer 4 counter stopped when core is halted +// 0: The clock of the involved Timer Counter is fed even if the core is halted +// 1: The clock of the involved Timer counter is stopped when the core is halted +// DBG_CAN1_STOP +// Debug CAN1 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN1 receive registers are frozen +// DBG_I2C1_SMBUS_TIMEOUT +// I2C1 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_I2C2_SMBUS_TIMEOUT +// I2C2 SMBUS timeout mode stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: The SMBUS timeout is frozen +// DBG_TIM8_STOP +// Timer 8 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM5_STOP +// Timer 5 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM6_STOP +// Timer 6 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM7_STOP +// Timer 7 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_CAN2_STOP +// Debug CAN2 stopped when Core is halted +// 0: Same behavior as in normal mode +// 1: CAN2 receive registers are frozen +// DBG_TIM12_STOP +// Timer 12 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM13_STOP +// Timer 13 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM14_STOP +// Timer 14 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM9_STOP +// Timer 9 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM10_STOP +// Timer 10 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// DBG_TIM11_STOP +// Timer 11 counter stopped when core is halted +// 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally. +// 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event). +// +DbgMCU_CR = 0x00000007; +// <<< end of configuration section >>> \ No newline at end of file diff --git a/USER/DebugConfig/Target_1_STM32F103RC_1.0.0.dbgconf b/USER/DebugConfig/Target_1_STM32F103RC_1.0.0.dbgconf new file mode 100644 index 0000000..66e10b6 --- /dev/null +++ b/USER/DebugConfig/Target_1_STM32F103RC_1.0.0.dbgconf @@ -0,0 +1,36 @@ +// File: STM32F101_102_103_105_107.dbgconf +// Version: 1.0.0 +// Note: refer to STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx Reference manual (RM0008) +// STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx datasheets + +// <<< Use Configuration Wizard in Context Menu >>> + +// Debug MCU configuration register (DBGMCU_CR) +// Reserved bits must be kept at reset value +// DBG_TIM11_STOP TIM11 counter stopped when core is halted +// DBG_TIM10_STOP TIM10 counter stopped when core is halted +// DBG_TIM9_STOP TIM9 counter stopped when core is halted +// DBG_TIM14_STOP TIM14 counter stopped when core is halted +// DBG_TIM13_STOP TIM13 counter stopped when core is halted +// DBG_TIM12_STOP TIM12 counter stopped when core is halted +// DBG_CAN2_STOP Debug CAN2 stopped when core is halted +// DBG_TIM7_STOP TIM7 counter stopped when core is halted +// DBG_TIM6_STOP TIM6 counter stopped when core is halted +// DBG_TIM5_STOP TIM5 counter stopped when core is halted +// DBG_TIM8_STOP TIM8 counter stopped when core is halted +// DBG_I2C2_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted +// DBG_I2C1_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted +// DBG_CAN1_STOP Debug CAN1 stopped when Core is halted +// DBG_TIM4_STOP TIM4 counter stopped when core is halted +// DBG_TIM3_STOP TIM3 counter stopped when core is halted +// DBG_TIM2_STOP TIM2 counter stopped when core is halted +// DBG_TIM1_STOP TIM1 counter stopped when core is halted +// DBG_WWDG_STOP Debug window watchdog stopped when core is halted +// DBG_IWDG_STOP Debug independent watchdog stopped when core is halted +// DBG_STANDBY Debug standby mode +// DBG_STOP Debug stop mode +// DBG_SLEEP Debug sleep mode +// +DbgMCU_CR = 0x00000007; + +// <<< end of configuration section >>> diff --git a/USER/EventRecorderStub.scvd b/USER/EventRecorderStub.scvd new file mode 100644 index 0000000..2956b29 --- /dev/null +++ b/USER/EventRecorderStub.scvd @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/USER/JLinkLog.txt b/USER/JLinkLog.txt new file mode 100644 index 0000000..fa44f0e --- /dev/null +++ b/USER/JLinkLog.txt @@ -0,0 +1,3347 @@ +T4E58 4251:261 SEGGER J-Link V6.20 Log File (0001ms, 12603ms total) +T4E58 4251:261 DLL Compiled: Sep 8 2017 18:04:35 (0001ms, 12603ms total) +T4E58 4251:261 Logging started @ 2026-08-24 15:14 (0001ms, 12603ms total) +T4E58 4251:262 JLINK_SetWarnOutHandler(...) (0000ms, 12603ms total) +T4E58 4251:262 JLINK_OpenEx(...) +Firmware: J-Link V9 compiled May 7 2021 16:26:12 +Hardware: V9.70 +S/N: 150711189 +Feature(s): GDB, RDI, FlashBP, FlashDL, JFlash +TELNET listener socket opened on port 19021WEBSRV +Webserver running on local port 19080 returns O.K. (0133ms, 12736ms total) +T4E58 4251:395 JLINK_GetEmuCaps() returns 0xB9FF7BBF (0000ms, 12736ms total) +T4E58 4251:395 JLINK_TIF_GetAvailable(...) (0001ms, 12737ms total) +T4E58 4251:396 JLINK_SetErrorOutHandler(...) (0000ms, 12737ms total) +T4E58 4251:396 JLINK_ExecCommand("ProjectFile = "C:\Users\yue\Desktop\20串200A项目\3、测试代码\BMS_STM32_[V4.0.0.0](串数写入优化)(充放电高温看状态)(屏幕遮挡历史优化)(屏幕剩余时间优化)(200A参数)+[20020SF]+[V1.0.0]\USER\JLinkSettings.ini"", ...). returns 0x00 (0055ms, 12792ms total) +T4E58 4251:486 JLINK_ExecCommand("Device = STM32F103RC", ...). Device "STM32F103RC" selected. returns 0x00 (0072ms, 12865ms total) +T4E58 4251:559 JLINK_ExecCommand("DisableConnectionTimeout", ...). returns 0x01 (0000ms, 12865ms total) +T4E58 4251:559 JLINK_GetHardwareVersion() returns 0x17AE8 (0000ms, 12865ms total) +T4E58 4251:559 JLINK_GetDLLVersion() returns 62000 (0000ms, 12865ms total) +T4E58 4251:559 JLINK_GetFirmwareString(...) (0000ms, 12865ms total) +T4E58 4251:616 JLINK_GetDLLVersion() returns 62000 (0000ms, 12865ms total) +T4E58 4251:616 JLINK_GetCompileDateTime() (0000ms, 12865ms total) +T4E58 4251:638 JLINK_GetFirmwareString(...) (0000ms, 12865ms total) +T4E58 4251:683 JLINK_GetHardwareVersion() returns 0x17AE8 (0004ms, 12869ms total) +T4E58 4251:744 JLINK_TIF_Select(JLINKARM_TIF_SWD) returns 0x00 (0003ms, 12872ms total) +T4E58 4251:747 JLINK_SetSpeed(2000) (0000ms, 12872ms total) +T4E58 4251:747 JLINK_GetId() >0x10B TIF>Found SW-DP with ID 0x1BA01477 >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> + >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x10B TIF>Found SW-DP with ID 0x1BA01477 >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF>Scanning AP map to find all available APs >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> + >0x21 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF>AP[1]: Stopped AP scan as end of AP map has been reachedAP[0]: AHB-AP (IDR: 0x14770011)Iterating through AP map to find AHB-AP to use >0x42 TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x42 TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF>AP[0]: Core foundAP[0]: AHB-AP ROM base: 0xE00FF000 >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> + >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF>CPUID register: 0x411FC231. Implementer code: 0x41 (ARM)Found Cortex-M3 r1p1, Little endian. -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE0002000)FPUnit: 6 code (BP) slots and 2 literal slots -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) -- CPU_WriteMem(4 bytes @ 0xE0001000) -- CPU_ReadMem(4 bytes @ 0xE000ED88) + -- CPU_WriteMem(4 bytes @ 0xE000ED88) -- CPU_ReadMem(4 bytes @ 0xE000ED88) -- CPU_WriteMem(4 bytes @ 0xE000ED88)CoreSight components:ROMTbl[0] @ E00FF000 -- CPU_ReadMem(16 bytes @ 0xE00FF000) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) -- CPU_ReadMem(16 bytes @ 0xE000EFE0)ROMTbl[0][0]: E000E000, CID: B105E00D, PID: 001BB000 SCS -- CPU_ReadMem(16 bytes @ 0xE0001FF0) -- CPU_ReadMem(16 bytes @ 0xE0001FE0)ROMTbl[0][1]: E0001000, CID: B105E00D, PID: 001BB002 DWT -- CPU_ReadMem(16 bytes @ 0xE0002FF0) + -- CPU_ReadMem(16 bytes @ 0xE0002FE0)ROMTbl[0][2]: E0002000, CID: B105E00D, PID: 000BB003 FPB -- CPU_ReadMem(16 bytes @ 0xE0000FF0) -- CPU_ReadMem(16 bytes @ 0xE0000FE0)ROMTbl[0][3]: E0000000, CID: B105E00D, PID: 001BB001 ITM -- CPU_ReadMem(16 bytes @ 0xE00FF010) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) -- CPU_ReadMem(16 bytes @ 0xE0040FE0)ROMTbl[0][4]: E0040000, CID: B105900D, PID: 001BB923 TPIU-Lite -- CPU_ReadMem(16 bytes @ 0xE0041FF0) -- CPU_ReadMem(16 bytes @ 0xE0041FE0) +ROMTbl[0][5]: E0041000, CID: B105900D, PID: 101BB924 ETM-M3 >0x0D TIF> >0x21 TIF> returns 0x1BA01477 (0393ms, 13265ms total) +T4E58 4252:140 JLINK_GetDLLVersion() returns 62000 (0000ms, 13265ms total) +T4E58 4252:140 JLINK_CORE_GetFound() returns 0x30000FF (0000ms, 13265ms total) +T4E58 4252:140 JLINK_GetDebugInfo(0x100 = JLINKARM_ROM_TABLE_ADDR_INDEX) -- Value=0xE00FF000 returns 0x00 (0000ms, 13265ms total) +T4E58 4252:146 JLINK_GetDebugInfo(0x100 = JLINKARM_ROM_TABLE_ADDR_INDEX) -- Value=0xE00FF000 returns 0x00 (0000ms, 13265ms total) +T4E58 4252:146 JLINK_GetDebugInfo(0x101 = JLINKARM_DEBUG_INFO_ETM_ADDR_INDEX) -- Value=0xE0041000 returns 0x00 (0000ms, 13265ms total) +T4E58 4252:146 JLINK_ReadMemEx(0xE0041FD0, 0x0020 Bytes, ..., Flags = 0x02000004) -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x20 (0001ms, 13266ms total) +T4E58 4252:147 JLINK_GetDebugInfo(0x102 = JLINKARM_DEBUG_INFO_MTB_ADDR_INDEX) -- Value=0x00000000 returns 0x00 (0000ms, 13266ms total) +T4E58 4252:147 JLINK_GetDebugInfo(0x103 = JLINKARM_DEBUG_INFO_TPIU_ADDR_INDEX) -- Value=0xE0040000 returns 0x00 (0000ms, 13266ms total) +T4E58 4252:147 JLINK_GetDebugInfo(0x104 = JLINKARM_DEBUG_INFO_ITM_ADDR_INDEX) -- Value=0xE0000000 returns 0x00 (0000ms, 13266ms total) +T4E58 4252:147 JLINK_GetDebugInfo(0x105 = JLINKARM_DEBUG_INFO_DWT_ADDR_INDEX) -- Value=0xE0001000 returns 0x00 (0000ms, 13266ms total) +T4E58 4252:147 JLINK_GetDebugInfo(0x106 = JLINKARM_DEBUG_INFO_FPB_ADDR_INDEX) -- Value=0xE0002000 returns 0x00 (0000ms, 13266ms total) +T4E58 4252:147 JLINK_GetDebugInfo(0x107 = JLINKARM_DEBUG_INFO_NVIC_ADDR_INDEX) -- Value=0xE000E000 returns 0x00 (0000ms, 13266ms total) +T4E58 4252:147 JLINK_GetDebugInfo(0x10C = JLINKARM_DEBUG_INFO_DBG_ADDR_INDEX) -- Value=0xE000EDF0 returns 0x00 (0002ms, 13268ms total) +T4E58 4252:149 JLINK_ReadMemU32(0xE000ED00, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000ED00) - Data: 31 C2 1F 41 returns 0x01 (0000ms, 13268ms total) +T4E58 4252:149 JLINK_GetDebugInfo(0x10F = JLINKARM_DEBUG_INFO_HAS_CORTEX_M_SECURITY_EXT_INDEX) -- Value=0x00000000 returns 0x00 (0000ms, 13268ms total) +T4E58 4252:149 JLINK_SetResetType(JLINKARM_CM3_RESET_TYPE_NORMAL) returns JLINKARM_CM3_RESET_TYPE_NORMAL (0000ms, 13268ms total) +T4E58 4252:149 JLINK_Reset() -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDFC)Reset: Halt core after reset via DEMCR.VC_CORERESET. >0x35 TIF>Reset: Reset device via AIRCR.SYSRESETREQ. -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000ED0C) >0x0D TIF> >0x28 TIF> -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDFC) + -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0088ms, 13356ms total) +T4E58 4252:237 JLINK_Halt() returns 0x00 (0000ms, 13356ms total) +T4E58 4252:237 JLINK_ReadMemU32(0xE000EDF0, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - Data: 03 00 03 00 returns 0x01 (0001ms, 13357ms total) +T4E58 4252:238 JLINK_WriteU32(0xE000EDF0, 0xA05F0003) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) returns 0x00 (0002ms, 13359ms total) +T4E58 4252:240 JLINK_WriteU32(0xE000EDFC, 0x01000000) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) returns 0x00 (0001ms, 13360ms total) +T4E58 4252:295 JLINK_GetHWStatus(...) returns 0x00 (0000ms, 13360ms total) +T4E58 4252:318 JLINK_GetNumBPUnits(Type = 0xFFFFFF00) returns 0x06 (0000ms, 13360ms total) +T4E58 4252:318 JLINK_GetNumBPUnits(Type = 0xF0) returns 0x2000 (0000ms, 13360ms total) +T4E58 4252:318 JLINK_GetNumWPUnits() returns 0x04 (0000ms, 13360ms total) +T4E58 4252:337 JLINK_GetSpeed() returns 0x7D0 (0000ms, 13360ms total) +T4E58 4252:358 JLINK_ReadMemU32(0xE000E004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000E004) - Data: 01 00 00 00 returns 0x01 (0001ms, 13361ms total) +T4E58 4252:359 JLINK_ReadMemU32(0xE000E004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000E004) - Data: 01 00 00 00 returns 0x01 (0000ms, 13361ms total) +T4E58 4252:360 JLINK_WriteMemEx(0xE0001000, 0x001C Bytes, ..., Flags = 0x02000004) - Data: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... -- CPU_WriteMem(28 bytes @ 0xE0001000) returns 0x1C (0001ms, 13362ms total) +T4E58 4252:361 JLINK_Halt() returns 0x00 (0000ms, 13362ms total) +T4E58 4252:361 JLINK_IsHalted() returns TRUE (0000ms, 13362ms total) +T4E58 4252:366 JLINK_WriteMem(0x20000000, 0x0164 Bytes, ...) - Data: 00 BE 0A E0 0D 78 2D 06 68 40 08 24 40 00 00 D3 ... -- CPU_WriteMem(356 bytes @ 0x20000000) returns 0x164 (0004ms, 13366ms total) +T4E58 4252:370 JLINK_WriteReg(R0, 0x08000000) returns 0x00 (0000ms, 13366ms total) +T4E58 4252:370 JLINK_WriteReg(R1, 0x00B71B00) returns 0x00 (0000ms, 13366ms total) +T4E58 4252:370 JLINK_WriteReg(R2, 0x00000001) returns 0x00 (0000ms, 13366ms total) +T4E58 4252:370 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 13366ms total) +T4E58 4252:370 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 13366ms total) +T4E58 4252:370 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 13366ms total) +T4E58 4252:370 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 13366ms total) +T4E58 4252:370 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 13366ms total) +T4E58 4252:370 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 13366ms total) +T4E58 4252:370 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 13366ms total) +T4E58 4252:370 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0001ms, 13367ms total) +T4E58 4252:371 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 13367ms total) +T4E58 4252:371 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 13367ms total) +T4E58 4252:371 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 13367ms total) +T4E58 4252:371 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 13367ms total) +T4E58 4252:371 JLINK_WriteReg(R15 (PC), 0x20000038) returns 0x00 (0000ms, 13367ms total) +T4E58 4252:371 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 13367ms total) +T4E58 4252:371 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 13367ms total) +T4E58 4252:371 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 13367ms total) +T4E58 4252:371 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 13367ms total) +T4E58 4252:371 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) -- CPU_ReadMem(2 bytes @ 0x20000000) returns 0x00000001 (0001ms, 13368ms total) +T4E58 4252:372 JLINK_Go() -- CPU_WriteMem(2 bytes @ 0x20000000) -- CPU_ReadMem(4 bytes @ 0xE0001000) -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) -- CPU_WriteMem(4 bytes @ 0xE0001004) (0009ms, 13377ms total) +T4E58 4252:381 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 13382ms total) +T4E58 4252:386 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 13377ms total) +T4E58 4252:386 JLINK_ClrBPEx(BPHandle = 0x00000001) returns 0x00 (0000ms, 13377ms total) +T4E58 4252:386 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 13377ms total) +T4E58 4252:389 JLINK_WriteReg(R0, 0x08000000) returns 0x00 (0000ms, 13377ms total) +T4E58 4252:389 JLINK_WriteReg(R1, 0x00B71B00) returns 0x00 (0000ms, 13377ms total) +T4E58 4252:389 JLINK_WriteReg(R2, 0x00000001) returns 0x00 (0000ms, 13377ms total) +T4E58 4252:389 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 13377ms total) +T4E58 4252:389 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 13377ms total) +T4E58 4252:389 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0001ms, 13378ms total) +T4E58 4252:390 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 13378ms total) +T4E58 4252:390 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 13378ms total) +T4E58 4252:390 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 13378ms total) +T4E58 4252:390 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 13378ms total) +T4E58 4252:390 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 13378ms total) +T4E58 4252:390 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 13378ms total) +T4E58 4252:390 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 13378ms total) +T4E58 4252:390 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 13378ms total) +T4E58 4252:390 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 13378ms total) +T4E58 4252:390 JLINK_WriteReg(R15 (PC), 0x2000007C) returns 0x00 (0000ms, 13378ms total) +T4E58 4252:390 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 13378ms total) +T4E58 4252:390 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 13378ms total) +T4E58 4252:390 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 13378ms total) +T4E58 4252:390 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 13378ms total) +T4E58 4252:390 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000002 (0000ms, 13378ms total) +T4E58 4252:390 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 13382ms total) +T4E58 4252:394 JLINK_IsHalted() returns FALSE (0001ms, 13383ms total) +T4E58 4252:525 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 13387ms total) +T4E58 4252:530 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 13382ms total) +T4E58 4252:530 JLINK_ClrBPEx(BPHandle = 0x00000002) returns 0x00 (0000ms, 13382ms total) +T4E58 4252:530 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 13382ms total) +T4E58 4252:585 JLINK_WriteReg(R0, 0x00000001) returns 0x00 (0000ms, 13382ms total) +T4E58 4252:585 JLINK_WriteReg(R1, 0x00B71B00) returns 0x00 (0000ms, 13382ms total) +T4E58 4252:585 JLINK_WriteReg(R2, 0x00000001) returns 0x00 (0000ms, 13382ms total) +T4E58 4252:585 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 13382ms total) +T4E58 4252:585 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 13382ms total) +T4E58 4252:585 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 13382ms total) +T4E58 4252:585 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 13382ms total) +T4E58 4252:585 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 13382ms total) +T4E58 4252:585 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0001ms, 13383ms total) +T4E58 4252:586 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 13383ms total) +T4E58 4252:586 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 13383ms total) +T4E58 4252:586 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 13383ms total) +T4E58 4252:586 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 13383ms total) +T4E58 4252:586 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 13383ms total) +T4E58 4252:586 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 13383ms total) +T4E58 4252:586 JLINK_WriteReg(R15 (PC), 0x2000006A) returns 0x00 (0000ms, 13383ms total) +T4E58 4252:586 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 13383ms total) +T4E58 4252:586 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 13383ms total) +T4E58 4252:586 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0001ms, 13384ms total) +T4E58 4252:587 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 13384ms total) +T4E58 4252:587 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000003 (0000ms, 13384ms total) +T4E58 4252:587 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 13387ms total) +T4E58 4252:590 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 13392ms total) +T4E58 4252:595 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 13387ms total) +T4E58 4252:595 JLINK_ClrBPEx(BPHandle = 0x00000003) returns 0x00 (0000ms, 13387ms total) +T4E58 4252:595 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 13387ms total) +T4E58 4252:613 JLINK_WriteMem(0x20000000, 0x0164 Bytes, ...) - Data: 00 BE 0A E0 0D 78 2D 06 68 40 08 24 40 00 00 D3 ... -- CPU_WriteMem(356 bytes @ 0x20000000) returns 0x164 (0004ms, 13391ms total) +T4E58 4252:617 JLINK_WriteReg(R0, 0x08000000) returns 0x00 (0000ms, 13391ms total) +T4E58 4252:617 JLINK_WriteReg(R1, 0x00B71B00) returns 0x00 (0000ms, 13391ms total) +T4E58 4252:617 JLINK_WriteReg(R2, 0x00000002) returns 0x00 (0000ms, 13391ms total) +T4E58 4252:617 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 13391ms total) +T4E58 4252:617 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 13391ms total) +T4E58 4252:617 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 13391ms total) +T4E58 4252:617 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 13391ms total) +T4E58 4252:617 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0001ms, 13392ms total) +T4E58 4252:618 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 13392ms total) +T4E58 4252:618 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 13392ms total) +T4E58 4252:618 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 13392ms total) +T4E58 4252:618 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 13392ms total) +T4E58 4252:618 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 13392ms total) +T4E58 4252:618 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 13392ms total) +T4E58 4252:618 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 13392ms total) +T4E58 4252:618 JLINK_WriteReg(R15 (PC), 0x20000038) returns 0x00 (0000ms, 13392ms total) +T4E58 4252:618 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 13392ms total) +T4E58 4252:618 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 13392ms total) +T4E58 4252:618 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 13392ms total) +T4E58 4252:618 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 13392ms total) +T4E58 4252:619 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) -- CPU_ReadMem(2 bytes @ 0x20000000) returns 0x00000004 (0000ms, 13393ms total) +T4E58 4252:620 JLINK_Go() -- CPU_WriteMem(2 bytes @ 0x20000000) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0005ms, 13399ms total) +T4E58 4252:625 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 13405ms total) +T4E58 4252:631 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 13399ms total) +T4E58 4252:631 JLINK_ClrBPEx(BPHandle = 0x00000004) returns 0x00 (0000ms, 13399ms total) +T4E58 4252:631 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 13399ms total) +T4E58 4252:633 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: B8 23 00 20 B9 02 00 08 CF 9F 00 08 29 7E 00 08 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 13405ms total) +T4E58 4252:639 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 11 46 FF F7 E9 FF 14 F0 4F FE 01 F0 BD FC 03 B4 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0004ms, 13409ms total) +T4E58 4252:643 JLINK_WriteReg(R0, 0x08000000) returns 0x00 (0000ms, 13409ms total) +T4E58 4252:643 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 13409ms total) +T4E58 4252:643 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 13409ms total) +T4E58 4252:643 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 13409ms total) +T4E58 4252:643 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 13409ms total) +T4E58 4252:643 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 13409ms total) +T4E58 4252:643 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 13409ms total) +T4E58 4252:643 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 13409ms total) +T4E58 4252:643 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0001ms, 13410ms total) +T4E58 4252:644 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 13410ms total) +T4E58 4252:644 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 13410ms total) +T4E58 4252:644 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 13410ms total) +T4E58 4252:644 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 13410ms total) +T4E58 4252:644 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 13410ms total) +T4E58 4252:644 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 13410ms total) +T4E58 4252:644 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 13410ms total) +T4E58 4252:644 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0001ms, 13411ms total) +T4E58 4252:645 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 13411ms total) +T4E58 4252:645 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 13411ms total) +T4E58 4252:645 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 13411ms total) +T4E58 4252:645 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000005 (0000ms, 13411ms total) +T4E58 4252:645 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 13414ms total) +T4E58 4252:648 JLINK_IsHalted() returns FALSE (0002ms, 13416ms total) +T4E58 4252:667 JLINK_IsHalted() returns FALSE (0001ms, 13415ms total) +T4E58 4252:670 JLINK_IsHalted() returns FALSE (0000ms, 13414ms total) +T4E58 4252:678 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 13419ms total) +T4E58 4252:683 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 13414ms total) +T4E58 4252:683 JLINK_ClrBPEx(BPHandle = 0x00000005) returns 0x00 (0000ms, 13414ms total) +T4E58 4252:683 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 13414ms total) +T4E58 4252:684 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 10 68 75 29 31 46 16 A5 10 D0 00 F0 84 FB 00 28 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0007ms, 13421ms total) +T4E58 4252:691 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: FF 30 0A 90 00 20 0C 90 06 48 78 44 06 90 06 48 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0003ms, 13424ms total) +T4E58 4252:694 JLINK_WriteReg(R0, 0x08000400) returns 0x00 (0000ms, 13424ms total) +T4E58 4252:694 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 13424ms total) +T4E58 4252:694 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 13424ms total) +T4E58 4252:694 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 13424ms total) +T4E58 4252:694 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0001ms, 13425ms total) +T4E58 4252:695 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 13425ms total) +T4E58 4252:695 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 13425ms total) +T4E58 4252:695 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 13425ms total) +T4E58 4252:695 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 13425ms total) +T4E58 4252:695 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 13425ms total) +T4E58 4252:695 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 13425ms total) +T4E58 4252:695 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 13425ms total) +T4E58 4252:695 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 13425ms total) +T4E58 4252:695 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 13425ms total) +T4E58 4252:695 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 13425ms total) +T4E58 4252:695 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 13425ms total) +T4E58 4252:695 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 13425ms total) +T4E58 4252:695 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0001ms, 13426ms total) +T4E58 4252:696 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 13426ms total) +T4E58 4252:696 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 13426ms total) +T4E58 4252:696 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000006 (0000ms, 13426ms total) +T4E58 4252:696 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 13429ms total) +T4E58 4252:699 JLINK_IsHalted() returns FALSE (0001ms, 13430ms total) +T4E58 4252:709 JLINK_IsHalted() returns FALSE (0001ms, 13430ms total) +T4E58 4252:712 JLINK_IsHalted() returns FALSE (0000ms, 13429ms total) +T4E58 4252:715 JLINK_IsHalted() returns FALSE (0001ms, 13430ms total) +T4E58 4252:718 JLINK_IsHalted() returns FALSE (0000ms, 13429ms total) +T4E58 4252:724 JLINK_IsHalted() returns FALSE (0001ms, 13430ms total) +T4E58 4252:727 JLINK_IsHalted() returns FALSE (0000ms, 13429ms total) +T4E58 4252:730 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 13434ms total) +T4E58 4252:735 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 13429ms total) +T4E58 4252:735 JLINK_ClrBPEx(BPHandle = 0x00000006) returns 0x00 (0000ms, 13429ms total) +T4E58 4252:735 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 13429ms total) +T4E58 4252:737 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 06 E0 21 07 02 D5 A0 F8 00 80 01 E0 C0 F8 00 80 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0005ms, 13434ms total) +T4E58 4252:742 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 89 00 28 BF 40 F8 04 2B 08 BF 70 47 48 BF 20 F8 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0004ms, 13438ms total) +T4E58 4252:746 JLINK_WriteReg(R0, 0x08000800) returns 0x00 (0000ms, 13438ms total) +T4E58 4252:746 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 13438ms total) +T4E58 4252:746 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 13438ms total) +T4E58 4252:746 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 13438ms total) +T4E58 4252:746 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 13438ms total) +T4E58 4252:746 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 13438ms total) +T4E58 4252:746 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 13438ms total) +T4E58 4252:746 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 13438ms total) +T4E58 4252:746 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 13438ms total) +T4E58 4252:746 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 13438ms total) +T4E58 4252:746 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 13438ms total) +T4E58 4252:746 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 13438ms total) +T4E58 4252:746 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 13438ms total) +T4E58 4252:746 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0001ms, 13439ms total) +T4E58 4252:747 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 13439ms total) +T4E58 4252:747 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 13439ms total) +T4E58 4252:747 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 13439ms total) +T4E58 4252:747 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 13439ms total) +T4E58 4252:747 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 13439ms total) +T4E58 4252:747 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 13439ms total) +T4E58 4252:747 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000007 (0000ms, 13439ms total) +T4E58 4252:747 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 13442ms total) +T4E58 4252:750 JLINK_IsHalted() returns FALSE (0001ms, 13443ms total) +T4E58 4252:758 JLINK_IsHalted() returns FALSE (0001ms, 13443ms total) +T4E58 4252:761 JLINK_IsHalted() returns FALSE (0000ms, 13442ms total) +T4E58 4252:763 JLINK_IsHalted() returns FALSE (0000ms, 13442ms total) +T4E58 4252:769 JLINK_IsHalted() returns FALSE (0000ms, 13442ms total) +T4E58 4252:772 JLINK_IsHalted() returns FALSE (0000ms, 13442ms total) +T4E58 4252:774 JLINK_IsHalted() returns FALSE (0000ms, 13442ms total) +T4E58 4252:776 JLINK_IsHalted() returns FALSE (0001ms, 13443ms total) +T4E58 4252:780 JLINK_IsHalted() returns FALSE (0001ms, 13443ms total) +T4E58 4252:787 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 13447ms total) +T4E58 4252:792 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 13442ms total) +T4E58 4252:792 JLINK_ClrBPEx(BPHandle = 0x00000007) returns 0x00 (0000ms, 13442ms total) +T4E58 4252:792 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 13442ms total) +T4E58 4252:793 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 06 E0 13 06 03 D5 C2 17 C1 E9 00 02 00 E0 08 60 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 13448ms total) +T4E58 4252:799 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 5A B1 C3 68 01 68 43 B9 83 68 8B 42 05 D0 49 1E ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0004ms, 13452ms total) +T4E58 4252:803 JLINK_WriteReg(R0, 0x08000C00) returns 0x00 (0000ms, 13452ms total) +T4E58 4252:803 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 13452ms total) +T4E58 4252:803 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 13452ms total) +T4E58 4252:803 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 13452ms total) +T4E58 4252:803 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 13452ms total) +T4E58 4252:803 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 13452ms total) +T4E58 4252:803 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 13452ms total) +T4E58 4252:803 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 13452ms total) +T4E58 4252:803 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 13452ms total) +T4E58 4252:803 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0001ms, 13453ms total) +T4E58 4252:804 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 13453ms total) +T4E58 4252:804 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 13453ms total) +T4E58 4252:804 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 13453ms total) +T4E58 4252:804 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 13453ms total) +T4E58 4252:804 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 13453ms total) +T4E58 4252:804 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 13453ms total) +T4E58 4252:804 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 13453ms total) +T4E58 4252:804 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 13453ms total) +T4E58 4252:804 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 13453ms total) +T4E58 4252:804 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 13453ms total) +T4E58 4252:804 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000008 (0000ms, 13453ms total) +T4E58 4252:804 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 13457ms total) +T4E58 4252:808 JLINK_IsHalted() returns FALSE (0001ms, 13458ms total) +T4E58 4252:812 JLINK_IsHalted() returns FALSE (0001ms, 13458ms total) +T4E58 4252:819 JLINK_IsHalted() returns FALSE (0001ms, 13458ms total) +T4E58 4252:822 JLINK_IsHalted() returns FALSE (0001ms, 13458ms total) +T4E58 4252:825 JLINK_IsHalted() returns FALSE (0000ms, 13457ms total) +T4E58 4252:827 JLINK_IsHalted() returns FALSE (0001ms, 13458ms total) +T4E58 4252:836 JLINK_IsHalted() returns FALSE (0001ms, 13458ms total) +T4E58 4252:841 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0004ms, 13461ms total) +T4E58 4252:845 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 13457ms total) +T4E58 4252:845 JLINK_ClrBPEx(BPHandle = 0x00000008) returns 0x00 (0000ms, 13457ms total) +T4E58 4252:847 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 13459ms total) +T4E58 4252:847 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 6D 1C DE E7 4A 46 00 DA 69 42 06 A8 00 F0 98 FD ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 13465ms total) +T4E58 4252:853 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 17 46 0C F1 30 0C 08 F8 01 CD EE E7 A8 F1 01 00 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0004ms, 13469ms total) +T4E58 4252:857 JLINK_WriteReg(R0, 0x08001000) returns 0x00 (0000ms, 13469ms total) +T4E58 4252:857 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 13469ms total) +T4E58 4252:857 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 13469ms total) +T4E58 4252:857 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 13469ms total) +T4E58 4252:857 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0001ms, 13470ms total) +T4E58 4252:858 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 13470ms total) +T4E58 4252:858 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 13470ms total) +T4E58 4252:858 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 13470ms total) +T4E58 4252:858 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 13470ms total) +T4E58 4252:858 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 13470ms total) +T4E58 4252:858 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 13470ms total) +T4E58 4252:858 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 13470ms total) +T4E58 4252:858 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 13470ms total) +T4E58 4252:858 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0002ms, 13472ms total) +T4E58 4252:860 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 13472ms total) +T4E58 4252:860 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 13472ms total) +T4E58 4252:860 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 13472ms total) +T4E58 4252:860 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 13472ms total) +T4E58 4252:860 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 13472ms total) +T4E58 4252:860 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 13472ms total) +T4E58 4252:860 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000009 (0000ms, 13472ms total) +T4E58 4252:860 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 13476ms total) +T4E58 4252:864 JLINK_IsHalted() returns FALSE (0001ms, 13477ms total) +T4E58 4252:871 JLINK_IsHalted() returns FALSE (0001ms, 13477ms total) +T4E58 4252:886 JLINK_IsHalted() returns FALSE (0001ms, 13477ms total) +T4E58 4252:889 JLINK_IsHalted() returns FALSE (0001ms, 13477ms total) +T4E58 4252:897 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 13481ms total) +T4E58 4252:902 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 13476ms total) +T4E58 4252:902 JLINK_ClrBPEx(BPHandle = 0x00000009) returns 0x00 (0000ms, 13476ms total) +T4E58 4252:902 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 13476ms total) +T4E58 4252:903 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: D0 70 01 EA 60 00 81 15 01 29 01 DD 4F F0 FF 31 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 13482ms total) +T4E58 4252:909 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: FF 32 E9 E7 2D E9 F3 4F 4F F0 00 0A 0C 46 56 46 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0003ms, 13485ms total) +T4E58 4252:912 JLINK_WriteReg(R0, 0x08001400) returns 0x00 (0000ms, 13485ms total) +T4E58 4252:913 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 13486ms total) +T4E58 4252:913 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 13486ms total) +T4E58 4252:913 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 13486ms total) +T4E58 4252:913 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 13486ms total) +T4E58 4252:913 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 13486ms total) +T4E58 4252:913 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 13486ms total) +T4E58 4252:913 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 13486ms total) +T4E58 4252:913 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 13486ms total) +T4E58 4252:913 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 13486ms total) +T4E58 4252:913 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0001ms, 13487ms total) +T4E58 4252:914 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 13487ms total) +T4E58 4252:914 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 13487ms total) +T4E58 4252:914 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 13487ms total) +T4E58 4252:914 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 13487ms total) +T4E58 4252:914 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 13487ms total) +T4E58 4252:914 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 13487ms total) +T4E58 4252:914 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 13487ms total) +T4E58 4252:914 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 13487ms total) +T4E58 4252:914 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 13487ms total) +T4E58 4252:914 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000000A (0000ms, 13487ms total) +T4E58 4252:914 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 13490ms total) +T4E58 4252:917 JLINK_IsHalted() returns FALSE (0001ms, 13491ms total) +T4E58 4252:932 JLINK_IsHalted() returns FALSE (0001ms, 13491ms total) +T4E58 4252:937 JLINK_IsHalted() returns FALSE (0001ms, 13491ms total) +T4E58 4252:946 JLINK_IsHalted() returns FALSE (0000ms, 13490ms total) +T4E58 4252:949 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0004ms, 13494ms total) +T4E58 4252:953 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0001ms, 13491ms total) +T4E58 4252:954 JLINK_ClrBPEx(BPHandle = 0x0000000A) returns 0x00 (0000ms, 13491ms total) +T4E58 4252:954 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 13491ms total) +T4E58 4252:955 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: F6 E0 6F 28 48 D0 08 DC 66 28 1D D0 67 28 1B D0 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 13497ms total) +T4E58 4252:961 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: C0 09 AC E8 C0 09 8D 46 70 47 00 00 10 B5 00 F0 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0003ms, 13500ms total) +T4E58 4252:964 JLINK_WriteReg(R0, 0x08001800) returns 0x00 (0001ms, 13501ms total) +T4E58 4252:965 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 13501ms total) +T4E58 4252:965 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 13501ms total) +T4E58 4252:965 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 13501ms total) +T4E58 4252:965 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 13501ms total) +T4E58 4252:965 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 13501ms total) +T4E58 4252:965 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 13501ms total) +T4E58 4252:965 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 13501ms total) +T4E58 4252:965 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 13501ms total) +T4E58 4252:965 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 13501ms total) +T4E58 4252:965 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 13501ms total) +T4E58 4252:965 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 13501ms total) +T4E58 4252:965 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 13501ms total) +T4E58 4252:965 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 13501ms total) +T4E58 4252:965 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 13501ms total) +T4E58 4252:965 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 13501ms total) +T4E58 4252:965 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 13501ms total) +T4E58 4252:965 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 13501ms total) +T4E58 4252:965 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 13501ms total) +T4E58 4252:965 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 13501ms total) +T4E58 4252:966 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000000B (0000ms, 13502ms total) +T4E58 4252:966 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 13505ms total) +T4E58 4252:969 JLINK_IsHalted() returns FALSE (0000ms, 13505ms total) +T4E58 4252:979 JLINK_IsHalted() returns FALSE (0000ms, 13505ms total) +T4E58 4252:982 JLINK_IsHalted() returns FALSE (0000ms, 13505ms total) +T4E58 4252:984 JLINK_IsHalted() returns FALSE (0000ms, 13505ms total) +T4E58 4252:992 JLINK_IsHalted() returns FALSE (0001ms, 13506ms total) +T4E58 4252:995 JLINK_IsHalted() returns FALSE (0001ms, 13506ms total) +T4E58 4252:998 JLINK_IsHalted() returns FALSE (0001ms, 13506ms total) +T4E58 4253:010 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 13511ms total) +T4E58 4253:016 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 13505ms total) +T4E58 4253:016 JLINK_ClrBPEx(BPHandle = 0x0000000B) returns 0x00 (0000ms, 13505ms total) +T4E58 4253:016 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 13505ms total) +T4E58 4253:018 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: B8 F1 00 0F 03 A8 02 D0 00 F0 D9 FA 01 E0 00 F0 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0007ms, 13512ms total) +T4E58 4253:025 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 57 72 0C FB 08 F7 34 BF A2 EB C7 02 B2 EB C7 02 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0003ms, 13515ms total) +T4E58 4253:028 JLINK_WriteReg(R0, 0x08001C00) returns 0x00 (0000ms, 13515ms total) +T4E58 4253:028 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 13515ms total) +T4E58 4253:028 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0001ms, 13516ms total) +T4E58 4253:029 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 13516ms total) +T4E58 4253:029 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 13516ms total) +T4E58 4253:029 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 13516ms total) +T4E58 4253:029 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 13516ms total) +T4E58 4253:029 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 13516ms total) +T4E58 4253:029 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 13516ms total) +T4E58 4253:029 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 13516ms total) +T4E58 4253:029 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 13516ms total) +T4E58 4253:029 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 13516ms total) +T4E58 4253:029 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 13516ms total) +T4E58 4253:029 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 13516ms total) +T4E58 4253:029 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 13516ms total) +T4E58 4253:029 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 13516ms total) +T4E58 4253:029 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 13516ms total) +T4E58 4253:029 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0001ms, 13517ms total) +T4E58 4253:030 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 13517ms total) +T4E58 4253:030 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 13517ms total) +T4E58 4253:030 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000000C (0000ms, 13517ms total) +T4E58 4253:030 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 13521ms total) +T4E58 4253:034 JLINK_IsHalted() returns FALSE (0001ms, 13522ms total) +T4E58 4253:042 JLINK_IsHalted() returns FALSE (0001ms, 13522ms total) +T4E58 4253:045 JLINK_IsHalted() returns FALSE (0001ms, 13522ms total) +T4E58 4253:053 JLINK_IsHalted() returns FALSE (0000ms, 13521ms total) +T4E58 4253:055 JLINK_IsHalted() returns FALSE (0000ms, 13521ms total) +T4E58 4253:057 JLINK_IsHalted() returns FALSE (0001ms, 13522ms total) +T4E58 4253:061 JLINK_IsHalted() returns FALSE (0000ms, 13521ms total) +T4E58 4253:068 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 13527ms total) +T4E58 4253:074 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 13521ms total) +T4E58 4253:074 JLINK_ClrBPEx(BPHandle = 0x0000000C) returns 0x00 (0000ms, 13521ms total) +T4E58 4253:074 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 13521ms total) +T4E58 4253:075 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 62 46 39 46 4E EB 0E 0E 4F F0 00 0B 00 18 52 41 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0005ms, 13526ms total) +T4E58 4253:080 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 00 06 1E EB 07 4E 4C EB 17 4B 18 EB 0B 08 40 F1 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0004ms, 13530ms total) +T4E58 4253:084 JLINK_WriteReg(R0, 0x08002000) returns 0x00 (0000ms, 13530ms total) +T4E58 4253:084 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 13530ms total) +T4E58 4253:084 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 13530ms total) +T4E58 4253:084 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 13530ms total) +T4E58 4253:084 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 13530ms total) +T4E58 4253:084 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 13530ms total) +T4E58 4253:084 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 13530ms total) +T4E58 4253:084 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 13530ms total) +T4E58 4253:084 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 13530ms total) +T4E58 4253:084 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 13530ms total) +T4E58 4253:084 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 13530ms total) +T4E58 4253:084 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 13530ms total) +T4E58 4253:084 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 13530ms total) +T4E58 4253:084 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 13530ms total) +T4E58 4253:084 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 13530ms total) +T4E58 4253:084 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 13530ms total) +T4E58 4253:084 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 13530ms total) +T4E58 4253:084 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0001ms, 13531ms total) +T4E58 4253:085 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 13531ms total) +T4E58 4253:085 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 13531ms total) +T4E58 4253:085 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000000D (0000ms, 13531ms total) +T4E58 4253:085 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 13534ms total) +T4E58 4253:088 JLINK_IsHalted() returns FALSE (0001ms, 13535ms total) +T4E58 4253:101 JLINK_IsHalted() returns FALSE (0001ms, 13535ms total) +T4E58 4253:104 JLINK_IsHalted() returns FALSE (0001ms, 13535ms total) +T4E58 4253:107 JLINK_IsHalted() returns FALSE (0001ms, 13535ms total) +T4E58 4253:110 JLINK_IsHalted() returns FALSE (0001ms, 13535ms total) +T4E58 4253:116 JLINK_IsHalted() returns FALSE (0001ms, 13535ms total) +T4E58 4253:119 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 13539ms total) +T4E58 4253:124 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 13534ms total) +T4E58 4253:124 JLINK_ClrBPEx(BPHandle = 0x0000000D) returns 0x00 (0000ms, 13534ms total) +T4E58 4253:124 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 13534ms total) +T4E58 4253:128 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 48 BF 70 47 B6 19 52 41 41 EB 01 01 A3 F1 01 03 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 13541ms total) +T4E58 4253:134 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 07 F0 A6 FB B5 84 A7 71 BD E8 F0 87 98 F8 00 00 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0004ms, 13545ms total) +T4E58 4253:138 JLINK_WriteReg(R0, 0x08002400) returns 0x00 (0000ms, 13545ms total) +T4E58 4253:138 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 13545ms total) +T4E58 4253:138 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 13545ms total) +T4E58 4253:138 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 13545ms total) +T4E58 4253:138 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 13545ms total) +T4E58 4253:138 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 13545ms total) +T4E58 4253:138 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 13545ms total) +T4E58 4253:138 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 13545ms total) +T4E58 4253:138 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 13545ms total) +T4E58 4253:138 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0001ms, 13546ms total) +T4E58 4253:139 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 13546ms total) +T4E58 4253:139 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 13546ms total) +T4E58 4253:139 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 13546ms total) +T4E58 4253:139 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 13546ms total) +T4E58 4253:139 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 13546ms total) +T4E58 4253:139 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 13546ms total) +T4E58 4253:139 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 13546ms total) +T4E58 4253:139 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 13546ms total) +T4E58 4253:139 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 13546ms total) +T4E58 4253:139 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 13546ms total) +T4E58 4253:139 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000000E (0000ms, 13546ms total) +T4E58 4253:139 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 13549ms total) +T4E58 4253:142 JLINK_IsHalted() returns FALSE (0001ms, 13550ms total) +T4E58 4253:150 JLINK_IsHalted() returns FALSE (0000ms, 13549ms total) +T4E58 4253:153 JLINK_IsHalted() returns FALSE (0000ms, 13549ms total) +T4E58 4253:156 JLINK_IsHalted() returns FALSE (0000ms, 13549ms total) +T4E58 4253:165 JLINK_IsHalted() returns FALSE (0001ms, 13550ms total) +T4E58 4253:168 JLINK_IsHalted() returns FALSE (0001ms, 13550ms total) +T4E58 4253:171 JLINK_IsHalted() returns FALSE (0001ms, 13550ms total) +T4E58 4253:179 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 13554ms total) +T4E58 4253:184 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 13549ms total) +T4E58 4253:184 JLINK_ClrBPEx(BPHandle = 0x0000000E) returns 0x00 (0000ms, 13549ms total) +T4E58 4253:184 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 13549ms total) +T4E58 4253:185 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 2B 78 13 B1 02 2B 07 D0 08 E0 21 F0 02 00 8D F8 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 13555ms total) +T4E58 4253:191 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 4E 10 4A 06 62 6A 0D D4 12 F5 FA 6F 08 DA 2A 7B ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0003ms, 13558ms total) +T4E58 4253:194 JLINK_WriteReg(R0, 0x08002800) returns 0x00 (0000ms, 13558ms total) +T4E58 4253:194 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 13558ms total) +T4E58 4253:194 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 13558ms total) +T4E58 4253:194 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 13558ms total) +T4E58 4253:194 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 13558ms total) +T4E58 4253:194 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 13558ms total) +T4E58 4253:194 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 13558ms total) +T4E58 4253:194 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 13558ms total) +T4E58 4253:194 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0001ms, 13559ms total) +T4E58 4253:195 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 13559ms total) +T4E58 4253:195 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 13559ms total) +T4E58 4253:195 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 13559ms total) +T4E58 4253:195 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 13559ms total) +T4E58 4253:195 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 13559ms total) +T4E58 4253:195 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 13559ms total) +T4E58 4253:195 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 13559ms total) +T4E58 4253:195 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 13559ms total) +T4E58 4253:195 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 13559ms total) +T4E58 4253:195 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 13559ms total) +T4E58 4253:195 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 13559ms total) +T4E58 4253:195 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000000F (0000ms, 13559ms total) +T4E58 4253:195 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 13563ms total) +T4E58 4253:199 JLINK_IsHalted() returns FALSE (0002ms, 13565ms total) +T4E58 4253:210 JLINK_IsHalted() returns FALSE (0001ms, 13564ms total) +T4E58 4253:213 JLINK_IsHalted() returns FALSE (0001ms, 13564ms total) +T4E58 4253:216 JLINK_IsHalted() returns FALSE (0001ms, 13564ms total) +T4E58 4253:224 JLINK_IsHalted() returns FALSE (0001ms, 13564ms total) +T4E58 4253:227 JLINK_IsHalted() returns FALSE (0000ms, 13563ms total) +T4E58 4253:230 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0004ms, 13567ms total) +T4E58 4253:234 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 13563ms total) +T4E58 4253:234 JLINK_ClrBPEx(BPHandle = 0x0000000F) returns 0x00 (0000ms, 13563ms total) +T4E58 4253:234 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 13563ms total) +T4E58 4253:236 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 92 B2 2A 85 B2 F5 96 7F 0B D9 7B 4A 2E 85 20 F0 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 13569ms total) +T4E58 4253:242 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 6A 75 2C 72 0A E0 DF 06 08 D4 D7 06 06 D4 06 F0 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0004ms, 13573ms total) +T4E58 4253:246 JLINK_WriteReg(R0, 0x08002C00) returns 0x00 (0000ms, 13573ms total) +T4E58 4253:246 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 13573ms total) +T4E58 4253:246 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 13573ms total) +T4E58 4253:246 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 13573ms total) +T4E58 4253:246 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 13573ms total) +T4E58 4253:246 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 13573ms total) +T4E58 4253:246 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 13573ms total) +T4E58 4253:246 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 13573ms total) +T4E58 4253:246 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0001ms, 13574ms total) +T4E58 4253:247 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 13574ms total) +T4E58 4253:247 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 13574ms total) +T4E58 4253:247 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 13574ms total) +T4E58 4253:247 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 13574ms total) +T4E58 4253:247 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 13574ms total) +T4E58 4253:247 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 13574ms total) +T4E58 4253:247 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 13574ms total) +T4E58 4253:247 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 13574ms total) +T4E58 4253:247 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 13574ms total) +T4E58 4253:247 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 13574ms total) +T4E58 4253:247 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 13574ms total) +T4E58 4253:247 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000010 (0000ms, 13574ms total) +T4E58 4253:248 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 13577ms total) +T4E58 4253:250 JLINK_IsHalted() returns FALSE (0001ms, 13578ms total) +T4E58 4253:262 JLINK_IsHalted() returns FALSE (0001ms, 13578ms total) +T4E58 4253:265 JLINK_IsHalted() returns FALSE (0002ms, 13579ms total) +T4E58 4253:274 JLINK_IsHalted() returns FALSE (0001ms, 13578ms total) +T4E58 4253:280 JLINK_IsHalted() returns FALSE (0000ms, 13577ms total) +T4E58 4253:290 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 13583ms total) +T4E58 4253:296 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 13577ms total) +T4E58 4253:296 JLINK_ClrBPEx(BPHandle = 0x00000010) returns 0x00 (0000ms, 13577ms total) +T4E58 4253:296 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 13577ms total) +T4E58 4253:298 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 4B 07 15 D5 E8 74 6A 75 E9 75 2C 72 10 E0 C6 07 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0007ms, 13584ms total) +T4E58 4253:305 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 6E 46 02 AF 02 21 28 46 0D F0 3E FA 00 28 F9 D0 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0003ms, 13587ms total) +T4E58 4253:308 JLINK_WriteReg(R0, 0x08003000) returns 0x00 (0000ms, 13587ms total) +T4E58 4253:308 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 13587ms total) +T4E58 4253:308 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 13587ms total) +T4E58 4253:308 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 13587ms total) +T4E58 4253:308 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 13587ms total) +T4E58 4253:308 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 13587ms total) +T4E58 4253:308 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 13587ms total) +T4E58 4253:308 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 13587ms total) +T4E58 4253:308 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 13587ms total) +T4E58 4253:308 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 13587ms total) +T4E58 4253:308 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 13587ms total) +T4E58 4253:308 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0001ms, 13588ms total) +T4E58 4253:309 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 13588ms total) +T4E58 4253:309 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 13588ms total) +T4E58 4253:309 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 13588ms total) +T4E58 4253:309 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 13588ms total) +T4E58 4253:309 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 13588ms total) +T4E58 4253:309 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 13588ms total) +T4E58 4253:309 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 13588ms total) +T4E58 4253:309 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 13588ms total) +T4E58 4253:309 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000011 (0000ms, 13588ms total) +T4E58 4253:309 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 13592ms total) +T4E58 4253:313 JLINK_IsHalted() returns FALSE (0001ms, 13593ms total) +T4E58 4253:326 JLINK_IsHalted() returns FALSE (0001ms, 13593ms total) +T4E58 4253:338 JLINK_IsHalted() returns FALSE (0001ms, 13593ms total) +T4E58 4253:341 JLINK_IsHalted() returns FALSE (0000ms, 13592ms total) +T4E58 4253:344 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0004ms, 13596ms total) +T4E58 4253:348 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 13592ms total) +T4E58 4253:348 JLINK_ClrBPEx(BPHandle = 0x00000011) returns 0x00 (0000ms, 13592ms total) +T4E58 4253:348 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 13592ms total) +T4E58 4253:350 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 81 01 49 09 21 80 46 88 71 BA 01 EB 81 01 49 09 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 13598ms total) +T4E58 4253:356 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 61 11 AC F8 26 10 4F F0 00 02 11 46 94 F8 D8 60 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0003ms, 13601ms total) +T4E58 4253:359 JLINK_WriteReg(R0, 0x08003400) returns 0x00 (0000ms, 13601ms total) +T4E58 4253:359 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 13601ms total) +T4E58 4253:359 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 13601ms total) +T4E58 4253:359 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 13601ms total) +T4E58 4253:359 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0001ms, 13602ms total) +T4E58 4253:360 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 13602ms total) +T4E58 4253:360 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 13602ms total) +T4E58 4253:360 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 13602ms total) +T4E58 4253:360 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 13602ms total) +T4E58 4253:360 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 13602ms total) +T4E58 4253:360 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 13602ms total) +T4E58 4253:360 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 13602ms total) +T4E58 4253:360 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 13602ms total) +T4E58 4253:360 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 13602ms total) +T4E58 4253:360 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 13602ms total) +T4E58 4253:360 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0001ms, 13603ms total) +T4E58 4253:361 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 13603ms total) +T4E58 4253:361 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 13603ms total) +T4E58 4253:361 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 13603ms total) +T4E58 4253:361 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 13603ms total) +T4E58 4253:361 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000012 (0000ms, 13603ms total) +T4E58 4253:361 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 13605ms total) +T4E58 4253:364 JLINK_IsHalted() returns FALSE (0000ms, 13606ms total) +T4E58 4253:371 JLINK_IsHalted() returns FALSE (0001ms, 13607ms total) +T4E58 4253:384 JLINK_IsHalted() returns FALSE (0001ms, 13607ms total) +T4E58 4253:387 JLINK_IsHalted() returns FALSE (0001ms, 13607ms total) +T4E58 4253:400 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 13611ms total) +T4E58 4253:405 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 13606ms total) +T4E58 4253:405 JLINK_ClrBPEx(BPHandle = 0x00000012) returns 0x00 (0000ms, 13606ms total) +T4E58 4253:405 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 13606ms total) +T4E58 4253:407 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 80 58 41 46 48 46 04 F0 70 F8 17 4D 00 24 6E 46 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 13612ms total) +T4E58 4253:413 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 10 20 40 1C 20 71 20 79 08 B1 E1 70 70 BD AA 20 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0004ms, 13616ms total) +T4E58 4253:417 JLINK_WriteReg(R0, 0x08003800) returns 0x00 (0000ms, 13616ms total) +T4E58 4253:417 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 13616ms total) +T4E58 4253:417 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 13616ms total) +T4E58 4253:417 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 13616ms total) +T4E58 4253:417 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 13616ms total) +T4E58 4253:417 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 13616ms total) +T4E58 4253:417 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 13616ms total) +T4E58 4253:417 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 13616ms total) +T4E58 4253:417 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 13616ms total) +T4E58 4253:417 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 13616ms total) +T4E58 4253:417 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 13616ms total) +T4E58 4253:417 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 13616ms total) +T4E58 4253:417 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 13616ms total) +T4E58 4253:417 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 13616ms total) +T4E58 4253:417 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 13616ms total) +T4E58 4253:417 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 13616ms total) +T4E58 4253:418 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 13617ms total) +T4E58 4253:418 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 13617ms total) +T4E58 4253:418 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 13617ms total) +T4E58 4253:418 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 13617ms total) +T4E58 4253:418 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000013 (0000ms, 13617ms total) +T4E58 4253:418 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 13620ms total) +T4E58 4253:421 JLINK_IsHalted() returns FALSE (0000ms, 13620ms total) +T4E58 4253:435 JLINK_IsHalted() returns FALSE (0001ms, 13621ms total) +T4E58 4253:446 JLINK_IsHalted() returns FALSE (0001ms, 13621ms total) +T4E58 4253:449 JLINK_IsHalted() returns FALSE (0000ms, 13620ms total) +T4E58 4253:454 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0007ms, 13627ms total) +T4E58 4253:461 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 13620ms total) +T4E58 4253:462 JLINK_ClrBPEx(BPHandle = 0x00000013) returns 0x00 (0000ms, 13620ms total) +T4E58 4253:462 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 13620ms total) +T4E58 4253:463 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: B8 78 38 B1 16 B1 DD A0 01 F0 20 FC E0 A0 01 F0 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0007ms, 13627ms total) +T4E58 4253:470 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 2B A0 01 F0 D5 FA 2F A0 01 F0 D2 FA 20 A0 01 F0 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0004ms, 13631ms total) +T4E58 4253:474 JLINK_WriteReg(R0, 0x08003C00) returns 0x00 (0000ms, 13631ms total) +T4E58 4253:474 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 13631ms total) +T4E58 4253:474 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 13631ms total) +T4E58 4253:474 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 13631ms total) +T4E58 4253:474 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 13631ms total) +T4E58 4253:474 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 13631ms total) +T4E58 4253:474 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0001ms, 13632ms total) +T4E58 4253:475 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 13632ms total) +T4E58 4253:475 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 13632ms total) +T4E58 4253:475 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 13632ms total) +T4E58 4253:475 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 13632ms total) +T4E58 4253:475 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 13632ms total) +T4E58 4253:475 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 13632ms total) +T4E58 4253:475 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 13632ms total) +T4E58 4253:475 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 13632ms total) +T4E58 4253:475 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 13632ms total) +T4E58 4253:475 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 13632ms total) +T4E58 4253:475 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 13632ms total) +T4E58 4253:475 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 13632ms total) +T4E58 4253:475 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 13632ms total) +T4E58 4253:475 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000014 (0001ms, 13633ms total) +T4E58 4253:476 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 13635ms total) +T4E58 4253:478 JLINK_IsHalted() returns FALSE (0001ms, 13636ms total) +T4E58 4253:489 JLINK_IsHalted() returns FALSE (0001ms, 13636ms total) +T4E58 4253:492 JLINK_IsHalted() returns FALSE (0001ms, 13636ms total) +T4E58 4253:516 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 13641ms total) +T4E58 4253:522 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 13635ms total) +T4E58 4253:522 JLINK_ClrBPEx(BPHandle = 0x00000014) returns 0x00 (0000ms, 13635ms total) +T4E58 4253:522 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 13635ms total) +T4E58 4253:523 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 66 55 56 22 3A 74 72 75 65 00 00 00 1C 17 00 20 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 13641ms total) +T4E58 4253:529 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 2C 00 00 00 22 41 6D 62 69 65 6E 74 54 22 3A 25 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0003ms, 13644ms total) +T4E58 4253:532 JLINK_WriteReg(R0, 0x08004000) returns 0x00 (0000ms, 13644ms total) +T4E58 4253:532 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 13644ms total) +T4E58 4253:532 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 13644ms total) +T4E58 4253:532 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 13644ms total) +T4E58 4253:532 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 13644ms total) +T4E58 4253:532 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 13644ms total) +T4E58 4253:532 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 13644ms total) +T4E58 4253:532 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 13644ms total) +T4E58 4253:532 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 13644ms total) +T4E58 4253:532 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 13644ms total) +T4E58 4253:532 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0001ms, 13645ms total) +T4E58 4253:533 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 13645ms total) +T4E58 4253:533 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 13645ms total) +T4E58 4253:533 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 13645ms total) +T4E58 4253:533 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 13645ms total) +T4E58 4253:533 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 13645ms total) +T4E58 4253:533 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 13645ms total) +T4E58 4253:533 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 13645ms total) +T4E58 4253:533 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 13645ms total) +T4E58 4253:533 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 13645ms total) +T4E58 4253:533 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000015 (0000ms, 13645ms total) +T4E58 4253:533 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0005ms, 13650ms total) +T4E58 4253:538 JLINK_IsHalted() returns FALSE (0001ms, 13651ms total) +T4E58 4253:557 JLINK_IsHalted() returns FALSE (0000ms, 13650ms total) +T4E58 4253:559 JLINK_IsHalted() returns FALSE (0001ms, 13651ms total) +T4E58 4253:574 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 13655ms total) +T4E58 4253:579 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 13650ms total) +T4E58 4253:579 JLINK_ClrBPEx(BPHandle = 0x00000015) returns 0x00 (0000ms, 13650ms total) +T4E58 4253:579 JLINK_ReadReg(R0) returns 0x00000000 (0001ms, 13651ms total) +T4E58 4253:581 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 01 26 78 79 38 B1 16 B1 9F A0 01 F0 1F F8 ED A0 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 13657ms total) +T4E58 4253:587 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 2C 00 00 00 22 42 61 74 74 65 72 79 54 33 22 3A ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0003ms, 13660ms total) +T4E58 4253:590 JLINK_WriteReg(R0, 0x08004400) returns 0x00 (0000ms, 13660ms total) +T4E58 4253:590 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 13660ms total) +T4E58 4253:590 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 13660ms total) +T4E58 4253:590 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 13660ms total) +T4E58 4253:590 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 13660ms total) +T4E58 4253:590 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 13660ms total) +T4E58 4253:590 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 13660ms total) +T4E58 4253:590 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 13660ms total) +T4E58 4253:590 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 13660ms total) +T4E58 4253:590 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0001ms, 13661ms total) +T4E58 4253:591 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 13661ms total) +T4E58 4253:591 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 13661ms total) +T4E58 4253:591 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 13661ms total) +T4E58 4253:591 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 13661ms total) +T4E58 4253:591 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 13661ms total) +T4E58 4253:591 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 13661ms total) +T4E58 4253:591 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 13661ms total) +T4E58 4253:591 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 13661ms total) +T4E58 4253:591 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 13661ms total) +T4E58 4253:591 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 13661ms total) +T4E58 4253:591 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000016 (0000ms, 13661ms total) +T4E58 4253:591 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 13665ms total) +T4E58 4253:595 JLINK_IsHalted() returns FALSE (0001ms, 13666ms total) +T4E58 4253:603 JLINK_IsHalted() returns FALSE (0001ms, 13666ms total) +T4E58 4253:606 JLINK_IsHalted() returns FALSE (0001ms, 13666ms total) +T4E58 4253:619 JLINK_IsHalted() returns FALSE (0001ms, 13666ms total) +T4E58 4253:622 JLINK_IsHalted() returns FALSE (0001ms, 13666ms total) +T4E58 4253:638 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 13671ms total) +T4E58 4253:644 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 13665ms total) +T4E58 4253:644 JLINK_ClrBPEx(BPHandle = 0x00000016) returns 0x00 (0000ms, 13665ms total) +T4E58 4253:644 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 13665ms total) +T4E58 4253:645 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 22 53 43 22 3A 74 72 75 65 00 00 00 3D 1D 00 20 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 13671ms total) +T4E58 4253:651 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: E9 D1 92 A0 E4 E7 87 A0 00 F0 D2 FC A9 78 92 A0 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0003ms, 13674ms total) +T4E58 4253:654 JLINK_WriteReg(R0, 0x08004800) returns 0x00 (0000ms, 13674ms total) +T4E58 4253:654 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 13674ms total) +T4E58 4253:654 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 13674ms total) +T4E58 4253:654 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0001ms, 13675ms total) +T4E58 4253:655 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 13675ms total) +T4E58 4253:655 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 13675ms total) +T4E58 4253:655 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 13675ms total) +T4E58 4253:655 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 13675ms total) +T4E58 4253:655 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 13675ms total) +T4E58 4253:655 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 13675ms total) +T4E58 4253:655 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 13675ms total) +T4E58 4253:655 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 13675ms total) +T4E58 4253:655 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 13675ms total) +T4E58 4253:655 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 13675ms total) +T4E58 4253:655 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 13675ms total) +T4E58 4253:655 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 13675ms total) +T4E58 4253:655 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 13675ms total) +T4E58 4253:655 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 13675ms total) +T4E58 4253:655 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0001ms, 13676ms total) +T4E58 4253:656 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 13676ms total) +T4E58 4253:656 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000017 (0000ms, 13676ms total) +T4E58 4253:656 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 13679ms total) +T4E58 4253:659 JLINK_IsHalted() returns FALSE (0001ms, 13680ms total) +T4E58 4253:671 JLINK_IsHalted() returns FALSE (0001ms, 13680ms total) +T4E58 4253:674 JLINK_IsHalted() returns FALSE (0001ms, 13680ms total) +T4E58 4253:676 JLINK_IsHalted() returns FALSE (0000ms, 13679ms total) +T4E58 4253:678 JLINK_IsHalted() returns FALSE (0000ms, 13679ms total) +T4E58 4253:681 JLINK_IsHalted() returns FALSE (0001ms, 13680ms total) +T4E58 4253:685 JLINK_IsHalted() returns FALSE (0001ms, 13680ms total) +T4E58 4253:709 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0007ms, 13686ms total) +T4E58 4253:716 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 13679ms total) +T4E58 4253:716 JLINK_ClrBPEx(BPHandle = 0x00000017) returns 0x00 (0000ms, 13679ms total) +T4E58 4253:716 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 13679ms total) +T4E58 4253:718 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 6E 67 22 3A 74 72 75 65 00 00 00 00 22 41 6D 62 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0007ms, 13686ms total) +T4E58 4253:725 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: C4 F3 80 16 2E 71 C3 F3 C0 06 6E 71 E5 06 01 D4 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0003ms, 13689ms total) +T4E58 4253:728 JLINK_WriteReg(R0, 0x08004C00) returns 0x00 (0000ms, 13689ms total) +T4E58 4253:728 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 13689ms total) +T4E58 4253:728 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 13689ms total) +T4E58 4253:728 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 13689ms total) +T4E58 4253:728 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 13689ms total) +T4E58 4253:728 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 13689ms total) +T4E58 4253:728 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 13689ms total) +T4E58 4253:729 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 13690ms total) +T4E58 4253:729 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 13690ms total) +T4E58 4253:729 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 13690ms total) +T4E58 4253:729 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 13690ms total) +T4E58 4253:729 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 13690ms total) +T4E58 4253:729 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 13690ms total) +T4E58 4253:729 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 13690ms total) +T4E58 4253:729 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 13690ms total) +T4E58 4253:729 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 13690ms total) +T4E58 4253:729 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 13690ms total) +T4E58 4253:729 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 13690ms total) +T4E58 4253:729 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 13690ms total) +T4E58 4253:729 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 13690ms total) +T4E58 4253:729 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000018 (0000ms, 13690ms total) +T4E58 4253:729 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 13694ms total) +T4E58 4253:733 JLINK_IsHalted() returns FALSE (0000ms, 13694ms total) +T4E58 4253:744 JLINK_IsHalted() returns FALSE (0000ms, 13694ms total) +T4E58 4253:746 JLINK_IsHalted() returns FALSE (0001ms, 13695ms total) +T4E58 4253:749 JLINK_IsHalted() returns FALSE (0000ms, 13694ms total) +T4E58 4253:759 JLINK_IsHalted() returns FALSE (0001ms, 13695ms total) +T4E58 4253:762 JLINK_IsHalted() returns FALSE (0001ms, 13695ms total) +T4E58 4253:770 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 13699ms total) +T4E58 4253:775 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 13694ms total) +T4E58 4253:775 JLINK_ClrBPEx(BPHandle = 0x00000018) returns 0x00 (0000ms, 13694ms total) +T4E58 4253:775 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 13694ms total) +T4E58 4253:776 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 10 08 00 20 34 1D 00 20 10 B5 08 48 0E F0 D6 FE ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 13700ms total) +T4E58 4253:782 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 00 F0 D6 F8 06 48 01 21 41 72 00 21 81 72 10 BD ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0005ms, 13705ms total) +T4E58 4253:787 JLINK_WriteReg(R0, 0x08005000) returns 0x00 (0000ms, 13705ms total) +T4E58 4253:787 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 13705ms total) +T4E58 4253:787 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 13705ms total) +T4E58 4253:787 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 13705ms total) +T4E58 4253:787 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 13705ms total) +T4E58 4253:787 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 13705ms total) +T4E58 4253:787 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 13705ms total) +T4E58 4253:787 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 13705ms total) +T4E58 4253:787 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 13705ms total) +T4E58 4253:787 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 13705ms total) +T4E58 4253:787 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 13705ms total) +T4E58 4253:787 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 13705ms total) +T4E58 4253:787 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 13705ms total) +T4E58 4253:787 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 13705ms total) +T4E58 4253:787 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 13705ms total) +T4E58 4253:787 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 13705ms total) +T4E58 4253:787 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0001ms, 13706ms total) +T4E58 4253:788 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 13706ms total) +T4E58 4253:788 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 13706ms total) +T4E58 4253:788 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 13706ms total) +T4E58 4253:788 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000019 (0000ms, 13706ms total) +T4E58 4253:788 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0002ms, 13708ms total) +T4E58 4253:790 JLINK_IsHalted() returns FALSE (0002ms, 13710ms total) +T4E58 4253:796 JLINK_IsHalted() returns FALSE (0001ms, 13709ms total) +T4E58 4253:803 JLINK_IsHalted() returns FALSE (0000ms, 13708ms total) +T4E58 4253:805 JLINK_IsHalted() returns FALSE (0000ms, 13708ms total) +T4E58 4253:807 JLINK_IsHalted() returns FALSE (0000ms, 13708ms total) +T4E58 4253:810 JLINK_IsHalted() returns FALSE (0000ms, 13708ms total) +T4E58 4253:820 JLINK_IsHalted() returns FALSE (0001ms, 13709ms total) +T4E58 4253:823 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 13713ms total) +T4E58 4253:828 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 13708ms total) +T4E58 4253:828 JLINK_ClrBPEx(BPHandle = 0x00000019) returns 0x00 (0000ms, 13708ms total) +T4E58 4253:828 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 13708ms total) +T4E58 4253:829 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 2B FD BD E8 10 40 4F F4 E1 30 10 F0 7B BE 00 00 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0007ms, 13715ms total) +T4E58 4253:836 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 00 66 00 40 00 60 00 40 02 46 00 20 53 69 0B 42 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0004ms, 13719ms total) +T4E58 4253:840 JLINK_WriteReg(R0, 0x08005400) returns 0x00 (0000ms, 13719ms total) +T4E58 4253:840 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 13719ms total) +T4E58 4253:840 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 13719ms total) +T4E58 4253:840 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 13719ms total) +T4E58 4253:840 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 13719ms total) +T4E58 4253:840 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 13719ms total) +T4E58 4253:840 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 13719ms total) +T4E58 4253:840 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 13719ms total) +T4E58 4253:840 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 13719ms total) +T4E58 4253:840 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 13719ms total) +T4E58 4253:840 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 13719ms total) +T4E58 4253:840 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 13719ms total) +T4E58 4253:840 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 13719ms total) +T4E58 4253:840 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0001ms, 13720ms total) +T4E58 4253:841 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 13720ms total) +T4E58 4253:841 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 13720ms total) +T4E58 4253:841 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 13720ms total) +T4E58 4253:841 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 13720ms total) +T4E58 4253:841 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 13720ms total) +T4E58 4253:841 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 13720ms total) +T4E58 4253:841 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000001A (0000ms, 13720ms total) +T4E58 4253:841 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 13723ms total) +T4E58 4253:844 JLINK_IsHalted() returns FALSE (0000ms, 13723ms total) +T4E58 4253:851 JLINK_IsHalted() returns FALSE (0001ms, 13724ms total) +T4E58 4253:854 JLINK_IsHalted() returns FALSE (0001ms, 13724ms total) +T4E58 4253:857 JLINK_IsHalted() returns FALSE (0001ms, 13724ms total) +T4E58 4253:865 JLINK_IsHalted() returns FALSE (0000ms, 13723ms total) +T4E58 4253:867 JLINK_IsHalted() returns FALSE (0000ms, 13723ms total) +T4E58 4253:869 JLINK_IsHalted() returns FALSE (0001ms, 13724ms total) +T4E58 4253:872 JLINK_IsHalted() returns FALSE (0001ms, 13724ms total) +T4E58 4253:885 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 13728ms total) +T4E58 4253:890 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 13723ms total) +T4E58 4253:890 JLINK_ClrBPEx(BPHandle = 0x0000001A) returns 0x00 (0000ms, 13723ms total) +T4E58 4253:890 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 13723ms total) +T4E58 4253:891 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 01 60 00 21 14 E0 00 20 10 BD 42 F0 80 02 C1 E7 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 13729ms total) +T4E58 4253:897 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 8D F8 01 40 8D F8 02 40 8D F8 03 40 69 46 4F F4 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0003ms, 13732ms total) +T4E58 4253:900 JLINK_WriteReg(R0, 0x08005800) returns 0x00 (0000ms, 13732ms total) +T4E58 4253:900 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 13732ms total) +T4E58 4253:900 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 13732ms total) +T4E58 4253:900 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 13732ms total) +T4E58 4253:900 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 13732ms total) +T4E58 4253:900 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 13732ms total) +T4E58 4253:900 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 13732ms total) +T4E58 4253:900 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 13732ms total) +T4E58 4253:900 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 13732ms total) +T4E58 4253:901 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 13733ms total) +T4E58 4253:901 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 13733ms total) +T4E58 4253:901 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 13733ms total) +T4E58 4253:901 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 13733ms total) +T4E58 4253:901 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 13733ms total) +T4E58 4253:901 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 13733ms total) +T4E58 4253:901 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 13733ms total) +T4E58 4253:901 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 13733ms total) +T4E58 4253:901 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 13733ms total) +T4E58 4253:901 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 13733ms total) +T4E58 4253:901 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 13733ms total) +T4E58 4253:901 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000001B (0000ms, 13733ms total) +T4E58 4253:901 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 13736ms total) +T4E58 4253:904 JLINK_IsHalted() returns FALSE (0001ms, 13737ms total) +T4E58 4253:911 JLINK_IsHalted() returns FALSE (0001ms, 13737ms total) +T4E58 4253:915 JLINK_IsHalted() returns FALSE (0000ms, 13736ms total) +T4E58 4253:917 JLINK_IsHalted() returns FALSE (0000ms, 13736ms total) +T4E58 4253:919 JLINK_IsHalted() returns FALSE (0001ms, 13737ms total) +T4E58 4253:922 JLINK_IsHalted() returns FALSE (0000ms, 13736ms total) +T4E58 4253:924 JLINK_IsHalted() returns FALSE (0000ms, 13736ms total) +T4E58 4253:932 JLINK_IsHalted() returns FALSE (0000ms, 13736ms total) +T4E58 4253:934 JLINK_IsHalted() returns FALSE (0001ms, 13737ms total) +T4E58 4253:943 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 13741ms total) +T4E58 4253:948 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 13736ms total) +T4E58 4253:948 JLINK_ClrBPEx(BPHandle = 0x0000001B) returns 0x00 (0000ms, 13736ms total) +T4E58 4253:948 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 13736ms total) +T4E58 4253:949 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 98 F8 00 80 A2 EB 08 02 0C FB 02 FC 1F FA 8C F2 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 13742ms total) +T4E58 4253:955 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 36 01 00 20 2D E9 FE 4F 00 25 AC 46 A8 46 2B 46 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0003ms, 13745ms total) +T4E58 4253:958 JLINK_WriteReg(R0, 0x08005C00) returns 0x00 (0000ms, 13745ms total) +T4E58 4253:958 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 13745ms total) +T4E58 4253:958 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 13745ms total) +T4E58 4253:958 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 13745ms total) +T4E58 4253:958 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 13745ms total) +T4E58 4253:958 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 13745ms total) +T4E58 4253:958 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 13745ms total) +T4E58 4253:958 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 13745ms total) +T4E58 4253:958 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 13745ms total) +T4E58 4253:958 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 13745ms total) +T4E58 4253:958 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 13745ms total) +T4E58 4253:958 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 13745ms total) +T4E58 4253:958 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 13745ms total) +T4E58 4253:958 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 13745ms total) +T4E58 4253:958 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 13745ms total) +T4E58 4253:958 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 13745ms total) +T4E58 4253:958 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 13745ms total) +T4E58 4253:958 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 13745ms total) +T4E58 4253:958 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 13745ms total) +T4E58 4253:958 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 13745ms total) +T4E58 4253:958 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000001C (0001ms, 13746ms total) +T4E58 4253:959 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 13750ms total) +T4E58 4253:963 JLINK_IsHalted() returns FALSE (0001ms, 13751ms total) +T4E58 4253:972 JLINK_IsHalted() returns FALSE (0000ms, 13750ms total) +T4E58 4253:974 JLINK_IsHalted() returns FALSE (0000ms, 13750ms total) +T4E58 4253:977 JLINK_IsHalted() returns FALSE (0000ms, 13750ms total) +T4E58 4253:979 JLINK_IsHalted() returns FALSE (0000ms, 13750ms total) +T4E58 4253:981 JLINK_IsHalted() returns FALSE (0001ms, 13751ms total) +T4E58 4253:984 JLINK_IsHalted() returns FALSE (0000ms, 13750ms total) +T4E58 4253:990 JLINK_IsHalted() returns FALSE (0001ms, 13751ms total) +T4E58 4253:993 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 13756ms total) +T4E58 4253:999 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 13750ms total) +T4E58 4253:999 JLINK_ClrBPEx(BPHandle = 0x0000001C) returns 0x00 (0000ms, 13750ms total) +T4E58 4253:999 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 13750ms total) +T4E58 4254:000 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: FD 01 41 F0 01 01 03 E0 04 F0 FE 01 41 F0 02 01 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 13756ms total) +T4E58 4254:006 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 00 00 01 0A 8D F8 01 10 01 0C 19 E0 F4 0D 00 20 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0002ms, 13758ms total) +T4E58 4254:008 JLINK_WriteReg(R0, 0x08006000) returns 0x00 (0000ms, 13758ms total) +T4E58 4254:008 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 13758ms total) +T4E58 4254:008 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 13758ms total) +T4E58 4254:008 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 13758ms total) +T4E58 4254:008 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 13758ms total) +T4E58 4254:008 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 13758ms total) +T4E58 4254:008 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 13758ms total) +T4E58 4254:008 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0002ms, 13760ms total) +T4E58 4254:010 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 13760ms total) +T4E58 4254:010 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 13760ms total) +T4E58 4254:010 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 13760ms total) +T4E58 4254:010 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 13760ms total) +T4E58 4254:010 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 13760ms total) +T4E58 4254:010 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 13760ms total) +T4E58 4254:010 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 13760ms total) +T4E58 4254:010 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 13760ms total) +T4E58 4254:010 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 13760ms total) +T4E58 4254:010 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 13760ms total) +T4E58 4254:010 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 13760ms total) +T4E58 4254:010 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 13760ms total) +T4E58 4254:010 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000001D (0000ms, 13760ms total) +T4E58 4254:010 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 13764ms total) +T4E58 4254:014 JLINK_IsHalted() returns FALSE (0001ms, 13765ms total) +T4E58 4254:028 JLINK_IsHalted() returns FALSE (0000ms, 13764ms total) +T4E58 4254:030 JLINK_IsHalted() returns FALSE (0001ms, 13765ms total) +T4E58 4254:033 JLINK_IsHalted() returns FALSE (0001ms, 13765ms total) +T4E58 4254:036 JLINK_IsHalted() returns FALSE (0000ms, 13764ms total) +T4E58 4254:042 JLINK_IsHalted() returns FALSE (0001ms, 13765ms total) +T4E58 4254:045 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 13769ms total) +T4E58 4254:050 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 13764ms total) +T4E58 4254:050 JLINK_ClrBPEx(BPHandle = 0x0000001D) returns 0x00 (0000ms, 13764ms total) +T4E58 4254:050 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 13764ms total) +T4E58 4254:053 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: BF 4D 00 24 40 F2 2C 40 2E 88 23 46 06 42 28 46 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 13770ms total) +T4E58 4254:059 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 00 0A 8D F8 01 00 8D F8 02 40 8D F8 03 40 69 46 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0004ms, 13774ms total) +T4E58 4254:063 JLINK_WriteReg(R0, 0x08006400) returns 0x00 (0000ms, 13774ms total) +T4E58 4254:063 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 13774ms total) +T4E58 4254:063 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 13774ms total) +T4E58 4254:063 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 13774ms total) +T4E58 4254:063 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 13774ms total) +T4E58 4254:063 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 13774ms total) +T4E58 4254:063 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 13774ms total) +T4E58 4254:063 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 13774ms total) +T4E58 4254:063 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 13774ms total) +T4E58 4254:063 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 13774ms total) +T4E58 4254:063 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 13774ms total) +T4E58 4254:063 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 13774ms total) +T4E58 4254:063 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 13774ms total) +T4E58 4254:063 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 13774ms total) +T4E58 4254:063 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 13774ms total) +T4E58 4254:063 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 13774ms total) +T4E58 4254:063 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 13774ms total) +T4E58 4254:064 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 13775ms total) +T4E58 4254:064 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 13775ms total) +T4E58 4254:064 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 13775ms total) +T4E58 4254:064 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000001E (0000ms, 13775ms total) +T4E58 4254:064 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 13778ms total) +T4E58 4254:067 JLINK_IsHalted() returns FALSE (0001ms, 13779ms total) +T4E58 4254:079 JLINK_IsHalted() returns FALSE (0000ms, 13778ms total) +T4E58 4254:082 JLINK_IsHalted() returns FALSE (0002ms, 13780ms total) +T4E58 4254:088 JLINK_IsHalted() returns FALSE (0001ms, 13779ms total) +T4E58 4254:091 JLINK_IsHalted() returns FALSE (0001ms, 13779ms total) +T4E58 4254:094 JLINK_IsHalted() returns FALSE (0002ms, 13780ms total) +T4E58 4254:098 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 13783ms total) +T4E58 4254:103 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 13778ms total) +T4E58 4254:103 JLINK_ClrBPEx(BPHandle = 0x0000001E) returns 0x00 (0000ms, 13778ms total) +T4E58 4254:103 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 13778ms total) +T4E58 4254:104 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 8C 10 98 F8 00 80 AC EB 08 0C 00 BF 01 FB 0C F1 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 13784ms total) +T4E58 4254:111 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 02 20 02 EB 00 12 D2 F8 80 31 03 F0 01 03 C2 F8 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0004ms, 13788ms total) +T4E58 4254:115 JLINK_WriteReg(R0, 0x08006800) returns 0x00 (0000ms, 13788ms total) +T4E58 4254:115 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 13788ms total) +T4E58 4254:115 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 13788ms total) +T4E58 4254:115 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 13788ms total) +T4E58 4254:115 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 13788ms total) +T4E58 4254:115 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 13788ms total) +T4E58 4254:115 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 13788ms total) +T4E58 4254:115 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 13788ms total) +T4E58 4254:115 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 13788ms total) +T4E58 4254:115 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 13788ms total) +T4E58 4254:115 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 13788ms total) +T4E58 4254:115 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 13788ms total) +T4E58 4254:115 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 13788ms total) +T4E58 4254:115 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0001ms, 13789ms total) +T4E58 4254:116 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 13789ms total) +T4E58 4254:116 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 13789ms total) +T4E58 4254:116 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 13789ms total) +T4E58 4254:116 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 13789ms total) +T4E58 4254:116 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 13789ms total) +T4E58 4254:116 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 13789ms total) +T4E58 4254:116 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000001F (0000ms, 13789ms total) +T4E58 4254:116 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 13793ms total) +T4E58 4254:120 JLINK_IsHalted() returns FALSE (0000ms, 13793ms total) +T4E58 4254:126 JLINK_IsHalted() returns FALSE (0000ms, 13793ms total) +T4E58 4254:128 JLINK_IsHalted() returns FALSE (0000ms, 13793ms total) +T4E58 4254:130 JLINK_IsHalted() returns FALSE (0001ms, 13794ms total) +T4E58 4254:134 JLINK_IsHalted() returns FALSE (0000ms, 13793ms total) +T4E58 4254:142 JLINK_IsHalted() returns FALSE (0000ms, 13793ms total) +T4E58 4254:144 JLINK_IsHalted() returns FALSE (0000ms, 13793ms total) +T4E58 4254:147 JLINK_IsHalted() returns FALSE (0000ms, 13793ms total) +T4E58 4254:149 JLINK_IsHalted() returns FALSE (0001ms, 13794ms total) +T4E58 4254:155 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 13798ms total) +T4E58 4254:160 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 13793ms total) +T4E58 4254:160 JLINK_ClrBPEx(BPHandle = 0x0000001F) returns 0x00 (0000ms, 13793ms total) +T4E58 4254:160 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 13793ms total) +T4E58 4254:161 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 44 05 C5 EB C4 14 B3 EB C4 0F EC DB C3 79 5B 1C ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 13799ms total) +T4E58 4254:167 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 9A 99 99 3E CD CC 4C 3E CD CC 4C 3D 0A D7 23 3C ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0003ms, 13802ms total) +T4E58 4254:170 JLINK_WriteReg(R0, 0x08006C00) returns 0x00 (0000ms, 13802ms total) +T4E58 4254:170 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 13802ms total) +T4E58 4254:170 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0001ms, 13803ms total) +T4E58 4254:171 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 13803ms total) +T4E58 4254:171 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 13803ms total) +T4E58 4254:171 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 13803ms total) +T4E58 4254:171 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 13803ms total) +T4E58 4254:171 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 13803ms total) +T4E58 4254:171 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 13803ms total) +T4E58 4254:171 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 13803ms total) +T4E58 4254:171 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 13803ms total) +T4E58 4254:171 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 13803ms total) +T4E58 4254:171 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0001ms, 13804ms total) +T4E58 4254:172 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 13804ms total) +T4E58 4254:172 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 13804ms total) +T4E58 4254:172 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 13804ms total) +T4E58 4254:172 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 13804ms total) +T4E58 4254:172 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 13804ms total) +T4E58 4254:172 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 13804ms total) +T4E58 4254:172 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 13804ms total) +T4E58 4254:172 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000020 (0000ms, 13804ms total) +T4E58 4254:172 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 13808ms total) +T4E58 4254:176 JLINK_IsHalted() returns FALSE (0001ms, 13809ms total) +T4E58 4254:181 JLINK_IsHalted() returns FALSE (0000ms, 13808ms total) +T4E58 4254:189 JLINK_IsHalted() returns FALSE (0001ms, 13809ms total) +T4E58 4254:192 JLINK_IsHalted() returns FALSE (0001ms, 13809ms total) +T4E58 4254:195 JLINK_IsHalted() returns FALSE (0000ms, 13808ms total) +T4E58 4254:197 JLINK_IsHalted() returns FALSE (0000ms, 13808ms total) +T4E58 4254:209 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 13813ms total) +T4E58 4254:214 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 13808ms total) +T4E58 4254:214 JLINK_ClrBPEx(BPHandle = 0x00000020) returns 0x00 (0000ms, 13808ms total) +T4E58 4254:214 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 13808ms total) +T4E58 4254:217 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 0D F0 2A FF F8 BD 0A 48 41 F2 70 71 C0 8C C0 F3 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 13814ms total) +T4E58 4254:223 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 00 F0 F6 F8 08 B1 01 20 1C BD 14 20 0D F0 D6 FD ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0004ms, 13818ms total) +T4E58 4254:227 JLINK_WriteReg(R0, 0x08007000) returns 0x00 (0000ms, 13818ms total) +T4E58 4254:227 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 13818ms total) +T4E58 4254:227 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 13818ms total) +T4E58 4254:227 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 13818ms total) +T4E58 4254:227 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0001ms, 13819ms total) +T4E58 4254:228 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 13819ms total) +T4E58 4254:228 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 13819ms total) +T4E58 4254:228 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 13819ms total) +T4E58 4254:228 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 13819ms total) +T4E58 4254:228 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 13819ms total) +T4E58 4254:228 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 13819ms total) +T4E58 4254:228 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 13819ms total) +T4E58 4254:228 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 13819ms total) +T4E58 4254:229 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 13820ms total) +T4E58 4254:229 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 13820ms total) +T4E58 4254:229 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 13820ms total) +T4E58 4254:229 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 13820ms total) +T4E58 4254:229 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 13820ms total) +T4E58 4254:229 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 13820ms total) +T4E58 4254:229 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 13820ms total) +T4E58 4254:229 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000021 (0000ms, 13820ms total) +T4E58 4254:229 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 13823ms total) +T4E58 4254:232 JLINK_IsHalted() returns FALSE (0002ms, 13825ms total) +T4E58 4254:240 JLINK_IsHalted() returns FALSE (0001ms, 13824ms total) +T4E58 4254:243 JLINK_IsHalted() returns FALSE (0001ms, 13824ms total) +T4E58 4254:253 JLINK_IsHalted() returns FALSE (0001ms, 13824ms total) +T4E58 4254:256 JLINK_IsHalted() returns FALSE (0001ms, 13824ms total) +T4E58 4254:259 JLINK_IsHalted() returns FALSE (0001ms, 13824ms total) +T4E58 4254:262 JLINK_IsHalted() returns FALSE (0001ms, 13824ms total) +T4E58 4254:282 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 13828ms total) +T4E58 4254:287 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 13823ms total) +T4E58 4254:287 JLINK_ClrBPEx(BPHandle = 0x00000021) returns 0x00 (0000ms, 13823ms total) +T4E58 4254:287 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 13823ms total) +T4E58 4254:289 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 2B FD 01 28 F4 D1 DF F8 7C 90 A0 46 AA F1 01 04 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0005ms, 13828ms total) +T4E58 4254:294 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 40 F0 01 00 20 61 35 80 38 46 00 F0 69 F8 21 69 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0005ms, 13833ms total) +T4E58 4254:299 JLINK_WriteReg(R0, 0x08007400) returns 0x00 (0000ms, 13833ms total) +T4E58 4254:299 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 13833ms total) +T4E58 4254:299 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 13833ms total) +T4E58 4254:299 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 13833ms total) +T4E58 4254:299 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 13833ms total) +T4E58 4254:299 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 13833ms total) +T4E58 4254:299 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 13833ms total) +T4E58 4254:299 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 13833ms total) +T4E58 4254:299 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 13833ms total) +T4E58 4254:300 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 13834ms total) +T4E58 4254:300 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 13834ms total) +T4E58 4254:300 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 13834ms total) +T4E58 4254:300 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 13834ms total) +T4E58 4254:300 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 13834ms total) +T4E58 4254:300 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 13834ms total) +T4E58 4254:300 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 13834ms total) +T4E58 4254:300 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 13834ms total) +T4E58 4254:300 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 13834ms total) +T4E58 4254:300 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 13834ms total) +T4E58 4254:300 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 13834ms total) +T4E58 4254:300 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000022 (0000ms, 13834ms total) +T4E58 4254:301 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 13838ms total) +T4E58 4254:304 JLINK_IsHalted() returns FALSE (0001ms, 13839ms total) +T4E58 4254:313 JLINK_IsHalted() returns FALSE (0000ms, 13838ms total) +T4E58 4254:316 JLINK_IsHalted() returns FALSE (0001ms, 13839ms total) +T4E58 4254:320 JLINK_IsHalted() returns FALSE (0001ms, 13839ms total) +T4E58 4254:322 JLINK_IsHalted() returns FALSE (0001ms, 13839ms total) +T4E58 4254:341 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 13844ms total) +T4E58 4254:347 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 13838ms total) +T4E58 4254:347 JLINK_ClrBPEx(BPHandle = 0x00000022) returns 0x00 (0000ms, 13838ms total) +T4E58 4254:347 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 13838ms total) +T4E58 4254:348 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 1C D0 04 68 0F 88 02 FA 05 F6 37 40 B7 42 11 D1 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0005ms, 13843ms total) +T4E58 4254:353 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 44 00 21 81 61 81 00 E0 E6 70 B8 F8 4C 10 8A 07 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0004ms, 13847ms total) +T4E58 4254:357 JLINK_WriteReg(R0, 0x08007800) returns 0x00 (0000ms, 13847ms total) +T4E58 4254:357 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 13847ms total) +T4E58 4254:357 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 13847ms total) +T4E58 4254:357 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 13847ms total) +T4E58 4254:357 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 13847ms total) +T4E58 4254:357 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 13847ms total) +T4E58 4254:357 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 13847ms total) +T4E58 4254:357 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 13847ms total) +T4E58 4254:359 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 13849ms total) +T4E58 4254:359 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 13849ms total) +T4E58 4254:359 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 13849ms total) +T4E58 4254:359 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 13849ms total) +T4E58 4254:359 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 13849ms total) +T4E58 4254:359 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 13849ms total) +T4E58 4254:359 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 13849ms total) +T4E58 4254:359 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 13849ms total) +T4E58 4254:359 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 13849ms total) +T4E58 4254:359 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0001ms, 13850ms total) +T4E58 4254:360 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 13850ms total) +T4E58 4254:360 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 13850ms total) +T4E58 4254:360 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000023 (0000ms, 13850ms total) +T4E58 4254:360 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 13853ms total) +T4E58 4254:363 JLINK_IsHalted() returns FALSE (0001ms, 13854ms total) +T4E58 4254:369 JLINK_IsHalted() returns FALSE (0001ms, 13854ms total) +T4E58 4254:372 JLINK_IsHalted() returns FALSE (0002ms, 13855ms total) +T4E58 4254:385 JLINK_IsHalted() returns FALSE (0000ms, 13853ms total) +T4E58 4254:387 JLINK_IsHalted() returns FALSE (0000ms, 13853ms total) +T4E58 4254:389 JLINK_IsHalted() returns FALSE (0000ms, 13853ms total) +T4E58 4254:398 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 13858ms total) +T4E58 4254:403 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 13853ms total) +T4E58 4254:403 JLINK_ClrBPEx(BPHandle = 0x00000023) returns 0x00 (0000ms, 13853ms total) +T4E58 4254:403 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 13853ms total) +T4E58 4254:407 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: A0 81 A0 89 02 22 01 0A 8D F8 00 10 8D F8 01 00 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0005ms, 13858ms total) +T4E58 4254:412 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 25 FF 20 46 BD E8 10 40 00 21 03 F0 1F BF 00 00 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0008ms, 13866ms total) +T4E58 4254:420 JLINK_WriteReg(R0, 0x08007C00) returns 0x00 (0000ms, 13866ms total) +T4E58 4254:420 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 13866ms total) +T4E58 4254:420 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 13866ms total) +T4E58 4254:420 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 13866ms total) +T4E58 4254:420 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 13866ms total) +T4E58 4254:420 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 13866ms total) +T4E58 4254:420 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 13866ms total) +T4E58 4254:420 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0001ms, 13867ms total) +T4E58 4254:421 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 13867ms total) +T4E58 4254:421 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 13867ms total) +T4E58 4254:421 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 13867ms total) +T4E58 4254:421 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 13867ms total) +T4E58 4254:421 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 13867ms total) +T4E58 4254:421 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 13867ms total) +T4E58 4254:421 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 13867ms total) +T4E58 4254:421 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 13867ms total) +T4E58 4254:421 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 13867ms total) +T4E58 4254:421 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 13867ms total) +T4E58 4254:421 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 13867ms total) +T4E58 4254:421 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 13867ms total) +T4E58 4254:421 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000024 (0000ms, 13867ms total) +T4E58 4254:421 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 13871ms total) +T4E58 4254:425 JLINK_IsHalted() returns FALSE (0001ms, 13872ms total) +T4E58 4254:431 JLINK_IsHalted() returns FALSE (0001ms, 13872ms total) +T4E58 4254:434 JLINK_IsHalted() returns FALSE (0001ms, 13872ms total) +T4E58 4254:437 JLINK_IsHalted() returns FALSE (0000ms, 13871ms total) +T4E58 4254:454 JLINK_IsHalted() returns FALSE (0000ms, 13871ms total) +T4E58 4254:461 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 13877ms total) +T4E58 4254:467 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 13871ms total) +T4E58 4254:467 JLINK_ClrBPEx(BPHandle = 0x00000024) returns 0x00 (0000ms, 13871ms total) +T4E58 4254:467 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 13871ms total) +T4E58 4254:471 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 01 48 FF F7 74 BC 00 00 00 10 01 40 80 21 01 48 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0005ms, 13876ms total) +T4E58 4254:476 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: C8 82 03 28 F8 D9 CA 82 CC 71 0A 72 4A 72 70 BD ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0004ms, 13880ms total) +T4E58 4254:480 JLINK_WriteReg(R0, 0x08008000) returns 0x00 (0000ms, 13880ms total) +T4E58 4254:480 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 13880ms total) +T4E58 4254:480 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 13880ms total) +T4E58 4254:480 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 13880ms total) +T4E58 4254:480 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0001ms, 13881ms total) +T4E58 4254:481 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 13881ms total) +T4E58 4254:481 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 13881ms total) +T4E58 4254:481 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 13881ms total) +T4E58 4254:481 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 13881ms total) +T4E58 4254:481 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 13881ms total) +T4E58 4254:481 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 13881ms total) +T4E58 4254:481 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 13881ms total) +T4E58 4254:481 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 13881ms total) +T4E58 4254:481 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 13881ms total) +T4E58 4254:481 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 13881ms total) +T4E58 4254:481 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 13881ms total) +T4E58 4254:482 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 13881ms total) +T4E58 4254:482 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 13881ms total) +T4E58 4254:482 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 13881ms total) +T4E58 4254:482 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 13881ms total) +T4E58 4254:482 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000025 (0000ms, 13881ms total) +T4E58 4254:482 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 13884ms total) +T4E58 4254:485 JLINK_IsHalted() returns FALSE (0000ms, 13884ms total) +T4E58 4254:491 JLINK_IsHalted() returns FALSE (0000ms, 13884ms total) +T4E58 4254:494 JLINK_IsHalted() returns FALSE (0001ms, 13885ms total) +T4E58 4254:497 JLINK_IsHalted() returns FALSE (0000ms, 13884ms total) +T4E58 4254:500 JLINK_IsHalted() returns FALSE (0001ms, 13885ms total) +T4E58 4254:514 JLINK_IsHalted() returns FALSE (0001ms, 13885ms total) +T4E58 4254:518 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0004ms, 13888ms total) +T4E58 4254:522 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 13884ms total) +T4E58 4254:522 JLINK_ClrBPEx(BPHandle = 0x00000025) returns 0x00 (0000ms, 13884ms total) +T4E58 4254:522 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 13884ms total) +T4E58 4254:523 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: F3 F0 86 B2 4F F4 7A 70 60 43 C4 F5 80 53 90 FB ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0007ms, 13891ms total) +T4E58 4254:530 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 20 46 FF F7 0B F8 19 21 68 46 FE F7 23 FC 9D F8 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0002ms, 13893ms total) +T4E58 4254:534 JLINK_WriteReg(R0, 0x08008400) returns 0x00 (0000ms, 13895ms total) +T4E58 4254:534 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 13895ms total) +T4E58 4254:534 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 13895ms total) +T4E58 4254:534 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 13895ms total) +T4E58 4254:534 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 13895ms total) +T4E58 4254:534 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 13895ms total) +T4E58 4254:534 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 13895ms total) +T4E58 4254:534 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 13895ms total) +T4E58 4254:534 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 13895ms total) +T4E58 4254:534 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 13895ms total) +T4E58 4254:534 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 13895ms total) +T4E58 4254:534 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 13895ms total) +T4E58 4254:534 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 13895ms total) +T4E58 4254:534 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0001ms, 13896ms total) +T4E58 4254:535 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 13896ms total) +T4E58 4254:535 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 13896ms total) +T4E58 4254:535 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 13896ms total) +T4E58 4254:535 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 13896ms total) +T4E58 4254:535 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 13896ms total) +T4E58 4254:535 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 13896ms total) +T4E58 4254:535 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000026 (0000ms, 13896ms total) +T4E58 4254:535 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 13899ms total) +T4E58 4254:538 JLINK_IsHalted() returns FALSE (0001ms, 13900ms total) +T4E58 4254:544 JLINK_IsHalted() returns FALSE (0000ms, 13899ms total) +T4E58 4254:547 JLINK_IsHalted() returns FALSE (0000ms, 13899ms total) +T4E58 4254:553 JLINK_IsHalted() returns FALSE (0000ms, 13899ms total) +T4E58 4254:555 JLINK_IsHalted() returns FALSE (0002ms, 13901ms total) +T4E58 4254:559 JLINK_IsHalted() returns FALSE (0001ms, 13900ms total) +T4E58 4254:562 JLINK_IsHalted() returns FALSE (0000ms, 13899ms total) +T4E58 4254:565 JLINK_IsHalted() returns FALSE (0000ms, 13899ms total) +T4E58 4254:574 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 13904ms total) +T4E58 4254:579 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 13899ms total) +T4E58 4254:579 JLINK_ClrBPEx(BPHandle = 0x00000026) returns 0x00 (0000ms, 13899ms total) +T4E58 4254:579 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 13899ms total) +T4E58 4254:581 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 59 FB E1 19 C0 F3 07 23 0A 7A 9A 42 7C D1 C9 79 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 13905ms total) +T4E58 4254:587 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: FE E7 B5 70 35 70 D1 B2 04 E0 75 70 35 70 0C EB ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0005ms, 13910ms total) +T4E58 4254:592 JLINK_WriteReg(R0, 0x08008800) returns 0x00 (0000ms, 13910ms total) +T4E58 4254:592 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 13910ms total) +T4E58 4254:592 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 13910ms total) +T4E58 4254:592 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 13910ms total) +T4E58 4254:592 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 13910ms total) +T4E58 4254:592 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 13910ms total) +T4E58 4254:592 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 13910ms total) +T4E58 4254:592 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 13910ms total) +T4E58 4254:592 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 13910ms total) +T4E58 4254:592 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 13910ms total) +T4E58 4254:592 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 13910ms total) +T4E58 4254:592 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 13910ms total) +T4E58 4254:592 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 13910ms total) +T4E58 4254:592 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 13910ms total) +T4E58 4254:592 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 13910ms total) +T4E58 4254:592 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 13910ms total) +T4E58 4254:592 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0001ms, 13911ms total) +T4E58 4254:593 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 13911ms total) +T4E58 4254:593 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 13911ms total) +T4E58 4254:593 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 13911ms total) +T4E58 4254:593 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000027 (0000ms, 13911ms total) +T4E58 4254:593 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 13915ms total) +T4E58 4254:597 JLINK_IsHalted() returns FALSE (0000ms, 13915ms total) +T4E58 4254:603 JLINK_IsHalted() returns FALSE (0001ms, 13916ms total) +T4E58 4254:606 JLINK_IsHalted() returns FALSE (0000ms, 13915ms total) +T4E58 4254:609 JLINK_IsHalted() returns FALSE (0001ms, 13916ms total) +T4E58 4254:611 JLINK_IsHalted() returns FALSE (0002ms, 13917ms total) +T4E58 4254:621 JLINK_IsHalted() returns FALSE (0001ms, 13916ms total) +T4E58 4254:623 JLINK_IsHalted() returns FALSE (0001ms, 13916ms total) +T4E58 4254:626 JLINK_IsHalted() returns FALSE (0000ms, 13915ms total) +T4E58 4254:630 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 13920ms total) +T4E58 4254:635 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 13915ms total) +T4E58 4254:635 JLINK_ClrBPEx(BPHandle = 0x00000027) returns 0x00 (0000ms, 13915ms total) +T4E58 4254:635 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 13915ms total) +T4E58 4254:636 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 35 70 BA F8 10 20 5A 21 23 70 67 70 A5 20 A1 70 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 13921ms total) +T4E58 4254:642 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: B2 4A 88 42 02 D1 63 78 23 2B 4F D0 88 42 02 D1 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0003ms, 13924ms total) +T4E58 4254:645 JLINK_WriteReg(R0, 0x08008C00) returns 0x00 (0000ms, 13924ms total) +T4E58 4254:645 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0001ms, 13925ms total) +T4E58 4254:646 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 13925ms total) +T4E58 4254:646 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 13925ms total) +T4E58 4254:646 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 13925ms total) +T4E58 4254:646 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 13925ms total) +T4E58 4254:646 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 13925ms total) +T4E58 4254:646 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 13925ms total) +T4E58 4254:646 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 13925ms total) +T4E58 4254:646 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 13925ms total) +T4E58 4254:646 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 13925ms total) +T4E58 4254:646 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 13925ms total) +T4E58 4254:646 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 13925ms total) +T4E58 4254:646 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0001ms, 13926ms total) +T4E58 4254:647 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 13926ms total) +T4E58 4254:647 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 13926ms total) +T4E58 4254:647 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 13926ms total) +T4E58 4254:647 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 13926ms total) +T4E58 4254:647 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 13926ms total) +T4E58 4254:647 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 13926ms total) +T4E58 4254:647 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000028 (0000ms, 13926ms total) +T4E58 4254:647 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 13929ms total) +T4E58 4254:650 JLINK_IsHalted() returns FALSE (0001ms, 13930ms total) +T4E58 4254:659 JLINK_IsHalted() returns FALSE (0001ms, 13930ms total) +T4E58 4254:667 JLINK_IsHalted() returns FALSE (0001ms, 13930ms total) +T4E58 4254:670 JLINK_IsHalted() returns FALSE (0001ms, 13930ms total) +T4E58 4254:672 JLINK_IsHalted() returns FALSE (0000ms, 13929ms total) +T4E58 4254:674 JLINK_IsHalted() returns FALSE (0000ms, 13929ms total) +T4E58 4254:676 JLINK_IsHalted() returns FALSE (0000ms, 13929ms total) +T4E58 4254:683 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 13934ms total) +T4E58 4254:688 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0001ms, 13930ms total) +T4E58 4254:689 JLINK_ClrBPEx(BPHandle = 0x00000028) returns 0x00 (0000ms, 13930ms total) +T4E58 4254:689 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 13930ms total) +T4E58 4254:689 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 02 E0 03 E0 15 70 7B E0 5E 48 8E E0 63 78 F2 2B ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0005ms, 13935ms total) +T4E58 4254:694 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 68 46 FD F7 27 FE 1A 4F 8D F8 01 00 25 70 15 21 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0004ms, 13939ms total) +T4E58 4254:699 JLINK_WriteReg(R0, 0x08009000) returns 0x00 (0000ms, 13939ms total) +T4E58 4254:699 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 13939ms total) +T4E58 4254:699 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 13939ms total) +T4E58 4254:699 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 13939ms total) +T4E58 4254:699 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 13939ms total) +T4E58 4254:699 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 13939ms total) +T4E58 4254:699 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 13939ms total) +T4E58 4254:699 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 13939ms total) +T4E58 4254:699 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 13939ms total) +T4E58 4254:699 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 13939ms total) +T4E58 4254:700 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 13939ms total) +T4E58 4254:700 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 13939ms total) +T4E58 4254:700 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 13939ms total) +T4E58 4254:700 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 13939ms total) +T4E58 4254:700 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 13939ms total) +T4E58 4254:700 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 13939ms total) +T4E58 4254:700 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 13939ms total) +T4E58 4254:700 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 13939ms total) +T4E58 4254:700 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 13939ms total) +T4E58 4254:700 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 13939ms total) +T4E58 4254:700 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000029 (0000ms, 13939ms total) +T4E58 4254:700 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 13943ms total) +T4E58 4254:704 JLINK_IsHalted() returns FALSE (0000ms, 13943ms total) +T4E58 4254:715 JLINK_IsHalted() returns FALSE (0001ms, 13944ms total) +T4E58 4254:718 JLINK_IsHalted() returns FALSE (0001ms, 13944ms total) +T4E58 4254:725 JLINK_IsHalted() returns FALSE (0001ms, 13944ms total) +T4E58 4254:728 JLINK_IsHalted() returns FALSE (0002ms, 13945ms total) +T4E58 4254:732 JLINK_IsHalted() returns FALSE (0000ms, 13943ms total) +T4E58 4254:734 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 13948ms total) +T4E58 4254:739 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 13943ms total) +T4E58 4254:739 JLINK_ClrBPEx(BPHandle = 0x00000029) returns 0x00 (0000ms, 13943ms total) +T4E58 4254:739 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 13943ms total) +T4E58 4254:740 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 4A 01 00 20 4B 01 00 20 F4 08 00 20 00 38 01 40 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 13949ms total) +T4E58 4254:746 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: BD E8 10 40 00 22 40 F2 25 51 05 48 0A F0 1A BB ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0004ms, 13953ms total) +T4E58 4254:750 JLINK_WriteReg(R0, 0x08009400) returns 0x00 (0000ms, 13953ms total) +T4E58 4254:750 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 13953ms total) +T4E58 4254:750 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 13953ms total) +T4E58 4254:750 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 13953ms total) +T4E58 4254:750 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 13953ms total) +T4E58 4254:750 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 13953ms total) +T4E58 4254:750 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 13953ms total) +T4E58 4254:750 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 13953ms total) +T4E58 4254:750 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 13953ms total) +T4E58 4254:750 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 13953ms total) +T4E58 4254:750 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 13953ms total) +T4E58 4254:750 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 13953ms total) +T4E58 4254:750 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 13953ms total) +T4E58 4254:750 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 13953ms total) +T4E58 4254:751 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 13954ms total) +T4E58 4254:751 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 13954ms total) +T4E58 4254:751 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 13954ms total) +T4E58 4254:751 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 13954ms total) +T4E58 4254:751 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 13954ms total) +T4E58 4254:751 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 13954ms total) +T4E58 4254:751 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000002A (0000ms, 13954ms total) +T4E58 4254:751 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 13958ms total) +T4E58 4254:755 JLINK_IsHalted() returns FALSE (0000ms, 13958ms total) +T4E58 4254:765 JLINK_IsHalted() returns FALSE (0001ms, 13959ms total) +T4E58 4254:768 JLINK_IsHalted() returns FALSE (0000ms, 13958ms total) +T4E58 4254:772 JLINK_IsHalted() returns FALSE (0000ms, 13958ms total) +T4E58 4254:778 JLINK_IsHalted() returns FALSE (0001ms, 13959ms total) +T4E58 4254:781 JLINK_IsHalted() returns FALSE (0001ms, 13959ms total) +T4E58 4254:784 JLINK_IsHalted() returns FALSE (0001ms, 13959ms total) +T4E58 4254:787 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0004ms, 13962ms total) +T4E58 4254:791 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 13958ms total) +T4E58 4254:791 JLINK_ClrBPEx(BPHandle = 0x0000002A) returns 0x00 (0000ms, 13958ms total) +T4E58 4254:791 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 13958ms total) +T4E58 4254:792 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 10 21 00 20 FD F7 42 FE 05 20 0B F0 25 FB 03 F0 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 13964ms total) +T4E58 4254:798 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 1E F9 20 46 BD E8 10 40 01 21 09 F0 B0 B8 40 F6 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0004ms, 13968ms total) +T4E58 4254:802 JLINK_WriteReg(R0, 0x08009800) returns 0x00 (0000ms, 13968ms total) +T4E58 4254:802 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 13968ms total) +T4E58 4254:802 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 13968ms total) +T4E58 4254:802 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 13968ms total) +T4E58 4254:802 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 13968ms total) +T4E58 4254:802 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 13968ms total) +T4E58 4254:802 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 13968ms total) +T4E58 4254:802 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 13968ms total) +T4E58 4254:802 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 13968ms total) +T4E58 4254:802 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 13968ms total) +T4E58 4254:802 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 13968ms total) +T4E58 4254:802 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 13968ms total) +T4E58 4254:802 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 13968ms total) +T4E58 4254:802 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 13968ms total) +T4E58 4254:802 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 13968ms total) +T4E58 4254:802 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 13968ms total) +T4E58 4254:802 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 13968ms total) +T4E58 4254:802 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0001ms, 13969ms total) +T4E58 4254:803 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 13969ms total) +T4E58 4254:803 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 13969ms total) +T4E58 4254:803 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000002B (0000ms, 13969ms total) +T4E58 4254:803 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 13972ms total) +T4E58 4254:806 JLINK_IsHalted() returns FALSE (0001ms, 13973ms total) +T4E58 4254:812 JLINK_IsHalted() returns FALSE (0001ms, 13973ms total) +T4E58 4254:815 JLINK_IsHalted() returns FALSE (0001ms, 13973ms total) +T4E58 4254:818 JLINK_IsHalted() returns FALSE (0000ms, 13972ms total) +T4E58 4254:821 JLINK_IsHalted() returns FALSE (0000ms, 13972ms total) +T4E58 4254:828 JLINK_IsHalted() returns FALSE (0001ms, 13973ms total) +T4E58 4254:831 JLINK_IsHalted() returns FALSE (0001ms, 13973ms total) +T4E58 4254:834 JLINK_IsHalted() returns FALSE (0000ms, 13972ms total) +T4E58 4254:836 JLINK_IsHalted() returns FALSE (0000ms, 13972ms total) +T4E58 4254:845 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 13977ms total) +T4E58 4254:850 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 13972ms total) +T4E58 4254:850 JLINK_ClrBPEx(BPHandle = 0x0000002B) returns 0x00 (0000ms, 13972ms total) +T4E58 4254:850 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 13972ms total) +T4E58 4254:851 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 88 42 02 D1 61 78 03 29 31 D0 15 28 0A D0 CD E0 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 13978ms total) +T4E58 4254:857 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: BE 00 88 42 EA D2 20 78 0A 28 E7 D9 66 77 E5 E7 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0004ms, 13982ms total) +T4E58 4254:861 JLINK_WriteReg(R0, 0x08009C00) returns 0x00 (0000ms, 13982ms total) +T4E58 4254:861 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 13982ms total) +T4E58 4254:861 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 13982ms total) +T4E58 4254:861 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 13982ms total) +T4E58 4254:861 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 13982ms total) +T4E58 4254:861 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 13982ms total) +T4E58 4254:861 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0001ms, 13983ms total) +T4E58 4254:862 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 13983ms total) +T4E58 4254:862 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 13983ms total) +T4E58 4254:862 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 13983ms total) +T4E58 4254:862 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 13983ms total) +T4E58 4254:862 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 13983ms total) +T4E58 4254:862 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 13983ms total) +T4E58 4254:862 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 13983ms total) +T4E58 4254:862 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 13983ms total) +T4E58 4254:862 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 13983ms total) +T4E58 4254:862 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 13983ms total) +T4E58 4254:862 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 13983ms total) +T4E58 4254:862 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 13983ms total) +T4E58 4254:862 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 13983ms total) +T4E58 4254:862 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000002C (0000ms, 13983ms total) +T4E58 4254:862 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 13986ms total) +T4E58 4254:866 JLINK_IsHalted() returns FALSE (0000ms, 13987ms total) +T4E58 4255:089 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 13993ms total) +T4E58 4255:095 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 13987ms total) +T4E58 4255:095 JLINK_ClrBPEx(BPHandle = 0x0000002C) returns 0x00 (0000ms, 13987ms total) +T4E58 4255:095 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 13987ms total) +T4E58 4255:099 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 01 1E 6F 20 63 0C 64 69 AF 78 4B FA 18 1B 10 1A ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0005ms, 13992ms total) +T4E58 4255:104 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0004ms, 13996ms total) +T4E58 4255:108 JLINK_WriteReg(R0, 0x0800A000) returns 0x00 (0000ms, 13996ms total) +T4E58 4255:108 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 13996ms total) +T4E58 4255:108 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0001ms, 13997ms total) +T4E58 4255:109 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 13997ms total) +T4E58 4255:109 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 13997ms total) +T4E58 4255:109 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 13997ms total) +T4E58 4255:109 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 13997ms total) +T4E58 4255:109 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 13997ms total) +T4E58 4255:109 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 13997ms total) +T4E58 4255:109 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0001ms, 13998ms total) +T4E58 4255:110 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 13998ms total) +T4E58 4255:110 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 13998ms total) +T4E58 4255:110 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 13998ms total) +T4E58 4255:110 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 13998ms total) +T4E58 4255:110 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 13998ms total) +T4E58 4255:110 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 13998ms total) +T4E58 4255:110 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 13998ms total) +T4E58 4255:110 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 13998ms total) +T4E58 4255:110 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 13998ms total) +T4E58 4255:110 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 13998ms total) +T4E58 4255:110 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000002D (0000ms, 13998ms total) +T4E58 4255:110 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0005ms, 14003ms total) +T4E58 4255:115 JLINK_IsHalted() returns FALSE (0001ms, 14004ms total) +T4E58 4255:136 JLINK_IsHalted() returns FALSE (0001ms, 14004ms total) +T4E58 4255:198 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 14009ms total) +T4E58 4255:204 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0001ms, 14010ms total) +T4E58 4255:205 JLINK_ClrBPEx(BPHandle = 0x0000002D) returns 0x00 (0000ms, 14010ms total) +T4E58 4255:205 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 14010ms total) +T4E58 4255:212 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 14016ms total) +T4E58 4255:218 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0004ms, 14020ms total) +T4E58 4255:222 JLINK_WriteReg(R0, 0x0800A400) returns 0x00 (0000ms, 14020ms total) +T4E58 4255:222 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 14020ms total) +T4E58 4255:222 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 14020ms total) +T4E58 4255:222 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 14020ms total) +T4E58 4255:222 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0001ms, 14021ms total) +T4E58 4255:223 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 14021ms total) +T4E58 4255:223 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 14021ms total) +T4E58 4255:223 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 14021ms total) +T4E58 4255:223 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 14021ms total) +T4E58 4255:223 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0001ms, 14022ms total) +T4E58 4255:224 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 14022ms total) +T4E58 4255:224 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 14022ms total) +T4E58 4255:224 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 14022ms total) +T4E58 4255:224 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 14022ms total) +T4E58 4255:224 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 14022ms total) +T4E58 4255:224 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0001ms, 14023ms total) +T4E58 4255:225 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 14023ms total) +T4E58 4255:225 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 14023ms total) +T4E58 4255:225 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 14023ms total) +T4E58 4255:225 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 14023ms total) +T4E58 4255:225 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000002E (0000ms, 14023ms total) +T4E58 4255:226 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 14027ms total) +T4E58 4255:230 JLINK_IsHalted() returns FALSE (0001ms, 14028ms total) +T4E58 4255:275 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 14033ms total) +T4E58 4255:281 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 14027ms total) +T4E58 4255:281 JLINK_ClrBPEx(BPHandle = 0x0000002E) returns 0x00 (0001ms, 14028ms total) +T4E58 4255:282 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 14028ms total) +T4E58 4255:287 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 2D E9 F0 47 AD 4C 01 26 A0 7A 01 28 02 D0 A6 72 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 14034ms total) +T4E58 4255:293 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 08 21 08 48 09 F0 72 F8 26 73 25 72 BD E8 F0 47 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0004ms, 14038ms total) +T4E58 4255:297 JLINK_WriteReg(R0, 0x0800A800) returns 0x00 (0000ms, 14038ms total) +T4E58 4255:297 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 14038ms total) +T4E58 4255:297 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0001ms, 14039ms total) +T4E58 4255:298 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 14039ms total) +T4E58 4255:298 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 14039ms total) +T4E58 4255:298 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 14039ms total) +T4E58 4255:298 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 14039ms total) +T4E58 4255:298 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 14039ms total) +T4E58 4255:298 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 14039ms total) +T4E58 4255:299 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 14040ms total) +T4E58 4255:299 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 14040ms total) +T4E58 4255:299 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 14040ms total) +T4E58 4255:299 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 14040ms total) +T4E58 4255:299 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0001ms, 14041ms total) +T4E58 4255:300 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 14041ms total) +T4E58 4255:300 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 14041ms total) +T4E58 4255:300 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 14041ms total) +T4E58 4255:300 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 14041ms total) +T4E58 4255:300 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 14041ms total) +T4E58 4255:300 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0001ms, 14042ms total) +T4E58 4255:301 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000002F (0000ms, 14042ms total) +T4E58 4255:301 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 14045ms total) +T4E58 4255:305 JLINK_IsHalted() returns FALSE (0001ms, 14047ms total) +T4E58 4255:337 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 14051ms total) +T4E58 4255:342 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0001ms, 14047ms total) +T4E58 4255:343 JLINK_ClrBPEx(BPHandle = 0x0000002F) returns 0x00 (0000ms, 14047ms total) +T4E58 4255:343 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 14047ms total) +T4E58 4255:346 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 09 78 29 70 10 21 69 70 AE 70 48 21 E9 70 2E 71 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 14053ms total) +T4E58 4255:352 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 40 F4 80 57 01 E0 20 F4 80 57 58 49 B1 F8 BE 00 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0004ms, 14057ms total) +T4E58 4255:356 JLINK_WriteReg(R0, 0x0800AC00) returns 0x00 (0000ms, 14057ms total) +T4E58 4255:356 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 14057ms total) +T4E58 4255:356 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0001ms, 14058ms total) +T4E58 4255:357 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 14058ms total) +T4E58 4255:357 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 14058ms total) +T4E58 4255:357 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 14058ms total) +T4E58 4255:357 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 14058ms total) +T4E58 4255:357 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 14058ms total) +T4E58 4255:357 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 14058ms total) +T4E58 4255:357 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 14058ms total) +T4E58 4255:358 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 14058ms total) +T4E58 4255:358 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 14058ms total) +T4E58 4255:358 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 14058ms total) +T4E58 4255:358 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 14058ms total) +T4E58 4255:358 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 14058ms total) +T4E58 4255:358 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 14058ms total) +T4E58 4255:358 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0001ms, 14059ms total) +T4E58 4255:359 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 14059ms total) +T4E58 4255:359 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 14059ms total) +T4E58 4255:359 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 14059ms total) +T4E58 4255:359 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000030 (0000ms, 14059ms total) +T4E58 4255:359 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0005ms, 14064ms total) +T4E58 4255:364 JLINK_IsHalted() returns FALSE (0001ms, 14065ms total) +T4E58 4255:385 JLINK_IsHalted() returns FALSE (0001ms, 14065ms total) +T4E58 4255:416 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0007ms, 14071ms total) +T4E58 4255:423 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 14064ms total) +T4E58 4255:423 JLINK_ClrBPEx(BPHandle = 0x00000030) returns 0x00 (0000ms, 14064ms total) +T4E58 4255:424 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 14065ms total) +T4E58 4255:425 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 46 50 CE E7 F4 0D 00 20 10 08 00 20 D4 00 00 20 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0007ms, 14072ms total) +T4E58 4255:432 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 07 EA C3 03 A0 F8 6A 30 4F F4 7A 73 0C FB 06 FC ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0003ms, 14075ms total) +T4E58 4255:435 JLINK_WriteReg(R0, 0x0800B000) returns 0x00 (0000ms, 14075ms total) +T4E58 4255:435 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 14075ms total) +T4E58 4255:435 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 14075ms total) +T4E58 4255:435 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 14075ms total) +T4E58 4255:435 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 14075ms total) +T4E58 4255:435 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 14075ms total) +T4E58 4255:435 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 14075ms total) +T4E58 4255:435 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 14075ms total) +T4E58 4255:435 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 14075ms total) +T4E58 4255:435 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0001ms, 14076ms total) +T4E58 4255:436 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 14076ms total) +T4E58 4255:436 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 14076ms total) +T4E58 4255:436 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 14076ms total) +T4E58 4255:436 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 14076ms total) +T4E58 4255:436 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 14076ms total) +T4E58 4255:436 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 14076ms total) +T4E58 4255:436 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 14076ms total) +T4E58 4255:436 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 14076ms total) +T4E58 4255:436 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 14076ms total) +T4E58 4255:437 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 14076ms total) +T4E58 4255:437 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000031 (0000ms, 14076ms total) +T4E58 4255:437 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0005ms, 14081ms total) +T4E58 4255:442 JLINK_IsHalted() returns FALSE (0000ms, 14081ms total) +T4E58 4255:463 JLINK_IsHalted() returns FALSE (0003ms, 14084ms total) +T4E58 4255:479 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0007ms, 14088ms total) +T4E58 4255:486 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0001ms, 14082ms total) +T4E58 4255:487 JLINK_ClrBPEx(BPHandle = 0x00000031) returns 0x00 (0000ms, 14082ms total) +T4E58 4255:487 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 14082ms total) +T4E58 4255:490 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 00 F1 E0 20 C0 F8 00 21 70 BD 01 F0 1F 00 82 40 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 14088ms total) +T4E58 4255:497 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 81 71 0A 21 01 73 0F 21 81 74 14 21 01 76 1E 21 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0003ms, 14091ms total) +T4E58 4255:500 JLINK_WriteReg(R0, 0x0800B400) returns 0x00 (0001ms, 14092ms total) +T4E58 4255:501 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 14092ms total) +T4E58 4255:501 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 14092ms total) +T4E58 4255:501 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 14092ms total) +T4E58 4255:501 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 14092ms total) +T4E58 4255:501 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 14092ms total) +T4E58 4255:501 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0001ms, 14093ms total) +T4E58 4255:502 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 14093ms total) +T4E58 4255:502 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 14093ms total) +T4E58 4255:502 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 14093ms total) +T4E58 4255:502 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 14093ms total) +T4E58 4255:502 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 14093ms total) +T4E58 4255:502 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 14093ms total) +T4E58 4255:502 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 14093ms total) +T4E58 4255:503 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 14094ms total) +T4E58 4255:503 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 14094ms total) +T4E58 4255:503 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 14094ms total) +T4E58 4255:503 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 14094ms total) +T4E58 4255:503 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 14094ms total) +T4E58 4255:503 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 14094ms total) +T4E58 4255:503 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000032 (0000ms, 14094ms total) +T4E58 4255:503 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 14098ms total) +T4E58 4255:509 JLINK_IsHalted() returns FALSE (0005ms, 14105ms total) +T4E58 4255:542 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0008ms, 14108ms total) +T4E58 4255:550 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 14100ms total) +T4E58 4255:550 JLINK_ClrBPEx(BPHandle = 0x00000032) returns 0x00 (0000ms, 14100ms total) +T4E58 4255:550 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 14100ms total) +T4E58 4255:552 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 20 79 40 1C C0 B2 20 71 02 28 1D D1 FE F7 EA FB ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0007ms, 14107ms total) +T4E58 4255:559 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 94 00 A4 F8 48 00 D9 F8 00 10 B1 FB F7 F1 41 43 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0004ms, 14111ms total) +T4E58 4255:564 JLINK_WriteReg(R0, 0x0800B800) returns 0x00 (0000ms, 14111ms total) +T4E58 4255:564 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 14111ms total) +T4E58 4255:564 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 14111ms total) +T4E58 4255:564 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 14111ms total) +T4E58 4255:564 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 14111ms total) +T4E58 4255:564 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 14111ms total) +T4E58 4255:564 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 14111ms total) +T4E58 4255:564 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0001ms, 14112ms total) +T4E58 4255:565 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0002ms, 14114ms total) +T4E58 4255:567 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 14114ms total) +T4E58 4255:567 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 14114ms total) +T4E58 4255:567 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 14114ms total) +T4E58 4255:567 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 14114ms total) +T4E58 4255:567 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 14114ms total) +T4E58 4255:567 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 14114ms total) +T4E58 4255:567 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0001ms, 14115ms total) +T4E58 4255:568 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 14115ms total) +T4E58 4255:568 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 14115ms total) +T4E58 4255:568 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 14115ms total) +T4E58 4255:568 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 14115ms total) +T4E58 4255:568 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000033 (0000ms, 14115ms total) +T4E58 4255:568 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0008ms, 14123ms total) +T4E58 4255:576 JLINK_IsHalted() returns FALSE (0004ms, 14127ms total) +T4E58 4255:590 JLINK_IsHalted() returns FALSE (0000ms, 14123ms total) +T4E58 4255:605 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0008ms, 14131ms total) +T4E58 4255:613 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 14123ms total) +T4E58 4255:613 JLINK_ClrBPEx(BPHandle = 0x00000033) returns 0x00 (0000ms, 14123ms total) +T4E58 4255:613 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 14123ms total) +T4E58 4255:615 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 01 2F 07 D0 AA 78 01 2A 0E D0 E9 78 01 29 15 D0 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 14129ms total) +T4E58 4255:621 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 01 79 8D F8 02 10 81 78 8D F8 03 10 41 78 8D F8 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0004ms, 14133ms total) +T4E58 4255:625 JLINK_WriteReg(R0, 0x0800BC00) returns 0x00 (0000ms, 14133ms total) +T4E58 4255:625 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 14133ms total) +T4E58 4255:625 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0001ms, 14134ms total) +T4E58 4255:626 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 14134ms total) +T4E58 4255:626 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 14134ms total) +T4E58 4255:626 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0002ms, 14136ms total) +T4E58 4255:628 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 14136ms total) +T4E58 4255:628 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 14136ms total) +T4E58 4255:628 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 14136ms total) +T4E58 4255:630 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 14138ms total) +T4E58 4255:630 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 14138ms total) +T4E58 4255:630 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 14138ms total) +T4E58 4255:630 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 14138ms total) +T4E58 4255:630 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 14138ms total) +T4E58 4255:630 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 14138ms total) +T4E58 4255:630 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 14138ms total) +T4E58 4255:630 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 14138ms total) +T4E58 4255:630 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0001ms, 14139ms total) +T4E58 4255:631 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 14139ms total) +T4E58 4255:631 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 14139ms total) +T4E58 4255:631 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000034 (0000ms, 14139ms total) +T4E58 4255:631 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 14142ms total) +T4E58 4255:634 JLINK_IsHalted() returns FALSE (0001ms, 14143ms total) +T4E58 4255:668 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 14148ms total) +T4E58 4255:674 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 14142ms total) +T4E58 4255:674 JLINK_ClrBPEx(BPHandle = 0x00000034) returns 0x00 (0000ms, 14142ms total) +T4E58 4255:674 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 14142ms total) +T4E58 4255:681 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 01 1E 6F 20 63 0C 64 69 AF 78 4B FA 18 1B 10 1A ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 14148ms total) +T4E58 4255:687 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0004ms, 14152ms total) +T4E58 4255:691 JLINK_WriteReg(R0, 0x0800C000) returns 0x00 (0000ms, 14152ms total) +T4E58 4255:691 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 14152ms total) +T4E58 4255:691 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 14152ms total) +T4E58 4255:691 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 14152ms total) +T4E58 4255:691 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 14152ms total) +T4E58 4255:691 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0001ms, 14153ms total) +T4E58 4255:692 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 14153ms total) +T4E58 4255:692 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 14153ms total) +T4E58 4255:692 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 14153ms total) +T4E58 4255:692 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 14153ms total) +T4E58 4255:692 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 14153ms total) +T4E58 4255:692 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 14153ms total) +T4E58 4255:693 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 14154ms total) +T4E58 4255:693 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 14154ms total) +T4E58 4255:693 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 14154ms total) +T4E58 4255:693 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 14154ms total) +T4E58 4255:693 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 14154ms total) +T4E58 4255:693 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0004ms, 14158ms total) +T4E58 4255:697 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 14158ms total) +T4E58 4255:698 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 14159ms total) +T4E58 4255:698 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000035 (0000ms, 14159ms total) +T4E58 4255:698 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 14163ms total) +T4E58 4255:702 JLINK_IsHalted() returns FALSE (0001ms, 14164ms total) +T4E58 4255:714 JLINK_IsHalted() returns FALSE (0003ms, 14166ms total) +T4E58 4255:745 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0009ms, 14172ms total) +T4E58 4255:754 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0002ms, 14165ms total) +T4E58 4255:756 JLINK_ClrBPEx(BPHandle = 0x00000035) returns 0x00 (0000ms, 14165ms total) +T4E58 4255:756 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 14165ms total) +T4E58 4255:760 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0007ms, 14172ms total) +T4E58 4255:767 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0005ms, 14177ms total) +T4E58 4255:772 JLINK_WriteReg(R0, 0x0800C400) returns 0x00 (0000ms, 14177ms total) +T4E58 4255:772 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 14177ms total) +T4E58 4255:772 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 14177ms total) +T4E58 4255:772 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 14177ms total) +T4E58 4255:772 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0001ms, 14178ms total) +T4E58 4255:773 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 14178ms total) +T4E58 4255:773 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 14178ms total) +T4E58 4255:773 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 14178ms total) +T4E58 4255:773 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 14178ms total) +T4E58 4255:773 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 14178ms total) +T4E58 4255:773 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 14178ms total) +T4E58 4255:773 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0001ms, 14179ms total) +T4E58 4255:774 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 14179ms total) +T4E58 4255:774 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 14179ms total) +T4E58 4255:774 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 14179ms total) +T4E58 4255:774 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 14179ms total) +T4E58 4255:774 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 14179ms total) +T4E58 4255:774 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 14179ms total) +T4E58 4255:774 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0001ms, 14180ms total) +T4E58 4255:775 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 14180ms total) +T4E58 4255:775 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000036 (0000ms, 14180ms total) +T4E58 4255:775 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0005ms, 14185ms total) +T4E58 4255:780 JLINK_IsHalted() returns FALSE (0003ms, 14188ms total) +T4E58 4255:793 JLINK_IsHalted() returns FALSE (0001ms, 14186ms total) +T4E58 4255:808 JLINK_IsHalted() returns FALSE (0001ms, 14186ms total) +T4E58 4255:856 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0007ms, 14192ms total) +T4E58 4255:863 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 14185ms total) +T4E58 4255:863 JLINK_ClrBPEx(BPHandle = 0x00000036) returns 0x00 (0000ms, 14185ms total) +T4E58 4255:863 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 14185ms total) +T4E58 4255:866 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 2D E9 FC 47 FF F7 78 FB DF F8 98 93 E4 4C B0 FB ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 14191ms total) +T4E58 4255:872 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: E8 E7 E1 61 00 E0 E6 61 E3 78 03 B9 A6 70 BC F8 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0005ms, 14196ms total) +T4E58 4255:877 JLINK_WriteReg(R0, 0x0800C800) returns 0x00 (0000ms, 14196ms total) +T4E58 4255:877 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 14196ms total) +T4E58 4255:877 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 14196ms total) +T4E58 4255:877 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 14196ms total) +T4E58 4255:877 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0001ms, 14197ms total) +T4E58 4255:878 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 14197ms total) +T4E58 4255:878 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 14197ms total) +T4E58 4255:878 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 14197ms total) +T4E58 4255:878 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 14197ms total) +T4E58 4255:878 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 14197ms total) +T4E58 4255:879 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0001ms, 14199ms total) +T4E58 4255:880 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 14199ms total) +T4E58 4255:880 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 14199ms total) +T4E58 4255:880 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 14199ms total) +T4E58 4255:882 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 14199ms total) +T4E58 4255:882 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 14199ms total) +T4E58 4255:882 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 14199ms total) +T4E58 4255:882 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 14199ms total) +T4E58 4255:882 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 14199ms total) +T4E58 4255:882 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0001ms, 14200ms total) +T4E58 4255:883 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000037 (0000ms, 14200ms total) +T4E58 4255:883 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 14204ms total) +T4E58 4255:887 JLINK_IsHalted() returns FALSE (0001ms, 14205ms total) +T4E58 4255:919 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 14210ms total) +T4E58 4255:925 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 14204ms total) +T4E58 4255:925 JLINK_ClrBPEx(BPHandle = 0x00000037) returns 0x00 (0000ms, 14204ms total) +T4E58 4255:925 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 14204ms total) +T4E58 4255:930 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 41 00 C6 B2 19 09 DD E9 0A 8C 03 F0 0F 00 01 EB ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 14210ms total) +T4E58 4255:936 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 46 22 43 1C 0A 2B 01 D2 05 A1 00 E0 06 A1 30 BC ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0004ms, 14214ms total) +T4E58 4255:940 JLINK_WriteReg(R0, 0x0800CC00) returns 0x00 (0000ms, 14214ms total) +T4E58 4255:940 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 14214ms total) +T4E58 4255:941 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 14215ms total) +T4E58 4255:941 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 14215ms total) +T4E58 4255:941 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 14215ms total) +T4E58 4255:941 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 14215ms total) +T4E58 4255:941 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0001ms, 14216ms total) +T4E58 4255:942 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 14216ms total) +T4E58 4255:942 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 14216ms total) +T4E58 4255:942 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 14216ms total) +T4E58 4255:942 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 14216ms total) +T4E58 4255:942 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 14216ms total) +T4E58 4255:942 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 14216ms total) +T4E58 4255:942 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0001ms, 14217ms total) +T4E58 4255:943 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 14217ms total) +T4E58 4255:943 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 14217ms total) +T4E58 4255:943 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 14217ms total) +T4E58 4255:943 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 14217ms total) +T4E58 4255:943 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 14217ms total) +T4E58 4255:943 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 14217ms total) +T4E58 4255:944 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000038 (0000ms, 14218ms total) +T4E58 4255:944 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 14222ms total) +T4E58 4255:948 JLINK_IsHalted() returns FALSE (0002ms, 14224ms total) +T4E58 4255:981 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 14228ms total) +T4E58 4255:987 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 14222ms total) +T4E58 4255:987 JLINK_ClrBPEx(BPHandle = 0x00000038) returns 0x00 (0000ms, 14222ms total) +T4E58 4255:987 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 14222ms total) +T4E58 4255:996 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 5E B9 92 F8 2A 60 76 1C F6 B2 82 F8 2A 60 86 42 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0007ms, 14229ms total) +T4E58 4256:003 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 9D 42 0A D2 0B 7E 5B 1C DB B2 0B 76 01 2B 05 D9 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0004ms, 14233ms total) +T4E58 4256:007 JLINK_WriteReg(R0, 0x0800D000) returns 0x00 (0000ms, 14233ms total) +T4E58 4256:007 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 14233ms total) +T4E58 4256:007 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 14233ms total) +T4E58 4256:007 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 14233ms total) +T4E58 4256:007 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0001ms, 14234ms total) +T4E58 4256:008 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 14234ms total) +T4E58 4256:008 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 14234ms total) +T4E58 4256:008 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 14234ms total) +T4E58 4256:008 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 14234ms total) +T4E58 4256:008 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 14234ms total) +T4E58 4256:008 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 14234ms total) +T4E58 4256:008 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 14234ms total) +T4E58 4256:008 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0001ms, 14235ms total) +T4E58 4256:009 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 14235ms total) +T4E58 4256:009 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 14235ms total) +T4E58 4256:009 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 14235ms total) +T4E58 4256:009 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 14235ms total) +T4E58 4256:009 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 14235ms total) +T4E58 4256:009 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 14235ms total) +T4E58 4256:009 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 14235ms total) +T4E58 4256:009 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000039 (0000ms, 14235ms total) +T4E58 4256:009 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0006ms, 14241ms total) +T4E58 4256:015 JLINK_IsHalted() returns FALSE (0001ms, 14242ms total) +T4E58 4256:060 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 14247ms total) +T4E58 4256:066 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 14241ms total) +T4E58 4256:066 JLINK_ClrBPEx(BPHandle = 0x00000039) returns 0x00 (0000ms, 14241ms total) +T4E58 4256:066 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 14241ms total) +T4E58 4256:070 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 6D 1C ED B2 C5 75 01 2D 08 D9 80 F8 22 30 B1 F8 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 14247ms total) +T4E58 4256:076 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 4E 07 00 20 10 08 00 20 5E 05 00 20 F0 B5 3B 49 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0004ms, 14251ms total) +T4E58 4256:080 JLINK_WriteReg(R0, 0x0800D400) returns 0x00 (0000ms, 14251ms total) +T4E58 4256:080 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 14251ms total) +T4E58 4256:080 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 14251ms total) +T4E58 4256:080 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 14251ms total) +T4E58 4256:080 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 14251ms total) +T4E58 4256:080 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 14251ms total) +T4E58 4256:080 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 14251ms total) +T4E58 4256:080 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 14251ms total) +T4E58 4256:080 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 14251ms total) +T4E58 4256:080 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 14251ms total) +T4E58 4256:080 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0001ms, 14252ms total) +T4E58 4256:081 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 14252ms total) +T4E58 4256:081 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 14252ms total) +T4E58 4256:081 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 14252ms total) +T4E58 4256:081 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 14252ms total) +T4E58 4256:081 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 14252ms total) +T4E58 4256:081 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 14252ms total) +T4E58 4256:081 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0001ms, 14253ms total) +T4E58 4256:082 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 14253ms total) +T4E58 4256:082 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0001ms, 14254ms total) +T4E58 4256:083 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000003A (0000ms, 14254ms total) +T4E58 4256:083 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 14258ms total) +T4E58 4256:087 JLINK_IsHalted() returns FALSE (0000ms, 14258ms total) +T4E58 4256:109 JLINK_IsHalted() returns FALSE (0002ms, 14260ms total) +T4E58 4256:123 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0007ms, 14265ms total) +T4E58 4256:130 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 14258ms total) +T4E58 4256:130 JLINK_ClrBPEx(BPHandle = 0x0000003A) returns 0x00 (0000ms, 14258ms total) +T4E58 4256:130 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 14258ms total) +T4E58 4256:133 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 90 F8 32 40 64 1C E4 B2 80 F8 32 40 03 2C 05 D9 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 14265ms total) +T4E58 4256:139 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 34 2E 70 38 2E 70 69 63 3D 34 35 FF FF FF 00 00 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0005ms, 14270ms total) +T4E58 4256:144 JLINK_WriteReg(R0, 0x0800D800) returns 0x00 (0000ms, 14270ms total) +T4E58 4256:144 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0001ms, 14271ms total) +T4E58 4256:145 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 14271ms total) +T4E58 4256:145 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 14271ms total) +T4E58 4256:145 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 14271ms total) +T4E58 4256:145 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 14271ms total) +T4E58 4256:145 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 14271ms total) +T4E58 4256:145 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 14271ms total) +T4E58 4256:145 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0001ms, 14272ms total) +T4E58 4256:146 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 14272ms total) +T4E58 4256:146 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 14272ms total) +T4E58 4256:146 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 14272ms total) +T4E58 4256:146 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 14272ms total) +T4E58 4256:146 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 14272ms total) +T4E58 4256:146 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 14272ms total) +T4E58 4256:146 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0001ms, 14273ms total) +T4E58 4256:147 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 14273ms total) +T4E58 4256:147 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 14273ms total) +T4E58 4256:147 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 14273ms total) +T4E58 4256:147 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 14273ms total) +T4E58 4256:147 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000003B (0000ms, 14273ms total) +T4E58 4256:147 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 14277ms total) +T4E58 4256:152 JLINK_IsHalted() returns FALSE (0001ms, 14279ms total) +T4E58 4256:185 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0007ms, 14285ms total) +T4E58 4256:192 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 14285ms total) +T4E58 4256:192 JLINK_ClrBPEx(BPHandle = 0x0000003B) returns 0x00 (0000ms, 14285ms total) +T4E58 4256:192 JLINK_ReadReg(R0) returns 0x00000000 (0001ms, 14286ms total) +T4E58 4256:196 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 5D D0 90 A0 05 F0 F0 FF 20 7B 20 28 59 D0 92 A0 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 14292ms total) +T4E58 4256:202 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 31 2E 70 69 63 3D 39 37 FF FF FF 00 70 61 67 65 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0003ms, 14295ms total) +T4E58 4256:205 JLINK_WriteReg(R0, 0x0800DC00) returns 0x00 (0000ms, 14295ms total) +T4E58 4256:205 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0002ms, 14297ms total) +T4E58 4256:207 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 14297ms total) +T4E58 4256:207 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 14297ms total) +T4E58 4256:207 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 14297ms total) +T4E58 4256:207 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 14297ms total) +T4E58 4256:207 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 14297ms total) +T4E58 4256:207 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 14297ms total) +T4E58 4256:207 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 14297ms total) +T4E58 4256:207 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 14297ms total) +T4E58 4256:207 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0001ms, 14298ms total) +T4E58 4256:208 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 14298ms total) +T4E58 4256:208 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 14298ms total) +T4E58 4256:208 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 14298ms total) +T4E58 4256:208 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 14298ms total) +T4E58 4256:208 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 14298ms total) +T4E58 4256:208 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 14298ms total) +T4E58 4256:209 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 14298ms total) +T4E58 4256:209 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 14298ms total) +T4E58 4256:209 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 14298ms total) +T4E58 4256:209 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000003C (0000ms, 14298ms total) +T4E58 4256:209 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 14302ms total) +T4E58 4256:213 JLINK_IsHalted() returns FALSE (0001ms, 14303ms total) +T4E58 4256:233 JLINK_IsHalted() returns FALSE (0001ms, 14303ms total) +T4E58 4256:249 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 14308ms total) +T4E58 4256:255 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 14302ms total) +T4E58 4256:255 JLINK_ClrBPEx(BPHandle = 0x0000003C) returns 0x00 (0000ms, 14302ms total) +T4E58 4256:255 JLINK_ReadReg(R0) returns 0x00000000 (0001ms, 14303ms total) +T4E58 4256:258 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 37 2E 70 35 2E 70 69 63 3D 38 36 FF FF FF 00 00 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 14309ms total) +T4E58 4256:264 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 08 D5 3A A0 0A 34 01 68 29 60 41 68 69 60 00 89 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0003ms, 14312ms total) +T4E58 4256:267 JLINK_WriteReg(R0, 0x0800E000) returns 0x00 (0000ms, 14312ms total) +T4E58 4256:267 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 14312ms total) +T4E58 4256:267 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 14312ms total) +T4E58 4256:267 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 14312ms total) +T4E58 4256:267 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0001ms, 14313ms total) +T4E58 4256:268 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 14313ms total) +T4E58 4256:268 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 14313ms total) +T4E58 4256:268 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 14313ms total) +T4E58 4256:268 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 14313ms total) +T4E58 4256:268 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 14313ms total) +T4E58 4256:268 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 14313ms total) +T4E58 4256:268 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 14313ms total) +T4E58 4256:268 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0002ms, 14315ms total) +T4E58 4256:270 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 14315ms total) +T4E58 4256:270 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 14315ms total) +T4E58 4256:270 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 14315ms total) +T4E58 4256:270 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 14315ms total) +T4E58 4256:270 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 14315ms total) +T4E58 4256:270 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 14315ms total) +T4E58 4256:270 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0001ms, 14316ms total) +T4E58 4256:271 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000003D (0000ms, 14316ms total) +T4E58 4256:271 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 14319ms total) +T4E58 4256:274 JLINK_IsHalted() returns FALSE (0000ms, 14319ms total) +T4E58 4256:296 JLINK_IsHalted() returns FALSE (0001ms, 14320ms total) +T4E58 4256:311 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 14325ms total) +T4E58 4256:317 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0001ms, 14326ms total) +T4E58 4256:318 JLINK_ClrBPEx(BPHandle = 0x0000003D) returns 0x00 (0000ms, 14326ms total) +T4E58 4256:318 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 14326ms total) +T4E58 4256:320 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 01 EB 82 12 26 F8 10 20 40 1C C0 B2 03 28 F5 D3 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0005ms, 14331ms total) +T4E58 4256:325 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 93 FB DF F8 DC 92 49 46 08 F0 94 FA 08 F0 04 FA ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0004ms, 14335ms total) +T4E58 4256:329 JLINK_WriteReg(R0, 0x0800E400) returns 0x00 (0000ms, 14335ms total) +T4E58 4256:329 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 14335ms total) +T4E58 4256:329 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 14335ms total) +T4E58 4256:329 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 14335ms total) +T4E58 4256:330 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 14336ms total) +T4E58 4256:330 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 14336ms total) +T4E58 4256:330 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 14336ms total) +T4E58 4256:330 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 14336ms total) +T4E58 4256:330 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 14336ms total) +T4E58 4256:330 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0001ms, 14337ms total) +T4E58 4256:331 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 14337ms total) +T4E58 4256:331 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 14337ms total) +T4E58 4256:331 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 14337ms total) +T4E58 4256:331 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 14337ms total) +T4E58 4256:331 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 14337ms total) +T4E58 4256:331 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 14337ms total) +T4E58 4256:331 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0001ms, 14338ms total) +T4E58 4256:332 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 14338ms total) +T4E58 4256:332 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 14338ms total) +T4E58 4256:332 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 14338ms total) +T4E58 4256:332 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000003E (0000ms, 14338ms total) +T4E58 4256:332 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 14342ms total) +T4E58 4256:336 JLINK_IsHalted() returns FALSE (0001ms, 14343ms total) +T4E58 4256:357 JLINK_IsHalted() returns FALSE (0000ms, 14342ms total) +T4E58 4256:373 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 14347ms total) +T4E58 4256:378 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 14342ms total) +T4E58 4256:378 JLINK_ClrBPEx(BPHandle = 0x0000003E) returns 0x00 (0001ms, 14343ms total) +T4E58 4256:379 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 14343ms total) +T4E58 4256:381 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 08 F0 58 F9 02 46 0B 46 F5 A0 05 F0 ED F9 20 8F ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 14349ms total) +T4E58 4256:387 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 3D 22 25 64 22 FF FF FF 00 00 00 00 70 61 67 65 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0003ms, 14352ms total) +T4E58 4256:390 JLINK_WriteReg(R0, 0x0800E800) returns 0x00 (0000ms, 14352ms total) +T4E58 4256:390 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 14352ms total) +T4E58 4256:390 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0002ms, 14354ms total) +T4E58 4256:392 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 14354ms total) +T4E58 4256:392 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 14354ms total) +T4E58 4256:392 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 14354ms total) +T4E58 4256:392 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 14354ms total) +T4E58 4256:392 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 14354ms total) +T4E58 4256:392 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 14354ms total) +T4E58 4256:392 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 14354ms total) +T4E58 4256:392 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 14354ms total) +T4E58 4256:393 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 14355ms total) +T4E58 4256:393 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 14355ms total) +T4E58 4256:393 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 14355ms total) +T4E58 4256:393 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 14355ms total) +T4E58 4256:393 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 14355ms total) +T4E58 4256:393 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 14355ms total) +T4E58 4256:393 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 14355ms total) +T4E58 4256:394 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 14356ms total) +T4E58 4256:394 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 14356ms total) +T4E58 4256:394 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000003F (0000ms, 14356ms total) +T4E58 4256:394 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 14360ms total) +T4E58 4256:398 JLINK_IsHalted() returns FALSE (0001ms, 14361ms total) +T4E58 4256:419 JLINK_IsHalted() returns FALSE (0001ms, 14361ms total) +T4E58 4256:435 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 14365ms total) +T4E58 4256:440 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 14360ms total) +T4E58 4256:440 JLINK_ClrBPEx(BPHandle = 0x0000003F) returns 0x00 (0000ms, 14360ms total) +T4E58 4256:440 JLINK_ReadReg(R0) returns 0x00000000 (0001ms, 14361ms total) +T4E58 4256:444 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 2E 74 78 74 3D 22 25 2E 31 66 22 FF FF FF 00 00 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 14367ms total) +T4E58 4256:450 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: B0 FB F6 F0 00 B2 00 EB 80 00 C1 17 00 EB D1 60 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0005ms, 14372ms total) +T4E58 4256:455 JLINK_WriteReg(R0, 0x0800EC00) returns 0x00 (0001ms, 14373ms total) +T4E58 4256:456 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 14373ms total) +T4E58 4256:456 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 14373ms total) +T4E58 4256:456 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 14373ms total) +T4E58 4256:456 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 14373ms total) +T4E58 4256:456 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 14373ms total) +T4E58 4256:457 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 14374ms total) +T4E58 4256:457 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 14374ms total) +T4E58 4256:457 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 14374ms total) +T4E58 4256:457 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 14374ms total) +T4E58 4256:457 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 14374ms total) +T4E58 4256:457 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0001ms, 14375ms total) +T4E58 4256:458 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 14375ms total) +T4E58 4256:458 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 14375ms total) +T4E58 4256:458 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 14375ms total) +T4E58 4256:458 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 14375ms total) +T4E58 4256:458 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0001ms, 14376ms total) +T4E58 4256:459 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 14376ms total) +T4E58 4256:459 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 14376ms total) +T4E58 4256:459 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 14376ms total) +T4E58 4256:459 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000040 (0000ms, 14376ms total) +T4E58 4256:459 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0005ms, 14381ms total) +T4E58 4256:464 JLINK_IsHalted() returns FALSE (0001ms, 14382ms total) +T4E58 4256:497 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0007ms, 14388ms total) +T4E58 4256:504 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 14388ms total) +T4E58 4256:504 JLINK_ClrBPEx(BPHandle = 0x00000040) returns 0x00 (0000ms, 14388ms total) +T4E58 4256:504 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 14388ms total) +T4E58 4256:506 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 04 F0 F2 FD 60 8B 40 01 B0 FB F6 F0 00 B2 00 EB ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0007ms, 14395ms total) +T4E58 4256:513 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 70 61 67 65 32 2E 74 34 2E 74 78 74 3D 22 25 64 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0004ms, 14399ms total) +T4E58 4256:517 JLINK_WriteReg(R0, 0x0800F000) returns 0x00 (0000ms, 14399ms total) +T4E58 4256:517 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 14399ms total) +T4E58 4256:517 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 14399ms total) +T4E58 4256:517 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 14399ms total) +T4E58 4256:517 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 14399ms total) +T4E58 4256:518 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 14400ms total) +T4E58 4256:518 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 14400ms total) +T4E58 4256:518 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 14400ms total) +T4E58 4256:518 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 14400ms total) +T4E58 4256:518 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 14400ms total) +T4E58 4256:518 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 14400ms total) +T4E58 4256:518 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 14400ms total) +T4E58 4256:518 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0001ms, 14401ms total) +T4E58 4256:519 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 14401ms total) +T4E58 4256:519 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 14401ms total) +T4E58 4256:519 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 14401ms total) +T4E58 4256:519 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 14401ms total) +T4E58 4256:519 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 14401ms total) +T4E58 4256:519 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 14401ms total) +T4E58 4256:519 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 14401ms total) +T4E58 4256:519 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000041 (0000ms, 14401ms total) +T4E58 4256:519 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0006ms, 14407ms total) +T4E58 4256:525 JLINK_IsHalted() returns FALSE (0001ms, 14408ms total) +T4E58 4256:561 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0007ms, 14414ms total) +T4E58 4256:568 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 14407ms total) +T4E58 4256:568 JLINK_ClrBPEx(BPHandle = 0x00000041) returns 0x00 (0000ms, 14407ms total) +T4E58 4256:568 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 14407ms total) +T4E58 4256:571 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: FF FF 00 00 70 61 67 65 33 2E 74 33 2E 74 78 74 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 14413ms total) +T4E58 4256:577 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 1E 00 43 79 82 79 06 A1 04 A8 F0 F7 41 FE 04 A9 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0005ms, 14418ms total) +T4E58 4256:582 JLINK_WriteReg(R0, 0x0800F400) returns 0x00 (0000ms, 14418ms total) +T4E58 4256:582 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 14418ms total) +T4E58 4256:582 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 14418ms total) +T4E58 4256:582 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 14418ms total) +T4E58 4256:582 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0001ms, 14419ms total) +T4E58 4256:583 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 14419ms total) +T4E58 4256:583 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 14419ms total) +T4E58 4256:583 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 14419ms total) +T4E58 4256:583 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 14419ms total) +T4E58 4256:583 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0001ms, 14420ms total) +T4E58 4256:584 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 14420ms total) +T4E58 4256:584 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0001ms, 14421ms total) +T4E58 4256:585 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 14421ms total) +T4E58 4256:585 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 14421ms total) +T4E58 4256:585 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 14421ms total) +T4E58 4256:585 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 14421ms total) +T4E58 4256:585 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0001ms, 14422ms total) +T4E58 4256:586 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 14422ms total) +T4E58 4256:586 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 14422ms total) +T4E58 4256:586 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 14422ms total) +T4E58 4256:586 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000042 (0000ms, 14422ms total) +T4E58 4256:586 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0005ms, 14427ms total) +T4E58 4256:591 JLINK_IsHalted() returns FALSE (0001ms, 14428ms total) +T4E58 4256:608 JLINK_IsHalted() returns FALSE (0001ms, 14428ms total) +T4E58 4256:623 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 14433ms total) +T4E58 4256:629 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 14433ms total) +T4E58 4256:629 JLINK_ClrBPEx(BPHandle = 0x00000042) returns 0x00 (0000ms, 14433ms total) +T4E58 4256:629 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 14433ms total) +T4E58 4256:632 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 20 46 07 F0 C7 FA 39 46 07 F0 E2 F9 07 F0 52 F9 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 14439ms total) +T4E58 4256:638 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 10 B5 51 4C 51 A0 B4 F8 BA 10 04 F0 9F F8 B4 F8 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0004ms, 14443ms total) +T4E58 4256:642 JLINK_WriteReg(R0, 0x0800F800) returns 0x00 (0000ms, 14443ms total) +T4E58 4256:642 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 14443ms total) +T4E58 4256:642 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 14443ms total) +T4E58 4256:642 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 14443ms total) +T4E58 4256:642 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 14443ms total) +T4E58 4256:642 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 14443ms total) +T4E58 4256:642 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0002ms, 14445ms total) +T4E58 4256:644 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 14445ms total) +T4E58 4256:644 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 14445ms total) +T4E58 4256:644 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 14445ms total) +T4E58 4256:644 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0001ms, 14446ms total) +T4E58 4256:645 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 14446ms total) +T4E58 4256:645 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 14446ms total) +T4E58 4256:645 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 14446ms total) +T4E58 4256:645 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 14446ms total) +T4E58 4256:645 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 14446ms total) +T4E58 4256:645 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0001ms, 14447ms total) +T4E58 4256:646 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 14447ms total) +T4E58 4256:646 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 14447ms total) +T4E58 4256:646 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 14447ms total) +T4E58 4256:646 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000043 (0000ms, 14447ms total) +T4E58 4256:646 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 14451ms total) +T4E58 4256:650 JLINK_IsHalted() returns FALSE (0001ms, 14452ms total) +T4E58 4256:671 JLINK_IsHalted() returns FALSE (0001ms, 14452ms total) +T4E58 4256:686 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 14457ms total) +T4E58 4256:692 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 14451ms total) +T4E58 4256:692 JLINK_ClrBPEx(BPHandle = 0x00000043) returns 0x00 (0000ms, 14451ms total) +T4E58 4256:692 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 14451ms total) +T4E58 4256:694 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 70 61 67 65 34 2E 70 31 2E 70 69 63 3D 33 32 FF ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 14457ms total) +T4E58 4256:700 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 89 06 01 D4 40 05 01 D5 64 A0 00 E0 68 A0 03 F0 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0004ms, 14461ms total) +T4E58 4256:705 JLINK_WriteReg(R0, 0x0800FC00) returns 0x00 (0000ms, 14461ms total) +T4E58 4256:705 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 14461ms total) +T4E58 4256:705 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 14461ms total) +T4E58 4256:705 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 14461ms total) +T4E58 4256:705 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 14461ms total) +T4E58 4256:705 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 14461ms total) +T4E58 4256:705 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 14461ms total) +T4E58 4256:705 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 14461ms total) +T4E58 4256:705 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 14461ms total) +T4E58 4256:705 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 14461ms total) +T4E58 4256:705 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 14461ms total) +T4E58 4256:705 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 14461ms total) +T4E58 4256:707 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 14463ms total) +T4E58 4256:707 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 14463ms total) +T4E58 4256:707 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 14463ms total) +T4E58 4256:707 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 14463ms total) +T4E58 4256:707 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 14463ms total) +T4E58 4256:707 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 14463ms total) +T4E58 4256:707 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 14463ms total) +T4E58 4256:707 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 14463ms total) +T4E58 4256:707 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000044 (0000ms, 14463ms total) +T4E58 4256:708 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 14468ms total) +T4E58 4256:712 JLINK_IsHalted() returns FALSE (0001ms, 14469ms total) +T4E58 4256:732 JLINK_IsHalted() returns FALSE (0002ms, 14470ms total) +T4E58 4256:748 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 14476ms total) +T4E58 4256:754 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 14470ms total) +T4E58 4256:754 JLINK_ClrBPEx(BPHandle = 0x00000044) returns 0x00 (0000ms, 14470ms total) +T4E58 4256:754 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 14470ms total) +T4E58 4256:758 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 34 2E 70 36 2E 70 69 63 3D 34 32 FF FF FF 00 00 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 14477ms total) +T4E58 4256:764 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: F2 F5 4A 68 FB 48 92 FB FA F4 02 68 FA 48 DF F8 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0004ms, 14481ms total) +T4E58 4256:768 JLINK_WriteReg(R0, 0x08010000) returns 0x00 (0000ms, 14481ms total) +T4E58 4256:768 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 14481ms total) +T4E58 4256:769 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 14482ms total) +T4E58 4256:769 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 14482ms total) +T4E58 4256:769 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 14482ms total) +T4E58 4256:769 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 14482ms total) +T4E58 4256:769 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 14482ms total) +T4E58 4256:769 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 14482ms total) +T4E58 4256:769 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0001ms, 14483ms total) +T4E58 4256:770 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 14483ms total) +T4E58 4256:770 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 14483ms total) +T4E58 4256:770 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0001ms, 14484ms total) +T4E58 4256:771 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 14484ms total) +T4E58 4256:771 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 14484ms total) +T4E58 4256:771 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 14484ms total) +T4E58 4256:771 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 14484ms total) +T4E58 4256:771 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 14484ms total) +T4E58 4256:771 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 14484ms total) +T4E58 4256:772 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 14485ms total) +T4E58 4256:772 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 14485ms total) +T4E58 4256:772 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000045 (0000ms, 14485ms total) +T4E58 4256:772 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 14489ms total) +T4E58 4256:776 JLINK_IsHalted() returns FALSE (0001ms, 14490ms total) +T4E58 4256:794 JLINK_IsHalted() returns FALSE (0003ms, 14492ms total) +T4E58 4256:826 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 14498ms total) +T4E58 4256:832 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 14498ms total) +T4E58 4256:832 JLINK_ClrBPEx(BPHandle = 0x00000045) returns 0x00 (0000ms, 14498ms total) +T4E58 4256:832 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 14498ms total) +T4E58 4256:835 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 22 F8 10 70 40 1C C0 B2 14 28 EB D3 BD F8 40 00 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 14504ms total) +T4E58 4256:841 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 94 00 00 20 4E 07 00 20 00 21 10 46 F6 F7 18 FE ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0004ms, 14508ms total) +T4E58 4256:845 JLINK_WriteReg(R0, 0x08010400) returns 0x00 (0000ms, 14508ms total) +T4E58 4256:845 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 14508ms total) +T4E58 4256:845 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0001ms, 14509ms total) +T4E58 4256:846 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 14509ms total) +T4E58 4256:846 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 14509ms total) +T4E58 4256:846 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 14509ms total) +T4E58 4256:846 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 14509ms total) +T4E58 4256:846 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 14509ms total) +T4E58 4256:846 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 14509ms total) +T4E58 4256:846 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 14509ms total) +T4E58 4256:846 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 14509ms total) +T4E58 4256:846 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0001ms, 14510ms total) +T4E58 4256:847 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 14510ms total) +T4E58 4256:847 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 14510ms total) +T4E58 4256:847 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 14510ms total) +T4E58 4256:847 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 14510ms total) +T4E58 4256:847 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 14510ms total) +T4E58 4256:847 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 14510ms total) +T4E58 4256:847 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0001ms, 14511ms total) +T4E58 4256:848 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 14511ms total) +T4E58 4256:848 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000046 (0000ms, 14511ms total) +T4E58 4256:848 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 14515ms total) +T4E58 4256:852 JLINK_IsHalted() returns FALSE (0001ms, 14516ms total) +T4E58 4256:874 JLINK_IsHalted() returns FALSE (0001ms, 14516ms total) +T4E58 4256:889 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0007ms, 14522ms total) +T4E58 4256:896 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0001ms, 14523ms total) +T4E58 4256:897 JLINK_ClrBPEx(BPHandle = 0x00000046) returns 0x00 (0000ms, 14523ms total) +T4E58 4256:897 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 14523ms total) +T4E58 4256:900 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: F1 F0 42 46 B0 FB F2 F1 B0 FB F8 F3 08 FB 13 02 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 14529ms total) +T4E58 4256:906 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 01 28 01 D1 B4 F8 BA 00 01 27 00 F0 FF 08 42 46 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0003ms, 14532ms total) +T4E58 4256:909 JLINK_WriteReg(R0, 0x08010800) returns 0x00 (0000ms, 14532ms total) +T4E58 4256:909 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0001ms, 14533ms total) +T4E58 4256:910 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 14533ms total) +T4E58 4256:910 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 14533ms total) +T4E58 4256:910 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 14533ms total) +T4E58 4256:911 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 14534ms total) +T4E58 4256:911 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 14534ms total) +T4E58 4256:911 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 14534ms total) +T4E58 4256:911 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 14534ms total) +T4E58 4256:911 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 14534ms total) +T4E58 4256:911 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 14534ms total) +T4E58 4256:912 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 14534ms total) +T4E58 4256:912 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 14534ms total) +T4E58 4256:912 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 14534ms total) +T4E58 4256:912 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 14534ms total) +T4E58 4256:912 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 14534ms total) +T4E58 4256:912 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 14534ms total) +T4E58 4256:912 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 14534ms total) +T4E58 4256:912 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0001ms, 14535ms total) +T4E58 4256:913 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 14535ms total) +T4E58 4256:913 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000047 (0000ms, 14535ms total) +T4E58 4256:913 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0005ms, 14540ms total) +T4E58 4256:918 JLINK_IsHalted() returns FALSE (0001ms, 14541ms total) +T4E58 4256:951 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0007ms, 14547ms total) +T4E58 4256:958 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 14540ms total) +T4E58 4256:958 JLINK_ClrBPEx(BPHandle = 0x00000047) returns 0x00 (0000ms, 14540ms total) +T4E58 4256:958 JLINK_ReadReg(R0) returns 0x00000000 (0001ms, 14541ms total) +T4E58 4256:960 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 70 61 67 65 31 32 2E 74 31 2E 74 78 74 3D 22 20 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0007ms, 14548ms total) +T4E58 4256:968 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 01 20 00 EB 80 01 6A A0 02 F0 A0 FE A1 78 E0 78 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0004ms, 14552ms total) +T4E58 4256:972 JLINK_WriteReg(R0, 0x08010C00) returns 0x00 (0000ms, 14552ms total) +T4E58 4256:972 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 14552ms total) +T4E58 4256:972 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 14552ms total) +T4E58 4256:972 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 14552ms total) +T4E58 4256:972 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0001ms, 14553ms total) +T4E58 4256:973 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 14553ms total) +T4E58 4256:973 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 14553ms total) +T4E58 4256:973 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 14553ms total) +T4E58 4256:973 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 14553ms total) +T4E58 4256:973 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0001ms, 14554ms total) +T4E58 4256:974 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 14554ms total) +T4E58 4256:974 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 14554ms total) +T4E58 4256:974 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 14554ms total) +T4E58 4256:974 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 14554ms total) +T4E58 4256:974 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 14554ms total) +T4E58 4256:974 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 14554ms total) +T4E58 4256:974 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0001ms, 14555ms total) +T4E58 4256:975 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 14555ms total) +T4E58 4256:975 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 14555ms total) +T4E58 4256:975 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 14555ms total) +T4E58 4256:975 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000048 (0000ms, 14555ms total) +T4E58 4256:975 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0006ms, 14561ms total) +T4E58 4256:981 JLINK_IsHalted() returns FALSE (0002ms, 14563ms total) +T4E58 4256:998 JLINK_IsHalted() returns FALSE (0001ms, 14562ms total) +T4E58 4257:013 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 14567ms total) +T4E58 4257:019 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 14561ms total) +T4E58 4257:019 JLINK_ClrBPEx(BPHandle = 0x00000048) returns 0x00 (0000ms, 14561ms total) +T4E58 4257:019 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 14561ms total) +T4E58 4257:021 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: FF 00 00 00 70 61 67 65 31 30 2E 74 36 2E 74 78 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0007ms, 14568ms total) +T4E58 4257:028 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 50 B3 AD A0 02 F0 A2 FC 88 F8 0A A0 B4 F8 4C 00 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0006ms, 14574ms total) +T4E58 4257:034 JLINK_WriteReg(R0, 0x08011000) returns 0x00 (0000ms, 14574ms total) +T4E58 4257:034 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 14574ms total) +T4E58 4257:034 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 14574ms total) +T4E58 4257:034 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 14574ms total) +T4E58 4257:034 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 14574ms total) +T4E58 4257:034 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 14574ms total) +T4E58 4257:034 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 14574ms total) +T4E58 4257:035 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 14575ms total) +T4E58 4257:035 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 14575ms total) +T4E58 4257:035 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 14575ms total) +T4E58 4257:035 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 14575ms total) +T4E58 4257:035 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 14575ms total) +T4E58 4257:036 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 14576ms total) +T4E58 4257:036 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 14576ms total) +T4E58 4257:036 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 14576ms total) +T4E58 4257:036 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 14576ms total) +T4E58 4257:036 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 14576ms total) +T4E58 4257:037 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 14577ms total) +T4E58 4257:037 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 14577ms total) +T4E58 4257:037 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 14577ms total) +T4E58 4257:037 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000049 (0000ms, 14577ms total) +T4E58 4257:037 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0005ms, 14582ms total) +T4E58 4257:042 JLINK_IsHalted() returns FALSE (0001ms, 14583ms total) +T4E58 4257:078 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 14587ms total) +T4E58 4257:085 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 14582ms total) +T4E58 4257:085 JLINK_ClrBPEx(BPHandle = 0x00000049) returns 0x00 (0000ms, 14582ms total) +T4E58 4257:085 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 14582ms total) +T4E58 4257:087 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 80 21 47 48 03 F0 6D FD 08 B1 08 21 4E E0 43 4A ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 14588ms total) +T4E58 4257:094 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 40 F0 90 00 22 E0 BA 4A 07 23 31 32 80 21 B9 48 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0004ms, 14592ms total) +T4E58 4257:098 JLINK_WriteReg(R0, 0x08011400) returns 0x00 (0000ms, 14592ms total) +T4E58 4257:098 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 14592ms total) +T4E58 4257:098 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 14592ms total) +T4E58 4257:098 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0001ms, 14593ms total) +T4E58 4257:099 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 14593ms total) +T4E58 4257:099 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 14593ms total) +T4E58 4257:099 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 14593ms total) +T4E58 4257:099 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 14593ms total) +T4E58 4257:099 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0001ms, 14594ms total) +T4E58 4257:100 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 14594ms total) +T4E58 4257:100 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 14594ms total) +T4E58 4257:100 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 14594ms total) +T4E58 4257:100 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 14594ms total) +T4E58 4257:100 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0001ms, 14595ms total) +T4E58 4257:101 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 14595ms total) +T4E58 4257:101 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 14595ms total) +T4E58 4257:101 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 14595ms total) +T4E58 4257:101 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 14595ms total) +T4E58 4257:101 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 14595ms total) +T4E58 4257:101 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 14595ms total) +T4E58 4257:101 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000004A (0000ms, 14595ms total) +T4E58 4257:102 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 14600ms total) +T4E58 4257:106 JLINK_IsHalted() returns FALSE (0001ms, 14601ms total) +T4E58 4257:124 JLINK_IsHalted() returns FALSE (0001ms, 14601ms total) +T4E58 4257:170 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 14606ms total) +T4E58 4257:176 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 14600ms total) +T4E58 4257:176 JLINK_ClrBPEx(BPHandle = 0x0000004A) returns 0x00 (0000ms, 14600ms total) +T4E58 4257:177 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 14600ms total) +T4E58 4257:180 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 0F 00 40 F0 07 00 46 E0 60 4A 07 23 77 32 80 21 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0007ms, 14607ms total) +T4E58 4257:187 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 23 E0 B9 4A 07 23 4D 32 80 21 B8 48 03 F0 1B FA ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0005ms, 14612ms total) +T4E58 4257:192 JLINK_WriteReg(R0, 0x08011800) returns 0x00 (0000ms, 14612ms total) +T4E58 4257:192 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 14612ms total) +T4E58 4257:192 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 14612ms total) +T4E58 4257:192 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 14612ms total) +T4E58 4257:192 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 14612ms total) +T4E58 4257:192 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 14612ms total) +T4E58 4257:192 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 14612ms total) +T4E58 4257:192 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0001ms, 14613ms total) +T4E58 4257:193 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 14613ms total) +T4E58 4257:193 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 14613ms total) +T4E58 4257:193 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 14613ms total) +T4E58 4257:193 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 14613ms total) +T4E58 4257:193 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 14613ms total) +T4E58 4257:193 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0001ms, 14614ms total) +T4E58 4257:194 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 14614ms total) +T4E58 4257:194 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 14614ms total) +T4E58 4257:194 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 14614ms total) +T4E58 4257:194 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 14614ms total) +T4E58 4257:194 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 14614ms total) +T4E58 4257:194 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0001ms, 14615ms total) +T4E58 4257:195 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000004B (0000ms, 14615ms total) +T4E58 4257:195 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 14619ms total) +T4E58 4257:199 JLINK_IsHalted() returns FALSE (0001ms, 14620ms total) +T4E58 4257:233 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 14624ms total) +T4E58 4257:238 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 14619ms total) +T4E58 4257:238 JLINK_ClrBPEx(BPHandle = 0x0000004B) returns 0x00 (0000ms, 14619ms total) +T4E58 4257:240 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 14621ms total) +T4E58 4257:242 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 05 EB 85 01 0B EB 41 01 08 44 EA E7 FF E7 64 A1 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 14627ms total) +T4E58 4257:249 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 05 EB 85 05 0C EB 45 05 15 44 03 E0 01 26 01 E0 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0004ms, 14631ms total) +T4E58 4257:253 JLINK_WriteReg(R0, 0x08011C00) returns 0x00 (0000ms, 14631ms total) +T4E58 4257:253 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 14631ms total) +T4E58 4257:253 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 14631ms total) +T4E58 4257:253 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0001ms, 14632ms total) +T4E58 4257:254 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 14632ms total) +T4E58 4257:254 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 14632ms total) +T4E58 4257:254 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 14632ms total) +T4E58 4257:254 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 14632ms total) +T4E58 4257:254 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0001ms, 14633ms total) +T4E58 4257:255 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 14633ms total) +T4E58 4257:255 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 14633ms total) +T4E58 4257:255 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 14633ms total) +T4E58 4257:255 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 14633ms total) +T4E58 4257:255 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0001ms, 14634ms total) +T4E58 4257:256 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 14634ms total) +T4E58 4257:256 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 14634ms total) +T4E58 4257:256 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 14634ms total) +T4E58 4257:256 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 14634ms total) +T4E58 4257:256 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0001ms, 14635ms total) +T4E58 4257:257 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 14635ms total) +T4E58 4257:257 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000004C (0000ms, 14635ms total) +T4E58 4257:257 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 14639ms total) +T4E58 4257:261 JLINK_IsHalted() returns FALSE (0001ms, 14640ms total) +T4E58 4257:293 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 14645ms total) +T4E58 4257:300 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 14639ms total) +T4E58 4257:300 JLINK_ClrBPEx(BPHandle = 0x0000004C) returns 0x00 (0001ms, 14640ms total) +T4E58 4257:301 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 14640ms total) +T4E58 4257:306 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: A2 F1 30 08 B8 F1 09 0F 07 D8 05 EB 85 05 0C EB ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 14648ms total) +T4E58 4257:312 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: BC F1 09 0F 05 D8 05 EB 85 05 03 EB 45 05 15 44 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0004ms, 14652ms total) +T4E58 4257:316 JLINK_WriteReg(R0, 0x08012000) returns 0x00 (0000ms, 14652ms total) +T4E58 4257:316 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 14652ms total) +T4E58 4257:316 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0001ms, 14653ms total) +T4E58 4257:317 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0001ms, 14654ms total) +T4E58 4257:318 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 14654ms total) +T4E58 4257:318 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 14654ms total) +T4E58 4257:318 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 14654ms total) +T4E58 4257:318 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 14654ms total) +T4E58 4257:318 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 14654ms total) +T4E58 4257:320 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 14656ms total) +T4E58 4257:320 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 14656ms total) +T4E58 4257:320 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 14656ms total) +T4E58 4257:320 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 14656ms total) +T4E58 4257:320 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 14656ms total) +T4E58 4257:320 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 14656ms total) +T4E58 4257:320 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 14656ms total) +T4E58 4257:320 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0001ms, 14657ms total) +T4E58 4257:321 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 14657ms total) +T4E58 4257:321 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 14657ms total) +T4E58 4257:321 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 14657ms total) +T4E58 4257:321 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000004D (0001ms, 14658ms total) +T4E58 4257:322 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 14662ms total) +T4E58 4257:326 JLINK_IsHalted() returns FALSE (0000ms, 14662ms total) +T4E58 4257:340 JLINK_IsHalted() returns FALSE (0001ms, 14663ms total) +T4E58 4257:356 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 14668ms total) +T4E58 4257:362 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 14662ms total) +T4E58 4257:362 JLINK_ClrBPEx(BPHandle = 0x0000004D) returns 0x00 (0000ms, 14662ms total) +T4E58 4257:362 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 14662ms total) +T4E58 4257:366 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 3E E0 99 F8 0D 20 4D 46 02 2A 0F D3 7C 48 90 F8 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 14668ms total) +T4E58 4257:372 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: F3 E7 28 A0 01 F0 A2 FA 2C A0 01 F0 9F FA 31 A0 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0004ms, 14672ms total) +T4E58 4257:376 JLINK_WriteReg(R0, 0x08012400) returns 0x00 (0000ms, 14672ms total) +T4E58 4257:376 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 14672ms total) +T4E58 4257:376 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 14672ms total) +T4E58 4257:376 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 14672ms total) +T4E58 4257:376 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 14672ms total) +T4E58 4257:376 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0001ms, 14673ms total) +T4E58 4257:377 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 14673ms total) +T4E58 4257:377 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0001ms, 14674ms total) +T4E58 4257:378 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 14674ms total) +T4E58 4257:378 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 14674ms total) +T4E58 4257:378 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 14674ms total) +T4E58 4257:378 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 14674ms total) +T4E58 4257:378 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0001ms, 14675ms total) +T4E58 4257:379 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 14675ms total) +T4E58 4257:379 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 14675ms total) +T4E58 4257:379 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 14675ms total) +T4E58 4257:379 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 14675ms total) +T4E58 4257:379 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 14675ms total) +T4E58 4257:379 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 14675ms total) +T4E58 4257:379 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 14675ms total) +T4E58 4257:379 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000004E (0000ms, 14675ms total) +T4E58 4257:379 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0007ms, 14682ms total) +T4E58 4257:386 JLINK_IsHalted() returns FALSE (0001ms, 14683ms total) +T4E58 4257:418 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0007ms, 14689ms total) +T4E58 4257:425 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 14682ms total) +T4E58 4257:425 JLINK_ClrBPEx(BPHandle = 0x0000004E) returns 0x00 (0000ms, 14682ms total) +T4E58 4257:425 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 14682ms total) +T4E58 4257:430 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 01 60 01 68 89 01 FC D5 41 68 21 F0 03 01 41 60 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 14688ms total) +T4E58 4257:436 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: D2 B2 02 70 01 2A 03 D9 0C 70 04 70 F7 F7 0C F8 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0004ms, 14692ms total) +T4E58 4257:441 JLINK_WriteReg(R0, 0x08012800) returns 0x00 (0000ms, 14692ms total) +T4E58 4257:441 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 14692ms total) +T4E58 4257:441 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 14692ms total) +T4E58 4257:441 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 14692ms total) +T4E58 4257:441 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 14692ms total) +T4E58 4257:443 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 14694ms total) +T4E58 4257:443 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 14694ms total) +T4E58 4257:443 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 14694ms total) +T4E58 4257:443 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 14694ms total) +T4E58 4257:443 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 14694ms total) +T4E58 4257:443 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 14694ms total) +T4E58 4257:443 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 14694ms total) +T4E58 4257:443 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 14694ms total) +T4E58 4257:443 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 14694ms total) +T4E58 4257:443 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0004ms, 14698ms total) +T4E58 4257:447 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 14698ms total) +T4E58 4257:447 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 14698ms total) +T4E58 4257:447 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 14698ms total) +T4E58 4257:447 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 14698ms total) +T4E58 4257:448 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 14699ms total) +T4E58 4257:448 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000004F (0000ms, 14699ms total) +T4E58 4257:448 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 14702ms total) +T4E58 4257:453 JLINK_IsHalted() returns FALSE (0000ms, 14704ms total) +T4E58 4257:465 JLINK_IsHalted() returns FALSE (0000ms, 14704ms total) +T4E58 4257:480 JLINK_IsHalted() returns FALSE (0001ms, 14705ms total) +T4E58 4257:495 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 14711ms total) +T4E58 4257:501 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 14705ms total) +T4E58 4257:501 JLINK_ClrBPEx(BPHandle = 0x0000004F) returns 0x00 (0000ms, 14705ms total) +T4E58 4257:501 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 14705ms total) +T4E58 4257:503 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 01 80 70 47 C9 43 01 82 70 47 00 29 01 88 02 D0 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 14711ms total) +T4E58 4257:509 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 4F F0 00 03 15 D4 AA 42 11 D9 19 4D 2D 78 01 2D ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0005ms, 14716ms total) +T4E58 4257:514 JLINK_WriteReg(R0, 0x08012C00) returns 0x00 (0000ms, 14716ms total) +T4E58 4257:514 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 14716ms total) +T4E58 4257:515 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 14717ms total) +T4E58 4257:515 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 14717ms total) +T4E58 4257:515 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 14717ms total) +T4E58 4257:515 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 14717ms total) +T4E58 4257:515 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 14717ms total) +T4E58 4257:515 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0001ms, 14718ms total) +T4E58 4257:516 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 14718ms total) +T4E58 4257:516 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 14718ms total) +T4E58 4257:516 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 14718ms total) +T4E58 4257:516 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 14718ms total) +T4E58 4257:516 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 14718ms total) +T4E58 4257:516 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 14718ms total) +T4E58 4257:516 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0001ms, 14719ms total) +T4E58 4257:517 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 14719ms total) +T4E58 4257:517 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 14719ms total) +T4E58 4257:517 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 14719ms total) +T4E58 4257:517 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 14719ms total) +T4E58 4257:517 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 14719ms total) +T4E58 4257:517 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000050 (0000ms, 14719ms total) +T4E58 4257:517 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0005ms, 14724ms total) +T4E58 4257:522 JLINK_IsHalted() returns FALSE (0001ms, 14725ms total) +T4E58 4257:541 JLINK_IsHalted() returns FALSE (0001ms, 14725ms total) +T4E58 4257:557 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0007ms, 14731ms total) +T4E58 4257:564 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 14724ms total) +T4E58 4257:564 JLINK_ClrBPEx(BPHandle = 0x00000050) returns 0x00 (0000ms, 14724ms total) +T4E58 4257:564 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 14724ms total) +T4E58 4257:566 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 00 70 B7 42 0F DB 90 F8 20 60 56 B9 06 7A 76 1C ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0007ms, 14731ms total) +T4E58 4257:573 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 64 1C E4 B2 81 F8 4F 40 03 2C 05 D9 42 F4 00 72 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0003ms, 14734ms total) +T4E58 4257:577 JLINK_WriteReg(R0, 0x08013000) returns 0x00 (0000ms, 14735ms total) +T4E58 4257:577 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 14735ms total) +T4E58 4257:577 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 14735ms total) +T4E58 4257:577 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 14735ms total) +T4E58 4257:577 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0001ms, 14736ms total) +T4E58 4257:578 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 14736ms total) +T4E58 4257:578 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 14736ms total) +T4E58 4257:578 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 14736ms total) +T4E58 4257:578 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 14736ms total) +T4E58 4257:578 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 14736ms total) +T4E58 4257:578 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 14736ms total) +T4E58 4257:579 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 14737ms total) +T4E58 4257:579 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 14737ms total) +T4E58 4257:579 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 14737ms total) +T4E58 4257:579 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 14737ms total) +T4E58 4257:579 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 14737ms total) +T4E58 4257:579 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 14737ms total) +T4E58 4257:579 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 14737ms total) +T4E58 4257:580 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 14738ms total) +T4E58 4257:580 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 14738ms total) +T4E58 4257:580 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000051 (0000ms, 14738ms total) +T4E58 4257:580 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 14742ms total) +T4E58 4257:584 JLINK_IsHalted() returns FALSE (0001ms, 14743ms total) +T4E58 4257:604 JLINK_IsHalted() returns FALSE (0002ms, 14744ms total) +T4E58 4257:620 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0009ms, 14753ms total) +T4E58 4257:629 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 14744ms total) +T4E58 4257:629 JLINK_ClrBPEx(BPHandle = 0x00000051) returns 0x00 (0000ms, 14744ms total) +T4E58 4257:629 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 14744ms total) +T4E58 4257:632 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 03 0F 05 D9 44 F4 80 54 A0 F8 56 40 81 F8 3E 20 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 14750ms total) +T4E58 4257:638 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: A1 F8 4E 50 B7 F5 FA 7F 29 DA B1 F8 4E 50 AE 04 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0004ms, 14754ms total) +T4E58 4257:644 JLINK_WriteReg(R0, 0x08013400) returns 0x00 (0000ms, 14754ms total) +T4E58 4257:644 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 14754ms total) +T4E58 4257:644 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0001ms, 14755ms total) +T4E58 4257:645 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 14755ms total) +T4E58 4257:645 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 14755ms total) +T4E58 4257:645 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 14755ms total) +T4E58 4257:645 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 14755ms total) +T4E58 4257:645 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 14755ms total) +T4E58 4257:645 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 14755ms total) +T4E58 4257:646 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 14756ms total) +T4E58 4257:646 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 14756ms total) +T4E58 4257:646 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 14756ms total) +T4E58 4257:646 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 14756ms total) +T4E58 4257:646 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 14756ms total) +T4E58 4257:646 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 14756ms total) +T4E58 4257:646 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 14756ms total) +T4E58 4257:647 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 14757ms total) +T4E58 4257:647 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 14757ms total) +T4E58 4257:647 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 14757ms total) +T4E58 4257:647 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 14757ms total) +T4E58 4257:647 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000052 (0000ms, 14757ms total) +T4E58 4257:647 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 14761ms total) +T4E58 4257:651 JLINK_IsHalted() returns FALSE (0001ms, 14762ms total) +T4E58 4257:683 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0008ms, 14769ms total) +T4E58 4257:691 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 14761ms total) +T4E58 4257:691 JLINK_ClrBPEx(BPHandle = 0x00000052) returns 0x00 (0001ms, 14762ms total) +T4E58 4257:692 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 14762ms total) +T4E58 4257:694 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: A0 F8 56 40 81 F8 36 20 B0 F8 56 40 25 07 0F D4 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 14768ms total) +T4E58 4257:700 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: A5 70 00 20 69 46 04 E0 0A 5C 23 18 40 1C DA 70 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0004ms, 14772ms total) +T4E58 4257:704 JLINK_WriteReg(R0, 0x08013800) returns 0x00 (0000ms, 14772ms total) +T4E58 4257:704 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 14772ms total) +T4E58 4257:704 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 14772ms total) +T4E58 4257:704 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 14772ms total) +T4E58 4257:704 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 14772ms total) +T4E58 4257:704 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0001ms, 14773ms total) +T4E58 4257:705 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 14773ms total) +T4E58 4257:705 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 14773ms total) +T4E58 4257:705 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 14773ms total) +T4E58 4257:705 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 14773ms total) +T4E58 4257:705 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 14773ms total) +T4E58 4257:705 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 14773ms total) +T4E58 4257:705 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0001ms, 14774ms total) +T4E58 4257:706 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 14774ms total) +T4E58 4257:706 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 14774ms total) +T4E58 4257:706 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 14774ms total) +T4E58 4257:706 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 14774ms total) +T4E58 4257:706 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 14774ms total) +T4E58 4257:706 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0001ms, 14775ms total) +T4E58 4257:707 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 14775ms total) +T4E58 4257:707 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000053 (0000ms, 14775ms total) +T4E58 4257:707 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 14779ms total) +T4E58 4257:711 JLINK_IsHalted() returns FALSE (0001ms, 14780ms total) +T4E58 4257:730 JLINK_IsHalted() returns FALSE (0001ms, 14780ms total) +T4E58 4257:761 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 14785ms total) +T4E58 4257:767 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 14779ms total) +T4E58 4257:767 JLINK_ClrBPEx(BPHandle = 0x00000053) returns 0x00 (0000ms, 14779ms total) +T4E58 4257:767 JLINK_ReadReg(R0) returns 0x00000000 (0001ms, 14780ms total) +T4E58 4257:771 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 05 E0 15 88 2D 06 FC D5 5D 5C 25 80 49 1C 81 42 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 14786ms total) +T4E58 4257:778 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 30 0A 34 28 02 D0 36 28 44 D0 53 E0 46 29 51 D1 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0004ms, 14790ms total) +T4E58 4257:782 JLINK_WriteReg(R0, 0x08013C00) returns 0x00 (0000ms, 14790ms total) +T4E58 4257:782 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 14790ms total) +T4E58 4257:782 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 14790ms total) +T4E58 4257:782 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 14790ms total) +T4E58 4257:782 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 14790ms total) +T4E58 4257:782 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 14790ms total) +T4E58 4257:782 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 14790ms total) +T4E58 4257:782 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 14790ms total) +T4E58 4257:782 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 14790ms total) +T4E58 4257:782 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 14790ms total) +T4E58 4257:782 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 14790ms total) +T4E58 4257:782 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 14790ms total) +T4E58 4257:782 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 14790ms total) +T4E58 4257:783 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 14791ms total) +T4E58 4257:783 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 14791ms total) +T4E58 4257:783 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 14791ms total) +T4E58 4257:783 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 14791ms total) +T4E58 4257:783 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 14791ms total) +T4E58 4257:783 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0001ms, 14792ms total) +T4E58 4257:784 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 14792ms total) +T4E58 4257:784 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000054 (0000ms, 14792ms total) +T4E58 4257:784 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 14795ms total) +T4E58 4257:788 JLINK_IsHalted() returns FALSE (0001ms, 14797ms total) +T4E58 4257:808 JLINK_IsHalted() returns FALSE (0002ms, 14798ms total) +T4E58 4257:824 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 14803ms total) +T4E58 4257:829 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 14798ms total) +T4E58 4257:829 JLINK_ClrBPEx(BPHandle = 0x00000054) returns 0x00 (0000ms, 14798ms total) +T4E58 4257:829 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 14798ms total) +T4E58 4257:833 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 67 74 A7 74 E7 74 27 75 67 75 A7 75 E7 75 27 76 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0007ms, 14805ms total) +T4E58 4257:840 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 21 00 E8 8B C0 F3 03 20 01 F0 28 F8 84 F8 22 00 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0004ms, 14809ms total) +T4E58 4257:844 JLINK_WriteReg(R0, 0x08014000) returns 0x00 (0000ms, 14809ms total) +T4E58 4257:844 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 14809ms total) +T4E58 4257:845 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 14809ms total) +T4E58 4257:845 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 14809ms total) +T4E58 4257:845 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0001ms, 14810ms total) +T4E58 4257:846 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 14810ms total) +T4E58 4257:846 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 14810ms total) +T4E58 4257:846 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 14810ms total) +T4E58 4257:846 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 14810ms total) +T4E58 4257:846 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 14810ms total) +T4E58 4257:846 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 14810ms total) +T4E58 4257:846 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 14810ms total) +T4E58 4257:846 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 14810ms total) +T4E58 4257:846 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0001ms, 14811ms total) +T4E58 4257:847 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 14811ms total) +T4E58 4257:847 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 14811ms total) +T4E58 4257:847 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 14811ms total) +T4E58 4257:847 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 14811ms total) +T4E58 4257:847 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 14811ms total) +T4E58 4257:847 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 14811ms total) +T4E58 4257:847 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000055 (0000ms, 14811ms total) +T4E58 4257:847 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0005ms, 14816ms total) +T4E58 4257:852 JLINK_IsHalted() returns FALSE (0001ms, 14817ms total) +T4E58 4257:869 JLINK_IsHalted() returns FALSE (0002ms, 14818ms total) +T4E58 4257:901 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 14822ms total) +T4E58 4257:907 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 14816ms total) +T4E58 4257:907 JLINK_ClrBPEx(BPHandle = 0x00000055) returns 0x00 (0000ms, 14816ms total) +T4E58 4257:907 JLINK_ReadReg(R0) returns 0x00000000 (0001ms, 14817ms total) +T4E58 4257:914 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: A8 7C 00 F0 0F 00 00 F0 77 FF 84 F8 3C 00 84 F8 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 14823ms total) +T4E58 4257:920 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 0F 00 00 F0 2B FE A0 74 4F EA 19 10 00 F0 26 FE ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0003ms, 14826ms total) +T4E58 4257:923 JLINK_WriteReg(R0, 0x08014400) returns 0x00 (0000ms, 14826ms total) +T4E58 4257:923 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 14826ms total) +T4E58 4257:923 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 14826ms total) +T4E58 4257:923 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0002ms, 14828ms total) +T4E58 4257:925 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 14828ms total) +T4E58 4257:925 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 14828ms total) +T4E58 4257:925 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 14828ms total) +T4E58 4257:925 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 14828ms total) +T4E58 4257:926 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 14829ms total) +T4E58 4257:926 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 14829ms total) +T4E58 4257:926 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 14829ms total) +T4E58 4257:926 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 14829ms total) +T4E58 4257:926 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 14829ms total) +T4E58 4257:926 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 14829ms total) +T4E58 4257:926 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0001ms, 14830ms total) +T4E58 4257:927 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 14830ms total) +T4E58 4257:928 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0001ms, 14832ms total) +T4E58 4257:929 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 14832ms total) +T4E58 4257:929 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 14832ms total) +T4E58 4257:929 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 14832ms total) +T4E58 4257:929 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000056 (0000ms, 14832ms total) +T4E58 4257:930 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 14836ms total) +T4E58 4257:933 JLINK_IsHalted() returns FALSE (0002ms, 14838ms total) +T4E58 4257:963 JLINK_IsHalted() returns FALSE (0001ms, 14837ms total) +T4E58 4257:979 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 14842ms total) +T4E58 4257:985 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 14836ms total) +T4E58 4257:985 JLINK_ClrBPEx(BPHandle = 0x00000056) returns 0x00 (0000ms, 14836ms total) +T4E58 4257:985 JLINK_ReadReg(R0) returns 0x00000000 (0001ms, 14837ms total) +T4E58 4257:988 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 09 78 40 1A 00 EB C0 01 01 EB 00 11 0A EA 01 17 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 14843ms total) +T4E58 4257:994 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 47 80 87 88 B5 F8 04 C0 47 EA 0C 07 87 80 C7 88 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0004ms, 14847ms total) +T4E58 4257:998 JLINK_WriteReg(R0, 0x08014800) returns 0x00 (0000ms, 14847ms total) +T4E58 4257:998 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 14847ms total) +T4E58 4257:998 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 14847ms total) +T4E58 4257:998 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 14847ms total) +T4E58 4257:998 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 14847ms total) +T4E58 4258:000 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 14849ms total) +T4E58 4258:000 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 14849ms total) +T4E58 4258:000 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 14849ms total) +T4E58 4258:000 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 14849ms total) +T4E58 4258:000 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 14849ms total) +T4E58 4258:000 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 14849ms total) +T4E58 4258:000 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 14849ms total) +T4E58 4258:000 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 14849ms total) +T4E58 4258:000 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 14849ms total) +T4E58 4258:001 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 14850ms total) +T4E58 4258:001 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 14850ms total) +T4E58 4258:001 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 14850ms total) +T4E58 4258:001 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 14850ms total) +T4E58 4258:001 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 14850ms total) +T4E58 4258:001 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 14850ms total) +T4E58 4258:001 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000057 (0000ms, 14850ms total) +T4E58 4258:001 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 14854ms total) +T4E58 4258:005 JLINK_IsHalted() returns FALSE (0001ms, 14855ms total) +T4E58 4258:027 JLINK_IsHalted() returns FALSE (0001ms, 14855ms total) +T4E58 4258:058 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 14860ms total) +T4E58 4258:064 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 14854ms total) +T4E58 4258:064 JLINK_ClrBPEx(BPHandle = 0x00000057) returns 0x00 (0000ms, 14854ms total) +T4E58 4258:064 JLINK_ReadReg(R0) returns 0x00000000 (0001ms, 14855ms total) +T4E58 4258:067 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 40 F6 7F 78 1C EA 08 0F 46 D1 B5 F9 2C C0 B0 F9 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 14861ms total) +T4E58 4258:073 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: F8 BD 00 00 3F 19 01 00 38 B5 00 22 13 46 4F F0 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0004ms, 14865ms total) +T4E58 4258:077 JLINK_WriteReg(R0, 0x08014C00) returns 0x00 (0000ms, 14865ms total) +T4E58 4258:077 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 14865ms total) +T4E58 4258:077 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 14865ms total) +T4E58 4258:077 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 14865ms total) +T4E58 4258:077 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 14865ms total) +T4E58 4258:078 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 14866ms total) +T4E58 4258:078 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 14866ms total) +T4E58 4258:078 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 14866ms total) +T4E58 4258:078 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 14866ms total) +T4E58 4258:078 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 14866ms total) +T4E58 4258:078 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 14866ms total) +T4E58 4258:078 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 14866ms total) +T4E58 4258:078 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 14866ms total) +T4E58 4258:078 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 14866ms total) +T4E58 4258:080 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 14868ms total) +T4E58 4258:080 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 14868ms total) +T4E58 4258:080 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 14868ms total) +T4E58 4258:080 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 14868ms total) +T4E58 4258:080 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 14868ms total) +T4E58 4258:080 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 14868ms total) +T4E58 4258:080 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000058 (0000ms, 14868ms total) +T4E58 4258:080 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 14872ms total) +T4E58 4258:084 JLINK_IsHalted() returns FALSE (0002ms, 14874ms total) +T4E58 4258:105 JLINK_IsHalted() returns FALSE (0001ms, 14873ms total) +T4E58 4258:120 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0007ms, 14879ms total) +T4E58 4258:127 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 14872ms total) +T4E58 4258:127 JLINK_ClrBPEx(BPHandle = 0x00000058) returns 0x00 (0000ms, 14872ms total) +T4E58 4258:127 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 14872ms total) +T4E58 4258:129 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 23 FC F0 F7 43 FA 32 21 E0 68 FD F7 DB FD 00 28 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 14878ms total) +T4E58 4258:135 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 0C 0F 14 D1 92 F8 02 C0 1C F0 FF 0F 0F D1 92 F8 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0006ms, 14884ms total) +T4E58 4258:141 JLINK_WriteReg(R0, 0x08015000) returns 0x00 (0000ms, 14884ms total) +T4E58 4258:141 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 14884ms total) +T4E58 4258:141 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 14884ms total) +T4E58 4258:141 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 14884ms total) +T4E58 4258:142 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 14885ms total) +T4E58 4258:142 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 14885ms total) +T4E58 4258:142 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 14885ms total) +T4E58 4258:142 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 14885ms total) +T4E58 4258:142 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 14885ms total) +T4E58 4258:142 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 14885ms total) +T4E58 4258:142 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0001ms, 14886ms total) +T4E58 4258:143 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 14886ms total) +T4E58 4258:143 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 14886ms total) +T4E58 4258:143 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 14886ms total) +T4E58 4258:143 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 14886ms total) +T4E58 4258:143 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 14886ms total) +T4E58 4258:143 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 14886ms total) +T4E58 4258:143 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 14886ms total) +T4E58 4258:143 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0001ms, 14887ms total) +T4E58 4258:144 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 14887ms total) +T4E58 4258:144 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000059 (0000ms, 14887ms total) +T4E58 4258:144 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 14891ms total) +T4E58 4258:148 JLINK_IsHalted() returns FALSE (0004ms, 14895ms total) +T4E58 4258:183 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 14897ms total) +T4E58 4258:189 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 14891ms total) +T4E58 4258:189 JLINK_ClrBPEx(BPHandle = 0x00000059) returns 0x00 (0000ms, 14891ms total) +T4E58 4258:189 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 14891ms total) +T4E58 4258:192 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 01 25 8D F8 21 50 00 24 8D F8 22 40 8D F8 23 50 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0005ms, 14896ms total) +T4E58 4258:197 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 12 21 00 20 F1 F7 F4 FE 05 20 FF F7 D7 FB CB E7 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0005ms, 14901ms total) +T4E58 4258:203 JLINK_WriteReg(R0, 0x08015400) returns 0x00 (0000ms, 14901ms total) +T4E58 4258:203 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 14901ms total) +T4E58 4258:203 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 14901ms total) +T4E58 4258:203 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 14901ms total) +T4E58 4258:203 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 14901ms total) +T4E58 4258:203 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 14901ms total) +T4E58 4258:203 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0001ms, 14902ms total) +T4E58 4258:204 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 14902ms total) +T4E58 4258:204 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 14902ms total) +T4E58 4258:204 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 14902ms total) +T4E58 4258:204 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 14902ms total) +T4E58 4258:204 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 14902ms total) +T4E58 4258:204 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 14902ms total) +T4E58 4258:205 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 14903ms total) +T4E58 4258:205 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 14903ms total) +T4E58 4258:205 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 14903ms total) +T4E58 4258:205 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 14903ms total) +T4E58 4258:205 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 14903ms total) +T4E58 4258:205 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 14903ms total) +T4E58 4258:205 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 14903ms total) +T4E58 4258:206 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000005A (0000ms, 14903ms total) +T4E58 4258:206 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 14907ms total) +T4E58 4258:210 JLINK_IsHalted() returns FALSE (0001ms, 14908ms total) +T4E58 4258:230 JLINK_IsHalted() returns FALSE (0001ms, 14908ms total) +T4E58 4258:262 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 14914ms total) +T4E58 4258:268 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0001ms, 14909ms total) +T4E58 4258:269 JLINK_ClrBPEx(BPHandle = 0x0000005A) returns 0x00 (0000ms, 14909ms total) +T4E58 4258:269 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 14909ms total) +T4E58 4258:273 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 8D F8 02 40 69 46 48 46 F1 F7 EA FF AD F8 00 60 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 14915ms total) +T4E58 4258:279 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 41 BA BD F8 06 00 A1 F5 80 54 43 BA 14 48 B4 F5 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0005ms, 14920ms total) +T4E58 4258:284 JLINK_WriteReg(R0, 0x08015800) returns 0x00 (0000ms, 14920ms total) +T4E58 4258:284 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 14920ms total) +T4E58 4258:284 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 14920ms total) +T4E58 4258:284 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 14920ms total) +T4E58 4258:284 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 14920ms total) +T4E58 4258:285 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 14920ms total) +T4E58 4258:285 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 14920ms total) +T4E58 4258:285 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 14920ms total) +T4E58 4258:285 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 14920ms total) +T4E58 4258:285 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 14920ms total) +T4E58 4258:285 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 14920ms total) +T4E58 4258:285 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 14920ms total) +T4E58 4258:285 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0001ms, 14921ms total) +T4E58 4258:286 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 14921ms total) +T4E58 4258:286 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 14921ms total) +T4E58 4258:286 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 14921ms total) +T4E58 4258:286 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 14921ms total) +T4E58 4258:286 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 14921ms total) +T4E58 4258:286 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0001ms, 14922ms total) +T4E58 4258:287 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 14922ms total) +T4E58 4258:287 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000005B (0000ms, 14922ms total) +T4E58 4258:287 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 14926ms total) +T4E58 4258:291 JLINK_IsHalted() returns FALSE (0002ms, 14928ms total) +T4E58 4258:309 JLINK_IsHalted() returns FALSE (0002ms, 14928ms total) +T4E58 4258:326 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0007ms, 14933ms total) +T4E58 4258:333 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 14933ms total) +T4E58 4258:333 JLINK_ClrBPEx(BPHandle = 0x0000005B) returns 0x00 (0000ms, 14933ms total) +T4E58 4258:333 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 14933ms total) +T4E58 4258:334 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: F7 F7 8E F8 F7 F7 9C F8 21 78 60 78 CD E9 00 01 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0005ms, 14938ms total) +T4E58 4258:339 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 19 FF 42 F2 0F 70 AD F8 04 00 47 20 AD F8 00 00 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0006ms, 14944ms total) +T4E58 4258:345 JLINK_WriteReg(R0, 0x08015C00) returns 0x00 (0000ms, 14944ms total) +T4E58 4258:345 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 14944ms total) +T4E58 4258:345 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 14944ms total) +T4E58 4258:345 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 14944ms total) +T4E58 4258:345 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 14944ms total) +T4E58 4258:345 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 14944ms total) +T4E58 4258:345 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 14944ms total) +T4E58 4258:345 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 14944ms total) +T4E58 4258:345 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 14944ms total) +T4E58 4258:345 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 14944ms total) +T4E58 4258:345 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0001ms, 14945ms total) +T4E58 4258:346 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 14945ms total) +T4E58 4258:346 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 14945ms total) +T4E58 4258:346 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 14945ms total) +T4E58 4258:346 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 14945ms total) +T4E58 4258:346 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 14945ms total) +T4E58 4258:346 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 14945ms total) +T4E58 4258:346 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0001ms, 14946ms total) +T4E58 4258:347 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 14946ms total) +T4E58 4258:347 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 14946ms total) +T4E58 4258:347 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000005C (0000ms, 14946ms total) +T4E58 4258:347 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 14950ms total) +T4E58 4258:351 JLINK_IsHalted() returns FALSE (0002ms, 14952ms total) +T4E58 4258:388 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0007ms, 14957ms total) +T4E58 4258:395 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 14957ms total) +T4E58 4258:395 JLINK_ClrBPEx(BPHandle = 0x0000005C) returns 0x00 (0000ms, 14957ms total) +T4E58 4258:396 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 14958ms total) +T4E58 4258:398 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 30 46 F1 F7 ED FB 04 20 AD F8 10 00 8D F8 12 40 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 14964ms total) +T4E58 4258:404 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 20 F0 01 00 41 F1 00 01 4F EA 41 03 13 F5 00 1F ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0004ms, 14968ms total) +T4E58 4258:408 JLINK_WriteReg(R0, 0x08016000) returns 0x00 (0000ms, 14968ms total) +T4E58 4258:409 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 14969ms total) +T4E58 4258:409 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 14969ms total) +T4E58 4258:409 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 14969ms total) +T4E58 4258:409 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 14969ms total) +T4E58 4258:409 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 14969ms total) +T4E58 4258:410 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 14970ms total) +T4E58 4258:410 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 14970ms total) +T4E58 4258:410 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 14970ms total) +T4E58 4258:410 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 14970ms total) +T4E58 4258:410 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0001ms, 14971ms total) +T4E58 4258:411 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 14971ms total) +T4E58 4258:411 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 14971ms total) +T4E58 4258:411 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 14971ms total) +T4E58 4258:411 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 14971ms total) +T4E58 4258:411 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 14971ms total) +T4E58 4258:411 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 14971ms total) +T4E58 4258:411 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 14971ms total) +T4E58 4258:411 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 14971ms total) +T4E58 4258:411 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0001ms, 14972ms total) +T4E58 4258:412 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000005D (0000ms, 14972ms total) +T4E58 4258:412 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 14975ms total) +T4E58 4258:416 JLINK_IsHalted() returns FALSE (0001ms, 14976ms total) +T4E58 4258:434 JLINK_IsHalted() returns FALSE (0001ms, 14976ms total) +T4E58 4258:450 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 14981ms total) +T4E58 4258:456 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0001ms, 14976ms total) +T4E58 4258:457 JLINK_ClrBPEx(BPHandle = 0x0000005D) returns 0x00 (0000ms, 14976ms total) +T4E58 4258:457 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 14976ms total) +T4E58 4258:460 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: AE F1 01 0E A6 FB 0C 58 4F F0 00 07 4F F0 00 05 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 14982ms total) +T4E58 4258:466 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: FF 3F 05 D0 4F F0 FF 30 70 47 4F F0 00 00 70 47 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0006ms, 14988ms total) +T4E58 4258:472 JLINK_WriteReg(R0, 0x08016400) returns 0x00 (0000ms, 14988ms total) +T4E58 4258:472 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 14988ms total) +T4E58 4258:472 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 14988ms total) +T4E58 4258:472 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 14988ms total) +T4E58 4258:472 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 14988ms total) +T4E58 4258:472 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 14988ms total) +T4E58 4258:472 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 14988ms total) +T4E58 4258:472 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 14988ms total) +T4E58 4258:472 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0001ms, 14989ms total) +T4E58 4258:473 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 14989ms total) +T4E58 4258:473 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 14989ms total) +T4E58 4258:473 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 14989ms total) +T4E58 4258:473 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 14989ms total) +T4E58 4258:473 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 14989ms total) +T4E58 4258:473 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 14989ms total) +T4E58 4258:473 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0001ms, 14990ms total) +T4E58 4258:474 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 14990ms total) +T4E58 4258:474 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 14990ms total) +T4E58 4258:474 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 14990ms total) +T4E58 4258:474 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 14990ms total) +T4E58 4258:474 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000005E (0001ms, 14991ms total) +T4E58 4258:475 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 14994ms total) +T4E58 4258:478 JLINK_IsHalted() returns FALSE (0001ms, 14995ms total) +T4E58 4258:497 JLINK_IsHalted() returns FALSE (0005ms, 14999ms total) +T4E58 4258:529 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0008ms, 15002ms total) +T4E58 4258:537 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 14994ms total) +T4E58 4258:537 JLINK_ClrBPEx(BPHandle = 0x0000005E) returns 0x00 (0000ms, 14994ms total) +T4E58 4258:537 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 14994ms total) +T4E58 4258:539 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 89 00 01 3E 00 F0 07 B8 00 F0 09 B8 4F EA 43 0C ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 15000ms total) +T4E58 4258:545 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 70 B5 FF F7 CB FE 00 BF 40 DF F6 3E 83 F0 00 41 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0006ms, 15006ms total) +T4E58 4258:552 JLINK_WriteReg(R0, 0x08016800) returns 0x00 (0000ms, 15007ms total) +T4E58 4258:552 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 15007ms total) +T4E58 4258:552 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0001ms, 15008ms total) +T4E58 4258:553 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 15008ms total) +T4E58 4258:554 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 15009ms total) +T4E58 4258:554 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 15009ms total) +T4E58 4258:554 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 15009ms total) +T4E58 4258:554 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 15009ms total) +T4E58 4258:554 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 15009ms total) +T4E58 4258:554 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 15009ms total) +T4E58 4258:555 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 15010ms total) +T4E58 4258:555 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 15010ms total) +T4E58 4258:555 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 15010ms total) +T4E58 4258:555 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 15010ms total) +T4E58 4258:555 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 15010ms total) +T4E58 4258:555 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 15010ms total) +T4E58 4258:555 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0001ms, 15011ms total) +T4E58 4258:556 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 15011ms total) +T4E58 4258:556 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 15011ms total) +T4E58 4258:556 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 15011ms total) +T4E58 4258:556 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x0000005F (0000ms, 15011ms total) +T4E58 4258:556 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0006ms, 15017ms total) +T4E58 4258:562 JLINK_IsHalted() returns FALSE (0001ms, 15018ms total) +T4E58 4258:591 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0007ms, 15024ms total) +T4E58 4258:598 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 15017ms total) +T4E58 4258:598 JLINK_ClrBPEx(BPHandle = 0x0000005F) returns 0x00 (0002ms, 15019ms total) +T4E58 4258:600 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 15019ms total) +T4E58 4258:602 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 20 F0 7F 40 00 B5 81 42 A2 EB 03 02 0F F2 08 1C ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 15025ms total) +T4E58 4258:609 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 48 BF 42 F4 80 72 62 45 38 BF 63 45 04 D2 80 EA ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0003ms, 15029ms total) +T4E58 4258:612 JLINK_WriteReg(R0, 0x08016C00) returns 0x00 (0000ms, 15029ms total) +T4E58 4258:612 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0001ms, 15030ms total) +T4E58 4258:613 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 15030ms total) +T4E58 4258:613 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 15030ms total) +T4E58 4258:613 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 15030ms total) +T4E58 4258:613 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 15030ms total) +T4E58 4258:613 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 15030ms total) +T4E58 4258:613 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0001ms, 15031ms total) +T4E58 4258:614 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 15031ms total) +T4E58 4258:614 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 15031ms total) +T4E58 4258:614 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 15031ms total) +T4E58 4258:614 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 15031ms total) +T4E58 4258:614 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 15031ms total) +T4E58 4258:614 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 15031ms total) +T4E58 4258:614 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0001ms, 15032ms total) +T4E58 4258:615 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 15032ms total) +T4E58 4258:615 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 15032ms total) +T4E58 4258:615 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 15032ms total) +T4E58 4258:615 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 15032ms total) +T4E58 4258:615 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 15032ms total) +T4E58 4258:615 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000060 (0000ms, 15032ms total) +T4E58 4258:615 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0005ms, 15037ms total) +T4E58 4258:620 JLINK_IsHalted() returns FALSE (0001ms, 15038ms total) +T4E58 4258:638 JLINK_IsHalted() returns FALSE (0001ms, 15038ms total) +T4E58 4258:653 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0007ms, 15044ms total) +T4E58 4258:660 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0003ms, 15040ms total) +T4E58 4258:663 JLINK_ClrBPEx(BPHandle = 0x00000060) returns 0x00 (0000ms, 15040ms total) +T4E58 4258:663 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 15040ms total) +T4E58 4258:666 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 7F 0F 18 BF 70 47 C3 F1 20 03 99 40 14 BF 40 1E ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 15046ms total) +T4E58 4258:672 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 40 62 00 66 C1 A6 81 A7 40 67 01 A5 C0 65 80 64 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0006ms, 15052ms total) +T4E58 4258:678 JLINK_WriteReg(R0, 0x08017000) returns 0x00 (0000ms, 15052ms total) +T4E58 4258:678 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 15052ms total) +T4E58 4258:679 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 15053ms total) +T4E58 4258:679 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 15053ms total) +T4E58 4258:679 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 15053ms total) +T4E58 4258:679 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 15053ms total) +T4E58 4258:679 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 15053ms total) +T4E58 4258:679 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 15053ms total) +T4E58 4258:679 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0001ms, 15054ms total) +T4E58 4258:680 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 15054ms total) +T4E58 4258:680 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 15054ms total) +T4E58 4258:680 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 15054ms total) +T4E58 4258:680 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 15054ms total) +T4E58 4258:680 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 15054ms total) +T4E58 4258:681 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 15055ms total) +T4E58 4258:681 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 15055ms total) +T4E58 4258:681 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 15055ms total) +T4E58 4258:681 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 15055ms total) +T4E58 4258:681 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 15055ms total) +T4E58 4258:682 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 15056ms total) +T4E58 4258:682 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000061 (0000ms, 15056ms total) +T4E58 4258:682 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 15060ms total) +T4E58 4258:686 JLINK_IsHalted() returns FALSE (0001ms, 15061ms total) +T4E58 4258:714 JLINK_IsHalted() returns FALSE (0002ms, 15062ms total) +T4E58 4258:730 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0007ms, 15067ms total) +T4E58 4258:737 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 15060ms total) +T4E58 4258:737 JLINK_ClrBPEx(BPHandle = 0x00000061) returns 0x00 (0000ms, 15060ms total) +T4E58 4258:737 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 15060ms total) +T4E58 4258:739 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 5E 0B D3 0A 4F 0A D3 09 5C 09 EC 08 81 08 1C 08 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 15066ms total) +T4E58 4258:745 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: 63 64 65 66 78 70 00 30 31 32 33 34 35 36 37 38 ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0004ms, 15070ms total) +T4E58 4258:749 JLINK_WriteReg(R0, 0x08017400) returns 0x00 (0000ms, 15070ms total) +T4E58 4258:749 JLINK_WriteReg(R1, 0x00000400) returns 0x00 (0000ms, 15070ms total) +T4E58 4258:749 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 15070ms total) +T4E58 4258:749 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0001ms, 15071ms total) +T4E58 4258:750 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 15071ms total) +T4E58 4258:750 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 15071ms total) +T4E58 4258:750 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 15071ms total) +T4E58 4258:750 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 15071ms total) +T4E58 4258:750 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 15071ms total) +T4E58 4258:750 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 15071ms total) +T4E58 4258:750 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0001ms, 15072ms total) +T4E58 4258:751 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 15072ms total) +T4E58 4258:751 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 15072ms total) +T4E58 4258:751 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 15072ms total) +T4E58 4258:751 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 15072ms total) +T4E58 4258:751 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 15072ms total) +T4E58 4258:751 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 15072ms total) +T4E58 4258:751 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0001ms, 15073ms total) +T4E58 4258:752 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 15073ms total) +T4E58 4258:752 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 15073ms total) +T4E58 4258:752 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000062 (0000ms, 15073ms total) +T4E58 4258:752 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0006ms, 15079ms total) +T4E58 4258:759 JLINK_IsHalted() returns FALSE (0001ms, 15081ms total) +T4E58 4258:777 JLINK_IsHalted() returns FALSE (0001ms, 15081ms total) +T4E58 4258:793 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0007ms, 15087ms total) +T4E58 4258:800 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 15080ms total) +T4E58 4258:800 JLINK_ClrBPEx(BPHandle = 0x00000062) returns 0x00 (0000ms, 15080ms total) +T4E58 4258:800 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 15080ms total) +T4E58 4258:803 JLINK_WriteMem(0x20000164, 0x029C Bytes, ...) - Data: 02 02 02 02 02 02 88 88 88 88 88 88 08 08 08 08 ... -- CPU_WriteMem(668 bytes @ 0x20000164) returns 0x29C (0006ms, 15086ms total) +T4E58 4258:809 JLINK_WriteMem(0x20000400, 0x0164 Bytes, ...) - Data: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ... -- CPU_WriteMem(356 bytes @ 0x20000400) returns 0x164 (0005ms, 15091ms total) +T4E58 4258:814 JLINK_WriteReg(R0, 0x08017800) returns 0x00 (0000ms, 15091ms total) +T4E58 4258:814 JLINK_WriteReg(R1, 0x00000284) returns 0x00 (0000ms, 15091ms total) +T4E58 4258:814 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 15091ms total) +T4E58 4258:814 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 15091ms total) +T4E58 4258:814 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 15091ms total) +T4E58 4258:815 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 15092ms total) +T4E58 4258:815 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 15092ms total) +T4E58 4258:815 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 15092ms total) +T4E58 4258:815 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 15092ms total) +T4E58 4258:815 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 15092ms total) +T4E58 4258:815 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 15092ms total) +T4E58 4258:815 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 15092ms total) +T4E58 4258:816 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 15092ms total) +T4E58 4258:816 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 15092ms total) +T4E58 4258:816 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 15092ms total) +T4E58 4258:816 JLINK_WriteReg(R15 (PC), 0x200000F4) returns 0x00 (0000ms, 15092ms total) +T4E58 4258:816 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 15092ms total) +T4E58 4258:816 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 15092ms total) +T4E58 4258:816 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 15092ms total) +T4E58 4258:816 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0001ms, 15093ms total) +T4E58 4258:817 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000063 (0000ms, 15093ms total) +T4E58 4258:817 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0005ms, 15098ms total) +T4E58 4258:824 JLINK_IsHalted() returns FALSE (0001ms, 15101ms total) +T4E58 4258:838 JLINK_IsHalted() returns FALSE (0001ms, 15101ms total) +T4E58 4258:854 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 15105ms total) +T4E58 4258:859 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0001ms, 15101ms total) +T4E58 4258:860 JLINK_ClrBPEx(BPHandle = 0x00000063) returns 0x00 (0000ms, 15101ms total) +T4E58 4258:860 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 15101ms total) +T4E58 4258:860 JLINK_WriteReg(R0, 0x00000002) returns 0x00 (0000ms, 15101ms total) +T4E58 4258:860 JLINK_WriteReg(R1, 0x00000284) returns 0x00 (0000ms, 15101ms total) +T4E58 4258:860 JLINK_WriteReg(R2, 0x20000164) returns 0x00 (0000ms, 15101ms total) +T4E58 4258:860 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 15101ms total) +T4E58 4258:860 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 15101ms total) +T4E58 4258:861 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 15102ms total) +T4E58 4258:861 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 15102ms total) +T4E58 4258:861 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 15102ms total) +T4E58 4258:861 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 15102ms total) +T4E58 4258:861 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 15102ms total) +T4E58 4258:861 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 15102ms total) +T4E58 4258:861 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 15102ms total) +T4E58 4258:861 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 15102ms total) +T4E58 4258:861 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0001ms, 15103ms total) +T4E58 4258:862 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 15103ms total) +T4E58 4258:862 JLINK_WriteReg(R15 (PC), 0x2000006A) returns 0x00 (0000ms, 15103ms total) +T4E58 4258:862 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 15103ms total) +T4E58 4258:862 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 15103ms total) +T4E58 4258:862 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 15103ms total) +T4E58 4258:862 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 15103ms total) +T4E58 4258:862 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000064 (0001ms, 15104ms total) +T4E58 4258:863 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 15108ms total) +T4E58 4258:867 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0011ms, 15119ms total) +T4E58 4258:878 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 15108ms total) +T4E58 4258:878 JLINK_ClrBPEx(BPHandle = 0x00000064) returns 0x00 (0000ms, 15108ms total) +T4E58 4258:879 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 15109ms total) +T4E58 4258:995 JLINK_WriteMem(0x20000000, 0x0164 Bytes, ...) - Data: 00 BE 0A E0 0D 78 2D 06 68 40 08 24 40 00 00 D3 ... -- CPU_WriteMem(356 bytes @ 0x20000000) returns 0x164 (0003ms, 15112ms total) +T4E58 4258:998 JLINK_WriteReg(R0, 0x08000000) returns 0x00 (0000ms, 15112ms total) +T4E58 4258:998 JLINK_WriteReg(R1, 0x00B71B00) returns 0x00 (0002ms, 15114ms total) +T4E58 4259:000 JLINK_WriteReg(R2, 0x00000003) returns 0x00 (0000ms, 15114ms total) +T4E58 4259:000 JLINK_WriteReg(R3, 0x00000000) returns 0x00 (0000ms, 15114ms total) +T4E58 4259:000 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 15114ms total) +T4E58 4259:000 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 15114ms total) +T4E58 4259:000 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 15114ms total) +T4E58 4259:000 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 15114ms total) +T4E58 4259:000 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 15114ms total) +T4E58 4259:001 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 15114ms total) +T4E58 4259:001 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 15114ms total) +T4E58 4259:001 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 15114ms total) +T4E58 4259:001 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 15114ms total) +T4E58 4259:001 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 15114ms total) +T4E58 4259:001 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 15114ms total) +T4E58 4259:001 JLINK_WriteReg(R15 (PC), 0x20000038) returns 0x00 (0000ms, 15114ms total) +T4E58 4259:001 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0001ms, 15115ms total) +T4E58 4259:002 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 15115ms total) +T4E58 4259:002 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 15115ms total) +T4E58 4259:002 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 15115ms total) +T4E58 4259:002 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) -- CPU_ReadMem(2 bytes @ 0x20000000) returns 0x00000065 (0001ms, 15116ms total) +T4E58 4259:003 JLINK_Go() -- CPU_WriteMem(2 bytes @ 0x20000000) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0006ms, 15122ms total) +T4E58 4259:009 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 15127ms total) +T4E58 4259:014 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 15122ms total) +T4E58 4259:014 JLINK_ClrBPEx(BPHandle = 0x00000065) returns 0x00 (0000ms, 15122ms total) +T4E58 4259:014 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 15122ms total) +T4E58 4259:014 JLINK_WriteReg(R0, 0xFFFFFFFF) returns 0x00 (0000ms, 15122ms total) +T4E58 4259:014 JLINK_WriteReg(R1, 0x08000000) returns 0x00 (0001ms, 15123ms total) +T4E58 4259:015 JLINK_WriteReg(R2, 0x00010000) returns 0x00 (0000ms, 15123ms total) +T4E58 4259:015 JLINK_WriteReg(R3, 0x04C11DB7) returns 0x00 (0000ms, 15123ms total) +T4E58 4259:015 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0001ms, 15124ms total) +T4E58 4259:016 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 15124ms total) +T4E58 4259:016 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 15124ms total) +T4E58 4259:016 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 15124ms total) +T4E58 4259:016 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 15124ms total) +T4E58 4259:016 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 15124ms total) +T4E58 4259:016 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 15124ms total) +T4E58 4259:016 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0001ms, 15125ms total) +T4E58 4259:017 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 15125ms total) +T4E58 4259:017 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 15125ms total) +T4E58 4259:017 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 15125ms total) +T4E58 4259:017 JLINK_WriteReg(R15 (PC), 0x20000002) returns 0x00 (0000ms, 15125ms total) +T4E58 4259:017 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 15125ms total) +T4E58 4259:017 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 15125ms total) +T4E58 4259:017 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0001ms, 15126ms total) +T4E58 4259:018 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 15126ms total) +T4E58 4259:018 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000066 (0000ms, 15126ms total) +T4E58 4259:018 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0004ms, 15130ms total) +T4E58 4259:022 JLINK_IsHalted() returns FALSE (0001ms, 15131ms total) +T4E58 4259:057 JLINK_IsHalted() returns FALSE (0001ms, 15131ms total) +T4E58 4259:104 JLINK_IsHalted() returns FALSE (0001ms, 15131ms total) +T4E58 4259:135 JLINK_IsHalted() returns FALSE (0001ms, 15132ms total) +T4E58 4259:183 JLINK_IsHalted() returns FALSE (0001ms, 15133ms total) +T4E58 4259:244 JLINK_IsHalted() returns FALSE (0001ms, 15133ms total) +T4E58 4259:275 JLINK_IsHalted() returns FALSE (0001ms, 15133ms total) +T4E58 4259:291 JLINK_IsHalted() returns FALSE (0001ms, 15133ms total) +T4E58 4259:307 JLINK_IsHalted() returns FALSE (0001ms, 15133ms total) +T4E58 4259:323 JLINK_IsHalted() returns FALSE (0001ms, 15133ms total) +T4E58 4259:354 JLINK_IsHalted() returns FALSE (0001ms, 15134ms total) +T4E58 4259:370 JLINK_IsHalted() returns FALSE (0001ms, 15134ms total) +T4E58 4259:386 JLINK_IsHalted() returns FALSE (0001ms, 15134ms total) +T4E58 4259:402 JLINK_IsHalted() returns FALSE (0001ms, 15134ms total) +T4E58 4259:418 JLINK_IsHalted() returns FALSE (0001ms, 15134ms total) +T4E58 4259:433 JLINK_IsHalted() returns FALSE (0001ms, 15134ms total) +T4E58 4259:464 JLINK_IsHalted() returns FALSE (0000ms, 15133ms total) +T4E58 4259:479 JLINK_IsHalted() returns FALSE (0001ms, 15134ms total) +T4E58 4259:495 JLINK_IsHalted() returns FALSE (0002ms, 15135ms total) +T4E58 4259:511 JLINK_IsHalted() returns FALSE (0001ms, 15134ms total) +T4E58 4259:543 JLINK_IsHalted() returns FALSE (0002ms, 15135ms total) +T4E58 4259:574 JLINK_IsHalted() returns FALSE (0001ms, 15136ms total) +T4E58 4259:605 JLINK_IsHalted() returns FALSE (0001ms, 15136ms total) +T4E58 4259:636 JLINK_IsHalted() returns FALSE (0001ms, 15136ms total) +T4E58 4259:698 JLINK_IsHalted() returns FALSE (0001ms, 15136ms total) +T4E58 4259:730 JLINK_IsHalted() returns FALSE (0001ms, 15136ms total) +T4E58 4259:793 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 15140ms total) +T4E58 4259:798 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0001ms, 15136ms total) +T4E58 4259:799 JLINK_ClrBPEx(BPHandle = 0x00000066) returns 0x00 (0000ms, 15136ms total) +T4E58 4259:799 JLINK_ReadReg(R0) returns 0x3B7CAD0D (0000ms, 15136ms total) +T4E58 4259:809 JLINK_WriteReg(R0, 0xFFFFFFFF) returns 0x00 (0000ms, 15136ms total) +T4E58 4259:809 JLINK_WriteReg(R1, 0x08010000) returns 0x00 (0001ms, 15137ms total) +T4E58 4259:810 JLINK_WriteReg(R2, 0x00007A84) returns 0x00 (0000ms, 15137ms total) +T4E58 4259:810 JLINK_WriteReg(R3, 0x04C11DB7) returns 0x00 (0000ms, 15137ms total) +T4E58 4259:810 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 15137ms total) +T4E58 4259:810 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 15137ms total) +T4E58 4259:810 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 15137ms total) +T4E58 4259:810 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0001ms, 15138ms total) +T4E58 4259:811 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 15138ms total) +T4E58 4259:811 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 15138ms total) +T4E58 4259:811 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 15138ms total) +T4E58 4259:811 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 15138ms total) +T4E58 4259:811 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0001ms, 15139ms total) +T4E58 4259:812 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 15139ms total) +T4E58 4259:812 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 15139ms total) +T4E58 4259:812 JLINK_WriteReg(R15 (PC), 0x20000002) returns 0x00 (0000ms, 15139ms total) +T4E58 4259:812 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 15139ms total) +T4E58 4259:812 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 15139ms total) +T4E58 4259:812 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 15139ms total) +T4E58 4259:812 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 15139ms total) +T4E58 4259:812 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000067 (0001ms, 15140ms total) +T4E58 4259:813 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0003ms, 15143ms total) +T4E58 4259:816 JLINK_IsHalted() returns FALSE (0001ms, 15144ms total) +T4E58 4259:840 JLINK_IsHalted() returns FALSE (0001ms, 15144ms total) +T4E58 4259:872 JLINK_IsHalted() returns FALSE (0005ms, 15148ms total) +T4E58 4259:903 JLINK_IsHalted() returns FALSE (0001ms, 15144ms total) +T4E58 4259:918 JLINK_IsHalted() returns FALSE (0001ms, 15144ms total) +T4E58 4259:934 JLINK_IsHalted() returns FALSE (0001ms, 15144ms total) +T4E58 4259:981 JLINK_IsHalted() returns FALSE (0001ms, 15144ms total) +T4E58 4260:012 JLINK_IsHalted() returns FALSE (0001ms, 15144ms total) +T4E58 4260:044 JLINK_IsHalted() returns FALSE (0002ms, 15145ms total) +T4E58 4260:060 JLINK_IsHalted() returns FALSE (0001ms, 15146ms total) +T4E58 4260:076 JLINK_IsHalted() returns FALSE (0001ms, 15146ms total) +T4E58 4260:107 JLINK_IsHalted() returns FALSE (0000ms, 15146ms total) +T4E58 4260:122 JLINK_IsHalted() returns FALSE (0001ms, 15147ms total) +T4E58 4260:138 JLINK_IsHalted() returns FALSE (0001ms, 15147ms total) +T4E58 4260:169 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0006ms, 15152ms total) +T4E58 4260:175 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0000ms, 15146ms total) +T4E58 4260:175 JLINK_ClrBPEx(BPHandle = 0x00000067) returns 0x00 (0000ms, 15146ms total) +T4E58 4260:175 JLINK_ReadReg(R0) returns 0x4C186042 (0000ms, 15146ms total) +T4E58 4260:182 JLINK_WriteReg(R0, 0x00000003) returns 0x00 (0000ms, 15146ms total) +T4E58 4260:182 JLINK_WriteReg(R1, 0x08010000) returns 0x00 (0000ms, 15146ms total) +T4E58 4260:182 JLINK_WriteReg(R2, 0x00007A84) returns 0x00 (0000ms, 15146ms total) +T4E58 4260:182 JLINK_WriteReg(R3, 0x04C11DB7) returns 0x00 (0000ms, 15146ms total) +T4E58 4260:182 JLINK_WriteReg(R4, 0x00000000) returns 0x00 (0000ms, 15146ms total) +T4E58 4260:183 JLINK_WriteReg(R5, 0x00000000) returns 0x00 (0000ms, 15147ms total) +T4E58 4260:183 JLINK_WriteReg(R6, 0x00000000) returns 0x00 (0000ms, 15147ms total) +T4E58 4260:183 JLINK_WriteReg(R7, 0x00000000) returns 0x00 (0000ms, 15147ms total) +T4E58 4260:183 JLINK_WriteReg(R8, 0x00000000) returns 0x00 (0000ms, 15147ms total) +T4E58 4260:183 JLINK_WriteReg(R9, 0x20000160) returns 0x00 (0000ms, 15147ms total) +T4E58 4260:184 JLINK_WriteReg(R10, 0x00000000) returns 0x00 (0000ms, 15148ms total) +T4E58 4260:184 JLINK_WriteReg(R11, 0x00000000) returns 0x00 (0000ms, 15148ms total) +T4E58 4260:184 JLINK_WriteReg(R12, 0x00000000) returns 0x00 (0000ms, 15148ms total) +T4E58 4260:184 JLINK_WriteReg(R13 (SP), 0x20001000) returns 0x00 (0000ms, 15148ms total) +T4E58 4260:184 JLINK_WriteReg(R14, 0x20000001) returns 0x00 (0000ms, 15148ms total) +T4E58 4260:184 JLINK_WriteReg(R15 (PC), 0x2000006A) returns 0x00 (0001ms, 15149ms total) +T4E58 4260:185 JLINK_WriteReg(XPSR, 0x01000000) returns 0x00 (0000ms, 15149ms total) +T4E58 4260:185 JLINK_WriteReg(MSP, 0x20001000) returns 0x00 (0000ms, 15149ms total) +T4E58 4260:185 JLINK_WriteReg(PSP, 0x20001000) returns 0x00 (0000ms, 15149ms total) +T4E58 4260:185 JLINK_WriteReg(CFBP, 0x00000000) returns 0x00 (0000ms, 15149ms total) +T4E58 4260:185 JLINK_SetBPEx(Addr = 0x20000000, Type = 0xFFFFFFF2) returns 0x00000068 (0000ms, 15149ms total) +T4E58 4260:185 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) (0005ms, 15154ms total) +T4E58 4260:190 JLINK_IsHalted() -- CPU_ReadMem(2 bytes @ 0x20000000) returns TRUE (0005ms, 15159ms total) +T4E58 4260:195 JLINK_ReadReg(R15 (PC)) returns 0x20000000 (0001ms, 15155ms total) +T4E58 4260:196 JLINK_ClrBPEx(BPHandle = 0x00000068) returns 0x00 (0000ms, 15155ms total) +T4E58 4260:196 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 15155ms total) +T4E58 4260:307 JLINK_WriteMemEx(0x20000000, 0x0002 Bytes, ..., Flags = 0x02000000) - Data: FE E7 -- CPU_WriteMem(2 bytes @ 0x20000000) returns 0x02 (0001ms, 15156ms total) +T4E58 4260:308 JLINK_SetResetType(JLINKARM_CM3_RESET_TYPE_NORMAL) returns JLINKARM_CM3_RESET_TYPE_NORMAL (0001ms, 15157ms total) +T4E58 4260:309 JLINK_Reset() -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC)Reset: Halt core after reset via DEMCR.VC_CORERESET. >0x35 TIF>Reset: Reset device via AIRCR.SYSRESETREQ. -- CPU_WriteMem(4 bytes @ 0xE000ED0C) >0x0D TIF> >0x28 TIF> -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE0002000) + -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0167ms, 15324ms total) +T4E58 4260:476 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) -- CPU_WriteMem(4 bytes @ 0xE0001004) (0006ms, 15330ms total) +T4E58 4260:561 JLINK_Close() -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000201C) >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> + >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF> (0041ms, 15371ms total) +T4E58 4260:561 (0042ms, 15372ms total) +T4E58 4260:561 Closed (0042ms, 15372ms total) diff --git a/USER/JLinkSettings.ini b/USER/JLinkSettings.ini new file mode 100644 index 0000000..39b6d05 --- /dev/null +++ b/USER/JLinkSettings.ini @@ -0,0 +1,39 @@ +[BREAKPOINTS] +ForceImpTypeAny = 0 +ShowInfoWin = 1 +EnableFlashBP = 2 +BPDuringExecution = 0 +[CFI] +CFISize = 0x00 +CFIAddr = 0x00 +[CPU] +MonModeVTableAddr = 0xFFFFFFFF +MonModeDebug = 0 +MaxNumAPs = 0 +LowPowerHandlingMode = 0 +OverrideMemMap = 0 +AllowSimulation = 1 +ScriptFile="" +[FLASH] +CacheExcludeSize = 0x00 +CacheExcludeAddr = 0x00 +MinNumBytesFlashDL = 0 +SkipProgOnCRCMatch = 1 +VerifyDownload = 1 +AllowCaching = 1 +EnableFlashDL = 2 +Override = 0 +Device="ARM7" +[GENERAL] +WorkRAMSize = 0x00 +WorkRAMAddr = 0x00 +RAMUsageLimit = 0x00 +[SWO] +SWOLogFile="" +[MEM] +RdOverrideOrMask = 0x00 +RdOverrideAndMask = 0xFFFFFFFF +RdOverrideAddr = 0xFFFFFFFF +WrOverrideOrMask = 0x00 +WrOverrideAndMask = 0xFFFFFFFF +WrOverrideAddr = 0xFFFFFFFF diff --git a/USER/Listings/BT_BMS_V3.map b/USER/Listings/BT_BMS_V3.map new file mode 100644 index 0000000..e5a5eaf --- /dev/null +++ b/USER/Listings/BT_BMS_V3.map @@ -0,0 +1,5603 @@ +Component: ARM Compiler 5.06 update 6 (build 750) Tool: armlink [4d35ed] + +============================================================================== + +Section Cross References + + startup_stm32f10x_hd.o(STACK) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_stm32f10x_hd.o(HEAP) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_stm32f10x_hd.o(RESET) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_stm32f10x_hd.o(RESET) refers to startup_stm32f10x_hd.o(STACK) for __initial_sp + startup_stm32f10x_hd.o(RESET) refers to startup_stm32f10x_hd.o(.text) for Reset_Handler + startup_stm32f10x_hd.o(RESET) refers to stm32f10x_it.o(i.NMI_Handler) for NMI_Handler + startup_stm32f10x_hd.o(RESET) refers to stm32f10x_it.o(i.HardFault_Handler) for HardFault_Handler + startup_stm32f10x_hd.o(RESET) refers to stm32f10x_it.o(i.MemManage_Handler) for MemManage_Handler + startup_stm32f10x_hd.o(RESET) refers to stm32f10x_it.o(i.BusFault_Handler) for BusFault_Handler + startup_stm32f10x_hd.o(RESET) refers to stm32f10x_it.o(i.UsageFault_Handler) for UsageFault_Handler + startup_stm32f10x_hd.o(RESET) refers to stm32f10x_it.o(i.SVC_Handler) for SVC_Handler + startup_stm32f10x_hd.o(RESET) refers to stm32f10x_it.o(i.DebugMon_Handler) for DebugMon_Handler + startup_stm32f10x_hd.o(RESET) refers to stm32f10x_it.o(i.PendSV_Handler) for PendSV_Handler + startup_stm32f10x_hd.o(RESET) refers to stm32f10x_it.o(i.SysTick_Handler) for SysTick_Handler + startup_stm32f10x_hd.o(RESET) refers to can.o(i.USB_LP_CAN1_RX0_IRQHandler) for USB_LP_CAN1_RX0_IRQHandler + startup_stm32f10x_hd.o(RESET) refers to tim.o(i.TIM3_IRQHandler) for TIM3_IRQHandler + startup_stm32f10x_hd.o(RESET) refers to uart.o(i.USART1_IRQHandler) for USART1_IRQHandler + startup_stm32f10x_hd.o(RESET) refers to uart.o(i.USART2_IRQHandler) for USART2_IRQHandler + startup_stm32f10x_hd.o(RESET) refers to uart.o(i.USART3_IRQHandler) for USART3_IRQHandler + startup_stm32f10x_hd.o(RESET) refers to uart.o(i.UART4_IRQHandler) for UART4_IRQHandler + startup_stm32f10x_hd.o(.text) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_stm32f10x_hd.o(.text) refers to system_stm32f10x.o(i.SystemInit) for SystemInit + startup_stm32f10x_hd.o(.text) refers to __main.o(!!!main) for __main + startup_stm32f10x_hd.o(.text) refers to startup_stm32f10x_hd.o(HEAP) for Heap_Mem + startup_stm32f10x_hd.o(.text) refers to startup_stm32f10x_hd.o(STACK) for Stack_Mem + main.o(i.main) refers to systick.o(i.delay_ms) for delay_ms + main.o(i.main) refers to gpio.o(i.uf_GPIO_Init) for uf_GPIO_Init + main.o(i.main) refers to gpio.o(i.uf_EXTI_Init) for uf_EXTI_Init + main.o(i.main) refers to tim.o(i.uf_TIM3_Init) for uf_TIM3_Init + main.o(i.main) refers to i2c.o(i.uf_I2C1_Init) for uf_I2C1_Init + main.o(i.main) refers to spi.o(i.uf_SPI2_Init) for uf_SPI2_Init + main.o(i.main) refers to can.o(i.uf_CAN1_Init) for uf_CAN1_Init + main.o(i.main) refers to adc.o(i.uf_ADC_Init) for uf_ADC_Init + main.o(i.main) refers to wdg.o(i.uf_IWDG_Init) for uf_IWDG_Init + main.o(i.main) refers to flash.o(i.uf_FLASH_Init) for uf_FLASH_Init + main.o(i.main) refers to global.o(i.uf_GLOBAL_Init) for uf_GLOBAL_Init + main.o(i.main) refers to mbo26a.o(i.BLE_Init) for BLE_Init + main.o(i.main) refers to mbo26a.o(i.BLE_IO_Init) for BLE_IO_Init + main.o(i.main) refers to mbo26a.o(i.BLE_Open) for BLE_Open + main.o(i.main) refers to rs485_modbus.o(i.MODBUS_Init) for MODBUS_Init + main.o(i.main) refers to rs485_modbus_inverter.o(i.MODBUS1_Init) for MODBUS1_Init + main.o(i.main) refers to afe_sh3673520.o(i.AFE_VoltageProcess) for AFE_VoltageProcess + main.o(i.main) refers to gasgauge.o(i.InitGasGauge) for InitGasGauge + main.o(i.main) refers to adc.o(i.MCU_TemperaProcess) for MCU_TemperaProcess + main.o(i.main) refers to rs485_modbus.o(i.MODBUS_Poll_Init) for MODBUS_Poll_Init + main.o(i.main) refers to screen.o(i.Screen_Init) for Screen_Init + main.o(i.main) refers to rtc.o(i.uf_RTC_Init) for uf_RTC_Init + main.o(i.main) refers to rtc.o(i.RTC_Get) for RTC_Get + main.o(i.main) refers to tim.o(i.TIMER_IsOut) for TIMER_IsOut + main.o(i.main) refers to tim.o(i.TIMER_Update) for TIMER_Update + main.o(i.main) refers to mbo26a.o(i.BLE_IQ_Update) for BLE_IQ_Update + main.o(i.main) refers to mbo26a.o(i.BLE_IQ_Transmit) for BLE_IQ_Transmit + main.o(i.main) refers to afe_sh3673520.o(i.AFE_CurrentProcess) for AFE_CurrentProcess + main.o(i.main) refers to afe_sh3673520.o(i.CALI_CurrentProcess) for CALI_CurrentProcess + main.o(i.main) refers to gpio.o(i.LED_RUN_Off) for LED_RUN_Off + main.o(i.main) refers to gpio.o(i.LED_RUN_On) for LED_RUN_On + main.o(i.main) refers to gpio.o(i.LED_RUN_Toggle) for LED_RUN_Toggle + main.o(i.main) refers to gpio.o(i.LED_ALARM_Off) for LED_ALARM_Off + main.o(i.main) refers to gpio.o(i.LED_ALARM_Toggle) for LED_ALARM_Toggle + main.o(i.main) refers to rs485_modbus.o(i.MODBUS_AddrAssign_Tx) for MODBUS_AddrAssign_Tx + main.o(i.main) refers to rs485_modbus.o(i.MODBUS_Config_RdSlave_Tx) for MODBUS_Config_RdSlave_Tx + main.o(i.main) refers to rs485_modbus.o(i.MODBUS_WrIndex_Tx) for MODBUS_WrIndex_Tx + main.o(i.main) refers to rs485_modbus.o(i.MODBUS_Screen_WrSlaveAddr_Tx) for MODBUS_Screen_WrSlaveAddr_Tx + main.o(i.main) refers to rs485_modbus.o(i.MODBUS_Screen_RdSlave_Tx) for MODBUS_Screen_RdSlave_Tx + main.o(i.main) refers to rs485_modbus.o(i.MODBUS_MASTER_Polling_Tx) for MODBUS_MASTER_Polling_Tx + main.o(i.main) refers to afe_sh3673520.o(i.AFE_TemperaProcess) for AFE_TemperaProcess + main.o(i.main) refers to afe_sh3673520.o(i.AFE_ProtectProcess) for AFE_ProtectProcess + main.o(i.main) refers to wdg.o(i.IWDG_Feed) for IWDG_Feed + main.o(i.main) refers to afe_sh3673520.o(i.CHG_LIMIT_Ctrl) for CHG_LIMIT_Ctrl + main.o(i.main) refers to gpio.o(i.TSC_Detect) for TSC_Detect + main.o(i.main) refers to gpio.o(i.PCHG_StartCtrl) for PCHG_StartCtrl + main.o(i.main) refers to afe_sh3673520.o(i.AFE_Ctrl) for AFE_Ctrl + main.o(i.main) refers to ocv.o(i.OCV_CaliSOC) for OCV_CaliSOC + main.o(i.main) refers to global.o(i.ParaChange) for ParaChange + main.o(i.main) refers to gasgauge.o(i.GaugeManage) for GaugeManage + main.o(i.main) refers to global.o(i.canMem_refresh) for canMem_refresh + main.o(i.main) refers to global.o(i.onlineMem_refresh) for onlineMem_refresh + main.o(i.main) refers to screen.o(i.Screen_IQ_Transmit) for Screen_IQ_Transmit + main.o(i.main) refers to can.o(i.CAN_UpdateData) for CAN_UpdateData + main.o(i.main) refers to rs485_modbus_inverter.o(i.MODBUS1_UpdateData) for MODBUS1_UpdateData + main.o(i.main) refers to rtc.o(i.uf_RTC_Update) for uf_RTC_Update + main.o(i.main) refers to global.o(i.Addr_Set) for Addr_Set + main.o(i.main) refers to rtc.o(i.RTC_BackUp) for RTC_BackUp + main.o(i.main) refers to screen.o(i.Screen_IT_Update) for Screen_IT_Update + main.o(i.main) refers to rs485_modbus.o(i.MODBUS_IQ_Transmit) for MODBUS_IQ_Transmit + main.o(i.main) refers to rs485_modbus_inverter.o(i.MODBUS1_IQ_Transmit) for MODBUS1_IQ_Transmit + main.o(i.main) refers to global.o(.bss) for paraMem + main.o(i.main) refers to rtc.o(.data) for LSEErrFlag + main.o(i.main) refers to tim.o(.bss) for tmrTemp + main.o(i.main) refers to rs485_modbus_inverter.o(.data) for ConfigData_Index + main.o(i.main) refers to uart.o(.data) for Screen_RevHandlerFlg + main.o(i.main) refers to afe_sh3673520.o(.data) for bAlarmFlag + main.o(i.main) refers to global.o(.data) for sleep_Moni_Count + main.o(i.main) refers to rs485_modbus.o(.data) for PollStop_flag + main.o(i.main) refers to rs485_modbus.o(.data) for assignAddr_relay + main.o(i.main) refers to screen.o(.data) for scr_RdData_Index + main.o(i.main) refers to gpio.o(.data) for TSC_detectFlag + global.o(i.Addr_Set) refers to i2c.o(i.EEPROM_WrMulByte) for EEPROM_WrMulByte + global.o(i.Addr_Set) refers to systick.o(i.delay_ms) for delay_ms + global.o(i.Addr_Set) refers to gpio.o(i.IO2_OUTSet) for IO2_OUTSet + global.o(i.Addr_Set) refers to gpio.o(i.IO2_OUTReset) for IO2_OUTReset + global.o(i.Addr_Set) refers to global.o(.bss) for .bss + global.o(i.Addr_Set) refers to rs485_modbus.o(.data) for assignAddr_State + global.o(i.Addr_Set) refers to screen.o(.data) for scr_RdData_Index + global.o(i.Addr_Set) refers to gpio.o(.data) for ClearArray_Flag + global.o(i.CRC8_Cal) refers to global.o(.constdata) for .constdata + global.o(i.FCCCali_TIM_Moni) refers to gasgauge.o(.data) for fcc_CaliStartFlag + global.o(i.FCCCali_TIM_Moni) refers to global.o(.bss) for .bss + global.o(i.FCCCali_TIM_Moni) refers to global.o(.data) for .data + global.o(i.GetID) refers to strstr.o(.text) for strstr + global.o(i.GetID) refers to strlen.o(.text) for strlen + global.o(i.GetID) refers to strchr.o(.text) for strchr + global.o(i.GetID) refers to strncpy.o(.text) for strncpy + global.o(i.GetStr) refers to strstr.o(.text) for strstr + global.o(i.GetStr) refers to strlen.o(.text) for strlen + global.o(i.GetStr) refers to strchr.o(.text) for strchr + global.o(i.GetStr) refers to strncpy.o(.text) for strncpy + global.o(i.GetStrFromJson) refers to strstr.o(.text) for strstr + global.o(i.GetStrFromJson) refers to strlen.o(.text) for strlen + global.o(i.GetStrFromJson) refers to strchr.o(.text) for strchr + global.o(i.GetStrFromJson) refers to strncpy.o(.text) for strncpy + global.o(i.ParaChange) refers to i2c.o(i.EEPROM_RdMulByte) for EEPROM_RdMulByte + global.o(i.ParaChange) refers to i2c.o(i.EEPROM_WrMulByte) for EEPROM_WrMulByte + global.o(i.ParaChange) refers to systick.o(i.delay_ms) for delay_ms + global.o(i.ParaChange) refers to global.o(i.SLEEP_Refresh) for SLEEP_Refresh + global.o(i.ParaChange) refers to global.o(i.SLEEP2_Refresh) for SLEEP2_Refresh + global.o(i.ParaChange) refers to flash.o(i.MEMORY_UpdateFlash) for MEMORY_UpdateFlash + global.o(i.ParaChange) refers to global.o(.bss) for .bss + global.o(i.ParaChange) refers to global.o(.data) for .data + global.o(i.ParaChange) refers to screen.o(.data) for scr_RdData_Index + global.o(i.ParaChange) refers to gasgauge.o(.data) for fcc + global.o(i.ParaChange) refers to rtc.o(.data) for LSEErrFlag + global.o(i.ParaChange) refers to afe_sh3673520.o(.data) for CTRL_Order + global.o(i.Refresh_BMS_SN) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + global.o(i.Refresh_BMS_SN) refers to _printf_c.o(.ARM.Collect$$_printf_percent$$00000013) for _printf_c + global.o(i.Refresh_BMS_SN) refers to _printf_str.o(.text) for _printf_str + global.o(i.Refresh_BMS_SN) refers to __2sprintf.o(.text) for __2sprintf + global.o(i.Refresh_BMS_SN) refers to global.o(.bss) for .bss + global.o(i.Refresh_BMS_SN) refers to mbo26a.o(.bss) for BMS_SN + global.o(i.Refresh_FirmwareVersion) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + global.o(i.Refresh_FirmwareVersion) refers to _printf_u.o(.ARM.Collect$$_printf_percent$$0000000A) for _printf_u + global.o(i.Refresh_FirmwareVersion) refers to _printf_dec.o(.text) for _printf_int_dec + global.o(i.Refresh_FirmwareVersion) refers to _printf_pad.o(.text) for _printf_pre_padding + global.o(i.Refresh_FirmwareVersion) refers to _printf_x.o(.ARM.Collect$$_printf_percent$$0000000C) for _printf_x + global.o(i.Refresh_FirmwareVersion) refers to _printf_hex_int_ll_ptr.o(.text) for _printf_longlong_hex + global.o(i.Refresh_FirmwareVersion) refers to __2sprintf.o(.text) for __2sprintf + global.o(i.Refresh_FirmwareVersion) refers to global.o(.bss) for .bss + global.o(i.Refresh_FirmwareVersion) refers to mbo26a.o(.bss) for FirmwareVersion + global.o(i.Refresh_HardwareVersion) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + global.o(i.Refresh_HardwareVersion) refers to _printf_u.o(.ARM.Collect$$_printf_percent$$0000000A) for _printf_u + global.o(i.Refresh_HardwareVersion) refers to _printf_dec.o(.text) for _printf_int_dec + global.o(i.Refresh_HardwareVersion) refers to _printf_c.o(.ARM.Collect$$_printf_percent$$00000013) for _printf_c + global.o(i.Refresh_HardwareVersion) refers to _printf_str.o(.text) for _printf_str + global.o(i.Refresh_HardwareVersion) refers to __2sprintf.o(.text) for __2sprintf + global.o(i.Refresh_HardwareVersion) refers to global.o(.bss) for .bss + global.o(i.Refresh_HardwareVersion) refers to mbo26a.o(.data) for HardwareVersion + global.o(i.Refresh_PACK_SN) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + global.o(i.Refresh_PACK_SN) refers to _printf_c.o(.ARM.Collect$$_printf_percent$$00000013) for _printf_c + global.o(i.Refresh_PACK_SN) refers to _printf_str.o(.text) for _printf_str + global.o(i.Refresh_PACK_SN) refers to __2sprintf.o(.text) for __2sprintf + global.o(i.Refresh_PACK_SN) refers to global.o(.bss) for .bss + global.o(i.Refresh_PACK_SN) refers to mbo26a.o(.bss) for PACK_SN + global.o(i.Refresh_ScreenVersion) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + global.o(i.Refresh_ScreenVersion) refers to _printf_u.o(.ARM.Collect$$_printf_percent$$0000000A) for _printf_u + global.o(i.Refresh_ScreenVersion) refers to _printf_dec.o(.text) for _printf_int_dec + global.o(i.Refresh_ScreenVersion) refers to __2sprintf.o(.text) for __2sprintf + global.o(i.Refresh_ScreenVersion) refers to global.o(.bss) for .bss + global.o(i.Refresh_ScreenVersion) refers to mbo26a.o(.data) for ScreenVersion + global.o(i.SLEEP2_Refresh) refers to stm32f10x_rtc.o(i.RTC_GetCounter) for RTC_GetCounter + global.o(i.SLEEP2_Refresh) refers to global.o(.bss) for .bss + global.o(i.SLEEP2_Refresh) refers to afe_sh3673520.o(.data) for cellVoltageMin + global.o(i.SLEEP2_Refresh) refers to rtc.o(.data) for LSEErrFlag + global.o(i.SLEEP2_Refresh) refers to global.o(.data) for .data + global.o(i.SLEEP2_TIM_Moni) refers to rtc.o(.data) for sleep_flag + global.o(i.SLEEP2_TIM_Moni) refers to global.o(.bss) for .bss + global.o(i.SLEEP2_TIM_Moni) refers to afe_sh3673520.o(.data) for cellVoltageMin + global.o(i.SLEEP2_TIM_Moni) refers to global.o(.data) for .data + global.o(i.SLEEP_Refresh) refers to stm32f10x_rtc.o(i.RTC_GetCounter) for RTC_GetCounter + global.o(i.SLEEP_Refresh) refers to rtc.o(.data) for LSEErrFlag + global.o(i.SLEEP_Refresh) refers to global.o(.bss) for .bss + global.o(i.SLEEP_Refresh) refers to global.o(.data) for .data + global.o(i.SLEEP_TIM_Moni) refers to rtc.o(.data) for sleep_flag + global.o(i.SLEEP_TIM_Moni) refers to global.o(.bss) for .bss + global.o(i.SLEEP_TIM_Moni) refers to global.o(.data) for .data + global.o(i.UVOff_TIM_Moni) refers to global.o(.bss) for .bss + global.o(i.UVOff_TIM_Moni) refers to global.o(.data) for .data + global.o(i.canMem_refresh) refers to can.o(.bss) for canMem + global.o(i.canMem_refresh) refers to global.o(.bss) for .bss + global.o(i.canMem_refresh) refers to rs485_modbus.o(.data) for assignAddr_random + global.o(i.canMem_refresh) refers to global.o(.data) for .data + global.o(i.canMem_refresh) refers to rs485_modbus.o(.data) for chg_forbidFlg + global.o(i.canMem_refresh) refers to rs485_modbus.o(.data) for dsg_forbidFlg + global.o(i.canMem_refresh) refers to rs485_modbus.o(.data) for chg_forceFlg + global.o(i.canMem_refresh) refers to rs485_modbus.o(.data) for chg_curlimitFlg + global.o(i.get_random) refers to stm32f10x_rtc.o(i.RTC_GetCounter) for RTC_GetCounter + global.o(i.int_str_len) refers to global.o(i.uint_str_len) for uint_str_len + global.o(i.onlineMem_refresh) refers to global.o(.bss) for .bss + global.o(i.onlineMem_refresh) refers to can.o(.bss) for canMem + global.o(i.uf_GLOBAL_Init) refers to i2c.o(i.EEPROM_CALI_RdZero) for EEPROM_CALI_RdZero + global.o(i.uf_GLOBAL_Init) refers to systick.o(i.delay_ms) for delay_ms + global.o(i.uf_GLOBAL_Init) refers to i2c.o(i.EEPROM_CALI_RdGain) for EEPROM_CALI_RdGain + global.o(i.uf_GLOBAL_Init) refers to i2c.o(i.EEPROM_RdMulByte) for EEPROM_RdMulByte + global.o(i.uf_GLOBAL_Init) refers to i2c.o(i.EEPROM_WrMulByte) for EEPROM_WrMulByte + global.o(i.uf_GLOBAL_Init) refers to global.o(i.Refresh_FirmwareVersion) for Refresh_FirmwareVersion + global.o(i.uf_GLOBAL_Init) refers to global.o(i.Refresh_HardwareVersion) for Refresh_HardwareVersion + global.o(i.uf_GLOBAL_Init) refers to global.o(i.Refresh_ScreenVersion) for Refresh_ScreenVersion + global.o(i.uf_GLOBAL_Init) refers to global.o(i.CRC8_Cal) for CRC8_Cal + global.o(i.uf_GLOBAL_Init) refers to global.o(i.Refresh_BMS_SN) for Refresh_BMS_SN + global.o(i.uf_GLOBAL_Init) refers to global.o(i.Refresh_PACK_SN) for Refresh_PACK_SN + global.o(i.uf_GLOBAL_Init) refers to rt_memclr.o(.text) for __aeabi_memclr + global.o(i.uf_GLOBAL_Init) refers to global.o(.bss) for .bss + global.o(i.uf_GLOBAL_Init) refers to gasgauge.o(.data) for fcc + global.o(i.uf_GLOBAL_Init) refers to afe_sh3673520.o(.bss) for cali + global.o(i.uf_GLOBAL_Init) refers to global.o(.data) for .data + global.o(i.uf_GLOBAL_Init) refers to rs485_modbus.o(.data) for assignAddr_relay + global.o(i.uf_GLOBAL_Init) refers to rs485_modbus_inverter.o(.data) for ConfigData_Index + global.o(i.uf_GLOBAL_Init) refers to screen.o(.data) for scr_RdData_Index + global.o(i.uf_GLOBAL_Init) refers to screen.o(.data) for scr_RdRecord_Flg + global.o(i.uf_GLOBAL_Init) refers to mbo26a.o(.bss) for BMS_SN + system_stm32f10x.o(i.SystemCoreClockUpdate) refers to system_stm32f10x.o(.data) for .data + system_stm32f10x.o(i.SystemInit) refers to system_stm32f10x.o(i.SetSysClockTo72) for SetSysClockTo72 + gpio.o(i.ADDR_Assign_Moni) refers to gpio.o(i.IO1_IN) for IO1_IN + gpio.o(i.ADDR_Assign_Moni) refers to global.o(.bss) for bmsMem + gpio.o(i.ADDR_Assign_Moni) refers to gpio.o(.data) for .data + gpio.o(i.ADDR_Rank_Moni) refers to gpio.o(i.IO3_IN) for IO3_IN + gpio.o(i.ADDR_Rank_Moni) refers to rs485_modbus.o(i.MODBUS_Init) for MODBUS_Init + gpio.o(i.ADDR_Rank_Moni) refers to global.o(.bss) for bmsMem + gpio.o(i.ADDR_Rank_Moni) refers to rs485_modbus.o(.data) for assignAddr_State + gpio.o(i.ADDR_Rank_Moni) refers to screen.o(.data) for scr_RdData_Index + gpio.o(i.ADDR_Rank_Moni) refers to gpio.o(.data) for .data + gpio.o(i.ADDR_Rank_Moni) refers to rs485_modbus.o(.data) for assignAddr_relay + gpio.o(i.DO_Off) refers to stm32f10x_gpio.o(i.GPIO_ResetBits) for GPIO_ResetBits + gpio.o(i.DO_On) refers to stm32f10x_gpio.o(i.GPIO_SetBits) for GPIO_SetBits + gpio.o(i.IO1_IN) refers to stm32f10x_gpio.o(i.GPIO_ReadInputDataBit) for GPIO_ReadInputDataBit + gpio.o(i.IO2_OUTReset) refers to stm32f10x_gpio.o(i.GPIO_ResetBits) for GPIO_ResetBits + gpio.o(i.IO2_OUTSet) refers to stm32f10x_gpio.o(i.GPIO_SetBits) for GPIO_SetBits + gpio.o(i.IO3_IN) refers to stm32f10x_gpio.o(i.GPIO_ReadInputDataBit) for GPIO_ReadInputDataBit + gpio.o(i.KEY_IN) refers to stm32f10x_gpio.o(i.GPIO_ReadInputDataBit) for GPIO_ReadInputDataBit + gpio.o(i.KEY_TIM_Moni) refers to gpio.o(i.KEY_IN) for KEY_IN + gpio.o(i.KEY_TIM_Moni) refers to gpio.o(.data) for .data + gpio.o(i.LED1_Off) refers to stm32f10x_gpio.o(i.GPIO_ResetBits) for GPIO_ResetBits + gpio.o(i.LED1_On) refers to stm32f10x_gpio.o(i.GPIO_SetBits) for GPIO_SetBits + gpio.o(i.LED2_Off) refers to stm32f10x_gpio.o(i.GPIO_ResetBits) for GPIO_ResetBits + gpio.o(i.LED2_On) refers to stm32f10x_gpio.o(i.GPIO_SetBits) for GPIO_SetBits + gpio.o(i.LED3_Off) refers to stm32f10x_gpio.o(i.GPIO_ResetBits) for GPIO_ResetBits + gpio.o(i.LED3_On) refers to stm32f10x_gpio.o(i.GPIO_SetBits) for GPIO_SetBits + gpio.o(i.LED4_Off) refers to stm32f10x_gpio.o(i.GPIO_ResetBits) for GPIO_ResetBits + gpio.o(i.LED4_On) refers to stm32f10x_gpio.o(i.GPIO_SetBits) for GPIO_SetBits + gpio.o(i.LED_ALARM_Off) refers to stm32f10x_gpio.o(i.GPIO_ResetBits) for GPIO_ResetBits + gpio.o(i.LED_ALARM_On) refers to stm32f10x_gpio.o(i.GPIO_SetBits) for GPIO_SetBits + gpio.o(i.LED_ALARM_Toggle) refers to gpio.o(i.HAL_GPIO_TogglePin) for HAL_GPIO_TogglePin + gpio.o(i.LED_ALL_OFF) refers to gpio.o(i.LED_RUN_Off) for LED_RUN_Off + gpio.o(i.LED_ALL_OFF) refers to gpio.o(i.LED_ALARM_Off) for LED_ALARM_Off + gpio.o(i.LED_ALL_OFF) refers to gpio.o(i.LED1_Off) for LED1_Off + gpio.o(i.LED_ALL_OFF) refers to gpio.o(i.LED2_Off) for LED2_Off + gpio.o(i.LED_ALL_OFF) refers to gpio.o(i.LED3_Off) for LED3_Off + gpio.o(i.LED_ALL_OFF) refers to gpio.o(i.LED4_Off) for LED4_Off + gpio.o(i.LED_ALL_ON) refers to gpio.o(i.LED_RUN_On) for LED_RUN_On + gpio.o(i.LED_ALL_ON) refers to gpio.o(i.LED_ALARM_On) for LED_ALARM_On + gpio.o(i.LED_ALL_ON) refers to gpio.o(i.LED1_On) for LED1_On + gpio.o(i.LED_ALL_ON) refers to gpio.o(i.LED2_On) for LED2_On + gpio.o(i.LED_ALL_ON) refers to gpio.o(i.LED3_On) for LED3_On + gpio.o(i.LED_ALL_ON) refers to gpio.o(i.LED4_On) for LED4_On + gpio.o(i.LED_ALL_Toggle) refers to gpio.o(i.HAL_GPIO_TogglePin) for HAL_GPIO_TogglePin + gpio.o(i.LED_RST_Toggle) refers to gpio.o(i.LED_ALL_Toggle) for LED_ALL_Toggle + gpio.o(i.LED_RST_Toggle) refers to gpio.o(i.LED_ALL_ON) for LED_ALL_ON + gpio.o(i.LED_RST_Toggle) refers to gpio.o(.data) for .data + gpio.o(i.LED_RUN_Off) refers to stm32f10x_gpio.o(i.GPIO_ResetBits) for GPIO_ResetBits + gpio.o(i.LED_RUN_On) refers to stm32f10x_gpio.o(i.GPIO_SetBits) for GPIO_SetBits + gpio.o(i.LED_RUN_Toggle) refers to gpio.o(i.HAL_GPIO_TogglePin) for HAL_GPIO_TogglePin + gpio.o(i.MCU_BalanceProcess) refers to global.o(.bss) for bmsMem + gpio.o(i.MCU_BalanceProcess) refers to gpio.o(.data) for .data + gpio.o(i.MCU_BalanceProcess) refers to afe_sh3673520.o(.data) for cellVoltageMax + gpio.o(i.PCHG_Ctrl) refers to gpio.o(i.PCHG_Off) for PCHG_Off + gpio.o(i.PCHG_Ctrl) refers to systick.o(i.delay_ms) for delay_ms + gpio.o(i.PCHG_Ctrl) refers to adc.o(i.LOAD_VOL) for LOAD_VOL + gpio.o(i.PCHG_Ctrl) refers to afe_sh3673520.o(i.CTRL_Off) for CTRL_Off + gpio.o(i.PCHG_Ctrl) refers to gpio.o(i.PCHG_On) for PCHG_On + gpio.o(i.PCHG_Ctrl) refers to afe_sh3673520.o(i.CTRL_On) for CTRL_On + gpio.o(i.PCHG_Ctrl) refers to gpio.o(.data) for .data + gpio.o(i.PCHG_Ctrl) refers to global.o(.bss) for bmsMem + gpio.o(i.PCHG_Ctrl) refers to adc.o(.data) for loadvol + gpio.o(i.PCHG_Off) refers to stm32f10x_gpio.o(i.GPIO_ResetBits) for GPIO_ResetBits + gpio.o(i.PCHG_On) refers to stm32f10x_gpio.o(i.GPIO_SetBits) for GPIO_SetBits + gpio.o(i.PCHG_StartCtrl) refers to gpio.o(i.PCHG_Off) for PCHG_Off + gpio.o(i.PCHG_StartCtrl) refers to systick.o(i.delay_ms) for delay_ms + gpio.o(i.PCHG_StartCtrl) refers to adc.o(i.LOAD_VOL) for LOAD_VOL + gpio.o(i.PCHG_StartCtrl) refers to gpio.o(i.PCHG_On) for PCHG_On + gpio.o(i.PCHG_StartCtrl) refers to afe_sh3673520.o(i.CTRL_On) for CTRL_On + gpio.o(i.PCHG_StartCtrl) refers to gpio.o(.data) for .data + gpio.o(i.PCHG_StartCtrl) refers to global.o(.bss) for bmsMem + gpio.o(i.PCHG_StartCtrl) refers to adc.o(.data) for loadvol + gpio.o(i.POWER_Check) refers to flash.o(i.FLASH_RdWord) for FLASH_RdWord + gpio.o(i.POWER_Check) refers to gpio.o(.data) for .data + gpio.o(i.POWER_Ctrl) refers to flash.o(i.FLASH_WrData) for FLASH_WrData + gpio.o(i.POWER_Ctrl) refers to systick.o(i.delay_ms) for delay_ms + gpio.o(i.POWER_Ctrl) refers to gpio.o(i.POWER_Off) for POWER_Off + gpio.o(i.POWER_Ctrl) refers to gpio.o(i.POWER_On) for POWER_On + gpio.o(i.POWER_Ctrl) refers to gpio.o(.data) for .data + gpio.o(i.POWER_Off) refers to stm32f10x_gpio.o(i.GPIO_ResetBits) for GPIO_ResetBits + gpio.o(i.POWER_On) refers to stm32f10x_gpio.o(i.GPIO_SetBits) for GPIO_SetBits + gpio.o(i.TSC_Detect) refers to afe_sh3673520.o(i.CTRL_Off) for CTRL_Off + gpio.o(i.TSC_Detect) refers to systick.o(i.delay_ms) for delay_ms + gpio.o(i.TSC_Detect) refers to adc.o(i.LOAD_VOL) for LOAD_VOL + gpio.o(i.TSC_Detect) refers to afe_sh3673520.o(i.CTRL_On) for CTRL_On + gpio.o(i.TSC_Detect) refers to gpio.o(.data) for .data + gpio.o(i.TSC_Detect) refers to global.o(.bss) for bmsMem + gpio.o(i.TSC_Detect) refers to adc.o(.data) for loadvol + gpio.o(i.uf_EXTI_Init) refers to misc.o(i.NVIC_PriorityGroupConfig) for NVIC_PriorityGroupConfig + gpio.o(i.uf_GPIO_Init) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) for RCC_APB2PeriphClockCmd + gpio.o(i.uf_GPIO_Init) refers to stm32f10x_gpio.o(i.GPIO_PinRemapConfig) for GPIO_PinRemapConfig + gpio.o(i.uf_GPIO_Init) refers to stm32f10x_gpio.o(i.GPIO_Init) for GPIO_Init + gpio.o(i.uf_GPIO_Init) refers to stm32f10x_gpio.o(i.GPIO_SetBits) for GPIO_SetBits + gpio.o(i.uf_GPIO_Init) refers to stm32f10x_gpio.o(i.GPIO_ResetBits) for GPIO_ResetBits + gpio.o(i.uf_GPIO_Init) refers to pwm.o(i.CHG_LIMIT_Init) for CHG_LIMIT_Init + tim.o(i.TIM3_IRQHandler) refers to stm32f10x_tim.o(i.TIM_GetITStatus) for TIM_GetITStatus + tim.o(i.TIM3_IRQHandler) refers to stm32f10x_tim.o(i.TIM_ClearITPendingBit) for TIM_ClearITPendingBit + tim.o(i.TIM3_IRQHandler) refers to gpio.o(i.KEY_TIM_Moni) for KEY_TIM_Moni + tim.o(i.TIM3_IRQHandler) refers to gasgauge.o(i.Cali_SOC_Moni) for Cali_SOC_Moni + tim.o(i.TIM3_IRQHandler) refers to screen.o(i.Screen_TIM_Moni) for Screen_TIM_Moni + tim.o(i.TIM3_IRQHandler) refers to can.o(i.CAN_TIM_Moni) for CAN_TIM_Moni + tim.o(i.TIM3_IRQHandler) refers to rs485_modbus.o(i.MODBUS_TIM_Moni) for MODBUS_TIM_Moni + tim.o(i.TIM3_IRQHandler) refers to rs485_modbus_inverter.o(i.MODBUS1_TIM_Moni) for MODBUS1_TIM_Moni + tim.o(i.TIM3_IRQHandler) refers to afe_sh3673520.o(i.OCC2_TIM_Moni) for OCC2_TIM_Moni + tim.o(i.TIM3_IRQHandler) refers to afe_sh3673520.o(i.OCC2_Ctrl) for OCC2_Ctrl + tim.o(i.TIM3_IRQHandler) refers to gpio.o(i.ADDR_Rank_Moni) for ADDR_Rank_Moni + tim.o(i.TIM3_IRQHandler) refers to gpio.o(i.ADDR_Assign_Moni) for ADDR_Assign_Moni + tim.o(i.TIM3_IRQHandler) refers to global.o(i.SLEEP_TIM_Moni) for SLEEP_TIM_Moni + tim.o(i.TIM3_IRQHandler) refers to global.o(i.SLEEP2_TIM_Moni) for SLEEP2_TIM_Moni + tim.o(i.TIM3_IRQHandler) refers to global.o(i.UVOff_TIM_Moni) for UVOff_TIM_Moni + tim.o(i.TIM3_IRQHandler) refers to global.o(i.FCCCali_TIM_Moni) for FCCCali_TIM_Moni + tim.o(i.TIM3_IRQHandler) refers to rs485_modbus.o(i.MODBUS_IT_TIMUpdate) for MODBUS_IT_TIMUpdate + tim.o(i.TIM3_IRQHandler) refers to rs485_modbus_inverter.o(i.MODBUS1_IT_TIMUpdate) for MODBUS1_IT_TIMUpdate + tim.o(i.TIM3_IRQHandler) refers to mbo26a.o(i.BLE_TIM_Moni) for BLE_TIM_Moni + tim.o(i.TIM3_IRQHandler) refers to mbo26a.o(i.BLE_IT_Update) for BLE_IT_Update + tim.o(i.TIM3_IRQHandler) refers to tim.o(.data) for .data + tim.o(i.TIM3_IRQHandler) refers to rtc.o(.data) for sleep_flag + tim.o(i.TIM3_IRQHandler) refers to global.o(.bss) for paraMem + tim.o(i.TIM3_IRQHandler) refers to uart.o(.data) for Screen_RevFlg + tim.o(i.TIM3_IRQHandler) refers to uart.o(.data) for Screen_RevHandlerFlg + tim.o(i.TIMER_IsOther) refers to tim.o(.data) for .data + tim.o(i.TIMER_IsOut) refers to tim.o(.data) for .data + tim.o(i.TIMER_Update) refers to tim.o(.data) for .data + tim.o(i.uf_TIM3_Init) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd) for RCC_APB1PeriphClockCmd + tim.o(i.uf_TIM3_Init) refers to stm32f10x_tim.o(i.TIM_TimeBaseInit) for TIM_TimeBaseInit + tim.o(i.uf_TIM3_Init) refers to misc.o(i.NVIC_Init) for NVIC_Init + tim.o(i.uf_TIM3_Init) refers to stm32f10x_tim.o(i.TIM_ITConfig) for TIM_ITConfig + tim.o(i.uf_TIM3_Init) refers to stm32f10x_tim.o(i.TIM_Cmd) for TIM_Cmd + uart.o(i.UART4_IRQHandler) refers to stm32f10x_usart.o(i.USART_GetITStatus) for USART_GetITStatus + uart.o(i.UART4_IRQHandler) refers to mbo26a.o(i.BLE_IT_Receive) for BLE_IT_Receive + uart.o(i.UART4_IRQHandler) refers to uart.o(.data) for .data + uart.o(i.USART1_IRQHandler) refers to stm32f10x_usart.o(i.USART_GetITStatus) for USART_GetITStatus + uart.o(i.USART1_IRQHandler) refers to rs485_modbus.o(i.MODBUS_IT_Receive) for MODBUS_IT_Receive + uart.o(i.USART1_IRQHandler) refers to uart.o(.data) for .data + uart.o(i.USART1_SendMulByte) refers to stm32f10x_usart.o(i.USART_SendData) for USART_SendData + uart.o(i.USART1_SendMulByte) refers to stm32f10x_usart.o(i.USART_GetFlagStatus) for USART_GetFlagStatus + uart.o(i.USART2_IRQHandler) refers to stm32f10x_usart.o(i.USART_GetITStatus) for USART_GetITStatus + uart.o(i.USART2_IRQHandler) refers to screen.o(i.Screen_IT_Receive) for Screen_IT_Receive + uart.o(i.USART2_IRQHandler) refers to uart.o(.data) for .data + uart.o(i.USART3_IRQHandler) refers to stm32f10x_usart.o(i.USART_GetITStatus) for USART_GetITStatus + uart.o(i.USART3_IRQHandler) refers to rs485_modbus_inverter.o(i.MODBUS1_IT_Receive) for MODBUS1_IT_Receive + uart.o(i.USART3_IRQHandler) refers to uart.o(.data) for .data + uart.o(i.USART3_SendMulByte) refers to stm32f10x_usart.o(i.USART_SendData) for USART_SendData + uart.o(i.USART3_SendMulByte) refers to stm32f10x_usart.o(i.USART_GetFlagStatus) for USART_GetFlagStatus + uart.o(i.uf_UART1_Init) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) for RCC_APB2PeriphClockCmd + uart.o(i.uf_UART1_Init) refers to stm32f10x_usart.o(i.USART_Init) for USART_Init + uart.o(i.uf_UART1_Init) refers to stm32f10x_gpio.o(i.GPIO_Init) for GPIO_Init + uart.o(i.uf_UART1_Init) refers to misc.o(i.NVIC_Init) for NVIC_Init + uart.o(i.uf_UART1_Init) refers to stm32f10x_usart.o(i.USART_ITConfig) for USART_ITConfig + uart.o(i.uf_UART1_Init) refers to stm32f10x_usart.o(i.USART_Cmd) for USART_Cmd + uart.o(i.uf_UART1_Init) refers to global.o(.bss) for bmsMem + uart.o(i.uf_UART2_Init) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) for RCC_APB2PeriphClockCmd + uart.o(i.uf_UART2_Init) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd) for RCC_APB1PeriphClockCmd + uart.o(i.uf_UART2_Init) refers to stm32f10x_usart.o(i.USART_Init) for USART_Init + uart.o(i.uf_UART2_Init) refers to stm32f10x_gpio.o(i.GPIO_Init) for GPIO_Init + uart.o(i.uf_UART2_Init) refers to misc.o(i.NVIC_Init) for NVIC_Init + uart.o(i.uf_UART2_Init) refers to stm32f10x_usart.o(i.USART_ITConfig) for USART_ITConfig + uart.o(i.uf_UART2_Init) refers to stm32f10x_usart.o(i.USART_Cmd) for USART_Cmd + uart.o(i.uf_UART3_Init) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) for RCC_APB2PeriphClockCmd + uart.o(i.uf_UART3_Init) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd) for RCC_APB1PeriphClockCmd + uart.o(i.uf_UART3_Init) refers to stm32f10x_usart.o(i.USART_Init) for USART_Init + uart.o(i.uf_UART3_Init) refers to stm32f10x_gpio.o(i.GPIO_Init) for GPIO_Init + uart.o(i.uf_UART3_Init) refers to misc.o(i.NVIC_Init) for NVIC_Init + uart.o(i.uf_UART3_Init) refers to stm32f10x_usart.o(i.USART_ITConfig) for USART_ITConfig + uart.o(i.uf_UART3_Init) refers to stm32f10x_usart.o(i.USART_Cmd) for USART_Cmd + uart.o(i.uf_UART4_Init) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) for RCC_APB2PeriphClockCmd + uart.o(i.uf_UART4_Init) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd) for RCC_APB1PeriphClockCmd + uart.o(i.uf_UART4_Init) refers to stm32f10x_usart.o(i.USART_Init) for USART_Init + uart.o(i.uf_UART4_Init) refers to stm32f10x_gpio.o(i.GPIO_Init) for GPIO_Init + uart.o(i.uf_UART4_Init) refers to misc.o(i.NVIC_Init) for NVIC_Init + uart.o(i.uf_UART4_Init) refers to stm32f10x_usart.o(i.USART_ITConfig) for USART_ITConfig + uart.o(i.uf_UART4_Init) refers to stm32f10x_usart.o(i.USART_Cmd) for USART_Cmd + i2c.o(i.EEPROM_CALI_RdGain) refers to i2c.o(i.EEPROM_RdMulByte) for EEPROM_RdMulByte + i2c.o(i.EEPROM_CALI_RdGain) refers to i2c.o(i.EEPROM_WrMulByte) for EEPROM_WrMulByte + i2c.o(i.EEPROM_CALI_RdGain) refers to systick.o(i.delay_ms) for delay_ms + i2c.o(i.EEPROM_CALI_RdZero) refers to i2c.o(i.EEPROM_RdMulByte) for EEPROM_RdMulByte + i2c.o(i.EEPROM_CALI_RdZero) refers to i2c.o(i.EEPROM_WrMulByte) for EEPROM_WrMulByte + i2c.o(i.EEPROM_CALI_RdZero) refers to systick.o(i.delay_ms) for delay_ms + i2c.o(i.EEPROM_CALI_WrGain) refers to i2c.o(i.EEPROM_WrMulByte) for EEPROM_WrMulByte + i2c.o(i.EEPROM_CALI_WrGain) refers to systick.o(i.delay_ms) for delay_ms + i2c.o(i.EEPROM_CALI_WrGain) refers to i2c.o(i.EEPROM_RdMulByte) for EEPROM_RdMulByte + i2c.o(i.EEPROM_CALI_WrZero) refers to i2c.o(i.EEPROM_WrMulByte) for EEPROM_WrMulByte + i2c.o(i.EEPROM_CALI_WrZero) refers to systick.o(i.delay_ms) for delay_ms + i2c.o(i.EEPROM_CALI_WrZero) refers to i2c.o(i.EEPROM_RdMulByte) for EEPROM_RdMulByte + i2c.o(i.EEPROM_RdMulByte) refers to stm32f10x_i2c.o(i.I2C_GetFlagStatus) for I2C_GetFlagStatus + i2c.o(i.EEPROM_RdMulByte) refers to stm32f10x_i2c.o(i.I2C_AcknowledgeConfig) for I2C_AcknowledgeConfig + i2c.o(i.EEPROM_RdMulByte) refers to stm32f10x_i2c.o(i.I2C_GenerateSTART) for I2C_GenerateSTART + i2c.o(i.EEPROM_RdMulByte) refers to stm32f10x_i2c.o(i.I2C_CheckEvent) for I2C_CheckEvent + i2c.o(i.EEPROM_RdMulByte) refers to stm32f10x_i2c.o(i.I2C_Send7bitAddress) for I2C_Send7bitAddress + i2c.o(i.EEPROM_RdMulByte) refers to stm32f10x_i2c.o(i.I2C_SendData) for I2C_SendData + i2c.o(i.EEPROM_RdMulByte) refers to stm32f10x_i2c.o(i.I2C_ReceiveData) for I2C_ReceiveData + i2c.o(i.EEPROM_RdMulByte) refers to stm32f10x_i2c.o(i.I2C_GenerateSTOP) for I2C_GenerateSTOP + i2c.o(i.EEPROM_WrMulByte) refers to stm32f10x_i2c.o(i.I2C_GetFlagStatus) for I2C_GetFlagStatus + i2c.o(i.EEPROM_WrMulByte) refers to stm32f10x_i2c.o(i.I2C_GenerateSTART) for I2C_GenerateSTART + i2c.o(i.EEPROM_WrMulByte) refers to stm32f10x_i2c.o(i.I2C_CheckEvent) for I2C_CheckEvent + i2c.o(i.EEPROM_WrMulByte) refers to stm32f10x_i2c.o(i.I2C_Send7bitAddress) for I2C_Send7bitAddress + i2c.o(i.EEPROM_WrMulByte) refers to stm32f10x_i2c.o(i.I2C_SendData) for I2C_SendData + i2c.o(i.EEPROM_WrMulByte) refers to stm32f10x_i2c.o(i.I2C_GenerateSTOP) for I2C_GenerateSTOP + i2c.o(i.uf_I2C1_Init) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) for RCC_APB2PeriphClockCmd + i2c.o(i.uf_I2C1_Init) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd) for RCC_APB1PeriphClockCmd + i2c.o(i.uf_I2C1_Init) refers to stm32f10x_gpio.o(i.GPIO_Init) for GPIO_Init + i2c.o(i.uf_I2C1_Init) refers to stm32f10x_i2c.o(i.I2C_DeInit) for I2C_DeInit + i2c.o(i.uf_I2C1_Init) refers to stm32f10x_i2c.o(i.I2C_Init) for I2C_Init + i2c.o(i.uf_I2C1_Init) refers to stm32f10x_i2c.o(i.I2C_Cmd) for I2C_Cmd + i2c.o(i.uf_I2C1_Init) refers to stm32f10x_i2c.o(i.I2C_AcknowledgeConfig) for I2C_AcknowledgeConfig + i2c.o(i.uf_I2C1_Init) refers to i2c.o(i.EEPROM_WrMulByte) for EEPROM_WrMulByte + i2c.o(i.uf_I2C1_Init) refers to systick.o(i.delay_ms) for delay_ms + i2c.o(i.uf_I2C1_Init) refers to i2c.o(i.EEPROM_RdMulByte) for EEPROM_RdMulByte + i2c.o(i.uf_I2C1_Init) refers to flash.o(i.FLASH_RdWord) for FLASH_RdWord + i2c.o(i.uf_I2C1_Init) refers to flash.o(i.FLASH_WrData) for FLASH_WrData + i2c.o(i.uf_I2C1_Init) refers to i2c.o(.data) for .data + i2c.o(i.uf_I2C1_Init) refers to global.o(.bss) for bmsMem + i2c.o(i.uf_I2C1_Init) refers to rtc.o(.data) for fcc_Calitimecount + i2c.o(i.uf_I2C1_Init) refers to gasgauge.o(.data) for fcc_CaliStartFlag + i2c.o(i.uf_I2C1_Init) refers to soe.o(.bss) for soe + spi.o(i.AFE_ReadMulByte) refers to stm32f10x_gpio.o(i.GPIO_ResetBits) for GPIO_ResetBits + spi.o(i.AFE_ReadMulByte) refers to stm32f10x_spi.o(i.SPI_I2S_GetFlagStatus) for SPI_I2S_GetFlagStatus + spi.o(i.AFE_ReadMulByte) refers to stm32f10x_spi.o(i.SPI_I2S_SendData) for SPI_I2S_SendData + spi.o(i.AFE_ReadMulByte) refers to stm32f10x_spi.o(i.SPI_I2S_ReceiveData) for SPI_I2S_ReceiveData + spi.o(i.AFE_ReadMulByte) refers to stm32f10x_gpio.o(i.GPIO_SetBits) for GPIO_SetBits + spi.o(i.AFE_ReadMulByte) refers to systick.o(i.delay_us) for delay_us + spi.o(i.AFE_ReadMulByte) refers to global.o(i.CRC8_Cal) for CRC8_Cal + spi.o(i.AFE_Reset) refers to global.o(i.CRC8_Cal) for CRC8_Cal + spi.o(i.AFE_Reset) refers to stm32f10x_gpio.o(i.GPIO_ResetBits) for GPIO_ResetBits + spi.o(i.AFE_Reset) refers to stm32f10x_spi.o(i.SPI_I2S_GetFlagStatus) for SPI_I2S_GetFlagStatus + spi.o(i.AFE_Reset) refers to stm32f10x_spi.o(i.SPI_I2S_SendData) for SPI_I2S_SendData + spi.o(i.AFE_Reset) refers to stm32f10x_spi.o(i.SPI_I2S_ReceiveData) for SPI_I2S_ReceiveData + spi.o(i.AFE_Reset) refers to stm32f10x_gpio.o(i.GPIO_SetBits) for GPIO_SetBits + spi.o(i.AFE_WriteOneByte) refers to global.o(i.CRC8_Cal) for CRC8_Cal + spi.o(i.AFE_WriteOneByte) refers to stm32f10x_gpio.o(i.GPIO_ResetBits) for GPIO_ResetBits + spi.o(i.AFE_WriteOneByte) refers to stm32f10x_spi.o(i.SPI_I2S_GetFlagStatus) for SPI_I2S_GetFlagStatus + spi.o(i.AFE_WriteOneByte) refers to stm32f10x_spi.o(i.SPI_I2S_SendData) for SPI_I2S_SendData + spi.o(i.AFE_WriteOneByte) refers to stm32f10x_spi.o(i.SPI_I2S_ReceiveData) for SPI_I2S_ReceiveData + spi.o(i.AFE_WriteOneByte) refers to stm32f10x_gpio.o(i.GPIO_SetBits) for GPIO_SetBits + spi.o(i.AFE_WriteOneByte) refers to systick.o(i.delay_us) for delay_us + spi.o(i.SPI2_Error) refers to spi.o(i.uf_SPI2_Init) for uf_SPI2_Init + spi.o(i.uf_SPI2_Init) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd) for RCC_APB1PeriphClockCmd + spi.o(i.uf_SPI2_Init) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) for RCC_APB2PeriphClockCmd + spi.o(i.uf_SPI2_Init) refers to stm32f10x_gpio.o(i.GPIO_Init) for GPIO_Init + spi.o(i.uf_SPI2_Init) refers to stm32f10x_gpio.o(i.GPIO_SetBits) for GPIO_SetBits + spi.o(i.uf_SPI2_Init) refers to stm32f10x_spi.o(i.SPI_I2S_DeInit) for SPI_I2S_DeInit + spi.o(i.uf_SPI2_Init) refers to stm32f10x_spi.o(i.SPI_Init) for SPI_Init + spi.o(i.uf_SPI2_Init) refers to stm32f10x_spi.o(i.SPI_Cmd) for SPI_Cmd + flash.o(i.FLASH_ReadCheck) refers to flash.o(i.FLASH_RdDataByte) for FLASH_RdDataByte + flash.o(i.FLASH_ReadCheck) refers to global.o(i.CRC8_Cal) for CRC8_Cal + flash.o(i.FLASH_ReadCheck) refers to rt_memcpy_w.o(.text) for __aeabi_memcpy4 + flash.o(i.FLASH_ReadCheck) refers to rt_memcpy_v6.o(.text) for __aeabi_memcpy + flash.o(i.FLASH_ReadCheck) refers to global.o(.bss) for bmsMem + flash.o(i.FLASH_UpdateMemory) refers to flash.o(i.FLASH_ReadCheck) for FLASH_ReadCheck + flash.o(i.FLASH_WrData) refers to stm32f10x_flash.o(i.FLASH_Unlock) for FLASH_Unlock + flash.o(i.FLASH_WrData) refers to stm32f10x_flash.o(i.FLASH_ClearFlag) for FLASH_ClearFlag + flash.o(i.FLASH_WrData) refers to stm32f10x_flash.o(i.FLASH_ErasePage) for FLASH_ErasePage + flash.o(i.FLASH_WrData) refers to stm32f10x_flash.o(i.FLASH_ProgramHalfWord) for FLASH_ProgramHalfWord + flash.o(i.FLASH_WrData) refers to stm32f10x_flash.o(i.FLASH_Lock) for FLASH_Lock + flash.o(i.MEMORY_UpdateFlash) refers to rt_memcpy_w.o(.text) for __aeabi_memcpy4 + flash.o(i.MEMORY_UpdateFlash) refers to rt_memcpy_v6.o(.text) for __aeabi_memcpy + flash.o(i.MEMORY_UpdateFlash) refers to flash.o(i.FLASH_WrData) for FLASH_WrData + flash.o(i.MEMORY_UpdateFlash) refers to flash.o(i.FLASH_RdDataByte) for FLASH_RdDataByte + flash.o(i.MEMORY_UpdateFlash) refers to global.o(i.CRC8_Cal) for CRC8_Cal + flash.o(i.MEMORY_UpdateFlash) refers to global.o(.bss) for bmsMem + flash.o(i.uf_FLASH_Init) refers to flash.o(i.FLASH_UpdateMemory) for FLASH_UpdateMemory + flash.o(i.uf_FLASH_Init) refers to afe_sh3673520.o(i.MEMORY_UpdateAFE) for MEMORY_UpdateAFE + flash.o(i.uf_FLASH_Init) refers to global.o(.data) for staPack + flash.o(i.uf_FLASH_Init) refers to global.o(.bss) for bmsMem + rtc.o(i.RTC_BackUp) refers to i2c.o(i.EEPROM_WrMulByte) for EEPROM_WrMulByte + rtc.o(i.RTC_BackUp) refers to systick.o(i.delay_ms) for delay_ms + rtc.o(i.RTC_BackUp) refers to afe_sh3673520.o(.data) for bCHGING + rtc.o(i.RTC_BackUp) refers to global.o(.bss) for bmsMem + rtc.o(i.RTC_BackUp) refers to rtc.o(.data) for .data + rtc.o(i.RTC_Get) refers to stm32f10x_rtc.o(i.RTC_GetCounter) for RTC_GetCounter + rtc.o(i.RTC_Get) refers to rtc.o(i.Is_Leap_Year) for Is_Leap_Year + rtc.o(i.RTC_Get) refers to rtc.o(i.RTC_Get_Week) for RTC_Get_Week + rtc.o(i.RTC_Get) refers to i2c.o(i.EEPROM_WrMulByte) for EEPROM_WrMulByte + rtc.o(i.RTC_Get) refers to systick.o(i.delay_ms) for delay_ms + rtc.o(i.RTC_Get) refers to rtc.o(.data) for .data + rtc.o(i.RTC_Get) refers to rtc.o(.constdata) for .constdata + rtc.o(i.RTC_Get) refers to global.o(.bss) for paraMem + rtc.o(i.RTC_Get) refers to global.o(.data) for sleep_Moni_Count + rtc.o(i.RTC_Get) refers to afe_sh3673520.o(.data) for cellVoltageMin + rtc.o(i.RTC_Get) refers to ocv.o(.data) for OCV_Wait_flag + rtc.o(i.RTC_Get) refers to gasgauge.o(.data) for fcc_CaliStartFlag + rtc.o(i.RTC_GetSynchro) refers to systick.o(i.delay_ms) for delay_ms + rtc.o(i.RTC_Get_Week) refers to rtc.o(.constdata) for .constdata + rtc.o(i.RTC_Set) refers to rtc.o(i.Is_Leap_Year) for Is_Leap_Year + rtc.o(i.RTC_Set) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd) for RCC_APB1PeriphClockCmd + rtc.o(i.RTC_Set) refers to stm32f10x_pwr.o(i.PWR_BackupAccessCmd) for PWR_BackupAccessCmd + rtc.o(i.RTC_Set) refers to stm32f10x_rtc.o(i.RTC_SetCounter) for RTC_SetCounter + rtc.o(i.RTC_Set) refers to stm32f10x_rtc.o(i.RTC_WaitForLastTask) for RTC_WaitForLastTask + rtc.o(i.RTC_Set) refers to rtc.o(.constdata) for .constdata + rtc.o(i.uf_RTC_Init) refers to i2c.o(i.EEPROM_RdMulByte) for EEPROM_RdMulByte + rtc.o(i.uf_RTC_Init) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd) for RCC_APB1PeriphClockCmd + rtc.o(i.uf_RTC_Init) refers to stm32f10x_pwr.o(i.PWR_BackupAccessCmd) for PWR_BackupAccessCmd + rtc.o(i.uf_RTC_Init) refers to stm32f10x_bkp.o(i.BKP_ReadBackupRegister) for BKP_ReadBackupRegister + rtc.o(i.uf_RTC_Init) refers to stm32f10x_bkp.o(i.BKP_DeInit) for BKP_DeInit + rtc.o(i.uf_RTC_Init) refers to stm32f10x_rcc.o(i.RCC_LSEConfig) for RCC_LSEConfig + rtc.o(i.uf_RTC_Init) refers to systick.o(i.delay_ms) for delay_ms + rtc.o(i.uf_RTC_Init) refers to stm32f10x_rcc.o(i.RCC_GetFlagStatus) for RCC_GetFlagStatus + rtc.o(i.uf_RTC_Init) refers to stm32f10x_rcc.o(i.RCC_RTCCLKConfig) for RCC_RTCCLKConfig + rtc.o(i.uf_RTC_Init) refers to stm32f10x_rcc.o(i.RCC_RTCCLKCmd) for RCC_RTCCLKCmd + rtc.o(i.uf_RTC_Init) refers to stm32f10x_rtc.o(i.RTC_WaitForLastTask) for RTC_WaitForLastTask + rtc.o(i.uf_RTC_Init) refers to stm32f10x_rtc.o(i.RTC_WaitForSynchro) for RTC_WaitForSynchro + rtc.o(i.uf_RTC_Init) refers to stm32f10x_rtc.o(i.RTC_ITConfig) for RTC_ITConfig + rtc.o(i.uf_RTC_Init) refers to stm32f10x_rtc.o(i.RTC_EnterConfigMode) for RTC_EnterConfigMode + rtc.o(i.uf_RTC_Init) refers to stm32f10x_rtc.o(i.RTC_SetPrescaler) for RTC_SetPrescaler + rtc.o(i.uf_RTC_Init) refers to rtc.o(i.RTC_Set) for RTC_Set + rtc.o(i.uf_RTC_Init) refers to stm32f10x_rtc.o(i.RTC_ExitConfigMode) for RTC_ExitConfigMode + rtc.o(i.uf_RTC_Init) refers to stm32f10x_bkp.o(i.BKP_WriteBackupRegister) for BKP_WriteBackupRegister + rtc.o(i.uf_RTC_Init) refers to rtc.o(i.RTC_GetSynchro) for RTC_GetSynchro + rtc.o(i.uf_RTC_Init) refers to stm32f10x_rtc.o(i.RTC_GetCounter) for RTC_GetCounter + rtc.o(i.uf_RTC_Init) refers to rtc.o(.data) for .data + rtc.o(i.uf_RTC_Init) refers to global.o(.bss) for paraMem + rtc.o(i.uf_RTC_Init) refers to afe_sh3673520.o(.data) for cellVoltageMin + rtc.o(i.uf_RTC_Update) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd) for RCC_APB1PeriphClockCmd + rtc.o(i.uf_RTC_Update) refers to stm32f10x_pwr.o(i.PWR_BackupAccessCmd) for PWR_BackupAccessCmd + rtc.o(i.uf_RTC_Update) refers to stm32f10x_bkp.o(i.BKP_DeInit) for BKP_DeInit + rtc.o(i.uf_RTC_Update) refers to stm32f10x_rcc.o(i.RCC_LSEConfig) for RCC_LSEConfig + rtc.o(i.uf_RTC_Update) refers to systick.o(i.delay_ms) for delay_ms + rtc.o(i.uf_RTC_Update) refers to stm32f10x_rcc.o(i.RCC_GetFlagStatus) for RCC_GetFlagStatus + rtc.o(i.uf_RTC_Update) refers to stm32f10x_rcc.o(i.RCC_RTCCLKConfig) for RCC_RTCCLKConfig + rtc.o(i.uf_RTC_Update) refers to stm32f10x_rcc.o(i.RCC_RTCCLKCmd) for RCC_RTCCLKCmd + rtc.o(i.uf_RTC_Update) refers to stm32f10x_rtc.o(i.RTC_WaitForLastTask) for RTC_WaitForLastTask + rtc.o(i.uf_RTC_Update) refers to stm32f10x_rtc.o(i.RTC_WaitForSynchro) for RTC_WaitForSynchro + rtc.o(i.uf_RTC_Update) refers to stm32f10x_rtc.o(i.RTC_ITConfig) for RTC_ITConfig + rtc.o(i.uf_RTC_Update) refers to stm32f10x_rtc.o(i.RTC_EnterConfigMode) for RTC_EnterConfigMode + rtc.o(i.uf_RTC_Update) refers to stm32f10x_rtc.o(i.RTC_SetPrescaler) for RTC_SetPrescaler + rtc.o(i.uf_RTC_Update) refers to rtc.o(i.RTC_Set) for RTC_Set + rtc.o(i.uf_RTC_Update) refers to stm32f10x_rtc.o(i.RTC_ExitConfigMode) for RTC_ExitConfigMode + rtc.o(i.uf_RTC_Update) refers to stm32f10x_bkp.o(i.BKP_WriteBackupRegister) for BKP_WriteBackupRegister + rtc.o(i.uf_RTC_Update) refers to i2c.o(i.EEPROM_WrMulByte) for EEPROM_WrMulByte + rtc.o(i.uf_RTC_Update) refers to rtc.o(.data) for .data + can.o(i.CAN1_SendData) refers to stm32f10x_can.o(i.CAN_Transmit) for CAN_Transmit + can.o(i.CAN1_SendData) refers to stm32f10x_can.o(i.CAN_TransmitStatus) for CAN_TransmitStatus + can.o(i.CAN1_SendData) refers to can.o(.bss) for .bss + can.o(i.CAN1_SendData) refers to can.o(.data) for .data + can.o(i.CAN_TIM_Moni) refers to can.o(i.uf_CAN1_Init) for uf_CAN1_Init + can.o(i.CAN_TIM_Moni) refers to can.o(.data) for .data + can.o(i.CAN_UpdateData) refers to protocolswitch_p1.o(i.CAN_Protocol_Growatt) for CAN_Protocol_Growatt + can.o(i.CAN_UpdateData) refers to protocolswitch_p1.o(i.CAN_Protocol_SolArk) for CAN_Protocol_SolArk + can.o(i.CAN_UpdateData) refers to protocolswitch_p1.o(i.CAN_Protocol_Pylon) for CAN_Protocol_Pylon + can.o(i.CAN_UpdateData) refers to protocolswitch_p1.o(i.CAN_Protocol_Deye) for CAN_Protocol_Deye + can.o(i.CAN_UpdateData) refers to protocolswitch_p1.o(i.CAN_Protocol_solis) for CAN_Protocol_solis + can.o(i.CAN_UpdateData) refers to screen.o(.data) for protocol + can.o(i.USB_LP_CAN1_RX0_IRQHandler) refers to stm32f10x_can.o(i.CAN_GetITStatus) for CAN_GetITStatus + can.o(i.USB_LP_CAN1_RX0_IRQHandler) refers to stm32f10x_can.o(i.CAN_Receive) for CAN_Receive + can.o(i.USB_LP_CAN1_RX0_IRQHandler) refers to global.o(i.SLEEP_Refresh) for SLEEP_Refresh + can.o(i.USB_LP_CAN1_RX0_IRQHandler) refers to global.o(i.SLEEP2_Refresh) for SLEEP2_Refresh + can.o(i.USB_LP_CAN1_RX0_IRQHandler) refers to can.o(.bss) for .bss + can.o(i.USB_LP_CAN1_RX0_IRQHandler) refers to can.o(.data) for .data + can.o(i.USB_LP_CAN1_RX0_IRQHandler) refers to rtc.o(.data) for sleep_flag + can.o(i.uf_CAN1_Init) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) for RCC_APB2PeriphClockCmd + can.o(i.uf_CAN1_Init) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd) for RCC_APB1PeriphClockCmd + can.o(i.uf_CAN1_Init) refers to stm32f10x_gpio.o(i.GPIO_Init) for GPIO_Init + can.o(i.uf_CAN1_Init) refers to misc.o(i.NVIC_Init) for NVIC_Init + can.o(i.uf_CAN1_Init) refers to systick.o(i.delay_ms) for delay_ms + can.o(i.uf_CAN1_Init) refers to stm32f10x_can.o(i.CAN_DeInit) for CAN_DeInit + can.o(i.uf_CAN1_Init) refers to stm32f10x_can.o(i.CAN_StructInit) for CAN_StructInit + can.o(i.uf_CAN1_Init) refers to stm32f10x_can.o(i.CAN_Init) for CAN_Init + can.o(i.uf_CAN1_Init) refers to stm32f10x_can.o(i.CAN_FilterInit) for CAN_FilterInit + can.o(i.uf_CAN1_Init) refers to stm32f10x_can.o(i.CAN_ITConfig) for CAN_ITConfig + can.o(i.uf_CAN1_Init) refers to screen.o(.data) for protocol + can.o(i.uf_CAN1_Init) refers to can.o(.data) for .data + adc.o(i.ADC_GetVal) refers to stm32f10x_adc.o(i.ADC_RegularChannelConfig) for ADC_RegularChannelConfig + adc.o(i.ADC_GetVal) refers to stm32f10x_adc.o(i.ADC_SoftwareStartConvCmd) for ADC_SoftwareStartConvCmd + adc.o(i.ADC_GetVal) refers to stm32f10x_adc.o(i.ADC_GetFlagStatus) for ADC_GetFlagStatus + adc.o(i.ADC_GetVal) refers to stm32f10x_adc.o(i.ADC_GetConversionValue) for ADC_GetConversionValue + adc.o(i.LOAD_VOL) refers to adc.o(i.ADC_GetVal) for ADC_GetVal + adc.o(i.LOAD_VOL) refers to adc.o(.data) for .data + adc.o(i.MCU_TemperaProcess) refers to adc.o(i.ADC_GetVal) for ADC_GetVal + adc.o(i.MCU_TemperaProcess) refers to ntc.o(i.TEMP_Cal) for TEMP_Cal + adc.o(i.MCU_TemperaProcess) refers to status.o(i.Trigger_mcuTAlarm) for Trigger_mcuTAlarm + adc.o(i.MCU_TemperaProcess) refers to status.o(i.Release_mcuTAlarm) for Release_mcuTAlarm + adc.o(i.MCU_TemperaProcess) refers to status.o(i.Trigger_mcuTProtect) for Trigger_mcuTProtect + adc.o(i.MCU_TemperaProcess) refers to status.o(i.Release_mcuTProtect) for Release_mcuTProtect + adc.o(i.MCU_TemperaProcess) refers to status.o(i.Trigger_CurAlarm) for Trigger_CurAlarm + adc.o(i.MCU_TemperaProcess) refers to status.o(i.Release_CurAlarm) for Release_CurAlarm + adc.o(i.MCU_TemperaProcess) refers to status.o(i.Trigger_CurProtect) for Trigger_CurProtect + adc.o(i.MCU_TemperaProcess) refers to status.o(i.Release_CurProtect) for Release_CurProtect + adc.o(i.MCU_TemperaProcess) refers to status.o(i.Trigger_CurProtectLock) for Trigger_CurProtectLock + adc.o(i.MCU_TemperaProcess) refers to global.o(.bss) for bmsMem + adc.o(i.MCU_TemperaProcess) refers to adc.o(.data) for .data + adc.o(i.uf_ADC_Init) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) for RCC_APB2PeriphClockCmd + adc.o(i.uf_ADC_Init) refers to stm32f10x_gpio.o(i.GPIO_Init) for GPIO_Init + adc.o(i.uf_ADC_Init) refers to stm32f10x_rcc.o(i.RCC_ADCCLKConfig) for RCC_ADCCLKConfig + adc.o(i.uf_ADC_Init) refers to stm32f10x_adc.o(i.ADC_DeInit) for ADC_DeInit + adc.o(i.uf_ADC_Init) refers to stm32f10x_adc.o(i.ADC_Init) for ADC_Init + adc.o(i.uf_ADC_Init) refers to stm32f10x_adc.o(i.ADC_Cmd) for ADC_Cmd + adc.o(i.uf_ADC_Init) refers to stm32f10x_adc.o(i.ADC_ResetCalibration) for ADC_ResetCalibration + adc.o(i.uf_ADC_Init) refers to stm32f10x_adc.o(i.ADC_GetResetCalibrationStatus) for ADC_GetResetCalibrationStatus + adc.o(i.uf_ADC_Init) refers to stm32f10x_adc.o(i.ADC_StartCalibration) for ADC_StartCalibration + adc.o(i.uf_ADC_Init) refers to stm32f10x_adc.o(i.ADC_GetCalibrationStatus) for ADC_GetCalibrationStatus + pwm.o(i.CHG_LIMIT_Init) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) for RCC_APB2PeriphClockCmd + pwm.o(i.CHG_LIMIT_Init) refers to stm32f10x_gpio.o(i.GPIO_Init) for GPIO_Init + pwm.o(i.CHG_LIMIT_Init) refers to stm32f10x_gpio.o(i.GPIO_ResetBits) for GPIO_ResetBits + pwm.o(i.CHG_LIMIT_Init) refers to pwm.o(i.TIM4_PWM_Init) for TIM4_PWM_Init + pwm.o(i.CHG_LIMIT_Off) refers to stm32f10x_gpio.o(i.GPIO_ResetBits) for GPIO_ResetBits + pwm.o(i.CHG_LIMIT_Off) refers to pwm.o(i.PWM_Set_Duty_Percent) for PWM_Set_Duty_Percent + pwm.o(i.CHG_LIMIT_Off) refers to systick.o(i.delay_ms) for delay_ms + pwm.o(i.CHG_LIMIT_Off) refers to pwm.o(.data) for .data + pwm.o(i.CHG_LIMIT_On) refers to systick.o(i.delay_ms) for delay_ms + pwm.o(i.CHG_LIMIT_On) refers to fflt_clz.o(x$fpl$ffltu) for __aeabi_ui2f + pwm.o(i.CHG_LIMIT_On) refers to fdiv.o(x$fpl$fdiv) for __aeabi_fdiv + pwm.o(i.CHG_LIMIT_On) refers to fmul.o(x$fpl$fmul) for __aeabi_fmul + pwm.o(i.CHG_LIMIT_On) refers to f2d.o(x$fpl$f2d) for __aeabi_f2d + pwm.o(i.CHG_LIMIT_On) refers to daddsub_clz.o(x$fpl$dadd) for __aeabi_dadd + pwm.o(i.CHG_LIMIT_On) refers to dfix.o(x$fpl$dfix) for __aeabi_d2iz + pwm.o(i.CHG_LIMIT_On) refers to fflt_clz.o(x$fpl$fflt) for __aeabi_i2f + pwm.o(i.CHG_LIMIT_On) refers to stm32f10x_gpio.o(i.GPIO_SetBits) for GPIO_SetBits + pwm.o(i.CHG_LIMIT_On) refers to pwm.o(i.PWM_Set_Duty_Percent) for PWM_Set_Duty_Percent + pwm.o(i.CHG_LIMIT_On) refers to pwm.o(.data) for .data + pwm.o(i.CHG_LIMIT_On) refers to global.o(.bss) for bmsMem + pwm.o(i.CHG_LIMIT_PWM_Adjust) refers to faddsub_clz.o(x$fpl$fsub) for __aeabi_fsub + pwm.o(i.CHG_LIMIT_PWM_Adjust) refers to faddsub_clz.o(x$fpl$fadd) for __aeabi_fadd + pwm.o(i.CHG_LIMIT_PWM_Adjust) refers to pwm.o(i.PWM_Set_Duty_Percent) for PWM_Set_Duty_Percent + pwm.o(i.CHG_LIMIT_PWM_Adjust) refers to global.o(.bss) for bmsMem + pwm.o(i.CHG_LIMIT_PWM_Adjust) refers to pwm.o(.data) for .data + pwm.o(i.PWM_Set_Duty_Percent) refers to fdiv.o(x$fpl$fdiv) for __aeabi_fdiv + pwm.o(i.PWM_Set_Duty_Percent) refers to fmul.o(x$fpl$fmul) for __aeabi_fmul + pwm.o(i.PWM_Set_Duty_Percent) refers to faddsub_clz.o(x$fpl$fadd) for __aeabi_fadd + pwm.o(i.PWM_Set_Duty_Percent) refers to ffixu.o(x$fpl$ffixu) for __aeabi_f2uiz + pwm.o(i.PWM_Set_Duty_Percent) refers to stm32f10x_tim.o(i.TIM_SetCompare4) for TIM_SetCompare4 + pwm.o(i.TIM4_PWM_Init) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd) for RCC_APB1PeriphClockCmd + pwm.o(i.TIM4_PWM_Init) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) for RCC_APB2PeriphClockCmd + pwm.o(i.TIM4_PWM_Init) refers to stm32f10x_gpio.o(i.GPIO_Init) for GPIO_Init + pwm.o(i.TIM4_PWM_Init) refers to stm32f10x_tim.o(i.TIM_TimeBaseInit) for TIM_TimeBaseInit + pwm.o(i.TIM4_PWM_Init) refers to stm32f10x_tim.o(i.TIM_OC4Init) for TIM_OC4Init + pwm.o(i.TIM4_PWM_Init) refers to stm32f10x_tim.o(i.TIM_OC4PreloadConfig) for TIM_OC4PreloadConfig + pwm.o(i.TIM4_PWM_Init) refers to stm32f10x_tim.o(i.TIM_ARRPreloadConfig) for TIM_ARRPreloadConfig + pwm.o(i.TIM4_PWM_Init) refers to stm32f10x_tim.o(i.TIM_CtrlPWMOutputs) for TIM_CtrlPWMOutputs + pwm.o(i.TIM4_PWM_Init) refers to stm32f10x_tim.o(i.TIM_Cmd) for TIM_Cmd + wdg.o(i.IWDG_Feed) refers to stm32f10x_iwdg.o(i.IWDG_ReloadCounter) for IWDG_ReloadCounter + wdg.o(i.uf_IWDG_Init) refers to stm32f10x_iwdg.o(i.IWDG_WriteAccessCmd) for IWDG_WriteAccessCmd + wdg.o(i.uf_IWDG_Init) refers to stm32f10x_iwdg.o(i.IWDG_SetPrescaler) for IWDG_SetPrescaler + wdg.o(i.uf_IWDG_Init) refers to stm32f10x_iwdg.o(i.IWDG_SetReload) for IWDG_SetReload + wdg.o(i.uf_IWDG_Init) refers to stm32f10x_iwdg.o(i.IWDG_ReloadCounter) for IWDG_ReloadCounter + wdg.o(i.uf_IWDG_Init) refers to stm32f10x_iwdg.o(i.IWDG_Enable) for IWDG_Enable + afe_sh3673520.o(i.AFE_Ctrl) refers to gpio.o(i.PCHG_Ctrl) for PCHG_Ctrl + afe_sh3673520.o(i.AFE_Ctrl) refers to pwm.o(i.CHG_LIMIT_Off) for CHG_LIMIT_Off + afe_sh3673520.o(i.AFE_Ctrl) refers to afe_sh3673520.o(i.AFE_Write) for AFE_Write + afe_sh3673520.o(i.AFE_Ctrl) refers to pwm.o(i.CHG_LIMIT_On) for CHG_LIMIT_On + afe_sh3673520.o(i.AFE_Ctrl) refers to gpio.o(.data) for PCHG_Flag + afe_sh3673520.o(i.AFE_Ctrl) refers to afe_sh3673520.o(.data) for .data + afe_sh3673520.o(i.AFE_Ctrl) refers to rtc.o(.data) for sleep_flag + afe_sh3673520.o(i.AFE_Ctrl) refers to global.o(.bss) for bmsMem + afe_sh3673520.o(i.AFE_CurrentProcess) refers to afe_sh3673520.o(i.AFE_Read) for AFE_Read + afe_sh3673520.o(i.AFE_CurrentProcess) refers to pwm.o(i.CHG_LIMIT_PWM_Adjust) for CHG_LIMIT_PWM_Adjust + afe_sh3673520.o(i.AFE_CurrentProcess) refers to global.o(i.SLEEP_Refresh) for SLEEP_Refresh + afe_sh3673520.o(i.AFE_CurrentProcess) refers to global.o(i.SLEEP2_Refresh) for SLEEP2_Refresh + afe_sh3673520.o(i.AFE_CurrentProcess) refers to afe_sh3673520.o(.data) for .data + afe_sh3673520.o(i.AFE_CurrentProcess) refers to global.o(.bss) for bmsMem + afe_sh3673520.o(i.AFE_CurrentProcess) refers to afe_sh3673520.o(.bss) for .bss + afe_sh3673520.o(i.AFE_CurrentProcess) refers to pwm.o(.data) for curLimit_ctrlFlag + afe_sh3673520.o(i.AFE_CurrentProcess) refers to rtc.o(.data) for sleep_flag + afe_sh3673520.o(i.AFE_ProtectProcess) refers to afe_sh3673520.o(i.AFE_Read) for AFE_Read + afe_sh3673520.o(i.AFE_ProtectProcess) refers to afe_sh3673520.o(i.AFE_Write) for AFE_Write + afe_sh3673520.o(i.AFE_ProtectProcess) refers to gpio.o(i.DO_On) for DO_On + afe_sh3673520.o(i.AFE_ProtectProcess) refers to afe_sh3673520.o(i.CTRL_Off) for CTRL_Off + afe_sh3673520.o(i.AFE_ProtectProcess) refers to gpio.o(i.DO_Off) for DO_Off + afe_sh3673520.o(i.AFE_ProtectProcess) refers to gpio.o(i.LED_ALARM_Off) for LED_ALARM_Off + afe_sh3673520.o(i.AFE_ProtectProcess) refers to gpio.o(i.LED_ALARM_On) for LED_ALARM_On + afe_sh3673520.o(i.AFE_ProtectProcess) refers to global.o(.bss) for bmsMem + afe_sh3673520.o(i.AFE_ProtectProcess) refers to afe_sh3673520.o(.data) for .data + afe_sh3673520.o(i.AFE_ProtectProcess) refers to gpio.o(.data) for TSC_detectFlag + afe_sh3673520.o(i.AFE_ProtectProcess) refers to gpio.o(.data) for TSC_Flag + afe_sh3673520.o(i.AFE_ProtectProcess) refers to rtc.o(.data) for sleep_flag + afe_sh3673520.o(i.AFE_ProtectProcess) refers to soe.o(.bss) for soe + afe_sh3673520.o(i.AFE_ProtectProcess) refers to soe.o(i.SOE_BkData) for SOE_BkData + afe_sh3673520.o(i.AFE_Read) refers to spi.o(i.AFE_ReadMulByte) for AFE_ReadMulByte + afe_sh3673520.o(i.AFE_Read) refers to spi.o(i.SPI2_Error) for SPI2_Error + afe_sh3673520.o(i.AFE_Read) refers to systick.o(i.delay_ms) for delay_ms + afe_sh3673520.o(i.AFE_TemperaProcess) refers to afe_sh3673520.o(i.AFE_Read) for AFE_Read + afe_sh3673520.o(i.AFE_TemperaProcess) refers to ntc.o(i.TEMP_Cal_CMFA) for TEMP_Cal_CMFA + afe_sh3673520.o(i.AFE_TemperaProcess) refers to status.o(i.Trigger_afeTAlarm) for Trigger_afeTAlarm + afe_sh3673520.o(i.AFE_TemperaProcess) refers to status.o(i.Release_afeTAlarm) for Release_afeTAlarm + afe_sh3673520.o(i.AFE_TemperaProcess) refers to status.o(i.Trigger_afeTProtect) for Trigger_afeTProtect + afe_sh3673520.o(i.AFE_TemperaProcess) refers to status.o(i.Release_afeTProtect) for Release_afeTProtect + afe_sh3673520.o(i.AFE_TemperaProcess) refers to status.o(i.Trigger_amTAlarm) for Trigger_amTAlarm + afe_sh3673520.o(i.AFE_TemperaProcess) refers to status.o(i.Release_amTAlarm) for Release_amTAlarm + afe_sh3673520.o(i.AFE_TemperaProcess) refers to status.o(i.Trigger_amTProtect) for Trigger_amTProtect + afe_sh3673520.o(i.AFE_TemperaProcess) refers to status.o(i.Release_amTProtect) for Release_amTProtect + afe_sh3673520.o(i.AFE_TemperaProcess) refers to afe_sh3673520.o(.bss) for .bss + afe_sh3673520.o(i.AFE_TemperaProcess) refers to afe_sh3673520.o(.data) for .data + afe_sh3673520.o(i.AFE_TemperaProcess) refers to global.o(.bss) for bmsMem + afe_sh3673520.o(i.AFE_VoltageProcess) refers to afe_sh3673520.o(i.AFE_Read) for AFE_Read + afe_sh3673520.o(i.AFE_VoltageProcess) refers to status.o(i.Trigger_OVAlarm) for Trigger_OVAlarm + afe_sh3673520.o(i.AFE_VoltageProcess) refers to status.o(i.Release_OVAlarm) for Release_OVAlarm + afe_sh3673520.o(i.AFE_VoltageProcess) refers to status.o(i.Trigger_OVProtect) for Trigger_OVProtect + afe_sh3673520.o(i.AFE_VoltageProcess) refers to status.o(i.Release_OVProtect) for Release_OVProtect + afe_sh3673520.o(i.AFE_VoltageProcess) refers to status.o(i.Trigger_UVAlarm) for Trigger_UVAlarm + afe_sh3673520.o(i.AFE_VoltageProcess) refers to status.o(i.Release_UVAlarm) for Release_UVAlarm + afe_sh3673520.o(i.AFE_VoltageProcess) refers to status.o(i.Trigger_UVProtect) for Trigger_UVProtect + afe_sh3673520.o(i.AFE_VoltageProcess) refers to status.o(i.Release_UVProtect) for Release_UVProtect + afe_sh3673520.o(i.AFE_VoltageProcess) refers to global.o(.bss) for paraMem + afe_sh3673520.o(i.AFE_VoltageProcess) refers to afe_sh3673520.o(.bss) for .bss + afe_sh3673520.o(i.AFE_VoltageProcess) refers to afe_sh3673520.o(.data) for .data + afe_sh3673520.o(i.AFE_Write) refers to spi.o(i.AFE_WriteOneByte) for AFE_WriteOneByte + afe_sh3673520.o(i.AFE_Write) refers to systick.o(i.delay_ms) for delay_ms + afe_sh3673520.o(i.CALI_CurrentProcess) refers to i2c.o(i.EEPROM_CALI_WrZero) for EEPROM_CALI_WrZero + afe_sh3673520.o(i.CALI_CurrentProcess) refers to i2c.o(i.EEPROM_CALI_WrGain) for EEPROM_CALI_WrGain + afe_sh3673520.o(i.CALI_CurrentProcess) refers to afe_sh3673520.o(.bss) for .bss + afe_sh3673520.o(i.CALI_CurrentProcess) refers to screen.o(.data) for scr_WrZero_Flg + afe_sh3673520.o(i.CALI_CurrentProcess) refers to rs485_modbus.o(.data) for modbusFaaRxFlg + afe_sh3673520.o(i.CALI_CurrentProcess) refers to rs485_modbus_inverter.o(.data) for modbus1FaaRxFlg + afe_sh3673520.o(i.CALI_CurrentProcess) refers to screen.o(.data) for scr_WrGain_Flg + afe_sh3673520.o(i.CHG_LIMIT_Ctrl) refers to afe_sh3673520.o(.data) for .data + afe_sh3673520.o(i.CHG_LIMIT_Ctrl) refers to global.o(.bss) for bmsMem + afe_sh3673520.o(i.CTRL_Off) refers to afe_sh3673520.o(i.AFE_Write) for AFE_Write + afe_sh3673520.o(i.CTRL_Off) refers to afe_sh3673520.o(.data) for .data + afe_sh3673520.o(i.CTRL_On) refers to afe_sh3673520.o(.data) for .data + afe_sh3673520.o(i.MEMORY_UpdateAFE) refers to afe_sh3673520.o(i.AFE_Write) for AFE_Write + afe_sh3673520.o(i.MEMORY_UpdateAFE) refers to spi.o(i.AFE_Reset) for AFE_Reset + afe_sh3673520.o(i.MEMORY_UpdateAFE) refers to afe_sh3673520.o(i.AFE_Read) for AFE_Read + afe_sh3673520.o(i.MEMORY_UpdateAFE) refers to global.o(.bss) for paraMem + afe_sh3673520.o(i.OCC2_Ctrl) refers to afe_sh3673520.o(i.AFE_Read) for AFE_Read + afe_sh3673520.o(i.OCC2_Ctrl) refers to afe_sh3673520.o(i.AFE_Write) for AFE_Write + afe_sh3673520.o(i.OCC2_Ctrl) refers to global.o(.bss) for bmsMem + afe_sh3673520.o(i.OCC2_Ctrl) refers to afe_sh3673520.o(.data) for .data + afe_sh3673520.o(i.OCC2_TIM_Moni) refers to global.o(.bss) for bmsMem + afe_sh3673520.o(i.OCC2_TIM_Moni) refers to afe_sh3673520.o(.data) for .data + rs485_modbus.o(i.CRC16_Cal) refers to rs485_modbus.o(.constdata) for .constdata + rs485_modbus.o(i.MODBUS_AddrAssign_Tx) refers to rs485_modbus.o(i.MODBUS_Init) for MODBUS_Init + rs485_modbus.o(i.MODBUS_AddrAssign_Tx) refers to gpio.o(i.IO2_OUTSet) for IO2_OUTSet + rs485_modbus.o(i.MODBUS_AddrAssign_Tx) refers to gpio.o(i.IO2_OUTReset) for IO2_OUTReset + rs485_modbus.o(i.MODBUS_AddrAssign_Tx) refers to global.o(i.get_random) for get_random + rs485_modbus.o(i.MODBUS_AddrAssign_Tx) refers to global.o(i.CRC8_Cal) for CRC8_Cal + rs485_modbus.o(i.MODBUS_AddrAssign_Tx) refers to rs485_modbus.o(i.CRC16_Cal) for CRC16_Cal + rs485_modbus.o(i.MODBUS_AddrAssign_Tx) refers to uart.o(i.USART1_SendMulByte) for USART1_SendMulByte + rs485_modbus.o(i.MODBUS_AddrAssign_Tx) refers to stm32f10x_usart.o(i.USART_ITConfig) for USART_ITConfig + rs485_modbus.o(i.MODBUS_AddrAssign_Tx) refers to rs485_modbus.o(.data) for .data + rs485_modbus.o(i.MODBUS_AddrAssign_Tx) refers to global.o(.bss) for paraMem + rs485_modbus.o(i.MODBUS_AddrAssign_Tx) refers to rs485_modbus.o(.bss) for .bss + rs485_modbus.o(i.MODBUS_Config_RdSlave_Tx) refers to rs485_modbus.o(i.MODBUS_Init) for MODBUS_Init + rs485_modbus.o(i.MODBUS_Config_RdSlave_Tx) refers to rs485_modbus.o(i.CRC16_Cal) for CRC16_Cal + rs485_modbus.o(i.MODBUS_Config_RdSlave_Tx) refers to uart.o(i.USART1_SendMulByte) for USART1_SendMulByte + rs485_modbus.o(i.MODBUS_Config_RdSlave_Tx) refers to stm32f10x_usart.o(i.USART_ITConfig) for USART_ITConfig + rs485_modbus.o(i.MODBUS_Config_RdSlave_Tx) refers to rs485_modbus.o(.data) for .data + rs485_modbus.o(i.MODBUS_Config_RdSlave_Tx) refers to rs485_modbus.o(.bss) for .bss + rs485_modbus.o(i.MODBUS_Config_RdSlave_Tx) refers to rs485_modbus_inverter.o(.data) for ConfigData_Index + rs485_modbus.o(i.MODBUS_Config_RdSlave_Tx) refers to global.o(.bss) for bmsMem_slave + rs485_modbus.o(i.MODBUS_Config_RdSlave_Tx) refers to can.o(.bss) for canMem + rs485_modbus.o(i.MODBUS_CtrlMOS_Rx) refers to rs485_modbus.o(i.CRC16_Cal) for CRC16_Cal + rs485_modbus.o(i.MODBUS_CtrlMOS_Rx) refers to rt_memcpy_v6.o(.text) for __aeabi_memcpy + rs485_modbus.o(i.MODBUS_CtrlMOS_Rx) refers to rs485_modbus.o(i.MODBUS_Init) for MODBUS_Init + rs485_modbus.o(i.MODBUS_CtrlMOS_Rx) refers to rs485_modbus.o(.bss) for .bss + rs485_modbus.o(i.MODBUS_F03_Rx) refers to rs485_modbus.o(i.CRC16_Cal) for CRC16_Cal + rs485_modbus.o(i.MODBUS_F03_Rx) refers to stm32f10x_usart.o(i.USART_ITConfig) for USART_ITConfig + rs485_modbus.o(i.MODBUS_F03_Rx) refers to rs485_modbus.o(i.MODBUS_Init) for MODBUS_Init + rs485_modbus.o(i.MODBUS_F03_Rx) refers to rs485_modbus.o(.bss) for .bss + rs485_modbus.o(i.MODBUS_F03_Rx) refers to rs485_modbus.o(.data) for .data + rs485_modbus.o(i.MODBUS_F10_Rx) refers to rs485_modbus.o(i.CRC16_Cal) for CRC16_Cal + rs485_modbus.o(i.MODBUS_F10_Rx) refers to global.o(i.CRC8_Cal) for CRC8_Cal + rs485_modbus.o(i.MODBUS_F10_Rx) refers to rt_memcpy_v6.o(.text) for __aeabi_memcpy + rs485_modbus.o(i.MODBUS_F10_Rx) refers to stm32f10x_usart.o(i.USART_ITConfig) for USART_ITConfig + rs485_modbus.o(i.MODBUS_F10_Rx) refers to rs485_modbus.o(i.MODBUS_Init) for MODBUS_Init + rs485_modbus.o(i.MODBUS_F10_Rx) refers to rs485_modbus.o(.bss) for .bss + rs485_modbus.o(i.MODBUS_F10_Rx) refers to rs485_modbus.o(.data) for .data + rs485_modbus.o(i.MODBUS_F10_Rx) refers to global.o(.bss) for paraMem + rs485_modbus.o(i.MODBUS_F10_Rx) refers to rs485_modbus_inverter.o(.data) for cumuliCapClear_flag + rs485_modbus.o(i.MODBUS_Faa_Rx) refers to rs485_modbus.o(i.CRC16_Cal) for CRC16_Cal + rs485_modbus.o(i.MODBUS_Faa_Rx) refers to stm32f10x_usart.o(i.USART_ITConfig) for USART_ITConfig + rs485_modbus.o(i.MODBUS_Faa_Rx) refers to rs485_modbus.o(i.MODBUS_Init) for MODBUS_Init + rs485_modbus.o(i.MODBUS_Faa_Rx) refers to rs485_modbus.o(.bss) for .bss + rs485_modbus.o(i.MODBUS_Faa_Rx) refers to afe_sh3673520.o(.bss) for cali + rs485_modbus.o(i.MODBUS_Fbb_Rx) refers to rs485_modbus.o(i.CRC16_Cal) for CRC16_Cal + rs485_modbus.o(i.MODBUS_Fbb_Rx) refers to stm32f10x_usart.o(i.USART_ITConfig) for USART_ITConfig + rs485_modbus.o(i.MODBUS_Fbb_Rx) refers to rs485_modbus.o(i.MODBUS_Init) for MODBUS_Init + rs485_modbus.o(i.MODBUS_Fbb_Rx) refers to rs485_modbus.o(.bss) for .bss + rs485_modbus.o(i.MODBUS_Fbb_Rx) refers to afe_sh3673520.o(.bss) for cali + rs485_modbus.o(i.MODBUS_IQ_Transmit) refers to rs485_modbus.o(i.CRC16_Cal) for CRC16_Cal + rs485_modbus.o(i.MODBUS_IQ_Transmit) refers to flash.o(i.MEMORY_UpdateFlash) for MEMORY_UpdateFlash + rs485_modbus.o(i.MODBUS_IQ_Transmit) refers to afe_sh3673520.o(i.MEMORY_UpdateAFE) for MEMORY_UpdateAFE + rs485_modbus.o(i.MODBUS_IQ_Transmit) refers to uart.o(i.USART1_SendMulByte) for USART1_SendMulByte + rs485_modbus.o(i.MODBUS_IQ_Transmit) refers to i2c.o(i.EEPROM_WrMulByte) for EEPROM_WrMulByte + rs485_modbus.o(i.MODBUS_IQ_Transmit) refers to systick.o(i.delay_ms) for delay_ms + rs485_modbus.o(i.MODBUS_IQ_Transmit) refers to global.o(i.Refresh_HardwareVersion) for Refresh_HardwareVersion + rs485_modbus.o(i.MODBUS_IQ_Transmit) refers to global.o(i.Refresh_ScreenVersion) for Refresh_ScreenVersion + rs485_modbus.o(i.MODBUS_IQ_Transmit) refers to mbo26a.o(i.BLE_WriteName) for BLE_WriteName + rs485_modbus.o(i.MODBUS_IQ_Transmit) refers to global.o(i.Refresh_PACK_SN) for Refresh_PACK_SN + rs485_modbus.o(i.MODBUS_IQ_Transmit) refers to i2c.o(i.EEPROM_RdMulByte) for EEPROM_RdMulByte + rs485_modbus.o(i.MODBUS_IQ_Transmit) refers to stm32f10x_usart.o(i.USART_ITConfig) for USART_ITConfig + rs485_modbus.o(i.MODBUS_IQ_Transmit) refers to can.o(i.uf_CAN1_Init) for uf_CAN1_Init + rs485_modbus.o(i.MODBUS_IQ_Transmit) refers to rs485_modbus.o(.data) for .data + rs485_modbus.o(i.MODBUS_IQ_Transmit) refers to rs485_modbus.o(.bss) for .bss + rs485_modbus.o(i.MODBUS_IQ_Transmit) refers to global.o(.bss) for bmsMem + rs485_modbus.o(i.MODBUS_IQ_Transmit) refers to afe_sh3673520.o(.bss) for cali + rs485_modbus.o(i.MODBUS_IQ_Transmit) refers to rs485_modbus_inverter.o(.data) for protocolSwitchFail + rs485_modbus.o(i.MODBUS_IQ_Transmit) refers to global.o(.data) for staPack + rs485_modbus.o(i.MODBUS_IQ_Transmit) refers to soe.o(.bss) for soe + rs485_modbus.o(i.MODBUS_IQ_Transmit) refers to screen.o(.data) for scr_RdRecord_Flg + rs485_modbus.o(i.MODBUS_IQ_Transmit) refers to screen.o(.data) for protocol + rs485_modbus.o(i.MODBUS_IT_Receive) refers to stm32f10x_usart.o(i.USART_ReceiveData) for USART_ReceiveData + rs485_modbus.o(i.MODBUS_IT_Receive) refers to stm32f10x_tim.o(i.TIM_SetCounter) for TIM_SetCounter + rs485_modbus.o(i.MODBUS_IT_Receive) refers to stm32f10x_tim.o(i.TIM_Cmd) for TIM_Cmd + rs485_modbus.o(i.MODBUS_IT_Receive) refers to global.o(.bss) for paraMem + rs485_modbus.o(i.MODBUS_IT_Receive) refers to rs485_modbus.o(.data) for .data + rs485_modbus.o(i.MODBUS_IT_Receive) refers to rs485_modbus.o(.bss) for .bss + rs485_modbus.o(i.MODBUS_IT_TIMUpdate) refers to global.o(i.SLEEP_Refresh) for SLEEP_Refresh + rs485_modbus.o(i.MODBUS_IT_TIMUpdate) refers to global.o(i.SLEEP2_Refresh) for SLEEP2_Refresh + rs485_modbus.o(i.MODBUS_IT_TIMUpdate) refers to rs485_modbus.o(i.MODBUS_F03_Rx) for MODBUS_F03_Rx + rs485_modbus.o(i.MODBUS_IT_TIMUpdate) refers to rs485_modbus.o(i.MODBUS_F10_Rx) for MODBUS_F10_Rx + rs485_modbus.o(i.MODBUS_IT_TIMUpdate) refers to rs485_modbus.o(i.MODBUS_MASTER_F03_Rx) for MODBUS_MASTER_F03_Rx + rs485_modbus.o(i.MODBUS_IT_TIMUpdate) refers to rs485_modbus.o(i.MODBUS_MASTER_F10_Rx) for MODBUS_MASTER_F10_Rx + rs485_modbus.o(i.MODBUS_IT_TIMUpdate) refers to rs485_modbus.o(i.MODBUS_Faa_Rx) for MODBUS_Faa_Rx + rs485_modbus.o(i.MODBUS_IT_TIMUpdate) refers to rs485_modbus.o(i.MODBUS_Fbb_Rx) for MODBUS_Fbb_Rx + rs485_modbus.o(i.MODBUS_IT_TIMUpdate) refers to rs485_modbus.o(i.UART1_ReadRecord) for UART1_ReadRecord + rs485_modbus.o(i.MODBUS_IT_TIMUpdate) refers to rs485_modbus.o(i.UART1_ClearRecord) for UART1_ClearRecord + rs485_modbus.o(i.MODBUS_IT_TIMUpdate) refers to rs485_modbus.o(i.UART1_ProtocolSwitch) for UART1_ProtocolSwitch + rs485_modbus.o(i.MODBUS_IT_TIMUpdate) refers to rs485_modbus.o(i.MODBUS_CtrlMOS_Rx) for MODBUS_CtrlMOS_Rx + rs485_modbus.o(i.MODBUS_IT_TIMUpdate) refers to rs485_modbus.o(i.MODBUS_Init) for MODBUS_Init + rs485_modbus.o(i.MODBUS_IT_TIMUpdate) refers to rs485_modbus.o(i.MODBUS_WrIndex_Rx) for MODBUS_WrIndex_Rx + rs485_modbus.o(i.MODBUS_IT_TIMUpdate) refers to global.o(.bss) for bmsMem + rs485_modbus.o(i.MODBUS_IT_TIMUpdate) refers to rtc.o(.data) for LSEErrFlag + rs485_modbus.o(i.MODBUS_IT_TIMUpdate) refers to rs485_modbus.o(.data) for .data + rs485_modbus.o(i.MODBUS_IT_TIMUpdate) refers to rs485_modbus.o(.bss) for .bss + rs485_modbus.o(i.MODBUS_IT_TIMUpdate) refers to rs485_modbus_inverter.o(.data) for ConfigData_Index + rs485_modbus.o(i.MODBUS_IT_TIMUpdate) refers to screen.o(.data) for scr_RdData_Index + rs485_modbus.o(i.MODBUS_IT_TIMUpdate) refers to afe_sh3673520.o(.data) for CTRL_Order + rs485_modbus.o(i.MODBUS_Init) refers to uart.o(i.uf_UART1_Init) for uf_UART1_Init + rs485_modbus.o(i.MODBUS_Init) refers to rs485_modbus.o(.data) for .data + rs485_modbus.o(i.MODBUS_Init) refers to global.o(.bss) for paraMem + rs485_modbus.o(i.MODBUS_MASTER_F03_Rx) refers to rs485_modbus.o(i.CRC16_Cal) for CRC16_Cal + rs485_modbus.o(i.MODBUS_MASTER_F03_Rx) refers to stm32f10x_usart.o(i.USART_ITConfig) for USART_ITConfig + rs485_modbus.o(i.MODBUS_MASTER_F03_Rx) refers to rs485_modbus.o(.bss) for .bss + rs485_modbus.o(i.MODBUS_MASTER_F03_Rx) refers to global.o(.bss) for paraMem + rs485_modbus.o(i.MODBUS_MASTER_F03_Rx) refers to rs485_modbus.o(.data) for .data + rs485_modbus.o(i.MODBUS_MASTER_F10_Rx) refers to rs485_modbus.o(i.CRC16_Cal) for CRC16_Cal + rs485_modbus.o(i.MODBUS_MASTER_F10_Rx) refers to stm32f10x_usart.o(i.USART_ITConfig) for USART_ITConfig + rs485_modbus.o(i.MODBUS_MASTER_F10_Rx) refers to rs485_modbus.o(.bss) for .bss + rs485_modbus.o(i.MODBUS_MASTER_F10_Rx) refers to rs485_modbus.o(.data) for .data + rs485_modbus.o(i.MODBUS_MASTER_Polling_Tx) refers to rs485_modbus.o(i.MODBUS_Init) for MODBUS_Init + rs485_modbus.o(i.MODBUS_MASTER_Polling_Tx) refers to rs485_modbus.o(i.CRC16_Cal) for CRC16_Cal + rs485_modbus.o(i.MODBUS_MASTER_Polling_Tx) refers to uart.o(i.USART1_SendMulByte) for USART1_SendMulByte + rs485_modbus.o(i.MODBUS_MASTER_Polling_Tx) refers to stm32f10x_usart.o(i.USART_ITConfig) for USART_ITConfig + rs485_modbus.o(i.MODBUS_MASTER_Polling_Tx) refers to rs485_modbus.o(.data) for .data + rs485_modbus.o(i.MODBUS_MASTER_Polling_Tx) refers to rs485_modbus.o(.bss) for .bss + rs485_modbus.o(i.MODBUS_MASTER_Polling_Tx) refers to can.o(.bss) for canMem + rs485_modbus.o(i.MODBUS_MASTER_Polling_Tx) refers to global.o(.bss) for paraMem + rs485_modbus.o(i.MODBUS_Poll_Init) refers to global.o(.bss) for bmsMem + rs485_modbus.o(i.MODBUS_Poll_Init) refers to can.o(.bss) for canMem + rs485_modbus.o(i.MODBUS_Poll_Init) refers to global.o(.data) for OnlineNum + rs485_modbus.o(i.MODBUS_Poll_Init) refers to rs485_modbus.o(.data) for .data + rs485_modbus.o(i.MODBUS_Screen_RdSlave_Tx) refers to rs485_modbus.o(i.MODBUS_Init) for MODBUS_Init + rs485_modbus.o(i.MODBUS_Screen_RdSlave_Tx) refers to rs485_modbus.o(i.CRC16_Cal) for CRC16_Cal + rs485_modbus.o(i.MODBUS_Screen_RdSlave_Tx) refers to uart.o(i.USART1_SendMulByte) for USART1_SendMulByte + rs485_modbus.o(i.MODBUS_Screen_RdSlave_Tx) refers to stm32f10x_usart.o(i.USART_ITConfig) for USART_ITConfig + rs485_modbus.o(i.MODBUS_Screen_RdSlave_Tx) refers to rs485_modbus.o(.data) for .data + rs485_modbus.o(i.MODBUS_Screen_RdSlave_Tx) refers to rs485_modbus.o(.bss) for .bss + rs485_modbus.o(i.MODBUS_Screen_RdSlave_Tx) refers to screen.o(.data) for scr_RdData_Index + rs485_modbus.o(i.MODBUS_Screen_RdSlave_Tx) refers to global.o(.bss) for bmsMem_slave + rs485_modbus.o(i.MODBUS_Screen_RdSlave_Tx) refers to can.o(.bss) for canMem + rs485_modbus.o(i.MODBUS_Screen_WrSlaveAddr_Tx) refers to rs485_modbus.o(i.MODBUS_Init) for MODBUS_Init + rs485_modbus.o(i.MODBUS_Screen_WrSlaveAddr_Tx) refers to global.o(i.CRC8_Cal) for CRC8_Cal + rs485_modbus.o(i.MODBUS_Screen_WrSlaveAddr_Tx) refers to rs485_modbus.o(i.CRC16_Cal) for CRC16_Cal + rs485_modbus.o(i.MODBUS_Screen_WrSlaveAddr_Tx) refers to uart.o(i.USART1_SendMulByte) for USART1_SendMulByte + rs485_modbus.o(i.MODBUS_Screen_WrSlaveAddr_Tx) refers to stm32f10x_usart.o(i.USART_ITConfig) for USART_ITConfig + rs485_modbus.o(i.MODBUS_Screen_WrSlaveAddr_Tx) refers to rs485_modbus.o(.data) for .data + rs485_modbus.o(i.MODBUS_Screen_WrSlaveAddr_Tx) refers to screen.o(.data) for scr_RdData_Index + rs485_modbus.o(i.MODBUS_Screen_WrSlaveAddr_Tx) refers to rs485_modbus.o(.bss) for .bss + rs485_modbus.o(i.MODBUS_TIM_Moni) refers to rs485_modbus.o(i.MODBUS_Poll_Init) for MODBUS_Poll_Init + rs485_modbus.o(i.MODBUS_TIM_Moni) refers to rs485_modbus.o(i.MODBUS_Init) for MODBUS_Init + rs485_modbus.o(i.MODBUS_TIM_Moni) refers to rs485_modbus.o(.data) for .data + rs485_modbus.o(i.MODBUS_WrIndex_Rx) refers to rs485_modbus.o(i.CRC16_Cal) for CRC16_Cal + rs485_modbus.o(i.MODBUS_WrIndex_Rx) refers to i2c.o(i.EEPROM_WrMulByte) for EEPROM_WrMulByte + rs485_modbus.o(i.MODBUS_WrIndex_Rx) refers to systick.o(i.delay_ms) for delay_ms + rs485_modbus.o(i.MODBUS_WrIndex_Rx) refers to rs485_modbus.o(i.MODBUS_Init) for MODBUS_Init + rs485_modbus.o(i.MODBUS_WrIndex_Rx) refers to rs485_modbus.o(.bss) for .bss + rs485_modbus.o(i.MODBUS_WrIndex_Rx) refers to rs485_modbus.o(.data) for .data + rs485_modbus.o(i.MODBUS_WrIndex_Rx) refers to global.o(.bss) for bmsMem + rs485_modbus.o(i.MODBUS_WrIndex_Tx) refers to rs485_modbus.o(i.CRC16_Cal) for CRC16_Cal + rs485_modbus.o(i.MODBUS_WrIndex_Tx) refers to uart.o(i.USART1_SendMulByte) for USART1_SendMulByte + rs485_modbus.o(i.MODBUS_WrIndex_Tx) refers to stm32f10x_usart.o(i.USART_ITConfig) for USART_ITConfig + rs485_modbus.o(i.MODBUS_WrIndex_Tx) refers to rs485_modbus.o(.data) for .data + rs485_modbus.o(i.MODBUS_WrIndex_Tx) refers to rs485_modbus.o(.bss) for .bss + rs485_modbus.o(i.UART1_ClearRecord) refers to rs485_modbus.o(i.CRC16_Cal) for CRC16_Cal + rs485_modbus.o(i.UART1_ClearRecord) refers to i2c.o(i.EEPROM_RdMulByte) for EEPROM_RdMulByte + rs485_modbus.o(i.UART1_ClearRecord) refers to stm32f10x_usart.o(i.USART_ITConfig) for USART_ITConfig + rs485_modbus.o(i.UART1_ClearRecord) refers to rs485_modbus.o(i.MODBUS_Init) for MODBUS_Init + rs485_modbus.o(i.UART1_ClearRecord) refers to rs485_modbus.o(.bss) for .bss + rs485_modbus.o(i.UART1_ClearRecord) refers to rs485_modbus.o(.data) for .data + rs485_modbus.o(i.UART1_ProtocolSwitch) refers to rs485_modbus.o(i.CRC16_Cal) for CRC16_Cal + rs485_modbus.o(i.UART1_ProtocolSwitch) refers to strcpy.o(.text) for strcpy + rs485_modbus.o(i.UART1_ProtocolSwitch) refers to strlen.o(.text) for strlen + rs485_modbus.o(i.UART1_ProtocolSwitch) refers to stm32f10x_usart.o(i.USART_ITConfig) for USART_ITConfig + rs485_modbus.o(i.UART1_ProtocolSwitch) refers to rs485_modbus.o(.bss) for .bss + rs485_modbus.o(i.UART1_ProtocolSwitch) refers to rs485_modbus_inverter.o(.data) for protocolNum + rs485_modbus.o(i.UART1_ProtocolSwitch) refers to rs485_modbus_inverter.o(.data) for protocolSwitchFail + rs485_modbus.o(i.UART1_ProtocolSwitch) refers to screen.o(.data) for protocol + rs485_modbus.o(i.UART1_ProtocolSwitch) refers to rs485_modbus.o(.data) for .data + rs485_modbus.o(i.UART1_ReadRecord) refers to rs485_modbus.o(i.CRC16_Cal) for CRC16_Cal + rs485_modbus.o(i.UART1_ReadRecord) refers to stm32f10x_usart.o(i.USART_ITConfig) for USART_ITConfig + rs485_modbus.o(i.UART1_ReadRecord) refers to rs485_modbus.o(i.MODBUS_Init) for MODBUS_Init + rs485_modbus.o(i.UART1_ReadRecord) refers to rs485_modbus.o(.bss) for .bss + rs485_modbus.o(i.UART1_ReadRecord) refers to rs485_modbus.o(.data) for .data + rs485_modbus_inverter.o(i.MODBUS1_CtrlMOS_Rx) refers to rs485_modbus.o(i.CRC16_Cal) for CRC16_Cal + rs485_modbus_inverter.o(i.MODBUS1_CtrlMOS_Rx) refers to rt_memcpy_v6.o(.text) for __aeabi_memcpy + rs485_modbus_inverter.o(i.MODBUS1_CtrlMOS_Rx) refers to rs485_modbus_inverter.o(i.MODBUS1_Init) for MODBUS1_Init + rs485_modbus_inverter.o(i.MODBUS1_CtrlMOS_Rx) refers to rs485_modbus_inverter.o(.bss) for .bss + rs485_modbus_inverter.o(i.MODBUS1_F03_Rx) refers to rs485_modbus.o(i.CRC16_Cal) for CRC16_Cal + rs485_modbus_inverter.o(i.MODBUS1_F03_Rx) refers to stm32f10x_usart.o(i.USART_ITConfig) for USART_ITConfig + rs485_modbus_inverter.o(i.MODBUS1_F03_Rx) refers to rs485_modbus_inverter.o(i.MODBUS1_Init) for MODBUS1_Init + rs485_modbus_inverter.o(i.MODBUS1_F03_Rx) refers to rs485_modbus_inverter.o(.bss) for .bss + rs485_modbus_inverter.o(i.MODBUS1_F03_Rx) refers to global.o(.bss) for VoltronicMem + rs485_modbus_inverter.o(i.MODBUS1_F03_Rx) refers to rs485_modbus_inverter.o(.data) for .data + rs485_modbus_inverter.o(i.MODBUS1_F10_Rx) refers to rs485_modbus.o(i.CRC16_Cal) for CRC16_Cal + rs485_modbus_inverter.o(i.MODBUS1_F10_Rx) refers to global.o(i.CRC8_Cal) for CRC8_Cal + rs485_modbus_inverter.o(i.MODBUS1_F10_Rx) refers to rt_memcpy_v6.o(.text) for __aeabi_memcpy + rs485_modbus_inverter.o(i.MODBUS1_F10_Rx) refers to stm32f10x_usart.o(i.USART_ITConfig) for USART_ITConfig + rs485_modbus_inverter.o(i.MODBUS1_F10_Rx) refers to rs485_modbus_inverter.o(i.MODBUS1_Init) for MODBUS1_Init + rs485_modbus_inverter.o(i.MODBUS1_F10_Rx) refers to rs485_modbus_inverter.o(.bss) for .bss + rs485_modbus_inverter.o(i.MODBUS1_F10_Rx) refers to rs485_modbus_inverter.o(.data) for .data + rs485_modbus_inverter.o(i.MODBUS1_F10_Rx) refers to global.o(.bss) for paraMem + rs485_modbus_inverter.o(i.MODBUS1_Faa_Rx) refers to rs485_modbus.o(i.CRC16_Cal) for CRC16_Cal + rs485_modbus_inverter.o(i.MODBUS1_Faa_Rx) refers to stm32f10x_usart.o(i.USART_ITConfig) for USART_ITConfig + rs485_modbus_inverter.o(i.MODBUS1_Faa_Rx) refers to rs485_modbus_inverter.o(i.MODBUS1_Init) for MODBUS1_Init + rs485_modbus_inverter.o(i.MODBUS1_Faa_Rx) refers to rs485_modbus_inverter.o(.bss) for .bss + rs485_modbus_inverter.o(i.MODBUS1_Faa_Rx) refers to afe_sh3673520.o(.bss) for cali + rs485_modbus_inverter.o(i.MODBUS1_Fbb_Rx) refers to rs485_modbus.o(i.CRC16_Cal) for CRC16_Cal + rs485_modbus_inverter.o(i.MODBUS1_Fbb_Rx) refers to stm32f10x_usart.o(i.USART_ITConfig) for USART_ITConfig + rs485_modbus_inverter.o(i.MODBUS1_Fbb_Rx) refers to rs485_modbus_inverter.o(i.MODBUS1_Init) for MODBUS1_Init + rs485_modbus_inverter.o(i.MODBUS1_Fbb_Rx) refers to rs485_modbus_inverter.o(.bss) for .bss + rs485_modbus_inverter.o(i.MODBUS1_Fbb_Rx) refers to afe_sh3673520.o(.bss) for cali + rs485_modbus_inverter.o(i.MODBUS1_IQ_Transmit) refers to i2c.o(i.EEPROM_WrMulByte) for EEPROM_WrMulByte + rs485_modbus_inverter.o(i.MODBUS1_IQ_Transmit) refers to systick.o(i.delay_ms) for delay_ms + rs485_modbus_inverter.o(i.MODBUS1_IQ_Transmit) refers to uart.o(i.USART3_SendMulByte) for USART3_SendMulByte + rs485_modbus_inverter.o(i.MODBUS1_IQ_Transmit) refers to stm32f10x_usart.o(i.USART_ITConfig) for USART_ITConfig + rs485_modbus_inverter.o(i.MODBUS1_IQ_Transmit) refers to flash.o(i.MEMORY_UpdateFlash) for MEMORY_UpdateFlash + rs485_modbus_inverter.o(i.MODBUS1_IQ_Transmit) refers to afe_sh3673520.o(i.MEMORY_UpdateAFE) for MEMORY_UpdateAFE + rs485_modbus_inverter.o(i.MODBUS1_IQ_Transmit) refers to global.o(i.Refresh_HardwareVersion) for Refresh_HardwareVersion + rs485_modbus_inverter.o(i.MODBUS1_IQ_Transmit) refers to global.o(i.Refresh_ScreenVersion) for Refresh_ScreenVersion + rs485_modbus_inverter.o(i.MODBUS1_IQ_Transmit) refers to global.o(i.Refresh_BMS_SN) for Refresh_BMS_SN + rs485_modbus_inverter.o(i.MODBUS1_IQ_Transmit) refers to mbo26a.o(i.BLE_WriteName) for BLE_WriteName + rs485_modbus_inverter.o(i.MODBUS1_IQ_Transmit) refers to global.o(i.Refresh_PACK_SN) for Refresh_PACK_SN + rs485_modbus_inverter.o(i.MODBUS1_IQ_Transmit) refers to rs485_modbus.o(i.CRC16_Cal) for CRC16_Cal + rs485_modbus_inverter.o(i.MODBUS1_IQ_Transmit) refers to i2c.o(i.EEPROM_RdMulByte) for EEPROM_RdMulByte + rs485_modbus_inverter.o(i.MODBUS1_IQ_Transmit) refers to can.o(i.uf_CAN1_Init) for uf_CAN1_Init + rs485_modbus_inverter.o(i.MODBUS1_IQ_Transmit) refers to rs485_modbus_inverter.o(.data) for .data + rs485_modbus_inverter.o(i.MODBUS1_IQ_Transmit) refers to rs485_modbus_inverter.o(.bss) for .bss + rs485_modbus_inverter.o(i.MODBUS1_IQ_Transmit) refers to global.o(.bss) for bmsMem + rs485_modbus_inverter.o(i.MODBUS1_IQ_Transmit) refers to afe_sh3673520.o(.bss) for cali + rs485_modbus_inverter.o(i.MODBUS1_IQ_Transmit) refers to i2c.o(.data) for IAP_Run + rs485_modbus_inverter.o(i.MODBUS1_IQ_Transmit) refers to global.o(.data) for staPack + rs485_modbus_inverter.o(i.MODBUS1_IQ_Transmit) refers to soe.o(.bss) for soe + rs485_modbus_inverter.o(i.MODBUS1_IQ_Transmit) refers to screen.o(.data) for scr_RdRecord_Flg + rs485_modbus_inverter.o(i.MODBUS1_IQ_Transmit) refers to screen.o(.data) for protocol + rs485_modbus_inverter.o(i.MODBUS1_IT_Receive) refers to stm32f10x_usart.o(i.USART_ReceiveData) for USART_ReceiveData + rs485_modbus_inverter.o(i.MODBUS1_IT_Receive) refers to stm32f10x_tim.o(i.TIM_SetCounter) for TIM_SetCounter + rs485_modbus_inverter.o(i.MODBUS1_IT_Receive) refers to stm32f10x_tim.o(i.TIM_Cmd) for TIM_Cmd + rs485_modbus_inverter.o(i.MODBUS1_IT_Receive) refers to rs485_modbus_inverter.o(.data) for .data + rs485_modbus_inverter.o(i.MODBUS1_IT_Receive) refers to rs485_modbus_inverter.o(.bss) for .bss + rs485_modbus_inverter.o(i.MODBUS1_IT_TIMUpdate) refers to global.o(i.SLEEP_Refresh) for SLEEP_Refresh + rs485_modbus_inverter.o(i.MODBUS1_IT_TIMUpdate) refers to global.o(i.SLEEP2_Refresh) for SLEEP2_Refresh + rs485_modbus_inverter.o(i.MODBUS1_IT_TIMUpdate) refers to protocolswitch_p1.o(i.YDN_Protocol_Pylon) for YDN_Protocol_Pylon + rs485_modbus_inverter.o(i.MODBUS1_IT_TIMUpdate) refers to rs485_modbus_inverter.o(i.MODBUS1_Init) for MODBUS1_Init + rs485_modbus_inverter.o(i.MODBUS1_IT_TIMUpdate) refers to rs485_modbus_inverter.o(i.MODBUS1_Faa_Rx) for MODBUS1_Faa_Rx + rs485_modbus_inverter.o(i.MODBUS1_IT_TIMUpdate) refers to rs485_modbus_inverter.o(i.MODBUS1_Fbb_Rx) for MODBUS1_Fbb_Rx + rs485_modbus_inverter.o(i.MODBUS1_IT_TIMUpdate) refers to rs485_modbus_inverter.o(i.UART3_ReadRecord) for UART3_ReadRecord + rs485_modbus_inverter.o(i.MODBUS1_IT_TIMUpdate) refers to rs485_modbus_inverter.o(i.UART3_ClearRecord) for UART3_ClearRecord + rs485_modbus_inverter.o(i.MODBUS1_IT_TIMUpdate) refers to rs485_modbus_inverter.o(i.UART3_ProtocolSwitch) for UART3_ProtocolSwitch + rs485_modbus_inverter.o(i.MODBUS1_IT_TIMUpdate) refers to rs485_modbus_inverter.o(i.MODBUS1_F10_Rx) for MODBUS1_F10_Rx + rs485_modbus_inverter.o(i.MODBUS1_IT_TIMUpdate) refers to rs485_modbus_inverter.o(i.MODBUS1_CtrlMOS_Rx) for MODBUS1_CtrlMOS_Rx + rs485_modbus_inverter.o(i.MODBUS1_IT_TIMUpdate) refers to rs485_modbus_inverter.o(i.MODBUS1_F03_Rx) for MODBUS1_F03_Rx + rs485_modbus_inverter.o(i.MODBUS1_IT_TIMUpdate) refers to rs485_modbus_inverter.o(i.UART3_EraseIAP) for UART3_EraseIAP + rs485_modbus_inverter.o(i.MODBUS1_IT_TIMUpdate) refers to global.o(.bss) for bmsMem + rs485_modbus_inverter.o(i.MODBUS1_IT_TIMUpdate) refers to rtc.o(.data) for LSEErrFlag + rs485_modbus_inverter.o(i.MODBUS1_IT_TIMUpdate) refers to rs485_modbus_inverter.o(.data) for .data + rs485_modbus_inverter.o(i.MODBUS1_IT_TIMUpdate) refers to rs485_modbus_inverter.o(.bss) for .bss + rs485_modbus_inverter.o(i.MODBUS1_IT_TIMUpdate) refers to screen.o(.data) for protocol + rs485_modbus_inverter.o(i.MODBUS1_IT_TIMUpdate) refers to rs485_modbus.o(.data) for PollStop_flag + rs485_modbus_inverter.o(i.MODBUS1_IT_TIMUpdate) refers to global.o(.bss) for GrowattMem + rs485_modbus_inverter.o(i.MODBUS1_IT_TIMUpdate) refers to global.o(.bss) for VoltronicMem + rs485_modbus_inverter.o(i.MODBUS1_IT_TIMUpdate) refers to can.o(.bss) for canMem + rs485_modbus_inverter.o(i.MODBUS1_IT_TIMUpdate) refers to global.o(.bss) for bmsMem_slave + rs485_modbus_inverter.o(i.MODBUS1_IT_TIMUpdate) refers to afe_sh3673520.o(.data) for CTRL_Order + rs485_modbus_inverter.o(i.MODBUS1_Init) refers to uart.o(i.uf_UART3_Init) for uf_UART3_Init + rs485_modbus_inverter.o(i.MODBUS1_Init) refers to rs485_modbus_inverter.o(.data) for .data + rs485_modbus_inverter.o(i.MODBUS1_TIM_Moni) refers to rs485_modbus_inverter.o(i.MODBUS1_Init) for MODBUS1_Init + rs485_modbus_inverter.o(i.MODBUS1_TIM_Moni) refers to rs485_modbus_inverter.o(.data) for .data + rs485_modbus_inverter.o(i.MODBUS1_UpdateData) refers to protocolswitch_p2.o(i.MOD_Protocol_Voltronic) for MOD_Protocol_Voltronic + rs485_modbus_inverter.o(i.MODBUS1_UpdateData) refers to protocolswitch_p1.o(i.MOD_Protocol_Growatt) for MOD_Protocol_Growatt + rs485_modbus_inverter.o(i.MODBUS1_UpdateData) refers to screen.o(.data) for protocol + rs485_modbus_inverter.o(i.UART3_ClearRecord) refers to rs485_modbus.o(i.CRC16_Cal) for CRC16_Cal + rs485_modbus_inverter.o(i.UART3_ClearRecord) refers to i2c.o(i.EEPROM_RdMulByte) for EEPROM_RdMulByte + rs485_modbus_inverter.o(i.UART3_ClearRecord) refers to stm32f10x_usart.o(i.USART_ITConfig) for USART_ITConfig + rs485_modbus_inverter.o(i.UART3_ClearRecord) refers to rs485_modbus_inverter.o(i.MODBUS1_Init) for MODBUS1_Init + rs485_modbus_inverter.o(i.UART3_ClearRecord) refers to rs485_modbus_inverter.o(.bss) for .bss + rs485_modbus_inverter.o(i.UART3_ClearRecord) refers to rs485_modbus_inverter.o(.data) for .data + rs485_modbus_inverter.o(i.UART3_EraseIAP) refers to rs485_modbus_inverter.o(i.MODBUS1_Init) for MODBUS1_Init + rs485_modbus_inverter.o(i.UART3_EraseIAP) refers to stm32f10x_usart.o(i.USART_ITConfig) for USART_ITConfig + rs485_modbus_inverter.o(i.UART3_EraseIAP) refers to rs485_modbus_inverter.o(.bss) for .bss + rs485_modbus_inverter.o(i.UART3_EraseIAP) refers to rs485_modbus_inverter.o(.data) for .data + rs485_modbus_inverter.o(i.UART3_ProtocolSwitch) refers to rs485_modbus.o(i.CRC16_Cal) for CRC16_Cal + rs485_modbus_inverter.o(i.UART3_ProtocolSwitch) refers to strcpy.o(.text) for strcpy + rs485_modbus_inverter.o(i.UART3_ProtocolSwitch) refers to strlen.o(.text) for strlen + rs485_modbus_inverter.o(i.UART3_ProtocolSwitch) refers to stm32f10x_usart.o(i.USART_ITConfig) for USART_ITConfig + rs485_modbus_inverter.o(i.UART3_ProtocolSwitch) refers to rs485_modbus_inverter.o(.bss) for .bss + rs485_modbus_inverter.o(i.UART3_ProtocolSwitch) refers to rs485_modbus_inverter.o(.data) for .data + rs485_modbus_inverter.o(i.UART3_ProtocolSwitch) refers to screen.o(.data) for protocol + rs485_modbus_inverter.o(i.UART3_ReadRecord) refers to rs485_modbus.o(i.CRC16_Cal) for CRC16_Cal + rs485_modbus_inverter.o(i.UART3_ReadRecord) refers to stm32f10x_usart.o(i.USART_ITConfig) for USART_ITConfig + rs485_modbus_inverter.o(i.UART3_ReadRecord) refers to rs485_modbus_inverter.o(i.MODBUS1_Init) for MODBUS1_Init + rs485_modbus_inverter.o(i.UART3_ReadRecord) refers to rs485_modbus_inverter.o(.bss) for .bss + rs485_modbus_inverter.o(i.UART3_ReadRecord) refers to rs485_modbus_inverter.o(.data) for .data + rs485_modbus_inverter.o(i.YDN) refers to global.o(i.toASCII) for toASCII + rs485_modbus_inverter.o(i.YDN) refers to rs485_modbus_inverter.o(i.MODBUS1_Init) for MODBUS1_Init + rs485_modbus_inverter.o(i.YDN) refers to rs485_modbus_inverter.o(.bss) for .bss + rs485_modbus_inverter.o(i.YDN) refers to rs485_modbus_inverter.o(.data) for .data + rs485_modbus_inverter.o(i.YDN) refers to global.o(.bss) for bmsMem + rs485_modbus_inverter.o(i.YDN) refers to can.o(.bss) for canMem + rs485_modbus_inverter.o(i.YDN) refers to stm32f10x_usart.o(i.USART_ITConfig) for USART_ITConfig + rs485_modbus_inverter.o(i.YDN) refers to rs485_modbus.o(.data) for chg_forbidFlg + rs485_modbus_inverter.o(i.YDN) refers to global.o(.data) for OnlineNum + rs485_modbus_inverter.o(i.YDN) refers to rs485_modbus.o(.data) for chg_curlimitFlg + rs485_modbus_inverter.o(i.YDN) refers to rs485_modbus.o(.data) for dsg_forbidFlg + rs485_modbus_inverter.o(i.YDN) refers to rs485_modbus.o(.data) for RequestFlag + rs485_modbus_inverter.o(i.YDN) refers to rs485_modbus.o(.data) for chg_forceFlg + ntc.o(i.TEMP_Cal) refers to ntc.o(.data) for .data + ntc.o(i.TEMP_Cal) refers to ntc.o(.constdata) for .constdata + ntc.o(i.TEMP_Cal_CMFA) refers to ntc.o(.data) for .data + ntc.o(i.TEMP_Cal_CMFA) refers to ntc.o(.constdata) for .constdata + screen.o(i.SCR_ClearAlarm) refers to screen.o(i.USART2_printf) for USART2_printf + screen.o(i.SCR_ClearAlarm) refers to global.o(.bss) for bmsMem + screen.o(i.SCR_DispProcotol) refers to i2c.o(i.EEPROM_RdMulByte) for EEPROM_RdMulByte + screen.o(i.SCR_DispProcotol) refers to screen.o(i.USART2_printf) for USART2_printf + screen.o(i.SCR_DispProcotol) refers to screen.o(.data) for .data + screen.o(i.SCR_JumpToAlarm) refers to screen.o(i.USART2_printf) for USART2_printf + screen.o(i.SCR_KeepLight0) refers to screen.o(i.USART2_printf) for USART2_printf + screen.o(i.SCR_Send_Record) refers to rt_memclr.o(.text) for __aeabi_memclr + screen.o(i.SCR_Send_Record) refers to rt_memcpy_v6.o(.text) for __aeabi_memcpy + screen.o(i.SCR_Send_Record) refers to screen.o(i.USART2_printf) for USART2_printf + screen.o(i.SCR_Send_Record) refers to screen.o(.bss) for .bss + screen.o(i.SCR_Send_RecordInfo) refers to _printf_pad.o(.text) for _printf_pre_padding + screen.o(i.SCR_Send_RecordInfo) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + screen.o(i.SCR_Send_RecordInfo) refers to _printf_x.o(.ARM.Collect$$_printf_percent$$0000000C) for _printf_x + screen.o(i.SCR_Send_RecordInfo) refers to _printf_hex_int_ll_ptr.o(.text) for _printf_longlong_hex + screen.o(i.SCR_Send_RecordInfo) refers to screen.o(i.USART2_printf) for USART2_printf + screen.o(i.SCR_Send_RecordInfo) refers to i2c.o(i.EEPROM_RdMulByte) for EEPROM_RdMulByte + screen.o(i.SCR_Send_RecordInfo) refers to systick.o(i.delay_ms) for delay_ms + screen.o(i.SCR_Send_RecordInfo) refers to screen.o(i.Set_Row_Hide) for Set_Row_Hide + screen.o(i.SCR_Send_RecordInfo) refers to screen.o(i.Send_Record_Blank) for Send_Record_Blank + screen.o(i.SCR_Send_RecordInfo) refers to __2sprintf.o(.text) for __2sprintf + screen.o(i.SCR_Send_RecordInfo) refers to screen.o(i.SCR_Send_Record) for SCR_Send_Record + screen.o(i.SCR_Send_RecordInfo) refers to screen.o(.data) for .data + screen.o(i.SCR_Send_RecordInfo) refers to soe.o(.bss) for soe + screen.o(i.SCR_Send_RecordInfo) refers to screen.o(.bss) for .bss + screen.o(i.SCR_Send_RecordTime) refers to _printf_pad.o(.text) for _printf_pre_padding + screen.o(i.SCR_Send_RecordTime) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + screen.o(i.SCR_Send_RecordTime) refers to _printf_x.o(.ARM.Collect$$_printf_percent$$0000000C) for _printf_x + screen.o(i.SCR_Send_RecordTime) refers to _printf_hex_int_ll_ptr.o(.text) for _printf_longlong_hex + screen.o(i.SCR_Send_RecordTime) refers to __2sprintf.o(.text) for __2sprintf + screen.o(i.SCR_Send_RecordTime) refers to screen.o(i.USART2_printf) for USART2_printf + screen.o(i.SCR_Send_RecordTime) refers to screen.o(.bss) for .bss + screen.o(i.SCR_Send_Self_BasicInfo) refers to screen.o(i.USART2_printf) for USART2_printf + screen.o(i.SCR_Send_Self_BasicInfo) refers to fflt_clz.o(x$fpl$ffltu) for __aeabi_ui2f + screen.o(i.SCR_Send_Self_BasicInfo) refers to fdiv.o(x$fpl$fdiv) for __aeabi_fdiv + screen.o(i.SCR_Send_Self_BasicInfo) refers to f2d.o(x$fpl$f2d) for __aeabi_f2d + screen.o(i.SCR_Send_Self_BasicInfo) refers to fflt_clz.o(x$fpl$fflt) for __aeabi_i2f + screen.o(i.SCR_Send_Self_BasicInfo) refers to screen.o(i.SCR_ClearAlarm) for SCR_ClearAlarm + screen.o(i.SCR_Send_Self_BasicInfo) refers to screen.o(i.SCR_JumpToAlarm) for SCR_JumpToAlarm + screen.o(i.SCR_Send_Self_BasicInfo) refers to screen.o(i.SCR_ShowAlarm) for SCR_ShowAlarm + screen.o(i.SCR_Send_Self_BasicInfo) refers to global.o(.bss) for bmsMem + screen.o(i.SCR_Send_Self_BasicInfo) refers to adc.o(.data) for TemperatureAverage + screen.o(i.SCR_Send_Self_BasicInfo) refers to afe_sh3673520.o(.bss) for cellVol + screen.o(i.SCR_Send_Self_BasicInfo) refers to afe_sh3673520.o(.data) for bAlarmFlag + screen.o(i.SCR_Send_Self_BasicInfo) refers to screen.o(.data) for .data + screen.o(i.SCR_Send_Self_BasicInfo) refers to gasgauge.o(.data) for fcc + screen.o(i.SCR_Send_Self_BasicInfo) refers to dflt_clz.o(x$fpl$dfltu) for __aeabi_ui2d + screen.o(i.SCR_Send_Self_BasicInfo) refers to gpio.o(.data) for balancing + screen.o(i.SCR_Send_Slave_BasicInfo) refers to fflt_clz.o(x$fpl$ffltu) for __aeabi_ui2f + screen.o(i.SCR_Send_Slave_BasicInfo) refers to fdiv.o(x$fpl$fdiv) for __aeabi_fdiv + screen.o(i.SCR_Send_Slave_BasicInfo) refers to f2d.o(x$fpl$f2d) for __aeabi_f2d + screen.o(i.SCR_Send_Slave_BasicInfo) refers to screen.o(i.USART2_printf) for USART2_printf + screen.o(i.SCR_Send_Slave_BasicInfo) refers to fflt_clz.o(x$fpl$fflt) for __aeabi_i2f + screen.o(i.SCR_Send_Slave_BasicInfo) refers to screen.o(i.SCR_ShowAlarm_Slave) for SCR_ShowAlarm_Slave + screen.o(i.SCR_Send_Slave_BasicInfo) refers to global.o(.bss) for bmsMem_slave + screen.o(i.SCR_Send_Slave_BasicInfo) refers to global.o(.bss) for bmsMem + screen.o(i.SCR_Send_Slave_BasicInfo) refers to screen.o(.data) for .data + screen.o(i.SCR_Send_Slave_BasicInfo) refers to screen.o(i.SCR_ClearAlarm) for SCR_ClearAlarm + screen.o(i.SCR_Send_Slave_BasicInfo) refers to screen.o(i.SCR_JumpToAlarm) for SCR_JumpToAlarm + screen.o(i.SCR_Send_Slave_BasicInfo) refers to dflt_clz.o(x$fpl$dfltu) for __aeabi_ui2d + screen.o(i.SCR_Send_Slave_BasicInfo) refers to gasgauge.o(.data) for fcc + screen.o(i.SCR_Send_Slave_RecordBank) refers to screen.o(i.USART2_printf) for USART2_printf + screen.o(i.SCR_Send_Slave_RecordBank) refers to screen.o(i.Set_Row_Hide) for Set_Row_Hide + screen.o(i.SCR_Send_Slave_RecordBank) refers to screen.o(i.Send_Record_Blank) for Send_Record_Blank + screen.o(i.SCR_Send_Time) refers to _printf_pad.o(.text) for _printf_pre_padding + screen.o(i.SCR_Send_Time) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + screen.o(i.SCR_Send_Time) refers to _printf_x.o(.ARM.Collect$$_printf_percent$$0000000C) for _printf_x + screen.o(i.SCR_Send_Time) refers to _printf_hex_int_ll_ptr.o(.text) for _printf_longlong_hex + screen.o(i.SCR_Send_Time) refers to __2sprintf.o(.text) for __2sprintf + screen.o(i.SCR_Send_Time) refers to screen.o(i.USART2_printf) for USART2_printf + screen.o(i.SCR_Send_Time) refers to rtc.o(.data) for calendar + screen.o(i.SCR_Send_TimeCount) refers to screen.o(i.USART2_printf) for USART2_printf + screen.o(i.SCR_Send_TotalInfo) refers to dflt_clz.o(x$fpl$dfltu) for __aeabi_ui2d + screen.o(i.SCR_Send_TotalInfo) refers to dmul.o(x$fpl$dmul) for __aeabi_dmul + screen.o(i.SCR_Send_TotalInfo) refers to ddiv.o(x$fpl$ddiv) for __aeabi_ddiv + screen.o(i.SCR_Send_TotalInfo) refers to dfixu.o(x$fpl$dfixu) for __aeabi_d2uiz + screen.o(i.SCR_Send_TotalInfo) refers to fflt_clz.o(x$fpl$ffltu) for __aeabi_ui2f + screen.o(i.SCR_Send_TotalInfo) refers to fdiv.o(x$fpl$fdiv) for __aeabi_fdiv + screen.o(i.SCR_Send_TotalInfo) refers to f2d.o(x$fpl$f2d) for __aeabi_f2d + screen.o(i.SCR_Send_TotalInfo) refers to screen.o(i.USART2_printf) for USART2_printf + screen.o(i.SCR_Send_TotalInfo) refers to fflt_clz.o(x$fpl$fflt) for __aeabi_i2f + screen.o(i.SCR_Send_TotalInfo) refers to global.o(.bss) for bmsMem + screen.o(i.SCR_Send_TotalInfo) refers to can.o(.bss) for canMem + screen.o(i.SCR_Send_TotalInfo) refers to gasgauge.o(.data) for ncc_Ah + screen.o(i.SCR_Send_TotalInfo) refers to global.o(.data) for OnlineNum + screen.o(i.SCR_Send_VER) refers to screen.o(i.USART2_printf) for USART2_printf + screen.o(i.SCR_Send_VER) refers to global.o(.bss) for bmsMem + screen.o(i.SCR_Send_VER) refers to mbo26a.o(.bss) for PACK_SN + screen.o(i.SCR_Send_VER) refers to mbo26a.o(.data) for HardwareVersion + screen.o(i.SCR_ShowAlarm) refers to screen.o(i.USART2_printf) for USART2_printf + screen.o(i.SCR_ShowAlarm) refers to global.o(.bss) for bmsMem + screen.o(i.SCR_ShowAlarm_Slave) refers to screen.o(i.USART2_printf) for USART2_printf + screen.o(i.SCR_ShowAlarm_Slave) refers to global.o(.bss) for bmsMem_slave + screen.o(i.Screen_ClearBuf) refers to rt_memclr.o(.text) for __aeabi_memclr + screen.o(i.Screen_ClearBuf) refers to screen.o(.data) for .data + screen.o(i.Screen_ClearBuf) refers to screen.o(.bss) for .bss + screen.o(i.Screen_IQ_Transmit) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + screen.o(i.Screen_IQ_Transmit) refers to _printf_d.o(.ARM.Collect$$_printf_percent$$00000009) for _printf_d + screen.o(i.Screen_IQ_Transmit) refers to _printf_dec.o(.text) for _printf_int_dec + screen.o(i.Screen_IQ_Transmit) refers to screen.o(i.SCR_Send_Time) for SCR_Send_Time + screen.o(i.Screen_IQ_Transmit) refers to screen.o(i.SCR_Send_TotalInfo) for SCR_Send_TotalInfo + screen.o(i.Screen_IQ_Transmit) refers to screen.o(i.SCR_Send_Slave_BasicInfo) for SCR_Send_Slave_BasicInfo + screen.o(i.Screen_IQ_Transmit) refers to screen.o(i.SCR_Send_Self_BasicInfo) for SCR_Send_Self_BasicInfo + screen.o(i.Screen_IQ_Transmit) refers to screen.o(i.USART2_printf) for USART2_printf + screen.o(i.Screen_IQ_Transmit) refers to __2sprintf.o(.text) for __2sprintf + screen.o(i.Screen_IQ_Transmit) refers to screen.o(i.SCR_Send_Slave_RecordBank) for SCR_Send_Slave_RecordBank + screen.o(i.Screen_IQ_Transmit) refers to screen.o(i.SCR_Send_RecordInfo) for SCR_Send_RecordInfo + screen.o(i.Screen_IQ_Transmit) refers to flash.o(i.MEMORY_UpdateFlash) for MEMORY_UpdateFlash + screen.o(i.Screen_IQ_Transmit) refers to afe_sh3673520.o(i.MEMORY_UpdateAFE) for MEMORY_UpdateAFE + screen.o(i.Screen_IQ_Transmit) refers to screen.o(i.SCR_Send_VER) for SCR_Send_VER + screen.o(i.Screen_IQ_Transmit) refers to screen.o(i.SCR_DispProcotol) for SCR_DispProcotol + screen.o(i.Screen_IQ_Transmit) refers to global.o(i.CRC8_Cal) for CRC8_Cal + screen.o(i.Screen_IQ_Transmit) refers to global.o(.bss) for bmsMem + screen.o(i.Screen_IQ_Transmit) refers to screen.o(.data) for .data + screen.o(i.Screen_IQ_Transmit) refers to rtc.o(.data) for LSEErrFlag + screen.o(i.Screen_IQ_Transmit) refers to global.o(.data) for uvoff_Moni_Count + screen.o(i.Screen_IQ_Transmit) refers to rs485_modbus.o(.data) for assignAddr_State + screen.o(i.Screen_IQ_Transmit) refers to rs485_modbus_inverter.o(.data) for ConfigData_Index + screen.o(i.Screen_IQ_Transmit) refers to can.o(.bss) for canMem + screen.o(i.Screen_IQ_Transmit) refers to fflt_clz.o(x$fpl$ffltu) for __aeabi_ui2f + screen.o(i.Screen_IQ_Transmit) refers to fdiv.o(x$fpl$fdiv) for __aeabi_fdiv + screen.o(i.Screen_IQ_Transmit) refers to f2d.o(x$fpl$f2d) for __aeabi_f2d + screen.o(i.Screen_IT_Receive) refers to stm32f10x_usart.o(i.USART_ReceiveData) for USART_ReceiveData + screen.o(i.Screen_IT_Receive) refers to screen.o(i.Screen_ClearBuf) for Screen_ClearBuf + screen.o(i.Screen_IT_Receive) refers to screen.o(.data) for .data + screen.o(i.Screen_IT_Receive) refers to screen.o(.bss) for .bss + screen.o(i.Screen_IT_Update) refers to screen.o(i.findHexStr) for findHexStr + screen.o(i.Screen_IT_Update) refers to screen.o(i.USART2_printf) for USART2_printf + screen.o(i.Screen_IT_Update) refers to global.o(i.SLEEP_Refresh) for SLEEP_Refresh + screen.o(i.Screen_IT_Update) refers to global.o(i.SLEEP2_Refresh) for SLEEP2_Refresh + screen.o(i.Screen_IT_Update) refers to aeabi_memset.o(.text) for __aeabi_memset + screen.o(i.Screen_IT_Update) refers to i2c.o(i.EEPROM_WrMulByte) for EEPROM_WrMulByte + screen.o(i.Screen_IT_Update) refers to systick.o(i.delay_ms) for delay_ms + screen.o(i.Screen_IT_Update) refers to stm32f10x_rtc.o(i.RTC_GetCounter) for RTC_GetCounter + screen.o(i.Screen_IT_Update) refers to screen.o(.data) for .data + screen.o(i.Screen_IT_Update) refers to screen.o(.bss) for .bss + screen.o(i.Screen_IT_Update) refers to rtc.o(.data) for sleep_flag + screen.o(i.Screen_IT_Update) refers to soe.o(.bss) for soe + screen.o(i.Screen_IT_Update) refers to global.o(.bss) for bmsMem + screen.o(i.Screen_IT_Update) refers to global.o(.data) for uvoff_Moni_Count + screen.o(i.Screen_IT_Update) refers to can.o(i.uf_CAN1_Init) for uf_CAN1_Init + screen.o(i.Screen_IT_Update) refers to strstr.o(.text) for strstr + screen.o(i.Screen_IT_Update) refers to global.o(i.GetStr) for GetStr + screen.o(i.Screen_IT_Update) refers to i2c.o(i.EEPROM_RdMulByte) for EEPROM_RdMulByte + screen.o(i.Screen_IT_Update) refers to screen.o(i.Screen_ClearBuf) for Screen_ClearBuf + screen.o(i.Screen_IT_Update) refers to rs485_modbus.o(.data) for sdwa_WrAddr + screen.o(i.Screen_IT_Update) refers to gasgauge.o(.data) for ncc_Ah + screen.o(i.Screen_Init) refers to screen.o(i.Screen_ClearBuf) for Screen_ClearBuf + screen.o(i.Screen_Init) refers to uart.o(i.uf_UART2_Init) for uf_UART2_Init + screen.o(i.Screen_Init) refers to screen.o(.data) for .data + screen.o(i.Screen_TIM_Moni) refers to screen.o(i.Screen_Init) for Screen_Init + screen.o(i.Screen_TIM_Moni) refers to screen.o(.data) for .data + screen.o(i.Send_Record_Blank) refers to screen.o(i.Set_Row_Hide) for Set_Row_Hide + screen.o(i.Send_Record_Blank) refers to screen.o(i.USART2_printf) for USART2_printf + screen.o(i.Set_Row_Hide) refers to screen.o(i.USART2_printf) for USART2_printf + screen.o(i.USART2_printf) refers to vsnprintf.o(.text) for vsnprintf + screen.o(i.USART2_printf) refers to screen.o(.bss) for .bss + screen.o(i.findHexStr) refers to memcmp.o(.text) for memcmp + gasgauge.o(i.Cali_FCC_Moni) refers to i2c.o(i.EEPROM_WrMulByte) for EEPROM_WrMulByte + gasgauge.o(i.Cali_FCC_Moni) refers to systick.o(i.delay_ms) for delay_ms + gasgauge.o(i.Cali_FCC_Moni) refers to stm32f10x_rtc.o(i.RTC_GetCounter) for RTC_GetCounter + gasgauge.o(i.Cali_FCC_Moni) refers to gasgauge.o(.data) for .data + gasgauge.o(i.Cali_FCC_Moni) refers to rtc.o(.data) for LSEErrFlag + gasgauge.o(i.Cali_FCC_Moni) refers to global.o(.bss) for bmsMem + gasgauge.o(i.Cali_FCC_Moni) refers to global.o(.data) for fcc_Cali_Moni_Count + gasgauge.o(i.Cali_SOC_Moni) refers to gasgauge.o(.data) for .data + gasgauge.o(i.Cali_SOC_Moni) refers to global.o(.bss) for bmsMem + gasgauge.o(i.GaugeManage) refers to i2c.o(i.EEPROM_WrMulByte) for EEPROM_WrMulByte + gasgauge.o(i.GaugeManage) refers to systick.o(i.delay_ms) for delay_ms + gasgauge.o(i.GaugeManage) refers to gasgauge.o(i.Cali_FCC_Moni) for Cali_FCC_Moni + gasgauge.o(i.GaugeManage) refers to global.o(.bss) for bmsMem + gasgauge.o(i.GaugeManage) refers to status.o(.data) for cell_OV + gasgauge.o(i.GaugeManage) refers to gasgauge.o(.data) for .data + gasgauge.o(i.GaugeManage) refers to afe_sh3673520.o(.data) for bDSGING + gasgauge.o(i.GaugeManage) refers to rs485_modbus_inverter.o(.data) for cumuliCapClear_flag + gasgauge.o(i.GaugeManage) refers to rtc.o(.data) for sleep_flag + gasgauge.o(i.GaugeManage) refers to gpio.o(i.LED_ALARM_On) for LED_ALARM_On + gasgauge.o(i.GaugeManage) refers to gpio.o(i.LED_ALARM_Off) for LED_ALARM_Off + gasgauge.o(i.GaugeManage) refers to gpio.o(i.LED1_On) for LED1_On + gasgauge.o(i.GaugeManage) refers to gpio.o(i.LED2_Off) for LED2_Off + gasgauge.o(i.GaugeManage) refers to gpio.o(i.LED3_Off) for LED3_Off + gasgauge.o(i.GaugeManage) refers to gpio.o(i.LED4_Off) for LED4_Off + gasgauge.o(i.GaugeManage) refers to gpio.o(i.LED2_On) for LED2_On + gasgauge.o(i.GaugeManage) refers to gpio.o(i.LED3_On) for LED3_On + gasgauge.o(i.GaugeManage) refers to gpio.o(i.LED4_On) for LED4_On + gasgauge.o(i.GaugeManage) refers to gpio.o(i.LED1_Off) for LED1_Off + gasgauge.o(i.InitGasGauge) refers to i2c.o(i.EEPROM_RdMulByte) for EEPROM_RdMulByte + gasgauge.o(i.InitGasGauge) refers to i2c.o(i.EEPROM_WrMulByte) for EEPROM_WrMulByte + gasgauge.o(i.InitGasGauge) refers to systick.o(i.delay_ms) for delay_ms + gasgauge.o(i.InitGasGauge) refers to ocv.o(i.OCV_CaliSOC_DataWr) for OCV_CaliSOC_DataWr + gasgauge.o(i.InitGasGauge) refers to ocv.o(i.OCV_CaliSoc_dp) for OCV_CaliSoc_dp + gasgauge.o(i.InitGasGauge) refers to global.o(.bss) for bmsMem + gasgauge.o(i.InitGasGauge) refers to gasgauge.o(.data) for .data + soe.o(i.SOE_BkData) refers to i2c.o(i.EEPROM_WrMulByte) for EEPROM_WrMulByte + soe.o(i.SOE_BkData) refers to systick.o(i.delay_ms) for delay_ms + soe.o(i.SOE_BkData) refers to i2c.o(i.EEPROM_RdMulByte) for EEPROM_RdMulByte + soe.o(i.SOE_BkData) refers to global.o(.bss) for bmsMem + soe.o(i.SOE_BkData) refers to gasgauge.o(.data) for fcc + soe.o(i.SOE_BkData) refers to soe.o(.bss) for .bss + soe.o(i.SOE_BkData) refers to rtc.o(.data) for calendar + soe.o(i.SOE_BkData) refers to screen.o(.data) for scr_RdRecord_Flg + ocv.o(i.OCV_CaliSOC) refers to i2c.o(i.EEPROM_RdMulByte) for EEPROM_RdMulByte + ocv.o(i.OCV_CaliSOC) refers to stm32f10x_rtc.o(i.RTC_GetCounter) for RTC_GetCounter + ocv.o(i.OCV_CaliSOC) refers to i2c.o(i.EEPROM_WrMulByte) for EEPROM_WrMulByte + ocv.o(i.OCV_CaliSOC) refers to systick.o(i.delay_ms) for delay_ms + ocv.o(i.OCV_CaliSOC) refers to ocv.o(i.OCV_CaliSOC_DataWr) for OCV_CaliSOC_DataWr + ocv.o(i.OCV_CaliSOC) refers to ocv.o(i.OCV_CaliSoc_dp) for OCV_CaliSoc_dp + ocv.o(i.OCV_CaliSOC) refers to rtc.o(.data) for LSEErrFlag + ocv.o(i.OCV_CaliSOC) refers to ocv.o(.data) for .data + ocv.o(i.OCV_CaliSOC) refers to global.o(.bss) for paraMem + ocv.o(i.OCV_CaliSOC) refers to ocv.o(.bss) for .bss + ocv.o(i.OCV_CaliSOC) refers to adc.o(.data) for TemperatureAverage + ocv.o(i.OCV_CaliSOC) refers to gasgauge.o(.data) for fcc + ocv.o(i.OCV_CaliSOC_DataWr) refers to ocv.o(.bss) for .bss + ocv.o(i.OCV_CaliSOC_DataWr) refers to global.o(.bss) for paraMem + ocv.o(i.OCV_CaliSoc_dp) refers to global.o(.bss) for bmsMem + ocv.o(i.OCV_CaliSoc_dp) refers to ocv.o(.bss) for .bss + status.o(i.Release_CurAlarm) refers to global.o(.bss) for bmsMem + status.o(i.Release_CurAlarm) refers to status.o(.data) for .data + status.o(i.Release_CurAlarm) refers to afe_sh3673520.o(.data) for bCHGING + status.o(i.Release_CurProtect) refers to global.o(.bss) for bmsMem + status.o(i.Release_CurProtect) refers to status.o(.data) for .data + status.o(i.Release_CurProtect) refers to afe_sh3673520.o(.data) for sc_close_flag + status.o(i.Release_OVAlarm) refers to global.o(.bss) for bmsMem + status.o(i.Release_OVAlarm) refers to status.o(.data) for .data + status.o(i.Release_OVAlarm) refers to afe_sh3673520.o(.data) for cellVoltageMax + status.o(i.Release_OVProtect) refers to global.o(.bss) for bmsMem + status.o(i.Release_OVProtect) refers to status.o(.data) for .data + status.o(i.Release_OVProtect) refers to afe_sh3673520.o(.data) for cellVoltageMax + status.o(i.Release_UVAlarm) refers to global.o(.bss) for bmsMem + status.o(i.Release_UVAlarm) refers to status.o(.data) for .data + status.o(i.Release_UVAlarm) refers to afe_sh3673520.o(.data) for cellVoltageMin + status.o(i.Release_UVProtect) refers to global.o(.bss) for bmsMem + status.o(i.Release_UVProtect) refers to status.o(.data) for .data + status.o(i.Release_UVProtect) refers to afe_sh3673520.o(.data) for cellVoltageMin + status.o(i.Release_afeTAlarm) refers to global.o(.bss) for bmsMem + status.o(i.Release_afeTAlarm) refers to status.o(.data) for .data + status.o(i.Release_afeTProtect) refers to global.o(.bss) for bmsMem + status.o(i.Release_afeTProtect) refers to status.o(.data) for .data + status.o(i.Release_amTAlarm) refers to global.o(.bss) for paraMem + status.o(i.Release_amTAlarm) refers to status.o(.data) for .data + status.o(i.Release_amTProtect) refers to global.o(.bss) for paraMem + status.o(i.Release_amTProtect) refers to status.o(.data) for .data + status.o(i.Release_mcuTAlarm) refers to global.o(.bss) for bmsMem + status.o(i.Release_mcuTAlarm) refers to adc.o(.data) for TemperatureMax + status.o(i.Release_mcuTAlarm) refers to status.o(.data) for .data + status.o(i.Release_mcuTProtect) refers to global.o(.bss) for bmsMem + status.o(i.Release_mcuTProtect) refers to adc.o(.data) for TemperatureMax + status.o(i.Release_mcuTProtect) refers to status.o(.data) for .data + status.o(i.Trigger_CurAlarm) refers to global.o(.bss) for bmsMem + status.o(i.Trigger_CurAlarm) refers to status.o(.data) for .data + status.o(i.Trigger_CurAlarm) refers to afe_sh3673520.o(.data) for bCHGING + status.o(i.Trigger_CurProtect) refers to global.o(.bss) for bmsMem + status.o(i.Trigger_CurProtect) refers to status.o(.data) for .data + status.o(i.Trigger_CurProtect) refers to afe_sh3673520.o(.data) for bCHGING + status.o(i.Trigger_OVAlarm) refers to global.o(.bss) for bmsMem + status.o(i.Trigger_OVAlarm) refers to afe_sh3673520.o(.data) for bDSGING + status.o(i.Trigger_OVAlarm) refers to status.o(.data) for .data + status.o(i.Trigger_OVProtect) refers to global.o(.bss) for bmsMem + status.o(i.Trigger_OVProtect) refers to status.o(.data) for .data + status.o(i.Trigger_OVProtect) refers to status.o(.constdata) for .constdata + status.o(i.Trigger_OVProtect) refers to afe_sh3673520.o(.data) for bDSGING + status.o(i.Trigger_UVAlarm) refers to global.o(.bss) for bmsMem + status.o(i.Trigger_UVAlarm) refers to afe_sh3673520.o(.data) for bCHGING + status.o(i.Trigger_UVAlarm) refers to status.o(.data) for .data + status.o(i.Trigger_UVProtect) refers to global.o(.bss) for bmsMem + status.o(i.Trigger_UVProtect) refers to status.o(.data) for .data + status.o(i.Trigger_UVProtect) refers to status.o(.constdata) for .constdata + status.o(i.Trigger_UVProtect) refers to afe_sh3673520.o(.data) for bCHGING + status.o(i.Trigger_afeTAlarm) refers to global.o(.bss) for paraMem + status.o(i.Trigger_afeTAlarm) refers to status.o(.data) for .data + status.o(i.Trigger_afeTProtect) refers to global.o(.bss) for bmsMem + status.o(i.Trigger_afeTProtect) refers to status.o(.data) for .data + status.o(i.Trigger_amTAlarm) refers to global.o(.bss) for paraMem + status.o(i.Trigger_amTAlarm) refers to status.o(.data) for .data + status.o(i.Trigger_amTProtect) refers to global.o(.bss) for paraMem + status.o(i.Trigger_amTProtect) refers to status.o(.data) for .data + status.o(i.Trigger_mcuTAlarm) refers to global.o(.bss) for paraMem + status.o(i.Trigger_mcuTAlarm) refers to adc.o(.data) for TemperatureMax + status.o(i.Trigger_mcuTAlarm) refers to status.o(.data) for .data + status.o(i.Trigger_mcuTProtect) refers to global.o(.bss) for bmsMem + status.o(i.Trigger_mcuTProtect) refers to adc.o(.data) for TemperatureMax + status.o(i.Trigger_mcuTProtect) refers to status.o(.data) for .data + mbo26a.o(i.BLE_CheckName) refers to mbo26a.o(i.BLE_ClearBuf) for BLE_ClearBuf + mbo26a.o(i.BLE_CheckName) refers to mbo26a.o(i.BLE_printf) for BLE_printf + mbo26a.o(i.BLE_CheckName) refers to systick.o(i.delay_ms) for delay_ms + mbo26a.o(i.BLE_CheckName) refers to strstr.o(.text) for strstr + mbo26a.o(i.BLE_CheckName) refers to mbo26a.o(i.BLE_Reset) for BLE_Reset + mbo26a.o(i.BLE_CheckName) refers to mbo26a.o(.bss) for .bss + mbo26a.o(i.BLE_CheckName) refers to mbo26a.o(.data) for .data + mbo26a.o(i.BLE_ClearBuf) refers to rt_memclr_w.o(.text) for __aeabi_memclr4 + mbo26a.o(i.BLE_ClearBuf) refers to mbo26a.o(.data) for .data + mbo26a.o(i.BLE_ClearBuf) refers to mbo26a.o(.bss) for .bss + mbo26a.o(i.BLE_ClearFlg) refers to mbo26a.o(.data) for .data + mbo26a.o(i.BLE_GETPARA) refers to strstr.o(.text) for strstr + mbo26a.o(i.BLE_GETPARA) refers to strlen.o(.text) for strlen + mbo26a.o(i.BLE_GETPARA) refers to strchr.o(.text) for strchr + mbo26a.o(i.BLE_GETPARA) refers to strncpy.o(.text) for strncpy + mbo26a.o(i.BLE_GETPARA) refers to mbo26a.o(.bss) for .bss + mbo26a.o(i.BLE_GETPARA) refers to mbo26a.o(.data) for .data + mbo26a.o(i.BLE_GETPARA) refers to screen.o(.data) for protocol + mbo26a.o(i.BLE_IO_Init) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) for RCC_APB2PeriphClockCmd + mbo26a.o(i.BLE_IO_Init) refers to stm32f10x_gpio.o(i.GPIO_Init) for GPIO_Init + mbo26a.o(i.BLE_IO_Init) refers to stm32f10x_gpio.o(i.GPIO_ResetBits) for GPIO_ResetBits + mbo26a.o(i.BLE_IQ_Transmit) refers to mbo26a.o(i.BLE_printf) for BLE_printf + mbo26a.o(i.BLE_IQ_Transmit) refers to mbo26a.o(i.BLE_Reset) for BLE_Reset + mbo26a.o(i.BLE_IQ_Transmit) refers to mbo26a.o(i.BLE_CheckName) for BLE_CheckName + mbo26a.o(i.BLE_IQ_Transmit) refers to fflt_clz.o(x$fpl$fflt) for __aeabi_i2f + mbo26a.o(i.BLE_IQ_Transmit) refers to fdiv.o(x$fpl$fdiv) for __aeabi_fdiv + mbo26a.o(i.BLE_IQ_Transmit) refers to f2d.o(x$fpl$f2d) for __aeabi_f2d + mbo26a.o(i.BLE_IQ_Transmit) refers to mbo26a.o(.data) for .data + mbo26a.o(i.BLE_IQ_Transmit) refers to rs485_modbus_inverter.o(.data) for protocolStrings + mbo26a.o(i.BLE_IQ_Transmit) refers to global.o(.bss) for bmsMem + mbo26a.o(i.BLE_IQ_Transmit) refers to afe_sh3673520.o(.bss) for cellVol + mbo26a.o(i.BLE_IQ_Transmit) refers to mbo26a.o(.bss) for .bss + mbo26a.o(i.BLE_IQ_Transmit) refers to afe_sh3673520.o(.data) for cellVoltageMax + mbo26a.o(i.BLE_IQ_Transmit) refers to screen.o(.data) for protocol + mbo26a.o(i.BLE_IQ_Update) refers to mbo26a.o(i.BLE_SetBaud) for BLE_SetBaud + mbo26a.o(i.BLE_IQ_Update) refers to mbo26a.o(i.BLE_CheckName) for BLE_CheckName + mbo26a.o(i.BLE_IQ_Update) refers to mbo26a.o(.data) for .data + mbo26a.o(i.BLE_IQ_Update) refers to global.o(.bss) for bmsMem + mbo26a.o(i.BLE_IQ_Update) refers to mbo26a.o(.bss) for .bss + mbo26a.o(i.BLE_IT_Receive) refers to stm32f10x_usart.o(i.USART_ReceiveData) for USART_ReceiveData + mbo26a.o(i.BLE_IT_Receive) refers to mbo26a.o(i.BLE_ClearBuf) for BLE_ClearBuf + mbo26a.o(i.BLE_IT_Receive) refers to mbo26a.o(.data) for .data + mbo26a.o(i.BLE_IT_Receive) refers to mbo26a.o(.bss) for .bss + mbo26a.o(i.BLE_IT_Update) refers to strstr.o(.text) for strstr + mbo26a.o(i.BLE_IT_Update) refers to mbo26a.o(i.BLE_ClearBuf) for BLE_ClearBuf + mbo26a.o(i.BLE_IT_Update) refers to mbo26a.o(i.BLE_SetBaud) for BLE_SetBaud + mbo26a.o(i.BLE_IT_Update) refers to mbo26a.o(i.BLE_CheckName) for BLE_CheckName + mbo26a.o(i.BLE_IT_Update) refers to mbo26a.o(i.BLE_PUTSRVC) for BLE_PUTSRVC + mbo26a.o(i.BLE_IT_Update) refers to mbo26a.o(i.BLE_SETPARA) for BLE_SETPARA + mbo26a.o(i.BLE_IT_Update) refers to mbo26a.o(i.BLE_GETPARA) for BLE_GETPARA + mbo26a.o(i.BLE_IT_Update) refers to mbo26a.o(.data) for .data + mbo26a.o(i.BLE_IT_Update) refers to mbo26a.o(.bss) for .bss + mbo26a.o(i.BLE_Init) refers to mbo26a.o(i.BLE_ClearFlg) for BLE_ClearFlg + mbo26a.o(i.BLE_Init) refers to mbo26a.o(i.BLE_ClearBuf) for BLE_ClearBuf + mbo26a.o(i.BLE_Init) refers to uart.o(i.uf_UART4_Init) for uf_UART4_Init + mbo26a.o(i.BLE_Init) refers to mbo26a.o(.data) for .data + mbo26a.o(i.BLE_PUTSRVC) refers to strstr.o(.text) for strstr + mbo26a.o(i.BLE_PUTSRVC) refers to strlen.o(.text) for strlen + mbo26a.o(i.BLE_PUTSRVC) refers to strchr.o(.text) for strchr + mbo26a.o(i.BLE_PUTSRVC) refers to strncpy.o(.text) for strncpy + mbo26a.o(i.BLE_PUTSRVC) refers to stm32f10x_rtc.o(i.RTC_GetCounter) for RTC_GetCounter + mbo26a.o(i.BLE_PUTSRVC) refers to mbo26a.o(.bss) for .bss + mbo26a.o(i.BLE_PUTSRVC) refers to mbo26a.o(.data) for .data + mbo26a.o(i.BLE_PUTSRVC) refers to global.o(.bss) for bmsMem + mbo26a.o(i.BLE_PUTSRVC) refers to rtc.o(.data) for LSEErrFlag + mbo26a.o(i.BLE_PUTSRVC) refers to global.o(.data) for uvoff_Moni_Count + mbo26a.o(i.BLE_Reset) refers to mbo26a.o(i.BLE_printf) for BLE_printf + mbo26a.o(i.BLE_Reset) refers to mbo26a.o(.data) for .data + mbo26a.o(i.BLE_SETPARA) refers to _scanf_int.o(.text) for _scanf_int + mbo26a.o(i.BLE_SETPARA) refers to strstr.o(.text) for strstr + mbo26a.o(i.BLE_SETPARA) refers to strlen.o(.text) for strlen + mbo26a.o(i.BLE_SETPARA) refers to strchr.o(.text) for strchr + mbo26a.o(i.BLE_SETPARA) refers to strncpy.o(.text) for strncpy + mbo26a.o(i.BLE_SETPARA) refers to global.o(i.GetStr) for GetStr + mbo26a.o(i.BLE_SETPARA) refers to __0sscanf.o(.text) for __0sscanf + mbo26a.o(i.BLE_SETPARA) refers to i2c.o(i.EEPROM_WrMulByte) for EEPROM_WrMulByte + mbo26a.o(i.BLE_SETPARA) refers to systick.o(i.delay_ms) for delay_ms + mbo26a.o(i.BLE_SETPARA) refers to can.o(i.uf_CAN1_Init) for uf_CAN1_Init + mbo26a.o(i.BLE_SETPARA) refers to mbo26a.o(.bss) for .bss + mbo26a.o(i.BLE_SETPARA) refers to mbo26a.o(.data) for .data + mbo26a.o(i.BLE_SETPARA) refers to screen.o(.data) for protocol + mbo26a.o(i.BLE_SetBaud) refers to mbo26a.o(i.BLE_printf) for BLE_printf + mbo26a.o(i.BLE_SetBaud) refers to systick.o(i.delay_ms) for delay_ms + mbo26a.o(i.BLE_SetBaud) refers to uart.o(i.uf_UART4_Init) for uf_UART4_Init + mbo26a.o(i.BLE_TIM_Moni) refers to mbo26a.o(i.BLE_Init) for BLE_Init + mbo26a.o(i.BLE_TIM_Moni) refers to mbo26a.o(.data) for .data + mbo26a.o(i.BLE_WriteName) refers to mbo26a.o(i.BLE_CheckName) for BLE_CheckName + mbo26a.o(i.BLE_printf) refers to vsnprintf.o(.text) for vsnprintf + mbo26a.o(i.BLE_printf) refers to mbo26a.o(.bss) for .bss + mbo26a.o(.data) refers to mbo26a.o(.conststring) for .conststring + lbs_transmit.o(i.gcj02_to_wgs84) refers to dleqf.o(x$fpl$dleqf) for __aeabi_cdcmple + lbs_transmit.o(i.gcj02_to_wgs84) refers to drleqf.o(x$fpl$drleqf) for __aeabi_cdrcmple + lbs_transmit.o(i.gcj02_to_wgs84) refers to daddsub_clz.o(x$fpl$dsub) for __aeabi_dsub + lbs_transmit.o(i.gcj02_to_wgs84) refers to lbs_transmit.o(i.transform_lat) for transform_lat + lbs_transmit.o(i.gcj02_to_wgs84) refers to lbs_transmit.o(i.transform_lon) for transform_lon + lbs_transmit.o(i.gcj02_to_wgs84) refers to dmul.o(x$fpl$dmul) for __aeabi_dmul + lbs_transmit.o(i.gcj02_to_wgs84) refers to ddiv.o(x$fpl$ddiv) for __aeabi_ddiv + lbs_transmit.o(i.gcj02_to_wgs84) refers to sin.o(i.sin) for sin + lbs_transmit.o(i.gcj02_to_wgs84) refers to daddsub_clz.o(x$fpl$drsb) for __aeabi_drsub + lbs_transmit.o(i.gcj02_to_wgs84) refers to sqrt.o(i.sqrt) for sqrt + lbs_transmit.o(i.gcj02_to_wgs84) refers to cos.o(i.cos) for cos + lbs_transmit.o(i.gcj02_to_wgs84) refers to daddsub_clz.o(x$fpl$dadd) for __aeabi_dadd + lbs_transmit.o(i.transform_lat) refers to sqrt.o(i.sqrt) for sqrt + lbs_transmit.o(i.transform_lat) refers to dmul.o(x$fpl$dmul) for __aeabi_dmul + lbs_transmit.o(i.transform_lat) refers to scalbn.o(x$fpl$scalbn) for __ARM_scalbn + lbs_transmit.o(i.transform_lat) refers to daddsub_clz.o(x$fpl$dadd) for __aeabi_dadd + lbs_transmit.o(i.transform_lat) refers to sin.o(i.sin) for sin + lbs_transmit.o(i.transform_lat) refers to ddiv.o(x$fpl$ddiv) for __aeabi_ddiv + lbs_transmit.o(i.transform_lon) refers to sqrt.o(i.sqrt) for sqrt + lbs_transmit.o(i.transform_lon) refers to dmul.o(x$fpl$dmul) for __aeabi_dmul + lbs_transmit.o(i.transform_lon) refers to scalbn.o(x$fpl$scalbn) for __ARM_scalbn + lbs_transmit.o(i.transform_lon) refers to daddsub_clz.o(x$fpl$dadd) for __aeabi_dadd + lbs_transmit.o(i.transform_lon) refers to sin.o(i.sin) for sin + lbs_transmit.o(i.transform_lon) refers to ddiv.o(x$fpl$ddiv) for __aeabi_ddiv + stm32f10x_adc.o(i.ADC_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphResetCmd) for RCC_APB2PeriphResetCmd + stm32f10x_bkp.o(i.BKP_DeInit) refers to stm32f10x_rcc.o(i.RCC_BackupResetCmd) for RCC_BackupResetCmd + stm32f10x_can.o(i.CAN_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphResetCmd) for RCC_APB1PeriphResetCmd + stm32f10x_can.o(i.CAN_GetITStatus) refers to stm32f10x_can.o(i.CheckITStatus) for CheckITStatus + stm32f10x_cec.o(i.CEC_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphResetCmd) for RCC_APB1PeriphResetCmd + stm32f10x_dac.o(i.DAC_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphResetCmd) for RCC_APB1PeriphResetCmd + stm32f10x_flash.o(i.FLASH_EnableWriteProtection) refers to stm32f10x_flash.o(i.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation + stm32f10x_flash.o(i.FLASH_EraseAllBank1Pages) refers to stm32f10x_flash.o(i.FLASH_WaitForLastBank1Operation) for FLASH_WaitForLastBank1Operation + stm32f10x_flash.o(i.FLASH_EraseAllPages) refers to stm32f10x_flash.o(i.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation + stm32f10x_flash.o(i.FLASH_EraseOptionBytes) refers to stm32f10x_flash.o(i.FLASH_GetReadOutProtectionStatus) for FLASH_GetReadOutProtectionStatus + stm32f10x_flash.o(i.FLASH_EraseOptionBytes) refers to stm32f10x_flash.o(i.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation + stm32f10x_flash.o(i.FLASH_ErasePage) refers to stm32f10x_flash.o(i.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation + stm32f10x_flash.o(i.FLASH_ProgramHalfWord) refers to stm32f10x_flash.o(i.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation + stm32f10x_flash.o(i.FLASH_ProgramOptionByteData) refers to stm32f10x_flash.o(i.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation + stm32f10x_flash.o(i.FLASH_ProgramWord) refers to stm32f10x_flash.o(i.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation + stm32f10x_flash.o(i.FLASH_ReadOutProtection) refers to stm32f10x_flash.o(i.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation + stm32f10x_flash.o(i.FLASH_UserOptionByteConfig) refers to stm32f10x_flash.o(i.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation + stm32f10x_flash.o(i.FLASH_WaitForLastBank1Operation) refers to stm32f10x_flash.o(i.FLASH_GetBank1Status) for FLASH_GetBank1Status + stm32f10x_flash.o(i.FLASH_WaitForLastOperation) refers to stm32f10x_flash.o(i.FLASH_GetBank1Status) for FLASH_GetBank1Status + stm32f10x_gpio.o(i.GPIO_AFIODeInit) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphResetCmd) for RCC_APB2PeriphResetCmd + stm32f10x_gpio.o(i.GPIO_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphResetCmd) for RCC_APB2PeriphResetCmd + stm32f10x_i2c.o(i.I2C_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphResetCmd) for RCC_APB1PeriphResetCmd + stm32f10x_i2c.o(i.I2C_Init) refers to stm32f10x_rcc.o(i.RCC_GetClocksFreq) for RCC_GetClocksFreq + stm32f10x_pwr.o(i.PWR_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphResetCmd) for RCC_APB1PeriphResetCmd + stm32f10x_rcc.o(i.RCC_GetClocksFreq) refers to stm32f10x_rcc.o(.data) for .data + stm32f10x_rcc.o(i.RCC_WaitForHSEStartUp) refers to stm32f10x_rcc.o(i.RCC_GetFlagStatus) for RCC_GetFlagStatus + stm32f10x_rtc.o(i.RTC_SetAlarm) refers to stm32f10x_rtc.o(i.RTC_EnterConfigMode) for RTC_EnterConfigMode + stm32f10x_rtc.o(i.RTC_SetAlarm) refers to stm32f10x_rtc.o(i.RTC_ExitConfigMode) for RTC_ExitConfigMode + stm32f10x_rtc.o(i.RTC_SetCounter) refers to stm32f10x_rtc.o(i.RTC_EnterConfigMode) for RTC_EnterConfigMode + stm32f10x_rtc.o(i.RTC_SetCounter) refers to stm32f10x_rtc.o(i.RTC_ExitConfigMode) for RTC_ExitConfigMode + stm32f10x_rtc.o(i.RTC_SetPrescaler) refers to stm32f10x_rtc.o(i.RTC_EnterConfigMode) for RTC_EnterConfigMode + stm32f10x_rtc.o(i.RTC_SetPrescaler) refers to stm32f10x_rtc.o(i.RTC_ExitConfigMode) for RTC_ExitConfigMode + stm32f10x_spi.o(i.I2S_Init) refers to stm32f10x_rcc.o(i.RCC_GetClocksFreq) for RCC_GetClocksFreq + stm32f10x_spi.o(i.SPI_I2S_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphResetCmd) for RCC_APB2PeriphResetCmd + stm32f10x_spi.o(i.SPI_I2S_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphResetCmd) for RCC_APB1PeriphResetCmd + stm32f10x_tim.o(i.TIM_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphResetCmd) for RCC_APB1PeriphResetCmd + stm32f10x_tim.o(i.TIM_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphResetCmd) for RCC_APB2PeriphResetCmd + stm32f10x_tim.o(i.TIM_ETRClockMode1Config) refers to stm32f10x_tim.o(i.TIM_ETRConfig) for TIM_ETRConfig + stm32f10x_tim.o(i.TIM_ETRClockMode2Config) refers to stm32f10x_tim.o(i.TIM_ETRConfig) for TIM_ETRConfig + stm32f10x_tim.o(i.TIM_ICInit) refers to stm32f10x_tim.o(i.TI1_Config) for TI1_Config + stm32f10x_tim.o(i.TIM_ICInit) refers to stm32f10x_tim.o(i.TIM_SetIC1Prescaler) for TIM_SetIC1Prescaler + stm32f10x_tim.o(i.TIM_ICInit) refers to stm32f10x_tim.o(i.TI2_Config) for TI2_Config + stm32f10x_tim.o(i.TIM_ICInit) refers to stm32f10x_tim.o(i.TIM_SetIC2Prescaler) for TIM_SetIC2Prescaler + stm32f10x_tim.o(i.TIM_ICInit) refers to stm32f10x_tim.o(i.TIM_SetIC3Prescaler) for TIM_SetIC3Prescaler + stm32f10x_tim.o(i.TIM_ICInit) refers to stm32f10x_tim.o(i.TIM_SetIC4Prescaler) for TIM_SetIC4Prescaler + stm32f10x_tim.o(i.TIM_ITRxExternalClockConfig) refers to stm32f10x_tim.o(i.TIM_SelectInputTrigger) for TIM_SelectInputTrigger + stm32f10x_tim.o(i.TIM_PWMIConfig) refers to stm32f10x_tim.o(i.TI2_Config) for TI2_Config + stm32f10x_tim.o(i.TIM_PWMIConfig) refers to stm32f10x_tim.o(i.TIM_SetIC2Prescaler) for TIM_SetIC2Prescaler + stm32f10x_tim.o(i.TIM_PWMIConfig) refers to stm32f10x_tim.o(i.TI1_Config) for TI1_Config + stm32f10x_tim.o(i.TIM_PWMIConfig) refers to stm32f10x_tim.o(i.TIM_SetIC1Prescaler) for TIM_SetIC1Prescaler + stm32f10x_tim.o(i.TIM_TIxExternalClockConfig) refers to stm32f10x_tim.o(i.TI1_Config) for TI1_Config + stm32f10x_tim.o(i.TIM_TIxExternalClockConfig) refers to stm32f10x_tim.o(i.TIM_SelectInputTrigger) for TIM_SelectInputTrigger + stm32f10x_tim.o(i.TIM_TIxExternalClockConfig) refers to stm32f10x_tim.o(i.TI2_Config) for TI2_Config + stm32f10x_usart.o(i.USART_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB2PeriphResetCmd) for RCC_APB2PeriphResetCmd + stm32f10x_usart.o(i.USART_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphResetCmd) for RCC_APB1PeriphResetCmd + stm32f10x_usart.o(i.USART_Init) refers to stm32f10x_rcc.o(i.RCC_GetClocksFreq) for RCC_GetClocksFreq + stm32f10x_wwdg.o(i.WWDG_DeInit) refers to stm32f10x_rcc.o(i.RCC_APB1PeriphResetCmd) for RCC_APB1PeriphResetCmd + protocolswitch_p1.o(i.CAN_Protocol_Afore) refers to can.o(i.CAN1_SendData) for CAN1_SendData + protocolswitch_p1.o(i.CAN_Protocol_Afore) refers to can.o(.bss) for canMem + protocolswitch_p1.o(i.CAN_Protocol_Afore) refers to can.o(.data) for CAN_SendCount + protocolswitch_p1.o(i.CAN_Protocol_Afore) refers to global.o(.bss) for bmsMem + protocolswitch_p1.o(i.CAN_Protocol_Afore) refers to rs485_modbus.o(.data) for RequestFlag + protocolswitch_p1.o(i.CAN_Protocol_Afore) refers to rs485_modbus.o(.data) for chg_forbidFlg + protocolswitch_p1.o(i.CAN_Protocol_Afore) refers to rs485_modbus.o(.data) for dsg_forbidFlg + protocolswitch_p1.o(i.CAN_Protocol_Afore) refers to rs485_modbus.o(.data) for chg_forceFlg + protocolswitch_p1.o(i.CAN_Protocol_Afore) refers to global.o(.data) for OnlineNum + protocolswitch_p1.o(i.CAN_Protocol_Afore) refers to rs485_modbus.o(.data) for chg_curlimitFlg + protocolswitch_p1.o(i.CAN_Protocol_Aiswei) refers to can.o(i.CAN1_SendData) for CAN1_SendData + protocolswitch_p1.o(i.CAN_Protocol_Aiswei) refers to can.o(.bss) for canMem + protocolswitch_p1.o(i.CAN_Protocol_Aiswei) refers to can.o(.data) for CAN_SendCount + protocolswitch_p1.o(i.CAN_Protocol_Aiswei) refers to global.o(.data) for OnlineNum + protocolswitch_p1.o(i.CAN_Protocol_Aiswei) refers to rs485_modbus.o(.data) for chg_forbidFlg + protocolswitch_p1.o(i.CAN_Protocol_Aiswei) refers to rs485_modbus.o(.data) for dsg_forbidFlg + protocolswitch_p1.o(i.CAN_Protocol_Aiswei) refers to global.o(.bss) for bmsMem + protocolswitch_p1.o(i.CAN_Protocol_Aiswei) refers to rs485_modbus.o(.data) for chg_curlimitFlg + protocolswitch_p1.o(i.CAN_Protocol_Aiswei) refers to rs485_modbus.o(.data) for RequestFlag + protocolswitch_p1.o(i.CAN_Protocol_Aiswei) refers to rs485_modbus.o(.data) for chg_forceFlg + protocolswitch_p1.o(i.CAN_Protocol_Aiswei) refers to gasgauge.o(.data) for ncc_Ah + protocolswitch_p1.o(i.CAN_Protocol_Deye) refers to can.o(i.CAN1_SendData) for CAN1_SendData + protocolswitch_p1.o(i.CAN_Protocol_Deye) refers to can.o(.bss) for canMem + protocolswitch_p1.o(i.CAN_Protocol_Deye) refers to protocolswitch_p1.o(.data) for .data + protocolswitch_p1.o(i.CAN_Protocol_Deye) refers to can.o(.data) for CAN_SendCount + protocolswitch_p1.o(i.CAN_Protocol_Deye) refers to global.o(.bss) for bmsMem + protocolswitch_p1.o(i.CAN_Protocol_Deye) refers to rs485_modbus.o(.data) for chg_forbidFlg + protocolswitch_p1.o(i.CAN_Protocol_Deye) refers to global.o(.data) for OnlineNum + protocolswitch_p1.o(i.CAN_Protocol_Deye) refers to rs485_modbus.o(.data) for chg_curlimitFlg + protocolswitch_p1.o(i.CAN_Protocol_Deye) refers to rs485_modbus.o(.data) for RequestFlag + protocolswitch_p1.o(i.CAN_Protocol_GoodWe) refers to can.o(i.CAN1_SendData) for CAN1_SendData + protocolswitch_p1.o(i.CAN_Protocol_GoodWe) refers to can.o(.bss) for canMem + protocolswitch_p1.o(i.CAN_Protocol_GoodWe) refers to can.o(.data) for CAN_SendCount + protocolswitch_p1.o(i.CAN_Protocol_GoodWe) refers to rs485_modbus.o(.data) for chg_forbidFlg + protocolswitch_p1.o(i.CAN_Protocol_GoodWe) refers to rs485_modbus.o(.data) for dsg_forbidFlg + protocolswitch_p1.o(i.CAN_Protocol_GoodWe) refers to global.o(.bss) for bmsMem + protocolswitch_p1.o(i.CAN_Protocol_GoodWe) refers to global.o(.data) for OnlineNum + protocolswitch_p1.o(i.CAN_Protocol_GoodWe) refers to rs485_modbus.o(.data) for chg_curlimitFlg + protocolswitch_p1.o(i.CAN_Protocol_GoodWe) refers to rs485_modbus.o(.data) for RequestFlag + protocolswitch_p1.o(i.CAN_Protocol_GoodWe) refers to rs485_modbus.o(.data) for chg_forceFlg + protocolswitch_p1.o(i.CAN_Protocol_Growatt) refers to can.o(i.CAN1_SendData) for CAN1_SendData + protocolswitch_p1.o(i.CAN_Protocol_Growatt) refers to can.o(.bss) for canMem + protocolswitch_p1.o(i.CAN_Protocol_Growatt) refers to global.o(.bss) for bmsMem + protocolswitch_p1.o(i.CAN_Protocol_Growatt) refers to afe_sh3673520.o(.data) for bCHGING + protocolswitch_p1.o(i.CAN_Protocol_Growatt) refers to can.o(.data) for CAN_SendCount + protocolswitch_p1.o(i.CAN_Protocol_Growatt) refers to global.o(.data) for OnlineNum + protocolswitch_p1.o(i.CAN_Protocol_Growatt) refers to rs485_modbus.o(.data) for chg_forbidFlg + protocolswitch_p1.o(i.CAN_Protocol_Growatt) refers to rs485_modbus.o(.data) for dsg_forbidFlg + protocolswitch_p1.o(i.CAN_Protocol_Growatt) refers to gasgauge.o(.data) for fcc_Ah + protocolswitch_p1.o(i.CAN_Protocol_Growatt) refers to rs485_modbus.o(.data) for RequestFlag + protocolswitch_p1.o(i.CAN_Protocol_Growatt) refers to rs485_modbus.o(.data) for chg_forceFlg + protocolswitch_p1.o(i.CAN_Protocol_MUST) refers to can.o(i.CAN1_SendData) for CAN1_SendData + protocolswitch_p1.o(i.CAN_Protocol_MUST) refers to can.o(.bss) for canMem + protocolswitch_p1.o(i.CAN_Protocol_MUST) refers to can.o(.data) for CAN_SendCount + protocolswitch_p1.o(i.CAN_Protocol_MUST) refers to global.o(.bss) for bmsMem + protocolswitch_p1.o(i.CAN_Protocol_MUST) refers to rs485_modbus.o(.data) for chg_forbidFlg + protocolswitch_p1.o(i.CAN_Protocol_MUST) refers to rs485_modbus.o(.data) for dsg_forbidFlg + protocolswitch_p1.o(i.CAN_Protocol_MUST) refers to rs485_modbus.o(.data) for RequestFlag + protocolswitch_p1.o(i.CAN_Protocol_MUST) refers to global.o(.data) for OnlineNum + protocolswitch_p1.o(i.CAN_Protocol_MUST) refers to rs485_modbus.o(.data) for chg_curlimitFlg + protocolswitch_p1.o(i.CAN_Protocol_MUST) refers to rs485_modbus.o(.data) for chg_forceFlg + protocolswitch_p1.o(i.CAN_Protocol_Megarevo) refers to can.o(i.CAN1_SendData) for CAN1_SendData + protocolswitch_p1.o(i.CAN_Protocol_Megarevo) refers to can.o(.bss) for canMem + protocolswitch_p1.o(i.CAN_Protocol_Megarevo) refers to can.o(.data) for CAN_SendCount + protocolswitch_p1.o(i.CAN_Protocol_Megarevo) refers to rs485_modbus.o(.data) for chg_forbidFlg + protocolswitch_p1.o(i.CAN_Protocol_Megarevo) refers to rs485_modbus.o(.data) for dsg_forbidFlg + protocolswitch_p1.o(i.CAN_Protocol_Megarevo) refers to global.o(.bss) for bmsMem + protocolswitch_p1.o(i.CAN_Protocol_Megarevo) refers to global.o(.data) for OnlineNum + protocolswitch_p1.o(i.CAN_Protocol_Megarevo) refers to rs485_modbus.o(.data) for chg_curlimitFlg + protocolswitch_p1.o(i.CAN_Protocol_Megarevo) refers to rs485_modbus.o(.data) for RequestFlag + protocolswitch_p1.o(i.CAN_Protocol_Megarevo) refers to rs485_modbus.o(.data) for chg_forceFlg + protocolswitch_p1.o(i.CAN_Protocol_Pylon) refers to can.o(i.CAN1_SendData) for CAN1_SendData + protocolswitch_p1.o(i.CAN_Protocol_Pylon) refers to can.o(.bss) for canMem + protocolswitch_p1.o(i.CAN_Protocol_Pylon) refers to can.o(.data) for CAN_SendCount + protocolswitch_p1.o(i.CAN_Protocol_Pylon) refers to global.o(.data) for OnlineNum + protocolswitch_p1.o(i.CAN_Protocol_Pylon) refers to global.o(.bss) for bmsMem + protocolswitch_p1.o(i.CAN_Protocol_Pylon) refers to rs485_modbus.o(.data) for chg_forbidFlg + protocolswitch_p1.o(i.CAN_Protocol_Pylon) refers to rs485_modbus.o(.data) for chg_curlimitFlg + protocolswitch_p1.o(i.CAN_Protocol_Pylon) refers to rs485_modbus.o(.data) for dsg_forbidFlg + protocolswitch_p1.o(i.CAN_Protocol_Pylon) refers to rs485_modbus.o(.data) for RequestFlag + protocolswitch_p1.o(i.CAN_Protocol_Pylon) refers to rs485_modbus.o(.data) for chg_forceFlg + protocolswitch_p1.o(i.CAN_Protocol_Pylon) refers to gasgauge.o(.data) for ncc_Ah + protocolswitch_p1.o(i.CAN_Protocol_SolArk) refers to can.o(i.CAN1_SendData) for CAN1_SendData + protocolswitch_p1.o(i.CAN_Protocol_SolArk) refers to can.o(.bss) for canMem + protocolswitch_p1.o(i.CAN_Protocol_SolArk) refers to can.o(.data) for CAN_SendCount + protocolswitch_p1.o(i.CAN_Protocol_SolArk) refers to global.o(.data) for OnlineNum + protocolswitch_p1.o(i.CAN_Protocol_SolArk) refers to rs485_modbus.o(.data) for chg_forbidFlg + protocolswitch_p1.o(i.CAN_Protocol_SolArk) refers to rs485_modbus.o(.data) for dsg_forbidFlg + protocolswitch_p1.o(i.CAN_Protocol_SolArk) refers to global.o(.bss) for bmsMem + protocolswitch_p1.o(i.CAN_Protocol_SolArk) refers to rs485_modbus.o(.data) for chg_curlimitFlg + protocolswitch_p1.o(i.CAN_Protocol_SolArk) refers to rs485_modbus.o(.data) for RequestFlag + protocolswitch_p1.o(i.CAN_Protocol_SolArk) refers to rs485_modbus.o(.data) for chg_forceFlg + protocolswitch_p1.o(i.CAN_Protocol_SolArk) refers to gasgauge.o(.data) for ncc_Ah + protocolswitch_p1.o(i.CAN_Protocol_Sorotec) refers to can.o(i.CAN1_SendData) for CAN1_SendData + protocolswitch_p1.o(i.CAN_Protocol_Sorotec) refers to can.o(.bss) for canMem + protocolswitch_p1.o(i.CAN_Protocol_Sorotec) refers to can.o(.data) for CAN_SendCount + protocolswitch_p1.o(i.CAN_Protocol_Sorotec) refers to global.o(.bss) for bmsMem + protocolswitch_p1.o(i.CAN_Protocol_Sorotec) refers to global.o(.data) for OnlineNum + protocolswitch_p1.o(i.CAN_Protocol_Sorotec) refers to rs485_modbus.o(.data) for chg_forbidFlg + protocolswitch_p1.o(i.CAN_Protocol_Sorotec) refers to rs485_modbus.o(.data) for chg_curlimitFlg + protocolswitch_p1.o(i.CAN_Protocol_Sorotec) refers to rs485_modbus.o(.data) for dsg_forbidFlg + protocolswitch_p1.o(i.CAN_Protocol_Sorotec) refers to gasgauge.o(.data) for ncc_Ah + protocolswitch_p1.o(i.CAN_Protocol_Victron) refers to can.o(i.CAN1_SendData) for CAN1_SendData + protocolswitch_p1.o(i.CAN_Protocol_Victron) refers to can.o(.bss) for canMem + protocolswitch_p1.o(i.CAN_Protocol_Victron) refers to can.o(.data) for CAN_SendCount + protocolswitch_p1.o(i.CAN_Protocol_Victron) refers to global.o(.bss) for bmsMem + protocolswitch_p1.o(i.CAN_Protocol_Victron) refers to global.o(.data) for OnlineNum + protocolswitch_p1.o(i.CAN_Protocol_Victron) refers to rs485_modbus.o(.data) for chg_forbidFlg + protocolswitch_p1.o(i.CAN_Protocol_Victron) refers to rs485_modbus.o(.data) for chg_curlimitFlg + protocolswitch_p1.o(i.CAN_Protocol_Victron) refers to rs485_modbus.o(.data) for dsg_forbidFlg + protocolswitch_p1.o(i.CAN_Protocol_Victron) refers to gasgauge.o(.data) for ncc_Ah + protocolswitch_p1.o(i.CAN_Protocol_solis) refers to can.o(i.CAN1_SendData) for CAN1_SendData + protocolswitch_p1.o(i.CAN_Protocol_solis) refers to can.o(.bss) for canMem + protocolswitch_p1.o(i.CAN_Protocol_solis) refers to can.o(.data) for CAN_SendCount + protocolswitch_p1.o(i.CAN_Protocol_solis) refers to global.o(.bss) for bmsMem + protocolswitch_p1.o(i.CAN_Protocol_solis) refers to global.o(.data) for OnlineNum + protocolswitch_p1.o(i.CAN_Protocol_solis) refers to rs485_modbus.o(.data) for chg_forbidFlg + protocolswitch_p1.o(i.CAN_Protocol_solis) refers to rs485_modbus.o(.data) for chg_curlimitFlg + protocolswitch_p1.o(i.CAN_Protocol_solis) refers to rs485_modbus.o(.data) for dsg_forbidFlg + protocolswitch_p1.o(i.CAN_Protocol_solis) refers to rs485_modbus.o(.data) for chg_forceFlg + protocolswitch_p1.o(i.CAN_Protocol_solis) refers to rs485_modbus.o(.data) for RequestFlag + protocolswitch_p1.o(i.CAN_Protocol_solis) refers to gasgauge.o(.data) for ncc_Ah + protocolswitch_p1.o(i.MOD_Protocol_Growatt) refers to can.o(.bss) for canMem + protocolswitch_p1.o(i.MOD_Protocol_Growatt) refers to global.o(.bss) for bmsMem + protocolswitch_p1.o(i.MOD_Protocol_Growatt) refers to afe_sh3673520.o(.data) for bCHGING + protocolswitch_p1.o(i.MOD_Protocol_Growatt) refers to rs485_modbus.o(.data) for chg_forceFlg + protocolswitch_p1.o(i.MOD_Protocol_Growatt) refers to global.o(.bss) for GrowattMem + protocolswitch_p1.o(i.MOD_Protocol_Growatt) refers to gasgauge.o(.data) for ncc_Ah + protocolswitch_p1.o(i.MOD_Protocol_Growatt) refers to global.o(.data) for OnlineNum + protocolswitch_p1.o(i.MOD_Protocol_Growatt) refers to rs485_modbus.o(.data) for chg_forbidFlg + protocolswitch_p1.o(i.MOD_Protocol_Growatt) refers to rs485_modbus.o(.data) for chg_curlimitFlg + protocolswitch_p1.o(i.MOD_Protocol_Growatt) refers to rs485_modbus.o(.data) for dsg_forbidFlg + protocolswitch_p1.o(i.MOD_Protocol_Sorotec) refers to protocolswitch_p1.o(i.MOD_Protocol_Growatt) for MOD_Protocol_Growatt + protocolswitch_p1.o(i.YDN_Protocol_Pylon) refers to rs485_modbus_inverter.o(i.YDN) for YDN + protocolswitch_p2.o(i.CAN_Protocol_AlpSolarr) refers to can.o(i.CAN1_SendData) for CAN1_SendData + protocolswitch_p2.o(i.CAN_Protocol_AlpSolarr) refers to can.o(.bss) for canMem + protocolswitch_p2.o(i.CAN_Protocol_AlpSolarr) refers to can.o(.data) for CAN_SendCount + protocolswitch_p2.o(i.CAN_Protocol_AlpSolarr) refers to rs485_modbus.o(.data) for chg_forbidFlg + protocolswitch_p2.o(i.CAN_Protocol_AlpSolarr) refers to rs485_modbus.o(.data) for dsg_forbidFlg + protocolswitch_p2.o(i.CAN_Protocol_AlpSolarr) refers to global.o(.bss) for bmsMem + protocolswitch_p2.o(i.CAN_Protocol_AlpSolarr) refers to global.o(.data) for OnlineNum + protocolswitch_p2.o(i.CAN_Protocol_AlpSolarr) refers to rs485_modbus.o(.data) for RequestFlag + protocolswitch_p2.o(i.CAN_Protocol_AlpSolarr) refers to rs485_modbus.o(.data) for chg_forceFlg + protocolswitch_p2.o(i.CAN_Protocol_AlpSolarr) refers to gasgauge.o(.data) for fcc_Ah + protocolswitch_p2.o(i.CAN_Protocol_Luxpower) refers to can.o(i.CAN1_SendData) for CAN1_SendData + protocolswitch_p2.o(i.CAN_Protocol_Luxpower) refers to can.o(.bss) for canMem + protocolswitch_p2.o(i.CAN_Protocol_Luxpower) refers to can.o(.data) for CAN_SendCount + protocolswitch_p2.o(i.CAN_Protocol_Luxpower) refers to global.o(.data) for OnlineNum + protocolswitch_p2.o(i.CAN_Protocol_Luxpower) refers to gasgauge.o(.data) for ncc_Ah + protocolswitch_p2.o(i.CAN_Protocol_Luxpower) refers to rs485_modbus.o(.data) for chg_forbidFlg + protocolswitch_p2.o(i.CAN_Protocol_Luxpower) refers to rs485_modbus.o(.data) for dsg_forbidFlg + protocolswitch_p2.o(i.CAN_Protocol_Luxpower) refers to global.o(.bss) for bmsMem + protocolswitch_p2.o(i.CAN_Protocol_Luxpower) refers to rs485_modbus.o(.data) for chg_curlimitFlg + protocolswitch_p2.o(i.CAN_Protocol_Luxpower) refers to rs485_modbus.o(.data) for RequestFlag + protocolswitch_p2.o(i.CAN_Protocol_Luxpower) refers to rs485_modbus.o(.data) for chg_forceFlg + protocolswitch_p2.o(i.CAN_Protocol_SMA) refers to can.o(i.CAN1_SendData) for CAN1_SendData + protocolswitch_p2.o(i.CAN_Protocol_SMA) refers to can.o(.bss) for canMem + protocolswitch_p2.o(i.CAN_Protocol_SMA) refers to can.o(.data) for CAN_SendCount + protocolswitch_p2.o(i.CAN_Protocol_SMA) refers to global.o(.bss) for bmsMem + protocolswitch_p2.o(i.CAN_Protocol_SMA) refers to global.o(.data) for OnlineNum + protocolswitch_p2.o(i.CAN_Protocol_SMA) refers to rs485_modbus.o(.data) for chg_forbidFlg + protocolswitch_p2.o(i.CAN_Protocol_SMA) refers to rs485_modbus.o(.data) for chg_curlimitFlg + protocolswitch_p2.o(i.CAN_Protocol_SMA) refers to rs485_modbus.o(.data) for dsg_forbidFlg + protocolswitch_p2.o(i.CAN_Protocol_SMA) refers to gasgauge.o(.data) for ncc_Ah + protocolswitch_p2.o(i.CAN_Protocol_Schneider) refers to can.o(i.CAN1_SendData) for CAN1_SendData + protocolswitch_p2.o(i.CAN_Protocol_Schneider) refers to can.o(.bss) for canMem + protocolswitch_p2.o(i.CAN_Protocol_Schneider) refers to can.o(.data) for CAN_SendCount + protocolswitch_p2.o(i.CAN_Protocol_Schneider) refers to global.o(.bss) for bmsMem + protocolswitch_p2.o(i.CAN_Protocol_Schneider) refers to rs485_modbus.o(.data) for chg_forbidFlg + protocolswitch_p2.o(i.CAN_Protocol_Schneider) refers to global.o(.data) for OnlineNum + protocolswitch_p2.o(i.CAN_Protocol_Schneider) refers to rs485_modbus.o(.data) for chg_curlimitFlg + protocolswitch_p2.o(i.CAN_Protocol_Schneider) refers to rs485_modbus.o(.data) for dsg_forbidFlg + protocolswitch_p2.o(i.CAN_Protocol_Schneider) refers to gasgauge.o(.data) for ncc_Ah + protocolswitch_p2.o(i.CAN_Protocol_Schneider) refers to rs485_modbus.o(.data) for RequestFlag + protocolswitch_p2.o(i.CAN_Protocol_Schneider) refers to rs485_modbus.o(.data) for chg_forceFlg + protocolswitch_p2.o(i.CAN_Protocol_Sunways) refers to can.o(i.CAN1_SendData) for CAN1_SendData + protocolswitch_p2.o(i.CAN_Protocol_Sunways) refers to global.o(.bss) for bmsMem + protocolswitch_p2.o(i.CAN_Protocol_Sunways) refers to can.o(.bss) for canMem + protocolswitch_p2.o(i.CAN_Protocol_Sunways) refers to can.o(.data) for CAN_SendCount + protocolswitch_p2.o(i.CAN_Protocol_Sunways) refers to global.o(.data) for OnlineNum + protocolswitch_p2.o(i.CAN_Protocol_Sunways) refers to rs485_modbus.o(.data) for chg_forbidFlg + protocolswitch_p2.o(i.CAN_Protocol_Sunways) refers to rs485_modbus.o(.data) for dsg_forbidFlg + protocolswitch_p2.o(i.CAN_Protocol_Sunways) refers to rs485_modbus.o(.data) for chg_curlimitFlg + protocolswitch_p2.o(i.CAN_Protocol_Sunways) refers to rs485_modbus.o(.data) for chg_forceFlg + protocolswitch_p2.o(i.CAN_Protocol_Sunways) refers to gasgauge.o(.data) for ncc_Ah + protocolswitch_p2.o(i.CAN_Protocol_Sunways) refers to rs485_modbus.o(.data) for RequestFlag + protocolswitch_p2.o(i.MOD_Protocol_COSUPER) refers to can.o(.bss) for canMem + protocolswitch_p2.o(i.MOD_Protocol_COSUPER) refers to global.o(.bss) for SRNEMem + protocolswitch_p2.o(i.MOD_Protocol_COSUPER) refers to afe_sh3673520.o(.data) for bCHGING + protocolswitch_p2.o(i.MOD_Protocol_COSUPER) refers to global.o(.bss) for bmsMem + protocolswitch_p2.o(i.MOD_Protocol_COSUPER) refers to gasgauge.o(.data) for ncc_Ah + protocolswitch_p2.o(i.MOD_Protocol_COSUPER) refers to global.o(.data) for OnlineNum + protocolswitch_p2.o(i.MOD_Protocol_COSUPER) refers to rs485_modbus.o(.data) for chg_forbidFlg + protocolswitch_p2.o(i.MOD_Protocol_COSUPER) refers to rs485_modbus.o(.data) for chg_curlimitFlg + protocolswitch_p2.o(i.MOD_Protocol_COSUPER) refers to rs485_modbus.o(.data) for dsg_forbidFlg + protocolswitch_p2.o(i.MOD_Protocol_SAKO) refers to protocolswitch_p2.o(i.MOD_Protocol_Voltronic) for MOD_Protocol_Voltronic + protocolswitch_p2.o(i.MOD_Protocol_SMK) refers to rs485_modbus.o(.data) for RequestFlag + protocolswitch_p2.o(i.MOD_Protocol_SMK) refers to rs485_modbus.o(.data) for chg_forbidFlg + protocolswitch_p2.o(i.MOD_Protocol_SMK) refers to rs485_modbus.o(.data) for dsg_forbidFlg + protocolswitch_p2.o(i.MOD_Protocol_SMK) refers to rs485_modbus.o(.data) for chg_forceFlg + protocolswitch_p2.o(i.MOD_Protocol_SMK) refers to global.o(.bss) for SMKMem + protocolswitch_p2.o(i.MOD_Protocol_SMK) refers to can.o(.bss) for canMem + protocolswitch_p2.o(i.MOD_Protocol_SMK) refers to gasgauge.o(.data) for ncc_Ah + protocolswitch_p2.o(i.MOD_Protocol_SMK) refers to global.o(.data) for OnlineNum + protocolswitch_p2.o(i.MOD_Protocol_SMK) refers to global.o(.bss) for bmsMem + protocolswitch_p2.o(i.MOD_Protocol_SMK) refers to rs485_modbus.o(.data) for chg_curlimitFlg + protocolswitch_p2.o(i.MOD_Protocol_SRNE) refers to can.o(.bss) for canMem + protocolswitch_p2.o(i.MOD_Protocol_SRNE) refers to global.o(.bss) for SRNEMem + protocolswitch_p2.o(i.MOD_Protocol_SRNE) refers to afe_sh3673520.o(.data) for bCHGING + protocolswitch_p2.o(i.MOD_Protocol_SRNE) refers to global.o(.bss) for bmsMem + protocolswitch_p2.o(i.MOD_Protocol_SRNE) refers to gasgauge.o(.data) for ncc_Ah + protocolswitch_p2.o(i.MOD_Protocol_SRNE) refers to global.o(.data) for OnlineNum + protocolswitch_p2.o(i.MOD_Protocol_SRNE) refers to rs485_modbus.o(.data) for chg_forbidFlg + protocolswitch_p2.o(i.MOD_Protocol_SRNE) refers to rs485_modbus.o(.data) for chg_curlimitFlg + protocolswitch_p2.o(i.MOD_Protocol_SRNE) refers to rs485_modbus.o(.data) for dsg_forbidFlg + protocolswitch_p2.o(i.MOD_Protocol_Voltronic) refers to can.o(.bss) for canMem + protocolswitch_p2.o(i.MOD_Protocol_Voltronic) refers to rs485_modbus.o(.data) for RequestFlag + protocolswitch_p2.o(i.MOD_Protocol_Voltronic) refers to rs485_modbus.o(.data) for chg_forbidFlg + protocolswitch_p2.o(i.MOD_Protocol_Voltronic) refers to rs485_modbus.o(.data) for dsg_forbidFlg + protocolswitch_p2.o(i.MOD_Protocol_Voltronic) refers to rs485_modbus.o(.data) for chg_forceFlg + protocolswitch_p2.o(i.MOD_Protocol_Voltronic) refers to global.o(.bss) for VoltronicMem + protocolswitch_p2.o(i.MOD_Protocol_Voltronic) refers to global.o(.bss) for VersionMem + protocolswitch_p2.o(i.MOD_Protocol_Voltronic) refers to global.o(.data) for OnlineNum + protocolswitch_p2.o(i.MOD_Protocol_Voltronic) refers to afe_sh3673520.o(.data) for bCHGING + protocolswitch_p2.o(i.MOD_Protocol_Voltronic) refers to gasgauge.o(.data) for ncc_Ah + protocolswitch_p2.o(i.MOD_Protocol_Voltronic) refers to rs485_modbus.o(.data) for chg_curlimitFlg + vsnprintf.o(.text) refers (Special) to _printf_a.o(.ARM.Collect$$_printf_percent$$00000006) for _printf_a + vsnprintf.o(.text) refers (Special) to _printf_c.o(.ARM.Collect$$_printf_percent$$00000013) for _printf_c + vsnprintf.o(.text) refers (Special) to _printf_charcount.o(.text) for _printf_charcount + vsnprintf.o(.text) refers (Special) to _printf_d.o(.ARM.Collect$$_printf_percent$$00000009) for _printf_d + vsnprintf.o(.text) refers (Special) to _printf_e.o(.ARM.Collect$$_printf_percent$$00000004) for _printf_e + vsnprintf.o(.text) refers (Special) to _printf_f.o(.ARM.Collect$$_printf_percent$$00000003) for _printf_f + vsnprintf.o(.text) refers (Special) to printf1.o(x$fpl$printf1) for _printf_fp_dec + vsnprintf.o(.text) refers (Special) to printf2.o(x$fpl$printf2) for _printf_fp_hex + vsnprintf.o(.text) refers (Special) to _printf_g.o(.ARM.Collect$$_printf_percent$$00000005) for _printf_g + vsnprintf.o(.text) refers (Special) to _printf_i.o(.ARM.Collect$$_printf_percent$$00000008) for _printf_i + vsnprintf.o(.text) refers (Special) to _printf_dec.o(.text) for _printf_int_dec + vsnprintf.o(.text) refers (Special) to _printf_l.o(.ARM.Collect$$_printf_percent$$00000012) for _printf_l + vsnprintf.o(.text) refers (Special) to _printf_lc.o(.ARM.Collect$$_printf_percent$$00000015) for _printf_lc + vsnprintf.o(.text) refers (Special) to _printf_ll.o(.ARM.Collect$$_printf_percent$$00000007) for _printf_ll + vsnprintf.o(.text) refers (Special) to _printf_lld.o(.ARM.Collect$$_printf_percent$$0000000E) for _printf_lld + vsnprintf.o(.text) refers (Special) to _printf_lli.o(.ARM.Collect$$_printf_percent$$0000000D) for _printf_lli + vsnprintf.o(.text) refers (Special) to _printf_llo.o(.ARM.Collect$$_printf_percent$$00000010) for _printf_llo + vsnprintf.o(.text) refers (Special) to _printf_llu.o(.ARM.Collect$$_printf_percent$$0000000F) for _printf_llu + vsnprintf.o(.text) refers (Special) to _printf_llx.o(.ARM.Collect$$_printf_percent$$00000011) for _printf_llx + vsnprintf.o(.text) refers (Special) to _printf_longlong_dec.o(.text) for _printf_longlong_dec + vsnprintf.o(.text) refers (Special) to _printf_hex_int_ll_ptr.o(.text) for _printf_longlong_hex + vsnprintf.o(.text) refers (Special) to _printf_oct_int_ll.o(.text) for _printf_longlong_oct + vsnprintf.o(.text) refers (Special) to _printf_ls.o(.ARM.Collect$$_printf_percent$$00000016) for _printf_ls + vsnprintf.o(.text) refers (Special) to _printf_n.o(.ARM.Collect$$_printf_percent$$00000001) for _printf_n + vsnprintf.o(.text) refers (Special) to _printf_o.o(.ARM.Collect$$_printf_percent$$0000000B) for _printf_o + vsnprintf.o(.text) refers (Special) to _printf_p.o(.ARM.Collect$$_printf_percent$$00000002) for _printf_p + vsnprintf.o(.text) refers (Special) to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + vsnprintf.o(.text) refers (Special) to _printf_pad.o(.text) for _printf_post_padding + vsnprintf.o(.text) refers (Special) to _printf_s.o(.ARM.Collect$$_printf_percent$$00000014) for _printf_s + vsnprintf.o(.text) refers (Special) to _printf_str.o(.text) for _printf_str + vsnprintf.o(.text) refers (Special) to _printf_truncate.o(.text) for _printf_truncate_signed + vsnprintf.o(.text) refers (Special) to _printf_u.o(.ARM.Collect$$_printf_percent$$0000000A) for _printf_u + vsnprintf.o(.text) refers (Special) to _printf_wctomb.o(.text) for _printf_wctomb + vsnprintf.o(.text) refers (Special) to _printf_x.o(.ARM.Collect$$_printf_percent$$0000000C) for _printf_x + vsnprintf.o(.text) refers to _printf_char_common.o(.text) for _printf_char_common + vsnprintf.o(.text) refers to _sputc.o(.text) for _sputc + vsnprintf.o(.text) refers to _snputc.o(.text) for _snputc + __2sprintf.o(.text) refers to _printf_char_common.o(.text) for _printf_char_common + __2sprintf.o(.text) refers to _sputc.o(.text) for _sputc + noretval__2sprintf.o(.text) refers to _printf_char_common.o(.text) for _printf_char_common + noretval__2sprintf.o(.text) refers to _sputc.o(.text) for _sputc + __printf.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + _printf_str.o(.text) refers (Special) to _printf_char.o(.text) for _printf_cs_common + _printf_str.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_pre_padding + _printf_str.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_post_padding + _printf_dec.o(.text) refers (Weak) to _printf_truncate.o(.text) for _printf_truncate_signed + _printf_dec.o(.text) refers (Weak) to _printf_truncate.o(.text) for _printf_truncate_unsigned + _printf_dec.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common + _printf_hex_ll.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common + _printf_hex_ll.o(.text) refers to _printf_hex_ll.o(.constdata) for .constdata + _printf_hex_int.o(.text) refers (Weak) to _printf_truncate.o(.text) for _printf_truncate_unsigned + _printf_hex_int.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common + _printf_hex_int.o(.text) refers to _printf_hex_int.o(.constdata) for .constdata + _printf_hex_int_ll.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common + _printf_hex_int_ll.o(.text) refers (Weak) to _printf_truncate.o(.text) for _printf_truncate_unsigned + _printf_hex_int_ll.o(.text) refers to _printf_hex_int_ll.o(.constdata) for .constdata + _printf_hex_ptr.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common + _printf_hex_ptr.o(.text) refers to _printf_hex_ptr.o(.constdata) for .constdata + _printf_hex_int_ptr.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common + _printf_hex_int_ptr.o(.text) refers (Weak) to _printf_truncate.o(.text) for _printf_truncate_unsigned + _printf_hex_int_ptr.o(.text) refers to _printf_hex_int_ptr.o(.constdata) for .constdata + _printf_hex_ll_ptr.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common + _printf_hex_ll_ptr.o(.text) refers to _printf_hex_ll_ptr.o(.constdata) for .constdata + _printf_hex_int_ll_ptr.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common + _printf_hex_int_ll_ptr.o(.text) refers (Weak) to _printf_truncate.o(.text) for _printf_truncate_unsigned + _printf_hex_int_ll_ptr.o(.text) refers to _printf_hex_int_ll_ptr.o(.constdata) for .constdata + __printf_flags.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + __printf_flags.o(.text) refers to __printf_flags.o(.constdata) for .constdata + __printf_ss.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + __printf_flags_ss.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + __printf_flags_ss.o(.text) refers to __printf_flags_ss.o(.constdata) for .constdata + __printf_wp.o(.text) refers to __printf_wp.o(i._is_digit) for _is_digit + __printf_wp.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + __printf_flags_wp.o(.text) refers to __printf_wp.o(i._is_digit) for _is_digit + __printf_flags_wp.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + __printf_flags_wp.o(.text) refers to __printf_flags_wp.o(.constdata) for .constdata + __printf_ss_wp.o(.text) refers to __printf_wp.o(i._is_digit) for _is_digit + __printf_ss_wp.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + __printf_flags_ss_wp.o(.text) refers to __printf_wp.o(i._is_digit) for _is_digit + __printf_flags_ss_wp.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + __printf_flags_ss_wp.o(.text) refers to __printf_flags_ss_wp.o(.constdata) for .constdata + _printf_c.o(.ARM.Collect$$_printf_percent$$00000013) refers (Weak) to _printf_char.o(.text) for _printf_char + _printf_x.o(.ARM.Collect$$_printf_percent$$0000000C) refers (Weak) to _printf_hex_int_ll_ptr.o(.text) for _printf_int_hex + _printf_d.o(.ARM.Collect$$_printf_percent$$00000009) refers (Weak) to _printf_dec.o(.text) for _printf_int_dec + _printf_u.o(.ARM.Collect$$_printf_percent$$0000000A) refers (Weak) to _printf_dec.o(.text) for _printf_int_dec + _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) refers (Special) to _printf_percent_end.o(.ARM.Collect$$_printf_percent$$00000017) for _printf_percent_end + __0sscanf.o(.text) refers to scanf_char.o(.text) for __vfscanf_char + __0sscanf.o(.text) refers to _sgetc.o(.text) for _sgetc + _scanf_int.o(.text) refers to _chval.o(.text) for _chval + rt_memcpy_v6.o(.text) refers to rt_memcpy_w.o(.text) for __aeabi_memcpy4 + aeabi_memset.o(.text) refers to rt_memclr.o(.text) for _memset + rt_memclr.o(.text) refers to rt_memclr_w.o(.text) for _memset_w + strncpy.o(.text) refers to rt_memclr.o(.text) for __aeabi_memclr + __main.o(!!!main) refers to __rtentry.o(.ARM.Collect$$rtentry$$00000000) for __rt_entry + daddsub_clz.o(x$fpl$dadd) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + daddsub_clz.o(x$fpl$dadd) refers to daddsub_clz.o(x$fpl$dsub) for _dsub1 + daddsub_clz.o(x$fpl$dadd) refers to dretinf.o(x$fpl$dretinf) for __fpl_dretinf + daddsub_clz.o(x$fpl$dadd) refers to dnaninf.o(x$fpl$dnaninf) for __fpl_dnaninf + daddsub_clz.o(x$fpl$drsb) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + daddsub_clz.o(x$fpl$drsb) refers to daddsub_clz.o(x$fpl$dadd) for _dadd1 + daddsub_clz.o(x$fpl$drsb) refers to daddsub_clz.o(x$fpl$dsub) for _dsub1 + daddsub_clz.o(x$fpl$dsub) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + daddsub_clz.o(x$fpl$dsub) refers to daddsub_clz.o(x$fpl$dadd) for _dadd1 + daddsub_clz.o(x$fpl$dsub) refers to dnaninf.o(x$fpl$dnaninf) for __fpl_dnaninf + ddiv.o(x$fpl$drdiv) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + ddiv.o(x$fpl$drdiv) refers to ddiv.o(x$fpl$ddiv) for ddiv_entry + ddiv.o(x$fpl$ddiv) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + ddiv.o(x$fpl$ddiv) refers to dretinf.o(x$fpl$dretinf) for __fpl_dretinf + ddiv.o(x$fpl$ddiv) refers to dnaninf.o(x$fpl$dnaninf) for __fpl_dnaninf + dfix.o(x$fpl$dfix) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + dfix.o(x$fpl$dfix) refers to dnaninf.o(x$fpl$dnaninf) for __fpl_dnaninf + dfix.o(x$fpl$dfixr) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + dfix.o(x$fpl$dfixr) refers to dnaninf.o(x$fpl$dnaninf) for __fpl_dnaninf + dfixu.o(x$fpl$dfixu) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + dfixu.o(x$fpl$dfixu) refers to dnaninf.o(x$fpl$dnaninf) for __fpl_dnaninf + dfixu.o(x$fpl$dfixur) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + dfixu.o(x$fpl$dfixur) refers to dnaninf.o(x$fpl$dnaninf) for __fpl_dnaninf + dflt_clz.o(x$fpl$dfltu) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + dflt_clz.o(x$fpl$dflt) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + dflt_clz.o(x$fpl$dfltn) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + dleqf.o(x$fpl$dleqf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + dleqf.o(x$fpl$dleqf) refers to dnaninf.o(x$fpl$dnaninf) for __fpl_dnaninf + dleqf.o(x$fpl$dleqf) refers to dcmpi.o(x$fpl$dcmpinf) for __fpl_dcmp_Inf + dmul.o(x$fpl$dmul) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + dmul.o(x$fpl$dmul) refers to dretinf.o(x$fpl$dretinf) for __fpl_dretinf + dmul.o(x$fpl$dmul) refers to dnaninf.o(x$fpl$dnaninf) for __fpl_dnaninf + drleqf.o(x$fpl$drleqf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + drleqf.o(x$fpl$drleqf) refers to dleqf.o(x$fpl$dleqf) for __fpl_dcmple_InfNaN + f2d.o(x$fpl$f2d) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + f2d.o(x$fpl$f2d) refers to fnaninf.o(x$fpl$fnaninf) for __fpl_fnaninf + f2d.o(x$fpl$f2d) refers to dretinf.o(x$fpl$dretinf) for __fpl_dretinf + faddsub_clz.o(x$fpl$fadd) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + faddsub_clz.o(x$fpl$fadd) refers to faddsub_clz.o(x$fpl$fsub) for _fsub1 + faddsub_clz.o(x$fpl$fadd) refers to fretinf.o(x$fpl$fretinf) for __fpl_fretinf + faddsub_clz.o(x$fpl$fadd) refers to fnaninf.o(x$fpl$fnaninf) for __fpl_fnaninf + faddsub_clz.o(x$fpl$frsb) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + faddsub_clz.o(x$fpl$frsb) refers to faddsub_clz.o(x$fpl$fadd) for _fadd1 + faddsub_clz.o(x$fpl$frsb) refers to faddsub_clz.o(x$fpl$fsub) for _fsub1 + faddsub_clz.o(x$fpl$fsub) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + faddsub_clz.o(x$fpl$fsub) refers to faddsub_clz.o(x$fpl$fadd) for _fadd1 + faddsub_clz.o(x$fpl$fsub) refers to fnaninf.o(x$fpl$fnaninf) for __fpl_fnaninf + fdiv.o(x$fpl$frdiv) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + fdiv.o(x$fpl$frdiv) refers to fdiv.o(x$fpl$fdiv) for _fdiv1 + fdiv.o(x$fpl$fdiv) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + fdiv.o(x$fpl$fdiv) refers to fretinf.o(x$fpl$fretinf) for __fpl_fretinf + fdiv.o(x$fpl$fdiv) refers to fnaninf.o(x$fpl$fnaninf) for __fpl_fnaninf + ffixu.o(x$fpl$ffixu) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + ffixu.o(x$fpl$ffixu) refers to fnaninf.o(x$fpl$fnaninf) for __fpl_fnaninf + ffixu.o(x$fpl$ffixur) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + ffixu.o(x$fpl$ffixur) refers to fnaninf.o(x$fpl$fnaninf) for __fpl_fnaninf + fflt_clz.o(x$fpl$ffltu) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + fflt_clz.o(x$fpl$fflt) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + fflt_clz.o(x$fpl$ffltn) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + fmul.o(x$fpl$fmul) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + fmul.o(x$fpl$fmul) refers to fretinf.o(x$fpl$fretinf) for __fpl_fretinf + fmul.o(x$fpl$fmul) refers to fnaninf.o(x$fpl$fnaninf) for __fpl_fnaninf + scalbn.o(x$fpl$scalbn) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + scalbn.o(x$fpl$scalbn) refers to dcheck1.o(x$fpl$dcheck1) for __fpl_dcheck_NaN1 + cos.o(i.__softfp_cos) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + cos.o(i.__softfp_cos) refers to cos.o(i.cos) for cos + cos.o(i.cos) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + cos.o(i.cos) refers to _rserrno.o(.text) for __set_errno + cos.o(i.cos) refers to dunder.o(i.__mathlib_dbl_invalid) for __mathlib_dbl_invalid + cos.o(i.cos) refers to dunder.o(i.__mathlib_dbl_infnan) for __mathlib_dbl_infnan + cos.o(i.cos) refers to rred.o(i.__ieee754_rem_pio2) for __ieee754_rem_pio2 + cos.o(i.cos) refers to sin_i.o(i.__kernel_sin) for __kernel_sin + cos.o(i.cos) refers to cos_i.o(i.__kernel_cos) for __kernel_cos + cos_x.o(i.____softfp_cos$lsc) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + cos_x.o(i.____softfp_cos$lsc) refers to cos_x.o(i.__cos$lsc) for __cos$lsc + cos_x.o(i.__cos$lsc) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + cos_x.o(i.__cos$lsc) refers to _rserrno.o(.text) for __set_errno + cos_x.o(i.__cos$lsc) refers to dunder.o(i.__mathlib_dbl_infnan) for __mathlib_dbl_infnan + cos_x.o(i.__cos$lsc) refers to rred.o(i.__ieee754_rem_pio2) for __ieee754_rem_pio2 + cos_x.o(i.__cos$lsc) refers to sin_i.o(i.__kernel_sin) for __kernel_sin + cos_x.o(i.__cos$lsc) refers to cos_i.o(i.__kernel_cos) for __kernel_cos + sin.o(i.__softfp_sin) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + sin.o(i.__softfp_sin) refers to sin.o(i.sin) for sin + sin.o(i.sin) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + sin.o(i.sin) refers to _rserrno.o(.text) for __set_errno + sin.o(i.sin) refers to dunder.o(i.__mathlib_dbl_invalid) for __mathlib_dbl_invalid + sin.o(i.sin) refers to dunder.o(i.__mathlib_dbl_infnan) for __mathlib_dbl_infnan + sin.o(i.sin) refers to rred.o(i.__ieee754_rem_pio2) for __ieee754_rem_pio2 + sin.o(i.sin) refers to cos_i.o(i.__kernel_cos) for __kernel_cos + sin.o(i.sin) refers to sin_i.o(i.__kernel_sin) for __kernel_sin + sin_x.o(i.____softfp_sin$lsc) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + sin_x.o(i.____softfp_sin$lsc) refers to sin_x.o(i.__sin$lsc) for __sin$lsc + sin_x.o(i.__sin$lsc) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + sin_x.o(i.__sin$lsc) refers to _rserrno.o(.text) for __set_errno + sin_x.o(i.__sin$lsc) refers to dunder.o(i.__mathlib_dbl_infnan) for __mathlib_dbl_infnan + sin_x.o(i.__sin$lsc) refers to rred.o(i.__ieee754_rem_pio2) for __ieee754_rem_pio2 + sin_x.o(i.__sin$lsc) refers to cos_i.o(i.__kernel_cos) for __kernel_cos + sin_x.o(i.__sin$lsc) refers to sin_i.o(i.__kernel_sin) for __kernel_sin + sqrt.o(i.__softfp_sqrt) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + sqrt.o(i.__softfp_sqrt) refers to dsqrt_noumaal.o(x$fpl$dsqrt) for _dsqrt + sqrt.o(i.__softfp_sqrt) refers to _rserrno.o(.text) for __set_errno + sqrt.o(i.sqrt) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + sqrt.o(i.sqrt) refers to dsqrt_noumaal.o(x$fpl$dsqrt) for _dsqrt + sqrt.o(i.sqrt) refers to _rserrno.o(.text) for __set_errno + sqrt_x.o(i.____softfp_sqrt$lsc) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + sqrt_x.o(i.____softfp_sqrt$lsc) refers to dleqf.o(x$fpl$dleqf) for __aeabi_cdcmple + sqrt_x.o(i.____softfp_sqrt$lsc) refers to _rserrno.o(.text) for __set_errno + sqrt_x.o(i.____softfp_sqrt$lsc) refers to dsqrt_noumaal.o(x$fpl$dsqrt) for _dsqrt + sqrt_x.o(i.__sqrt$lsc) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + sqrt_x.o(i.__sqrt$lsc) refers to dleqf.o(x$fpl$dleqf) for __aeabi_cdcmple + sqrt_x.o(i.__sqrt$lsc) refers to _rserrno.o(.text) for __set_errno + sqrt_x.o(i.__sqrt$lsc) refers to dsqrt_noumaal.o(x$fpl$dsqrt) for _dsqrt + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) for __rt_entry_li + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) for __rt_entry_main + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000C) for __rt_entry_postli_1 + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$00000009) for __rt_entry_postsh_1 + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$00000002) for __rt_entry_presh_1 + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry4.o(.ARM.Collect$$rtentry$$00000004) for __rt_entry_sh + _rserrno.o(.text) refers to rt_errno_addr_intlibspace.o(.text) for __aeabi_errno_addr + _printf_intcommon.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_pre_padding + _printf_intcommon.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_pre_padding + _printf_intcommon.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_post_padding + _printf_char_common.o(.text) refers to __printf_flags_ss_wp.o(.text) for __printf + _printf_char.o(.text) refers (Weak) to _printf_str.o(.text) for _printf_str + _printf_wctomb.o(.text) refers (Special) to _printf_wchar.o(.text) for _printf_lcs_common + _printf_wctomb.o(.text) refers to _wcrtomb.o(.text) for _wcrtomb + _printf_wctomb.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_pre_padding + _printf_wctomb.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_post_padding + _printf_wctomb.o(.text) refers to _printf_wctomb.o(.constdata) for .constdata + _printf_wctomb.o(.constdata) refers (Special) to _printf_wchar.o(.text) for _printf_lcs_common + _printf_longlong_dec.o(.text) refers to lludiv10.o(.text) for _ll_udiv10 + _printf_longlong_dec.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common + _printf_oct_ll.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common + _printf_oct_int.o(.text) refers (Weak) to _printf_truncate.o(.text) for _printf_truncate_unsigned + _printf_oct_int.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common + _printf_oct_int_ll.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common + _printf_oct_int_ll.o(.text) refers (Weak) to _printf_truncate.o(.text) for _printf_truncate_unsigned + _printf_s.o(.ARM.Collect$$_printf_percent$$00000014) refers (Weak) to _printf_char.o(.text) for _printf_string + _printf_n.o(.ARM.Collect$$_printf_percent$$00000001) refers (Weak) to _printf_charcount.o(.text) for _printf_charcount + _printf_p.o(.ARM.Collect$$_printf_percent$$00000002) refers (Weak) to _printf_hex_int_ll_ptr.o(.text) for _printf_hex_ptr + _printf_o.o(.ARM.Collect$$_printf_percent$$0000000B) refers (Weak) to _printf_oct_int_ll.o(.text) for _printf_int_oct + _printf_i.o(.ARM.Collect$$_printf_percent$$00000008) refers (Weak) to _printf_dec.o(.text) for _printf_int_dec + _printf_f.o(.ARM.Collect$$_printf_percent$$00000003) refers (Weak) to printf1.o(x$fpl$printf1) for _printf_fp_dec + _printf_e.o(.ARM.Collect$$_printf_percent$$00000004) refers (Weak) to printf1.o(x$fpl$printf1) for _printf_fp_dec + _printf_g.o(.ARM.Collect$$_printf_percent$$00000005) refers (Weak) to printf1.o(x$fpl$printf1) for _printf_fp_dec + _printf_a.o(.ARM.Collect$$_printf_percent$$00000006) refers (Weak) to printf2.o(x$fpl$printf2) for _printf_fp_hex + _printf_lli.o(.ARM.Collect$$_printf_percent$$0000000D) refers (Special) to _printf_ll.o(.ARM.Collect$$_printf_percent$$00000007) for _printf_ll + _printf_lli.o(.ARM.Collect$$_printf_percent$$0000000D) refers (Weak) to _printf_longlong_dec.o(.text) for _printf_longlong_dec + _printf_lld.o(.ARM.Collect$$_printf_percent$$0000000E) refers (Special) to _printf_ll.o(.ARM.Collect$$_printf_percent$$00000007) for _printf_ll + _printf_lld.o(.ARM.Collect$$_printf_percent$$0000000E) refers (Weak) to _printf_longlong_dec.o(.text) for _printf_longlong_dec + _printf_llu.o(.ARM.Collect$$_printf_percent$$0000000F) refers (Special) to _printf_ll.o(.ARM.Collect$$_printf_percent$$00000007) for _printf_ll + _printf_llu.o(.ARM.Collect$$_printf_percent$$0000000F) refers (Weak) to _printf_longlong_dec.o(.text) for _printf_longlong_dec + _printf_lc.o(.ARM.Collect$$_printf_percent$$00000015) refers (Special) to _printf_l.o(.ARM.Collect$$_printf_percent$$00000012) for _printf_l + _printf_lc.o(.ARM.Collect$$_printf_percent$$00000015) refers (Weak) to _printf_wchar.o(.text) for _printf_wchar + _printf_ls.o(.ARM.Collect$$_printf_percent$$00000016) refers (Special) to _printf_l.o(.ARM.Collect$$_printf_percent$$00000012) for _printf_l + _printf_ls.o(.ARM.Collect$$_printf_percent$$00000016) refers (Weak) to _printf_wchar.o(.text) for _printf_wstring + _printf_llo.o(.ARM.Collect$$_printf_percent$$00000010) refers (Special) to _printf_ll.o(.ARM.Collect$$_printf_percent$$00000007) for _printf_ll + _printf_llo.o(.ARM.Collect$$_printf_percent$$00000010) refers (Weak) to _printf_oct_int_ll.o(.text) for _printf_ll_oct + _printf_llx.o(.ARM.Collect$$_printf_percent$$00000011) refers (Special) to _printf_ll.o(.ARM.Collect$$_printf_percent$$00000007) for _printf_ll + _printf_llx.o(.ARM.Collect$$_printf_percent$$00000011) refers (Weak) to _printf_hex_int_ll_ptr.o(.text) for _printf_ll_hex + scanf_char.o(.text) refers to _scanf.o(.text) for __vfscanf + scanf_char.o(.text) refers to isspace.o(.text) for isspace + dcheck1.o(x$fpl$dcheck1) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + dcheck1.o(x$fpl$dcheck1) refers to retnan.o(x$fpl$retnan) for __fpl_return_NaN + dcmpi.o(x$fpl$dcmpinf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + dnaninf.o(x$fpl$dnaninf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + dretinf.o(x$fpl$dretinf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + dsqrt_noumaal.o(x$fpl$dsqrt) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + dsqrt_noumaal.o(x$fpl$dsqrt) refers to dnaninf.o(x$fpl$dnaninf) for __fpl_dnaninf + fnaninf.o(x$fpl$fnaninf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + fretinf.o(x$fpl$fretinf) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + printf1.o(x$fpl$printf1) refers to _printf_fp_dec.o(.text) for _printf_fp_dec_real + printf2.o(x$fpl$printf2) refers to _printf_fp_hex.o(.text) for _printf_fp_hex_real + printf2b.o(x$fpl$printf2) refers to _printf_fp_hex.o(.text) for _printf_fp_hex_real + cos_i.o(i.__kernel_cos) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + cos_i.o(i.__kernel_cos) refers to dfix.o(x$fpl$dfix) for __aeabi_d2iz + cos_i.o(i.__kernel_cos) refers to dmul.o(x$fpl$dmul) for __aeabi_dmul + cos_i.o(i.__kernel_cos) refers to poly.o(i.__kernel_poly) for __kernel_poly + cos_i.o(i.__kernel_cos) refers to daddsub_clz.o(x$fpl$dsub) for __aeabi_dsub + cos_i.o(i.__kernel_cos) refers to scalbn.o(x$fpl$scalbn) for __ARM_scalbn + cos_i.o(i.__kernel_cos) refers to daddsub_clz.o(x$fpl$drsb) for __aeabi_drsub + cos_i.o(i.__kernel_cos) refers to cos_i.o(.constdata) for .constdata + cos_i.o(.constdata) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + dunder.o(i.__mathlib_dbl_divzero) refers to ddiv.o(x$fpl$ddiv) for __aeabi_ddiv + dunder.o(i.__mathlib_dbl_infnan) refers to scalbn.o(x$fpl$scalbn) for __ARM_scalbn + dunder.o(i.__mathlib_dbl_infnan2) refers to daddsub_clz.o(x$fpl$dadd) for __aeabi_dadd + dunder.o(i.__mathlib_dbl_invalid) refers to ddiv.o(x$fpl$ddiv) for __aeabi_ddiv + dunder.o(i.__mathlib_dbl_overflow) refers to scalbn.o(x$fpl$scalbn) for __ARM_scalbn + dunder.o(i.__mathlib_dbl_posinfnan) refers to dmul.o(x$fpl$dmul) for __aeabi_dmul + dunder.o(i.__mathlib_dbl_underflow) refers to scalbn.o(x$fpl$scalbn) for __ARM_scalbn + rred.o(i.__ieee754_rem_pio2) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + rred.o(i.__ieee754_rem_pio2) refers to daddsub_clz.o(x$fpl$dsub) for __aeabi_dsub + rred.o(i.__ieee754_rem_pio2) refers to daddsub_clz.o(x$fpl$dadd) for __aeabi_dadd + rred.o(i.__ieee754_rem_pio2) refers to dmul.o(x$fpl$dmul) for __aeabi_dmul + rred.o(i.__ieee754_rem_pio2) refers to dfix.o(x$fpl$dfix) for __aeabi_d2iz + rred.o(i.__ieee754_rem_pio2) refers to dflt_clz.o(x$fpl$dflt) for __aeabi_i2d + rred.o(i.__ieee754_rem_pio2) refers to daddsub_clz.o(x$fpl$drsb) for __aeabi_drsub + rred.o(i.__ieee754_rem_pio2) refers to dflt_clz.o(x$fpl$dfltu) for __aeabi_ui2d + rred.o(i.__ieee754_rem_pio2) refers to scalbn.o(x$fpl$scalbn) for __ARM_scalbn + rred.o(i.__ieee754_rem_pio2) refers to rred.o(.constdata) for .constdata + rred.o(i.__use_accurate_range_reduction) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + rred.o(.constdata) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + sin_i.o(i.__kernel_sin) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + sin_i.o(i.__kernel_sin) refers to fpclassify.o(i.__ARM_fpclassify) for __ARM_fpclassify + sin_i.o(i.__kernel_sin) refers to dunder.o(i.__mathlib_dbl_underflow) for __mathlib_dbl_underflow + sin_i.o(i.__kernel_sin) refers to dmul.o(x$fpl$dmul) for __aeabi_dmul + sin_i.o(i.__kernel_sin) refers to poly.o(i.__kernel_poly) for __kernel_poly + sin_i.o(i.__kernel_sin) refers to scalbn.o(x$fpl$scalbn) for __ARM_scalbn + sin_i.o(i.__kernel_sin) refers to daddsub_clz.o(x$fpl$dsub) for __aeabi_dsub + sin_i.o(i.__kernel_sin) refers to daddsub_clz.o(x$fpl$drsb) for __aeabi_drsub + sin_i.o(i.__kernel_sin) refers to daddsub_clz.o(x$fpl$dadd) for __aeabi_dadd + sin_i.o(i.__kernel_sin) refers to sin_i.o(.constdata) for .constdata + sin_i.o(.constdata) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + sin_i_x.o(i.____kernel_sin$lsc) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + sin_i_x.o(i.____kernel_sin$lsc) refers to dmul.o(x$fpl$dmul) for __aeabi_dmul + sin_i_x.o(i.____kernel_sin$lsc) refers to poly.o(i.__kernel_poly) for __kernel_poly + sin_i_x.o(i.____kernel_sin$lsc) refers to scalbn.o(x$fpl$scalbn) for __ARM_scalbn + sin_i_x.o(i.____kernel_sin$lsc) refers to daddsub_clz.o(x$fpl$dsub) for __aeabi_dsub + sin_i_x.o(i.____kernel_sin$lsc) refers to daddsub_clz.o(x$fpl$drsb) for __aeabi_drsub + sin_i_x.o(i.____kernel_sin$lsc) refers to daddsub_clz.o(x$fpl$dadd) for __aeabi_dadd + sin_i_x.o(i.____kernel_sin$lsc) refers to sin_i_x.o(.constdata) for .constdata + sin_i_x.o(.constdata) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + __rtentry2.o(.ARM.Collect$$rtentry$$00000008) refers to boardinit2.o(.text) for _platform_post_stackheap_init + __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) refers to libinit.o(.ARM.Collect$$libinit$$00000000) for __rt_lib_init + __rtentry2.o(.ARM.Collect$$rtentry$$0000000B) refers to boardinit3.o(.text) for _platform_post_lib_init + __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) refers to main.o(i.main) for main + __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) refers to exit.o(.text) for exit + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$00000001) for .ARM.Collect$$rtentry$$00000001 + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$00000008) for .ARM.Collect$$rtentry$$00000008 + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) for .ARM.Collect$$rtentry$$0000000A + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000B) for .ARM.Collect$$rtentry$$0000000B + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) for .ARM.Collect$$rtentry$$0000000D + __rtentry4.o(.ARM.Collect$$rtentry$$00000004) refers to sys_stackheap_outer.o(.text) for __user_setup_stackheap + __rtentry4.o(.ARM.exidx) refers to __rtentry4.o(.ARM.Collect$$rtentry$$00000004) for .ARM.Collect$$rtentry$$00000004 + rt_errno_addr.o(.text) refers to rt_errno_addr.o(.bss) for __aeabi_errno_addr_data + rt_errno_addr_intlibspace.o(.text) refers to libspace.o(.bss) for __libspace_start + isspace.o(.text) refers to rt_ctype_table.o(.text) for __rt_ctype_table + _printf_fp_dec.o(.text) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + _printf_fp_dec.o(.text) refers (Special) to lc_numeric_c.o(locale$$code) for _get_lc_numeric + _printf_fp_dec.o(.text) refers to bigflt0.o(.text) for _btod_etento + _printf_fp_dec.o(.text) refers to btod.o(CL$$btod_d2e) for _btod_d2e + _printf_fp_dec.o(.text) refers to btod.o(CL$$btod_ediv) for _btod_ediv + _printf_fp_dec.o(.text) refers to btod.o(CL$$btod_emul) for _btod_emul + _printf_fp_dec.o(.text) refers to lludiv10.o(.text) for _ll_udiv10 + _printf_fp_dec.o(.text) refers to fpclassify.o(i.__ARM_fpclassify) for __ARM_fpclassify + _printf_fp_dec.o(.text) refers to _printf_fp_infnan.o(.text) for _printf_fp_infnan + _printf_fp_dec.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_pre_padding + _printf_fp_dec.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_pre_padding + _printf_fp_dec.o(.text) refers to rt_locale_intlibspace.o(.text) for __rt_locale + _printf_fp_dec.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_post_padding + _printf_fp_hex.o(.text) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + _printf_fp_hex.o(.text) refers to fpclassify.o(i.__ARM_fpclassify) for __ARM_fpclassify + _printf_fp_hex.o(.text) refers to _printf_fp_infnan.o(.text) for _printf_fp_infnan + _printf_fp_hex.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_pre_padding + _printf_fp_hex.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_pre_padding + _printf_fp_hex.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_post_padding + _printf_fp_hex.o(.text) refers to _printf_fp_hex.o(.constdata) for .constdata + _printf_fp_hex.o(.constdata) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + _printf_wchar.o(.text) refers (Weak) to _printf_wctomb.o(.text) for _printf_wctomb + _scanf.o(.text) refers (Weak) to _scanf_int.o(.text) for _scanf_int + _wcrtomb.o(.text) refers to rt_ctype_table.o(.text) for __rt_ctype_table + retnan.o(x$fpl$retnan) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + retnan.o(x$fpl$retnan) refers to trapv.o(x$fpl$trapveneer) for __fpl_cmpreturn + fpclassify.o(i.__ARM_fpclassify) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + poly.o(i.__kernel_poly) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + poly.o(i.__kernel_poly) refers to dmul.o(x$fpl$dmul) for __aeabi_dmul + poly.o(i.__kernel_poly) refers to daddsub_clz.o(x$fpl$dadd) for __aeabi_dadd + libspace.o(.text) refers to libspace.o(.bss) for __libspace_start + sys_stackheap_outer.o(.text) refers to libspace.o(.text) for __user_perproc_libspace + sys_stackheap_outer.o(.text) refers to startup_stm32f10x_hd.o(.text) for __user_initial_stackheap + rt_ctype_table.o(.text) refers to rt_locale_intlibspace.o(.text) for __rt_locale + rt_ctype_table.o(.text) refers to lc_ctype_c.o(locale$$code) for _get_lc_ctype + rt_locale.o(.text) refers to rt_locale.o(.bss) for __rt_locale_data + rt_locale_intlibspace.o(.text) refers to libspace.o(.bss) for __libspace_start + _printf_fp_infnan.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_pre_padding + _printf_fp_infnan.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_post_padding + bigflt0.o(.text) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + bigflt0.o(.text) refers to btod.o(CL$$btod_emul) for _btod_emul + bigflt0.o(.text) refers to btod.o(CL$$btod_ediv) for _btod_ediv + bigflt0.o(.text) refers to bigflt0.o(.constdata) for .constdata + bigflt0.o(.constdata) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + btod.o(CL$$btod_d2e) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + btod.o(CL$$btod_d2e) refers to btod.o(CL$$btod_d2e_norm_op1) for _d2e_norm_op1 + btod.o(CL$$btod_d2e_norm_op1) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + btod.o(CL$$btod_d2e_norm_op1) refers to btod.o(CL$$btod_d2e_denorm_low) for _d2e_denorm_low + btod.o(CL$$btod_d2e_denorm_low) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + btod.o(CL$$btod_emul) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + btod.o(CL$$btod_emul) refers to btod.o(CL$$btod_mult_common) for __btod_mult_common + btod.o(CL$$btod_emul) refers to btod.o(CL$$btod_e2e) for _e2e + btod.o(CL$$btod_ediv) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + btod.o(CL$$btod_ediv) refers to btod.o(CL$$btod_div_common) for __btod_div_common + btod.o(CL$$btod_ediv) refers to btod.o(CL$$btod_e2e) for _e2e + btod.o(CL$$btod_emuld) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + btod.o(CL$$btod_emuld) refers to btod.o(CL$$btod_mult_common) for __btod_mult_common + btod.o(CL$$btod_emuld) refers to btod.o(CL$$btod_e2d) for _e2d + btod.o(CL$$btod_edivd) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + btod.o(CL$$btod_edivd) refers to btod.o(CL$$btod_div_common) for __btod_div_common + btod.o(CL$$btod_edivd) refers to btod.o(CL$$btod_e2d) for _e2d + btod.o(CL$$btod_e2e) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + btod.o(CL$$btod_e2d) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + btod.o(CL$$btod_e2d) refers to btod.o(CL$$btod_e2e) for _e2e + btod.o(CL$$btod_mult_common) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + btod.o(CL$$btod_div_common) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + lc_numeric_c.o(locale$$data) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000016) for __rt_lib_init_lc_numeric_2 + lc_numeric_c.o(locale$$code) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000016) for __rt_lib_init_lc_numeric_2 + lc_numeric_c.o(locale$$code) refers to strcmpv7m.o(.text) for strcmp + lc_numeric_c.o(locale$$code) refers to lc_numeric_c.o(locale$$data) for __lcnum_c_name + exit.o(.text) refers to rtexit.o(.ARM.Collect$$rtexit$$00000000) for __rt_exit + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000002E) for __rt_lib_init_alloca_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000002C) for __rt_lib_init_argv_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001B) for __rt_lib_init_atexit_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000021) for __rt_lib_init_clock_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000032) for __rt_lib_init_cpp_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000030) for __rt_lib_init_exceptions_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000002) for __rt_lib_init_fp_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001F) for __rt_lib_init_fp_trap_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000023) for __rt_lib_init_getenv_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000A) for __rt_lib_init_heap_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000011) for __rt_lib_init_lc_collate_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000013) for __rt_lib_init_lc_ctype_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000015) for __rt_lib_init_lc_monetary_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000017) for __rt_lib_init_lc_numeric_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000019) for __rt_lib_init_lc_time_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000004) for __rt_lib_init_preinit_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000E) for __rt_lib_init_rand_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000033) for __rt_lib_init_return + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001D) for __rt_lib_init_signal_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000025) for __rt_lib_init_stdio_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000C) for __rt_lib_init_user_alloc_1 + istatus.o(x$fpl$ieeestatus) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + trapv.o(x$fpl$trapveneer) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for __rt_exit_exit + rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for __rt_exit_ls + rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000002) for __rt_exit_prels_1 + rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for __rt_exit_exit + rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for __rt_exit_ls + rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000002) for __rt_exit_prels_1 + rtexit.o(.ARM.exidx) refers to rtexit.o(.ARM.Collect$$rtexit$$00000000) for .ARM.Collect$$rtexit$$00000000 + lc_ctype_c.o(locale$$data) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000012) for __rt_lib_init_lc_ctype_2 + lc_ctype_c.o(locale$$code) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000012) for __rt_lib_init_lc_ctype_2 + lc_ctype_c.o(locale$$code) refers to strcmpv7m.o(.text) for strcmp + lc_ctype_c.o(locale$$code) refers to lc_ctype_c.o(locale$$data) for __lcctype_c_name + libinit2.o(.ARM.Collect$$libinit$$0000000F) refers (Weak) to rt_locale_intlibspace.o(.text) for __rt_locale + libinit2.o(.ARM.Collect$$libinit$$00000010) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F + libinit2.o(.ARM.Collect$$libinit$$00000012) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F + libinit2.o(.ARM.Collect$$libinit$$00000012) refers (Weak) to lc_ctype_c.o(locale$$code) for _get_lc_ctype + libinit2.o(.ARM.Collect$$libinit$$00000014) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F + libinit2.o(.ARM.Collect$$libinit$$00000016) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F + libinit2.o(.ARM.Collect$$libinit$$00000016) refers (Weak) to lc_numeric_c.o(locale$$code) for _get_lc_numeric + libinit2.o(.ARM.Collect$$libinit$$00000018) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F + libinit2.o(.ARM.Collect$$libinit$$00000026) refers to argv_veneer.o(.emb_text) for __ARM_argv_veneer + libinit2.o(.ARM.Collect$$libinit$$00000027) refers to argv_veneer.o(.emb_text) for __ARM_argv_veneer + rtexit2.o(.ARM.Collect$$rtexit$$00000003) refers to libshutdown.o(.ARM.Collect$$libshutdown$$00000000) for __rt_lib_shutdown + rtexit2.o(.ARM.Collect$$rtexit$$00000004) refers to sys_exit.o(.text) for _sys_exit + rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000001) for .ARM.Collect$$rtexit$$00000001 + rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for .ARM.Collect$$rtexit$$00000003 + rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for .ARM.Collect$$rtexit$$00000004 + argv_veneer.o(.emb_text) refers to no_argv.o(.text) for __ARM_get_argv + sys_exit.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_exit.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + _get_argv_nomalloc.o(.text) refers (Special) to hrguard.o(.text) for __heap_region$guard + _get_argv_nomalloc.o(.text) refers to defsig_rtmem_outer.o(.text) for __rt_SIGRTMEM + _get_argv_nomalloc.o(.text) refers to sys_command.o(.text) for _sys_command_string + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000002) for __rt_lib_shutdown_cpp_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000007) for __rt_lib_shutdown_fp_trap_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F) for __rt_lib_shutdown_heap_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000010) for __rt_lib_shutdown_return + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000A) for __rt_lib_shutdown_signal_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000004) for __rt_lib_shutdown_stdio_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C) for __rt_lib_shutdown_user_alloc_1 + sys_command.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_command.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + defsig_rtmem_outer.o(.text) refers to defsig_rtmem_inner.o(.text) for __rt_SIGRTMEM_inner + defsig_rtmem_outer.o(.text) refers to defsig_exit.o(.text) for __sig_exit + defsig_rtmem_formal.o(.text) refers to rt_raise.o(.text) for __rt_raise + rt_raise.o(.text) refers to __raise.o(.text) for __raise + rt_raise.o(.text) refers to sys_exit.o(.text) for _sys_exit + defsig_exit.o(.text) refers to sys_exit.o(.text) for _sys_exit + defsig_rtmem_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + __raise.o(.text) refers to defsig.o(CL$$defsig) for __default_signal_handler + defsig_general.o(.text) refers to sys_wrch.o(.text) for _ttywrch + sys_wrch.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_wrch.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + defsig.o(CL$$defsig) refers to defsig_rtmem_inner.o(.text) for __rt_SIGRTMEM_inner + defsig_abrt_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_fpe_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_rtred_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_stak_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_pvfn_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_cppl_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_segv_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_other.o(.text) refers to defsig_general.o(.text) for __default_signal_display + + +============================================================================== + +Removing Unused input sections from the image. + + Removing core_cm3.o(.emb_text), (32 bytes). + Removing global.o(i.CRC16_FirmtoEE), (60 bytes). + Removing global.o(i.GetID), (84 bytes). + Removing global.o(i.GetStrFromJson), (98 bytes). + Removing global.o(i.int_str_len), (34 bytes). + Removing global.o(i.uint_str_len), (112 bytes). + Removing global.o(.bss), (80 bytes). + Removing global.o(.bss), (72 bytes). + Removing global.o(.data), (2 bytes). + Removing global.o(.data), (2 bytes). + Removing global.o(.data), (2 bytes). + Removing global.o(.data), (2 bytes). + Removing global.o(.data), (2 bytes). + Removing system_stm32f10x.o(i.SystemCoreClockUpdate), (100 bytes). + Removing system_stm32f10x.o(.data), (20 bytes). + Removing gpio.o(i.LED_ALL_OFF), (30 bytes). + Removing gpio.o(i.LED_ALL_ON), (30 bytes). + Removing gpio.o(i.LED_ALL_Toggle), (72 bytes). + Removing gpio.o(i.LED_RST_Toggle), (44 bytes). + Removing gpio.o(i.MCU_BalanceProcess), (124 bytes). + Removing gpio.o(i.POWER_Check), (40 bytes). + Removing gpio.o(i.POWER_Ctrl), (108 bytes). + Removing gpio.o(i.POWER_Off), (32 bytes). + Removing gpio.o(i.POWER_On), (32 bytes). + Removing gpio.o(.data), (1 bytes). + Removing gpio.o(.data), (1 bytes). + Removing gpio.o(.data), (1 bytes). + Removing gpio.o(.data), (1 bytes). + Removing tim.o(i.TIMER_IsOther), (32 bytes). + Removing afe_sh3673520.o(.data), (1 bytes). + Removing afe_sh3673520.o(.data), (1 bytes). + Removing afe_sh3673520.o(.data), (1 bytes). + Removing afe_sh3673520.o(.data), (1 bytes). + Removing afe_sh3673520.o(.data), (1 bytes). + Removing afe_sh3673520.o(.data), (1 bytes). + Removing afe_sh3673520.o(.data), (1 bytes). + Removing afe_sh3673520.o(.data), (1 bytes). + Removing afe_sh3673520.o(.data), (1 bytes). + Removing afe_sh3673520.o(.data), (1 bytes). + Removing afe_sh3673520.o(.data), (1 bytes). + Removing afe_sh3673520.o(.data), (1 bytes). + Removing afe_sh3673520.o(.data), (1 bytes). + Removing screen.o(i.SCR_KeepLight0), (20 bytes). + Removing screen.o(i.SCR_Send_RecordTime), (176 bytes). + Removing screen.o(i.SCR_Send_TimeCount), (56 bytes). + Removing screen.o(i.Screen_ClearFlg), (2 bytes). + Removing screen.o(.bss), (41 bytes). + Removing screen.o(.data), (4 bytes). + Removing screen.o(.data), (4 bytes). + Removing screen.o(.data), (7 bytes). + Removing screen.o(.data), (7 bytes). + Removing screen.o(.data), (7 bytes). + Removing screen.o(.data), (1 bytes). + Removing screen.o(.data), (1 bytes). + Removing screen.o(.data), (1 bytes). + Removing screen.o(.data), (1 bytes). + Removing screen.o(.data), (1 bytes). + Removing screen.o(.data), (1 bytes). + Removing screen.o(.data), (2 bytes). + Removing screen.o(.data), (1 bytes). + Removing screen.o(.data), (1 bytes). + Removing screen.o(.data), (1 bytes). + Removing screen.o(.data), (1 bytes). + Removing gasgauge.o(.data), (1 bytes). + Removing gasgauge.o(.data), (1 bytes). + Removing gasgauge.o(.data), (1 bytes). + Removing gasgauge.o(.data), (1 bytes). + Removing gasgauge.o(.data), (1 bytes). + Removing status.o(.bss), (55 bytes). + Removing status.o(.bss), (220 bytes). + Removing status.o(.bss), (16 bytes). + Removing status.o(.bss), (16 bytes). + Removing status.o(.data), (1 bytes). + Removing status.o(.data), (1 bytes). + Removing status.o(.data), (1 bytes). + Removing status.o(.data), (1 bytes). + Removing status.o(.data), (1 bytes). + Removing status.o(.data), (1 bytes). + Removing status.o(.data), (1 bytes). + Removing status.o(.data), (1 bytes). + Removing status.o(.data), (1 bytes). + Removing status.o(.data), (1 bytes). + Removing status.o(.data), (1 bytes). + Removing status.o(.data), (1 bytes). + Removing status.o(.data), (1 bytes). + Removing status.o(.data), (1 bytes). + Removing status.o(.data), (1 bytes). + Removing status.o(.data), (1 bytes). + Removing status.o(.data), (1 bytes). + Removing status.o(.data), (1 bytes). + Removing status.o(.data), (1 bytes). + Removing status.o(.data), (1 bytes). + Removing status.o(.data), (1 bytes). + Removing status.o(.data), (2 bytes). + Removing status.o(.data), (2 bytes). + Removing status.o(.data), (2 bytes). + Removing status.o(.data), (2 bytes). + Removing status.o(.data), (2 bytes). + Removing status.o(.data), (2 bytes). + Removing status.o(.data), (2 bytes). + Removing status.o(.data), (2 bytes). + Removing mbo26a.o(i.BLE_Close), (2 bytes). + Removing mbo26a.o(.bss), (34 bytes). + Removing mbo26a.o(.bss), (34 bytes). + Removing mbo26a.o(.bss), (256 bytes). + Removing lbs_transmit.o(i.gcj02_to_wgs84), (552 bytes). + Removing lbs_transmit.o(i.transform_lat), (504 bytes). + Removing lbs_transmit.o(i.transform_lon), (496 bytes). + Removing misc.o(i.NVIC_SetVectorTable), (20 bytes). + Removing misc.o(i.NVIC_SystemLPConfig), (24 bytes). + Removing misc.o(i.SysTick_CLKSourceConfig), (24 bytes). + Removing stm32f10x_adc.o(i.ADC_AnalogWatchdogCmd), (16 bytes). + Removing stm32f10x_adc.o(i.ADC_AnalogWatchdogSingleChannelConfig), (12 bytes). + Removing stm32f10x_adc.o(i.ADC_AnalogWatchdogThresholdsConfig), (6 bytes). + Removing stm32f10x_adc.o(i.ADC_AutoInjectedConvCmd), (20 bytes). + Removing stm32f10x_adc.o(i.ADC_ClearFlag), (6 bytes). + Removing stm32f10x_adc.o(i.ADC_ClearITPendingBit), (8 bytes). + Removing stm32f10x_adc.o(i.ADC_DMACmd), (20 bytes). + Removing stm32f10x_adc.o(i.ADC_DiscModeChannelCountConfig), (16 bytes). + Removing stm32f10x_adc.o(i.ADC_DiscModeCmd), (20 bytes). + Removing stm32f10x_adc.o(i.ADC_ExternalTrigConvCmd), (20 bytes). + Removing stm32f10x_adc.o(i.ADC_ExternalTrigInjectedConvCmd), (20 bytes). + Removing stm32f10x_adc.o(i.ADC_ExternalTrigInjectedConvConfig), (12 bytes). + Removing stm32f10x_adc.o(i.ADC_GetDualModeConversionValue), (12 bytes). + Removing stm32f10x_adc.o(i.ADC_GetITStatus), (28 bytes). + Removing stm32f10x_adc.o(i.ADC_GetInjectedConversionValue), (14 bytes). + Removing stm32f10x_adc.o(i.ADC_GetSoftwareStartConvStatus), (14 bytes). + Removing stm32f10x_adc.o(i.ADC_GetSoftwareStartInjectedConvCmdStatus), (14 bytes). + Removing stm32f10x_adc.o(i.ADC_ITConfig), (18 bytes). + Removing stm32f10x_adc.o(i.ADC_InjectedChannelConfig), (74 bytes). + Removing stm32f10x_adc.o(i.ADC_InjectedDiscModeCmd), (20 bytes). + Removing stm32f10x_adc.o(i.ADC_InjectedSequencerLengthConfig), (16 bytes). + Removing stm32f10x_adc.o(i.ADC_SetInjectedOffset), (10 bytes). + Removing stm32f10x_adc.o(i.ADC_SoftwareStartInjectedConvCmd), (20 bytes). + Removing stm32f10x_adc.o(i.ADC_StructInit), (18 bytes). + Removing stm32f10x_adc.o(i.ADC_TempSensorVrefintCmd), (28 bytes). + Removing stm32f10x_bkp.o(i.BKP_ClearFlag), (16 bytes). + Removing stm32f10x_bkp.o(i.BKP_ClearITPendingBit), (16 bytes). + Removing stm32f10x_bkp.o(i.BKP_GetFlagStatus), (12 bytes). + Removing stm32f10x_bkp.o(i.BKP_GetITStatus), (12 bytes). + Removing stm32f10x_bkp.o(i.BKP_ITConfig), (12 bytes). + Removing stm32f10x_bkp.o(i.BKP_RTCOutputConfig), (20 bytes). + Removing stm32f10x_bkp.o(i.BKP_SetRTCCalibrationValue), (20 bytes). + Removing stm32f10x_bkp.o(i.BKP_TamperPinCmd), (12 bytes). + Removing stm32f10x_bkp.o(i.BKP_TamperPinLevelConfig), (12 bytes). + Removing stm32f10x_can.o(i.CAN_CancelTransmit), (36 bytes). + Removing stm32f10x_can.o(i.CAN_ClearFlag), (48 bytes). + Removing stm32f10x_can.o(i.CAN_ClearITPendingBit), (120 bytes). + Removing stm32f10x_can.o(i.CAN_DBGFreeze), (20 bytes). + Removing stm32f10x_can.o(i.CAN_FIFORelease), (22 bytes). + Removing stm32f10x_can.o(i.CAN_GetFlagStatus), (52 bytes). + Removing stm32f10x_can.o(i.CAN_GetLSBTransmitErrorCounter), (8 bytes). + Removing stm32f10x_can.o(i.CAN_GetLastErrorCode), (10 bytes). + Removing stm32f10x_can.o(i.CAN_GetReceiveErrorCounter), (6 bytes). + Removing stm32f10x_can.o(i.CAN_MessagePending), (22 bytes). + Removing stm32f10x_can.o(i.CAN_OperatingModeRequest), (140 bytes). + Removing stm32f10x_can.o(i.CAN_SlaveStartBank), (44 bytes). + Removing stm32f10x_can.o(i.CAN_Sleep), (30 bytes). + Removing stm32f10x_can.o(i.CAN_TTComModeCmd), (90 bytes). + Removing stm32f10x_can.o(i.CAN_WakeUp), (40 bytes). + Removing stm32f10x_cec.o(i.CEC_ClearFlag), (32 bytes). + Removing stm32f10x_cec.o(i.CEC_ClearITPendingBit), (32 bytes). + Removing stm32f10x_cec.o(i.CEC_Cmd), (28 bytes). + Removing stm32f10x_cec.o(i.CEC_DeInit), (24 bytes). + Removing stm32f10x_cec.o(i.CEC_EndOfMessageCmd), (12 bytes). + Removing stm32f10x_cec.o(i.CEC_GetFlagStatus), (36 bytes). + Removing stm32f10x_cec.o(i.CEC_GetITStatus), (36 bytes). + Removing stm32f10x_cec.o(i.CEC_ITConfig), (12 bytes). + Removing stm32f10x_cec.o(i.CEC_Init), (24 bytes). + Removing stm32f10x_cec.o(i.CEC_OwnAddressConfig), (12 bytes). + Removing stm32f10x_cec.o(i.CEC_ReceiveDataByte), (12 bytes). + Removing stm32f10x_cec.o(i.CEC_SendDataByte), (12 bytes). + Removing stm32f10x_cec.o(i.CEC_SetPrescaler), (12 bytes). + Removing stm32f10x_cec.o(i.CEC_StartOfMessage), (16 bytes). + Removing stm32f10x_crc.o(i.CRC_CalcBlockCRC), (28 bytes). + Removing stm32f10x_crc.o(i.CRC_CalcCRC), (12 bytes). + Removing stm32f10x_crc.o(i.CRC_GetCRC), (12 bytes). + Removing stm32f10x_crc.o(i.CRC_GetIDRegister), (12 bytes). + Removing stm32f10x_crc.o(i.CRC_ResetDR), (12 bytes). + Removing stm32f10x_crc.o(i.CRC_SetIDRegister), (12 bytes). + Removing stm32f10x_dac.o(i.DAC_Cmd), (24 bytes). + Removing stm32f10x_dac.o(i.DAC_DMACmd), (24 bytes). + Removing stm32f10x_dac.o(i.DAC_DeInit), (24 bytes). + Removing stm32f10x_dac.o(i.DAC_DualSoftwareTriggerCmd), (28 bytes). + Removing stm32f10x_dac.o(i.DAC_GetDataOutputValue), (24 bytes). + Removing stm32f10x_dac.o(i.DAC_Init), (40 bytes). + Removing stm32f10x_dac.o(i.DAC_SetChannel1Data), (20 bytes). + Removing stm32f10x_dac.o(i.DAC_SetChannel2Data), (20 bytes). + Removing stm32f10x_dac.o(i.DAC_SetDualChannelData), (28 bytes). + Removing stm32f10x_dac.o(i.DAC_SoftwareTriggerCmd), (28 bytes). + Removing stm32f10x_dac.o(i.DAC_StructInit), (12 bytes). + Removing stm32f10x_dac.o(i.DAC_WaveGenerationCmd), (24 bytes). + Removing stm32f10x_dbgmcu.o(i.DBGMCU_Config), (24 bytes). + Removing stm32f10x_dbgmcu.o(i.DBGMCU_GetDEVID), (16 bytes). + Removing stm32f10x_dbgmcu.o(i.DBGMCU_GetREVID), (12 bytes). + Removing stm32f10x_dma.o(i.DMA_ClearFlag), (24 bytes). + Removing stm32f10x_dma.o(i.DMA_ClearITPendingBit), (24 bytes). + Removing stm32f10x_dma.o(i.DMA_Cmd), (22 bytes). + Removing stm32f10x_dma.o(i.DMA_DeInit), (228 bytes). + Removing stm32f10x_dma.o(i.DMA_GetCurrDataCounter), (6 bytes). + Removing stm32f10x_dma.o(i.DMA_GetFlagStatus), (32 bytes). + Removing stm32f10x_dma.o(i.DMA_GetITStatus), (32 bytes). + Removing stm32f10x_dma.o(i.DMA_ITConfig), (16 bytes). + Removing stm32f10x_dma.o(i.DMA_Init), (58 bytes). + Removing stm32f10x_dma.o(i.DMA_SetCurrDataCounter), (4 bytes). + Removing stm32f10x_dma.o(i.DMA_StructInit), (26 bytes). + Removing stm32f10x_exti.o(i.EXTI_ClearFlag), (12 bytes). + Removing stm32f10x_exti.o(i.EXTI_ClearITPendingBit), (12 bytes). + Removing stm32f10x_exti.o(i.EXTI_DeInit), (36 bytes). + Removing stm32f10x_exti.o(i.EXTI_GenerateSWInterrupt), (16 bytes). + Removing stm32f10x_exti.o(i.EXTI_GetFlagStatus), (20 bytes). + Removing stm32f10x_exti.o(i.EXTI_GetITStatus), (32 bytes). + Removing stm32f10x_exti.o(i.EXTI_Init), (112 bytes). + Removing stm32f10x_exti.o(i.EXTI_StructInit), (14 bytes). + Removing stm32f10x_flash.o(i.FLASH_EnableWriteProtection), (172 bytes). + Removing stm32f10x_flash.o(i.FLASH_EraseAllBank1Pages), (56 bytes). + Removing stm32f10x_flash.o(i.FLASH_EraseAllPages), (56 bytes). + Removing stm32f10x_flash.o(i.FLASH_EraseOptionBytes), (124 bytes). + Removing stm32f10x_flash.o(i.FLASH_GetFlagStatus), (32 bytes). + Removing stm32f10x_flash.o(i.FLASH_GetPrefetchBufferStatus), (20 bytes). + Removing stm32f10x_flash.o(i.FLASH_GetReadOutProtectionStatus), (20 bytes). + Removing stm32f10x_flash.o(i.FLASH_GetStatus), (40 bytes). + Removing stm32f10x_flash.o(i.FLASH_GetUserOptionByte), (12 bytes). + Removing stm32f10x_flash.o(i.FLASH_GetWriteProtectionOptionByte), (12 bytes). + Removing stm32f10x_flash.o(i.FLASH_HalfCycleAccessCmd), (24 bytes). + Removing stm32f10x_flash.o(i.FLASH_ITConfig), (24 bytes). + Removing stm32f10x_flash.o(i.FLASH_LockBank1), (16 bytes). + Removing stm32f10x_flash.o(i.FLASH_PrefetchBufferCmd), (24 bytes). + Removing stm32f10x_flash.o(i.FLASH_ProgramOptionByteData), (76 bytes). + Removing stm32f10x_flash.o(i.FLASH_ProgramWord), (80 bytes). + Removing stm32f10x_flash.o(i.FLASH_ReadOutProtection), (136 bytes). + Removing stm32f10x_flash.o(i.FLASH_SetLatency), (20 bytes). + Removing stm32f10x_flash.o(i.FLASH_UnlockBank1), (24 bytes). + Removing stm32f10x_flash.o(i.FLASH_UserOptionByteConfig), (96 bytes). + Removing stm32f10x_flash.o(i.FLASH_WaitForLastBank1Operation), (36 bytes). + Removing stm32f10x_fsmc.o(i.FSMC_ClearFlag), (38 bytes). + Removing stm32f10x_fsmc.o(i.FSMC_ClearITPendingBit), (44 bytes). + Removing stm32f10x_fsmc.o(i.FSMC_GetECC), (18 bytes). + Removing stm32f10x_fsmc.o(i.FSMC_GetFlagStatus), (40 bytes). + Removing stm32f10x_fsmc.o(i.FSMC_GetITStatus), (48 bytes). + Removing stm32f10x_fsmc.o(i.FSMC_ITConfig), (72 bytes). + Removing stm32f10x_fsmc.o(i.FSMC_NANDCmd), (56 bytes). + Removing stm32f10x_fsmc.o(i.FSMC_NANDDeInit), (40 bytes). + Removing stm32f10x_fsmc.o(i.FSMC_NANDECCCmd), (56 bytes). + Removing stm32f10x_fsmc.o(i.FSMC_NANDInit), (104 bytes). + Removing stm32f10x_fsmc.o(i.FSMC_NANDStructInit), (54 bytes). + Removing stm32f10x_fsmc.o(i.FSMC_NORSRAMCmd), (32 bytes). + Removing stm32f10x_fsmc.o(i.FSMC_NORSRAMDeInit), (40 bytes). + Removing stm32f10x_fsmc.o(i.FSMC_NORSRAMInit), (200 bytes). + Removing stm32f10x_fsmc.o(i.FSMC_NORSRAMStructInit), (98 bytes). + Removing stm32f10x_fsmc.o(i.FSMC_PCCARDCmd), (32 bytes). + Removing stm32f10x_fsmc.o(i.FSMC_PCCARDDeInit), (26 bytes). + Removing stm32f10x_fsmc.o(i.FSMC_PCCARDInit), (102 bytes). + Removing stm32f10x_fsmc.o(i.FSMC_PCCARDStructInit), (60 bytes). + Removing stm32f10x_gpio.o(i.GPIO_AFIODeInit), (22 bytes). + Removing stm32f10x_gpio.o(i.GPIO_DeInit), (180 bytes). + Removing stm32f10x_gpio.o(i.GPIO_ETH_MediaInterfaceConfig), (12 bytes). + Removing stm32f10x_gpio.o(i.GPIO_EXTILineConfig), (40 bytes). + Removing stm32f10x_gpio.o(i.GPIO_EventOutputCmd), (12 bytes). + Removing stm32f10x_gpio.o(i.GPIO_EventOutputConfig), (28 bytes). + Removing stm32f10x_gpio.o(i.GPIO_PinLockConfig), (16 bytes). + Removing stm32f10x_gpio.o(i.GPIO_ReadInputData), (6 bytes). + Removing stm32f10x_gpio.o(i.GPIO_ReadOutputData), (6 bytes). + Removing stm32f10x_gpio.o(i.GPIO_ReadOutputDataBit), (14 bytes). + Removing stm32f10x_gpio.o(i.GPIO_StructInit), (16 bytes). + Removing stm32f10x_gpio.o(i.GPIO_Write), (4 bytes). + Removing stm32f10x_gpio.o(i.GPIO_WriteBit), (10 bytes). + Removing stm32f10x_i2c.o(i.I2C_ARPCmd), (20 bytes). + Removing stm32f10x_i2c.o(i.I2C_CalculatePEC), (20 bytes). + Removing stm32f10x_i2c.o(i.I2C_ClearFlag), (6 bytes). + Removing stm32f10x_i2c.o(i.I2C_ClearITPendingBit), (6 bytes). + Removing stm32f10x_i2c.o(i.I2C_DMACmd), (20 bytes). + Removing stm32f10x_i2c.o(i.I2C_DMALastTransferCmd), (20 bytes). + Removing stm32f10x_i2c.o(i.I2C_DualAddressCmd), (20 bytes). + Removing stm32f10x_i2c.o(i.I2C_FastModeDutyCycleConfig), (22 bytes). + Removing stm32f10x_i2c.o(i.I2C_GeneralCallCmd), (20 bytes). + Removing stm32f10x_i2c.o(i.I2C_GetITStatus), (36 bytes). + Removing stm32f10x_i2c.o(i.I2C_GetLastEvent), (14 bytes). + Removing stm32f10x_i2c.o(i.I2C_GetPEC), (6 bytes). + Removing stm32f10x_i2c.o(i.I2C_ITConfig), (16 bytes). + Removing stm32f10x_i2c.o(i.I2C_NACKPositionConfig), (22 bytes). + Removing stm32f10x_i2c.o(i.I2C_OwnAddress2Config), (16 bytes). + Removing stm32f10x_i2c.o(i.I2C_PECPositionConfig), (22 bytes). + Removing stm32f10x_i2c.o(i.I2C_ReadRegister), (10 bytes). + Removing stm32f10x_i2c.o(i.I2C_SMBusAlertConfig), (22 bytes). + Removing stm32f10x_i2c.o(i.I2C_SoftwareResetCmd), (20 bytes). + Removing stm32f10x_i2c.o(i.I2C_StretchClockCmd), (20 bytes). + Removing stm32f10x_i2c.o(i.I2C_StructInit), (28 bytes). + Removing stm32f10x_i2c.o(i.I2C_TransmitPEC), (20 bytes). + Removing stm32f10x_iwdg.o(i.IWDG_GetFlagStatus), (20 bytes). + Removing stm32f10x_pwr.o(i.PWR_ClearFlag), (16 bytes). + Removing stm32f10x_pwr.o(i.PWR_DeInit), (24 bytes). + Removing stm32f10x_pwr.o(i.PWR_EnterSTANDBYMode), (32 bytes). + Removing stm32f10x_pwr.o(i.PWR_EnterSTOPMode), (52 bytes). + Removing stm32f10x_pwr.o(i.PWR_GetFlagStatus), (20 bytes). + Removing stm32f10x_pwr.o(i.PWR_PVDCmd), (12 bytes). + Removing stm32f10x_pwr.o(i.PWR_PVDLevelConfig), (20 bytes). + Removing stm32f10x_pwr.o(i.PWR_WakeUpPinCmd), (12 bytes). + Removing stm32f10x_rcc.o(i.RCC_AHBPeriphClockCmd), (24 bytes). + Removing stm32f10x_rcc.o(i.RCC_AdjustHSICalibrationValue), (20 bytes). + Removing stm32f10x_rcc.o(i.RCC_ClearFlag), (16 bytes). + Removing stm32f10x_rcc.o(i.RCC_ClearITPendingBit), (12 bytes). + Removing stm32f10x_rcc.o(i.RCC_ClockSecuritySystemCmd), (12 bytes). + Removing stm32f10x_rcc.o(i.RCC_DeInit), (64 bytes). + Removing stm32f10x_rcc.o(i.RCC_GetITStatus), (20 bytes). + Removing stm32f10x_rcc.o(i.RCC_GetSYSCLKSource), (16 bytes). + Removing stm32f10x_rcc.o(i.RCC_HCLKConfig), (20 bytes). + Removing stm32f10x_rcc.o(i.RCC_HSEConfig), (52 bytes). + Removing stm32f10x_rcc.o(i.RCC_HSICmd), (12 bytes). + Removing stm32f10x_rcc.o(i.RCC_ITConfig), (24 bytes). + Removing stm32f10x_rcc.o(i.RCC_LSICmd), (12 bytes). + Removing stm32f10x_rcc.o(i.RCC_MCOConfig), (12 bytes). + Removing stm32f10x_rcc.o(i.RCC_PCLK1Config), (20 bytes). + Removing stm32f10x_rcc.o(i.RCC_PCLK2Config), (20 bytes). + Removing stm32f10x_rcc.o(i.RCC_PLLCmd), (12 bytes). + Removing stm32f10x_rcc.o(i.RCC_PLLConfig), (20 bytes). + Removing stm32f10x_rcc.o(i.RCC_SYSCLKConfig), (20 bytes). + Removing stm32f10x_rcc.o(i.RCC_USBCLKConfig), (12 bytes). + Removing stm32f10x_rcc.o(i.RCC_WaitForHSEStartUp), (44 bytes). + Removing stm32f10x_rtc.o(i.RTC_ClearFlag), (16 bytes). + Removing stm32f10x_rtc.o(i.RTC_ClearITPendingBit), (16 bytes). + Removing stm32f10x_rtc.o(i.RTC_GetDivider), (24 bytes). + Removing stm32f10x_rtc.o(i.RTC_GetFlagStatus), (20 bytes). + Removing stm32f10x_rtc.o(i.RTC_GetITStatus), (32 bytes). + Removing stm32f10x_rtc.o(i.RTC_SetAlarm), (32 bytes). + Removing stm32f10x_sdio.o(i.SDIO_CEATAITCmd), (16 bytes). + Removing stm32f10x_sdio.o(i.SDIO_ClearFlag), (12 bytes). + Removing stm32f10x_sdio.o(i.SDIO_ClearITPendingBit), (12 bytes). + Removing stm32f10x_sdio.o(i.SDIO_ClockCmd), (12 bytes). + Removing stm32f10x_sdio.o(i.SDIO_CmdStructInit), (14 bytes). + Removing stm32f10x_sdio.o(i.SDIO_CommandCompletionCmd), (12 bytes). + Removing stm32f10x_sdio.o(i.SDIO_DMACmd), (12 bytes). + Removing stm32f10x_sdio.o(i.SDIO_DataConfig), (44 bytes). + Removing stm32f10x_sdio.o(i.SDIO_DataStructInit), (20 bytes). + Removing stm32f10x_sdio.o(i.SDIO_DeInit), (36 bytes). + Removing stm32f10x_sdio.o(i.SDIO_GetCommandResponse), (12 bytes). + Removing stm32f10x_sdio.o(i.SDIO_GetDataCounter), (12 bytes). + Removing stm32f10x_sdio.o(i.SDIO_GetFIFOCount), (12 bytes). + Removing stm32f10x_sdio.o(i.SDIO_GetFlagStatus), (20 bytes). + Removing stm32f10x_sdio.o(i.SDIO_GetITStatus), (20 bytes). + Removing stm32f10x_sdio.o(i.SDIO_GetPowerState), (16 bytes). + Removing stm32f10x_sdio.o(i.SDIO_GetResponse), (16 bytes). + Removing stm32f10x_sdio.o(i.SDIO_ITConfig), (24 bytes). + Removing stm32f10x_sdio.o(i.SDIO_Init), (44 bytes). + Removing stm32f10x_sdio.o(i.SDIO_ReadData), (12 bytes). + Removing stm32f10x_sdio.o(i.SDIO_SendCEATACmd), (12 bytes). + Removing stm32f10x_sdio.o(i.SDIO_SendCommand), (40 bytes). + Removing stm32f10x_sdio.o(i.SDIO_SendSDIOSuspendCmd), (12 bytes). + Removing stm32f10x_sdio.o(i.SDIO_SetPowerState), (12 bytes). + Removing stm32f10x_sdio.o(i.SDIO_SetSDIOOperation), (12 bytes). + Removing stm32f10x_sdio.o(i.SDIO_SetSDIOReadWaitMode), (12 bytes). + Removing stm32f10x_sdio.o(i.SDIO_StartSDIOReadWait), (12 bytes). + Removing stm32f10x_sdio.o(i.SDIO_StopSDIOReadWait), (12 bytes). + Removing stm32f10x_sdio.o(i.SDIO_StructInit), (16 bytes). + Removing stm32f10x_sdio.o(i.SDIO_WriteData), (12 bytes). + Removing stm32f10x_spi.o(i.I2S_Cmd), (20 bytes). + Removing stm32f10x_spi.o(i.I2S_Init), (152 bytes). + Removing stm32f10x_spi.o(i.I2S_StructInit), (18 bytes). + Removing stm32f10x_spi.o(i.SPI_BiDirectionalLineConfig), (22 bytes). + Removing stm32f10x_spi.o(i.SPI_CalculateCRC), (20 bytes). + Removing stm32f10x_spi.o(i.SPI_DataSizeConfig), (16 bytes). + Removing stm32f10x_spi.o(i.SPI_GetCRC), (12 bytes). + Removing stm32f10x_spi.o(i.SPI_GetCRCPolynomial), (4 bytes). + Removing stm32f10x_spi.o(i.SPI_I2S_ClearFlag), (6 bytes). + Removing stm32f10x_spi.o(i.SPI_I2S_ClearITPendingBit), (14 bytes). + Removing stm32f10x_spi.o(i.SPI_I2S_DMACmd), (16 bytes). + Removing stm32f10x_spi.o(i.SPI_I2S_GetITStatus), (42 bytes). + Removing stm32f10x_spi.o(i.SPI_I2S_ITConfig), (24 bytes). + Removing stm32f10x_spi.o(i.SPI_NSSInternalSoftwareConfig), (24 bytes). + Removing stm32f10x_spi.o(i.SPI_SSOutputCmd), (20 bytes). + Removing stm32f10x_spi.o(i.SPI_StructInit), (24 bytes). + Removing stm32f10x_spi.o(i.SPI_TransmitCRC), (10 bytes). + Removing stm32f10x_tim.o(i.TI1_Config), (108 bytes). + Removing stm32f10x_tim.o(i.TI2_Config), (124 bytes). + Removing stm32f10x_tim.o(i.TIM_BDTRConfig), (34 bytes). + Removing stm32f10x_tim.o(i.TIM_BDTRStructInit), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_CCPreloadControl), (20 bytes). + Removing stm32f10x_tim.o(i.TIM_CCxCmd), (22 bytes). + Removing stm32f10x_tim.o(i.TIM_CCxNCmd), (22 bytes). + Removing stm32f10x_tim.o(i.TIM_ClearFlag), (6 bytes). + Removing stm32f10x_tim.o(i.TIM_ClearOC1Ref), (12 bytes). + Removing stm32f10x_tim.o(i.TIM_ClearOC2Ref), (20 bytes). + Removing stm32f10x_tim.o(i.TIM_ClearOC3Ref), (12 bytes). + Removing stm32f10x_tim.o(i.TIM_ClearOC4Ref), (20 bytes). + Removing stm32f10x_tim.o(i.TIM_CounterModeConfig), (12 bytes). + Removing stm32f10x_tim.o(i.TIM_DMACmd), (16 bytes). + Removing stm32f10x_tim.o(i.TIM_DMAConfig), (8 bytes). + Removing stm32f10x_tim.o(i.TIM_DeInit), (368 bytes). + Removing stm32f10x_tim.o(i.TIM_ETRClockMode1Config), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_ETRClockMode2Config), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_ETRConfig), (24 bytes). + Removing stm32f10x_tim.o(i.TIM_EncoderInterfaceConfig), (50 bytes). + Removing stm32f10x_tim.o(i.TIM_ForcedOC1Config), (12 bytes). + Removing stm32f10x_tim.o(i.TIM_ForcedOC2Config), (20 bytes). + Removing stm32f10x_tim.o(i.TIM_ForcedOC3Config), (12 bytes). + Removing stm32f10x_tim.o(i.TIM_ForcedOC4Config), (20 bytes). + Removing stm32f10x_tim.o(i.TIM_GenerateEvent), (4 bytes). + Removing stm32f10x_tim.o(i.TIM_GetCapture1), (4 bytes). + Removing stm32f10x_tim.o(i.TIM_GetCapture2), (4 bytes). + Removing stm32f10x_tim.o(i.TIM_GetCapture3), (4 bytes). + Removing stm32f10x_tim.o(i.TIM_GetCapture4), (6 bytes). + Removing stm32f10x_tim.o(i.TIM_GetCounter), (4 bytes). + Removing stm32f10x_tim.o(i.TIM_GetFlagStatus), (14 bytes). + Removing stm32f10x_tim.o(i.TIM_GetPrescaler), (4 bytes). + Removing stm32f10x_tim.o(i.TIM_ICInit), (300 bytes). + Removing stm32f10x_tim.o(i.TIM_ICStructInit), (16 bytes). + Removing stm32f10x_tim.o(i.TIM_ITRxExternalClockConfig), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_InternalClockConfig), (10 bytes). + Removing stm32f10x_tim.o(i.TIM_OC1FastConfig), (12 bytes). + Removing stm32f10x_tim.o(i.TIM_OC1Init), (128 bytes). + Removing stm32f10x_tim.o(i.TIM_OC1NPolarityConfig), (12 bytes). + Removing stm32f10x_tim.o(i.TIM_OC1PolarityConfig), (12 bytes). + Removing stm32f10x_tim.o(i.TIM_OC1PreloadConfig), (12 bytes). + Removing stm32f10x_tim.o(i.TIM_OC2FastConfig), (20 bytes). + Removing stm32f10x_tim.o(i.TIM_OC2Init), (128 bytes). + Removing stm32f10x_tim.o(i.TIM_OC2NPolarityConfig), (20 bytes). + Removing stm32f10x_tim.o(i.TIM_OC2PolarityConfig), (20 bytes). + Removing stm32f10x_tim.o(i.TIM_OC2PreloadConfig), (20 bytes). + Removing stm32f10x_tim.o(i.TIM_OC3FastConfig), (12 bytes). + Removing stm32f10x_tim.o(i.TIM_OC3Init), (124 bytes). + Removing stm32f10x_tim.o(i.TIM_OC3NPolarityConfig), (20 bytes). + Removing stm32f10x_tim.o(i.TIM_OC3PolarityConfig), (20 bytes). + Removing stm32f10x_tim.o(i.TIM_OC3PreloadConfig), (12 bytes). + Removing stm32f10x_tim.o(i.TIM_OC4FastConfig), (20 bytes). + Removing stm32f10x_tim.o(i.TIM_OC4PolarityConfig), (20 bytes). + Removing stm32f10x_tim.o(i.TIM_OCStructInit), (20 bytes). + Removing stm32f10x_tim.o(i.TIM_PWMIConfig), (108 bytes). + Removing stm32f10x_tim.o(i.TIM_PrescalerConfig), (6 bytes). + Removing stm32f10x_tim.o(i.TIM_SelectCCDMA), (20 bytes). + Removing stm32f10x_tim.o(i.TIM_SelectCOM), (20 bytes). + Removing stm32f10x_tim.o(i.TIM_SelectHallSensor), (20 bytes). + Removing stm32f10x_tim.o(i.TIM_SelectInputTrigger), (12 bytes). + Removing stm32f10x_tim.o(i.TIM_SelectMasterSlaveMode), (16 bytes). + Removing stm32f10x_tim.o(i.TIM_SelectOCxM), (70 bytes). + Removing stm32f10x_tim.o(i.TIM_SelectOnePulseMode), (16 bytes). + Removing stm32f10x_tim.o(i.TIM_SelectOutputTrigger), (16 bytes). + Removing stm32f10x_tim.o(i.TIM_SelectSlaveMode), (16 bytes). + Removing stm32f10x_tim.o(i.TIM_SetAutoreload), (4 bytes). + Removing stm32f10x_tim.o(i.TIM_SetClockDivision), (16 bytes). + Removing stm32f10x_tim.o(i.TIM_SetCompare1), (4 bytes). + Removing stm32f10x_tim.o(i.TIM_SetCompare2), (4 bytes). + Removing stm32f10x_tim.o(i.TIM_SetCompare3), (4 bytes). + Removing stm32f10x_tim.o(i.TIM_SetIC1Prescaler), (16 bytes). + Removing stm32f10x_tim.o(i.TIM_SetIC2Prescaler), (24 bytes). + Removing stm32f10x_tim.o(i.TIM_SetIC3Prescaler), (16 bytes). + Removing stm32f10x_tim.o(i.TIM_SetIC4Prescaler), (24 bytes). + Removing stm32f10x_tim.o(i.TIM_TIxExternalClockConfig), (46 bytes). + Removing stm32f10x_tim.o(i.TIM_TimeBaseStructInit), (18 bytes). + Removing stm32f10x_tim.o(i.TIM_UpdateDisableConfig), (20 bytes). + Removing stm32f10x_tim.o(i.TIM_UpdateRequestConfig), (20 bytes). + Removing stm32f10x_usart.o(i.USART_ClearFlag), (6 bytes). + Removing stm32f10x_usart.o(i.USART_ClearITPendingBit), (12 bytes). + Removing stm32f10x_usart.o(i.USART_ClockInit), (30 bytes). + Removing stm32f10x_usart.o(i.USART_ClockStructInit), (12 bytes). + Removing stm32f10x_usart.o(i.USART_DMACmd), (16 bytes). + Removing stm32f10x_usart.o(i.USART_DeInit), (116 bytes). + Removing stm32f10x_usart.o(i.USART_HalfDuplexCmd), (20 bytes). + Removing stm32f10x_usart.o(i.USART_IrDACmd), (20 bytes). + Removing stm32f10x_usart.o(i.USART_IrDAConfig), (16 bytes). + Removing stm32f10x_usart.o(i.USART_LINBreakDetectLengthConfig), (16 bytes). + Removing stm32f10x_usart.o(i.USART_LINCmd), (20 bytes). + Removing stm32f10x_usart.o(i.USART_OneBitMethodCmd), (20 bytes). + Removing stm32f10x_usart.o(i.USART_OverSampling8Cmd), (20 bytes). + Removing stm32f10x_usart.o(i.USART_ReceiverWakeUpCmd), (20 bytes). + Removing stm32f10x_usart.o(i.USART_SendBreak), (10 bytes). + Removing stm32f10x_usart.o(i.USART_SetAddress), (16 bytes). + Removing stm32f10x_usart.o(i.USART_SetGuardTime), (16 bytes). + Removing stm32f10x_usart.o(i.USART_SetPrescaler), (16 bytes). + Removing stm32f10x_usart.o(i.USART_SmartCardCmd), (20 bytes). + Removing stm32f10x_usart.o(i.USART_SmartCardNACKCmd), (20 bytes). + Removing stm32f10x_usart.o(i.USART_StructInit), (22 bytes). + Removing stm32f10x_usart.o(i.USART_WakeUpConfig), (16 bytes). + Removing stm32f10x_wwdg.o(i.WWDG_ClearFlag), (12 bytes). + Removing stm32f10x_wwdg.o(i.WWDG_DeInit), (24 bytes). + Removing stm32f10x_wwdg.o(i.WWDG_Enable), (16 bytes). + Removing stm32f10x_wwdg.o(i.WWDG_EnableIT), (16 bytes). + Removing stm32f10x_wwdg.o(i.WWDG_GetFlagStatus), (12 bytes). + Removing stm32f10x_wwdg.o(i.WWDG_SetCounter), (16 bytes). + Removing stm32f10x_wwdg.o(i.WWDG_SetPrescaler), (20 bytes). + Removing stm32f10x_wwdg.o(i.WWDG_SetWindowValue), (28 bytes). + Removing protocolswitch_p1.o(i.CAN_Protocol_Afore), (1016 bytes). + Removing protocolswitch_p1.o(i.CAN_Protocol_Aiswei), (964 bytes). + Removing protocolswitch_p1.o(i.CAN_Protocol_GoodWe), (804 bytes). + Removing protocolswitch_p1.o(i.CAN_Protocol_MUST), (592 bytes). + Removing protocolswitch_p1.o(i.CAN_Protocol_Megarevo), (664 bytes). + Removing protocolswitch_p1.o(i.CAN_Protocol_Sorotec), (892 bytes). + Removing protocolswitch_p1.o(i.CAN_Protocol_Victron), (1248 bytes). + Removing protocolswitch_p1.o(i.MOD_Protocol_Sorotec), (4 bytes). + Removing protocolswitch_p2.o(i.CAN_Protocol_AlpSolarr), (684 bytes). + Removing protocolswitch_p2.o(i.CAN_Protocol_Luxpower), (744 bytes). + Removing protocolswitch_p2.o(i.CAN_Protocol_SMA), (880 bytes). + Removing protocolswitch_p2.o(i.CAN_Protocol_Schneider), (836 bytes). + Removing protocolswitch_p2.o(i.CAN_Protocol_Sunways), (1478 bytes). + Removing protocolswitch_p2.o(i.MOD_Protocol_COSUPER), (720 bytes). + Removing protocolswitch_p2.o(i.MOD_Protocol_SAKO), (4 bytes). + Removing protocolswitch_p2.o(i.MOD_Protocol_SMK), (252 bytes). + Removing protocolswitch_p2.o(i.MOD_Protocol_SNADI), (2 bytes). + Removing protocolswitch_p2.o(i.MOD_Protocol_SRNE), (672 bytes). + Removing protocolswitch_p2.o(i.MOD_Protocol_invt), (2 bytes). + +499 unused section(s) (total 27090 bytes) removed from the image. + +============================================================================== + +Image Symbol Table + + Local Symbols + + Symbol Name Value Ov Type Size Object(Section) + + ../clib/angel/boardlib.s 0x00000000 Number 0 boardinit1.o ABSOLUTE + ../clib/angel/boardlib.s 0x00000000 Number 0 boardshut.o ABSOLUTE + ../clib/angel/boardlib.s 0x00000000 Number 0 boardinit3.o ABSOLUTE + ../clib/angel/boardlib.s 0x00000000 Number 0 boardinit2.o ABSOLUTE + ../clib/angel/dczerorl2.s 0x00000000 Number 0 __dczerorl2.o ABSOLUTE + ../clib/angel/handlers.s 0x00000000 Number 0 __scatter_zi.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 __rtentry.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 __rtentry4.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 rtexit2.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 rtexit.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 __rtentry2.o ABSOLUTE + ../clib/angel/rt.s 0x00000000 Number 0 rt_ctype_table.o ABSOLUTE + ../clib/angel/rt.s 0x00000000 Number 0 rt_raise.o ABSOLUTE + ../clib/angel/rt.s 0x00000000 Number 0 rt_errno_addr_intlibspace.o ABSOLUTE + ../clib/angel/rt.s 0x00000000 Number 0 rt_errno_addr.o ABSOLUTE + ../clib/angel/rt.s 0x00000000 Number 0 rt_locale_intlibspace.o ABSOLUTE + ../clib/angel/rt.s 0x00000000 Number 0 rt_locale.o ABSOLUTE + ../clib/angel/scatter.s 0x00000000 Number 0 __scatter.o ABSOLUTE + ../clib/angel/startup.s 0x00000000 Number 0 __main.o ABSOLUTE + ../clib/angel/sys.s 0x00000000 Number 0 use_no_semi.o ABSOLUTE + ../clib/angel/sys.s 0x00000000 Number 0 sys_stackheap_outer.o ABSOLUTE + ../clib/angel/sys.s 0x00000000 Number 0 indicate_semi.o ABSOLUTE + ../clib/angel/sys.s 0x00000000 Number 0 libspace.o ABSOLUTE + ../clib/angel/sysapp.c 0x00000000 Number 0 sys_command.o ABSOLUTE + ../clib/angel/sysapp.c 0x00000000 Number 0 sys_wrch.o ABSOLUTE + ../clib/angel/sysapp.c 0x00000000 Number 0 sys_exit.o ABSOLUTE + ../clib/armsys.c 0x00000000 Number 0 no_argv.o ABSOLUTE + ../clib/armsys.c 0x00000000 Number 0 argv_veneer.o ABSOLUTE + ../clib/armsys.c 0x00000000 Number 0 argv_veneer.o ABSOLUTE + ../clib/armsys.c 0x00000000 Number 0 _get_argv_nomalloc.o ABSOLUTE + ../clib/bigflt.c 0x00000000 Number 0 bigflt0.o ABSOLUTE + ../clib/btod.s 0x00000000 Number 0 btod.o ABSOLUTE + ../clib/ctype.c 0x00000000 Number 0 isspace.o ABSOLUTE + ../clib/fenv.c 0x00000000 Number 0 _rserrno.o ABSOLUTE + ../clib/heapalloc.c 0x00000000 Number 0 hrguard.o ABSOLUTE + ../clib/heapaux.c 0x00000000 Number 0 heapauxi.o ABSOLUTE + ../clib/libinit.s 0x00000000 Number 0 libshutdown2.o ABSOLUTE + ../clib/libinit.s 0x00000000 Number 0 libinit2.o ABSOLUTE + ../clib/libinit.s 0x00000000 Number 0 libinit.o ABSOLUTE + ../clib/libinit.s 0x00000000 Number 0 libshutdown.o ABSOLUTE + ../clib/locale.c 0x00000000 Number 0 _wcrtomb.o ABSOLUTE + ../clib/locale.s 0x00000000 Number 0 lc_numeric_c.o ABSOLUTE + ../clib/locale.s 0x00000000 Number 0 lc_ctype_c.o ABSOLUTE + ../clib/longlong.s 0x00000000 Number 0 lludiv10.o ABSOLUTE + ../clib/memcpset.s 0x00000000 Number 0 rt_memcpy_w.o ABSOLUTE + ../clib/memcpset.s 0x00000000 Number 0 rt_memclr.o ABSOLUTE + ../clib/memcpset.s 0x00000000 Number 0 strcmpv7m.o ABSOLUTE + ../clib/memcpset.s 0x00000000 Number 0 strncpy.o ABSOLUTE + ../clib/memcpset.s 0x00000000 Number 0 rt_memclr_w.o ABSOLUTE + ../clib/memcpset.s 0x00000000 Number 0 aeabi_memset.o ABSOLUTE + ../clib/memcpset.s 0x00000000 Number 0 rt_memcpy_v6.o ABSOLUTE + ../clib/misc.s 0x00000000 Number 0 printf_stubs.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 vsnprintf.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __2sprintf.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_fp_infnan.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 noretval__2sprintf.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_pad.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_str.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_dec.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_truncate.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_wchar.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf_nopercent.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_fp_hex.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_fp_dec.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_hex_ll.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_hex_int.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_hex_int_ll.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_hex_ptr.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_hex_int_ptr.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_hex_ll_ptr.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_hex_int_ll_ptr.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf_flags.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf_ss.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf_flags_ss.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf_wp.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf_flags_wp.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf_ss_wp.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 __printf_flags_ss_wp.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_oct_int_ll.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_oct_int.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_oct_ll.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_longlong_dec.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_wctomb.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_char.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _snputc.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _sputc.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_char_common.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_charcount.o ABSOLUTE + ../clib/printf.c 0x00000000 Number 0 _printf_intcommon.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_lc.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_percent.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_s.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_l.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_d.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_llu.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_i.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_ll.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_f.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_c.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_e.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_a.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_percent_end.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_n.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_u.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_p.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_g.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_lld.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_x.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_lli.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_llx.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_o.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_llo.o ABSOLUTE + ../clib/printf_percent.s 0x00000000 Number 0 _printf_ls.o ABSOLUTE + ../clib/scanf.c 0x00000000 Number 0 __0sscanf.o ABSOLUTE + ../clib/scanf.c 0x00000000 Number 0 _scanf_int.o ABSOLUTE + ../clib/scanf.c 0x00000000 Number 0 _scanf.o ABSOLUTE + ../clib/scanf.c 0x00000000 Number 0 _sgetc.o ABSOLUTE + ../clib/scanf.c 0x00000000 Number 0 scanf_char.o ABSOLUTE + ../clib/scanf.c 0x00000000 Number 0 _chval.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_pvfn_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_stak_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_rtred_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_fpe_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_abrt_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 __raise.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_general.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_rtmem_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_exit.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_rtmem_outer.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_rtmem_formal.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_segv_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_other.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_cppl_inner.o ABSOLUTE + ../clib/signal.s 0x00000000 Number 0 defsig.o ABSOLUTE + ../clib/stdlib.c 0x00000000 Number 0 exit.o ABSOLUTE + ../clib/string.c 0x00000000 Number 0 strchr.o ABSOLUTE + ../clib/string.c 0x00000000 Number 0 strstr.o ABSOLUTE + ../clib/string.c 0x00000000 Number 0 memcmp.o ABSOLUTE + ../clib/string.c 0x00000000 Number 0 strcpy.o ABSOLUTE + ../clib/string.c 0x00000000 Number 0 strlen.o ABSOLUTE + ../fplib/daddsub.s 0x00000000 Number 0 daddsub_clz.o ABSOLUTE + ../fplib/dcheck1.s 0x00000000 Number 0 dcheck1.o ABSOLUTE + ../fplib/dcmpi.s 0x00000000 Number 0 dcmpi.o ABSOLUTE + ../fplib/ddiv.s 0x00000000 Number 0 ddiv.o ABSOLUTE + ../fplib/dfix.s 0x00000000 Number 0 dfix.o ABSOLUTE + ../fplib/dfixu.s 0x00000000 Number 0 dfixu.o ABSOLUTE + ../fplib/dflt.s 0x00000000 Number 0 dflt_clz.o ABSOLUTE + ../fplib/dleqf.s 0x00000000 Number 0 dleqf.o ABSOLUTE + ../fplib/dmul.s 0x00000000 Number 0 dmul.o ABSOLUTE + ../fplib/dnaninf.s 0x00000000 Number 0 dnaninf.o ABSOLUTE + ../fplib/dretinf.s 0x00000000 Number 0 dretinf.o ABSOLUTE + ../fplib/drleqf.s 0x00000000 Number 0 drleqf.o ABSOLUTE + ../fplib/dsqrt.s 0x00000000 Number 0 dsqrt_noumaal.o ABSOLUTE + ../fplib/f2d.s 0x00000000 Number 0 f2d.o ABSOLUTE + ../fplib/faddsub.s 0x00000000 Number 0 faddsub_clz.o ABSOLUTE + ../fplib/fdiv.s 0x00000000 Number 0 fdiv.o ABSOLUTE + ../fplib/ffixu.s 0x00000000 Number 0 ffixu.o ABSOLUTE + ../fplib/fflt.s 0x00000000 Number 0 fflt_clz.o ABSOLUTE + ../fplib/fmul.s 0x00000000 Number 0 fmul.o ABSOLUTE + ../fplib/fnaninf.s 0x00000000 Number 0 fnaninf.o ABSOLUTE + ../fplib/fpinit.s 0x00000000 Number 0 fpinit.o ABSOLUTE + ../fplib/fretinf.s 0x00000000 Number 0 fretinf.o ABSOLUTE + ../fplib/istatus.s 0x00000000 Number 0 istatus.o ABSOLUTE + ../fplib/printf1.s 0x00000000 Number 0 printf1.o ABSOLUTE + ../fplib/printf2.s 0x00000000 Number 0 printf2.o ABSOLUTE + ../fplib/printf2a.s 0x00000000 Number 0 printf2a.o ABSOLUTE + ../fplib/printf2b.s 0x00000000 Number 0 printf2b.o ABSOLUTE + ../fplib/retnan.s 0x00000000 Number 0 retnan.o ABSOLUTE + ../fplib/scalbn.s 0x00000000 Number 0 scalbn.o ABSOLUTE + ../fplib/trapv.s 0x00000000 Number 0 trapv.o ABSOLUTE + ../fplib/usenofp.s 0x00000000 Number 0 usenofp.o ABSOLUTE + ../mathlib/cos.c 0x00000000 Number 0 cos_x.o ABSOLUTE + ../mathlib/cos.c 0x00000000 Number 0 cos.o ABSOLUTE + ../mathlib/cos_i.c 0x00000000 Number 0 cos_i.o ABSOLUTE + ../mathlib/dunder.c 0x00000000 Number 0 dunder.o ABSOLUTE + ../mathlib/fpclassify.c 0x00000000 Number 0 fpclassify.o ABSOLUTE + ../mathlib/poly.c 0x00000000 Number 0 poly.o ABSOLUTE + ../mathlib/rred.c 0x00000000 Number 0 rred.o ABSOLUTE + ../mathlib/sin.c 0x00000000 Number 0 sin_x.o ABSOLUTE + ../mathlib/sin.c 0x00000000 Number 0 sin.o ABSOLUTE + ../mathlib/sin_i.c 0x00000000 Number 0 sin_i.o ABSOLUTE + ../mathlib/sin_i.c 0x00000000 Number 0 sin_i_x.o ABSOLUTE + ../mathlib/sqrt.c 0x00000000 Number 0 sqrt.o ABSOLUTE + ../mathlib/sqrt.c 0x00000000 Number 0 sqrt_x.o ABSOLUTE + ..\BSP\adc.c 0x00000000 Number 0 adc.o ABSOLUTE + ..\BSP\can.c 0x00000000 Number 0 can.o ABSOLUTE + ..\BSP\flash.c 0x00000000 Number 0 flash.o ABSOLUTE + ..\BSP\gpio.c 0x00000000 Number 0 gpio.o ABSOLUTE + ..\BSP\i2c.c 0x00000000 Number 0 i2c.o ABSOLUTE + ..\BSP\pwm.c 0x00000000 Number 0 pwm.o ABSOLUTE + ..\BSP\rtc.c 0x00000000 Number 0 rtc.o ABSOLUTE + ..\BSP\spi.c 0x00000000 Number 0 spi.o ABSOLUTE + ..\BSP\systick.c 0x00000000 Number 0 systick.o ABSOLUTE + ..\BSP\tim.c 0x00000000 Number 0 tim.o ABSOLUTE + ..\BSP\uart.c 0x00000000 Number 0 uart.o ABSOLUTE + ..\BSP\wdg.c 0x00000000 Number 0 wdg.o ABSOLUTE + ..\CORE\core_cm3.c 0x00000000 Number 0 core_cm3.o ABSOLUTE + ..\CORE\startup_stm32f10x_hd.s 0x00000000 Number 0 startup_stm32f10x_hd.o ABSOLUTE + ..\MOUDLE\AFE_SH3673520.c 0x00000000 Number 0 afe_sh3673520.o ABSOLUTE + ..\MOUDLE\GasGauge.c 0x00000000 Number 0 gasgauge.o ABSOLUTE + ..\MOUDLE\H7690C.c 0x00000000 Number 0 h7690c.o ABSOLUTE + ..\MOUDLE\LBS_Transmit.c 0x00000000 Number 0 lbs_transmit.o ABSOLUTE + ..\MOUDLE\MBO26A.c 0x00000000 Number 0 mbo26a.o ABSOLUTE + ..\MOUDLE\NTC.c 0x00000000 Number 0 ntc.o ABSOLUTE + ..\MOUDLE\OCV.c 0x00000000 Number 0 ocv.o ABSOLUTE + ..\MOUDLE\OTA.c 0x00000000 Number 0 ota.o ABSOLUTE + ..\MOUDLE\RS485_Modbus.c 0x00000000 Number 0 rs485_modbus.o ABSOLUTE + ..\MOUDLE\RS485_Modbus_Inverter.c 0x00000000 Number 0 rs485_modbus_inverter.o ABSOLUTE + ..\MOUDLE\SOE.c 0x00000000 Number 0 soe.o ABSOLUTE + ..\MOUDLE\Screen.c 0x00000000 Number 0 screen.o ABSOLUTE + ..\MOUDLE\Status.c 0x00000000 Number 0 status.o ABSOLUTE + ..\MOUDLE\YiBang.c 0x00000000 Number 0 yibang.o ABSOLUTE + ..\PROTOCOL\ProtocolSwitch_P1.c 0x00000000 Number 0 protocolswitch_p1.o ABSOLUTE + ..\PROTOCOL\ProtocolSwitch_P2.c 0x00000000 Number 0 protocolswitch_p2.o ABSOLUTE + ..\STM32F10x_FWLIB\src\misc.c 0x00000000 Number 0 misc.o ABSOLUTE + ..\STM32F10x_FWLIB\src\stm32f10x_adc.c 0x00000000 Number 0 stm32f10x_adc.o ABSOLUTE + ..\STM32F10x_FWLIB\src\stm32f10x_bkp.c 0x00000000 Number 0 stm32f10x_bkp.o ABSOLUTE + ..\STM32F10x_FWLIB\src\stm32f10x_can.c 0x00000000 Number 0 stm32f10x_can.o ABSOLUTE + ..\STM32F10x_FWLIB\src\stm32f10x_cec.c 0x00000000 Number 0 stm32f10x_cec.o ABSOLUTE + ..\STM32F10x_FWLIB\src\stm32f10x_crc.c 0x00000000 Number 0 stm32f10x_crc.o ABSOLUTE + ..\STM32F10x_FWLIB\src\stm32f10x_dac.c 0x00000000 Number 0 stm32f10x_dac.o ABSOLUTE + ..\STM32F10x_FWLIB\src\stm32f10x_dbgmcu.c 0x00000000 Number 0 stm32f10x_dbgmcu.o ABSOLUTE + ..\STM32F10x_FWLIB\src\stm32f10x_dma.c 0x00000000 Number 0 stm32f10x_dma.o ABSOLUTE + ..\STM32F10x_FWLIB\src\stm32f10x_exti.c 0x00000000 Number 0 stm32f10x_exti.o ABSOLUTE + ..\STM32F10x_FWLIB\src\stm32f10x_flash.c 0x00000000 Number 0 stm32f10x_flash.o ABSOLUTE + ..\STM32F10x_FWLIB\src\stm32f10x_fsmc.c 0x00000000 Number 0 stm32f10x_fsmc.o ABSOLUTE + ..\STM32F10x_FWLIB\src\stm32f10x_gpio.c 0x00000000 Number 0 stm32f10x_gpio.o ABSOLUTE + ..\STM32F10x_FWLIB\src\stm32f10x_i2c.c 0x00000000 Number 0 stm32f10x_i2c.o ABSOLUTE + ..\STM32F10x_FWLIB\src\stm32f10x_iwdg.c 0x00000000 Number 0 stm32f10x_iwdg.o ABSOLUTE + ..\STM32F10x_FWLIB\src\stm32f10x_pwr.c 0x00000000 Number 0 stm32f10x_pwr.o ABSOLUTE + ..\STM32F10x_FWLIB\src\stm32f10x_rcc.c 0x00000000 Number 0 stm32f10x_rcc.o ABSOLUTE + ..\STM32F10x_FWLIB\src\stm32f10x_rtc.c 0x00000000 Number 0 stm32f10x_rtc.o ABSOLUTE + ..\STM32F10x_FWLIB\src\stm32f10x_sdio.c 0x00000000 Number 0 stm32f10x_sdio.o ABSOLUTE + ..\STM32F10x_FWLIB\src\stm32f10x_spi.c 0x00000000 Number 0 stm32f10x_spi.o ABSOLUTE + ..\STM32F10x_FWLIB\src\stm32f10x_tim.c 0x00000000 Number 0 stm32f10x_tim.o ABSOLUTE + ..\STM32F10x_FWLIB\src\stm32f10x_usart.c 0x00000000 Number 0 stm32f10x_usart.o ABSOLUTE + ..\STM32F10x_FWLIB\src\stm32f10x_wwdg.c 0x00000000 Number 0 stm32f10x_wwdg.o ABSOLUTE + ..\\CORE\\core_cm3.c 0x00000000 Number 0 core_cm3.o ABSOLUTE + dc.s 0x00000000 Number 0 dc.o ABSOLUTE + global.c 0x00000000 Number 0 global.o ABSOLUTE + main.c 0x00000000 Number 0 main.o ABSOLUTE + stm32f10x_it.c 0x00000000 Number 0 stm32f10x_it.o ABSOLUTE + system_stm32f10x.c 0x00000000 Number 0 system_stm32f10x.o ABSOLUTE + RESET 0x08000000 Section 304 startup_stm32f10x_hd.o(RESET) + !!!main 0x08000130 Section 8 __main.o(!!!main) + !!!scatter 0x08000138 Section 52 __scatter.o(!!!scatter) + !!dczerorl2 0x0800016c Section 90 __dczerorl2.o(!!dczerorl2) + !!handler_zi 0x080001c8 Section 28 __scatter_zi.o(!!handler_zi) + .ARM.Collect$$_printf_percent$$00000000 0x080001e4 Section 0 _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) + .ARM.Collect$$_printf_percent$$00000001 0x080001e4 Section 6 _printf_n.o(.ARM.Collect$$_printf_percent$$00000001) + .ARM.Collect$$_printf_percent$$00000002 0x080001ea Section 6 _printf_p.o(.ARM.Collect$$_printf_percent$$00000002) + .ARM.Collect$$_printf_percent$$00000003 0x080001f0 Section 6 _printf_f.o(.ARM.Collect$$_printf_percent$$00000003) + .ARM.Collect$$_printf_percent$$00000004 0x080001f6 Section 6 _printf_e.o(.ARM.Collect$$_printf_percent$$00000004) + .ARM.Collect$$_printf_percent$$00000005 0x080001fc Section 6 _printf_g.o(.ARM.Collect$$_printf_percent$$00000005) + .ARM.Collect$$_printf_percent$$00000006 0x08000202 Section 6 _printf_a.o(.ARM.Collect$$_printf_percent$$00000006) + .ARM.Collect$$_printf_percent$$00000007 0x08000208 Section 10 _printf_ll.o(.ARM.Collect$$_printf_percent$$00000007) + .ARM.Collect$$_printf_percent$$00000008 0x08000212 Section 6 _printf_i.o(.ARM.Collect$$_printf_percent$$00000008) + .ARM.Collect$$_printf_percent$$00000009 0x08000218 Section 6 _printf_d.o(.ARM.Collect$$_printf_percent$$00000009) + .ARM.Collect$$_printf_percent$$0000000A 0x0800021e Section 6 _printf_u.o(.ARM.Collect$$_printf_percent$$0000000A) + .ARM.Collect$$_printf_percent$$0000000B 0x08000224 Section 6 _printf_o.o(.ARM.Collect$$_printf_percent$$0000000B) + .ARM.Collect$$_printf_percent$$0000000C 0x0800022a Section 6 _printf_x.o(.ARM.Collect$$_printf_percent$$0000000C) + .ARM.Collect$$_printf_percent$$0000000D 0x08000230 Section 6 _printf_lli.o(.ARM.Collect$$_printf_percent$$0000000D) + .ARM.Collect$$_printf_percent$$0000000E 0x08000236 Section 6 _printf_lld.o(.ARM.Collect$$_printf_percent$$0000000E) + .ARM.Collect$$_printf_percent$$0000000F 0x0800023c Section 6 _printf_llu.o(.ARM.Collect$$_printf_percent$$0000000F) + .ARM.Collect$$_printf_percent$$00000010 0x08000242 Section 6 _printf_llo.o(.ARM.Collect$$_printf_percent$$00000010) + .ARM.Collect$$_printf_percent$$00000011 0x08000248 Section 6 _printf_llx.o(.ARM.Collect$$_printf_percent$$00000011) + .ARM.Collect$$_printf_percent$$00000012 0x0800024e Section 10 _printf_l.o(.ARM.Collect$$_printf_percent$$00000012) + .ARM.Collect$$_printf_percent$$00000013 0x08000258 Section 6 _printf_c.o(.ARM.Collect$$_printf_percent$$00000013) + .ARM.Collect$$_printf_percent$$00000014 0x0800025e Section 6 _printf_s.o(.ARM.Collect$$_printf_percent$$00000014) + .ARM.Collect$$_printf_percent$$00000015 0x08000264 Section 6 _printf_lc.o(.ARM.Collect$$_printf_percent$$00000015) + .ARM.Collect$$_printf_percent$$00000016 0x0800026a Section 6 _printf_ls.o(.ARM.Collect$$_printf_percent$$00000016) + .ARM.Collect$$_printf_percent$$00000017 0x08000270 Section 4 _printf_percent_end.o(.ARM.Collect$$_printf_percent$$00000017) + .ARM.Collect$$libinit$$00000000 0x08000274 Section 2 libinit.o(.ARM.Collect$$libinit$$00000000) + .ARM.Collect$$libinit$$00000002 0x08000276 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000002) + .ARM.Collect$$libinit$$00000004 0x08000276 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000004) + .ARM.Collect$$libinit$$0000000A 0x08000276 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000000A) + .ARM.Collect$$libinit$$0000000C 0x08000276 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000000C) + .ARM.Collect$$libinit$$0000000E 0x08000276 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000000E) + .ARM.Collect$$libinit$$0000000F 0x08000276 Section 6 libinit2.o(.ARM.Collect$$libinit$$0000000F) + .ARM.Collect$$libinit$$00000011 0x0800027c Section 0 libinit2.o(.ARM.Collect$$libinit$$00000011) + .ARM.Collect$$libinit$$00000012 0x0800027c Section 12 libinit2.o(.ARM.Collect$$libinit$$00000012) + .ARM.Collect$$libinit$$00000013 0x08000288 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000013) + .ARM.Collect$$libinit$$00000015 0x08000288 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000015) + .ARM.Collect$$libinit$$00000016 0x08000288 Section 10 libinit2.o(.ARM.Collect$$libinit$$00000016) + .ARM.Collect$$libinit$$00000017 0x08000292 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000017) + .ARM.Collect$$libinit$$00000019 0x08000292 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000019) + .ARM.Collect$$libinit$$0000001B 0x08000292 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000001B) + .ARM.Collect$$libinit$$0000001D 0x08000292 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000001D) + .ARM.Collect$$libinit$$0000001F 0x08000292 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000001F) + .ARM.Collect$$libinit$$00000021 0x08000292 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000021) + .ARM.Collect$$libinit$$00000023 0x08000292 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000023) + .ARM.Collect$$libinit$$00000025 0x08000292 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000025) + .ARM.Collect$$libinit$$0000002C 0x08000292 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000002C) + .ARM.Collect$$libinit$$0000002E 0x08000292 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000002E) + .ARM.Collect$$libinit$$00000030 0x08000292 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000030) + .ARM.Collect$$libinit$$00000032 0x08000292 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000032) + .ARM.Collect$$libinit$$00000033 0x08000292 Section 2 libinit2.o(.ARM.Collect$$libinit$$00000033) + .ARM.Collect$$libshutdown$$00000000 0x08000294 Section 2 libshutdown.o(.ARM.Collect$$libshutdown$$00000000) + .ARM.Collect$$libshutdown$$00000002 0x08000296 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000002) + .ARM.Collect$$libshutdown$$00000004 0x08000296 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000004) + .ARM.Collect$$libshutdown$$00000007 0x08000296 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000007) + .ARM.Collect$$libshutdown$$0000000A 0x08000296 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000A) + .ARM.Collect$$libshutdown$$0000000C 0x08000296 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C) + .ARM.Collect$$libshutdown$$0000000F 0x08000296 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F) + .ARM.Collect$$libshutdown$$00000010 0x08000296 Section 2 libshutdown2.o(.ARM.Collect$$libshutdown$$00000010) + .ARM.Collect$$rtentry$$00000000 0x08000298 Section 0 __rtentry.o(.ARM.Collect$$rtentry$$00000000) + .ARM.Collect$$rtentry$$00000002 0x08000298 Section 0 __rtentry2.o(.ARM.Collect$$rtentry$$00000002) + .ARM.Collect$$rtentry$$00000004 0x08000298 Section 6 __rtentry4.o(.ARM.Collect$$rtentry$$00000004) + .ARM.Collect$$rtentry$$00000009 0x0800029e Section 0 __rtentry2.o(.ARM.Collect$$rtentry$$00000009) + .ARM.Collect$$rtentry$$0000000A 0x0800029e Section 4 __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) + .ARM.Collect$$rtentry$$0000000C 0x080002a2 Section 0 __rtentry2.o(.ARM.Collect$$rtentry$$0000000C) + .ARM.Collect$$rtentry$$0000000D 0x080002a2 Section 8 __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) + .ARM.Collect$$rtexit$$00000000 0x080002aa Section 2 rtexit.o(.ARM.Collect$$rtexit$$00000000) + .ARM.Collect$$rtexit$$00000002 0x080002ac Section 0 rtexit2.o(.ARM.Collect$$rtexit$$00000002) + .ARM.Collect$$rtexit$$00000003 0x080002ac Section 4 rtexit2.o(.ARM.Collect$$rtexit$$00000003) + .ARM.Collect$$rtexit$$00000004 0x080002b0 Section 6 rtexit2.o(.ARM.Collect$$rtexit$$00000004) + .text 0x080002b8 Section 64 startup_stm32f10x_hd.o(.text) + .text 0x080002f8 Section 0 vsnprintf.o(.text) + .text 0x0800032c Section 0 __2sprintf.o(.text) + .text 0x08000358 Section 0 _printf_pad.o(.text) + .text 0x080003a6 Section 0 _printf_str.o(.text) + .text 0x080003f8 Section 0 _printf_dec.o(.text) + .text 0x08000470 Section 0 _printf_hex_int_ll_ptr.o(.text) + _printf_hex_common 0x08000471 Thumb Code 0 _printf_hex_int_ll_ptr.o(.text) + .text 0x08000504 Section 0 __printf_flags_ss_wp.o(.text) + .text 0x0800068c Section 0 __0sscanf.o(.text) + .text 0x080006c8 Section 0 _scanf_int.o(.text) + .text 0x08000814 Section 0 strchr.o(.text) + .text 0x08000828 Section 0 strstr.o(.text) + .text 0x0800084c Section 0 memcmp.o(.text) + .text 0x080008a4 Section 0 strcpy.o(.text) + .text 0x080008ec Section 0 strlen.o(.text) + .text 0x0800092a Section 138 rt_memcpy_v6.o(.text) + .text 0x080009b4 Section 100 rt_memcpy_w.o(.text) + .text 0x08000a18 Section 16 aeabi_memset.o(.text) + .text 0x08000a28 Section 68 rt_memclr.o(.text) + .text 0x08000a6c Section 78 rt_memclr_w.o(.text) + .text 0x08000aba Section 86 strncpy.o(.text) + .text 0x08000b10 Section 0 heapauxi.o(.text) + .text 0x08000b16 Section 0 _printf_truncate.o(.text) + .text 0x08000b3a Section 0 _printf_intcommon.o(.text) + .text 0x08000bec Section 0 _printf_charcount.o(.text) + .text 0x08000c14 Section 0 _printf_char_common.o(.text) + _printf_input_char 0x08000c15 Thumb Code 10 _printf_char_common.o(.text) + .text 0x08000c44 Section 0 _sputc.o(.text) + .text 0x08000c4e Section 0 _snputc.o(.text) + .text 0x08000c5e Section 0 _printf_char.o(.text) + .text 0x08000c8c Section 0 _printf_wctomb.o(.text) + .text 0x08000d48 Section 0 _printf_longlong_dec.o(.text) + .text 0x08000dc4 Section 0 _printf_oct_int_ll.o(.text) + _printf_longlong_oct_internal 0x08000dc5 Thumb Code 0 _printf_oct_int_ll.o(.text) + .text 0x08000e34 Section 0 _chval.o(.text) + .text 0x08000e50 Section 0 scanf_char.o(.text) + _scanf_char_input 0x08000e51 Thumb Code 12 scanf_char.o(.text) + .text 0x08000e7c Section 0 _sgetc.o(.text) + .text 0x08000ebc Section 138 lludiv10.o(.text) + .text 0x08000f46 Section 0 isspace.o(.text) + .text 0x08000f58 Section 0 _printf_fp_dec.o(.text) + _fp_digits 0x08000f5b Thumb Code 432 _printf_fp_dec.o(.text) + .text 0x08001378 Section 0 _printf_fp_hex.o(.text) + .text 0x08001674 Section 0 _printf_wchar.o(.text) + .text 0x080016a0 Section 0 _scanf.o(.text) + .text 0x08001a14 Section 0 _wcrtomb.o(.text) + .text 0x08001a54 Section 8 libspace.o(.text) + .text 0x08001a5c Section 74 sys_stackheap_outer.o(.text) + .text 0x08001aa8 Section 16 rt_ctype_table.o(.text) + .text 0x08001ab8 Section 8 rt_locale_intlibspace.o(.text) + .text 0x08001ac0 Section 0 _printf_fp_infnan.o(.text) + .text 0x08001b40 Section 0 bigflt0.o(.text) + .text 0x08001c24 Section 0 exit.o(.text) + .text 0x08001c38 Section 128 strcmpv7m.o(.text) + .text 0x08001cb8 Section 0 sys_exit.o(.text) + .text 0x08001cc4 Section 2 use_no_semi.o(.text) + .text 0x08001cc6 Section 0 indicate_semi.o(.text) + CL$$btod_d2e 0x08001cc6 Section 62 btod.o(CL$$btod_d2e) + CL$$btod_d2e_denorm_low 0x08001d04 Section 70 btod.o(CL$$btod_d2e_denorm_low) + CL$$btod_d2e_norm_op1 0x08001d4a Section 96 btod.o(CL$$btod_d2e_norm_op1) + CL$$btod_div_common 0x08001daa Section 824 btod.o(CL$$btod_div_common) + CL$$btod_e2e 0x080020e2 Section 220 btod.o(CL$$btod_e2e) + CL$$btod_ediv 0x080021be Section 42 btod.o(CL$$btod_ediv) + CL$$btod_emul 0x080021e8 Section 42 btod.o(CL$$btod_emul) + CL$$btod_mult_common 0x08002212 Section 580 btod.o(CL$$btod_mult_common) + i.ADC_Cmd 0x08002456 Section 0 stm32f10x_adc.o(i.ADC_Cmd) + i.ADC_DeInit 0x0800246c Section 0 stm32f10x_adc.o(i.ADC_DeInit) + i.ADC_GetCalibrationStatus 0x080024b0 Section 0 stm32f10x_adc.o(i.ADC_GetCalibrationStatus) + i.ADC_GetConversionValue 0x080024be Section 0 stm32f10x_adc.o(i.ADC_GetConversionValue) + i.ADC_GetFlagStatus 0x080024c4 Section 0 stm32f10x_adc.o(i.ADC_GetFlagStatus) + i.ADC_GetResetCalibrationStatus 0x080024d2 Section 0 stm32f10x_adc.o(i.ADC_GetResetCalibrationStatus) + i.ADC_GetVal 0x080024e0 Section 0 adc.o(i.ADC_GetVal) + i.ADC_Init 0x08002514 Section 0 stm32f10x_adc.o(i.ADC_Init) + i.ADC_RegularChannelConfig 0x0800255c Section 0 stm32f10x_adc.o(i.ADC_RegularChannelConfig) + i.ADC_ResetCalibration 0x080025d0 Section 0 stm32f10x_adc.o(i.ADC_ResetCalibration) + i.ADC_SoftwareStartConvCmd 0x080025da Section 0 stm32f10x_adc.o(i.ADC_SoftwareStartConvCmd) + i.ADC_StartCalibration 0x080025ee Section 0 stm32f10x_adc.o(i.ADC_StartCalibration) + i.ADDR_Assign_Moni 0x080025f8 Section 0 gpio.o(i.ADDR_Assign_Moni) + i.ADDR_Rank_Moni 0x08002650 Section 0 gpio.o(i.ADDR_Rank_Moni) + i.AFE_Ctrl 0x080026e8 Section 0 afe_sh3673520.o(i.AFE_Ctrl) + i.AFE_CurrentProcess 0x08002848 Section 0 afe_sh3673520.o(i.AFE_CurrentProcess) + i.AFE_ProtectProcess 0x080029f4 Section 0 afe_sh3673520.o(i.AFE_ProtectProcess) + i.AFE_Read 0x080030f2 Section 0 afe_sh3673520.o(i.AFE_Read) + i.AFE_ReadMulByte 0x08003128 Section 0 spi.o(i.AFE_ReadMulByte) + i.AFE_Reset 0x08003260 Section 0 spi.o(i.AFE_Reset) + i.AFE_TemperaProcess 0x080032f4 Section 0 afe_sh3673520.o(i.AFE_TemperaProcess) + i.AFE_VoltageProcess 0x08003398 Section 0 afe_sh3673520.o(i.AFE_VoltageProcess) + i.AFE_Write 0x08003788 Section 0 afe_sh3673520.o(i.AFE_Write) + i.AFE_WriteOneByte 0x080037d4 Section 0 spi.o(i.AFE_WriteOneByte) + i.Addr_Set 0x0800386c Section 0 global.o(i.Addr_Set) + i.BKP_DeInit 0x08003924 Section 0 stm32f10x_bkp.o(i.BKP_DeInit) + i.BKP_ReadBackupRegister 0x08003938 Section 0 stm32f10x_bkp.o(i.BKP_ReadBackupRegister) + i.BKP_WriteBackupRegister 0x08003948 Section 0 stm32f10x_bkp.o(i.BKP_WriteBackupRegister) + i.BLE_CheckName 0x08003958 Section 0 mbo26a.o(i.BLE_CheckName) + i.BLE_ClearBuf 0x080039f4 Section 0 mbo26a.o(i.BLE_ClearBuf) + i.BLE_ClearFlg 0x08003a0c Section 0 mbo26a.o(i.BLE_ClearFlg) + i.BLE_GETPARA 0x08003a20 Section 0 mbo26a.o(i.BLE_GETPARA) + i.BLE_IO_Init 0x08003aec Section 0 mbo26a.o(i.BLE_IO_Init) + i.BLE_IQ_Transmit 0x08003b24 Section 0 mbo26a.o(i.BLE_IQ_Transmit) + i.BLE_IQ_Update 0x08004d54 Section 0 mbo26a.o(i.BLE_IQ_Update) + i.BLE_IT_Receive 0x08005008 Section 0 mbo26a.o(i.BLE_IT_Receive) + i.BLE_IT_Update 0x08005038 Section 0 mbo26a.o(i.BLE_IT_Update) + i.BLE_Init 0x08005134 Section 0 mbo26a.o(i.BLE_Init) + i.BLE_Open 0x08005160 Section 0 mbo26a.o(i.BLE_Open) + i.BLE_PUTSRVC 0x08005164 Section 0 mbo26a.o(i.BLE_PUTSRVC) + i.BLE_Reset 0x08005298 Section 0 mbo26a.o(i.BLE_Reset) + i.BLE_SETPARA 0x080052c0 Section 0 mbo26a.o(i.BLE_SETPARA) + i.BLE_SetBaud 0x080053f4 Section 0 mbo26a.o(i.BLE_SetBaud) + i.BLE_TIM_Moni 0x0800541c Section 0 mbo26a.o(i.BLE_TIM_Moni) + i.BLE_WriteName 0x08005448 Section 0 mbo26a.o(i.BLE_WriteName) + i.BLE_printf 0x0800544c Section 0 mbo26a.o(i.BLE_printf) + i.BusFault_Handler 0x08005488 Section 0 stm32f10x_it.o(i.BusFault_Handler) + i.CALI_CurrentProcess 0x0800548c Section 0 afe_sh3673520.o(i.CALI_CurrentProcess) + i.CAN1_SendData 0x08005510 Section 0 can.o(i.CAN1_SendData) + i.CAN_DeInit 0x080055ac Section 0 stm32f10x_can.o(i.CAN_DeInit) + i.CAN_FilterInit 0x080055d8 Section 0 stm32f10x_can.o(i.CAN_FilterInit) + i.CAN_GetITStatus 0x080056a4 Section 0 stm32f10x_can.o(i.CAN_GetITStatus) + i.CAN_ITConfig 0x0800574c Section 0 stm32f10x_can.o(i.CAN_ITConfig) + i.CAN_Init 0x0800575c Section 0 stm32f10x_can.o(i.CAN_Init) + i.CAN_Protocol_Deye 0x08005844 Section 0 protocolswitch_p1.o(i.CAN_Protocol_Deye) + i.CAN_Protocol_Growatt 0x08005b08 Section 0 protocolswitch_p1.o(i.CAN_Protocol_Growatt) + i.CAN_Protocol_Pylon 0x08005ea0 Section 0 protocolswitch_p1.o(i.CAN_Protocol_Pylon) + i.CAN_Protocol_SolArk 0x08006404 Section 0 protocolswitch_p1.o(i.CAN_Protocol_SolArk) + i.CAN_Protocol_solis 0x0800673c Section 0 protocolswitch_p1.o(i.CAN_Protocol_solis) + i.CAN_Receive 0x080069c0 Section 0 stm32f10x_can.o(i.CAN_Receive) + i.CAN_StructInit 0x08006a50 Section 0 stm32f10x_can.o(i.CAN_StructInit) + i.CAN_TIM_Moni 0x08006a70 Section 0 can.o(i.CAN_TIM_Moni) + i.CAN_Transmit 0x08006a88 Section 0 stm32f10x_can.o(i.CAN_Transmit) + i.CAN_TransmitStatus 0x08006b2c Section 0 stm32f10x_can.o(i.CAN_TransmitStatus) + i.CAN_UpdateData 0x08006b98 Section 0 can.o(i.CAN_UpdateData) + i.CHG_LIMIT_Ctrl 0x08006bcc Section 0 afe_sh3673520.o(i.CHG_LIMIT_Ctrl) + i.CHG_LIMIT_Init 0x08006cac Section 0 pwm.o(i.CHG_LIMIT_Init) + i.CHG_LIMIT_Off 0x08006cf4 Section 0 pwm.o(i.CHG_LIMIT_Off) + i.CHG_LIMIT_On 0x08006d2c Section 0 pwm.o(i.CHG_LIMIT_On) + i.CHG_LIMIT_PWM_Adjust 0x08006ddc Section 0 pwm.o(i.CHG_LIMIT_PWM_Adjust) + i.CRC16_Cal 0x08006ebc Section 0 rs485_modbus.o(i.CRC16_Cal) + i.CRC8_Cal 0x08006ef8 Section 0 global.o(i.CRC8_Cal) + i.CTRL_Off 0x08006f1c Section 0 afe_sh3673520.o(i.CTRL_Off) + i.CTRL_On 0x08006f3c Section 0 afe_sh3673520.o(i.CTRL_On) + i.Cali_FCC_Moni 0x08006f48 Section 0 gasgauge.o(i.Cali_FCC_Moni) + i.Cali_SOC_Moni 0x08007040 Section 0 gasgauge.o(i.Cali_SOC_Moni) + i.CheckITStatus 0x08007088 Section 0 stm32f10x_can.o(i.CheckITStatus) + CheckITStatus 0x08007089 Thumb Code 12 stm32f10x_can.o(i.CheckITStatus) + i.DO_Off 0x08007094 Section 0 gpio.o(i.DO_Off) + i.DO_On 0x080070a0 Section 0 gpio.o(i.DO_On) + i.DebugMon_Handler 0x080070ac Section 0 stm32f10x_it.o(i.DebugMon_Handler) + i.EEPROM_CALI_RdGain 0x080070ae Section 0 i2c.o(i.EEPROM_CALI_RdGain) + i.EEPROM_CALI_RdZero 0x0800716a Section 0 i2c.o(i.EEPROM_CALI_RdZero) + i.EEPROM_CALI_WrGain 0x08007224 Section 0 i2c.o(i.EEPROM_CALI_WrGain) + i.EEPROM_CALI_WrZero 0x08007284 Section 0 i2c.o(i.EEPROM_CALI_WrZero) + i.EEPROM_RdMulByte 0x080072e4 Section 0 i2c.o(i.EEPROM_RdMulByte) + i.EEPROM_WrMulByte 0x08007494 Section 0 i2c.o(i.EEPROM_WrMulByte) + i.FCCCali_TIM_Moni 0x080075d4 Section 0 global.o(i.FCCCali_TIM_Moni) + i.FLASH_ClearFlag 0x0800760c Section 0 stm32f10x_flash.o(i.FLASH_ClearFlag) + i.FLASH_ErasePage 0x08007618 Section 0 stm32f10x_flash.o(i.FLASH_ErasePage) + i.FLASH_GetBank1Status 0x08007654 Section 0 stm32f10x_flash.o(i.FLASH_GetBank1Status) + i.FLASH_Lock 0x0800767c Section 0 stm32f10x_flash.o(i.FLASH_Lock) + i.FLASH_ProgramHalfWord 0x0800768c Section 0 stm32f10x_flash.o(i.FLASH_ProgramHalfWord) + i.FLASH_RdDataByte 0x080076c0 Section 0 flash.o(i.FLASH_RdDataByte) + i.FLASH_RdWord 0x080076d4 Section 0 flash.o(i.FLASH_RdWord) + i.FLASH_ReadCheck 0x080076f0 Section 0 flash.o(i.FLASH_ReadCheck) + i.FLASH_Unlock 0x08007748 Section 0 stm32f10x_flash.o(i.FLASH_Unlock) + i.FLASH_UpdateMemory 0x08007760 Section 0 flash.o(i.FLASH_UpdateMemory) + i.FLASH_WaitForLastOperation 0x08007784 Section 0 stm32f10x_flash.o(i.FLASH_WaitForLastOperation) + i.FLASH_WrData 0x080077a8 Section 0 flash.o(i.FLASH_WrData) + i.GPIO_Init 0x080077e8 Section 0 stm32f10x_gpio.o(i.GPIO_Init) + i.GPIO_PinRemapConfig 0x0800788c Section 0 stm32f10x_gpio.o(i.GPIO_PinRemapConfig) + i.GPIO_ReadInputDataBit 0x080078e4 Section 0 stm32f10x_gpio.o(i.GPIO_ReadInputDataBit) + i.GPIO_ResetBits 0x080078f2 Section 0 stm32f10x_gpio.o(i.GPIO_ResetBits) + i.GPIO_SetBits 0x080078f6 Section 0 stm32f10x_gpio.o(i.GPIO_SetBits) + i.GaugeManage 0x080078fc Section 0 gasgauge.o(i.GaugeManage) + i.GetStr 0x08007dcc Section 0 global.o(i.GetStr) + i.HAL_GPIO_TogglePin 0x08007e20 Section 0 gpio.o(i.HAL_GPIO_TogglePin) + i.HardFault_Handler 0x08007e30 Section 0 stm32f10x_it.o(i.HardFault_Handler) + i.I2C_AcknowledgeConfig 0x08007e4c Section 0 stm32f10x_i2c.o(i.I2C_AcknowledgeConfig) + i.I2C_CheckEvent 0x08007e60 Section 0 stm32f10x_i2c.o(i.I2C_CheckEvent) + i.I2C_Cmd 0x08007e78 Section 0 stm32f10x_i2c.o(i.I2C_Cmd) + i.I2C_DeInit 0x08007e8c Section 0 stm32f10x_i2c.o(i.I2C_DeInit) + i.I2C_GenerateSTART 0x08007eb8 Section 0 stm32f10x_i2c.o(i.I2C_GenerateSTART) + i.I2C_GenerateSTOP 0x08007ecc Section 0 stm32f10x_i2c.o(i.I2C_GenerateSTOP) + i.I2C_GetFlagStatus 0x08007ee0 Section 0 stm32f10x_i2c.o(i.I2C_GetFlagStatus) + i.I2C_Init 0x08007f0c Section 0 stm32f10x_i2c.o(i.I2C_Init) + i.I2C_ReceiveData 0x08007fc8 Section 0 stm32f10x_i2c.o(i.I2C_ReceiveData) + i.I2C_Send7bitAddress 0x08007fce Section 0 stm32f10x_i2c.o(i.I2C_Send7bitAddress) + i.I2C_SendData 0x08007fde Section 0 stm32f10x_i2c.o(i.I2C_SendData) + i.IO1_IN 0x08007fe4 Section 0 gpio.o(i.IO1_IN) + i.IO2_OUTReset 0x08007ff4 Section 0 gpio.o(i.IO2_OUTReset) + i.IO2_OUTSet 0x08008004 Section 0 gpio.o(i.IO2_OUTSet) + i.IO3_IN 0x08008014 Section 0 gpio.o(i.IO3_IN) + i.IWDG_Enable 0x08008020 Section 0 stm32f10x_iwdg.o(i.IWDG_Enable) + i.IWDG_Feed 0x08008030 Section 0 wdg.o(i.IWDG_Feed) + i.IWDG_ReloadCounter 0x08008034 Section 0 stm32f10x_iwdg.o(i.IWDG_ReloadCounter) + i.IWDG_SetPrescaler 0x08008044 Section 0 stm32f10x_iwdg.o(i.IWDG_SetPrescaler) + i.IWDG_SetReload 0x08008050 Section 0 stm32f10x_iwdg.o(i.IWDG_SetReload) + i.IWDG_WriteAccessCmd 0x0800805c Section 0 stm32f10x_iwdg.o(i.IWDG_WriteAccessCmd) + i.InitGasGauge 0x08008068 Section 0 gasgauge.o(i.InitGasGauge) + i.Is_Leap_Year 0x080081fc Section 0 rtc.o(i.Is_Leap_Year) + i.KEY_IN 0x08008228 Section 0 gpio.o(i.KEY_IN) + i.KEY_TIM_Moni 0x08008234 Section 0 gpio.o(i.KEY_TIM_Moni) + i.LED1_Off 0x080082e8 Section 0 gpio.o(i.LED1_Off) + i.LED1_On 0x080082f4 Section 0 gpio.o(i.LED1_On) + i.LED2_Off 0x08008300 Section 0 gpio.o(i.LED2_Off) + i.LED2_On 0x08008310 Section 0 gpio.o(i.LED2_On) + i.LED3_Off 0x08008320 Section 0 gpio.o(i.LED3_Off) + i.LED3_On 0x0800832c Section 0 gpio.o(i.LED3_On) + i.LED4_Off 0x08008338 Section 0 gpio.o(i.LED4_Off) + i.LED4_On 0x08008344 Section 0 gpio.o(i.LED4_On) + i.LED_ALARM_Off 0x08008350 Section 0 gpio.o(i.LED_ALARM_Off) + i.LED_ALARM_On 0x0800835c Section 0 gpio.o(i.LED_ALARM_On) + i.LED_ALARM_Toggle 0x08008368 Section 0 gpio.o(i.LED_ALARM_Toggle) + i.LED_RUN_Off 0x08008374 Section 0 gpio.o(i.LED_RUN_Off) + i.LED_RUN_On 0x08008384 Section 0 gpio.o(i.LED_RUN_On) + i.LED_RUN_Toggle 0x08008394 Section 0 gpio.o(i.LED_RUN_Toggle) + i.LOAD_VOL 0x080083a4 Section 0 adc.o(i.LOAD_VOL) + i.MCU_TemperaProcess 0x080083c8 Section 0 adc.o(i.MCU_TemperaProcess) + i.MEMORY_UpdateAFE 0x0800858c Section 0 afe_sh3673520.o(i.MEMORY_UpdateAFE) + i.MEMORY_UpdateFlash 0x0800867c Section 0 flash.o(i.MEMORY_UpdateFlash) + i.MODBUS1_CtrlMOS_Rx 0x080086e0 Section 0 rs485_modbus_inverter.o(i.MODBUS1_CtrlMOS_Rx) + i.MODBUS1_F03_Rx 0x08008728 Section 0 rs485_modbus_inverter.o(i.MODBUS1_F03_Rx) + i.MODBUS1_F10_Rx 0x080087f4 Section 0 rs485_modbus_inverter.o(i.MODBUS1_F10_Rx) + i.MODBUS1_Faa_Rx 0x0800892c Section 0 rs485_modbus_inverter.o(i.MODBUS1_Faa_Rx) + i.MODBUS1_Fbb_Rx 0x08008974 Section 0 rs485_modbus_inverter.o(i.MODBUS1_Fbb_Rx) + i.MODBUS1_IQ_Transmit 0x080089cc Section 0 rs485_modbus_inverter.o(i.MODBUS1_IQ_Transmit) + i.MODBUS1_IT_Receive 0x08008e0c Section 0 rs485_modbus_inverter.o(i.MODBUS1_IT_Receive) + i.MODBUS1_IT_TIMUpdate 0x08008e54 Section 0 rs485_modbus_inverter.o(i.MODBUS1_IT_TIMUpdate) + i.MODBUS1_Init 0x08009198 Section 0 rs485_modbus_inverter.o(i.MODBUS1_Init) + i.MODBUS1_TIM_Moni 0x080091c4 Section 0 rs485_modbus_inverter.o(i.MODBUS1_TIM_Moni) + i.MODBUS1_UpdateData 0x080091e4 Section 0 rs485_modbus_inverter.o(i.MODBUS1_UpdateData) + i.MODBUS_AddrAssign_Tx 0x08009200 Section 0 rs485_modbus.o(i.MODBUS_AddrAssign_Tx) + i.MODBUS_Config_RdSlave_Tx 0x0800931c Section 0 rs485_modbus.o(i.MODBUS_Config_RdSlave_Tx) + i.MODBUS_CtrlMOS_Rx 0x0800941c Section 0 rs485_modbus.o(i.MODBUS_CtrlMOS_Rx) + i.MODBUS_F03_Rx 0x08009464 Section 0 rs485_modbus.o(i.MODBUS_F03_Rx) + i.MODBUS_F10_Rx 0x080094e8 Section 0 rs485_modbus.o(i.MODBUS_F10_Rx) + i.MODBUS_Faa_Rx 0x08009628 Section 0 rs485_modbus.o(i.MODBUS_Faa_Rx) + i.MODBUS_Fbb_Rx 0x08009670 Section 0 rs485_modbus.o(i.MODBUS_Fbb_Rx) + i.MODBUS_IQ_Transmit 0x080096c8 Section 0 rs485_modbus.o(i.MODBUS_IQ_Transmit) + i.MODBUS_IT_Receive 0x08009a6c Section 0 rs485_modbus.o(i.MODBUS_IT_Receive) + i.MODBUS_IT_TIMUpdate 0x08009acc Section 0 rs485_modbus.o(i.MODBUS_IT_TIMUpdate) + i.MODBUS_Init 0x08009df4 Section 0 rs485_modbus.o(i.MODBUS_Init) + i.MODBUS_MASTER_F03_Rx 0x08009e3c Section 0 rs485_modbus.o(i.MODBUS_MASTER_F03_Rx) + i.MODBUS_MASTER_F10_Rx 0x08009ec8 Section 0 rs485_modbus.o(i.MODBUS_MASTER_F10_Rx) + i.MODBUS_Poll_Init 0x08009f0c Section 0 rs485_modbus.o(i.MODBUS_Poll_Init) + i.MODBUS_TIM_Moni 0x08009fb0 Section 0 rs485_modbus.o(i.MODBUS_TIM_Moni) + i.MemManage_Handler 0x08009fd4 Section 0 stm32f10x_it.o(i.MemManage_Handler) + i.NMI_Handler 0x08009fd6 Section 0 stm32f10x_it.o(i.NMI_Handler) + i.NVIC_PriorityGroupConfig 0x08009fd8 Section 0 misc.o(i.NVIC_PriorityGroupConfig) + i.PCHG_Off 0x08009fec Section 0 gpio.o(i.PCHG_Off) + i.PendSV_Handler 0x08009ff8 Section 0 stm32f10x_it.o(i.PendSV_Handler) + i.SPI2_Error 0x08009ffa Section 0 spi.o(i.SPI2_Error) + i.SVC_Handler 0x08009ffe Section 0 stm32f10x_it.o(i.SVC_Handler) + .ARM.__AT_0x0800A000 0x0800a000 Section 2048 flash.o(.ARM.__AT_0x0800A000) + i.MODBUS_MASTER_Polling_Tx 0x0800a800 Section 0 rs485_modbus.o(i.MODBUS_MASTER_Polling_Tx) + i.MODBUS_Screen_RdSlave_Tx 0x0800aad4 Section 0 rs485_modbus.o(i.MODBUS_Screen_RdSlave_Tx) + i.MODBUS_Screen_WrSlaveAddr_Tx 0x0800abc4 Section 0 rs485_modbus.o(i.MODBUS_Screen_WrSlaveAddr_Tx) + i.MODBUS_WrIndex_Rx 0x0800ac80 Section 0 rs485_modbus.o(i.MODBUS_WrIndex_Rx) + i.MODBUS_WrIndex_Tx 0x0800ace4 Section 0 rs485_modbus.o(i.MODBUS_WrIndex_Tx) + i.MOD_Protocol_Growatt 0x0800ad40 Section 0 protocolswitch_p1.o(i.MOD_Protocol_Growatt) + i.MOD_Protocol_Voltronic 0x0800b03c Section 0 protocolswitch_p2.o(i.MOD_Protocol_Voltronic) + i.NVIC_Init 0x0800b3c0 Section 0 misc.o(i.NVIC_Init) + i.OCC2_Ctrl 0x0800b424 Section 0 afe_sh3673520.o(i.OCC2_Ctrl) + i.OCC2_TIM_Moni 0x0800b470 Section 0 afe_sh3673520.o(i.OCC2_TIM_Moni) + i.OCV_CaliSOC 0x0800b4bc Section 0 ocv.o(i.OCV_CaliSOC) + i.OCV_CaliSOC_DataWr 0x0800b690 Section 0 ocv.o(i.OCV_CaliSOC_DataWr) + i.OCV_CaliSoc_dp 0x0800b744 Section 0 ocv.o(i.OCV_CaliSoc_dp) + i.PCHG_Ctrl 0x0800b7f8 Section 0 gpio.o(i.PCHG_Ctrl) + i.PCHG_On 0x0800b894 Section 0 gpio.o(i.PCHG_On) + i.PCHG_StartCtrl 0x0800b8a0 Section 0 gpio.o(i.PCHG_StartCtrl) + i.PWM_Set_Duty_Percent 0x0800b938 Section 0 pwm.o(i.PWM_Set_Duty_Percent) + i.PWR_BackupAccessCmd 0x0800b97c Section 0 stm32f10x_pwr.o(i.PWR_BackupAccessCmd) + i.ParaChange 0x0800b988 Section 0 global.o(i.ParaChange) + i.RCC_ADCCLKConfig 0x0800bcc8 Section 0 stm32f10x_rcc.o(i.RCC_ADCCLKConfig) + i.RCC_APB1PeriphClockCmd 0x0800bcdc Section 0 stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd) + i.RCC_APB1PeriphResetCmd 0x0800bcf4 Section 0 stm32f10x_rcc.o(i.RCC_APB1PeriphResetCmd) + i.RCC_APB2PeriphClockCmd 0x0800bd0c Section 0 stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) + i.RCC_APB2PeriphResetCmd 0x0800bd24 Section 0 stm32f10x_rcc.o(i.RCC_APB2PeriphResetCmd) + i.RCC_BackupResetCmd 0x0800bd3c Section 0 stm32f10x_rcc.o(i.RCC_BackupResetCmd) + i.RCC_GetClocksFreq 0x0800bd48 Section 0 stm32f10x_rcc.o(i.RCC_GetClocksFreq) + i.RCC_GetFlagStatus 0x0800bdd8 Section 0 stm32f10x_rcc.o(i.RCC_GetFlagStatus) + i.RCC_LSEConfig 0x0800be08 Section 0 stm32f10x_rcc.o(i.RCC_LSEConfig) + i.RCC_RTCCLKCmd 0x0800be28 Section 0 stm32f10x_rcc.o(i.RCC_RTCCLKCmd) + i.RCC_RTCCLKConfig 0x0800be34 Section 0 stm32f10x_rcc.o(i.RCC_RTCCLKConfig) + i.RTC_BackUp 0x0800be44 Section 0 rtc.o(i.RTC_BackUp) + i.RTC_EnterConfigMode 0x0800bee4 Section 0 stm32f10x_rtc.o(i.RTC_EnterConfigMode) + i.RTC_ExitConfigMode 0x0800bef4 Section 0 stm32f10x_rtc.o(i.RTC_ExitConfigMode) + i.RTC_GetCounter 0x0800bf04 Section 0 stm32f10x_rtc.o(i.RTC_GetCounter) + i.RTC_GetSynchro 0x0800bf24 Section 0 rtc.o(i.RTC_GetSynchro) + i.RTC_Get_Week 0x0800bf58 Section 0 rtc.o(i.RTC_Get_Week) + i.RTC_WaitForLastTask 0x0800bfec Section 0 stm32f10x_rtc.o(i.RTC_WaitForLastTask) + i.SPI_I2S_ReceiveData 0x0800bffc Section 0 stm32f10x_spi.o(i.SPI_I2S_ReceiveData) + .ARM.__AT_0x0800C000 0x0800c000 Section 2048 flash.o(.ARM.__AT_0x0800C000) + i.RTC_Get 0x0800c800 Section 0 rtc.o(i.RTC_Get) + i.RTC_ITConfig 0x0800cbd0 Section 0 stm32f10x_rtc.o(i.RTC_ITConfig) + i.RTC_Set 0x0800cbe8 Section 0 rtc.o(i.RTC_Set) + i.RTC_SetCounter 0x0800cd18 Section 0 stm32f10x_rtc.o(i.RTC_SetCounter) + i.RTC_SetPrescaler 0x0800cd38 Section 0 stm32f10x_rtc.o(i.RTC_SetPrescaler) + i.RTC_WaitForSynchro 0x0800cd58 Section 0 stm32f10x_rtc.o(i.RTC_WaitForSynchro) + i.Refresh_BMS_SN 0x0800cd70 Section 0 global.o(i.Refresh_BMS_SN) + i.Refresh_FirmwareVersion 0x0800cd9c Section 0 global.o(i.Refresh_FirmwareVersion) + i.Refresh_HardwareVersion 0x0800cde4 Section 0 global.o(i.Refresh_HardwareVersion) + i.Refresh_PACK_SN 0x0800ce24 Section 0 global.o(i.Refresh_PACK_SN) + i.Refresh_ScreenVersion 0x0800ce54 Section 0 global.o(i.Refresh_ScreenVersion) + i.Release_CurAlarm 0x0800ced4 Section 0 status.o(i.Release_CurAlarm) + i.Release_CurProtect 0x0800cfcc Section 0 status.o(i.Release_CurProtect) + i.Release_OVAlarm 0x0800d0b0 Section 0 status.o(i.Release_OVAlarm) + i.Release_OVProtect 0x0800d1e0 Section 0 status.o(i.Release_OVProtect) + i.Release_UVAlarm 0x0800d2f8 Section 0 status.o(i.Release_UVAlarm) + i.Release_UVProtect 0x0800d3c4 Section 0 status.o(i.Release_UVProtect) + i.Release_afeTAlarm 0x0800d48c Section 0 status.o(i.Release_afeTAlarm) + i.Release_afeTProtect 0x0800d520 Section 0 status.o(i.Release_afeTProtect) + i.Release_amTAlarm 0x0800d5b4 Section 0 status.o(i.Release_amTAlarm) + i.Release_amTProtect 0x0800d6b0 Section 0 status.o(i.Release_amTProtect) + i.Release_mcuTAlarm 0x0800d7ac Section 0 status.o(i.Release_mcuTAlarm) + i.Release_mcuTProtect 0x0800d8bc Section 0 status.o(i.Release_mcuTProtect) + i.SCR_ClearAlarm 0x0800d9cc Section 0 screen.o(i.SCR_ClearAlarm) + i.SCR_DispProcotol 0x0800db18 Section 0 screen.o(i.SCR_DispProcotol) + i.SCR_JumpToAlarm 0x0800e0a8 Section 0 screen.o(i.SCR_JumpToAlarm) + i.SCR_Send_Record 0x0800e0d8 Section 0 screen.o(i.SCR_Send_Record) + i.SCR_Send_RecordInfo 0x0800e3e4 Section 0 screen.o(i.SCR_Send_RecordInfo) + i.SCR_Send_Self_BasicInfo 0x0800e668 Section 0 screen.o(i.SCR_Send_Self_BasicInfo) + i.SCR_Send_Slave_BasicInfo 0x0800edc0 Section 0 screen.o(i.SCR_Send_Slave_BasicInfo) + i.SCR_Send_Slave_RecordBank 0x0800f5e0 Section 0 screen.o(i.SCR_Send_Slave_RecordBank) + i.SCR_Send_Time 0x0800f694 Section 0 screen.o(i.SCR_Send_Time) + i.SCR_Send_TotalInfo 0x0800f6fc Section 0 screen.o(i.SCR_Send_TotalInfo) + i.SCR_Send_VER 0x0800f9c0 Section 0 screen.o(i.SCR_Send_VER) + i.SCR_ShowAlarm 0x0800faa4 Section 0 screen.o(i.SCR_ShowAlarm) + i.SCR_ShowAlarm_Slave 0x0800fde8 Section 0 screen.o(i.SCR_ShowAlarm_Slave) + i.SLEEP2_Refresh 0x08010108 Section 0 global.o(i.SLEEP2_Refresh) + i.SLEEP2_TIM_Moni 0x08010194 Section 0 global.o(i.SLEEP2_TIM_Moni) + i.SLEEP_Refresh 0x08010220 Section 0 global.o(i.SLEEP_Refresh) + i.SLEEP_TIM_Moni 0x08010258 Section 0 global.o(i.SLEEP_TIM_Moni) + i.SOE_BkData 0x08010290 Section 0 soe.o(i.SOE_BkData) + i.SPI_Cmd 0x080106c4 Section 0 stm32f10x_spi.o(i.SPI_Cmd) + i.SPI_I2S_DeInit 0x080106d8 Section 0 stm32f10x_spi.o(i.SPI_I2S_DeInit) + i.SPI_I2S_GetFlagStatus 0x0801072c Section 0 stm32f10x_spi.o(i.SPI_I2S_GetFlagStatus) + i.SPI_I2S_SendData 0x0801073a Section 0 stm32f10x_spi.o(i.SPI_I2S_SendData) + i.SPI_Init 0x0801073e Section 0 stm32f10x_spi.o(i.SPI_Init) + i.Screen_ClearBuf 0x08010778 Section 0 screen.o(i.Screen_ClearBuf) + i.Screen_IQ_Transmit 0x08010790 Section 0 screen.o(i.Screen_IQ_Transmit) + i.Screen_IT_Receive 0x080110e4 Section 0 screen.o(i.Screen_IT_Receive) + i.Screen_IT_Update 0x08011118 Section 0 screen.o(i.Screen_IT_Update) + i.Screen_Init 0x08012634 Section 0 screen.o(i.Screen_Init) + i.Screen_TIM_Moni 0x08012654 Section 0 screen.o(i.Screen_TIM_Moni) + i.Send_Record_Blank 0x0801266c Section 0 screen.o(i.Send_Record_Blank) + i.SetSysClockTo72 0x08012790 Section 0 system_stm32f10x.o(i.SetSysClockTo72) + SetSysClockTo72 0x08012791 Thumb Code 160 system_stm32f10x.o(i.SetSysClockTo72) + i.Set_Row_Hide 0x08012838 Section 0 screen.o(i.Set_Row_Hide) + i.SysTick_Handler 0x080128a8 Section 0 stm32f10x_it.o(i.SysTick_Handler) + i.SystemInit 0x080128ac Section 0 system_stm32f10x.o(i.SystemInit) + i.TEMP_Cal 0x080128fc Section 0 ntc.o(i.TEMP_Cal) + i.TEMP_Cal_CMFA 0x08012980 Section 0 ntc.o(i.TEMP_Cal_CMFA) + i.TIM3_IRQHandler 0x08012a04 Section 0 tim.o(i.TIM3_IRQHandler) + i.TIM4_PWM_Init 0x08012b34 Section 0 pwm.o(i.TIM4_PWM_Init) + i.TIMER_IsOut 0x08012bcc Section 0 tim.o(i.TIMER_IsOut) + i.TIMER_Update 0x08012bec Section 0 tim.o(i.TIMER_Update) + i.TIM_ARRPreloadConfig 0x08012bf8 Section 0 stm32f10x_tim.o(i.TIM_ARRPreloadConfig) + i.TIM_ClearITPendingBit 0x08012c0c Section 0 stm32f10x_tim.o(i.TIM_ClearITPendingBit) + i.TIM_Cmd 0x08012c12 Section 0 stm32f10x_tim.o(i.TIM_Cmd) + i.TIM_CtrlPWMOutputs 0x08012c26 Section 0 stm32f10x_tim.o(i.TIM_CtrlPWMOutputs) + i.TIM_GetITStatus 0x08012c3c Section 0 stm32f10x_tim.o(i.TIM_GetITStatus) + i.TIM_ITConfig 0x08012c54 Section 0 stm32f10x_tim.o(i.TIM_ITConfig) + i.TIM_OC4Init 0x08012c64 Section 0 stm32f10x_tim.o(i.TIM_OC4Init) + i.TIM_OC4PreloadConfig 0x08012cc8 Section 0 stm32f10x_tim.o(i.TIM_OC4PreloadConfig) + i.TIM_SetCompare4 0x08012cdc Section 0 stm32f10x_tim.o(i.TIM_SetCompare4) + i.TIM_SetCounter 0x08012ce2 Section 0 stm32f10x_tim.o(i.TIM_SetCounter) + i.TIM_TimeBaseInit 0x08012ce8 Section 0 stm32f10x_tim.o(i.TIM_TimeBaseInit) + i.TSC_Detect 0x08012d84 Section 0 gpio.o(i.TSC_Detect) + i.Trigger_CurAlarm 0x08012de8 Section 0 status.o(i.Trigger_CurAlarm) + i.Trigger_CurProtect 0x08012e80 Section 0 status.o(i.Trigger_CurProtect) + i.Trigger_CurProtectLock 0x08012f1c Section 0 status.o(i.Trigger_CurProtectLock) + i.Trigger_OVAlarm 0x08012f20 Section 0 status.o(i.Trigger_OVAlarm) + i.Trigger_OVProtect 0x08012fc0 Section 0 status.o(i.Trigger_OVProtect) + i.Trigger_UVAlarm 0x080130a0 Section 0 status.o(i.Trigger_UVAlarm) + i.Trigger_UVProtect 0x08013140 Section 0 status.o(i.Trigger_UVProtect) + i.Trigger_afeTAlarm 0x08013218 Section 0 status.o(i.Trigger_afeTAlarm) + i.Trigger_afeTProtect 0x080132d8 Section 0 status.o(i.Trigger_afeTProtect) + i.Trigger_amTAlarm 0x08013390 Section 0 status.o(i.Trigger_amTAlarm) + i.Trigger_amTProtect 0x080134bc Section 0 status.o(i.Trigger_amTProtect) + i.Trigger_mcuTAlarm 0x080135e8 Section 0 status.o(i.Trigger_mcuTAlarm) + i.Trigger_mcuTProtect 0x08013724 Section 0 status.o(i.Trigger_mcuTProtect) + i.UART1_ClearRecord 0x08013858 Section 0 rs485_modbus.o(i.UART1_ClearRecord) + i.UART1_ProtocolSwitch 0x080138bc Section 0 rs485_modbus.o(i.UART1_ProtocolSwitch) + i.UART1_ReadRecord 0x08013964 Section 0 rs485_modbus.o(i.UART1_ReadRecord) + i.UART3_ClearRecord 0x080139ac Section 0 rs485_modbus_inverter.o(i.UART3_ClearRecord) + i.UART3_EraseIAP 0x08013a10 Section 0 rs485_modbus_inverter.o(i.UART3_EraseIAP) + i.UART3_ProtocolSwitch 0x08013a40 Section 0 rs485_modbus_inverter.o(i.UART3_ProtocolSwitch) + i.UART3_ReadRecord 0x08013af0 Section 0 rs485_modbus_inverter.o(i.UART3_ReadRecord) + i.UART4_IRQHandler 0x08013b38 Section 0 uart.o(i.UART4_IRQHandler) + i.USART1_IRQHandler 0x08013b64 Section 0 uart.o(i.USART1_IRQHandler) + i.USART1_SendMulByte 0x08013b90 Section 0 uart.o(i.USART1_SendMulByte) + i.USART2_IRQHandler 0x08013bc4 Section 0 uart.o(i.USART2_IRQHandler) + i.USART2_printf 0x08013bf0 Section 0 screen.o(i.USART2_printf) + i.USART3_IRQHandler 0x08013c28 Section 0 uart.o(i.USART3_IRQHandler) + i.USART3_SendMulByte 0x08013c54 Section 0 uart.o(i.USART3_SendMulByte) + i.USART_Cmd 0x08013c88 Section 0 stm32f10x_usart.o(i.USART_Cmd) + i.USART_GetFlagStatus 0x08013c9c Section 0 stm32f10x_usart.o(i.USART_GetFlagStatus) + i.USART_GetITStatus 0x08013caa Section 0 stm32f10x_usart.o(i.USART_GetITStatus) + i.USART_ITConfig 0x08013ce8 Section 0 stm32f10x_usart.o(i.USART_ITConfig) + i.USART_Init 0x08013d18 Section 0 stm32f10x_usart.o(i.USART_Init) + i.USART_ReceiveData 0x08013dc4 Section 0 stm32f10x_usart.o(i.USART_ReceiveData) + i.USART_SendData 0x08013dcc Section 0 stm32f10x_usart.o(i.USART_SendData) + i.USB_LP_CAN1_RX0_IRQHandler 0x08013dd4 Section 0 can.o(i.USB_LP_CAN1_RX0_IRQHandler) + i.UVOff_TIM_Moni 0x08013e30 Section 0 global.o(i.UVOff_TIM_Moni) + i.UsageFault_Handler 0x08013e68 Section 0 stm32f10x_it.o(i.UsageFault_Handler) + i.YDN 0x08013e6c Section 0 rs485_modbus_inverter.o(i.YDN) + i.YDN_Protocol_Pylon 0x08014904 Section 0 protocolswitch_p1.o(i.YDN_Protocol_Pylon) + i.__ARM_fpclassify 0x08014908 Section 0 fpclassify.o(i.__ARM_fpclassify) + i._is_digit 0x08014930 Section 0 __printf_wp.o(i._is_digit) + i.canMem_refresh 0x08014940 Section 0 global.o(i.canMem_refresh) + i.delay_ms 0x08014e60 Section 0 systick.o(i.delay_ms) + i.delay_us 0x08014eac Section 0 systick.o(i.delay_us) + i.findHexStr 0x08014eea Section 0 screen.o(i.findHexStr) + i.get_random 0x08014f18 Section 0 global.o(i.get_random) + i.main 0x08014f4c Section 0 main.o(i.main) + i.onlineMem_refresh 0x0801526c Section 0 global.o(i.onlineMem_refresh) + i.toASCII 0x08015300 Section 0 global.o(i.toASCII) + i.uf_ADC_Init 0x08015310 Section 0 adc.o(i.uf_ADC_Init) + i.uf_CAN1_Init 0x080153bc Section 0 can.o(i.uf_CAN1_Init) + i.uf_EXTI_Init 0x080154ec Section 0 gpio.o(i.uf_EXTI_Init) + i.uf_FLASH_Init 0x080154f4 Section 0 flash.o(i.uf_FLASH_Init) + i.uf_GLOBAL_Init 0x08015534 Section 0 global.o(i.uf_GLOBAL_Init) + i.uf_GPIO_Init 0x0801574c Section 0 gpio.o(i.uf_GPIO_Init) + i.uf_I2C1_Init 0x0801590c Section 0 i2c.o(i.uf_I2C1_Init) + i.uf_IWDG_Init 0x08015b08 Section 0 wdg.o(i.uf_IWDG_Init) + i.uf_RTC_Init 0x08015b30 Section 0 rtc.o(i.uf_RTC_Init) + i.uf_RTC_Update 0x08015ce4 Section 0 rtc.o(i.uf_RTC_Update) + i.uf_SPI2_Init 0x08015dd8 Section 0 spi.o(i.uf_SPI2_Init) + i.uf_TIM3_Init 0x08015e9c Section 0 tim.o(i.uf_TIM3_Init) + i.uf_UART1_Init 0x08015efc Section 0 uart.o(i.uf_UART1_Init) + i.uf_UART2_Init 0x08015fb8 Section 0 uart.o(i.uf_UART2_Init) + i.uf_UART3_Init 0x08016064 Section 0 uart.o(i.uf_UART3_Init) + i.uf_UART4_Init 0x0801610c Section 0 uart.o(i.uf_UART4_Init) + locale$$code 0x080161b4 Section 44 lc_numeric_c.o(locale$$code) + locale$$code 0x080161e0 Section 44 lc_ctype_c.o(locale$$code) + x$fpl$dadd 0x0801620c Section 336 daddsub_clz.o(x$fpl$dadd) + _dadd1 0x0801621d Thumb Code 0 daddsub_clz.o(x$fpl$dadd) + x$fpl$ddiv 0x0801635c Section 688 ddiv.o(x$fpl$ddiv) + ddiv_entry 0x08016363 Thumb Code 0 ddiv.o(x$fpl$ddiv) + x$fpl$dfix 0x0801660c Section 94 dfix.o(x$fpl$dfix) + x$fpl$dfixu 0x0801666c Section 90 dfixu.o(x$fpl$dfixu) + x$fpl$dfltu 0x080166c6 Section 38 dflt_clz.o(x$fpl$dfltu) + x$fpl$dmul 0x080166ec Section 340 dmul.o(x$fpl$dmul) + x$fpl$dnaninf 0x08016840 Section 156 dnaninf.o(x$fpl$dnaninf) + x$fpl$dretinf 0x080168dc Section 12 dretinf.o(x$fpl$dretinf) + x$fpl$dsub 0x080168e8 Section 468 daddsub_clz.o(x$fpl$dsub) + _dsub1 0x080168f9 Thumb Code 0 daddsub_clz.o(x$fpl$dsub) + x$fpl$f2d 0x08016abc Section 86 f2d.o(x$fpl$f2d) + x$fpl$fadd 0x08016b14 Section 196 faddsub_clz.o(x$fpl$fadd) + _fadd1 0x08016b23 Thumb Code 0 faddsub_clz.o(x$fpl$fadd) + x$fpl$fdiv 0x08016bd8 Section 388 fdiv.o(x$fpl$fdiv) + _fdiv1 0x08016bd9 Thumb Code 0 fdiv.o(x$fpl$fdiv) + x$fpl$ffixu 0x08016d5c Section 62 ffixu.o(x$fpl$ffixu) + x$fpl$fflt 0x08016d9c Section 48 fflt_clz.o(x$fpl$fflt) + x$fpl$ffltu 0x08016dcc Section 38 fflt_clz.o(x$fpl$ffltu) + x$fpl$fmul 0x08016df4 Section 258 fmul.o(x$fpl$fmul) + x$fpl$fnaninf 0x08016ef6 Section 140 fnaninf.o(x$fpl$fnaninf) + x$fpl$fretinf 0x08016f82 Section 10 fretinf.o(x$fpl$fretinf) + x$fpl$fsub 0x08016f8c Section 234 faddsub_clz.o(x$fpl$fsub) + _fsub1 0x08016f9b Thumb Code 0 faddsub_clz.o(x$fpl$fsub) + x$fpl$printf1 0x08017076 Section 4 printf1.o(x$fpl$printf1) + x$fpl$printf2 0x0801707a Section 4 printf2.o(x$fpl$printf2) + .constdata 0x0801707e Section 256 global.o(.constdata) + x$fpl$usenofp 0x0801707e Section 0 usenofp.o(x$fpl$usenofp) + .constdata 0x0801717e Section 24 rtc.o(.constdata) + .constdata 0x08017196 Section 512 rs485_modbus.o(.constdata) + .constdata 0x08017396 Section 694 ntc.o(.constdata) + .constdata 0x0801764c Section 10 status.o(.constdata) + .constdata 0x08017656 Section 40 _printf_hex_int_ll_ptr.o(.constdata) + uc_hextab 0x08017656 Data 20 _printf_hex_int_ll_ptr.o(.constdata) + lc_hextab 0x0801766a Data 20 _printf_hex_int_ll_ptr.o(.constdata) + .constdata 0x0801767e Section 17 __printf_flags_ss_wp.o(.constdata) + maptable 0x0801767e Data 17 __printf_flags_ss_wp.o(.constdata) + .constdata 0x08017690 Section 8 _printf_wctomb.o(.constdata) + initial_mbstate 0x08017690 Data 8 _printf_wctomb.o(.constdata) + .constdata 0x08017698 Section 38 _printf_fp_hex.o(.constdata) + lc_hextab 0x08017698 Data 19 _printf_fp_hex.o(.constdata) + uc_hextab 0x080176ab Data 19 _printf_fp_hex.o(.constdata) + .constdata 0x080176c0 Section 148 bigflt0.o(.constdata) + tenpwrs_x 0x080176c0 Data 60 bigflt0.o(.constdata) + tenpwrs_i 0x080176fc Data 64 bigflt0.o(.constdata) + .conststring 0x08017754 Section 13 mbo26a.o(.conststring) + locale$$data 0x08017784 Section 28 lc_numeric_c.o(locale$$data) + __lcnum_c_name 0x08017788 Data 2 lc_numeric_c.o(locale$$data) + __lcnum_c_start 0x08017790 Data 0 lc_numeric_c.o(locale$$data) + __lcnum_c_point 0x0801779c Data 0 lc_numeric_c.o(locale$$data) + __lcnum_c_thousands 0x0801779e Data 0 lc_numeric_c.o(locale$$data) + __lcnum_c_grouping 0x0801779f Data 0 lc_numeric_c.o(locale$$data) + locale$$data 0x080177a0 Section 272 lc_ctype_c.o(locale$$data) + __lcnum_c_end 0x080177a0 Data 0 lc_numeric_c.o(locale$$data) + __lcctype_c_name 0x080177a4 Data 2 lc_ctype_c.o(locale$$data) + __lcctype_c_start 0x080177ac Data 0 lc_ctype_c.o(locale$$data) + __lcctype_c_end 0x080178b0 Data 0 lc_ctype_c.o(locale$$data) + .data 0x20000000 Section 32 global.o(.data) + .data 0x20000020 Section 24 gpio.o(.data) + .data 0x20000038 Section 1 gpio.o(.data) + .data 0x2000003c Section 4 tim.o(.data) + .data 0x20000040 Section 8 uart.o(.data) + .data 0x20000048 Section 1 uart.o(.data) + .data 0x2000004c Section 12 i2c.o(.data) + .data 0x20000058 Section 81 rtc.o(.data) + daycnt 0x2000005e Data 2 rtc.o(.data) + .data 0x200000aa Section 4 can.o(.data) + .data 0x200000b0 Section 16 adc.o(.data) + .data 0x200000c0 Section 16 pwm.o(.data) + .data 0x200000d0 Section 62 afe_sh3673520.o(.data) + .data 0x2000010e Section 38 rs485_modbus.o(.data) + .data 0x20000134 Section 1 rs485_modbus.o(.data) + .data 0x20000135 Section 1 rs485_modbus.o(.data) + .data 0x20000136 Section 1 rs485_modbus.o(.data) + .data 0x20000138 Section 2 rs485_modbus.o(.data) + .data 0x2000013a Section 1 rs485_modbus.o(.data) + .data 0x2000013b Section 1 rs485_modbus.o(.data) + .data 0x2000013c Section 1 rs485_modbus_inverter.o(.data) + .data 0x2000013e Section 444 rs485_modbus_inverter.o(.data) + .data 0x200002fa Section 1 ntc.o(.data) + .data 0x200002fc Section 542 screen.o(.data) + last_alarm_stat 0x200002fc Data 1 screen.o(.data) + reset_timer 0x200002fd Data 1 screen.o(.data) + .data 0x2000051a Section 1 screen.o(.data) + .data 0x2000051b Section 1 screen.o(.data) + .data 0x2000051c Section 1 screen.o(.data) + .data 0x20000520 Section 56 gasgauge.o(.data) + .data 0x20000558 Section 6 ocv.o(.data) + .data 0x2000055e Section 98 status.o(.data) + .data 0x200005c0 Section 100 mbo26a.o(.data) + .data 0x20000624 Section 20 stm32f10x_rcc.o(.data) + ADCPrescTable 0x20000624 Data 4 stm32f10x_rcc.o(.data) + APBAHBPrescTable 0x20000628 Data 16 stm32f10x_rcc.o(.data) + .data 0x20000638 Section 1 protocolswitch_p1.o(.data) + .bss 0x2000063c Section 696 global.o(.bss) + .bss 0x200008f4 Section 228 global.o(.bss) + .bss 0x200009d8 Section 240 global.o(.bss) + .bss 0x20000ac8 Section 290 global.o(.bss) + .bss 0x20000bec Section 80 tim.o(.bss) + .bss 0x20000c3c Section 440 can.o(.bss) + .bss 0x20000df4 Section 1144 can.o(.bss) + .bss 0x2000126c Section 154 afe_sh3673520.o(.bss) + .bss 0x20001306 Section 220 rs485_modbus.o(.bss) + .bss 0x200013e2 Section 220 rs485_modbus_inverter.o(.bss) + .bss 0x200014be Section 384 screen.o(.bss) + .bss 0x20001640 Section 100 soe.o(.bss) + .bss 0x200016a4 Section 120 ocv.o(.bss) + .bss 0x2000171c Section 1593 mbo26a.o(.bss) + .bss 0x20001d58 Section 96 libspace.o(.bss) + HEAP 0x20001db8 Section 512 startup_stm32f10x_hd.o(HEAP) + Heap_Mem 0x20001db8 Data 512 startup_stm32f10x_hd.o(HEAP) + STACK 0x20001fb8 Section 1024 startup_stm32f10x_hd.o(STACK) + Stack_Mem 0x20001fb8 Data 1024 startup_stm32f10x_hd.o(STACK) + __initial_sp 0x200023b8 Data 0 startup_stm32f10x_hd.o(STACK) + + Global Symbols + + Symbol Name Value Ov Type Size Object(Section) + + BuildAttributes$$THM_ISAv4$P$D$K$B$S$PE$A:L22UL41UL21$X:L11$S22US41US21$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OTIME$ROPI$IEEEX$EBA8$UX$STANDARDLIB$REQ8$PRES8$EABIv2 0x00000000 Number 0 anon$$obj.o ABSOLUTE + __ARM_use_no_argv 0x00000000 Number 0 main.o ABSOLUTE + _printf_flags 0x00000000 Number 0 printf_stubs.o ABSOLUTE + _printf_return_value 0x00000000 Number 0 printf_stubs.o ABSOLUTE + _printf_sizespec 0x00000000 Number 0 printf_stubs.o ABSOLUTE + _printf_widthprec 0x00000000 Number 0 printf_stubs.o ABSOLUTE + __ARM_exceptions_init - Undefined Weak Reference + __alloca_initialize - Undefined Weak Reference + __arm_preinit_ - Undefined Weak Reference + __cpp_initialize__aeabi_ - Undefined Weak Reference + __cxa_finalize - Undefined Weak Reference + __sigvec_lookup - Undefined Weak Reference + _atexit_init - Undefined Weak Reference + _call_atexit_fns - Undefined Weak Reference + _clock_init - Undefined Weak Reference + _fp_trap_init - Undefined Weak Reference + _fp_trap_shutdown - Undefined Weak Reference + _get_lc_collate - Undefined Weak Reference + _get_lc_monetary - Undefined Weak Reference + _get_lc_time - Undefined Weak Reference + _getenv_init - Undefined Weak Reference + _handle_redirection - Undefined Weak Reference + _init_alloc - Undefined Weak Reference + _init_user_alloc - Undefined Weak Reference + _initio - Undefined Weak Reference + _printf_mbtowc - Undefined Weak Reference + _printf_wc - Undefined Weak Reference + _rand_init - Undefined Weak Reference + _scanf_longlong - Undefined Weak Reference + _scanf_mbtowc - Undefined Weak Reference + _scanf_real - Undefined Weak Reference + _scanf_string - Undefined Weak Reference + _scanf_wctomb - Undefined Weak Reference + _scanf_wstring - Undefined Weak Reference + _signal_finish - Undefined Weak Reference + _signal_init - Undefined Weak Reference + _terminate_alloc - Undefined Weak Reference + _terminate_user_alloc - Undefined Weak Reference + _terminateio - Undefined Weak Reference + __Vectors_Size 0x00000130 Number 0 startup_stm32f10x_hd.o ABSOLUTE + __Vectors 0x08000000 Data 4 startup_stm32f10x_hd.o(RESET) + __Vectors_End 0x08000130 Data 0 startup_stm32f10x_hd.o(RESET) + __main 0x08000131 Thumb Code 8 __main.o(!!!main) + __scatterload 0x08000139 Thumb Code 0 __scatter.o(!!!scatter) + __scatterload_rt2 0x08000139 Thumb Code 44 __scatter.o(!!!scatter) + __scatterload_rt2_thumb_only 0x08000139 Thumb Code 0 __scatter.o(!!!scatter) + __scatterload_null 0x08000147 Thumb Code 0 __scatter.o(!!!scatter) + __decompress 0x0800016d Thumb Code 90 __dczerorl2.o(!!dczerorl2) + __decompress1 0x0800016d Thumb Code 0 __dczerorl2.o(!!dczerorl2) + __scatterload_zeroinit 0x080001c9 Thumb Code 28 __scatter_zi.o(!!handler_zi) + _printf_n 0x080001e5 Thumb Code 0 _printf_n.o(.ARM.Collect$$_printf_percent$$00000001) + _printf_percent 0x080001e5 Thumb Code 0 _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) + _printf_p 0x080001eb Thumb Code 0 _printf_p.o(.ARM.Collect$$_printf_percent$$00000002) + _printf_f 0x080001f1 Thumb Code 0 _printf_f.o(.ARM.Collect$$_printf_percent$$00000003) + _printf_e 0x080001f7 Thumb Code 0 _printf_e.o(.ARM.Collect$$_printf_percent$$00000004) + _printf_g 0x080001fd Thumb Code 0 _printf_g.o(.ARM.Collect$$_printf_percent$$00000005) + _printf_a 0x08000203 Thumb Code 0 _printf_a.o(.ARM.Collect$$_printf_percent$$00000006) + _printf_ll 0x08000209 Thumb Code 0 _printf_ll.o(.ARM.Collect$$_printf_percent$$00000007) + _printf_i 0x08000213 Thumb Code 0 _printf_i.o(.ARM.Collect$$_printf_percent$$00000008) + _printf_d 0x08000219 Thumb Code 0 _printf_d.o(.ARM.Collect$$_printf_percent$$00000009) + _printf_u 0x0800021f Thumb Code 0 _printf_u.o(.ARM.Collect$$_printf_percent$$0000000A) + _printf_o 0x08000225 Thumb Code 0 _printf_o.o(.ARM.Collect$$_printf_percent$$0000000B) + _printf_x 0x0800022b Thumb Code 0 _printf_x.o(.ARM.Collect$$_printf_percent$$0000000C) + _printf_lli 0x08000231 Thumb Code 0 _printf_lli.o(.ARM.Collect$$_printf_percent$$0000000D) + _printf_lld 0x08000237 Thumb Code 0 _printf_lld.o(.ARM.Collect$$_printf_percent$$0000000E) + _printf_llu 0x0800023d Thumb Code 0 _printf_llu.o(.ARM.Collect$$_printf_percent$$0000000F) + _printf_llo 0x08000243 Thumb Code 0 _printf_llo.o(.ARM.Collect$$_printf_percent$$00000010) + _printf_llx 0x08000249 Thumb Code 0 _printf_llx.o(.ARM.Collect$$_printf_percent$$00000011) + _printf_l 0x0800024f Thumb Code 0 _printf_l.o(.ARM.Collect$$_printf_percent$$00000012) + _printf_c 0x08000259 Thumb Code 0 _printf_c.o(.ARM.Collect$$_printf_percent$$00000013) + _printf_s 0x0800025f Thumb Code 0 _printf_s.o(.ARM.Collect$$_printf_percent$$00000014) + _printf_lc 0x08000265 Thumb Code 0 _printf_lc.o(.ARM.Collect$$_printf_percent$$00000015) + _printf_ls 0x0800026b Thumb Code 0 _printf_ls.o(.ARM.Collect$$_printf_percent$$00000016) + _printf_percent_end 0x08000271 Thumb Code 0 _printf_percent_end.o(.ARM.Collect$$_printf_percent$$00000017) + __rt_lib_init 0x08000275 Thumb Code 0 libinit.o(.ARM.Collect$$libinit$$00000000) + __rt_lib_init_fp_1 0x08000277 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000002) + __rt_lib_init_heap_1 0x08000277 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000000A) + __rt_lib_init_lc_common 0x08000277 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000000F) + __rt_lib_init_preinit_1 0x08000277 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000004) + __rt_lib_init_rand_1 0x08000277 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000000E) + __rt_lib_init_user_alloc_1 0x08000277 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000000C) + __rt_lib_init_lc_collate_1 0x0800027d Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000011) + __rt_lib_init_lc_ctype_2 0x0800027d Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000012) + __rt_lib_init_lc_ctype_1 0x08000289 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000013) + __rt_lib_init_lc_monetary_1 0x08000289 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000015) + __rt_lib_init_lc_numeric_2 0x08000289 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000016) + __rt_lib_init_alloca_1 0x08000293 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000002E) + __rt_lib_init_argv_1 0x08000293 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000002C) + __rt_lib_init_atexit_1 0x08000293 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000001B) + __rt_lib_init_clock_1 0x08000293 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000021) + __rt_lib_init_cpp_1 0x08000293 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000032) + __rt_lib_init_exceptions_1 0x08000293 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000030) + __rt_lib_init_fp_trap_1 0x08000293 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000001F) + __rt_lib_init_getenv_1 0x08000293 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000023) + __rt_lib_init_lc_numeric_1 0x08000293 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000017) + __rt_lib_init_lc_time_1 0x08000293 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000019) + __rt_lib_init_return 0x08000293 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000033) + __rt_lib_init_signal_1 0x08000293 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000001D) + __rt_lib_init_stdio_1 0x08000293 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000025) + __rt_lib_shutdown 0x08000295 Thumb Code 0 libshutdown.o(.ARM.Collect$$libshutdown$$00000000) + __rt_lib_shutdown_cpp_1 0x08000297 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000002) + __rt_lib_shutdown_fp_trap_1 0x08000297 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000007) + __rt_lib_shutdown_heap_1 0x08000297 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F) + __rt_lib_shutdown_return 0x08000297 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000010) + __rt_lib_shutdown_signal_1 0x08000297 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000A) + __rt_lib_shutdown_stdio_1 0x08000297 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000004) + __rt_lib_shutdown_user_alloc_1 0x08000297 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C) + __rt_entry 0x08000299 Thumb Code 0 __rtentry.o(.ARM.Collect$$rtentry$$00000000) + __rt_entry_presh_1 0x08000299 Thumb Code 0 __rtentry2.o(.ARM.Collect$$rtentry$$00000002) + __rt_entry_sh 0x08000299 Thumb Code 0 __rtentry4.o(.ARM.Collect$$rtentry$$00000004) + __rt_entry_li 0x0800029f Thumb Code 0 __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) + __rt_entry_postsh_1 0x0800029f Thumb Code 0 __rtentry2.o(.ARM.Collect$$rtentry$$00000009) + __rt_entry_main 0x080002a3 Thumb Code 0 __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) + __rt_entry_postli_1 0x080002a3 Thumb Code 0 __rtentry2.o(.ARM.Collect$$rtentry$$0000000C) + __rt_exit 0x080002ab Thumb Code 0 rtexit.o(.ARM.Collect$$rtexit$$00000000) + __rt_exit_ls 0x080002ad Thumb Code 0 rtexit2.o(.ARM.Collect$$rtexit$$00000003) + __rt_exit_prels_1 0x080002ad Thumb Code 0 rtexit2.o(.ARM.Collect$$rtexit$$00000002) + __rt_exit_exit 0x080002b1 Thumb Code 0 rtexit2.o(.ARM.Collect$$rtexit$$00000004) + Reset_Handler 0x080002b9 Thumb Code 8 startup_stm32f10x_hd.o(.text) + ADC1_2_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + ADC3_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + CAN1_RX1_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + CAN1_SCE_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + DMA1_Channel1_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + DMA1_Channel2_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + DMA1_Channel3_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + DMA1_Channel4_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + DMA1_Channel5_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + DMA1_Channel6_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + DMA1_Channel7_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + DMA2_Channel1_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + DMA2_Channel2_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + DMA2_Channel3_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + DMA2_Channel4_5_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + EXTI0_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + EXTI15_10_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + EXTI1_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + EXTI2_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + EXTI3_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + EXTI4_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + EXTI9_5_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + FLASH_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + FSMC_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + I2C1_ER_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + I2C1_EV_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + I2C2_ER_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + I2C2_EV_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + PVD_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + RCC_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + RTCAlarm_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + RTC_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + SDIO_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + SPI1_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + SPI2_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + SPI3_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + TAMPER_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM1_BRK_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM1_CC_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM1_TRG_COM_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM1_UP_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM2_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM4_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM5_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM6_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM7_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM8_BRK_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM8_CC_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM8_TRG_COM_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + TIM8_UP_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + UART5_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + USBWakeUp_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + USB_HP_CAN1_TX_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + WWDG_IRQHandler 0x080002d3 Thumb Code 0 startup_stm32f10x_hd.o(.text) + __user_initial_stackheap 0x080002d5 Thumb Code 0 startup_stm32f10x_hd.o(.text) + vsnprintf 0x080002f9 Thumb Code 48 vsnprintf.o(.text) + __2sprintf 0x0800032d Thumb Code 38 __2sprintf.o(.text) + _printf_pre_padding 0x08000359 Thumb Code 44 _printf_pad.o(.text) + _printf_post_padding 0x08000385 Thumb Code 34 _printf_pad.o(.text) + _printf_str 0x080003a7 Thumb Code 82 _printf_str.o(.text) + _printf_int_dec 0x080003f9 Thumb Code 104 _printf_dec.o(.text) + _printf_longlong_hex 0x08000471 Thumb Code 86 _printf_hex_int_ll_ptr.o(.text) + _printf_int_hex 0x080004c7 Thumb Code 28 _printf_hex_int_ll_ptr.o(.text) + _printf_ll_hex 0x080004e3 Thumb Code 12 _printf_hex_int_ll_ptr.o(.text) + _printf_hex_ptr 0x080004ef Thumb Code 18 _printf_hex_int_ll_ptr.o(.text) + __printf 0x08000505 Thumb Code 388 __printf_flags_ss_wp.o(.text) + __0sscanf 0x0800068d Thumb Code 52 __0sscanf.o(.text) + _scanf_int 0x080006c9 Thumb Code 332 _scanf_int.o(.text) + strchr 0x08000815 Thumb Code 20 strchr.o(.text) + strstr 0x08000829 Thumb Code 36 strstr.o(.text) + memcmp 0x0800084d Thumb Code 88 memcmp.o(.text) + strcpy 0x080008a5 Thumb Code 72 strcpy.o(.text) + strlen 0x080008ed Thumb Code 62 strlen.o(.text) + __aeabi_memcpy 0x0800092b Thumb Code 0 rt_memcpy_v6.o(.text) + __rt_memcpy 0x0800092b Thumb Code 138 rt_memcpy_v6.o(.text) + _memcpy_lastbytes 0x08000991 Thumb Code 0 rt_memcpy_v6.o(.text) + __aeabi_memcpy4 0x080009b5 Thumb Code 0 rt_memcpy_w.o(.text) + __aeabi_memcpy8 0x080009b5 Thumb Code 0 rt_memcpy_w.o(.text) + __rt_memcpy_w 0x080009b5 Thumb Code 100 rt_memcpy_w.o(.text) + _memcpy_lastbytes_aligned 0x080009fd Thumb Code 0 rt_memcpy_w.o(.text) + __aeabi_memset 0x08000a19 Thumb Code 16 aeabi_memset.o(.text) + __aeabi_memclr 0x08000a29 Thumb Code 0 rt_memclr.o(.text) + __rt_memclr 0x08000a29 Thumb Code 68 rt_memclr.o(.text) + _memset 0x08000a2d Thumb Code 0 rt_memclr.o(.text) + __aeabi_memclr4 0x08000a6d Thumb Code 0 rt_memclr_w.o(.text) + __aeabi_memclr8 0x08000a6d Thumb Code 0 rt_memclr_w.o(.text) + __rt_memclr_w 0x08000a6d Thumb Code 78 rt_memclr_w.o(.text) + _memset_w 0x08000a71 Thumb Code 0 rt_memclr_w.o(.text) + strncpy 0x08000abb Thumb Code 86 strncpy.o(.text) + __use_two_region_memory 0x08000b11 Thumb Code 2 heapauxi.o(.text) + __rt_heap_escrow$2region 0x08000b13 Thumb Code 2 heapauxi.o(.text) + __rt_heap_expand$2region 0x08000b15 Thumb Code 2 heapauxi.o(.text) + _printf_truncate_signed 0x08000b17 Thumb Code 18 _printf_truncate.o(.text) + _printf_truncate_unsigned 0x08000b29 Thumb Code 18 _printf_truncate.o(.text) + _printf_int_common 0x08000b3b Thumb Code 178 _printf_intcommon.o(.text) + _printf_charcount 0x08000bed Thumb Code 40 _printf_charcount.o(.text) + _printf_char_common 0x08000c1f Thumb Code 32 _printf_char_common.o(.text) + _sputc 0x08000c45 Thumb Code 10 _sputc.o(.text) + _snputc 0x08000c4f Thumb Code 16 _snputc.o(.text) + _printf_cs_common 0x08000c5f Thumb Code 20 _printf_char.o(.text) + _printf_char 0x08000c73 Thumb Code 16 _printf_char.o(.text) + _printf_string 0x08000c83 Thumb Code 8 _printf_char.o(.text) + _printf_wctomb 0x08000c8d Thumb Code 182 _printf_wctomb.o(.text) + _printf_longlong_dec 0x08000d49 Thumb Code 108 _printf_longlong_dec.o(.text) + _printf_longlong_oct 0x08000dc5 Thumb Code 66 _printf_oct_int_ll.o(.text) + _printf_int_oct 0x08000e07 Thumb Code 24 _printf_oct_int_ll.o(.text) + _printf_ll_oct 0x08000e1f Thumb Code 12 _printf_oct_int_ll.o(.text) + _chval 0x08000e35 Thumb Code 28 _chval.o(.text) + __vfscanf_char 0x08000e5d Thumb Code 24 scanf_char.o(.text) + _sgetc 0x08000e7d Thumb Code 30 _sgetc.o(.text) + _sbackspace 0x08000e9b Thumb Code 34 _sgetc.o(.text) + _ll_udiv10 0x08000ebd Thumb Code 138 lludiv10.o(.text) + isspace 0x08000f47 Thumb Code 18 isspace.o(.text) + __lib_sel_fp_printf 0x08000f59 Thumb Code 2 _printf_fp_dec.o(.text) + _printf_fp_dec_real 0x0800110b Thumb Code 620 _printf_fp_dec.o(.text) + _printf_fp_hex_real 0x08001379 Thumb Code 756 _printf_fp_hex.o(.text) + _printf_lcs_common 0x08001675 Thumb Code 20 _printf_wchar.o(.text) + _printf_wchar 0x08001689 Thumb Code 16 _printf_wchar.o(.text) + _printf_wstring 0x08001699 Thumb Code 8 _printf_wchar.o(.text) + __vfscanf 0x080016a1 Thumb Code 878 _scanf.o(.text) + _wcrtomb 0x08001a15 Thumb Code 64 _wcrtomb.o(.text) + __user_libspace 0x08001a55 Thumb Code 8 libspace.o(.text) + __user_perproc_libspace 0x08001a55 Thumb Code 0 libspace.o(.text) + __user_perthread_libspace 0x08001a55 Thumb Code 0 libspace.o(.text) + __user_setup_stackheap 0x08001a5d Thumb Code 74 sys_stackheap_outer.o(.text) + __rt_ctype_table 0x08001aa9 Thumb Code 16 rt_ctype_table.o(.text) + __rt_locale 0x08001ab9 Thumb Code 8 rt_locale_intlibspace.o(.text) + _printf_fp_infnan 0x08001ac1 Thumb Code 112 _printf_fp_infnan.o(.text) + _btod_etento 0x08001b41 Thumb Code 224 bigflt0.o(.text) + exit 0x08001c25 Thumb Code 18 exit.o(.text) + strcmp 0x08001c39 Thumb Code 128 strcmpv7m.o(.text) + _sys_exit 0x08001cb9 Thumb Code 8 sys_exit.o(.text) + __I$use$semihosting 0x08001cc5 Thumb Code 0 use_no_semi.o(.text) + __use_no_semihosting_swi 0x08001cc5 Thumb Code 2 use_no_semi.o(.text) + __semihosting_library_function 0x08001cc7 Thumb Code 0 indicate_semi.o(.text) + _btod_d2e 0x08001cc7 Thumb Code 62 btod.o(CL$$btod_d2e) + _d2e_denorm_low 0x08001d05 Thumb Code 70 btod.o(CL$$btod_d2e_denorm_low) + _d2e_norm_op1 0x08001d4b Thumb Code 96 btod.o(CL$$btod_d2e_norm_op1) + __btod_div_common 0x08001dab Thumb Code 696 btod.o(CL$$btod_div_common) + _e2e 0x080020e3 Thumb Code 220 btod.o(CL$$btod_e2e) + _btod_ediv 0x080021bf Thumb Code 42 btod.o(CL$$btod_ediv) + _btod_emul 0x080021e9 Thumb Code 42 btod.o(CL$$btod_emul) + __btod_mult_common 0x08002213 Thumb Code 580 btod.o(CL$$btod_mult_common) + ADC_Cmd 0x08002457 Thumb Code 20 stm32f10x_adc.o(i.ADC_Cmd) + ADC_DeInit 0x0800246d Thumb Code 56 stm32f10x_adc.o(i.ADC_DeInit) + ADC_GetCalibrationStatus 0x080024b1 Thumb Code 14 stm32f10x_adc.o(i.ADC_GetCalibrationStatus) + ADC_GetConversionValue 0x080024bf Thumb Code 6 stm32f10x_adc.o(i.ADC_GetConversionValue) + ADC_GetFlagStatus 0x080024c5 Thumb Code 14 stm32f10x_adc.o(i.ADC_GetFlagStatus) + ADC_GetResetCalibrationStatus 0x080024d3 Thumb Code 14 stm32f10x_adc.o(i.ADC_GetResetCalibrationStatus) + ADC_GetVal 0x080024e1 Thumb Code 46 adc.o(i.ADC_GetVal) + ADC_Init 0x08002515 Thumb Code 62 stm32f10x_adc.o(i.ADC_Init) + ADC_RegularChannelConfig 0x0800255d Thumb Code 116 stm32f10x_adc.o(i.ADC_RegularChannelConfig) + ADC_ResetCalibration 0x080025d1 Thumb Code 10 stm32f10x_adc.o(i.ADC_ResetCalibration) + ADC_SoftwareStartConvCmd 0x080025db Thumb Code 20 stm32f10x_adc.o(i.ADC_SoftwareStartConvCmd) + ADC_StartCalibration 0x080025ef Thumb Code 10 stm32f10x_adc.o(i.ADC_StartCalibration) + ADDR_Assign_Moni 0x080025f9 Thumb Code 80 gpio.o(i.ADDR_Assign_Moni) + ADDR_Rank_Moni 0x08002651 Thumb Code 132 gpio.o(i.ADDR_Rank_Moni) + AFE_Ctrl 0x080026e9 Thumb Code 330 afe_sh3673520.o(i.AFE_Ctrl) + AFE_CurrentProcess 0x08002849 Thumb Code 402 afe_sh3673520.o(i.AFE_CurrentProcess) + AFE_ProtectProcess 0x080029f5 Thumb Code 1790 afe_sh3673520.o(i.AFE_ProtectProcess) + AFE_Read 0x080030f3 Thumb Code 54 afe_sh3673520.o(i.AFE_Read) + AFE_ReadMulByte 0x08003129 Thumb Code 302 spi.o(i.AFE_ReadMulByte) + AFE_Reset 0x08003261 Thumb Code 140 spi.o(i.AFE_Reset) + AFE_TemperaProcess 0x080032f5 Thumb Code 152 afe_sh3673520.o(i.AFE_TemperaProcess) + AFE_VoltageProcess 0x08003399 Thumb Code 990 afe_sh3673520.o(i.AFE_VoltageProcess) + AFE_Write 0x08003789 Thumb Code 76 afe_sh3673520.o(i.AFE_Write) + AFE_WriteOneByte 0x080037d5 Thumb Code 144 spi.o(i.AFE_WriteOneByte) + Addr_Set 0x0800386d Thumb Code 166 global.o(i.Addr_Set) + BKP_DeInit 0x08003925 Thumb Code 18 stm32f10x_bkp.o(i.BKP_DeInit) + BKP_ReadBackupRegister 0x08003939 Thumb Code 12 stm32f10x_bkp.o(i.BKP_ReadBackupRegister) + BKP_WriteBackupRegister 0x08003949 Thumb Code 12 stm32f10x_bkp.o(i.BKP_WriteBackupRegister) + BLE_CheckName 0x08003959 Thumb Code 96 mbo26a.o(i.BLE_CheckName) + BLE_ClearBuf 0x080039f5 Thumb Code 16 mbo26a.o(i.BLE_ClearBuf) + BLE_ClearFlg 0x08003a0d Thumb Code 16 mbo26a.o(i.BLE_ClearFlg) + BLE_GETPARA 0x08003a21 Thumb Code 148 mbo26a.o(i.BLE_GETPARA) + BLE_IO_Init 0x08003aed Thumb Code 50 mbo26a.o(i.BLE_IO_Init) + BLE_IQ_Transmit 0x08003b25 Thumb Code 4254 mbo26a.o(i.BLE_IQ_Transmit) + BLE_IQ_Update 0x08004d55 Thumb Code 680 mbo26a.o(i.BLE_IQ_Update) + BLE_IT_Receive 0x08005009 Thumb Code 36 mbo26a.o(i.BLE_IT_Receive) + BLE_IT_Update 0x08005039 Thumb Code 152 mbo26a.o(i.BLE_IT_Update) + BLE_Init 0x08005135 Thumb Code 40 mbo26a.o(i.BLE_Init) + BLE_Open 0x08005161 Thumb Code 2 mbo26a.o(i.BLE_Open) + BLE_PUTSRVC 0x08005165 Thumb Code 220 mbo26a.o(i.BLE_PUTSRVC) + BLE_Reset 0x08005299 Thumb Code 20 mbo26a.o(i.BLE_Reset) + BLE_SETPARA 0x080052c1 Thumb Code 222 mbo26a.o(i.BLE_SETPARA) + BLE_SetBaud 0x080053f5 Thumb Code 26 mbo26a.o(i.BLE_SetBaud) + BLE_TIM_Moni 0x0800541d Thumb Code 38 mbo26a.o(i.BLE_TIM_Moni) + BLE_WriteName 0x08005449 Thumb Code 4 mbo26a.o(i.BLE_WriteName) + BLE_printf 0x0800544d Thumb Code 50 mbo26a.o(i.BLE_printf) + BusFault_Handler 0x08005489 Thumb Code 2 stm32f10x_it.o(i.BusFault_Handler) + CALI_CurrentProcess 0x0800548d Thumb Code 102 afe_sh3673520.o(i.CALI_CurrentProcess) + CAN1_SendData 0x08005511 Thumb Code 138 can.o(i.CAN1_SendData) + CAN_DeInit 0x080055ad Thumb Code 38 stm32f10x_can.o(i.CAN_DeInit) + CAN_FilterInit 0x080055d9 Thumb Code 194 stm32f10x_can.o(i.CAN_FilterInit) + CAN_GetITStatus 0x080056a5 Thumb Code 162 stm32f10x_can.o(i.CAN_GetITStatus) + CAN_ITConfig 0x0800574d Thumb Code 16 stm32f10x_can.o(i.CAN_ITConfig) + CAN_Init 0x0800575d Thumb Code 232 stm32f10x_can.o(i.CAN_Init) + CAN_Protocol_Deye 0x08005845 Thumb Code 664 protocolswitch_p1.o(i.CAN_Protocol_Deye) + CAN_Protocol_Growatt 0x08005b09 Thumb Code 862 protocolswitch_p1.o(i.CAN_Protocol_Growatt) + CAN_Protocol_Pylon 0x08005ea1 Thumb Code 1378 protocolswitch_p1.o(i.CAN_Protocol_Pylon) + CAN_Protocol_SolArk 0x08006405 Thumb Code 770 protocolswitch_p1.o(i.CAN_Protocol_SolArk) + CAN_Protocol_solis 0x0800673d Thumb Code 590 protocolswitch_p1.o(i.CAN_Protocol_solis) + CAN_Receive 0x080069c1 Thumb Code 144 stm32f10x_can.o(i.CAN_Receive) + CAN_StructInit 0x08006a51 Thumb Code 32 stm32f10x_can.o(i.CAN_StructInit) + CAN_TIM_Moni 0x08006a71 Thumb Code 20 can.o(i.CAN_TIM_Moni) + CAN_Transmit 0x08006a89 Thumb Code 164 stm32f10x_can.o(i.CAN_Transmit) + CAN_TransmitStatus 0x08006b2d Thumb Code 88 stm32f10x_can.o(i.CAN_TransmitStatus) + CAN_UpdateData 0x08006b99 Thumb Code 46 can.o(i.CAN_UpdateData) + CHG_LIMIT_Ctrl 0x08006bcd Thumb Code 212 afe_sh3673520.o(i.CHG_LIMIT_Ctrl) + CHG_LIMIT_Init 0x08006cad Thumb Code 68 pwm.o(i.CHG_LIMIT_Init) + CHG_LIMIT_Off 0x08006cf5 Thumb Code 46 pwm.o(i.CHG_LIMIT_Off) + CHG_LIMIT_On 0x08006d2d Thumb Code 146 pwm.o(i.CHG_LIMIT_On) + CHG_LIMIT_PWM_Adjust 0x08006ddd Thumb Code 188 pwm.o(i.CHG_LIMIT_PWM_Adjust) + CRC16_Cal 0x08006ebd Thumb Code 54 rs485_modbus.o(i.CRC16_Cal) + CRC8_Cal 0x08006ef9 Thumb Code 30 global.o(i.CRC8_Cal) + CTRL_Off 0x08006f1d Thumb Code 26 afe_sh3673520.o(i.CTRL_Off) + CTRL_On 0x08006f3d Thumb Code 8 afe_sh3673520.o(i.CTRL_On) + Cali_FCC_Moni 0x08006f49 Thumb Code 218 gasgauge.o(i.Cali_FCC_Moni) + Cali_SOC_Moni 0x08007041 Thumb Code 62 gasgauge.o(i.Cali_SOC_Moni) + DO_Off 0x08007095 Thumb Code 8 gpio.o(i.DO_Off) + DO_On 0x080070a1 Thumb Code 8 gpio.o(i.DO_On) + DebugMon_Handler 0x080070ad Thumb Code 2 stm32f10x_it.o(i.DebugMon_Handler) + EEPROM_CALI_RdGain 0x080070af Thumb Code 188 i2c.o(i.EEPROM_CALI_RdGain) + EEPROM_CALI_RdZero 0x0800716b Thumb Code 186 i2c.o(i.EEPROM_CALI_RdZero) + EEPROM_CALI_WrGain 0x08007225 Thumb Code 96 i2c.o(i.EEPROM_CALI_WrGain) + EEPROM_CALI_WrZero 0x08007285 Thumb Code 96 i2c.o(i.EEPROM_CALI_WrZero) + EEPROM_RdMulByte 0x080072e5 Thumb Code 420 i2c.o(i.EEPROM_RdMulByte) + EEPROM_WrMulByte 0x08007495 Thumb Code 308 i2c.o(i.EEPROM_WrMulByte) + FCCCali_TIM_Moni 0x080075d5 Thumb Code 44 global.o(i.FCCCali_TIM_Moni) + FLASH_ClearFlag 0x0800760d Thumb Code 6 stm32f10x_flash.o(i.FLASH_ClearFlag) + FLASH_ErasePage 0x08007619 Thumb Code 56 stm32f10x_flash.o(i.FLASH_ErasePage) + FLASH_GetBank1Status 0x08007655 Thumb Code 34 stm32f10x_flash.o(i.FLASH_GetBank1Status) + FLASH_Lock 0x0800767d Thumb Code 12 stm32f10x_flash.o(i.FLASH_Lock) + FLASH_ProgramHalfWord 0x0800768d Thumb Code 48 stm32f10x_flash.o(i.FLASH_ProgramHalfWord) + FLASH_RdDataByte 0x080076c1 Thumb Code 20 flash.o(i.FLASH_RdDataByte) + FLASH_RdWord 0x080076d5 Thumb Code 26 flash.o(i.FLASH_RdWord) + FLASH_ReadCheck 0x080076f1 Thumb Code 78 flash.o(i.FLASH_ReadCheck) + FLASH_Unlock 0x08007749 Thumb Code 12 stm32f10x_flash.o(i.FLASH_Unlock) + FLASH_UpdateMemory 0x08007761 Thumb Code 26 flash.o(i.FLASH_UpdateMemory) + FLASH_WaitForLastOperation 0x08007785 Thumb Code 36 stm32f10x_flash.o(i.FLASH_WaitForLastOperation) + FLASH_WrData 0x080077a9 Thumb Code 64 flash.o(i.FLASH_WrData) + GPIO_Init 0x080077e9 Thumb Code 162 stm32f10x_gpio.o(i.GPIO_Init) + GPIO_PinRemapConfig 0x0800788d Thumb Code 82 stm32f10x_gpio.o(i.GPIO_PinRemapConfig) + GPIO_ReadInputDataBit 0x080078e5 Thumb Code 14 stm32f10x_gpio.o(i.GPIO_ReadInputDataBit) + GPIO_ResetBits 0x080078f3 Thumb Code 4 stm32f10x_gpio.o(i.GPIO_ResetBits) + GPIO_SetBits 0x080078f7 Thumb Code 4 stm32f10x_gpio.o(i.GPIO_SetBits) + GaugeManage 0x080078fd Thumb Code 1226 gasgauge.o(i.GaugeManage) + GetStr 0x08007dcd Thumb Code 84 global.o(i.GetStr) + HAL_GPIO_TogglePin 0x08007e21 Thumb Code 16 gpio.o(i.HAL_GPIO_TogglePin) + HardFault_Handler 0x08007e31 Thumb Code 20 stm32f10x_it.o(i.HardFault_Handler) + I2C_AcknowledgeConfig 0x08007e4d Thumb Code 20 stm32f10x_i2c.o(i.I2C_AcknowledgeConfig) + I2C_CheckEvent 0x08007e61 Thumb Code 24 stm32f10x_i2c.o(i.I2C_CheckEvent) + I2C_Cmd 0x08007e79 Thumb Code 20 stm32f10x_i2c.o(i.I2C_Cmd) + I2C_DeInit 0x08007e8d Thumb Code 38 stm32f10x_i2c.o(i.I2C_DeInit) + I2C_GenerateSTART 0x08007eb9 Thumb Code 20 stm32f10x_i2c.o(i.I2C_GenerateSTART) + I2C_GenerateSTOP 0x08007ecd Thumb Code 20 stm32f10x_i2c.o(i.I2C_GenerateSTOP) + I2C_GetFlagStatus 0x08007ee1 Thumb Code 42 stm32f10x_i2c.o(i.I2C_GetFlagStatus) + I2C_Init 0x08007f0d Thumb Code 178 stm32f10x_i2c.o(i.I2C_Init) + I2C_ReceiveData 0x08007fc9 Thumb Code 6 stm32f10x_i2c.o(i.I2C_ReceiveData) + I2C_Send7bitAddress 0x08007fcf Thumb Code 16 stm32f10x_i2c.o(i.I2C_Send7bitAddress) + I2C_SendData 0x08007fdf Thumb Code 4 stm32f10x_i2c.o(i.I2C_SendData) + IO1_IN 0x08007fe5 Thumb Code 10 gpio.o(i.IO1_IN) + IO2_OUTReset 0x08007ff5 Thumb Code 10 gpio.o(i.IO2_OUTReset) + IO2_OUTSet 0x08008005 Thumb Code 10 gpio.o(i.IO2_OUTSet) + IO3_IN 0x08008015 Thumb Code 8 gpio.o(i.IO3_IN) + IWDG_Enable 0x08008021 Thumb Code 10 stm32f10x_iwdg.o(i.IWDG_Enable) + IWDG_Feed 0x08008031 Thumb Code 4 wdg.o(i.IWDG_Feed) + IWDG_ReloadCounter 0x08008035 Thumb Code 10 stm32f10x_iwdg.o(i.IWDG_ReloadCounter) + IWDG_SetPrescaler 0x08008045 Thumb Code 6 stm32f10x_iwdg.o(i.IWDG_SetPrescaler) + IWDG_SetReload 0x08008051 Thumb Code 6 stm32f10x_iwdg.o(i.IWDG_SetReload) + IWDG_WriteAccessCmd 0x0800805d Thumb Code 6 stm32f10x_iwdg.o(i.IWDG_WriteAccessCmd) + InitGasGauge 0x08008069 Thumb Code 384 gasgauge.o(i.InitGasGauge) + Is_Leap_Year 0x080081fd Thumb Code 44 rtc.o(i.Is_Leap_Year) + KEY_IN 0x08008229 Thumb Code 8 gpio.o(i.KEY_IN) + KEY_TIM_Moni 0x08008235 Thumb Code 174 gpio.o(i.KEY_TIM_Moni) + LED1_Off 0x080082e9 Thumb Code 8 gpio.o(i.LED1_Off) + LED1_On 0x080082f5 Thumb Code 8 gpio.o(i.LED1_On) + LED2_Off 0x08008301 Thumb Code 10 gpio.o(i.LED2_Off) + LED2_On 0x08008311 Thumb Code 10 gpio.o(i.LED2_On) + LED3_Off 0x08008321 Thumb Code 8 gpio.o(i.LED3_Off) + LED3_On 0x0800832d Thumb Code 8 gpio.o(i.LED3_On) + LED4_Off 0x08008339 Thumb Code 8 gpio.o(i.LED4_Off) + LED4_On 0x08008345 Thumb Code 8 gpio.o(i.LED4_On) + LED_ALARM_Off 0x08008351 Thumb Code 8 gpio.o(i.LED_ALARM_Off) + LED_ALARM_On 0x0800835d Thumb Code 8 gpio.o(i.LED_ALARM_On) + LED_ALARM_Toggle 0x08008369 Thumb Code 8 gpio.o(i.LED_ALARM_Toggle) + LED_RUN_Off 0x08008375 Thumb Code 10 gpio.o(i.LED_RUN_Off) + LED_RUN_On 0x08008385 Thumb Code 10 gpio.o(i.LED_RUN_On) + LED_RUN_Toggle 0x08008395 Thumb Code 10 gpio.o(i.LED_RUN_Toggle) + LOAD_VOL 0x080083a5 Thumb Code 26 adc.o(i.LOAD_VOL) + MCU_TemperaProcess 0x080083c9 Thumb Code 440 adc.o(i.MCU_TemperaProcess) + MEMORY_UpdateAFE 0x0800858d Thumb Code 232 afe_sh3673520.o(i.MEMORY_UpdateAFE) + MEMORY_UpdateFlash 0x0800867d Thumb Code 90 flash.o(i.MEMORY_UpdateFlash) + MODBUS1_CtrlMOS_Rx 0x080086e1 Thumb Code 68 rs485_modbus_inverter.o(i.MODBUS1_CtrlMOS_Rx) + MODBUS1_F03_Rx 0x08008729 Thumb Code 188 rs485_modbus_inverter.o(i.MODBUS1_F03_Rx) + MODBUS1_F10_Rx 0x080087f5 Thumb Code 292 rs485_modbus_inverter.o(i.MODBUS1_F10_Rx) + MODBUS1_Faa_Rx 0x0800892d Thumb Code 60 rs485_modbus_inverter.o(i.MODBUS1_Faa_Rx) + MODBUS1_Fbb_Rx 0x08008975 Thumb Code 76 rs485_modbus_inverter.o(i.MODBUS1_Fbb_Rx) + MODBUS1_IQ_Transmit 0x080089cd Thumb Code 1088 rs485_modbus_inverter.o(i.MODBUS1_IQ_Transmit) + MODBUS1_IT_Receive 0x08008e0d Thumb Code 60 rs485_modbus_inverter.o(i.MODBUS1_IT_Receive) + MODBUS1_IT_TIMUpdate 0x08008e55 Thumb Code 770 rs485_modbus_inverter.o(i.MODBUS1_IT_TIMUpdate) + MODBUS1_Init 0x08009199 Thumb Code 38 rs485_modbus_inverter.o(i.MODBUS1_Init) + MODBUS1_TIM_Moni 0x080091c5 Thumb Code 26 rs485_modbus_inverter.o(i.MODBUS1_TIM_Moni) + MODBUS1_UpdateData 0x080091e5 Thumb Code 22 rs485_modbus_inverter.o(i.MODBUS1_UpdateData) + MODBUS_AddrAssign_Tx 0x08009201 Thumb Code 268 rs485_modbus.o(i.MODBUS_AddrAssign_Tx) + MODBUS_Config_RdSlave_Tx 0x0800931d Thumb Code 226 rs485_modbus.o(i.MODBUS_Config_RdSlave_Tx) + MODBUS_CtrlMOS_Rx 0x0800941d Thumb Code 68 rs485_modbus.o(i.MODBUS_CtrlMOS_Rx) + MODBUS_F03_Rx 0x08009465 Thumb Code 120 rs485_modbus.o(i.MODBUS_F03_Rx) + MODBUS_F10_Rx 0x080094e9 Thumb Code 294 rs485_modbus.o(i.MODBUS_F10_Rx) + MODBUS_Faa_Rx 0x08009629 Thumb Code 60 rs485_modbus.o(i.MODBUS_Faa_Rx) + MODBUS_Fbb_Rx 0x08009671 Thumb Code 76 rs485_modbus.o(i.MODBUS_Fbb_Rx) + MODBUS_IQ_Transmit 0x080096c9 Thumb Code 870 rs485_modbus.o(i.MODBUS_IQ_Transmit) + MODBUS_IT_Receive 0x08009a6d Thumb Code 76 rs485_modbus.o(i.MODBUS_IT_Receive) + MODBUS_IT_TIMUpdate 0x08009acd Thumb Code 764 rs485_modbus.o(i.MODBUS_IT_TIMUpdate) + MODBUS_Init 0x08009df5 Thumb Code 62 rs485_modbus.o(i.MODBUS_Init) + MODBUS_MASTER_F03_Rx 0x08009e3d Thumb Code 120 rs485_modbus.o(i.MODBUS_MASTER_F03_Rx) + MODBUS_MASTER_F10_Rx 0x08009ec9 Thumb Code 54 rs485_modbus.o(i.MODBUS_MASTER_F10_Rx) + MODBUS_Poll_Init 0x08009f0d Thumb Code 148 rs485_modbus.o(i.MODBUS_Poll_Init) + MODBUS_TIM_Moni 0x08009fb1 Thumb Code 30 rs485_modbus.o(i.MODBUS_TIM_Moni) + MemManage_Handler 0x08009fd5 Thumb Code 2 stm32f10x_it.o(i.MemManage_Handler) + NMI_Handler 0x08009fd7 Thumb Code 2 stm32f10x_it.o(i.NMI_Handler) + NVIC_PriorityGroupConfig 0x08009fd9 Thumb Code 10 misc.o(i.NVIC_PriorityGroupConfig) + PCHG_Off 0x08009fed Thumb Code 8 gpio.o(i.PCHG_Off) + PendSV_Handler 0x08009ff9 Thumb Code 2 stm32f10x_it.o(i.PendSV_Handler) + SPI2_Error 0x08009ffb Thumb Code 4 spi.o(i.SPI2_Error) + SVC_Handler 0x08009fff Thumb Code 2 stm32f10x_it.o(i.SVC_Handler) + dataFlashA 0x0800a000 Data 2048 flash.o(.ARM.__AT_0x0800A000) + MODBUS_MASTER_Polling_Tx 0x0800a801 Thumb Code 700 rs485_modbus.o(i.MODBUS_MASTER_Polling_Tx) + MODBUS_Screen_RdSlave_Tx 0x0800aad5 Thumb Code 216 rs485_modbus.o(i.MODBUS_Screen_RdSlave_Tx) + MODBUS_Screen_WrSlaveAddr_Tx 0x0800abc5 Thumb Code 170 rs485_modbus.o(i.MODBUS_Screen_WrSlaveAddr_Tx) + MODBUS_WrIndex_Rx 0x0800ac81 Thumb Code 88 rs485_modbus.o(i.MODBUS_WrIndex_Rx) + MODBUS_WrIndex_Tx 0x0800ace5 Thumb Code 78 rs485_modbus.o(i.MODBUS_WrIndex_Tx) + MOD_Protocol_Growatt 0x0800ad41 Thumb Code 708 protocolswitch_p1.o(i.MOD_Protocol_Growatt) + MOD_Protocol_Voltronic 0x0800b03d Thumb Code 840 protocolswitch_p2.o(i.MOD_Protocol_Voltronic) + NVIC_Init 0x0800b3c1 Thumb Code 94 misc.o(i.NVIC_Init) + OCC2_Ctrl 0x0800b425 Thumb Code 66 afe_sh3673520.o(i.OCC2_Ctrl) + OCC2_TIM_Moni 0x0800b471 Thumb Code 64 afe_sh3673520.o(i.OCC2_TIM_Moni) + OCV_CaliSOC 0x0800b4bd Thumb Code 420 ocv.o(i.OCV_CaliSOC) + OCV_CaliSOC_DataWr 0x0800b691 Thumb Code 168 ocv.o(i.OCV_CaliSOC_DataWr) + OCV_CaliSoc_dp 0x0800b745 Thumb Code 172 ocv.o(i.OCV_CaliSoc_dp) + PCHG_Ctrl 0x0800b7f9 Thumb Code 140 gpio.o(i.PCHG_Ctrl) + PCHG_On 0x0800b895 Thumb Code 8 gpio.o(i.PCHG_On) + PCHG_StartCtrl 0x0800b8a1 Thumb Code 136 gpio.o(i.PCHG_StartCtrl) + PWM_Set_Duty_Percent 0x0800b939 Thumb Code 54 pwm.o(i.PWM_Set_Duty_Percent) + PWR_BackupAccessCmd 0x0800b97d Thumb Code 6 stm32f10x_pwr.o(i.PWR_BackupAccessCmd) + ParaChange 0x0800b989 Thumb Code 750 global.o(i.ParaChange) + RCC_ADCCLKConfig 0x0800bcc9 Thumb Code 14 stm32f10x_rcc.o(i.RCC_ADCCLKConfig) + RCC_APB1PeriphClockCmd 0x0800bcdd Thumb Code 18 stm32f10x_rcc.o(i.RCC_APB1PeriphClockCmd) + RCC_APB1PeriphResetCmd 0x0800bcf5 Thumb Code 18 stm32f10x_rcc.o(i.RCC_APB1PeriphResetCmd) + RCC_APB2PeriphClockCmd 0x0800bd0d Thumb Code 18 stm32f10x_rcc.o(i.RCC_APB2PeriphClockCmd) + RCC_APB2PeriphResetCmd 0x0800bd25 Thumb Code 18 stm32f10x_rcc.o(i.RCC_APB2PeriphResetCmd) + RCC_BackupResetCmd 0x0800bd3d Thumb Code 6 stm32f10x_rcc.o(i.RCC_BackupResetCmd) + RCC_GetClocksFreq 0x0800bd49 Thumb Code 128 stm32f10x_rcc.o(i.RCC_GetClocksFreq) + RCC_GetFlagStatus 0x0800bdd9 Thumb Code 44 stm32f10x_rcc.o(i.RCC_GetFlagStatus) + RCC_LSEConfig 0x0800be09 Thumb Code 28 stm32f10x_rcc.o(i.RCC_LSEConfig) + RCC_RTCCLKCmd 0x0800be29 Thumb Code 6 stm32f10x_rcc.o(i.RCC_RTCCLKCmd) + RCC_RTCCLKConfig 0x0800be35 Thumb Code 10 stm32f10x_rcc.o(i.RCC_RTCCLKConfig) + RTC_BackUp 0x0800be45 Thumb Code 144 rtc.o(i.RTC_BackUp) + RTC_EnterConfigMode 0x0800bee5 Thumb Code 12 stm32f10x_rtc.o(i.RTC_EnterConfigMode) + RTC_ExitConfigMode 0x0800bef5 Thumb Code 12 stm32f10x_rtc.o(i.RTC_ExitConfigMode) + RTC_GetCounter 0x0800bf05 Thumb Code 28 stm32f10x_rtc.o(i.RTC_GetCounter) + RTC_GetSynchro 0x0800bf25 Thumb Code 46 rtc.o(i.RTC_GetSynchro) + RTC_Get_Week 0x0800bf59 Thumb Code 142 rtc.o(i.RTC_Get_Week) + RTC_WaitForLastTask 0x0800bfed Thumb Code 10 stm32f10x_rtc.o(i.RTC_WaitForLastTask) + SPI_I2S_ReceiveData 0x0800bffd Thumb Code 4 stm32f10x_spi.o(i.SPI_I2S_ReceiveData) + dataFlashB 0x0800c000 Data 2048 flash.o(.ARM.__AT_0x0800C000) + RTC_Get 0x0800c801 Thumb Code 926 rtc.o(i.RTC_Get) + RTC_ITConfig 0x0800cbd1 Thumb Code 18 stm32f10x_rtc.o(i.RTC_ITConfig) + RTC_Set 0x0800cbe9 Thumb Code 288 rtc.o(i.RTC_Set) + RTC_SetCounter 0x0800cd19 Thumb Code 26 stm32f10x_rtc.o(i.RTC_SetCounter) + RTC_SetPrescaler 0x0800cd39 Thumb Code 28 stm32f10x_rtc.o(i.RTC_SetPrescaler) + RTC_WaitForSynchro 0x0800cd59 Thumb Code 18 stm32f10x_rtc.o(i.RTC_WaitForSynchro) + Refresh_BMS_SN 0x0800cd71 Thumb Code 30 global.o(i.Refresh_BMS_SN) + Refresh_FirmwareVersion 0x0800cd9d Thumb Code 36 global.o(i.Refresh_FirmwareVersion) + Refresh_HardwareVersion 0x0800cde5 Thumb Code 32 global.o(i.Refresh_HardwareVersion) + Refresh_PACK_SN 0x0800ce25 Thumb Code 34 global.o(i.Refresh_PACK_SN) + Refresh_ScreenVersion 0x0800ce55 Thumb Code 102 global.o(i.Refresh_ScreenVersion) + Release_CurAlarm 0x0800ced5 Thumb Code 228 status.o(i.Release_CurAlarm) + Release_CurProtect 0x0800cfcd Thumb Code 214 status.o(i.Release_CurProtect) + Release_OVAlarm 0x0800d0b1 Thumb Code 284 status.o(i.Release_OVAlarm) + Release_OVProtect 0x0800d1e1 Thumb Code 260 status.o(i.Release_OVProtect) + Release_UVAlarm 0x0800d2f9 Thumb Code 188 status.o(i.Release_UVAlarm) + Release_UVProtect 0x0800d3c5 Thumb Code 182 status.o(i.Release_UVProtect) + Release_afeTAlarm 0x0800d48d Thumb Code 140 status.o(i.Release_afeTAlarm) + Release_afeTProtect 0x0800d521 Thumb Code 140 status.o(i.Release_afeTProtect) + Release_amTAlarm 0x0800d5b5 Thumb Code 238 status.o(i.Release_amTAlarm) + Release_amTProtect 0x0800d6b1 Thumb Code 238 status.o(i.Release_amTProtect) + Release_mcuTAlarm 0x0800d7ad Thumb Code 256 status.o(i.Release_mcuTAlarm) + Release_mcuTProtect 0x0800d8bd Thumb Code 256 status.o(i.Release_mcuTProtect) + SCR_ClearAlarm 0x0800d9cd Thumb Code 84 screen.o(i.SCR_ClearAlarm) + SCR_DispProcotol 0x0800db19 Thumb Code 454 screen.o(i.SCR_DispProcotol) + SCR_JumpToAlarm 0x0800e0a9 Thumb Code 18 screen.o(i.SCR_JumpToAlarm) + SCR_Send_Record 0x0800e0d9 Thumb Code 542 screen.o(i.SCR_Send_Record) + SCR_Send_RecordInfo 0x0800e3e5 Thumb Code 366 screen.o(i.SCR_Send_RecordInfo) + SCR_Send_Self_BasicInfo 0x0800e669 Thumb Code 1786 screen.o(i.SCR_Send_Self_BasicInfo) + SCR_Send_Slave_BasicInfo 0x0800edc1 Thumb Code 1968 screen.o(i.SCR_Send_Slave_BasicInfo) + SCR_Send_Slave_RecordBank 0x0800f5e1 Thumb Code 60 screen.o(i.SCR_Send_Slave_RecordBank) + SCR_Send_Time 0x0800f695 Thumb Code 42 screen.o(i.SCR_Send_Time) + SCR_Send_TotalInfo 0x0800f6fd Thumb Code 452 screen.o(i.SCR_Send_TotalInfo) + SCR_Send_VER 0x0800f9c1 Thumb Code 58 screen.o(i.SCR_Send_VER) + SCR_ShowAlarm 0x0800faa5 Thumb Code 326 screen.o(i.SCR_ShowAlarm) + SCR_ShowAlarm_Slave 0x0800fde9 Thumb Code 314 screen.o(i.SCR_ShowAlarm_Slave) + SLEEP2_Refresh 0x08010109 Thumb Code 118 global.o(i.SLEEP2_Refresh) + SLEEP2_TIM_Moni 0x08010195 Thumb Code 124 global.o(i.SLEEP2_TIM_Moni) + SLEEP_Refresh 0x08010221 Thumb Code 40 global.o(i.SLEEP_Refresh) + SLEEP_TIM_Moni 0x08010259 Thumb Code 44 global.o(i.SLEEP_TIM_Moni) + SOE_BkData 0x08010291 Thumb Code 1072 soe.o(i.SOE_BkData) + SPI_Cmd 0x080106c5 Thumb Code 20 stm32f10x_spi.o(i.SPI_Cmd) + SPI_I2S_DeInit 0x080106d9 Thumb Code 72 stm32f10x_spi.o(i.SPI_I2S_DeInit) + SPI_I2S_GetFlagStatus 0x0801072d Thumb Code 14 stm32f10x_spi.o(i.SPI_I2S_GetFlagStatus) + SPI_I2S_SendData 0x0801073b Thumb Code 4 stm32f10x_spi.o(i.SPI_I2S_SendData) + SPI_Init 0x0801073f Thumb Code 56 stm32f10x_spi.o(i.SPI_Init) + Screen_ClearBuf 0x08010779 Thumb Code 14 screen.o(i.Screen_ClearBuf) + Screen_IQ_Transmit 0x08010791 Thumb Code 1902 screen.o(i.Screen_IQ_Transmit) + Screen_IT_Receive 0x080110e5 Thumb Code 40 screen.o(i.Screen_IT_Receive) + Screen_IT_Update 0x08011119 Thumb Code 5314 screen.o(i.Screen_IT_Update) + Screen_Init 0x08012635 Thumb Code 26 screen.o(i.Screen_Init) + Screen_TIM_Moni 0x08012655 Thumb Code 20 screen.o(i.Screen_TIM_Moni) + Send_Record_Blank 0x0801266d Thumb Code 76 screen.o(i.Send_Record_Blank) + Set_Row_Hide 0x08012839 Thumb Code 50 screen.o(i.Set_Row_Hide) + SysTick_Handler 0x080128a9 Thumb Code 2 stm32f10x_it.o(i.SysTick_Handler) + SystemInit 0x080128ad Thumb Code 64 system_stm32f10x.o(i.SystemInit) + TEMP_Cal 0x080128fd Thumb Code 122 ntc.o(i.TEMP_Cal) + TEMP_Cal_CMFA 0x08012981 Thumb Code 122 ntc.o(i.TEMP_Cal_CMFA) + TIM3_IRQHandler 0x08012a05 Thumb Code 246 tim.o(i.TIM3_IRQHandler) + TIM4_PWM_Init 0x08012b35 Thumb Code 144 pwm.o(i.TIM4_PWM_Init) + TIMER_IsOut 0x08012bcd Thumb Code 28 tim.o(i.TIMER_IsOut) + TIMER_Update 0x08012bed Thumb Code 6 tim.o(i.TIMER_Update) + TIM_ARRPreloadConfig 0x08012bf9 Thumb Code 20 stm32f10x_tim.o(i.TIM_ARRPreloadConfig) + TIM_ClearITPendingBit 0x08012c0d Thumb Code 6 stm32f10x_tim.o(i.TIM_ClearITPendingBit) + TIM_Cmd 0x08012c13 Thumb Code 20 stm32f10x_tim.o(i.TIM_Cmd) + TIM_CtrlPWMOutputs 0x08012c27 Thumb Code 22 stm32f10x_tim.o(i.TIM_CtrlPWMOutputs) + TIM_GetITStatus 0x08012c3d Thumb Code 24 stm32f10x_tim.o(i.TIM_GetITStatus) + TIM_ITConfig 0x08012c55 Thumb Code 16 stm32f10x_tim.o(i.TIM_ITConfig) + TIM_OC4Init 0x08012c65 Thumb Code 90 stm32f10x_tim.o(i.TIM_OC4Init) + TIM_OC4PreloadConfig 0x08012cc9 Thumb Code 20 stm32f10x_tim.o(i.TIM_OC4PreloadConfig) + TIM_SetCompare4 0x08012cdd Thumb Code 6 stm32f10x_tim.o(i.TIM_SetCompare4) + TIM_SetCounter 0x08012ce3 Thumb Code 4 stm32f10x_tim.o(i.TIM_SetCounter) + TIM_TimeBaseInit 0x08012ce9 Thumb Code 114 stm32f10x_tim.o(i.TIM_TimeBaseInit) + TSC_Detect 0x08012d85 Thumb Code 82 gpio.o(i.TSC_Detect) + Trigger_CurAlarm 0x08012de9 Thumb Code 132 status.o(i.Trigger_CurAlarm) + Trigger_CurProtect 0x08012e81 Thumb Code 140 status.o(i.Trigger_CurProtect) + Trigger_CurProtectLock 0x08012f1d Thumb Code 2 status.o(i.Trigger_CurProtectLock) + Trigger_OVAlarm 0x08012f21 Thumb Code 138 status.o(i.Trigger_OVAlarm) + Trigger_OVProtect 0x08012fc1 Thumb Code 198 status.o(i.Trigger_OVProtect) + Trigger_UVAlarm 0x080130a1 Thumb Code 138 status.o(i.Trigger_UVAlarm) + Trigger_UVProtect 0x08013141 Thumb Code 192 status.o(i.Trigger_UVProtect) + Trigger_afeTAlarm 0x08013219 Thumb Code 178 status.o(i.Trigger_afeTAlarm) + Trigger_afeTProtect 0x080132d9 Thumb Code 176 status.o(i.Trigger_afeTProtect) + Trigger_amTAlarm 0x08013391 Thumb Code 288 status.o(i.Trigger_amTAlarm) + Trigger_amTProtect 0x080134bd Thumb Code 288 status.o(i.Trigger_amTProtect) + Trigger_mcuTAlarm 0x080135e9 Thumb Code 294 status.o(i.Trigger_mcuTAlarm) + Trigger_mcuTProtect 0x08013725 Thumb Code 292 status.o(i.Trigger_mcuTProtect) + UART1_ClearRecord 0x08013859 Thumb Code 86 rs485_modbus.o(i.UART1_ClearRecord) + UART1_ProtocolSwitch 0x080138bd Thumb Code 138 rs485_modbus.o(i.UART1_ProtocolSwitch) + UART1_ReadRecord 0x08013965 Thumb Code 60 rs485_modbus.o(i.UART1_ReadRecord) + UART3_ClearRecord 0x080139ad Thumb Code 86 rs485_modbus_inverter.o(i.UART3_ClearRecord) + UART3_EraseIAP 0x08013a11 Thumb Code 36 rs485_modbus_inverter.o(i.UART3_EraseIAP) + UART3_ProtocolSwitch 0x08013a41 Thumb Code 160 rs485_modbus_inverter.o(i.UART3_ProtocolSwitch) + UART3_ReadRecord 0x08013af1 Thumb Code 60 rs485_modbus_inverter.o(i.UART3_ReadRecord) + UART4_IRQHandler 0x08013b39 Thumb Code 36 uart.o(i.UART4_IRQHandler) + USART1_IRQHandler 0x08013b65 Thumb Code 36 uart.o(i.USART1_IRQHandler) + USART1_SendMulByte 0x08013b91 Thumb Code 48 uart.o(i.USART1_SendMulByte) + USART2_IRQHandler 0x08013bc5 Thumb Code 36 uart.o(i.USART2_IRQHandler) + USART2_printf 0x08013bf1 Thumb Code 48 screen.o(i.USART2_printf) + USART3_IRQHandler 0x08013c29 Thumb Code 36 uart.o(i.USART3_IRQHandler) + USART3_SendMulByte 0x08013c55 Thumb Code 48 uart.o(i.USART3_SendMulByte) + USART_Cmd 0x08013c89 Thumb Code 20 stm32f10x_usart.o(i.USART_Cmd) + USART_GetFlagStatus 0x08013c9d Thumb Code 14 stm32f10x_usart.o(i.USART_GetFlagStatus) + USART_GetITStatus 0x08013cab Thumb Code 62 stm32f10x_usart.o(i.USART_GetITStatus) + USART_ITConfig 0x08013ce9 Thumb Code 48 stm32f10x_usart.o(i.USART_ITConfig) + USART_Init 0x08013d19 Thumb Code 166 stm32f10x_usart.o(i.USART_Init) + USART_ReceiveData 0x08013dc5 Thumb Code 8 stm32f10x_usart.o(i.USART_ReceiveData) + USART_SendData 0x08013dcd Thumb Code 8 stm32f10x_usart.o(i.USART_SendData) + USB_LP_CAN1_RX0_IRQHandler 0x08013dd5 Thumb Code 74 can.o(i.USB_LP_CAN1_RX0_IRQHandler) + UVOff_TIM_Moni 0x08013e31 Thumb Code 46 global.o(i.UVOff_TIM_Moni) + UsageFault_Handler 0x08013e69 Thumb Code 2 stm32f10x_it.o(i.UsageFault_Handler) + YDN 0x08013e6d Thumb Code 2662 rs485_modbus_inverter.o(i.YDN) + YDN_Protocol_Pylon 0x08014905 Thumb Code 4 protocolswitch_p1.o(i.YDN_Protocol_Pylon) + __ARM_fpclassify 0x08014909 Thumb Code 40 fpclassify.o(i.__ARM_fpclassify) + _is_digit 0x08014931 Thumb Code 14 __printf_wp.o(i._is_digit) + canMem_refresh 0x08014941 Thumb Code 1296 global.o(i.canMem_refresh) + delay_ms 0x08014e61 Thumb Code 70 systick.o(i.delay_ms) + delay_us 0x08014ead Thumb Code 62 systick.o(i.delay_us) + findHexStr 0x08014eeb Thumb Code 46 screen.o(i.findHexStr) + get_random 0x08014f19 Thumb Code 46 global.o(i.get_random) + main 0x08014f4d Thumb Code 720 main.o(i.main) + onlineMem_refresh 0x0801526d Thumb Code 136 global.o(i.onlineMem_refresh) + toASCII 0x08015301 Thumb Code 14 global.o(i.toASCII) + uf_ADC_Init 0x08015311 Thumb Code 160 adc.o(i.uf_ADC_Init) + uf_CAN1_Init 0x080153bd Thumb Code 286 can.o(i.uf_CAN1_Init) + uf_EXTI_Init 0x080154ed Thumb Code 8 gpio.o(i.uf_EXTI_Init) + uf_FLASH_Init 0x080154f5 Thumb Code 56 flash.o(i.uf_FLASH_Init) + uf_GLOBAL_Init 0x08015535 Thumb Code 488 global.o(i.uf_GLOBAL_Init) + uf_GPIO_Init 0x0801574d Thumb Code 430 gpio.o(i.uf_GPIO_Init) + uf_I2C1_Init 0x0801590d Thumb Code 464 i2c.o(i.uf_I2C1_Init) + uf_IWDG_Init 0x08015b09 Thumb Code 38 wdg.o(i.uf_IWDG_Init) + uf_RTC_Init 0x08015b31 Thumb Code 418 rtc.o(i.uf_RTC_Init) + uf_RTC_Update 0x08015ce5 Thumb Code 238 rtc.o(i.uf_RTC_Update) + uf_SPI2_Init 0x08015dd9 Thumb Code 186 spi.o(i.uf_SPI2_Init) + uf_TIM3_Init 0x08015e9d Thumb Code 90 tim.o(i.uf_TIM3_Init) + uf_UART1_Init 0x08015efd Thumb Code 174 uart.o(i.uf_UART1_Init) + uf_UART2_Init 0x08015fb9 Thumb Code 162 uart.o(i.uf_UART2_Init) + uf_UART3_Init 0x08016065 Thumb Code 160 uart.o(i.uf_UART3_Init) + uf_UART4_Init 0x0801610d Thumb Code 160 uart.o(i.uf_UART4_Init) + _get_lc_numeric 0x080161b5 Thumb Code 44 lc_numeric_c.o(locale$$code) + _get_lc_ctype 0x080161e1 Thumb Code 44 lc_ctype_c.o(locale$$code) + __aeabi_dadd 0x0801620d Thumb Code 0 daddsub_clz.o(x$fpl$dadd) + _dadd 0x0801620d Thumb Code 332 daddsub_clz.o(x$fpl$dadd) + __aeabi_ddiv 0x0801635d Thumb Code 0 ddiv.o(x$fpl$ddiv) + _ddiv 0x0801635d Thumb Code 552 ddiv.o(x$fpl$ddiv) + __aeabi_d2iz 0x0801660d Thumb Code 0 dfix.o(x$fpl$dfix) + _dfix 0x0801660d Thumb Code 94 dfix.o(x$fpl$dfix) + __aeabi_d2uiz 0x0801666d Thumb Code 0 dfixu.o(x$fpl$dfixu) + _dfixu 0x0801666d Thumb Code 90 dfixu.o(x$fpl$dfixu) + __aeabi_ui2d 0x080166c7 Thumb Code 0 dflt_clz.o(x$fpl$dfltu) + _dfltu 0x080166c7 Thumb Code 38 dflt_clz.o(x$fpl$dfltu) + __aeabi_dmul 0x080166ed Thumb Code 0 dmul.o(x$fpl$dmul) + _dmul 0x080166ed Thumb Code 332 dmul.o(x$fpl$dmul) + __fpl_dnaninf 0x08016841 Thumb Code 156 dnaninf.o(x$fpl$dnaninf) + __fpl_dretinf 0x080168dd Thumb Code 12 dretinf.o(x$fpl$dretinf) + __aeabi_dsub 0x080168e9 Thumb Code 0 daddsub_clz.o(x$fpl$dsub) + _dsub 0x080168e9 Thumb Code 464 daddsub_clz.o(x$fpl$dsub) + __aeabi_f2d 0x08016abd Thumb Code 0 f2d.o(x$fpl$f2d) + _f2d 0x08016abd Thumb Code 86 f2d.o(x$fpl$f2d) + __aeabi_fadd 0x08016b15 Thumb Code 0 faddsub_clz.o(x$fpl$fadd) + _fadd 0x08016b15 Thumb Code 196 faddsub_clz.o(x$fpl$fadd) + __aeabi_fdiv 0x08016bd9 Thumb Code 0 fdiv.o(x$fpl$fdiv) + _fdiv 0x08016bd9 Thumb Code 384 fdiv.o(x$fpl$fdiv) + __aeabi_f2uiz 0x08016d5d Thumb Code 0 ffixu.o(x$fpl$ffixu) + _ffixu 0x08016d5d Thumb Code 62 ffixu.o(x$fpl$ffixu) + __aeabi_i2f 0x08016d9d Thumb Code 0 fflt_clz.o(x$fpl$fflt) + _fflt 0x08016d9d Thumb Code 48 fflt_clz.o(x$fpl$fflt) + __aeabi_ui2f 0x08016dcd Thumb Code 0 fflt_clz.o(x$fpl$ffltu) + _ffltu 0x08016dcd Thumb Code 38 fflt_clz.o(x$fpl$ffltu) + __aeabi_fmul 0x08016df5 Thumb Code 0 fmul.o(x$fpl$fmul) + _fmul 0x08016df5 Thumb Code 258 fmul.o(x$fpl$fmul) + __fpl_fnaninf 0x08016ef7 Thumb Code 140 fnaninf.o(x$fpl$fnaninf) + __fpl_fretinf 0x08016f83 Thumb Code 10 fretinf.o(x$fpl$fretinf) + __aeabi_fsub 0x08016f8d Thumb Code 0 faddsub_clz.o(x$fpl$fsub) + _fsub 0x08016f8d Thumb Code 234 faddsub_clz.o(x$fpl$fsub) + _printf_fp_dec 0x08017077 Thumb Code 4 printf1.o(x$fpl$printf1) + _printf_fp_hex 0x0801707b Thumb Code 4 printf2.o(x$fpl$printf2) + CRC8Table 0x0801707e Data 256 global.o(.constdata) + __I$use$fp 0x0801707e Number 0 usenofp.o(x$fpl$usenofp) + table_week 0x0801717e Data 12 rtc.o(.constdata) + mon_table 0x0801718a Data 12 rtc.o(.constdata) + CRC16Table 0x08017196 Data 512 rs485_modbus.o(.constdata) + NTC_103AT 0x08017396 Data 362 ntc.o(.constdata) + NTC_103AT_CMFA 0x08017500 Data 332 ntc.o(.constdata) + VP_Time 0x0801764c Data 10 status.o(.constdata) + Region$$Table$$Base 0x08017764 Number 0 anon$$obj.o(Region$$Table) + Region$$Table$$Limit 0x08017784 Number 0 anon$$obj.o(Region$$Table) + __ctype 0x080177ad Data 0 lc_ctype_c.o(locale$$data) + staPack 0x20000000 Data 1 global.o(.data) + chgCurLimit_changeFlg 0x20000001 Data 1 global.o(.data) + dsgCurLimit_changeFlg 0x20000002 Data 1 global.o(.data) + dsgVolLimit_changeFlg 0x20000003 Data 1 global.o(.data) + OnlineNum 0x20000004 Data 1 global.o(.data) + OnlineFirstAddr 0x20000005 Data 1 global.o(.data) + chg_curLimitNum 0x20000006 Data 1 global.o(.data) + dsg_curLimitNum 0x20000007 Data 1 global.o(.data) + chg_cur0Num 0x20000008 Data 1 global.o(.data) + Addr_SetCount 0x20000009 Data 1 global.o(.data) + alarm_occ_old 0x2000000a Data 2 global.o(.data) + alarm_ocd1_old 0x2000000c Data 2 global.o(.data) + alarm_puv_old 0x2000000e Data 2 global.o(.data) + uvoff_Moni_Count 0x20000010 Data 2 global.o(.data) + sleep_Moni_Count 0x20000014 Data 4 global.o(.data) + sleep2_Moni_Count 0x20000018 Data 4 global.o(.data) + fcc_Cali_Moni_Count 0x2000001c Data 4 global.o(.data) + balancing 0x20000020 Data 1 gpio.o(.data) + PCHG_startFlag 0x20000021 Data 1 gpio.o(.data) + PCHG_startCnt 0x20000022 Data 1 gpio.o(.data) + PCHG_Flag 0x20000023 Data 1 gpio.o(.data) + PCHG_Cnt 0x20000024 Data 1 gpio.o(.data) + TSC_detectFlag 0x20000025 Data 1 gpio.o(.data) + ClearArray_Flag 0x20000026 Data 1 gpio.o(.data) + ON_confirm_flg 0x20000027 Data 1 gpio.o(.data) + RST_confirm_flg 0x20000028 Data 1 gpio.o(.data) + OFF_confirm_flg 0x20000029 Data 1 gpio.o(.data) + key_state 0x2000002a Data 1 gpio.o(.data) + power_state 0x2000002b Data 1 gpio.o(.data) + led_toggle_step 0x2000002c Data 1 gpio.o(.data) + power_old 0x2000002d Data 1 gpio.o(.data) + IO1_INH_Count 0x2000002e Data 1 gpio.o(.data) + IO1_INL_Count 0x2000002f Data 1 gpio.o(.data) + balCount 0x20000030 Data 2 gpio.o(.data) + ADDR_Moni_Count 0x20000032 Data 2 gpio.o(.data) + KEY_INH_Count 0x20000034 Data 2 gpio.o(.data) + KEY_INL_Count 0x20000036 Data 2 gpio.o(.data) + TSC_Flag 0x20000038 Data 1 gpio.o(.data) + tmrSys 0x2000003c Data 4 tim.o(.data) + Screen_RevFlg 0x20000040 Data 1 uart.o(.data) + Screen_RevCount 0x20000041 Data 1 uart.o(.data) + MODBUS_RevFlg 0x20000042 Data 1 uart.o(.data) + MODBUS_RevCount 0x20000043 Data 1 uart.o(.data) + MODBUS1_RevFlg 0x20000044 Data 1 uart.o(.data) + MODBUS1_RevCount 0x20000045 Data 1 uart.o(.data) + BLE_RevFlg 0x20000046 Data 1 uart.o(.data) + BLE_RevCount 0x20000047 Data 1 uart.o(.data) + Screen_RevHandlerFlg 0x20000048 Data 1 uart.o(.data) + IAP_Run 0x2000004c Data 1 i2c.o(.data) + DL_Index 0x2000004d Data 1 i2c.o(.data) + DL_Addr 0x20000050 Data 4 i2c.o(.data) + DL_Jump 0x20000054 Data 4 i2c.o(.data) + LSEErrFlag 0x20000058 Data 1 rtc.o(.data) + LSEErrCount 0x20000059 Data 1 rtc.o(.data) + sleep_flag 0x2000005a Data 1 rtc.o(.data) + sleep_enableflag 0x2000005b Data 1 rtc.o(.data) + RTC_UpdateFlag 0x2000005c Data 1 rtc.o(.data) + uvofftime 0x20000060 Data 2 rtc.o(.data) + timecount 0x20000064 Data 4 rtc.o(.data) + oldtimecnt 0x20000068 Data 4 rtc.o(.data) + sleeptimecount 0x2000006c Data 4 rtc.o(.data) + sleeptime 0x20000070 Data 4 rtc.o(.data) + sleep2timecount 0x20000074 Data 4 rtc.o(.data) + sleep2time 0x20000078 Data 4 rtc.o(.data) + uvofftimecount 0x2000007c Data 4 rtc.o(.data) + ocvtimecount 0x20000080 Data 4 rtc.o(.data) + ocvtime 0x20000084 Data 4 rtc.o(.data) + fcc_Calitimecount 0x20000088 Data 4 rtc.o(.data) + fcc_Calitime 0x2000008c Data 4 rtc.o(.data) + oldCur 0x20000090 Data 4 rtc.o(.data) + calendar 0x20000094 Data 7 rtc.o(.data) + calendar_WRITE 0x2000009b Data 7 rtc.o(.data) + calendar_BACKUP 0x200000a2 Data 7 rtc.o(.data) + CAN_SendCount 0x200000aa Data 1 can.o(.data) + CAN_MoniCount 0x200000ac Data 2 can.o(.data) + TemperatureAverage 0x200000b0 Data 2 adc.o(.data) + TemperatureMax 0x200000b2 Data 2 adc.o(.data) + TemperatureMin 0x200000b4 Data 2 adc.o(.data) + TemperatureMaxIndex 0x200000b6 Data 2 adc.o(.data) + TemperatureMinIndex 0x200000b8 Data 2 adc.o(.data) + loadvol 0x200000bc Data 4 adc.o(.data) + curLimit_ctrlFlag 0x200000c0 Data 1 pwm.o(.data) + base_duty 0x200000c4 Data 4 pwm.o(.data) + old_duty 0x200000c8 Data 4 pwm.o(.data) + duty_cycle 0x200000cc Data 4 pwm.o(.data) + bAlarmFlag 0x200000d0 Data 1 afe_sh3673520.o(.data) + bAlarmFlagOld 0x200000d1 Data 1 afe_sh3673520.o(.data) + ucCadcTimeCnt 0x200000d2 Data 1 afe_sh3673520.o(.data) + bDSGING 0x200000d3 Data 1 afe_sh3673520.o(.data) + bCHGING 0x200000d4 Data 1 afe_sh3673520.o(.data) + bSTANDBY 0x200000d5 Data 1 afe_sh3673520.o(.data) + curLimitFlag 0x200000d6 Data 1 afe_sh3673520.o(.data) + curLimitCount 0x200000d7 Data 1 afe_sh3673520.o(.data) + DSGcount 0x200000d8 Data 1 afe_sh3673520.o(.data) + DSGminiFlag 0x200000d9 Data 1 afe_sh3673520.o(.data) + CHGcount 0x200000da Data 1 afe_sh3673520.o(.data) + CHGminiFlag 0x200000db Data 1 afe_sh3673520.o(.data) + ErrDSGcount 0x200000dc Data 1 afe_sh3673520.o(.data) + ErrCHGcount 0x200000dd Data 1 afe_sh3673520.o(.data) + ErrDSGRelaycount 0x200000de Data 1 afe_sh3673520.o(.data) + ErrCHGRelaycount 0x200000df Data 1 afe_sh3673520.o(.data) + nullCurrent_Flag 0x200000e0 Data 1 afe_sh3673520.o(.data) + sc_OccurFlag 0x200000e1 Data 1 afe_sh3673520.o(.data) + tsc_OccurFlag 0x200000e2 Data 1 afe_sh3673520.o(.data) + sc_RepeatFlag 0x200000e3 Data 1 afe_sh3673520.o(.data) + sc_RepeatDelay 0x200000e4 Data 1 afe_sh3673520.o(.data) + sc_RepeatCount 0x200000e5 Data 1 afe_sh3673520.o(.data) + tsc_RepeatFlag 0x200000e6 Data 1 afe_sh3673520.o(.data) + tsc_RepeatDelay 0x200000e7 Data 1 afe_sh3673520.o(.data) + tsc_RepeatCount 0x200000e8 Data 1 afe_sh3673520.o(.data) + fcc4_count 0x200000e9 Data 1 afe_sh3673520.o(.data) + fcc4r_count 0x200000ea Data 1 afe_sh3673520.o(.data) + OCC2_Flag 0x200000eb Data 1 afe_sh3673520.o(.data) + dsgCtrl 0x200000ec Data 1 afe_sh3673520.o(.data) + dsgCtrl_old 0x200000ed Data 1 afe_sh3673520.o(.data) + MOS_Close_Flg 0x200000ee Data 1 afe_sh3673520.o(.data) + sc_close_flag 0x200000ef Data 1 afe_sh3673520.o(.data) + curLimitReleaseCount 0x200000f0 Data 2 afe_sh3673520.o(.data) + curLimitCloseCount 0x200000f2 Data 2 afe_sh3673520.o(.data) + CTRL_Order 0x200000f4 Data 2 afe_sh3673520.o(.data) + OCC2MoniCount 0x200000f6 Data 2 afe_sh3673520.o(.data) + tsc_relaycount 0x200000f8 Data 2 afe_sh3673520.o(.data) + cellVoltageMax 0x200000fa Data 2 afe_sh3673520.o(.data) + cellVoltageMin 0x200000fc Data 2 afe_sh3673520.o(.data) + afeFlg 0x200000fe Data 8 afe_sh3673520.o(.data) + siCurBuf 0x20000106 Data 8 afe_sh3673520.o(.data) + modbusBufIndex 0x2000010e Data 1 rs485_modbus.o(.data) + modbusF03RxFlg 0x2000010f Data 1 rs485_modbus.o(.data) + modbusF10RxFlg 0x20000110 Data 1 rs485_modbus.o(.data) + modbusFaaRxFlg 0x20000111 Data 1 rs485_modbus.o(.data) + modbusFbbRxFlg 0x20000112 Data 1 rs485_modbus.o(.data) + modbusFddRxFlg 0x20000113 Data 1 rs485_modbus.o(.data) + modbusFeeRxFlg 0x20000114 Data 1 rs485_modbus.o(.data) + modbusFf1RxFlg 0x20000115 Data 1 rs485_modbus.o(.data) + modbusCurF03RxFlag 0x20000116 Data 1 rs485_modbus.o(.data) + modbusCurF10RxFlag 0x20000117 Data 1 rs485_modbus.o(.data) + modbusCurStatus 0x20000118 Data 1 rs485_modbus.o(.data) + modbusCurDev 0x20000119 Data 1 rs485_modbus.o(.data) + modbusCurSta 0x2000011a Data 1 rs485_modbus.o(.data) + modbusCurLastAddr 0x2000011b Data 1 rs485_modbus.o(.data) + ReAskFlag 0x2000011c Data 1 rs485_modbus.o(.data) + sleepOFFcount 0x2000011d Data 1 rs485_modbus.o(.data) + sdwa_WrAddr 0x2000011e Data 1 rs485_modbus.o(.data) + sdwa_WrAddr_Flg 0x2000011f Data 1 rs485_modbus.o(.data) + sdwa_WrAddr_Failcount 0x20000120 Data 1 rs485_modbus.o(.data) + assignAddr_State 0x20000121 Data 1 rs485_modbus.o(.data) + assignAddr_Step 0x20000122 Data 1 rs485_modbus.o(.data) + assignAddr_Failcount 0x20000123 Data 1 rs485_modbus.o(.data) + assignAddr_485num 0x20000124 Data 1 rs485_modbus.o(.data) + assignAddr_WrIndex_Flg 0x20000125 Data 1 rs485_modbus.o(.data) + assign_ready_count1 0x20000126 Data 1 rs485_modbus.o(.data) + assign_ready_count2 0x20000127 Data 1 rs485_modbus.o(.data) + assign_ready_count3 0x20000128 Data 1 rs485_modbus.o(.data) + assign_ready_count4 0x20000129 Data 1 rs485_modbus.o(.data) + assign_ready_count5 0x2000012a Data 1 rs485_modbus.o(.data) + AnswerFlag1 0x2000012b Data 1 rs485_modbus.o(.data) + AnswerFlag2 0x2000012c Data 1 rs485_modbus.o(.data) + PollStop_flag 0x2000012d Data 1 rs485_modbus.o(.data) + PollStop_count 0x2000012e Data 1 rs485_modbus.o(.data) + modbusMoniCount 0x20000130 Data 2 rs485_modbus.o(.data) + assignAddr_random 0x20000132 Data 2 rs485_modbus.o(.data) + chg_forbidFlg 0x20000134 Data 1 rs485_modbus.o(.data) + dsg_forbidFlg 0x20000135 Data 1 rs485_modbus.o(.data) + chg_forceFlg 0x20000136 Data 1 rs485_modbus.o(.data) + RequestFlag 0x20000138 Data 2 rs485_modbus.o(.data) + chg_curlimitFlg 0x2000013a Data 1 rs485_modbus.o(.data) + assignAddr_relay 0x2000013b Data 1 rs485_modbus.o(.data) + protocolNum 0x2000013c Data 1 rs485_modbus_inverter.o(.data) + modbus1BufIndex 0x2000013e Data 1 rs485_modbus_inverter.o(.data) + modbus1VoltronicRxFlg 0x2000013f Data 1 rs485_modbus_inverter.o(.data) + modbus1F03RxFlg 0x20000140 Data 1 rs485_modbus_inverter.o(.data) + modbus1F10RxFlg 0x20000141 Data 1 rs485_modbus_inverter.o(.data) + modbus1FaaRxFlg 0x20000142 Data 1 rs485_modbus_inverter.o(.data) + modbus1FbbRxFlg 0x20000143 Data 1 rs485_modbus_inverter.o(.data) + modbus1FddRxFlg 0x20000144 Data 1 rs485_modbus_inverter.o(.data) + modbus1FeeRxFlg 0x20000145 Data 1 rs485_modbus_inverter.o(.data) + modbus1Ff1RxFlg 0x20000146 Data 1 rs485_modbus_inverter.o(.data) + cmdRxIapFlg 0x20000147 Data 1 rs485_modbus_inverter.o(.data) + protocolSwitchFail 0x20000148 Data 1 rs485_modbus_inverter.o(.data) + ydn23RxFlg 0x20000149 Data 1 rs485_modbus_inverter.o(.data) + ConfigData_Index 0x2000014a Data 1 rs485_modbus_inverter.o(.data) + Online_Flag 0x2000014b Data 1 rs485_modbus_inverter.o(.data) + cumuliCapClear_flag 0x2000014c Data 1 rs485_modbus_inverter.o(.data) + modbus1MoniCount 0x2000014e Data 2 rs485_modbus_inverter.o(.data) + INFOlen 0x20000150 Data 2 rs485_modbus_inverter.o(.data) + protocolIdx 0x20000152 Data 40 rs485_modbus_inverter.o(.data) + protocolStrings 0x2000017a Data 384 rs485_modbus_inverter.o(.data) + ucTempeMiddle 0x200002fa Data 1 ntc.o(.data) + read_index 0x200002fe Data 1 screen.o(.data) + clearFlag 0x200002ff Data 1 screen.o(.data) + clearFlag_timer 0x20000300 Data 1 screen.o(.data) + flashUpdateFlag 0x20000301 Data 1 screen.o(.data) + SCR_setADDRFlag 0x20000302 Data 1 screen.o(.data) + SCR_HistoryFlag 0x20000303 Data 1 screen.o(.data) + SCR_ParallelFlag 0x20000304 Data 1 screen.o(.data) + SCR_PACKFlag 0x20000305 Data 1 screen.o(.data) + force_discharge_flag 0x20000306 Data 1 screen.o(.data) + factory_reset_flag 0x20000307 Data 1 screen.o(.data) + protocol 0x20000308 Data 1 screen.o(.data) + scr_RdData_Index 0x20000309 Data 1 screen.o(.data) + bAlarmFlagOld_slave 0x2000030a Data 1 screen.o(.data) + SCR_Rx_BufIndex 0x2000030c Data 2 screen.o(.data) + SCR_Moni_Count 0x2000030e Data 2 screen.o(.data) + SCR_Sleep 0x20000310 Data 4 screen.o(.data) + SCR_setADDR 0x20000314 Data 7 screen.o(.data) + SCR_ForceDischarge 0x2000031b Data 7 screen.o(.data) + SCR_FactoryReset 0x20000322 Data 7 screen.o(.data) + SCR_Hide_History 0x20000329 Data 7 screen.o(.data) + SCR_up_History 0x20000330 Data 7 screen.o(.data) + SCR_down_History 0x20000337 Data 7 screen.o(.data) + SCR_clean_History 0x2000033e Data 7 screen.o(.data) + SCR_Parallel 0x20000345 Data 7 screen.o(.data) + SCR_Allpack 0x2000034c Data 7 screen.o(.data) + SCR_Allcell 0x20000353 Data 7 screen.o(.data) + SCR_PACK1 0x2000035a Data 7 screen.o(.data) + SCR_PACK2 0x20000361 Data 7 screen.o(.data) + SCR_PACK3 0x20000368 Data 7 screen.o(.data) + SCR_PACK4 0x2000036f Data 7 screen.o(.data) + SCR_PACK5 0x20000376 Data 7 screen.o(.data) + SCR_PACK6 0x2000037d Data 7 screen.o(.data) + SCR_PACK7 0x20000384 Data 7 screen.o(.data) + SCR_PACK8 0x2000038b Data 7 screen.o(.data) + SCR_PACK9 0x20000392 Data 7 screen.o(.data) + SCR_PACK10 0x20000399 Data 7 screen.o(.data) + SCR_PACK11 0x200003a0 Data 7 screen.o(.data) + SCR_PACK12 0x200003a7 Data 7 screen.o(.data) + SCR_PACK13 0x200003ae Data 7 screen.o(.data) + SCR_PACK14 0x200003b5 Data 7 screen.o(.data) + SCR_PACK15 0x200003bc Data 7 screen.o(.data) + SCR_PACK16 0x200003c3 Data 7 screen.o(.data) + SCR_setProtocol_SolArk 0x200003ca Data 7 screen.o(.data) + SCR_setProtocol_GoodWe 0x200003d1 Data 7 screen.o(.data) + SCR_setProtocol_Megarevo 0x200003d8 Data 7 screen.o(.data) + SCR_setProtocol_Pylon 0x200003df Data 7 screen.o(.data) + SCR_setProtocol_Deye 0x200003e6 Data 7 screen.o(.data) + SCR_setProtocol_MUST 0x200003ed Data 7 screen.o(.data) + SCR_setProtocol_Solis 0x200003f4 Data 7 screen.o(.data) + SCR_setProtocol_Growatt 0x200003fb Data 7 screen.o(.data) + SCR_setProtocol_Aiswei 0x20000402 Data 7 screen.o(.data) + SCR_setProtocol_Afore 0x20000409 Data 7 screen.o(.data) + SCR_setProtocol_Victron 0x20000410 Data 7 screen.o(.data) + SCR_setProtocol_Sorotec 0x20000417 Data 7 screen.o(.data) + SCR_setProtocol_SMA 0x2000041e Data 7 screen.o(.data) + SCR_setProtocol_Sunways 0x20000425 Data 7 screen.o(.data) + SCR_setProtocol_Luxpower 0x2000042c Data 7 screen.o(.data) + SCR_setProtocol_Schneider 0x20000433 Data 7 screen.o(.data) + SCR_setProtocol_AlpSolarr 0x2000043a Data 7 screen.o(.data) + SCR_setProtocol_SRNE 0x20000441 Data 7 screen.o(.data) + SCR_setProtocol_Voltronic 0x20000448 Data 7 screen.o(.data) + SCR_setProtocol_COSUPER 0x2000044f Data 7 screen.o(.data) + SCR_setProtocol_SMK 0x20000456 Data 7 screen.o(.data) + SCR_setProtocol_SAKO 0x2000045d Data 7 screen.o(.data) + SCR_setProtocol_SNADI 0x20000464 Data 7 screen.o(.data) + SCR_setProtocol_invt 0x2000046b Data 7 screen.o(.data) + SCR_setSCVol_0 0x20000472 Data 7 screen.o(.data) + SCR_setSCVol_1 0x20000479 Data 7 screen.o(.data) + SCR_setSCVol_2 0x20000480 Data 7 screen.o(.data) + SCR_setSCVol_3 0x20000487 Data 7 screen.o(.data) + SCR_setSCVol_4 0x2000048e Data 7 screen.o(.data) + SCR_setSCVol_5 0x20000495 Data 7 screen.o(.data) + SCR_setSCVol_6 0x2000049c Data 7 screen.o(.data) + SCR_setSCVol_7 0x200004a3 Data 7 screen.o(.data) + SCR_setSCVol_8 0x200004aa Data 7 screen.o(.data) + SCR_setSCVol_9 0x200004b1 Data 7 screen.o(.data) + SCR_setSCVol_10 0x200004b8 Data 7 screen.o(.data) + SCR_setSCVol_11 0x200004bf Data 7 screen.o(.data) + SCR_setSCTim_0 0x200004c6 Data 7 screen.o(.data) + SCR_setSCTim_1 0x200004cd Data 7 screen.o(.data) + SCR_setSCTim_2 0x200004d4 Data 7 screen.o(.data) + SCR_setSCTim_3 0x200004db Data 7 screen.o(.data) + SCR_setSCTim_4 0x200004e2 Data 7 screen.o(.data) + SCR_setSCTim_5 0x200004e9 Data 7 screen.o(.data) + SCR_setSCTim_6 0x200004f0 Data 7 screen.o(.data) + SCR_setSCTim_7 0x200004f7 Data 7 screen.o(.data) + SCR_setSCTim_8 0x200004fe Data 7 screen.o(.data) + SCR_setSCTim_9 0x20000505 Data 7 screen.o(.data) + SCR_setSCTim_10 0x2000050c Data 7 screen.o(.data) + SCR_setSCTim_11 0x20000513 Data 7 screen.o(.data) + scr_RdRecord_Flg 0x2000051a Data 1 screen.o(.data) + scr_WrZero_Flg 0x2000051b Data 1 screen.o(.data) + scr_WrGain_Flg 0x2000051c Data 1 screen.o(.data) + oldsoc 0x20000520 Data 1 gasgauge.o(.data) + Cali_Soc_Flag 0x20000521 Data 1 gasgauge.o(.data) + fcc_CaliStartFlag 0x20000522 Data 1 gasgauge.o(.data) + fcc_fullFlag 0x20000523 Data 1 gasgauge.o(.data) + ncc_Ah 0x20000524 Data 2 gasgauge.o(.data) + fcc_Ah 0x20000526 Data 2 gasgauge.o(.data) + rcc_Ah 0x20000528 Data 2 gasgauge.o(.data) + oldrcc_Ah 0x2000052a Data 2 gasgauge.o(.data) + cumuliCapacity 0x2000052c Data 2 gasgauge.o(.data) + CaliSocMoniCount 0x2000052e Data 2 gasgauge.o(.data) + oldcyc 0x20000530 Data 2 gasgauge.o(.data) + ClearEE 0x20000532 Data 4 gasgauge.o(.data) + packcheck_OV 0x20000538 Data 4 gasgauge.o(.data) + packcheck_UV 0x2000053c Data 4 gasgauge.o(.data) + RdFCC 0x20000540 Data 4 gasgauge.o(.data) + fcc 0x20000544 Data 4 gasgauge.o(.data) + tmpRdFCC 0x20000548 Data 8 gasgauge.o(.data) + tmpWrFCC 0x20000550 Data 8 gasgauge.o(.data) + OCV_soc 0x20000558 Data 1 ocv.o(.data) + OCV_status 0x20000559 Data 1 ocv.o(.data) + OCV_Wait_flag 0x2000055a Data 1 ocv.o(.data) + OCV_CaliSOC_flag 0x2000055b Data 1 ocv.o(.data) + OCV_WrTime_count 0x2000055c Data 2 ocv.o(.data) + cellov_alarmcount 0x2000055e Data 1 status.o(.data) + celluv_alarmcount 0x2000055f Data 1 status.o(.data) + packov_alarmcount 0x20000560 Data 1 status.o(.data) + packuv_alarmcount 0x20000561 Data 1 status.o(.data) + cellovr_alarmcount 0x20000562 Data 1 status.o(.data) + celluvr_alarmcount 0x20000563 Data 1 status.o(.data) + packovr_alarmcount 0x20000564 Data 1 status.o(.data) + packuvr_alarmcount 0x20000565 Data 1 status.o(.data) + cellov_count 0x20000566 Data 1 status.o(.data) + celluv_count 0x20000567 Data 1 status.o(.data) + packov_count 0x20000568 Data 1 status.o(.data) + packuv_count 0x20000569 Data 1 status.o(.data) + cellovr_count 0x2000056a Data 1 status.o(.data) + celluvr_count 0x2000056b Data 1 status.o(.data) + packovr_count 0x2000056c Data 1 status.o(.data) + packuvr_count 0x2000056d Data 1 status.o(.data) + cellovr_alarmcount2 0x2000056e Data 1 status.o(.data) + celluvr_alarmcount2 0x2000056f Data 1 status.o(.data) + packovr_alarmcount2 0x20000570 Data 1 status.o(.data) + packuvr_alarmcount2 0x20000571 Data 1 status.o(.data) + cellovr_alarmcount3 0x20000572 Data 1 status.o(.data) + packovr_alarmcount3 0x20000573 Data 1 status.o(.data) + cellovr_count2 0x20000574 Data 1 status.o(.data) + celluvr_count2 0x20000575 Data 1 status.o(.data) + packovr_count2 0x20000576 Data 1 status.o(.data) + packuvr_count2 0x20000577 Data 1 status.o(.data) + cellovr_count3 0x20000578 Data 1 status.o(.data) + packovr_count3 0x20000579 Data 1 status.o(.data) + cellovr_alarmflag 0x2000057a Data 1 status.o(.data) + packovr_alarmflag 0x2000057b Data 1 status.o(.data) + celluvr_alarmflag 0x2000057c Data 1 status.o(.data) + packuvr_alarmflag 0x2000057d Data 1 status.o(.data) + cellovr_flag 0x2000057e Data 1 status.o(.data) + packovr_flag 0x2000057f Data 1 status.o(.data) + celluvr_flag 0x20000580 Data 1 status.o(.data) + packuvr_flag 0x20000581 Data 1 status.o(.data) + occ_alarmcount 0x20000582 Data 1 status.o(.data) + ocd1_alarmcount 0x20000583 Data 1 status.o(.data) + occr_alarmcount 0x20000584 Data 1 status.o(.data) + occr_alarmcount2 0x20000585 Data 1 status.o(.data) + ocd1r_alarmcount 0x20000586 Data 1 status.o(.data) + ocd1r_alarmcount2 0x20000587 Data 1 status.o(.data) + scr_count 0x20000588 Data 1 status.o(.data) + occ_count 0x20000589 Data 1 status.o(.data) + ocd_count 0x2000058a Data 1 status.o(.data) + ocr_count 0x2000058b Data 1 status.o(.data) + mcuotc_alarmcount 0x2000058c Data 1 status.o(.data) + mcuutc_alarmcount 0x2000058d Data 1 status.o(.data) + mcuotd_alarmcount 0x2000058e Data 1 status.o(.data) + mcuutd_alarmcount 0x2000058f Data 1 status.o(.data) + mcuotcr_alarmcount 0x20000590 Data 1 status.o(.data) + mcuutcr_alarmcount 0x20000591 Data 1 status.o(.data) + mcuotdr_alarmcount 0x20000592 Data 1 status.o(.data) + mcuutdr_alarmcount 0x20000593 Data 1 status.o(.data) + dsg_htp_count 0x20000594 Data 1 status.o(.data) + dsg_ltp_count 0x20000595 Data 1 status.o(.data) + chg_htp_count 0x20000596 Data 1 status.o(.data) + chg_ltp_count 0x20000597 Data 1 status.o(.data) + dsg_htpr_count 0x20000598 Data 1 status.o(.data) + dsg_ltpr_count 0x20000599 Data 1 status.o(.data) + chg_htpr_count 0x2000059a Data 1 status.o(.data) + chg_ltpr_count 0x2000059b Data 1 status.o(.data) + am_otc_alarmcount 0x2000059c Data 1 status.o(.data) + am_utc_alarmcount 0x2000059d Data 1 status.o(.data) + am_otd_alarmcount 0x2000059e Data 1 status.o(.data) + am_utd_alarmcount 0x2000059f Data 1 status.o(.data) + am_otcr_alarmcount 0x200005a0 Data 1 status.o(.data) + am_utcr_alarmcount 0x200005a1 Data 1 status.o(.data) + am_otdr_alarmcount 0x200005a2 Data 1 status.o(.data) + am_utdr_alarmcount 0x200005a3 Data 1 status.o(.data) + am_otc_count 0x200005a4 Data 1 status.o(.data) + am_otcr_count 0x200005a5 Data 1 status.o(.data) + am_otd_count 0x200005a6 Data 1 status.o(.data) + am_otdr_count 0x200005a7 Data 1 status.o(.data) + am_utc_count 0x200005a8 Data 1 status.o(.data) + am_utcr_count 0x200005a9 Data 1 status.o(.data) + am_utd_count 0x200005aa Data 1 status.o(.data) + am_utdr_count 0x200005ab Data 1 status.o(.data) + afeotc_alarmcount 0x200005ac Data 1 status.o(.data) + afeotd_alarmcount 0x200005ad Data 1 status.o(.data) + afeotcr_alarmcount 0x200005ae Data 1 status.o(.data) + afeotdr_alarmcount 0x200005af Data 1 status.o(.data) + afeotc_count 0x200005b0 Data 1 status.o(.data) + afeotd_count 0x200005b1 Data 1 status.o(.data) + afeotcr_count 0x200005b2 Data 1 status.o(.data) + afeotdr_count 0x200005b3 Data 1 status.o(.data) + cell_OV 0x200005b4 Data 2 status.o(.data) + cell_UV 0x200005b6 Data 2 status.o(.data) + cell_OVT 0x200005b8 Data 2 status.o(.data) + cell_UVT 0x200005ba Data 2 status.o(.data) + cell_OVR 0x200005bc Data 2 status.o(.data) + cell_UVR 0x200005be Data 2 status.o(.data) + putSrvc_reply_flg 0x200005c0 Data 1 mbo26a.o(.data) + setPara_reply_flg 0x200005c1 Data 1 mbo26a.o(.data) + setPara_reply_num 0x200005c2 Data 1 mbo26a.o(.data) + getPara_reply_flg 0x200005c3 Data 1 mbo26a.o(.data) + getPara_reply_num 0x200005c4 Data 1 mbo26a.o(.data) + protocol_reply_flg 0x200005c5 Data 1 mbo26a.o(.data) + protocol_reply_index 0x200005c6 Data 1 mbo26a.o(.data) + BLE_SendFlag 0x200005c7 Data 1 mbo26a.o(.data) + BLE_SendFlag_old 0x200005c8 Data 1 mbo26a.o(.data) + BLE_READYflag 0x200005c9 Data 1 mbo26a.o(.data) + BLE_READYcount 0x200005ca Data 1 mbo26a.o(.data) + BLE_Onflag 0x200005cb Data 1 mbo26a.o(.data) + BLE_status 0x200005cc Data 1 mbo26a.o(.data) + BLE_step 0x200005cd Data 1 mbo26a.o(.data) + BLE_Check_Flag 0x200005ce Data 1 mbo26a.o(.data) + BLE_RST_Flag 0x200005cf Data 1 mbo26a.o(.data) + BLE_RST_count 0x200005d0 Data 1 mbo26a.o(.data) + BLE_Rx_BufIndex 0x200005d2 Data 2 mbo26a.o(.data) + BLE_Moni_Count 0x200005d4 Data 2 mbo26a.o(.data) + BLE_SendWarning_Cur 0x200005d6 Data 2 mbo26a.o(.data) + putSrvc_reply_namestr 0x200005d8 Data 4 mbo26a.o(.data) + putSrvc_reply_str 0x200005dc Data 4 mbo26a.o(.data) + BLE_ChargeStatus_str 0x200005e0 Data 4 mbo26a.o(.data) + BLE_DischargeStatus_str 0x200005e4 Data 4 mbo26a.o(.data) + BLE_PreChargeStatus_str 0x200005e8 Data 4 mbo26a.o(.data) + BLE_ChgMosStatus_str 0x200005ec Data 4 mbo26a.o(.data) + BLE_DsgMosStatus_str 0x200005f0 Data 4 mbo26a.o(.data) + BLE_PchgMosStatus_str 0x200005f4 Data 4 mbo26a.o(.data) + BLE_ChgLimitStatus_str 0x200005f8 Data 4 mbo26a.o(.data) + BLE_BalanceStatus_str 0x200005fc Data 4 mbo26a.o(.data) + BLE_SendWarning_Vol 0x20000600 Data 4 mbo26a.o(.data) + BLE_SendProtect_Cur 0x20000604 Data 5 mbo26a.o(.data) + HardwareVersion 0x20000609 Data 6 mbo26a.o(.data) + ScreenVersion 0x2000060f Data 6 mbo26a.o(.data) + BLE_SendProtect_Vol 0x20000615 Data 6 mbo26a.o(.data) + Status 0x2000061c Data 8 mbo26a.o(.data) + Deye_dsg_forbidFlg 0x20000638 Data 1 protocolswitch_p1.o(.data) + onlineMem 0x2000063c Data 50 global.o(.bss) + VersionMem 0x2000066e Data 224 global.o(.bss) + paraMem 0x2000074e Data 192 global.o(.bss) + bmsMem 0x20000810 Data 228 global.o(.bss) + bmsMem_slave 0x200008f4 Data 228 global.o(.bss) + VoltronicMem 0x200009d8 Data 240 global.o(.bss) + GrowattMem 0x20000ac8 Data 290 global.o(.bss) + tmrTemp 0x20000bec Data 80 tim.o(.bss) + TxMessage 0x20000c3c Data 400 can.o(.bss) + RxMessage 0x20000dcc Data 20 can.o(.bss) + TxMailBox 0x20000de0 Data 20 can.o(.bss) + canMem 0x20000df4 Data 1144 can.o(.bss) + cali 0x2000126c Data 24 afe_sh3673520.o(.bss) + afeRam 0x20001284 Data 90 afe_sh3673520.o(.bss) + cellVol 0x200012de Data 40 afe_sh3673520.o(.bss) + modbusBuf 0x20001306 Data 220 rs485_modbus.o(.bss) + modbus1Buf 0x200013e2 Data 220 rs485_modbus_inverter.o(.bss) + SCR_Rx_Buf 0x200014be Data 128 screen.o(.bss) + SCR_Tx_Buf 0x2000153e Data 128 screen.o(.bss) + recordBuf 0x200015be Data 64 screen.o(.bss) + sendRecord 0x200015fe Data 64 screen.o(.bss) + soe 0x20001640 Data 36 soe.o(.bss) + rdd 0x20001664 Data 64 soe.o(.bss) + ocv_data 0x200016a4 Data 90 ocv.o(.bss) + ocv_Media_dp 0x200016fe Data 30 ocv.o(.bss) + BMS_SN 0x2000171c Data 10 mbo26a.o(.bss) + PACK_SN 0x20001726 Data 16 mbo26a.o(.bss) + FirmwareVersion 0x20001736 Data 11 mbo26a.o(.bss) + params_str 0x20001741 Data 600 mbo26a.o(.bss) + setPara_reply_name 0x2000199c Data 136 mbo26a.o(.bss) + setPara_reply_temp 0x20001a24 Data 68 mbo26a.o(.bss) + getPara_reply_name 0x20001a68 Data 136 mbo26a.o(.bss) + getPara_reply_temp 0x20001af0 Data 68 mbo26a.o(.bss) + BLE_Rx_Buf 0x20001b34 Data 256 mbo26a.o(.bss) + BLE_Tx_Buf 0x20001c34 Data 256 mbo26a.o(.bss) + BLE_SendStatus 0x20001d34 Data 9 mbo26a.o(.bss) + BLE_SendProtect_Temp 0x20001d3d Data 12 mbo26a.o(.bss) + BLE_SendWarning_Temp 0x20001d49 Data 12 mbo26a.o(.bss) + __libspace_start 0x20001d58 Data 96 libspace.o(.bss) + __temporary_stack_top$libspace 0x20001db8 Data 0 libspace.o(.bss) + + + +============================================================================== + +Memory Map of the image + + Image Entry point : 0x08000131 + + Load Region LR_IROM1 (Base: 0x08000000, Size: 0x00017eec, Max: 0x00040000, ABSOLUTE, COMPRESSED[0x00017a8c]) + + Execution Region ER_IROM1 (Exec base: 0x08000000, Load base: 0x08000000, Size: 0x000178b0, Max: 0x00040000, ABSOLUTE) + + Exec Addr Load Addr Size Type Attr Idx E Section Name Object + + 0x08000000 0x08000000 0x00000130 Data RO 19 RESET startup_stm32f10x_hd.o + 0x08000130 0x08000130 0x00000008 Code RO 5490 * !!!main c_w.l(__main.o) + 0x08000138 0x08000138 0x00000034 Code RO 5906 !!!scatter c_w.l(__scatter.o) + 0x0800016c 0x0800016c 0x0000005a Code RO 5904 !!dczerorl2 c_w.l(__dczerorl2.o) + 0x080001c6 0x080001c6 0x00000002 PAD + 0x080001c8 0x080001c8 0x0000001c Code RO 5908 !!handler_zi c_w.l(__scatter_zi.o) + 0x080001e4 0x080001e4 0x00000000 Code RO 5461 .ARM.Collect$$_printf_percent$$00000000 c_w.l(_printf_percent.o) + 0x080001e4 0x080001e4 0x00000006 Code RO 5601 .ARM.Collect$$_printf_percent$$00000001 c_w.l(_printf_n.o) + 0x080001ea 0x080001ea 0x00000006 Code RO 5602 .ARM.Collect$$_printf_percent$$00000002 c_w.l(_printf_p.o) + 0x080001f0 0x080001f0 0x00000006 Code RO 5605 .ARM.Collect$$_printf_percent$$00000003 c_w.l(_printf_f.o) + 0x080001f6 0x080001f6 0x00000006 Code RO 5606 .ARM.Collect$$_printf_percent$$00000004 c_w.l(_printf_e.o) + 0x080001fc 0x080001fc 0x00000006 Code RO 5607 .ARM.Collect$$_printf_percent$$00000005 c_w.l(_printf_g.o) + 0x08000202 0x08000202 0x00000006 Code RO 5608 .ARM.Collect$$_printf_percent$$00000006 c_w.l(_printf_a.o) + 0x08000208 0x08000208 0x0000000a Code RO 5613 .ARM.Collect$$_printf_percent$$00000007 c_w.l(_printf_ll.o) + 0x08000212 0x08000212 0x00000006 Code RO 5604 .ARM.Collect$$_printf_percent$$00000008 c_w.l(_printf_i.o) + 0x08000218 0x08000218 0x00000006 Code RO 5459 .ARM.Collect$$_printf_percent$$00000009 c_w.l(_printf_d.o) + 0x0800021e 0x0800021e 0x00000006 Code RO 5460 .ARM.Collect$$_printf_percent$$0000000A c_w.l(_printf_u.o) + 0x08000224 0x08000224 0x00000006 Code RO 5603 .ARM.Collect$$_printf_percent$$0000000B c_w.l(_printf_o.o) + 0x0800022a 0x0800022a 0x00000006 Code RO 5458 .ARM.Collect$$_printf_percent$$0000000C c_w.l(_printf_x.o) + 0x08000230 0x08000230 0x00000006 Code RO 5610 .ARM.Collect$$_printf_percent$$0000000D c_w.l(_printf_lli.o) + 0x08000236 0x08000236 0x00000006 Code RO 5611 .ARM.Collect$$_printf_percent$$0000000E c_w.l(_printf_lld.o) + 0x0800023c 0x0800023c 0x00000006 Code RO 5612 .ARM.Collect$$_printf_percent$$0000000F c_w.l(_printf_llu.o) + 0x08000242 0x08000242 0x00000006 Code RO 5617 .ARM.Collect$$_printf_percent$$00000010 c_w.l(_printf_llo.o) + 0x08000248 0x08000248 0x00000006 Code RO 5618 .ARM.Collect$$_printf_percent$$00000011 c_w.l(_printf_llx.o) + 0x0800024e 0x0800024e 0x0000000a Code RO 5614 .ARM.Collect$$_printf_percent$$00000012 c_w.l(_printf_l.o) + 0x08000258 0x08000258 0x00000006 Code RO 5457 .ARM.Collect$$_printf_percent$$00000013 c_w.l(_printf_c.o) + 0x0800025e 0x0800025e 0x00000006 Code RO 5600 .ARM.Collect$$_printf_percent$$00000014 c_w.l(_printf_s.o) + 0x08000264 0x08000264 0x00000006 Code RO 5615 .ARM.Collect$$_printf_percent$$00000015 c_w.l(_printf_lc.o) + 0x0800026a 0x0800026a 0x00000006 Code RO 5616 .ARM.Collect$$_printf_percent$$00000016 c_w.l(_printf_ls.o) + 0x08000270 0x08000270 0x00000004 Code RO 5609 .ARM.Collect$$_printf_percent$$00000017 c_w.l(_printf_percent_end.o) + 0x08000274 0x08000274 0x00000002 Code RO 5768 .ARM.Collect$$libinit$$00000000 c_w.l(libinit.o) + 0x08000276 0x08000276 0x00000000 Code RO 5781 .ARM.Collect$$libinit$$00000002 c_w.l(libinit2.o) + 0x08000276 0x08000276 0x00000000 Code RO 5783 .ARM.Collect$$libinit$$00000004 c_w.l(libinit2.o) + 0x08000276 0x08000276 0x00000000 Code RO 5786 .ARM.Collect$$libinit$$0000000A c_w.l(libinit2.o) + 0x08000276 0x08000276 0x00000000 Code RO 5788 .ARM.Collect$$libinit$$0000000C c_w.l(libinit2.o) + 0x08000276 0x08000276 0x00000000 Code RO 5790 .ARM.Collect$$libinit$$0000000E c_w.l(libinit2.o) + 0x08000276 0x08000276 0x00000006 Code RO 5791 .ARM.Collect$$libinit$$0000000F c_w.l(libinit2.o) + 0x0800027c 0x0800027c 0x00000000 Code RO 5793 .ARM.Collect$$libinit$$00000011 c_w.l(libinit2.o) + 0x0800027c 0x0800027c 0x0000000c Code RO 5794 .ARM.Collect$$libinit$$00000012 c_w.l(libinit2.o) + 0x08000288 0x08000288 0x00000000 Code RO 5795 .ARM.Collect$$libinit$$00000013 c_w.l(libinit2.o) + 0x08000288 0x08000288 0x00000000 Code RO 5797 .ARM.Collect$$libinit$$00000015 c_w.l(libinit2.o) + 0x08000288 0x08000288 0x0000000a Code RO 5798 .ARM.Collect$$libinit$$00000016 c_w.l(libinit2.o) + 0x08000292 0x08000292 0x00000000 Code RO 5799 .ARM.Collect$$libinit$$00000017 c_w.l(libinit2.o) + 0x08000292 0x08000292 0x00000000 Code RO 5801 .ARM.Collect$$libinit$$00000019 c_w.l(libinit2.o) + 0x08000292 0x08000292 0x00000000 Code RO 5803 .ARM.Collect$$libinit$$0000001B c_w.l(libinit2.o) + 0x08000292 0x08000292 0x00000000 Code RO 5805 .ARM.Collect$$libinit$$0000001D c_w.l(libinit2.o) + 0x08000292 0x08000292 0x00000000 Code RO 5807 .ARM.Collect$$libinit$$0000001F c_w.l(libinit2.o) + 0x08000292 0x08000292 0x00000000 Code RO 5809 .ARM.Collect$$libinit$$00000021 c_w.l(libinit2.o) + 0x08000292 0x08000292 0x00000000 Code RO 5811 .ARM.Collect$$libinit$$00000023 c_w.l(libinit2.o) + 0x08000292 0x08000292 0x00000000 Code RO 5813 .ARM.Collect$$libinit$$00000025 c_w.l(libinit2.o) + 0x08000292 0x08000292 0x00000000 Code RO 5817 .ARM.Collect$$libinit$$0000002C c_w.l(libinit2.o) + 0x08000292 0x08000292 0x00000000 Code RO 5819 .ARM.Collect$$libinit$$0000002E c_w.l(libinit2.o) + 0x08000292 0x08000292 0x00000000 Code RO 5821 .ARM.Collect$$libinit$$00000030 c_w.l(libinit2.o) + 0x08000292 0x08000292 0x00000000 Code RO 5823 .ARM.Collect$$libinit$$00000032 c_w.l(libinit2.o) + 0x08000292 0x08000292 0x00000002 Code RO 5824 .ARM.Collect$$libinit$$00000033 c_w.l(libinit2.o) + 0x08000294 0x08000294 0x00000002 Code RO 5844 .ARM.Collect$$libshutdown$$00000000 c_w.l(libshutdown.o) + 0x08000296 0x08000296 0x00000000 Code RO 5857 .ARM.Collect$$libshutdown$$00000002 c_w.l(libshutdown2.o) + 0x08000296 0x08000296 0x00000000 Code RO 5859 .ARM.Collect$$libshutdown$$00000004 c_w.l(libshutdown2.o) + 0x08000296 0x08000296 0x00000000 Code RO 5862 .ARM.Collect$$libshutdown$$00000007 c_w.l(libshutdown2.o) + 0x08000296 0x08000296 0x00000000 Code RO 5865 .ARM.Collect$$libshutdown$$0000000A c_w.l(libshutdown2.o) + 0x08000296 0x08000296 0x00000000 Code RO 5867 .ARM.Collect$$libshutdown$$0000000C c_w.l(libshutdown2.o) + 0x08000296 0x08000296 0x00000000 Code RO 5870 .ARM.Collect$$libshutdown$$0000000F c_w.l(libshutdown2.o) + 0x08000296 0x08000296 0x00000002 Code RO 5871 .ARM.Collect$$libshutdown$$00000010 c_w.l(libshutdown2.o) + 0x08000298 0x08000298 0x00000000 Code RO 5572 .ARM.Collect$$rtentry$$00000000 c_w.l(__rtentry.o) + 0x08000298 0x08000298 0x00000000 Code RO 5677 .ARM.Collect$$rtentry$$00000002 c_w.l(__rtentry2.o) + 0x08000298 0x08000298 0x00000006 Code RO 5689 .ARM.Collect$$rtentry$$00000004 c_w.l(__rtentry4.o) + 0x0800029e 0x0800029e 0x00000000 Code RO 5679 .ARM.Collect$$rtentry$$00000009 c_w.l(__rtentry2.o) + 0x0800029e 0x0800029e 0x00000004 Code RO 5680 .ARM.Collect$$rtentry$$0000000A c_w.l(__rtentry2.o) + 0x080002a2 0x080002a2 0x00000000 Code RO 5682 .ARM.Collect$$rtentry$$0000000C c_w.l(__rtentry2.o) + 0x080002a2 0x080002a2 0x00000008 Code RO 5683 .ARM.Collect$$rtentry$$0000000D c_w.l(__rtentry2.o) + 0x080002aa 0x080002aa 0x00000002 Code RO 5773 .ARM.Collect$$rtexit$$00000000 c_w.l(rtexit.o) + 0x080002ac 0x080002ac 0x00000000 Code RO 5826 .ARM.Collect$$rtexit$$00000002 c_w.l(rtexit2.o) + 0x080002ac 0x080002ac 0x00000004 Code RO 5827 .ARM.Collect$$rtexit$$00000003 c_w.l(rtexit2.o) + 0x080002b0 0x080002b0 0x00000006 Code RO 5828 .ARM.Collect$$rtexit$$00000004 c_w.l(rtexit2.o) + 0x080002b6 0x080002b6 0x00000002 PAD + 0x080002b8 0x080002b8 0x00000040 Code RO 20 .text startup_stm32f10x_hd.o + 0x080002f8 0x080002f8 0x00000034 Code RO 5402 .text c_w.l(vsnprintf.o) + 0x0800032c 0x0800032c 0x0000002c Code RO 5404 .text c_w.l(__2sprintf.o) + 0x08000358 0x08000358 0x0000004e Code RO 5410 .text c_w.l(_printf_pad.o) + 0x080003a6 0x080003a6 0x00000052 Code RO 5412 .text c_w.l(_printf_str.o) + 0x080003f8 0x080003f8 0x00000078 Code RO 5414 .text c_w.l(_printf_dec.o) + 0x08000470 0x08000470 0x00000094 Code RO 5434 .text c_w.l(_printf_hex_int_ll_ptr.o) + 0x08000504 0x08000504 0x00000188 Code RO 5454 .text c_w.l(__printf_flags_ss_wp.o) + 0x0800068c 0x0800068c 0x0000003c Code RO 5462 .text c_w.l(__0sscanf.o) + 0x080006c8 0x080006c8 0x0000014c Code RO 5464 .text c_w.l(_scanf_int.o) + 0x08000814 0x08000814 0x00000014 Code RO 5466 .text c_w.l(strchr.o) + 0x08000828 0x08000828 0x00000024 Code RO 5468 .text c_w.l(strstr.o) + 0x0800084c 0x0800084c 0x00000058 Code RO 5470 .text c_w.l(memcmp.o) + 0x080008a4 0x080008a4 0x00000048 Code RO 5472 .text c_w.l(strcpy.o) + 0x080008ec 0x080008ec 0x0000003e Code RO 5474 .text c_w.l(strlen.o) + 0x0800092a 0x0800092a 0x0000008a Code RO 5476 .text c_w.l(rt_memcpy_v6.o) + 0x080009b4 0x080009b4 0x00000064 Code RO 5478 .text c_w.l(rt_memcpy_w.o) + 0x08000a18 0x08000a18 0x00000010 Code RO 5480 .text c_w.l(aeabi_memset.o) + 0x08000a28 0x08000a28 0x00000044 Code RO 5482 .text c_w.l(rt_memclr.o) + 0x08000a6c 0x08000a6c 0x0000004e Code RO 5484 .text c_w.l(rt_memclr_w.o) + 0x08000aba 0x08000aba 0x00000056 Code RO 5486 .text c_w.l(strncpy.o) + 0x08000b10 0x08000b10 0x00000006 Code RO 5488 .text c_w.l(heapauxi.o) + 0x08000b16 0x08000b16 0x00000024 Code RO 5575 .text c_w.l(_printf_truncate.o) + 0x08000b3a 0x08000b3a 0x000000b2 Code RO 5577 .text c_w.l(_printf_intcommon.o) + 0x08000bec 0x08000bec 0x00000028 Code RO 5579 .text c_w.l(_printf_charcount.o) + 0x08000c14 0x08000c14 0x00000030 Code RO 5581 .text c_w.l(_printf_char_common.o) + 0x08000c44 0x08000c44 0x0000000a Code RO 5583 .text c_w.l(_sputc.o) + 0x08000c4e 0x08000c4e 0x00000010 Code RO 5585 .text c_w.l(_snputc.o) + 0x08000c5e 0x08000c5e 0x0000002c Code RO 5587 .text c_w.l(_printf_char.o) + 0x08000c8a 0x08000c8a 0x00000002 PAD + 0x08000c8c 0x08000c8c 0x000000bc Code RO 5589 .text c_w.l(_printf_wctomb.o) + 0x08000d48 0x08000d48 0x0000007c Code RO 5592 .text c_w.l(_printf_longlong_dec.o) + 0x08000dc4 0x08000dc4 0x00000070 Code RO 5598 .text c_w.l(_printf_oct_int_ll.o) + 0x08000e34 0x08000e34 0x0000001c Code RO 5619 .text c_w.l(_chval.o) + 0x08000e50 0x08000e50 0x0000002c Code RO 5621 .text c_w.l(scanf_char.o) + 0x08000e7c 0x08000e7c 0x00000040 Code RO 5623 .text c_w.l(_sgetc.o) + 0x08000ebc 0x08000ebc 0x0000008a Code RO 5696 .text c_w.l(lludiv10.o) + 0x08000f46 0x08000f46 0x00000012 Code RO 5698 .text c_w.l(isspace.o) + 0x08000f58 0x08000f58 0x0000041e Code RO 5700 .text c_w.l(_printf_fp_dec.o) + 0x08001376 0x08001376 0x00000002 PAD + 0x08001378 0x08001378 0x000002fc Code RO 5702 .text c_w.l(_printf_fp_hex.o) + 0x08001674 0x08001674 0x0000002c Code RO 5707 .text c_w.l(_printf_wchar.o) + 0x080016a0 0x080016a0 0x00000374 Code RO 5709 .text c_w.l(_scanf.o) + 0x08001a14 0x08001a14 0x00000040 Code RO 5711 .text c_w.l(_wcrtomb.o) + 0x08001a54 0x08001a54 0x00000008 Code RO 5719 .text c_w.l(libspace.o) + 0x08001a5c 0x08001a5c 0x0000004a Code RO 5722 .text c_w.l(sys_stackheap_outer.o) + 0x08001aa6 0x08001aa6 0x00000002 PAD + 0x08001aa8 0x08001aa8 0x00000010 Code RO 5724 .text c_w.l(rt_ctype_table.o) + 0x08001ab8 0x08001ab8 0x00000008 Code RO 5729 .text c_w.l(rt_locale_intlibspace.o) + 0x08001ac0 0x08001ac0 0x00000080 Code RO 5731 .text c_w.l(_printf_fp_infnan.o) + 0x08001b40 0x08001b40 0x000000e4 Code RO 5733 .text c_w.l(bigflt0.o) + 0x08001c24 0x08001c24 0x00000012 Code RO 5761 .text c_w.l(exit.o) + 0x08001c36 0x08001c36 0x00000002 PAD + 0x08001c38 0x08001c38 0x00000080 Code RO 5778 .text c_w.l(strcmpv7m.o) + 0x08001cb8 0x08001cb8 0x0000000c Code RO 5836 .text c_w.l(sys_exit.o) + 0x08001cc4 0x08001cc4 0x00000002 Code RO 5847 .text c_w.l(use_no_semi.o) + 0x08001cc6 0x08001cc6 0x00000000 Code RO 5849 .text c_w.l(indicate_semi.o) + 0x08001cc6 0x08001cc6 0x0000003e Code RO 5736 CL$$btod_d2e c_w.l(btod.o) + 0x08001d04 0x08001d04 0x00000046 Code RO 5738 CL$$btod_d2e_denorm_low c_w.l(btod.o) + 0x08001d4a 0x08001d4a 0x00000060 Code RO 5737 CL$$btod_d2e_norm_op1 c_w.l(btod.o) + 0x08001daa 0x08001daa 0x00000338 Code RO 5746 CL$$btod_div_common c_w.l(btod.o) + 0x080020e2 0x080020e2 0x000000dc Code RO 5743 CL$$btod_e2e c_w.l(btod.o) + 0x080021be 0x080021be 0x0000002a Code RO 5740 CL$$btod_ediv c_w.l(btod.o) + 0x080021e8 0x080021e8 0x0000002a Code RO 5739 CL$$btod_emul c_w.l(btod.o) + 0x08002212 0x08002212 0x00000244 Code RO 5745 CL$$btod_mult_common c_w.l(btod.o) + 0x08002456 0x08002456 0x00000014 Code RO 2316 i.ADC_Cmd stm32f10x_adc.o + 0x0800246a 0x0800246a 0x00000002 PAD + 0x0800246c 0x0800246c 0x00000044 Code RO 2318 i.ADC_DeInit stm32f10x_adc.o + 0x080024b0 0x080024b0 0x0000000e Code RO 2324 i.ADC_GetCalibrationStatus stm32f10x_adc.o + 0x080024be 0x080024be 0x00000006 Code RO 2325 i.ADC_GetConversionValue stm32f10x_adc.o + 0x080024c4 0x080024c4 0x0000000e Code RO 2327 i.ADC_GetFlagStatus stm32f10x_adc.o + 0x080024d2 0x080024d2 0x0000000e Code RO 2330 i.ADC_GetResetCalibrationStatus stm32f10x_adc.o + 0x080024e0 0x080024e0 0x00000034 Code RO 1076 i.ADC_GetVal adc.o + 0x08002514 0x08002514 0x00000048 Code RO 2334 i.ADC_Init stm32f10x_adc.o + 0x0800255c 0x0800255c 0x00000074 Code RO 2338 i.ADC_RegularChannelConfig stm32f10x_adc.o + 0x080025d0 0x080025d0 0x0000000a Code RO 2339 i.ADC_ResetCalibration stm32f10x_adc.o + 0x080025da 0x080025da 0x00000014 Code RO 2341 i.ADC_SoftwareStartConvCmd stm32f10x_adc.o + 0x080025ee 0x080025ee 0x0000000a Code RO 2343 i.ADC_StartCalibration stm32f10x_adc.o + 0x080025f8 0x080025f8 0x00000058 Code RO 411 i.ADDR_Assign_Moni gpio.o + 0x08002650 0x08002650 0x00000098 Code RO 412 i.ADDR_Rank_Moni gpio.o + 0x080026e8 0x080026e8 0x00000160 Code RO 1180 i.AFE_Ctrl afe_sh3673520.o + 0x08002848 0x08002848 0x000001ac Code RO 1181 i.AFE_CurrentProcess afe_sh3673520.o + 0x080029f4 0x080029f4 0x000006fe Code RO 1182 i.AFE_ProtectProcess afe_sh3673520.o + 0x080030f2 0x080030f2 0x00000036 Code RO 1183 i.AFE_Read afe_sh3673520.o + 0x08003128 0x08003128 0x00000138 Code RO 857 i.AFE_ReadMulByte spi.o + 0x08003260 0x08003260 0x00000094 Code RO 858 i.AFE_Reset spi.o + 0x080032f4 0x080032f4 0x000000a4 Code RO 1184 i.AFE_TemperaProcess afe_sh3673520.o + 0x08003398 0x08003398 0x000003f0 Code RO 1185 i.AFE_VoltageProcess afe_sh3673520.o + 0x08003788 0x08003788 0x0000004c Code RO 1186 i.AFE_Write afe_sh3673520.o + 0x080037d4 0x080037d4 0x00000098 Code RO 859 i.AFE_WriteOneByte spi.o + 0x0800386c 0x0800386c 0x000000b8 Code RO 135 i.Addr_Set global.o + 0x08003924 0x08003924 0x00000012 Code RO 2534 i.BKP_DeInit stm32f10x_bkp.o + 0x08003936 0x08003936 0x00000002 PAD + 0x08003938 0x08003938 0x00000010 Code RO 2539 i.BKP_ReadBackupRegister stm32f10x_bkp.o + 0x08003948 0x08003948 0x00000010 Code RO 2543 i.BKP_WriteBackupRegister stm32f10x_bkp.o + 0x08003958 0x08003958 0x0000009c Code RO 2091 i.BLE_CheckName mbo26a.o + 0x080039f4 0x080039f4 0x00000018 Code RO 2092 i.BLE_ClearBuf mbo26a.o + 0x08003a0c 0x08003a0c 0x00000014 Code RO 2093 i.BLE_ClearFlg mbo26a.o + 0x08003a20 0x08003a20 0x000000cc Code RO 2095 i.BLE_GETPARA mbo26a.o + 0x08003aec 0x08003aec 0x00000038 Code RO 2096 i.BLE_IO_Init mbo26a.o + 0x08003b24 0x08003b24 0x00001230 Code RO 2097 i.BLE_IQ_Transmit mbo26a.o + 0x08004d54 0x08004d54 0x000002b4 Code RO 2098 i.BLE_IQ_Update mbo26a.o + 0x08005008 0x08005008 0x00000030 Code RO 2099 i.BLE_IT_Receive mbo26a.o + 0x08005038 0x08005038 0x000000fc Code RO 2100 i.BLE_IT_Update mbo26a.o + 0x08005134 0x08005134 0x0000002c Code RO 2101 i.BLE_Init mbo26a.o + 0x08005160 0x08005160 0x00000002 Code RO 2102 i.BLE_Open mbo26a.o + 0x08005162 0x08005162 0x00000002 PAD + 0x08005164 0x08005164 0x00000134 Code RO 2103 i.BLE_PUTSRVC mbo26a.o + 0x08005298 0x08005298 0x00000028 Code RO 2104 i.BLE_Reset mbo26a.o + 0x080052c0 0x080052c0 0x00000134 Code RO 2105 i.BLE_SETPARA mbo26a.o + 0x080053f4 0x080053f4 0x00000028 Code RO 2106 i.BLE_SetBaud mbo26a.o + 0x0800541c 0x0800541c 0x0000002c Code RO 2107 i.BLE_TIM_Moni mbo26a.o + 0x08005448 0x08005448 0x00000004 Code RO 2108 i.BLE_WriteName mbo26a.o + 0x0800544c 0x0800544c 0x0000003c Code RO 2109 i.BLE_printf mbo26a.o + 0x08005488 0x08005488 0x00000002 Code RO 315 i.BusFault_Handler stm32f10x_it.o + 0x0800548a 0x0800548a 0x00000002 PAD + 0x0800548c 0x0800548c 0x00000084 Code RO 1187 i.CALI_CurrentProcess afe_sh3673520.o + 0x08005510 0x08005510 0x0000009c Code RO 1031 i.CAN1_SendData can.o + 0x080055ac 0x080055ac 0x0000002c Code RO 2614 i.CAN_DeInit stm32f10x_can.o + 0x080055d8 0x080055d8 0x000000cc Code RO 2616 i.CAN_FilterInit stm32f10x_can.o + 0x080056a4 0x080056a4 0x000000a8 Code RO 2618 i.CAN_GetITStatus stm32f10x_can.o + 0x0800574c 0x0800574c 0x00000010 Code RO 2622 i.CAN_ITConfig stm32f10x_can.o + 0x0800575c 0x0800575c 0x000000e8 Code RO 2623 i.CAN_Init stm32f10x_can.o + 0x08005844 0x08005844 0x000002c4 Code RO 5225 i.CAN_Protocol_Deye protocolswitch_p1.o + 0x08005b08 0x08005b08 0x00000398 Code RO 5227 i.CAN_Protocol_Growatt protocolswitch_p1.o + 0x08005ea0 0x08005ea0 0x00000562 Code RO 5230 i.CAN_Protocol_Pylon protocolswitch_p1.o + 0x08006402 0x08006402 0x00000002 PAD + 0x08006404 0x08006404 0x00000338 Code RO 5231 i.CAN_Protocol_SolArk protocolswitch_p1.o + 0x0800673c 0x0800673c 0x00000284 Code RO 5234 i.CAN_Protocol_solis protocolswitch_p1.o + 0x080069c0 0x080069c0 0x00000090 Code RO 2626 i.CAN_Receive stm32f10x_can.o + 0x08006a50 0x08006a50 0x00000020 Code RO 2629 i.CAN_StructInit stm32f10x_can.o + 0x08006a70 0x08006a70 0x00000018 Code RO 1032 i.CAN_TIM_Moni can.o + 0x08006a88 0x08006a88 0x000000a4 Code RO 2631 i.CAN_Transmit stm32f10x_can.o + 0x08006b2c 0x08006b2c 0x0000006c Code RO 2632 i.CAN_TransmitStatus stm32f10x_can.o + 0x08006b98 0x08006b98 0x00000034 Code RO 1033 i.CAN_UpdateData can.o + 0x08006bcc 0x08006bcc 0x000000e0 Code RO 1188 i.CHG_LIMIT_Ctrl afe_sh3673520.o + 0x08006cac 0x08006cac 0x00000048 Code RO 1113 i.CHG_LIMIT_Init pwm.o + 0x08006cf4 0x08006cf4 0x00000038 Code RO 1114 i.CHG_LIMIT_Off pwm.o + 0x08006d2c 0x08006d2c 0x000000b0 Code RO 1115 i.CHG_LIMIT_On pwm.o + 0x08006ddc 0x08006ddc 0x000000e0 Code RO 1116 i.CHG_LIMIT_PWM_Adjust pwm.o + 0x08006ebc 0x08006ebc 0x0000003c Code RO 1293 i.CRC16_Cal rs485_modbus.o + 0x08006ef8 0x08006ef8 0x00000024 Code RO 137 i.CRC8_Cal global.o + 0x08006f1c 0x08006f1c 0x00000020 Code RO 1189 i.CTRL_Off afe_sh3673520.o + 0x08006f3c 0x08006f3c 0x0000000c Code RO 1190 i.CTRL_On afe_sh3673520.o + 0x08006f48 0x08006f48 0x000000f8 Code RO 1802 i.Cali_FCC_Moni gasgauge.o + 0x08007040 0x08007040 0x00000048 Code RO 1803 i.Cali_SOC_Moni gasgauge.o + 0x08007088 0x08007088 0x0000000c Code RO 2634 i.CheckITStatus stm32f10x_can.o + 0x08007094 0x08007094 0x0000000c Code RO 413 i.DO_Off gpio.o + 0x080070a0 0x080070a0 0x0000000c Code RO 414 i.DO_On gpio.o + 0x080070ac 0x080070ac 0x00000002 Code RO 316 i.DebugMon_Handler stm32f10x_it.o + 0x080070ae 0x080070ae 0x000000bc Code RO 799 i.EEPROM_CALI_RdGain i2c.o + 0x0800716a 0x0800716a 0x000000ba Code RO 800 i.EEPROM_CALI_RdZero i2c.o + 0x08007224 0x08007224 0x00000060 Code RO 801 i.EEPROM_CALI_WrGain i2c.o + 0x08007284 0x08007284 0x00000060 Code RO 802 i.EEPROM_CALI_WrZero i2c.o + 0x080072e4 0x080072e4 0x000001b0 Code RO 803 i.EEPROM_RdMulByte i2c.o + 0x08007494 0x08007494 0x00000140 Code RO 804 i.EEPROM_WrMulByte i2c.o + 0x080075d4 0x080075d4 0x00000038 Code RO 138 i.FCCCali_TIM_Moni global.o + 0x0800760c 0x0800760c 0x0000000c Code RO 3125 i.FLASH_ClearFlag stm32f10x_flash.o + 0x08007618 0x08007618 0x0000003c Code RO 3130 i.FLASH_ErasePage stm32f10x_flash.o + 0x08007654 0x08007654 0x00000028 Code RO 3131 i.FLASH_GetBank1Status stm32f10x_flash.o + 0x0800767c 0x0800767c 0x00000010 Code RO 3140 i.FLASH_Lock stm32f10x_flash.o + 0x0800768c 0x0800768c 0x00000034 Code RO 3143 i.FLASH_ProgramHalfWord stm32f10x_flash.o + 0x080076c0 0x080076c0 0x00000014 Code RO 897 i.FLASH_RdDataByte flash.o + 0x080076d4 0x080076d4 0x0000001a Code RO 898 i.FLASH_RdWord flash.o + 0x080076ee 0x080076ee 0x00000002 PAD + 0x080076f0 0x080076f0 0x00000058 Code RO 899 i.FLASH_ReadCheck flash.o + 0x08007748 0x08007748 0x00000018 Code RO 3148 i.FLASH_Unlock stm32f10x_flash.o + 0x08007760 0x08007760 0x00000024 Code RO 900 i.FLASH_UpdateMemory flash.o + 0x08007784 0x08007784 0x00000024 Code RO 3152 i.FLASH_WaitForLastOperation stm32f10x_flash.o + 0x080077a8 0x080077a8 0x00000040 Code RO 901 i.FLASH_WrData flash.o + 0x080077e8 0x080077e8 0x000000a2 Code RO 3423 i.GPIO_Init stm32f10x_gpio.o + 0x0800788a 0x0800788a 0x00000002 PAD + 0x0800788c 0x0800788c 0x00000058 Code RO 3425 i.GPIO_PinRemapConfig stm32f10x_gpio.o + 0x080078e4 0x080078e4 0x0000000e Code RO 3427 i.GPIO_ReadInputDataBit stm32f10x_gpio.o + 0x080078f2 0x080078f2 0x00000004 Code RO 3430 i.GPIO_ResetBits stm32f10x_gpio.o + 0x080078f6 0x080078f6 0x00000004 Code RO 3431 i.GPIO_SetBits stm32f10x_gpio.o + 0x080078fa 0x080078fa 0x00000002 PAD + 0x080078fc 0x080078fc 0x000004d0 Code RO 1804 i.GaugeManage gasgauge.o + 0x08007dcc 0x08007dcc 0x00000054 Code RO 140 i.GetStr global.o + 0x08007e20 0x08007e20 0x00000010 Code RO 415 i.HAL_GPIO_TogglePin gpio.o + 0x08007e30 0x08007e30 0x0000001c Code RO 317 i.HardFault_Handler stm32f10x_it.o + 0x08007e4c 0x08007e4c 0x00000014 Code RO 3532 i.I2C_AcknowledgeConfig stm32f10x_i2c.o + 0x08007e60 0x08007e60 0x00000018 Code RO 3534 i.I2C_CheckEvent stm32f10x_i2c.o + 0x08007e78 0x08007e78 0x00000014 Code RO 3537 i.I2C_Cmd stm32f10x_i2c.o + 0x08007e8c 0x08007e8c 0x0000002c Code RO 3540 i.I2C_DeInit stm32f10x_i2c.o + 0x08007eb8 0x08007eb8 0x00000014 Code RO 3544 i.I2C_GenerateSTART stm32f10x_i2c.o + 0x08007ecc 0x08007ecc 0x00000014 Code RO 3545 i.I2C_GenerateSTOP stm32f10x_i2c.o + 0x08007ee0 0x08007ee0 0x0000002a Code RO 3546 i.I2C_GetFlagStatus stm32f10x_i2c.o + 0x08007f0a 0x08007f0a 0x00000002 PAD + 0x08007f0c 0x08007f0c 0x000000bc Code RO 3551 i.I2C_Init stm32f10x_i2c.o + 0x08007fc8 0x08007fc8 0x00000006 Code RO 3556 i.I2C_ReceiveData stm32f10x_i2c.o + 0x08007fce 0x08007fce 0x00000010 Code RO 3558 i.I2C_Send7bitAddress stm32f10x_i2c.o + 0x08007fde 0x08007fde 0x00000004 Code RO 3559 i.I2C_SendData stm32f10x_i2c.o + 0x08007fe2 0x08007fe2 0x00000002 PAD + 0x08007fe4 0x08007fe4 0x00000010 Code RO 416 i.IO1_IN gpio.o + 0x08007ff4 0x08007ff4 0x00000010 Code RO 417 i.IO2_OUTReset gpio.o + 0x08008004 0x08008004 0x00000010 Code RO 418 i.IO2_OUTSet gpio.o + 0x08008014 0x08008014 0x0000000c Code RO 419 i.IO3_IN gpio.o + 0x08008020 0x08008020 0x00000010 Code RO 3735 i.IWDG_Enable stm32f10x_iwdg.o + 0x08008030 0x08008030 0x00000004 Code RO 1162 i.IWDG_Feed wdg.o + 0x08008034 0x08008034 0x00000010 Code RO 3737 i.IWDG_ReloadCounter stm32f10x_iwdg.o + 0x08008044 0x08008044 0x0000000c Code RO 3738 i.IWDG_SetPrescaler stm32f10x_iwdg.o + 0x08008050 0x08008050 0x0000000c Code RO 3739 i.IWDG_SetReload stm32f10x_iwdg.o + 0x0800805c 0x0800805c 0x0000000c Code RO 3740 i.IWDG_WriteAccessCmd stm32f10x_iwdg.o + 0x08008068 0x08008068 0x00000194 Code RO 1805 i.InitGasGauge gasgauge.o + 0x080081fc 0x080081fc 0x0000002c Code RO 948 i.Is_Leap_Year rtc.o + 0x08008228 0x08008228 0x0000000c Code RO 420 i.KEY_IN gpio.o + 0x08008234 0x08008234 0x000000b4 Code RO 421 i.KEY_TIM_Moni gpio.o + 0x080082e8 0x080082e8 0x0000000c Code RO 422 i.LED1_Off gpio.o + 0x080082f4 0x080082f4 0x0000000c Code RO 423 i.LED1_On gpio.o + 0x08008300 0x08008300 0x00000010 Code RO 424 i.LED2_Off gpio.o + 0x08008310 0x08008310 0x00000010 Code RO 425 i.LED2_On gpio.o + 0x08008320 0x08008320 0x0000000c Code RO 426 i.LED3_Off gpio.o + 0x0800832c 0x0800832c 0x0000000c Code RO 427 i.LED3_On gpio.o + 0x08008338 0x08008338 0x0000000c Code RO 428 i.LED4_Off gpio.o + 0x08008344 0x08008344 0x0000000c Code RO 429 i.LED4_On gpio.o + 0x08008350 0x08008350 0x0000000c Code RO 430 i.LED_ALARM_Off gpio.o + 0x0800835c 0x0800835c 0x0000000c Code RO 431 i.LED_ALARM_On gpio.o + 0x08008368 0x08008368 0x0000000c Code RO 432 i.LED_ALARM_Toggle gpio.o + 0x08008374 0x08008374 0x00000010 Code RO 437 i.LED_RUN_Off gpio.o + 0x08008384 0x08008384 0x00000010 Code RO 438 i.LED_RUN_On gpio.o + 0x08008394 0x08008394 0x00000010 Code RO 439 i.LED_RUN_Toggle gpio.o + 0x080083a4 0x080083a4 0x00000024 Code RO 1077 i.LOAD_VOL adc.o + 0x080083c8 0x080083c8 0x000001c4 Code RO 1078 i.MCU_TemperaProcess adc.o + 0x0800858c 0x0800858c 0x000000f0 Code RO 1191 i.MEMORY_UpdateAFE afe_sh3673520.o + 0x0800867c 0x0800867c 0x00000064 Code RO 902 i.MEMORY_UpdateFlash flash.o + 0x080086e0 0x080086e0 0x00000048 Code RO 1462 i.MODBUS1_CtrlMOS_Rx rs485_modbus_inverter.o + 0x08008728 0x08008728 0x000000cc Code RO 1463 i.MODBUS1_F03_Rx rs485_modbus_inverter.o + 0x080087f4 0x080087f4 0x00000138 Code RO 1464 i.MODBUS1_F10_Rx rs485_modbus_inverter.o + 0x0800892c 0x0800892c 0x00000048 Code RO 1465 i.MODBUS1_Faa_Rx rs485_modbus_inverter.o + 0x08008974 0x08008974 0x00000058 Code RO 1466 i.MODBUS1_Fbb_Rx rs485_modbus_inverter.o + 0x080089cc 0x080089cc 0x00000440 Code RO 1467 i.MODBUS1_IQ_Transmit rs485_modbus_inverter.o + 0x08008e0c 0x08008e0c 0x00000048 Code RO 1468 i.MODBUS1_IT_Receive rs485_modbus_inverter.o + 0x08008e54 0x08008e54 0x00000344 Code RO 1469 i.MODBUS1_IT_TIMUpdate rs485_modbus_inverter.o + 0x08009198 0x08009198 0x0000002c Code RO 1470 i.MODBUS1_Init rs485_modbus_inverter.o + 0x080091c4 0x080091c4 0x00000020 Code RO 1471 i.MODBUS1_TIM_Moni rs485_modbus_inverter.o + 0x080091e4 0x080091e4 0x0000001c Code RO 1472 i.MODBUS1_UpdateData rs485_modbus_inverter.o + 0x08009200 0x08009200 0x0000011c Code RO 1294 i.MODBUS_AddrAssign_Tx rs485_modbus.o + 0x0800931c 0x0800931c 0x00000100 Code RO 1295 i.MODBUS_Config_RdSlave_Tx rs485_modbus.o + 0x0800941c 0x0800941c 0x00000048 Code RO 1296 i.MODBUS_CtrlMOS_Rx rs485_modbus.o + 0x08009464 0x08009464 0x00000084 Code RO 1297 i.MODBUS_F03_Rx rs485_modbus.o + 0x080094e8 0x080094e8 0x00000140 Code RO 1298 i.MODBUS_F10_Rx rs485_modbus.o + 0x08009628 0x08009628 0x00000048 Code RO 1299 i.MODBUS_Faa_Rx rs485_modbus.o + 0x08009670 0x08009670 0x00000058 Code RO 1300 i.MODBUS_Fbb_Rx rs485_modbus.o + 0x080096c8 0x080096c8 0x000003a4 Code RO 1301 i.MODBUS_IQ_Transmit rs485_modbus.o + 0x08009a6c 0x08009a6c 0x00000060 Code RO 1302 i.MODBUS_IT_Receive rs485_modbus.o + 0x08009acc 0x08009acc 0x00000328 Code RO 1303 i.MODBUS_IT_TIMUpdate rs485_modbus.o + 0x08009df4 0x08009df4 0x00000048 Code RO 1304 i.MODBUS_Init rs485_modbus.o + 0x08009e3c 0x08009e3c 0x0000008c Code RO 1305 i.MODBUS_MASTER_F03_Rx rs485_modbus.o + 0x08009ec8 0x08009ec8 0x00000044 Code RO 1306 i.MODBUS_MASTER_F10_Rx rs485_modbus.o + 0x08009f0c 0x08009f0c 0x000000a4 Code RO 1308 i.MODBUS_Poll_Init rs485_modbus.o + 0x08009fb0 0x08009fb0 0x00000024 Code RO 1311 i.MODBUS_TIM_Moni rs485_modbus.o + 0x08009fd4 0x08009fd4 0x00000002 Code RO 318 i.MemManage_Handler stm32f10x_it.o + 0x08009fd6 0x08009fd6 0x00000002 Code RO 319 i.NMI_Handler stm32f10x_it.o + 0x08009fd8 0x08009fd8 0x00000014 Code RO 2275 i.NVIC_PriorityGroupConfig misc.o + 0x08009fec 0x08009fec 0x0000000c Code RO 442 i.PCHG_Off gpio.o + 0x08009ff8 0x08009ff8 0x00000002 Code RO 320 i.PendSV_Handler stm32f10x_it.o + 0x08009ffa 0x08009ffa 0x00000004 Code RO 860 i.SPI2_Error spi.o + 0x08009ffe 0x08009ffe 0x00000002 Code RO 321 i.SVC_Handler stm32f10x_it.o + 0x0800a000 0x0800a000 0x00000800 Data RO 904 .ARM.__AT_0x0800A000 flash.o + 0x0800a800 0x0800a800 0x000002d4 Code RO 1307 i.MODBUS_MASTER_Polling_Tx rs485_modbus.o + 0x0800aad4 0x0800aad4 0x000000f0 Code RO 1309 i.MODBUS_Screen_RdSlave_Tx rs485_modbus.o + 0x0800abc4 0x0800abc4 0x000000bc Code RO 1310 i.MODBUS_Screen_WrSlaveAddr_Tx rs485_modbus.o + 0x0800ac80 0x0800ac80 0x00000064 Code RO 1312 i.MODBUS_WrIndex_Rx rs485_modbus.o + 0x0800ace4 0x0800ace4 0x0000005c Code RO 1313 i.MODBUS_WrIndex_Tx rs485_modbus.o + 0x0800ad40 0x0800ad40 0x000002fc Code RO 5235 i.MOD_Protocol_Growatt protocolswitch_p1.o + 0x0800b03c 0x0800b03c 0x00000384 Code RO 5332 i.MOD_Protocol_Voltronic protocolswitch_p2.o + 0x0800b3c0 0x0800b3c0 0x00000064 Code RO 2274 i.NVIC_Init misc.o + 0x0800b424 0x0800b424 0x0000004c Code RO 1192 i.OCC2_Ctrl afe_sh3673520.o + 0x0800b470 0x0800b470 0x0000004c Code RO 1193 i.OCC2_TIM_Moni afe_sh3673520.o + 0x0800b4bc 0x0800b4bc 0x000001d4 Code RO 1862 i.OCV_CaliSOC ocv.o + 0x0800b690 0x0800b690 0x000000b4 Code RO 1863 i.OCV_CaliSOC_DataWr ocv.o + 0x0800b744 0x0800b744 0x000000b4 Code RO 1864 i.OCV_CaliSoc_dp ocv.o + 0x0800b7f8 0x0800b7f8 0x0000009c Code RO 441 i.PCHG_Ctrl gpio.o + 0x0800b894 0x0800b894 0x0000000c Code RO 443 i.PCHG_On gpio.o + 0x0800b8a0 0x0800b8a0 0x00000098 Code RO 444 i.PCHG_StartCtrl gpio.o + 0x0800b938 0x0800b938 0x00000044 Code RO 1117 i.PWM_Set_Duty_Percent pwm.o + 0x0800b97c 0x0800b97c 0x0000000c Code RO 3777 i.PWR_BackupAccessCmd stm32f10x_pwr.o + 0x0800b988 0x0800b988 0x00000340 Code RO 142 i.ParaChange global.o + 0x0800bcc8 0x0800bcc8 0x00000014 Code RO 3837 i.RCC_ADCCLKConfig stm32f10x_rcc.o + 0x0800bcdc 0x0800bcdc 0x00000018 Code RO 3839 i.RCC_APB1PeriphClockCmd stm32f10x_rcc.o + 0x0800bcf4 0x0800bcf4 0x00000018 Code RO 3840 i.RCC_APB1PeriphResetCmd stm32f10x_rcc.o + 0x0800bd0c 0x0800bd0c 0x00000018 Code RO 3841 i.RCC_APB2PeriphClockCmd stm32f10x_rcc.o + 0x0800bd24 0x0800bd24 0x00000018 Code RO 3842 i.RCC_APB2PeriphResetCmd stm32f10x_rcc.o + 0x0800bd3c 0x0800bd3c 0x0000000c Code RO 3844 i.RCC_BackupResetCmd stm32f10x_rcc.o + 0x0800bd48 0x0800bd48 0x00000090 Code RO 3849 i.RCC_GetClocksFreq stm32f10x_rcc.o + 0x0800bdd8 0x0800bdd8 0x00000030 Code RO 3850 i.RCC_GetFlagStatus stm32f10x_rcc.o + 0x0800be08 0x0800be08 0x00000020 Code RO 3857 i.RCC_LSEConfig stm32f10x_rcc.o + 0x0800be28 0x0800be28 0x0000000c Code RO 3864 i.RCC_RTCCLKCmd stm32f10x_rcc.o + 0x0800be34 0x0800be34 0x00000010 Code RO 3865 i.RCC_RTCCLKConfig stm32f10x_rcc.o + 0x0800be44 0x0800be44 0x000000a0 Code RO 949 i.RTC_BackUp rtc.o + 0x0800bee4 0x0800bee4 0x00000010 Code RO 4039 i.RTC_EnterConfigMode stm32f10x_rtc.o + 0x0800bef4 0x0800bef4 0x00000010 Code RO 4040 i.RTC_ExitConfigMode stm32f10x_rtc.o + 0x0800bf04 0x0800bf04 0x00000020 Code RO 4041 i.RTC_GetCounter stm32f10x_rtc.o + 0x0800bf24 0x0800bf24 0x00000034 Code RO 951 i.RTC_GetSynchro rtc.o + 0x0800bf58 0x0800bf58 0x00000094 Code RO 952 i.RTC_Get_Week rtc.o + 0x0800bfec 0x0800bfec 0x00000010 Code RO 4049 i.RTC_WaitForLastTask stm32f10x_rtc.o + 0x0800bffc 0x0800bffc 0x00000004 Code RO 4328 i.SPI_I2S_ReceiveData stm32f10x_spi.o + 0x0800c000 0x0800c000 0x00000800 Data RO 905 .ARM.__AT_0x0800C000 flash.o + 0x0800c800 0x0800c800 0x000003d0 Code RO 950 i.RTC_Get rtc.o + 0x0800cbd0 0x0800cbd0 0x00000018 Code RO 4045 i.RTC_ITConfig stm32f10x_rtc.o + 0x0800cbe8 0x0800cbe8 0x00000130 Code RO 953 i.RTC_Set rtc.o + 0x0800cd18 0x0800cd18 0x00000020 Code RO 4047 i.RTC_SetCounter stm32f10x_rtc.o + 0x0800cd38 0x0800cd38 0x00000020 Code RO 4048 i.RTC_SetPrescaler stm32f10x_rtc.o + 0x0800cd58 0x0800cd58 0x00000018 Code RO 4050 i.RTC_WaitForSynchro stm32f10x_rtc.o + 0x0800cd70 0x0800cd70 0x0000002c Code RO 143 i.Refresh_BMS_SN global.o + 0x0800cd9c 0x0800cd9c 0x00000048 Code RO 144 i.Refresh_FirmwareVersion global.o + 0x0800cde4 0x0800cde4 0x00000040 Code RO 145 i.Refresh_HardwareVersion global.o + 0x0800ce24 0x0800ce24 0x00000030 Code RO 146 i.Refresh_PACK_SN global.o + 0x0800ce54 0x0800ce54 0x00000080 Code RO 147 i.Refresh_ScreenVersion global.o + 0x0800ced4 0x0800ced4 0x000000f8 Code RO 1894 i.Release_CurAlarm status.o + 0x0800cfcc 0x0800cfcc 0x000000e4 Code RO 1895 i.Release_CurProtect status.o + 0x0800d0b0 0x0800d0b0 0x00000130 Code RO 1896 i.Release_OVAlarm status.o + 0x0800d1e0 0x0800d1e0 0x00000118 Code RO 1897 i.Release_OVProtect status.o + 0x0800d2f8 0x0800d2f8 0x000000cc Code RO 1898 i.Release_UVAlarm status.o + 0x0800d3c4 0x0800d3c4 0x000000c8 Code RO 1899 i.Release_UVProtect status.o + 0x0800d48c 0x0800d48c 0x00000094 Code RO 1900 i.Release_afeTAlarm status.o + 0x0800d520 0x0800d520 0x00000094 Code RO 1901 i.Release_afeTProtect status.o + 0x0800d5b4 0x0800d5b4 0x000000fc Code RO 1902 i.Release_amTAlarm status.o + 0x0800d6b0 0x0800d6b0 0x000000fc Code RO 1903 i.Release_amTProtect status.o + 0x0800d7ac 0x0800d7ac 0x00000110 Code RO 1904 i.Release_mcuTAlarm status.o + 0x0800d8bc 0x0800d8bc 0x00000110 Code RO 1905 i.Release_mcuTProtect status.o + 0x0800d9cc 0x0800d9cc 0x0000014c Code RO 1603 i.SCR_ClearAlarm screen.o + 0x0800db18 0x0800db18 0x00000590 Code RO 1604 i.SCR_DispProcotol screen.o + 0x0800e0a8 0x0800e0a8 0x00000030 Code RO 1605 i.SCR_JumpToAlarm screen.o + 0x0800e0d8 0x0800e0d8 0x0000030c Code RO 1607 i.SCR_Send_Record screen.o + 0x0800e3e4 0x0800e3e4 0x00000284 Code RO 1608 i.SCR_Send_RecordInfo screen.o + 0x0800e668 0x0800e668 0x00000758 Code RO 1610 i.SCR_Send_Self_BasicInfo screen.o + 0x0800edc0 0x0800edc0 0x00000820 Code RO 1611 i.SCR_Send_Slave_BasicInfo screen.o + 0x0800f5e0 0x0800f5e0 0x000000b4 Code RO 1612 i.SCR_Send_Slave_RecordBank screen.o + 0x0800f694 0x0800f694 0x00000068 Code RO 1613 i.SCR_Send_Time screen.o + 0x0800f6fc 0x0800f6fc 0x000002c4 Code RO 1615 i.SCR_Send_TotalInfo screen.o + 0x0800f9c0 0x0800f9c0 0x000000e4 Code RO 1616 i.SCR_Send_VER screen.o + 0x0800faa4 0x0800faa4 0x00000344 Code RO 1617 i.SCR_ShowAlarm screen.o + 0x0800fde8 0x0800fde8 0x00000320 Code RO 1618 i.SCR_ShowAlarm_Slave screen.o + 0x08010108 0x08010108 0x0000008c Code RO 148 i.SLEEP2_Refresh global.o + 0x08010194 0x08010194 0x0000008c Code RO 149 i.SLEEP2_TIM_Moni global.o + 0x08010220 0x08010220 0x00000038 Code RO 150 i.SLEEP_Refresh global.o + 0x08010258 0x08010258 0x00000038 Code RO 151 i.SLEEP_TIM_Moni global.o + 0x08010290 0x08010290 0x00000434 Code RO 1844 i.SOE_BkData soe.o + 0x080106c4 0x080106c4 0x00000014 Code RO 4317 i.SPI_Cmd stm32f10x_spi.o + 0x080106d8 0x080106d8 0x00000054 Code RO 4324 i.SPI_I2S_DeInit stm32f10x_spi.o + 0x0801072c 0x0801072c 0x0000000e Code RO 4325 i.SPI_I2S_GetFlagStatus stm32f10x_spi.o + 0x0801073a 0x0801073a 0x00000004 Code RO 4329 i.SPI_I2S_SendData stm32f10x_spi.o + 0x0801073e 0x0801073e 0x00000038 Code RO 4330 i.SPI_Init stm32f10x_spi.o + 0x08010776 0x08010776 0x00000002 PAD + 0x08010778 0x08010778 0x00000018 Code RO 1619 i.Screen_ClearBuf screen.o + 0x08010790 0x08010790 0x00000954 Code RO 1621 i.Screen_IQ_Transmit screen.o + 0x080110e4 0x080110e4 0x00000034 Code RO 1622 i.Screen_IT_Receive screen.o + 0x08011118 0x08011118 0x0000151c Code RO 1623 i.Screen_IT_Update screen.o + 0x08012634 0x08012634 0x00000020 Code RO 1624 i.Screen_Init screen.o + 0x08012654 0x08012654 0x00000018 Code RO 1625 i.Screen_TIM_Moni screen.o + 0x0801266c 0x0801266c 0x00000124 Code RO 1626 i.Send_Record_Blank screen.o + 0x08012790 0x08012790 0x000000a8 Code RO 382 i.SetSysClockTo72 system_stm32f10x.o + 0x08012838 0x08012838 0x00000070 Code RO 1627 i.Set_Row_Hide screen.o + 0x080128a8 0x080128a8 0x00000002 Code RO 322 i.SysTick_Handler stm32f10x_it.o + 0x080128aa 0x080128aa 0x00000002 PAD + 0x080128ac 0x080128ac 0x00000050 Code RO 384 i.SystemInit system_stm32f10x.o + 0x080128fc 0x080128fc 0x00000084 Code RO 1577 i.TEMP_Cal ntc.o + 0x08012980 0x08012980 0x00000084 Code RO 1578 i.TEMP_Cal_CMFA ntc.o + 0x08012a04 0x08012a04 0x00000130 Code RO 681 i.TIM3_IRQHandler tim.o + 0x08012b34 0x08012b34 0x00000098 Code RO 1118 i.TIM4_PWM_Init pwm.o + 0x08012bcc 0x08012bcc 0x00000020 Code RO 683 i.TIMER_IsOut tim.o + 0x08012bec 0x08012bec 0x0000000c Code RO 684 i.TIMER_Update tim.o + 0x08012bf8 0x08012bf8 0x00000014 Code RO 4458 i.TIM_ARRPreloadConfig stm32f10x_tim.o + 0x08012c0c 0x08012c0c 0x00000006 Code RO 4465 i.TIM_ClearITPendingBit stm32f10x_tim.o + 0x08012c12 0x08012c12 0x00000014 Code RO 4470 i.TIM_Cmd stm32f10x_tim.o + 0x08012c26 0x08012c26 0x00000016 Code RO 4472 i.TIM_CtrlPWMOutputs stm32f10x_tim.o + 0x08012c3c 0x08012c3c 0x00000018 Code RO 4491 i.TIM_GetITStatus stm32f10x_tim.o + 0x08012c54 0x08012c54 0x00000010 Code RO 4495 i.TIM_ITConfig stm32f10x_tim.o + 0x08012c64 0x08012c64 0x00000064 Code RO 4514 i.TIM_OC4Init stm32f10x_tim.o + 0x08012cc8 0x08012cc8 0x00000014 Code RO 4516 i.TIM_OC4PreloadConfig stm32f10x_tim.o + 0x08012cdc 0x08012cdc 0x00000006 Code RO 4534 i.TIM_SetCompare4 stm32f10x_tim.o + 0x08012ce2 0x08012ce2 0x00000004 Code RO 4535 i.TIM_SetCounter stm32f10x_tim.o + 0x08012ce6 0x08012ce6 0x00000002 PAD + 0x08012ce8 0x08012ce8 0x0000009c Code RO 4541 i.TIM_TimeBaseInit stm32f10x_tim.o + 0x08012d84 0x08012d84 0x00000064 Code RO 449 i.TSC_Detect gpio.o + 0x08012de8 0x08012de8 0x00000098 Code RO 1906 i.Trigger_CurAlarm status.o + 0x08012e80 0x08012e80 0x0000009c Code RO 1907 i.Trigger_CurProtect status.o + 0x08012f1c 0x08012f1c 0x00000002 Code RO 1908 i.Trigger_CurProtectLock status.o + 0x08012f1e 0x08012f1e 0x00000002 PAD + 0x08012f20 0x08012f20 0x000000a0 Code RO 1909 i.Trigger_OVAlarm status.o + 0x08012fc0 0x08012fc0 0x000000e0 Code RO 1910 i.Trigger_OVProtect status.o + 0x080130a0 0x080130a0 0x000000a0 Code RO 1911 i.Trigger_UVAlarm status.o + 0x08013140 0x08013140 0x000000d8 Code RO 1912 i.Trigger_UVProtect status.o + 0x08013218 0x08013218 0x000000c0 Code RO 1913 i.Trigger_afeTAlarm status.o + 0x080132d8 0x080132d8 0x000000b8 Code RO 1914 i.Trigger_afeTProtect status.o + 0x08013390 0x08013390 0x0000012c Code RO 1915 i.Trigger_amTAlarm status.o + 0x080134bc 0x080134bc 0x0000012c Code RO 1916 i.Trigger_amTProtect status.o + 0x080135e8 0x080135e8 0x0000013c Code RO 1917 i.Trigger_mcuTAlarm status.o + 0x08013724 0x08013724 0x00000134 Code RO 1918 i.Trigger_mcuTProtect status.o + 0x08013858 0x08013858 0x00000064 Code RO 1314 i.UART1_ClearRecord rs485_modbus.o + 0x080138bc 0x080138bc 0x000000a8 Code RO 1315 i.UART1_ProtocolSwitch rs485_modbus.o + 0x08013964 0x08013964 0x00000048 Code RO 1316 i.UART1_ReadRecord rs485_modbus.o + 0x080139ac 0x080139ac 0x00000064 Code RO 1473 i.UART3_ClearRecord rs485_modbus_inverter.o + 0x08013a10 0x08013a10 0x00000030 Code RO 1474 i.UART3_EraseIAP rs485_modbus_inverter.o + 0x08013a40 0x08013a40 0x000000b0 Code RO 1475 i.UART3_ProtocolSwitch rs485_modbus_inverter.o + 0x08013af0 0x08013af0 0x00000048 Code RO 1476 i.UART3_ReadRecord rs485_modbus_inverter.o + 0x08013b38 0x08013b38 0x0000002c Code RO 725 i.UART4_IRQHandler uart.o + 0x08013b64 0x08013b64 0x0000002c Code RO 726 i.USART1_IRQHandler uart.o + 0x08013b90 0x08013b90 0x00000034 Code RO 727 i.USART1_SendMulByte uart.o + 0x08013bc4 0x08013bc4 0x0000002c Code RO 728 i.USART2_IRQHandler uart.o + 0x08013bf0 0x08013bf0 0x00000038 Code RO 1628 i.USART2_printf screen.o + 0x08013c28 0x08013c28 0x0000002c Code RO 729 i.USART3_IRQHandler uart.o + 0x08013c54 0x08013c54 0x00000034 Code RO 730 i.USART3_SendMulByte uart.o + 0x08013c88 0x08013c88 0x00000014 Code RO 4993 i.USART_Cmd stm32f10x_usart.o + 0x08013c9c 0x08013c9c 0x0000000e Code RO 4996 i.USART_GetFlagStatus stm32f10x_usart.o + 0x08013caa 0x08013caa 0x0000003e Code RO 4997 i.USART_GetITStatus stm32f10x_usart.o + 0x08013ce8 0x08013ce8 0x00000030 Code RO 4999 i.USART_ITConfig stm32f10x_usart.o + 0x08013d18 0x08013d18 0x000000ac Code RO 5000 i.USART_Init stm32f10x_usart.o + 0x08013dc4 0x08013dc4 0x00000008 Code RO 5007 i.USART_ReceiveData stm32f10x_usart.o + 0x08013dcc 0x08013dcc 0x00000008 Code RO 5010 i.USART_SendData stm32f10x_usart.o + 0x08013dd4 0x08013dd4 0x0000005c Code RO 1034 i.USB_LP_CAN1_RX0_IRQHandler can.o + 0x08013e30 0x08013e30 0x00000038 Code RO 152 i.UVOff_TIM_Moni global.o + 0x08013e68 0x08013e68 0x00000002 Code RO 323 i.UsageFault_Handler stm32f10x_it.o + 0x08013e6a 0x08013e6a 0x00000002 PAD + 0x08013e6c 0x08013e6c 0x00000a98 Code RO 1477 i.YDN rs485_modbus_inverter.o + 0x08014904 0x08014904 0x00000004 Code RO 5237 i.YDN_Protocol_Pylon protocolswitch_p1.o + 0x08014908 0x08014908 0x00000028 Code RO 5715 i.__ARM_fpclassify m_ws.l(fpclassify.o) + 0x08014930 0x08014930 0x0000000e Code RO 5447 i._is_digit c_w.l(__printf_wp.o) + 0x0801493e 0x0801493e 0x00000002 PAD + 0x08014940 0x08014940 0x00000520 Code RO 153 i.canMem_refresh global.o + 0x08014e60 0x08014e60 0x0000004c Code RO 1013 i.delay_ms systick.o + 0x08014eac 0x08014eac 0x0000003e Code RO 1014 i.delay_us systick.o + 0x08014eea 0x08014eea 0x0000002e Code RO 1629 i.findHexStr screen.o + 0x08014f18 0x08014f18 0x00000034 Code RO 154 i.get_random global.o + 0x08014f4c 0x08014f4c 0x00000320 Code RO 24 i.main main.o + 0x0801526c 0x0801526c 0x00000094 Code RO 156 i.onlineMem_refresh global.o + 0x08015300 0x08015300 0x0000000e Code RO 157 i.toASCII global.o + 0x0801530e 0x0801530e 0x00000002 PAD + 0x08015310 0x08015310 0x000000ac Code RO 1079 i.uf_ADC_Init adc.o + 0x080153bc 0x080153bc 0x00000130 Code RO 1035 i.uf_CAN1_Init can.o + 0x080154ec 0x080154ec 0x00000008 Code RO 450 i.uf_EXTI_Init gpio.o + 0x080154f4 0x080154f4 0x00000040 Code RO 903 i.uf_FLASH_Init flash.o + 0x08015534 0x08015534 0x00000218 Code RO 158 i.uf_GLOBAL_Init global.o + 0x0801574c 0x0801574c 0x000001c0 Code RO 451 i.uf_GPIO_Init gpio.o + 0x0801590c 0x0801590c 0x000001fc Code RO 805 i.uf_I2C1_Init i2c.o + 0x08015b08 0x08015b08 0x00000026 Code RO 1163 i.uf_IWDG_Init wdg.o + 0x08015b2e 0x08015b2e 0x00000002 PAD + 0x08015b30 0x08015b30 0x000001b4 Code RO 954 i.uf_RTC_Init rtc.o + 0x08015ce4 0x08015ce4 0x000000f4 Code RO 955 i.uf_RTC_Update rtc.o + 0x08015dd8 0x08015dd8 0x000000c4 Code RO 861 i.uf_SPI2_Init spi.o + 0x08015e9c 0x08015e9c 0x00000060 Code RO 685 i.uf_TIM3_Init tim.o + 0x08015efc 0x08015efc 0x000000bc Code RO 731 i.uf_UART1_Init uart.o + 0x08015fb8 0x08015fb8 0x000000ac Code RO 732 i.uf_UART2_Init uart.o + 0x08016064 0x08016064 0x000000a8 Code RO 733 i.uf_UART3_Init uart.o + 0x0801610c 0x0801610c 0x000000a8 Code RO 734 i.uf_UART4_Init uart.o + 0x080161b4 0x080161b4 0x0000002c Code RO 5759 locale$$code c_w.l(lc_numeric_c.o) + 0x080161e0 0x080161e0 0x0000002c Code RO 5776 locale$$code c_w.l(lc_ctype_c.o) + 0x0801620c 0x0801620c 0x00000150 Code RO 5492 x$fpl$dadd fz_ws.l(daddsub_clz.o) + 0x0801635c 0x0801635c 0x000002b0 Code RO 5499 x$fpl$ddiv fz_ws.l(ddiv.o) + 0x0801660c 0x0801660c 0x0000005e Code RO 5502 x$fpl$dfix fz_ws.l(dfix.o) + 0x0801666a 0x0801666a 0x00000002 PAD + 0x0801666c 0x0801666c 0x0000005a Code RO 5506 x$fpl$dfixu fz_ws.l(dfixu.o) + 0x080166c6 0x080166c6 0x00000026 Code RO 5510 x$fpl$dfltu fz_ws.l(dflt_clz.o) + 0x080166ec 0x080166ec 0x00000154 Code RO 5518 x$fpl$dmul fz_ws.l(dmul.o) + 0x08016840 0x08016840 0x0000009c Code RO 5629 x$fpl$dnaninf fz_ws.l(dnaninf.o) + 0x080168dc 0x080168dc 0x0000000c Code RO 5631 x$fpl$dretinf fz_ws.l(dretinf.o) + 0x080168e8 0x080168e8 0x000001d4 Code RO 5494 x$fpl$dsub fz_ws.l(daddsub_clz.o) + 0x08016abc 0x08016abc 0x00000056 Code RO 5522 x$fpl$f2d fz_ws.l(f2d.o) + 0x08016b12 0x08016b12 0x00000002 PAD + 0x08016b14 0x08016b14 0x000000c4 Code RO 5524 x$fpl$fadd fz_ws.l(faddsub_clz.o) + 0x08016bd8 0x08016bd8 0x00000184 Code RO 5531 x$fpl$fdiv fz_ws.l(fdiv.o) + 0x08016d5c 0x08016d5c 0x0000003e Code RO 5534 x$fpl$ffixu fz_ws.l(ffixu.o) + 0x08016d9a 0x08016d9a 0x00000002 PAD + 0x08016d9c 0x08016d9c 0x00000030 Code RO 5539 x$fpl$fflt fz_ws.l(fflt_clz.o) + 0x08016dcc 0x08016dcc 0x00000026 Code RO 5538 x$fpl$ffltu fz_ws.l(fflt_clz.o) + 0x08016df2 0x08016df2 0x00000002 PAD + 0x08016df4 0x08016df4 0x00000102 Code RO 5544 x$fpl$fmul fz_ws.l(fmul.o) + 0x08016ef6 0x08016ef6 0x0000008c Code RO 5635 x$fpl$fnaninf fz_ws.l(fnaninf.o) + 0x08016f82 0x08016f82 0x0000000a Code RO 5637 x$fpl$fretinf fz_ws.l(fretinf.o) + 0x08016f8c 0x08016f8c 0x000000ea Code RO 5526 x$fpl$fsub fz_ws.l(faddsub_clz.o) + 0x08017076 0x08017076 0x00000004 Code RO 5639 x$fpl$printf1 fz_ws.l(printf1.o) + 0x0801707a 0x0801707a 0x00000004 Code RO 5641 x$fpl$printf2 fz_ws.l(printf2.o) + 0x0801707e 0x0801707e 0x00000000 Code RO 5647 x$fpl$usenofp fz_ws.l(usenofp.o) + 0x0801707e 0x0801707e 0x00000100 Data RO 166 .constdata global.o + 0x0801717e 0x0801717e 0x00000018 Data RO 956 .constdata rtc.o + 0x08017196 0x08017196 0x00000200 Data RO 1318 .constdata rs485_modbus.o + 0x08017396 0x08017396 0x000002b6 Data RO 1579 .constdata ntc.o + 0x0801764c 0x0801764c 0x0000000a Data RO 1923 .constdata status.o + 0x08017656 0x08017656 0x00000028 Data RO 5435 .constdata c_w.l(_printf_hex_int_ll_ptr.o) + 0x0801767e 0x0801767e 0x00000011 Data RO 5455 .constdata c_w.l(__printf_flags_ss_wp.o) + 0x0801768f 0x0801768f 0x00000001 PAD + 0x08017690 0x08017690 0x00000008 Data RO 5590 .constdata c_w.l(_printf_wctomb.o) + 0x08017698 0x08017698 0x00000026 Data RO 5703 .constdata c_w.l(_printf_fp_hex.o) + 0x080176be 0x080176be 0x00000002 PAD + 0x080176c0 0x080176c0 0x00000094 Data RO 5734 .constdata c_w.l(bigflt0.o) + 0x08017754 0x08017754 0x0000000d Data RO 2114 .conststring mbo26a.o + 0x08017761 0x08017761 0x00000003 PAD + 0x08017764 0x08017764 0x00000020 Data RO 5902 Region$$Table anon$$obj.o + 0x08017784 0x08017784 0x0000001c Data RO 5758 locale$$data c_w.l(lc_numeric_c.o) + 0x080177a0 0x080177a0 0x00000110 Data RO 5775 locale$$data c_w.l(lc_ctype_c.o) + + + Execution Region RW_IRAM1 (Exec base: 0x20000000, Load base: 0x080178b0, Size: 0x000023b8, Max: 0x0000c000, ABSOLUTE, COMPRESSED[0x000001dc]) + + Exec Addr Load Addr Size Type Attr Idx E Section Name Object + + 0x20000000 COMPRESSED 0x00000020 Data RW 172 .data global.o + 0x20000020 COMPRESSED 0x00000018 Data RW 452 .data gpio.o + 0x20000038 COMPRESSED 0x00000001 Data RW 455 .data gpio.o + 0x20000039 COMPRESSED 0x00000003 PAD + 0x2000003c COMPRESSED 0x00000004 Data RW 687 .data tim.o + 0x20000040 COMPRESSED 0x00000008 Data RW 735 .data uart.o + 0x20000048 COMPRESSED 0x00000001 Data RW 736 .data uart.o + 0x20000049 COMPRESSED 0x00000003 PAD + 0x2000004c COMPRESSED 0x0000000c Data RW 806 .data i2c.o + 0x20000058 COMPRESSED 0x00000051 Data RW 957 .data rtc.o + 0x200000a9 COMPRESSED 0x00000001 PAD + 0x200000aa COMPRESSED 0x00000004 Data RW 1038 .data can.o + 0x200000ae COMPRESSED 0x00000002 PAD + 0x200000b0 COMPRESSED 0x00000010 Data RW 1080 .data adc.o + 0x200000c0 COMPRESSED 0x00000010 Data RW 1119 .data pwm.o + 0x200000d0 COMPRESSED 0x0000003e Data RW 1195 .data afe_sh3673520.o + 0x2000010e COMPRESSED 0x00000026 Data RW 1319 .data rs485_modbus.o + 0x20000134 COMPRESSED 0x00000001 Data RW 1320 .data rs485_modbus.o + 0x20000135 COMPRESSED 0x00000001 Data RW 1321 .data rs485_modbus.o + 0x20000136 COMPRESSED 0x00000001 Data RW 1322 .data rs485_modbus.o + 0x20000137 COMPRESSED 0x00000001 PAD + 0x20000138 COMPRESSED 0x00000002 Data RW 1323 .data rs485_modbus.o + 0x2000013a COMPRESSED 0x00000001 Data RW 1324 .data rs485_modbus.o + 0x2000013b COMPRESSED 0x00000001 Data RW 1325 .data rs485_modbus.o + 0x2000013c COMPRESSED 0x00000001 Data RW 1479 .data rs485_modbus_inverter.o + 0x2000013d COMPRESSED 0x00000001 PAD + 0x2000013e COMPRESSED 0x000001bc Data RW 1480 .data rs485_modbus_inverter.o + 0x200002fa COMPRESSED 0x00000001 Data RW 1580 .data ntc.o + 0x200002fb COMPRESSED 0x00000001 PAD + 0x200002fc COMPRESSED 0x0000021e Data RW 1634 .data screen.o + 0x2000051a COMPRESSED 0x00000001 Data RW 1648 .data screen.o + 0x2000051b COMPRESSED 0x00000001 Data RW 1649 .data screen.o + 0x2000051c COMPRESSED 0x00000001 Data RW 1650 .data screen.o + 0x2000051d COMPRESSED 0x00000003 PAD + 0x20000520 COMPRESSED 0x00000038 Data RW 1806 .data gasgauge.o + 0x20000558 COMPRESSED 0x00000006 Data RW 1866 .data ocv.o + 0x2000055e COMPRESSED 0x00000062 Data RW 1924 .data status.o + 0x200005c0 COMPRESSED 0x00000064 Data RW 2115 .data mbo26a.o + 0x20000624 COMPRESSED 0x00000014 Data RW 3869 .data stm32f10x_rcc.o + 0x20000638 COMPRESSED 0x00000001 Data RW 5238 .data protocolswitch_p1.o + 0x20000639 COMPRESSED 0x00000003 PAD + 0x2000063c - 0x000002b8 Zero RW 160 .bss global.o + 0x200008f4 - 0x000000e4 Zero RW 161 .bss global.o + 0x200009d8 - 0x000000f0 Zero RW 163 .bss global.o + 0x20000ac8 - 0x00000122 Zero RW 165 .bss global.o + 0x20000bea COMPRESSED 0x00000002 PAD + 0x20000bec - 0x00000050 Zero RW 686 .bss tim.o + 0x20000c3c - 0x000001b8 Zero RW 1036 .bss can.o + 0x20000df4 - 0x00000478 Zero RW 1037 .bss can.o + 0x2000126c - 0x0000009a Zero RW 1194 .bss afe_sh3673520.o + 0x20001306 - 0x000000dc Zero RW 1317 .bss rs485_modbus.o + 0x200013e2 - 0x000000dc Zero RW 1478 .bss rs485_modbus_inverter.o + 0x200014be - 0x00000180 Zero RW 1630 .bss screen.o + 0x2000163e COMPRESSED 0x00000002 PAD + 0x20001640 - 0x00000064 Zero RW 1845 .bss soe.o + 0x200016a4 - 0x00000078 Zero RW 1865 .bss ocv.o + 0x2000171c - 0x00000639 Zero RW 2110 .bss mbo26a.o + 0x20001d55 COMPRESSED 0x00000003 PAD + 0x20001d58 - 0x00000060 Zero RW 5720 .bss c_w.l(libspace.o) + 0x20001db8 - 0x00000200 Zero RW 18 HEAP startup_stm32f10x_hd.o + 0x20001fb8 - 0x00000400 Zero RW 17 STACK startup_stm32f10x_hd.o + + +============================================================================== + +Image component sizes + + + Code (inc. data) RO Data RW Data ZI Data Debug Object Name + + 712 40 0 16 0 3742 adc.o + 4664 190 0 62 154 42676 afe_sh3673520.o + 628 64 0 4 1584 26511 can.o + 0 0 0 0 0 4548 core_cm3.o + 398 38 4096 0 0 6091 flash.o + 1956 118 0 56 0 5921 gasgauge.o + 4058 420 256 32 1454 39318 global.o + 1608 210 0 25 0 245541 gpio.o + 1826 68 0 12 0 8516 i2c.o + 800 80 0 0 0 280199 main.o + 6958 2544 13 100 1593 19687 mbo26a.o + 120 16 0 0 0 1931 misc.o + 264 20 694 1 0 2672 ntc.o + 828 68 0 6 120 25570 ocv.o + 5242 318 0 1 0 12324 protocolswitch_p1.o + 900 60 0 0 0 1549 protocolswitch_p2.o + 748 102 0 16 0 4884 pwm.o + 5284 458 512 45 220 46809 rs485_modbus.o + 5956 348 0 445 220 56712 rs485_modbus_inverter.o + 2364 118 24 81 0 9856 rtc.o + 18474 7120 0 545 384 33660 screen.o + 1076 28 0 0 100 3363 soe.o + 812 36 0 0 0 5061 spi.o + 64 26 304 0 1536 908 startup_stm32f10x_hd.o + 5478 398 10 98 0 28311 status.o + 364 22 0 0 0 10390 stm32f10x_adc.o + 50 8 0 0 0 3240 stm32f10x_bkp.o + 1124 42 0 0 0 9437 stm32f10x_can.o + 240 36 0 0 0 6837 stm32f10x_flash.o + 272 6 0 0 0 5222 stm32f10x_gpio.o + 404 16 0 0 0 10065 stm32f10x_i2c.o + 44 8 0 0 0 20241 stm32f10x_it.o + 68 30 0 0 0 3194 stm32f10x_iwdg.o + 12 6 0 0 0 654 stm32f10x_pwr.o + 380 72 0 20 0 10815 stm32f10x_rcc.o + 192 40 0 0 0 5940 stm32f10x_rtc.o + 182 12 0 0 0 5515 stm32f10x_spi.o + 394 52 0 0 0 9653 stm32f10x_tim.o + 332 6 0 0 0 7377 stm32f10x_usart.o + 248 24 0 0 0 1877 system_stm32f10x.o + 138 6 0 0 0 1882 systick.o + 444 74 0 4 80 3627 tim.o + 976 80 0 9 0 8660 uart.o + 42 0 0 0 0 1243 wdg.o + + ---------------------------------------------------------------------- + 77158 13428 5944 1596 7452 1042229 Object Totals + 0 0 32 0 0 0 (incl. Generated) + 34 0 3 18 7 0 (incl. Padding) + + ---------------------------------------------------------------------- + + Code (inc. data) RO Data RW Data ZI Data Debug Library Member Name + + 60 8 0 0 0 84 __0sscanf.o + 44 6 0 0 0 84 __2sprintf.o + 90 0 0 0 0 0 __dczerorl2.o + 8 0 0 0 0 68 __main.o + 392 4 17 0 0 92 __printf_flags_ss_wp.o + 14 0 0 0 0 68 __printf_wp.o + 0 0 0 0 0 0 __rtentry.o + 12 0 0 0 0 0 __rtentry2.o + 6 0 0 0 0 0 __rtentry4.o + 52 8 0 0 0 0 __scatter.o + 28 0 0 0 0 0 __scatter_zi.o + 28 0 0 0 0 68 _chval.o + 6 0 0 0 0 0 _printf_a.o + 6 0 0 0 0 0 _printf_c.o + 44 0 0 0 0 108 _printf_char.o + 48 6 0 0 0 96 _printf_char_common.o + 40 0 0 0 0 68 _printf_charcount.o + 6 0 0 0 0 0 _printf_d.o + 120 16 0 0 0 92 _printf_dec.o + 6 0 0 0 0 0 _printf_e.o + 6 0 0 0 0 0 _printf_f.o + 1054 0 0 0 0 216 _printf_fp_dec.o + 764 8 38 0 0 100 _printf_fp_hex.o + 128 16 0 0 0 84 _printf_fp_infnan.o + 6 0 0 0 0 0 _printf_g.o + 148 4 40 0 0 160 _printf_hex_int_ll_ptr.o + 6 0 0 0 0 0 _printf_i.o + 178 0 0 0 0 88 _printf_intcommon.o + 10 0 0 0 0 0 _printf_l.o + 6 0 0 0 0 0 _printf_lc.o + 10 0 0 0 0 0 _printf_ll.o + 6 0 0 0 0 0 _printf_lld.o + 6 0 0 0 0 0 _printf_lli.o + 6 0 0 0 0 0 _printf_llo.o + 6 0 0 0 0 0 _printf_llu.o + 6 0 0 0 0 0 _printf_llx.o + 124 16 0 0 0 92 _printf_longlong_dec.o + 6 0 0 0 0 0 _printf_ls.o + 6 0 0 0 0 0 _printf_n.o + 6 0 0 0 0 0 _printf_o.o + 112 10 0 0 0 124 _printf_oct_int_ll.o + 6 0 0 0 0 0 _printf_p.o + 78 0 0 0 0 108 _printf_pad.o + 0 0 0 0 0 0 _printf_percent.o + 4 0 0 0 0 0 _printf_percent_end.o + 6 0 0 0 0 0 _printf_s.o + 82 0 0 0 0 80 _printf_str.o + 36 0 0 0 0 84 _printf_truncate.o + 6 0 0 0 0 0 _printf_u.o + 44 0 0 0 0 108 _printf_wchar.o + 188 6 8 0 0 92 _printf_wctomb.o + 6 0 0 0 0 0 _printf_x.o + 884 6 0 0 0 100 _scanf.o + 332 0 0 0 0 96 _scanf_int.o + 64 0 0 0 0 84 _sgetc.o + 16 0 0 0 0 68 _snputc.o + 10 0 0 0 0 68 _sputc.o + 64 0 0 0 0 92 _wcrtomb.o + 16 0 0 0 0 68 aeabi_memset.o + 228 4 148 0 0 96 bigflt0.o + 1936 128 0 0 0 672 btod.o + 18 0 0 0 0 80 exit.o + 6 0 0 0 0 152 heapauxi.o + 0 0 0 0 0 0 indicate_semi.o + 18 0 0 0 0 76 isspace.o + 44 10 272 0 0 76 lc_ctype_c.o + 44 10 28 0 0 76 lc_numeric_c.o + 2 0 0 0 0 0 libinit.o + 30 0 0 0 0 0 libinit2.o + 2 0 0 0 0 0 libshutdown.o + 2 0 0 0 0 0 libshutdown2.o + 8 4 0 0 96 68 libspace.o + 138 0 0 0 0 80 lludiv10.o + 88 0 0 0 0 76 memcmp.o + 16 4 0 0 0 76 rt_ctype_table.o + 8 4 0 0 0 68 rt_locale_intlibspace.o + 68 0 0 0 0 68 rt_memclr.o + 78 0 0 0 0 80 rt_memclr_w.o + 138 0 0 0 0 68 rt_memcpy_v6.o + 100 0 0 0 0 80 rt_memcpy_w.o + 2 0 0 0 0 0 rtexit.o + 10 0 0 0 0 0 rtexit2.o + 44 8 0 0 0 84 scanf_char.o + 20 0 0 0 0 68 strchr.o + 128 0 0 0 0 68 strcmpv7m.o + 72 0 0 0 0 80 strcpy.o + 62 0 0 0 0 76 strlen.o + 86 0 0 0 0 76 strncpy.o + 36 0 0 0 0 80 strstr.o + 12 4 0 0 0 68 sys_exit.o + 74 0 0 0 0 80 sys_stackheap_outer.o + 2 0 0 0 0 68 use_no_semi.o + 52 4 0 0 0 80 vsnprintf.o + 804 16 0 0 0 272 daddsub_clz.o + 688 140 0 0 0 208 ddiv.o + 94 4 0 0 0 92 dfix.o + 90 4 0 0 0 92 dfixu.o + 38 0 0 0 0 68 dflt_clz.o + 340 12 0 0 0 104 dmul.o + 156 4 0 0 0 92 dnaninf.o + 12 0 0 0 0 68 dretinf.o + 86 4 0 0 0 84 f2d.o + 430 8 0 0 0 168 faddsub_clz.o + 388 76 0 0 0 96 fdiv.o + 62 4 0 0 0 84 ffixu.o + 86 0 0 0 0 136 fflt_clz.o + 258 4 0 0 0 84 fmul.o + 140 4 0 0 0 84 fnaninf.o + 10 0 0 0 0 68 fretinf.o + 4 0 0 0 0 68 printf1.o + 4 0 0 0 0 68 printf2.o + 0 0 0 0 0 0 usenofp.o + 40 0 0 0 0 68 fpclassify.o + + ---------------------------------------------------------------------- + 12776 574 554 0 96 7464 Library Totals + 22 0 3 0 0 0 (incl. Padding) + + ---------------------------------------------------------------------- + + Code (inc. data) RO Data RW Data ZI Data Debug Library Name + + 9024 294 551 0 96 5460 c_w.l + 3690 280 0 0 0 1936 fz_ws.l + 40 0 0 0 0 68 m_ws.l + + ---------------------------------------------------------------------- + 12776 574 554 0 96 7464 Library Totals + + ---------------------------------------------------------------------- + +============================================================================== + + + Code (inc. data) RO Data RW Data ZI Data Debug + + 89934 14002 6498 1596 7548 1027069 Grand Totals + 89934 14002 6498 476 7548 1027069 ELF Image Totals (compressed) + 89934 14002 6498 476 0 0 ROM Totals + +============================================================================== + + Total RO Size (Code + RO Data) 96432 ( 94.17kB) + Total RW Size (RW Data + ZI Data) 9144 ( 8.93kB) + Total ROM Size (Code + RO Data + RW Data) 96908 ( 94.64kB) + +============================================================================== + diff --git a/USER/Listings/startup_stm32f10x_hd.lst b/USER/Listings/startup_stm32f10x_hd.lst new file mode 100644 index 0000000..07f133c --- /dev/null +++ b/USER/Listings/startup_stm32f10x_hd.lst @@ -0,0 +1,1466 @@ + + + +ARM Macro Assembler Page 1 + + + 1 00000000 ;******************** (C) COPYRIGHT 2011 STMicroelectron + ics ******************** + 2 00000000 ;* File Name : startup_stm32f10x_hd.s + 3 00000000 ;* Author : MCD Application Team + 4 00000000 ;* Version : V3.5.1 + 5 00000000 ;* Date : 08-September-2021 + 6 00000000 ;* Description : STM32F10x High Density Devices v + ector table for MDK-ARM + 7 00000000 ;* toolchain. + 8 00000000 ;* This module performs: + 9 00000000 ;* - Set the initial SP + 10 00000000 ;* - Set the initial PC == Reset_Ha + ndler + 11 00000000 ;* - Set the vector table entries w + ith the exceptions ISR address + 12 00000000 ;* - Configure the clock system and + also configure the external + 13 00000000 ;* SRAM mounted on STM3210E-EVAL + board to be used as data + 14 00000000 ;* memory (optional, to be enable + d by user) + 15 00000000 ;* - Branches to __main in the C li + brary (which eventually + 16 00000000 ;* calls main()). + 17 00000000 ;* After Reset the CortexM3 process + or is in Thread mode, + 18 00000000 ;* priority is Privileged, and the + Stack is set to Main. + 19 00000000 ;* <<< Use Configuration Wizard in Context Menu >>> + 20 00000000 ;******************************************************* + ************************ + 21 00000000 ;* + 22 00000000 ;* Copyright (c) 2011 STMicroelectronics. + 23 00000000 ;* All rights reserved. + 24 00000000 ;* + 25 00000000 ;* This software is licensed under terms that can be fou + nd in the LICENSE file + 26 00000000 ;* in the root directory of this software component. + 27 00000000 ;* If no LICENSE file comes with this software, it is pr + ovided AS-IS. + 28 00000000 ; + 29 00000000 ;******************************************************* + ************************ + 30 00000000 + 31 00000000 ; Amount of memory (in bytes) allocated for Stack + 32 00000000 ; Tailor this value to your application needs + 33 00000000 ; Stack Configuration + 34 00000000 ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> + 35 00000000 ; + 36 00000000 + 37 00000000 00000400 + Stack_Size + EQU 0x00000400 + 38 00000000 + 39 00000000 AREA STACK, NOINIT, READWRITE, ALIGN +=3 + 40 00000000 Stack_Mem + SPACE Stack_Size + 41 00000400 __initial_sp + + + +ARM Macro Assembler Page 2 + + + 42 00000400 + 43 00000400 ; Heap Configuration + 44 00000400 ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> + 45 00000400 ; + 46 00000400 + 47 00000400 00000200 + Heap_Size + EQU 0x00000200 + 48 00000400 + 49 00000400 AREA HEAP, NOINIT, READWRITE, ALIGN= +3 + 50 00000000 __heap_base + 51 00000000 Heap_Mem + SPACE Heap_Size + 52 00000200 __heap_limit + 53 00000200 + 54 00000200 PRESERVE8 + 55 00000200 THUMB + 56 00000200 + 57 00000200 + 58 00000200 ; Vector Table Mapped to Address 0 at Reset + 59 00000200 AREA RESET, DATA, READONLY + 60 00000000 EXPORT __Vectors + 61 00000000 EXPORT __Vectors_End + 62 00000000 EXPORT __Vectors_Size + 63 00000000 + 64 00000000 00000000 + __Vectors + DCD __initial_sp ; Top of Stack + 65 00000004 00000000 DCD Reset_Handler ; Reset Handler + 66 00000008 00000000 DCD NMI_Handler ; NMI Handler + 67 0000000C 00000000 DCD HardFault_Handler ; Hard Fault + Handler + 68 00000010 00000000 DCD MemManage_Handler + ; MPU Fault Handler + + 69 00000014 00000000 DCD BusFault_Handler + ; Bus Fault Handler + + 70 00000018 00000000 DCD UsageFault_Handler ; Usage Faul + t Handler + 71 0000001C 00000000 DCD 0 ; Reserved + 72 00000020 00000000 DCD 0 ; Reserved + 73 00000024 00000000 DCD 0 ; Reserved + 74 00000028 00000000 DCD 0 ; Reserved + 75 0000002C 00000000 DCD SVC_Handler ; SVCall Handler + 76 00000030 00000000 DCD DebugMon_Handler ; Debug Monito + r Handler + 77 00000034 00000000 DCD 0 ; Reserved + 78 00000038 00000000 DCD PendSV_Handler ; PendSV Handler + + 79 0000003C 00000000 DCD SysTick_Handler + ; SysTick Handler + 80 00000040 + 81 00000040 ; External Interrupts + 82 00000040 00000000 DCD WWDG_IRQHandler + ; Window Watchdog + 83 00000044 00000000 DCD PVD_IRQHandler ; PVD through EX + TI Line detect + + + +ARM Macro Assembler Page 3 + + + 84 00000048 00000000 DCD TAMPER_IRQHandler ; Tamper + 85 0000004C 00000000 DCD RTC_IRQHandler ; RTC + 86 00000050 00000000 DCD FLASH_IRQHandler ; Flash + 87 00000054 00000000 DCD RCC_IRQHandler ; RCC + 88 00000058 00000000 DCD EXTI0_IRQHandler ; EXTI Line 0 + 89 0000005C 00000000 DCD EXTI1_IRQHandler ; EXTI Line 1 + 90 00000060 00000000 DCD EXTI2_IRQHandler ; EXTI Line 2 + 91 00000064 00000000 DCD EXTI3_IRQHandler ; EXTI Line 3 + 92 00000068 00000000 DCD EXTI4_IRQHandler ; EXTI Line 4 + 93 0000006C 00000000 DCD DMA1_Channel1_IRQHandler + ; DMA1 Channel 1 + 94 00000070 00000000 DCD DMA1_Channel2_IRQHandler + ; DMA1 Channel 2 + 95 00000074 00000000 DCD DMA1_Channel3_IRQHandler + ; DMA1 Channel 3 + 96 00000078 00000000 DCD DMA1_Channel4_IRQHandler + ; DMA1 Channel 4 + 97 0000007C 00000000 DCD DMA1_Channel5_IRQHandler + ; DMA1 Channel 5 + 98 00000080 00000000 DCD DMA1_Channel6_IRQHandler + ; DMA1 Channel 6 + 99 00000084 00000000 DCD DMA1_Channel7_IRQHandler + ; DMA1 Channel 7 + 100 00000088 00000000 DCD ADC1_2_IRQHandler ; ADC1 & ADC2 + + 101 0000008C 00000000 DCD USB_HP_CAN1_TX_IRQHandler ; USB + High Priority or C + AN1 TX + 102 00000090 00000000 DCD USB_LP_CAN1_RX0_IRQHandler ; US + B Low Priority or + CAN1 RX0 + 103 00000094 00000000 DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + 104 00000098 00000000 DCD CAN1_SCE_IRQHandler ; CAN1 SCE + 105 0000009C 00000000 DCD EXTI9_5_IRQHandler + ; EXTI Line 9..5 + 106 000000A0 00000000 DCD TIM1_BRK_IRQHandler + ; TIM1 Break + 107 000000A4 00000000 DCD TIM1_UP_IRQHandler + ; TIM1 Update + 108 000000A8 00000000 DCD TIM1_TRG_COM_IRQHandler ; TIM1 + Trigger and Commuta + tion + 109 000000AC 00000000 DCD TIM1_CC_IRQHandler ; TIM1 Captu + re Compare + 110 000000B0 00000000 DCD TIM2_IRQHandler ; TIM2 + 111 000000B4 00000000 DCD TIM3_IRQHandler ; TIM3 + 112 000000B8 00000000 DCD TIM4_IRQHandler ; TIM4 + 113 000000BC 00000000 DCD I2C1_EV_IRQHandler ; I2C1 Event + + 114 000000C0 00000000 DCD I2C1_ER_IRQHandler ; I2C1 Error + + 115 000000C4 00000000 DCD I2C2_EV_IRQHandler ; I2C2 Event + + 116 000000C8 00000000 DCD I2C2_ER_IRQHandler ; I2C2 Error + + 117 000000CC 00000000 DCD SPI1_IRQHandler ; SPI1 + 118 000000D0 00000000 DCD SPI2_IRQHandler ; SPI2 + 119 000000D4 00000000 DCD USART1_IRQHandler ; USART1 + 120 000000D8 00000000 DCD USART2_IRQHandler ; USART2 + + + +ARM Macro Assembler Page 4 + + + 121 000000DC 00000000 DCD USART3_IRQHandler ; USART3 + 122 000000E0 00000000 DCD EXTI15_10_IRQHandler + ; EXTI Line 15..10 + 123 000000E4 00000000 DCD RTCAlarm_IRQHandler ; RTC Alarm + through EXTI Line + 124 000000E8 00000000 DCD USBWakeUp_IRQHandler ; USB Wake + up from suspend + 125 000000EC 00000000 DCD TIM8_BRK_IRQHandler + ; TIM8 Break + 126 000000F0 00000000 DCD TIM8_UP_IRQHandler + ; TIM8 Update + 127 000000F4 00000000 DCD TIM8_TRG_COM_IRQHandler ; TIM8 + Trigger and Commuta + tion + 128 000000F8 00000000 DCD TIM8_CC_IRQHandler ; TIM8 Captu + re Compare + 129 000000FC 00000000 DCD ADC3_IRQHandler ; ADC3 + 130 00000100 00000000 DCD FSMC_IRQHandler ; FSMC + 131 00000104 00000000 DCD SDIO_IRQHandler ; SDIO + 132 00000108 00000000 DCD TIM5_IRQHandler ; TIM5 + 133 0000010C 00000000 DCD SPI3_IRQHandler ; SPI3 + 134 00000110 00000000 DCD UART4_IRQHandler ; UART4 + 135 00000114 00000000 DCD UART5_IRQHandler ; UART5 + 136 00000118 00000000 DCD TIM6_IRQHandler ; TIM6 + 137 0000011C 00000000 DCD TIM7_IRQHandler ; TIM7 + 138 00000120 00000000 DCD DMA2_Channel1_IRQHandler + ; DMA2 Channel1 + 139 00000124 00000000 DCD DMA2_Channel2_IRQHandler + ; DMA2 Channel2 + 140 00000128 00000000 DCD DMA2_Channel3_IRQHandler + ; DMA2 Channel3 + 141 0000012C 00000000 DCD DMA2_Channel4_5_IRQHandler ; DM + A2 Channel4 & Chann + el5 + 142 00000130 __Vectors_End + 143 00000130 + 144 00000130 00000130 + __Vectors_Size + EQU __Vectors_End - __Vectors + 145 00000130 + 146 00000130 AREA |.text|, CODE, READONLY + 147 00000000 + 148 00000000 ; Reset handler + 149 00000000 Reset_Handler + PROC + 150 00000000 EXPORT Reset_Handler [WEAK +] + 151 00000000 IMPORT __main + 152 00000000 IMPORT SystemInit + 153 00000000 4809 LDR R0, =SystemInit + 154 00000002 4780 BLX R0 + 155 00000004 4809 LDR R0, =__main + 156 00000006 4700 BX R0 + 157 00000008 ENDP + 158 00000008 + 159 00000008 ; Dummy Exception Handlers (infinite loops which can be + modified) + 160 00000008 + 161 00000008 NMI_Handler + + + +ARM Macro Assembler Page 5 + + + PROC + 162 00000008 EXPORT NMI_Handler [WEA +K] + 163 00000008 E7FE B . + 164 0000000A ENDP + 166 0000000A HardFault_Handler + PROC + 167 0000000A EXPORT HardFault_Handler [WEA +K] + 168 0000000A E7FE B . + 169 0000000C ENDP + 171 0000000C MemManage_Handler + PROC + 172 0000000C EXPORT MemManage_Handler [WEA +K] + 173 0000000C E7FE B . + 174 0000000E ENDP + 176 0000000E BusFault_Handler + PROC + 177 0000000E EXPORT BusFault_Handler [WEA +K] + 178 0000000E E7FE B . + 179 00000010 ENDP + 181 00000010 UsageFault_Handler + PROC + 182 00000010 EXPORT UsageFault_Handler [WEA +K] + 183 00000010 E7FE B . + 184 00000012 ENDP + 185 00000012 SVC_Handler + PROC + 186 00000012 EXPORT SVC_Handler [WEA +K] + 187 00000012 E7FE B . + 188 00000014 ENDP + 190 00000014 DebugMon_Handler + PROC + 191 00000014 EXPORT DebugMon_Handler [WEA +K] + 192 00000014 E7FE B . + 193 00000016 ENDP + 194 00000016 PendSV_Handler + PROC + 195 00000016 EXPORT PendSV_Handler [WEA +K] + 196 00000016 E7FE B . + 197 00000018 ENDP + 198 00000018 SysTick_Handler + PROC + 199 00000018 EXPORT SysTick_Handler [WEA +K] + 200 00000018 E7FE B . + 201 0000001A ENDP + 202 0000001A + 203 0000001A Default_Handler + PROC + 204 0000001A + 205 0000001A EXPORT WWDG_IRQHandler [WEA +K] + + + +ARM Macro Assembler Page 6 + + + 206 0000001A EXPORT PVD_IRQHandler [WEA +K] + 207 0000001A EXPORT TAMPER_IRQHandler [WEA +K] + 208 0000001A EXPORT RTC_IRQHandler [WEA +K] + 209 0000001A EXPORT FLASH_IRQHandler [WEA +K] + 210 0000001A EXPORT RCC_IRQHandler [WEA +K] + 211 0000001A EXPORT EXTI0_IRQHandler [WEA +K] + 212 0000001A EXPORT EXTI1_IRQHandler [WEA +K] + 213 0000001A EXPORT EXTI2_IRQHandler [WEA +K] + 214 0000001A EXPORT EXTI3_IRQHandler [WEA +K] + 215 0000001A EXPORT EXTI4_IRQHandler [WEA +K] + 216 0000001A EXPORT DMA1_Channel1_IRQHandler [WEA +K] + 217 0000001A EXPORT DMA1_Channel2_IRQHandler [WEA +K] + 218 0000001A EXPORT DMA1_Channel3_IRQHandler [WEA +K] + 219 0000001A EXPORT DMA1_Channel4_IRQHandler [WEA +K] + 220 0000001A EXPORT DMA1_Channel5_IRQHandler [WEA +K] + 221 0000001A EXPORT DMA1_Channel6_IRQHandler [WEA +K] + 222 0000001A EXPORT DMA1_Channel7_IRQHandler [WEA +K] + 223 0000001A EXPORT ADC1_2_IRQHandler [WEA +K] + 224 0000001A EXPORT USB_HP_CAN1_TX_IRQHandler [WEA +K] + 225 0000001A EXPORT USB_LP_CAN1_RX0_IRQHandler [WEA +K] + 226 0000001A EXPORT CAN1_RX1_IRQHandler [WEA +K] + 227 0000001A EXPORT CAN1_SCE_IRQHandler [WEA +K] + 228 0000001A EXPORT EXTI9_5_IRQHandler [WEA +K] + 229 0000001A EXPORT TIM1_BRK_IRQHandler [WEA +K] + 230 0000001A EXPORT TIM1_UP_IRQHandler [WEA +K] + 231 0000001A EXPORT TIM1_TRG_COM_IRQHandler [WEA +K] + 232 0000001A EXPORT TIM1_CC_IRQHandler [WEA +K] + 233 0000001A EXPORT TIM2_IRQHandler [WEA +K] + 234 0000001A EXPORT TIM3_IRQHandler [WEA +K] + 235 0000001A EXPORT TIM4_IRQHandler [WEA + + + +ARM Macro Assembler Page 7 + + +K] + 236 0000001A EXPORT I2C1_EV_IRQHandler [WEA +K] + 237 0000001A EXPORT I2C1_ER_IRQHandler [WEA +K] + 238 0000001A EXPORT I2C2_EV_IRQHandler [WEA +K] + 239 0000001A EXPORT I2C2_ER_IRQHandler [WEA +K] + 240 0000001A EXPORT SPI1_IRQHandler [WEA +K] + 241 0000001A EXPORT SPI2_IRQHandler [WEA +K] + 242 0000001A EXPORT USART1_IRQHandler [WEA +K] + 243 0000001A EXPORT USART2_IRQHandler [WEA +K] + 244 0000001A EXPORT USART3_IRQHandler [WEA +K] + 245 0000001A EXPORT EXTI15_10_IRQHandler [WEA +K] + 246 0000001A EXPORT RTCAlarm_IRQHandler [WEA +K] + 247 0000001A EXPORT USBWakeUp_IRQHandler [WEA +K] + 248 0000001A EXPORT TIM8_BRK_IRQHandler [WEA +K] + 249 0000001A EXPORT TIM8_UP_IRQHandler [WEA +K] + 250 0000001A EXPORT TIM8_TRG_COM_IRQHandler [WEA +K] + 251 0000001A EXPORT TIM8_CC_IRQHandler [WEA +K] + 252 0000001A EXPORT ADC3_IRQHandler [WEA +K] + 253 0000001A EXPORT FSMC_IRQHandler [WEA +K] + 254 0000001A EXPORT SDIO_IRQHandler [WEA +K] + 255 0000001A EXPORT TIM5_IRQHandler [WEA +K] + 256 0000001A EXPORT SPI3_IRQHandler [WEA +K] + 257 0000001A EXPORT UART4_IRQHandler [WEA +K] + 258 0000001A EXPORT UART5_IRQHandler [WEA +K] + 259 0000001A EXPORT TIM6_IRQHandler [WEA +K] + 260 0000001A EXPORT TIM7_IRQHandler [WEA +K] + 261 0000001A EXPORT DMA2_Channel1_IRQHandler [WEA +K] + 262 0000001A EXPORT DMA2_Channel2_IRQHandler [WEA +K] + 263 0000001A EXPORT DMA2_Channel3_IRQHandler [WEA +K] + 264 0000001A EXPORT DMA2_Channel4_5_IRQHandler [WEA +K] + + + +ARM Macro Assembler Page 8 + + + 265 0000001A + 266 0000001A WWDG_IRQHandler + 267 0000001A PVD_IRQHandler + 268 0000001A TAMPER_IRQHandler + 269 0000001A RTC_IRQHandler + 270 0000001A FLASH_IRQHandler + 271 0000001A RCC_IRQHandler + 272 0000001A EXTI0_IRQHandler + 273 0000001A EXTI1_IRQHandler + 274 0000001A EXTI2_IRQHandler + 275 0000001A EXTI3_IRQHandler + 276 0000001A EXTI4_IRQHandler + 277 0000001A DMA1_Channel1_IRQHandler + 278 0000001A DMA1_Channel2_IRQHandler + 279 0000001A DMA1_Channel3_IRQHandler + 280 0000001A DMA1_Channel4_IRQHandler + 281 0000001A DMA1_Channel5_IRQHandler + 282 0000001A DMA1_Channel6_IRQHandler + 283 0000001A DMA1_Channel7_IRQHandler + 284 0000001A ADC1_2_IRQHandler + 285 0000001A USB_HP_CAN1_TX_IRQHandler + 286 0000001A USB_LP_CAN1_RX0_IRQHandler + 287 0000001A CAN1_RX1_IRQHandler + 288 0000001A CAN1_SCE_IRQHandler + 289 0000001A EXTI9_5_IRQHandler + 290 0000001A TIM1_BRK_IRQHandler + 291 0000001A TIM1_UP_IRQHandler + 292 0000001A TIM1_TRG_COM_IRQHandler + 293 0000001A TIM1_CC_IRQHandler + 294 0000001A TIM2_IRQHandler + 295 0000001A TIM3_IRQHandler + 296 0000001A TIM4_IRQHandler + 297 0000001A I2C1_EV_IRQHandler + 298 0000001A I2C1_ER_IRQHandler + 299 0000001A I2C2_EV_IRQHandler + 300 0000001A I2C2_ER_IRQHandler + 301 0000001A SPI1_IRQHandler + 302 0000001A SPI2_IRQHandler + 303 0000001A USART1_IRQHandler + 304 0000001A USART2_IRQHandler + 305 0000001A USART3_IRQHandler + 306 0000001A EXTI15_10_IRQHandler + 307 0000001A RTCAlarm_IRQHandler + 308 0000001A USBWakeUp_IRQHandler + 309 0000001A TIM8_BRK_IRQHandler + 310 0000001A TIM8_UP_IRQHandler + 311 0000001A TIM8_TRG_COM_IRQHandler + 312 0000001A TIM8_CC_IRQHandler + 313 0000001A ADC3_IRQHandler + 314 0000001A FSMC_IRQHandler + 315 0000001A SDIO_IRQHandler + 316 0000001A TIM5_IRQHandler + 317 0000001A SPI3_IRQHandler + 318 0000001A UART4_IRQHandler + 319 0000001A UART5_IRQHandler + 320 0000001A TIM6_IRQHandler + 321 0000001A TIM7_IRQHandler + 322 0000001A DMA2_Channel1_IRQHandler + 323 0000001A DMA2_Channel2_IRQHandler + + + +ARM Macro Assembler Page 9 + + + 324 0000001A DMA2_Channel3_IRQHandler + 325 0000001A DMA2_Channel4_5_IRQHandler + 326 0000001A E7FE B . + 327 0000001C + 328 0000001C ENDP + 329 0000001C + 330 0000001C ALIGN + 331 0000001C + 332 0000001C ;******************************************************* + ************************ + 333 0000001C ; User Stack and Heap initialization + 334 0000001C ;******************************************************* + ************************ + 335 0000001C IF :DEF:__MICROLIB + 342 0000001C + 343 0000001C IMPORT __use_two_region_memory + 344 0000001C EXPORT __user_initial_stackheap + 345 0000001C + 346 0000001C __user_initial_stackheap + 347 0000001C + 348 0000001C 4804 LDR R0, = Heap_Mem + 349 0000001E 4905 LDR R1, =(Stack_Mem + Stack_Size) + 350 00000020 4A05 LDR R2, = (Heap_Mem + Heap_Size) + 351 00000022 4B06 LDR R3, = Stack_Mem + 352 00000024 4770 BX LR + 353 00000026 + 354 00000026 00 00 ALIGN + 355 00000028 + 356 00000028 ENDIF + 357 00000028 + 358 00000028 END + 00000000 + 00000000 + 00000000 + 00000400 + 00000200 + 00000000 +Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M3 --apcs=interw +ork --depend=..\obj\startup_stm32f10x_hd.d -o..\obj\startup_stm32f10x_hd.o -I.\ +RTE\_Target_1 -IE:\keil_v5_old\ARM\PACK\Keil\STM32F1xx_DFP\2.3.0\Device\Include + -IE:\keil_v5_old\ARM\CMSIS\Include --predefine="__UVISION_VERSION SETA 525" -- +predefine="STM32F10X_HD SETA 1" --list=.\listings\startup_stm32f10x_hd.lst ..\C +ORE\startup_stm32f10x_hd.s + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +STACK 00000000 + +Symbol: STACK + Definitions + At line 39 in file ..\CORE\startup_stm32f10x_hd.s + Uses + None +Comment: STACK unused +Stack_Mem 00000000 + +Symbol: Stack_Mem + Definitions + At line 40 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 349 in file ..\CORE\startup_stm32f10x_hd.s + At line 351 in file ..\CORE\startup_stm32f10x_hd.s + +__initial_sp 00000400 + +Symbol: __initial_sp + Definitions + At line 41 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 64 in file ..\CORE\startup_stm32f10x_hd.s +Comment: __initial_sp used once +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +HEAP 00000000 + +Symbol: HEAP + Definitions + At line 49 in file ..\CORE\startup_stm32f10x_hd.s + Uses + None +Comment: HEAP unused +Heap_Mem 00000000 + +Symbol: Heap_Mem + Definitions + At line 51 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 348 in file ..\CORE\startup_stm32f10x_hd.s + At line 350 in file ..\CORE\startup_stm32f10x_hd.s + +__heap_base 00000000 + +Symbol: __heap_base + Definitions + At line 50 in file ..\CORE\startup_stm32f10x_hd.s + Uses + None +Comment: __heap_base unused +__heap_limit 00000200 + +Symbol: __heap_limit + Definitions + At line 52 in file ..\CORE\startup_stm32f10x_hd.s + Uses + None +Comment: __heap_limit unused +4 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +RESET 00000000 + +Symbol: RESET + Definitions + At line 59 in file ..\CORE\startup_stm32f10x_hd.s + Uses + None +Comment: RESET unused +__Vectors 00000000 + +Symbol: __Vectors + Definitions + At line 64 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 60 in file ..\CORE\startup_stm32f10x_hd.s + At line 144 in file ..\CORE\startup_stm32f10x_hd.s + +__Vectors_End 00000130 + +Symbol: __Vectors_End + Definitions + At line 142 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 61 in file ..\CORE\startup_stm32f10x_hd.s + At line 144 in file ..\CORE\startup_stm32f10x_hd.s + +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +.text 00000000 + +Symbol: .text + Definitions + At line 146 in file ..\CORE\startup_stm32f10x_hd.s + Uses + None +Comment: .text unused +ADC1_2_IRQHandler 0000001A + +Symbol: ADC1_2_IRQHandler + Definitions + At line 284 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 100 in file ..\CORE\startup_stm32f10x_hd.s + At line 223 in file ..\CORE\startup_stm32f10x_hd.s + +ADC3_IRQHandler 0000001A + +Symbol: ADC3_IRQHandler + Definitions + At line 313 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 129 in file ..\CORE\startup_stm32f10x_hd.s + At line 252 in file ..\CORE\startup_stm32f10x_hd.s + +BusFault_Handler 0000000E + +Symbol: BusFault_Handler + Definitions + At line 176 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 69 in file ..\CORE\startup_stm32f10x_hd.s + At line 177 in file ..\CORE\startup_stm32f10x_hd.s + +CAN1_RX1_IRQHandler 0000001A + +Symbol: CAN1_RX1_IRQHandler + Definitions + At line 287 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 103 in file ..\CORE\startup_stm32f10x_hd.s + At line 226 in file ..\CORE\startup_stm32f10x_hd.s + +CAN1_SCE_IRQHandler 0000001A + +Symbol: CAN1_SCE_IRQHandler + Definitions + At line 288 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 104 in file ..\CORE\startup_stm32f10x_hd.s + At line 227 in file ..\CORE\startup_stm32f10x_hd.s + +DMA1_Channel1_IRQHandler 0000001A + +Symbol: DMA1_Channel1_IRQHandler + Definitions + At line 277 in file ..\CORE\startup_stm32f10x_hd.s + Uses + + + +ARM Macro Assembler Page 2 Alphabetic symbol ordering +Relocatable symbols + + At line 93 in file ..\CORE\startup_stm32f10x_hd.s + At line 216 in file ..\CORE\startup_stm32f10x_hd.s + +DMA1_Channel2_IRQHandler 0000001A + +Symbol: DMA1_Channel2_IRQHandler + Definitions + At line 278 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 94 in file ..\CORE\startup_stm32f10x_hd.s + At line 217 in file ..\CORE\startup_stm32f10x_hd.s + +DMA1_Channel3_IRQHandler 0000001A + +Symbol: DMA1_Channel3_IRQHandler + Definitions + At line 279 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 95 in file ..\CORE\startup_stm32f10x_hd.s + At line 218 in file ..\CORE\startup_stm32f10x_hd.s + +DMA1_Channel4_IRQHandler 0000001A + +Symbol: DMA1_Channel4_IRQHandler + Definitions + At line 280 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 96 in file ..\CORE\startup_stm32f10x_hd.s + At line 219 in file ..\CORE\startup_stm32f10x_hd.s + +DMA1_Channel5_IRQHandler 0000001A + +Symbol: DMA1_Channel5_IRQHandler + Definitions + At line 281 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 97 in file ..\CORE\startup_stm32f10x_hd.s + At line 220 in file ..\CORE\startup_stm32f10x_hd.s + +DMA1_Channel6_IRQHandler 0000001A + +Symbol: DMA1_Channel6_IRQHandler + Definitions + At line 282 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 98 in file ..\CORE\startup_stm32f10x_hd.s + At line 221 in file ..\CORE\startup_stm32f10x_hd.s + +DMA1_Channel7_IRQHandler 0000001A + +Symbol: DMA1_Channel7_IRQHandler + Definitions + At line 283 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 99 in file ..\CORE\startup_stm32f10x_hd.s + At line 222 in file ..\CORE\startup_stm32f10x_hd.s + +DMA2_Channel1_IRQHandler 0000001A + + + + +ARM Macro Assembler Page 3 Alphabetic symbol ordering +Relocatable symbols + +Symbol: DMA2_Channel1_IRQHandler + Definitions + At line 322 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 138 in file ..\CORE\startup_stm32f10x_hd.s + At line 261 in file ..\CORE\startup_stm32f10x_hd.s + +DMA2_Channel2_IRQHandler 0000001A + +Symbol: DMA2_Channel2_IRQHandler + Definitions + At line 323 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 139 in file ..\CORE\startup_stm32f10x_hd.s + At line 262 in file ..\CORE\startup_stm32f10x_hd.s + +DMA2_Channel3_IRQHandler 0000001A + +Symbol: DMA2_Channel3_IRQHandler + Definitions + At line 324 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 140 in file ..\CORE\startup_stm32f10x_hd.s + At line 263 in file ..\CORE\startup_stm32f10x_hd.s + +DMA2_Channel4_5_IRQHandler 0000001A + +Symbol: DMA2_Channel4_5_IRQHandler + Definitions + At line 325 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 141 in file ..\CORE\startup_stm32f10x_hd.s + At line 264 in file ..\CORE\startup_stm32f10x_hd.s + +DebugMon_Handler 00000014 + +Symbol: DebugMon_Handler + Definitions + At line 190 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 76 in file ..\CORE\startup_stm32f10x_hd.s + At line 191 in file ..\CORE\startup_stm32f10x_hd.s + +Default_Handler 0000001A + +Symbol: Default_Handler + Definitions + At line 203 in file ..\CORE\startup_stm32f10x_hd.s + Uses + None +Comment: Default_Handler unused +EXTI0_IRQHandler 0000001A + +Symbol: EXTI0_IRQHandler + Definitions + At line 272 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 88 in file ..\CORE\startup_stm32f10x_hd.s + At line 211 in file ..\CORE\startup_stm32f10x_hd.s + + + +ARM Macro Assembler Page 4 Alphabetic symbol ordering +Relocatable symbols + + +EXTI15_10_IRQHandler 0000001A + +Symbol: EXTI15_10_IRQHandler + Definitions + At line 306 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 122 in file ..\CORE\startup_stm32f10x_hd.s + At line 245 in file ..\CORE\startup_stm32f10x_hd.s + +EXTI1_IRQHandler 0000001A + +Symbol: EXTI1_IRQHandler + Definitions + At line 273 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 89 in file ..\CORE\startup_stm32f10x_hd.s + At line 212 in file ..\CORE\startup_stm32f10x_hd.s + +EXTI2_IRQHandler 0000001A + +Symbol: EXTI2_IRQHandler + Definitions + At line 274 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 90 in file ..\CORE\startup_stm32f10x_hd.s + At line 213 in file ..\CORE\startup_stm32f10x_hd.s + +EXTI3_IRQHandler 0000001A + +Symbol: EXTI3_IRQHandler + Definitions + At line 275 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 91 in file ..\CORE\startup_stm32f10x_hd.s + At line 214 in file ..\CORE\startup_stm32f10x_hd.s + +EXTI4_IRQHandler 0000001A + +Symbol: EXTI4_IRQHandler + Definitions + At line 276 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 92 in file ..\CORE\startup_stm32f10x_hd.s + At line 215 in file ..\CORE\startup_stm32f10x_hd.s + +EXTI9_5_IRQHandler 0000001A + +Symbol: EXTI9_5_IRQHandler + Definitions + At line 289 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 105 in file ..\CORE\startup_stm32f10x_hd.s + At line 228 in file ..\CORE\startup_stm32f10x_hd.s + +FLASH_IRQHandler 0000001A + +Symbol: FLASH_IRQHandler + Definitions + + + +ARM Macro Assembler Page 5 Alphabetic symbol ordering +Relocatable symbols + + At line 270 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 86 in file ..\CORE\startup_stm32f10x_hd.s + At line 209 in file ..\CORE\startup_stm32f10x_hd.s + +FSMC_IRQHandler 0000001A + +Symbol: FSMC_IRQHandler + Definitions + At line 314 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 130 in file ..\CORE\startup_stm32f10x_hd.s + At line 253 in file ..\CORE\startup_stm32f10x_hd.s + +HardFault_Handler 0000000A + +Symbol: HardFault_Handler + Definitions + At line 166 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 67 in file ..\CORE\startup_stm32f10x_hd.s + At line 167 in file ..\CORE\startup_stm32f10x_hd.s + +I2C1_ER_IRQHandler 0000001A + +Symbol: I2C1_ER_IRQHandler + Definitions + At line 298 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 114 in file ..\CORE\startup_stm32f10x_hd.s + At line 237 in file ..\CORE\startup_stm32f10x_hd.s + +I2C1_EV_IRQHandler 0000001A + +Symbol: I2C1_EV_IRQHandler + Definitions + At line 297 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 113 in file ..\CORE\startup_stm32f10x_hd.s + At line 236 in file ..\CORE\startup_stm32f10x_hd.s + +I2C2_ER_IRQHandler 0000001A + +Symbol: I2C2_ER_IRQHandler + Definitions + At line 300 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 116 in file ..\CORE\startup_stm32f10x_hd.s + At line 239 in file ..\CORE\startup_stm32f10x_hd.s + +I2C2_EV_IRQHandler 0000001A + +Symbol: I2C2_EV_IRQHandler + Definitions + At line 299 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 115 in file ..\CORE\startup_stm32f10x_hd.s + At line 238 in file ..\CORE\startup_stm32f10x_hd.s + + + + +ARM Macro Assembler Page 6 Alphabetic symbol ordering +Relocatable symbols + +MemManage_Handler 0000000C + +Symbol: MemManage_Handler + Definitions + At line 171 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 68 in file ..\CORE\startup_stm32f10x_hd.s + At line 172 in file ..\CORE\startup_stm32f10x_hd.s + +NMI_Handler 00000008 + +Symbol: NMI_Handler + Definitions + At line 161 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 66 in file ..\CORE\startup_stm32f10x_hd.s + At line 162 in file ..\CORE\startup_stm32f10x_hd.s + +PVD_IRQHandler 0000001A + +Symbol: PVD_IRQHandler + Definitions + At line 267 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 83 in file ..\CORE\startup_stm32f10x_hd.s + At line 206 in file ..\CORE\startup_stm32f10x_hd.s + +PendSV_Handler 00000016 + +Symbol: PendSV_Handler + Definitions + At line 194 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 78 in file ..\CORE\startup_stm32f10x_hd.s + At line 195 in file ..\CORE\startup_stm32f10x_hd.s + +RCC_IRQHandler 0000001A + +Symbol: RCC_IRQHandler + Definitions + At line 271 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 87 in file ..\CORE\startup_stm32f10x_hd.s + At line 210 in file ..\CORE\startup_stm32f10x_hd.s + +RTCAlarm_IRQHandler 0000001A + +Symbol: RTCAlarm_IRQHandler + Definitions + At line 307 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 123 in file ..\CORE\startup_stm32f10x_hd.s + At line 246 in file ..\CORE\startup_stm32f10x_hd.s + +RTC_IRQHandler 0000001A + +Symbol: RTC_IRQHandler + Definitions + At line 269 in file ..\CORE\startup_stm32f10x_hd.s + + + +ARM Macro Assembler Page 7 Alphabetic symbol ordering +Relocatable symbols + + Uses + At line 85 in file ..\CORE\startup_stm32f10x_hd.s + At line 208 in file ..\CORE\startup_stm32f10x_hd.s + +Reset_Handler 00000000 + +Symbol: Reset_Handler + Definitions + At line 149 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 65 in file ..\CORE\startup_stm32f10x_hd.s + At line 150 in file ..\CORE\startup_stm32f10x_hd.s + +SDIO_IRQHandler 0000001A + +Symbol: SDIO_IRQHandler + Definitions + At line 315 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 131 in file ..\CORE\startup_stm32f10x_hd.s + At line 254 in file ..\CORE\startup_stm32f10x_hd.s + +SPI1_IRQHandler 0000001A + +Symbol: SPI1_IRQHandler + Definitions + At line 301 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 117 in file ..\CORE\startup_stm32f10x_hd.s + At line 240 in file ..\CORE\startup_stm32f10x_hd.s + +SPI2_IRQHandler 0000001A + +Symbol: SPI2_IRQHandler + Definitions + At line 302 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 118 in file ..\CORE\startup_stm32f10x_hd.s + At line 241 in file ..\CORE\startup_stm32f10x_hd.s + +SPI3_IRQHandler 0000001A + +Symbol: SPI3_IRQHandler + Definitions + At line 317 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 133 in file ..\CORE\startup_stm32f10x_hd.s + At line 256 in file ..\CORE\startup_stm32f10x_hd.s + +SVC_Handler 00000012 + +Symbol: SVC_Handler + Definitions + At line 185 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 75 in file ..\CORE\startup_stm32f10x_hd.s + At line 186 in file ..\CORE\startup_stm32f10x_hd.s + +SysTick_Handler 00000018 + + + +ARM Macro Assembler Page 8 Alphabetic symbol ordering +Relocatable symbols + + +Symbol: SysTick_Handler + Definitions + At line 198 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 79 in file ..\CORE\startup_stm32f10x_hd.s + At line 199 in file ..\CORE\startup_stm32f10x_hd.s + +TAMPER_IRQHandler 0000001A + +Symbol: TAMPER_IRQHandler + Definitions + At line 268 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 84 in file ..\CORE\startup_stm32f10x_hd.s + At line 207 in file ..\CORE\startup_stm32f10x_hd.s + +TIM1_BRK_IRQHandler 0000001A + +Symbol: TIM1_BRK_IRQHandler + Definitions + At line 290 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 106 in file ..\CORE\startup_stm32f10x_hd.s + At line 229 in file ..\CORE\startup_stm32f10x_hd.s + +TIM1_CC_IRQHandler 0000001A + +Symbol: TIM1_CC_IRQHandler + Definitions + At line 293 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 109 in file ..\CORE\startup_stm32f10x_hd.s + At line 232 in file ..\CORE\startup_stm32f10x_hd.s + +TIM1_TRG_COM_IRQHandler 0000001A + +Symbol: TIM1_TRG_COM_IRQHandler + Definitions + At line 292 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 108 in file ..\CORE\startup_stm32f10x_hd.s + At line 231 in file ..\CORE\startup_stm32f10x_hd.s + +TIM1_UP_IRQHandler 0000001A + +Symbol: TIM1_UP_IRQHandler + Definitions + At line 291 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 107 in file ..\CORE\startup_stm32f10x_hd.s + At line 230 in file ..\CORE\startup_stm32f10x_hd.s + +TIM2_IRQHandler 0000001A + +Symbol: TIM2_IRQHandler + Definitions + At line 294 in file ..\CORE\startup_stm32f10x_hd.s + Uses + + + +ARM Macro Assembler Page 9 Alphabetic symbol ordering +Relocatable symbols + + At line 110 in file ..\CORE\startup_stm32f10x_hd.s + At line 233 in file ..\CORE\startup_stm32f10x_hd.s + +TIM3_IRQHandler 0000001A + +Symbol: TIM3_IRQHandler + Definitions + At line 295 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 111 in file ..\CORE\startup_stm32f10x_hd.s + At line 234 in file ..\CORE\startup_stm32f10x_hd.s + +TIM4_IRQHandler 0000001A + +Symbol: TIM4_IRQHandler + Definitions + At line 296 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 112 in file ..\CORE\startup_stm32f10x_hd.s + At line 235 in file ..\CORE\startup_stm32f10x_hd.s + +TIM5_IRQHandler 0000001A + +Symbol: TIM5_IRQHandler + Definitions + At line 316 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 132 in file ..\CORE\startup_stm32f10x_hd.s + At line 255 in file ..\CORE\startup_stm32f10x_hd.s + +TIM6_IRQHandler 0000001A + +Symbol: TIM6_IRQHandler + Definitions + At line 320 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 136 in file ..\CORE\startup_stm32f10x_hd.s + At line 259 in file ..\CORE\startup_stm32f10x_hd.s + +TIM7_IRQHandler 0000001A + +Symbol: TIM7_IRQHandler + Definitions + At line 321 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 137 in file ..\CORE\startup_stm32f10x_hd.s + At line 260 in file ..\CORE\startup_stm32f10x_hd.s + +TIM8_BRK_IRQHandler 0000001A + +Symbol: TIM8_BRK_IRQHandler + Definitions + At line 309 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 125 in file ..\CORE\startup_stm32f10x_hd.s + At line 248 in file ..\CORE\startup_stm32f10x_hd.s + +TIM8_CC_IRQHandler 0000001A + + + + +ARM Macro Assembler Page 10 Alphabetic symbol ordering +Relocatable symbols + +Symbol: TIM8_CC_IRQHandler + Definitions + At line 312 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 128 in file ..\CORE\startup_stm32f10x_hd.s + At line 251 in file ..\CORE\startup_stm32f10x_hd.s + +TIM8_TRG_COM_IRQHandler 0000001A + +Symbol: TIM8_TRG_COM_IRQHandler + Definitions + At line 311 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 127 in file ..\CORE\startup_stm32f10x_hd.s + At line 250 in file ..\CORE\startup_stm32f10x_hd.s + +TIM8_UP_IRQHandler 0000001A + +Symbol: TIM8_UP_IRQHandler + Definitions + At line 310 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 126 in file ..\CORE\startup_stm32f10x_hd.s + At line 249 in file ..\CORE\startup_stm32f10x_hd.s + +UART4_IRQHandler 0000001A + +Symbol: UART4_IRQHandler + Definitions + At line 318 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 134 in file ..\CORE\startup_stm32f10x_hd.s + At line 257 in file ..\CORE\startup_stm32f10x_hd.s + +UART5_IRQHandler 0000001A + +Symbol: UART5_IRQHandler + Definitions + At line 319 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 135 in file ..\CORE\startup_stm32f10x_hd.s + At line 258 in file ..\CORE\startup_stm32f10x_hd.s + +USART1_IRQHandler 0000001A + +Symbol: USART1_IRQHandler + Definitions + At line 303 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 119 in file ..\CORE\startup_stm32f10x_hd.s + At line 242 in file ..\CORE\startup_stm32f10x_hd.s + +USART2_IRQHandler 0000001A + +Symbol: USART2_IRQHandler + Definitions + At line 304 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 120 in file ..\CORE\startup_stm32f10x_hd.s + + + +ARM Macro Assembler Page 11 Alphabetic symbol ordering +Relocatable symbols + + At line 243 in file ..\CORE\startup_stm32f10x_hd.s + +USART3_IRQHandler 0000001A + +Symbol: USART3_IRQHandler + Definitions + At line 305 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 121 in file ..\CORE\startup_stm32f10x_hd.s + At line 244 in file ..\CORE\startup_stm32f10x_hd.s + +USBWakeUp_IRQHandler 0000001A + +Symbol: USBWakeUp_IRQHandler + Definitions + At line 308 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 124 in file ..\CORE\startup_stm32f10x_hd.s + At line 247 in file ..\CORE\startup_stm32f10x_hd.s + +USB_HP_CAN1_TX_IRQHandler 0000001A + +Symbol: USB_HP_CAN1_TX_IRQHandler + Definitions + At line 285 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 101 in file ..\CORE\startup_stm32f10x_hd.s + At line 224 in file ..\CORE\startup_stm32f10x_hd.s + +USB_LP_CAN1_RX0_IRQHandler 0000001A + +Symbol: USB_LP_CAN1_RX0_IRQHandler + Definitions + At line 286 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 102 in file ..\CORE\startup_stm32f10x_hd.s + At line 225 in file ..\CORE\startup_stm32f10x_hd.s + +UsageFault_Handler 00000010 + +Symbol: UsageFault_Handler + Definitions + At line 181 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 70 in file ..\CORE\startup_stm32f10x_hd.s + At line 182 in file ..\CORE\startup_stm32f10x_hd.s + +WWDG_IRQHandler 0000001A + +Symbol: WWDG_IRQHandler + Definitions + At line 266 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 82 in file ..\CORE\startup_stm32f10x_hd.s + At line 205 in file ..\CORE\startup_stm32f10x_hd.s + +__user_initial_stackheap 0000001C + +Symbol: __user_initial_stackheap + + + +ARM Macro Assembler Page 12 Alphabetic symbol ordering +Relocatable symbols + + Definitions + At line 346 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 344 in file ..\CORE\startup_stm32f10x_hd.s +Comment: __user_initial_stackheap used once +73 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Absolute symbols + +Heap_Size 00000200 + +Symbol: Heap_Size + Definitions + At line 47 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 51 in file ..\CORE\startup_stm32f10x_hd.s + At line 350 in file ..\CORE\startup_stm32f10x_hd.s + +Stack_Size 00000400 + +Symbol: Stack_Size + Definitions + At line 37 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 40 in file ..\CORE\startup_stm32f10x_hd.s + At line 349 in file ..\CORE\startup_stm32f10x_hd.s + +__Vectors_Size 00000130 + +Symbol: __Vectors_Size + Definitions + At line 144 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 62 in file ..\CORE\startup_stm32f10x_hd.s +Comment: __Vectors_Size used once +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +External symbols + +SystemInit 00000000 + +Symbol: SystemInit + Definitions + At line 152 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 153 in file ..\CORE\startup_stm32f10x_hd.s +Comment: SystemInit used once +__main 00000000 + +Symbol: __main + Definitions + At line 151 in file ..\CORE\startup_stm32f10x_hd.s + Uses + At line 155 in file ..\CORE\startup_stm32f10x_hd.s +Comment: __main used once +__use_two_region_memory 00000000 + +Symbol: __use_two_region_memory + Definitions + At line 343 in file ..\CORE\startup_stm32f10x_hd.s + Uses + None +Comment: __use_two_region_memory unused +3 symbols +425 symbols in table diff --git a/USER/RTE/Device/STM32F103RC/STM32F101_102_103_105_107.dbgconf b/USER/RTE/Device/STM32F103RC/STM32F101_102_103_105_107.dbgconf new file mode 100644 index 0000000..66e10b6 --- /dev/null +++ b/USER/RTE/Device/STM32F103RC/STM32F101_102_103_105_107.dbgconf @@ -0,0 +1,36 @@ +// File: STM32F101_102_103_105_107.dbgconf +// Version: 1.0.0 +// Note: refer to STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx Reference manual (RM0008) +// STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx datasheets + +// <<< Use Configuration Wizard in Context Menu >>> + +// Debug MCU configuration register (DBGMCU_CR) +// Reserved bits must be kept at reset value +// DBG_TIM11_STOP TIM11 counter stopped when core is halted +// DBG_TIM10_STOP TIM10 counter stopped when core is halted +// DBG_TIM9_STOP TIM9 counter stopped when core is halted +// DBG_TIM14_STOP TIM14 counter stopped when core is halted +// DBG_TIM13_STOP TIM13 counter stopped when core is halted +// DBG_TIM12_STOP TIM12 counter stopped when core is halted +// DBG_CAN2_STOP Debug CAN2 stopped when core is halted +// DBG_TIM7_STOP TIM7 counter stopped when core is halted +// DBG_TIM6_STOP TIM6 counter stopped when core is halted +// DBG_TIM5_STOP TIM5 counter stopped when core is halted +// DBG_TIM8_STOP TIM8 counter stopped when core is halted +// DBG_I2C2_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted +// DBG_I2C1_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted +// DBG_CAN1_STOP Debug CAN1 stopped when Core is halted +// DBG_TIM4_STOP TIM4 counter stopped when core is halted +// DBG_TIM3_STOP TIM3 counter stopped when core is halted +// DBG_TIM2_STOP TIM2 counter stopped when core is halted +// DBG_TIM1_STOP TIM1 counter stopped when core is halted +// DBG_WWDG_STOP Debug window watchdog stopped when core is halted +// DBG_IWDG_STOP Debug independent watchdog stopped when core is halted +// DBG_STANDBY Debug standby mode +// DBG_STOP Debug stop mode +// DBG_SLEEP Debug sleep mode +// +DbgMCU_CR = 0x00000007; + +// <<< end of configuration section >>> diff --git a/USER/RTE/Device/STM32F103RC/STM32F101_102_103_105_107.dbgconf.base@1.0.0 b/USER/RTE/Device/STM32F103RC/STM32F101_102_103_105_107.dbgconf.base@1.0.0 new file mode 100644 index 0000000..66e10b6 --- /dev/null +++ b/USER/RTE/Device/STM32F103RC/STM32F101_102_103_105_107.dbgconf.base@1.0.0 @@ -0,0 +1,36 @@ +// File: STM32F101_102_103_105_107.dbgconf +// Version: 1.0.0 +// Note: refer to STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx Reference manual (RM0008) +// STM32F101xx STM32F102xx STM32F103xx STM32F105xx STM32F107xx datasheets + +// <<< Use Configuration Wizard in Context Menu >>> + +// Debug MCU configuration register (DBGMCU_CR) +// Reserved bits must be kept at reset value +// DBG_TIM11_STOP TIM11 counter stopped when core is halted +// DBG_TIM10_STOP TIM10 counter stopped when core is halted +// DBG_TIM9_STOP TIM9 counter stopped when core is halted +// DBG_TIM14_STOP TIM14 counter stopped when core is halted +// DBG_TIM13_STOP TIM13 counter stopped when core is halted +// DBG_TIM12_STOP TIM12 counter stopped when core is halted +// DBG_CAN2_STOP Debug CAN2 stopped when core is halted +// DBG_TIM7_STOP TIM7 counter stopped when core is halted +// DBG_TIM6_STOP TIM6 counter stopped when core is halted +// DBG_TIM5_STOP TIM5 counter stopped when core is halted +// DBG_TIM8_STOP TIM8 counter stopped when core is halted +// DBG_I2C2_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted +// DBG_I2C1_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted +// DBG_CAN1_STOP Debug CAN1 stopped when Core is halted +// DBG_TIM4_STOP TIM4 counter stopped when core is halted +// DBG_TIM3_STOP TIM3 counter stopped when core is halted +// DBG_TIM2_STOP TIM2 counter stopped when core is halted +// DBG_TIM1_STOP TIM1 counter stopped when core is halted +// DBG_WWDG_STOP Debug window watchdog stopped when core is halted +// DBG_IWDG_STOP Debug independent watchdog stopped when core is halted +// DBG_STANDBY Debug standby mode +// DBG_STOP Debug stop mode +// DBG_SLEEP Debug sleep mode +// +DbgMCU_CR = 0x00000007; + +// <<< end of configuration section >>> diff --git a/USER/global.c b/USER/global.c new file mode 100644 index 0000000..23c7f88 --- /dev/null +++ b/USER/global.c @@ -0,0 +1,1493 @@ +/** + ****************************************************************************** + * @file tim.c + * @author Jerry + * @version V2.1 + * @date 19-April-2022 + * @brief tim program body. + ****************************************************************************** + * @attention + * + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" +#include "global.h" +#include "string.h" +#include "stdio.h" + +ONLINE_MEMORY onlineMem; + +VERSION_MEMORY VersionMem; +PARA_MEMORY paraMem; +BMS_MEMORY bmsMem; +BMS_MEMORY bmsMem_slave; + +PROTOCOL_SRNE_MEMORY SRNEMem; +PROTOCOL_VOLTRONIC_MEMORY VoltronicMem; +PROTOCOL_SMK_MEMORY SMKMem; +PROTOCOL_Growatt_MEMORY GrowattMem; + +UNION_VOLTAGE_STATUS staVol; +UNION_CURRENT_STATUS staCur; +UNION_TEMPERA_STATUS1 staTemp1; +UNION_TEMPERA_STATUS2 staTemp2; +UNION_MOSFET_STATUS staMos; +UNION_PACK_STATUS staPack; + +uint16_t alarm_occ_old; +uint16_t alarm_ocd1_old; +uint16_t alarm_puv_old; +uint8_t chgCurLimit_changeFlg; +uint8_t dsgCurLimit_changeFlg; +uint8_t dsgVolLimit_changeFlg; + +const uint8_t CRC8Table[]= +{ //120424-1 CRC Table + 0x00,0x07,0x0E,0x09,0x1C,0x1B,0x12,0x15,0x38,0x3F,0x36,0x31,0x24,0x23,0x2A,0x2D, + 0x70,0x77,0x7E,0x79,0x6C,0x6B,0x62,0x65,0x48,0x4F,0x46,0x41,0x54,0x53,0x5A,0x5D, + 0xE0,0xE7,0xEE,0xE9,0xFC,0xFB,0xF2,0xF5,0xD8,0xDF,0xD6,0xD1,0xC4,0xC3,0xCA,0xCD, + 0x90,0x97,0x9E,0x99,0x8C,0x8B,0x82,0x85,0xA8,0xAF,0xA6,0xA1,0xB4,0xB3,0xBA,0xBD, + 0xC7,0xC0,0xC9,0xCE,0xDB,0xDC,0xD5,0xD2,0xFF,0xF8,0xF1,0xF6,0xE3,0xE4,0xED,0xEA, + 0xB7,0xB0,0xB9,0xBE,0xAB,0xAC,0xA5,0xA2,0x8F,0x88,0x81,0x86,0x93,0x94,0x9D,0x9A, + 0x27,0x20,0x29,0x2E,0x3B,0x3C,0x35,0x32,0x1F,0x18,0x11,0x16,0x03,0x04,0x0D,0x0A, + 0x57,0x50,0x59,0x5E,0x4B,0x4C,0x45,0x42,0x6F,0x68,0x61,0x66,0x73,0x74,0x7D,0x7A, + 0x89,0x8E,0x87,0x80,0x95,0x92,0x9B,0x9C,0xB1,0xB6,0xBF,0xB8,0xAD,0xAA,0xA3,0xA4, + 0xF9,0xFE,0xF7,0xF0,0xE5,0xE2,0xEB,0xEC,0xC1,0xC6,0xCF,0xC8,0xDD,0xDA,0xD3,0xD4, + 0x69,0x6E,0x67,0x60,0x75,0x72,0x7B,0x7C,0x51,0x56,0x5F,0x58,0x4D,0x4A,0x43,0x44, + 0x19,0x1E,0x17,0x10,0x05,0x02,0x0B,0x0C,0x21,0x26,0x2F,0x28,0x3D,0x3A,0x33,0x34, + 0x4E,0x49,0x40,0x47,0x52,0x55,0x5C,0x5B,0x76,0x71,0x78,0x7F,0x6A,0x6D,0x64,0x63, + 0x3E,0x39,0x30,0x37,0x22,0x25,0x2C,0x2B,0x06,0x01,0x08,0x0F,0x1A,0x1D,0x14,0x13, + 0xAE,0xA9,0xA0,0xA7,0xB2,0xB5,0xBC,0xBB,0x96,0x91,0x98,0x9F,0x8A,0x8D,0x84,0x83, + 0xDE,0xD9,0xD0,0xD7,0xC2,0xC5,0xCC,0xCB,0xE6,0xE1,0xE8,0xEF,0xFA,0xFD,0xF4,0xF3 +}; + +//look-up table calculte CRC +uint8_t CRC8_Cal(uint8_t *pdata, uint8_t len) +{ + uint8_t crc8 = 0; + + for(; len > 0; len--) + { + crc8 = CRC8Table[crc8^*pdata]; + pdata++; + } + return(crc8); +} + +//和Flash_CRC校验同理的值 +uint16_t CRC16_FirmtoEE(uint8_t *data, uint16_t len) +{ + uint16_t i,j; + uint16_t mCrc = 0; + + for(i=0; i 0x30~0x39 + { + result = 0x30 + data; + } + else //A~F -> 0x41~0x46 + { + result = 0x37 + data; + } + + return result; +} + +//根据当前时间取伪随机数，范围AddrMax+1~65534 +#define MODULUS 2147483647 +#define MULTIPLIER 1103515245 +#define ADDEND 12345 +uint16_t get_random(void) +{ + uint32_t time; + uint32_t rand; + uint16_t index; + + time=RTC_GetCounter(); + rand=(time * MULTIPLIER + ADDEND) % MODULUS; //取值范围是0到MODULUS-1 + + index=rand%(65535-(AddrMax+1)-1+1)+(AddrMax+1); //取值范围是AddrMax+1~65534 + + return index; +} + +//功能函数：获取字符串里的参数值 +uint8_t GetStr(const char* dataKey, char End1, char End2, char* InStr, char* OutStr) +{ + uint8_t datalen = 0; //字符串长度 + + char* dataStart = strstr(InStr, dataKey); //找dataKey + if(dataStart == NULL) + { + return 0; //找不到dataKey，返回0 + } + dataStart += strlen(dataKey); //跳过dataKey + + char* dataEnd = strchr(dataStart, End1); //先找End1 + if(dataEnd == NULL) + { + dataEnd = strchr(dataStart, End2); //再找End2 + } + if(dataEnd == NULL) + { + return 0; //找不到End1和End2，返回0 + } + + datalen = dataEnd - dataStart; + strncpy(OutStr, dataStart, datalen); + OutStr[datalen] = '\0'; + + return datalen; //返回内容长度 +} + +//功能函数：获取request_id +uint8_t GetID(char* InStr, char* OutStr) +{ + //{"request_id":"123124sdf",…} + const char* dataKey = "\"request_id\":\""; + char End = '\"'; + + uint8_t datalen = 0; //字符串长度 + + char* dataStart = strstr(InStr, dataKey); //找dataKey + if(dataStart == NULL) + { + return 0; //找不到dataKey，返回0 + } + dataStart += strlen(dataKey); + + char* dataEnd = strchr(dataStart, End); //找End + if(dataEnd == NULL) + { + return 0; //找不到End，返回0 + } + + datalen = dataEnd - dataStart; + strncpy(OutStr, dataStart, datalen); + OutStr[datalen] = '\0'; + + return datalen; //返回内容长度 +} + +//功能函数：获取字符串里的参数值 +//增加：只输入名称，会寻找之后的第一个':' +//注意：只适合"Name":Value这种格式，结束符固定','或'}' +uint8_t GetStrFromJson(const char* dataKey, char* InStr, char* OutStr) +{ + uint8_t datalen = 0; //字符串长度 + + char* dataStart = strstr(InStr, dataKey); //找dataKey + if(dataStart == NULL) + { + return 0; //找不到dataKey，返回0 + } + dataStart += strlen(dataKey); //跳过dataKey + + dataStart = strchr(dataStart, ':');//找dataKey之后的第一个':' + if(dataStart == NULL) + { + return 0; //找不到':'，返回0 + } + dataStart += 1; //跳过冒号 + + while (*dataStart == ' ') dataStart++; //跳过空白 + + char* dataEnd = strchr(dataStart, ','); //先找End1 + if(dataEnd == NULL) + { + dataEnd = strchr(dataStart, '}'); //再找End2 + } + if(dataEnd == NULL) + { + return 0; //找不到End1和End2，返回0 + } + + datalen = dataEnd - dataStart; + strncpy(OutStr, dataStart, datalen); + OutStr[datalen] = '\0'; + + return datalen; //返回内容长度 +} + +//计算无符号数在十进制转字符串后，要多少字节 +//输入最大5位数，保险起见再加1位 +uint8_t uint_str_len(uint32_t value) +{ + if(value < 10) return 1; + else if((value < 100)) return 2; + else if((value < 1000)) return 3; + else if((value < 10000)) return 4; + else if((value < 100000)) return 5; + else if((value < 1000000)) return 6; + else if((value < 10000000)) return 7; + else if((value < 100000000)) return 8; + else if((value < 1000000000)) return 9; + return 10; +} + +//计算有符号数在十进制转字符串后，要多少字节 +uint8_t int_str_len(int32_t value) +{ + uint32_t abs_vlaue; + uint8_t abs_len; + + if(value == INT32_MIN) return 11; //"-2147483648" + + abs_vlaue = (value<0) ? (uint32_t)(-value):(uint32_t)value; + abs_len = uint_str_len(abs_vlaue); + + return (value<0) ? abs_len+1:abs_len; +} + +//实时更新并机总数据和数据判断，1s执行1次 +uint8_t OnlineNum; //BMS正常工作数量 +uint8_t OnlineFirstAddr; //第一个是正常工作的并机地址 +uint8_t chg_curLimitNum; //充电限流置0的个数，SOC大于100%的时候启用 +uint8_t dsg_curLimitNum; //放电限流置0的个数，SOC小于10%的时候启用 +uint8_t chg_cur0Num; //因报警触发充电限流40A时，出现保护限流0A的个数 +void canMem_refresh(void) +{ + uint8_t i; + int32_t oldcur = canMem[0].cur; //保留上一次的总电流值，在计算值异常时放入 + + + /*并机汇总信息的计算*/ + //1.485采集数据初始化 + canMem[0].status_byte1 = 0; + canMem[0].status_byte2 = 0; + canMem[0].status_byte3 = 0; + canMem[0].status_byte4 = 0; + canMem[0].soc = 0; + canMem[0].soh = 0; + canMem[0].cur = 0; + canMem[0].temp = 0; + canMem[0].VolMax = 0; + canMem[0].VolMin = 0; + canMem[0].VolMaxIndex = 0; + canMem[0].VolMinIndex = 0; + canMem[0].TempMax = 0; + canMem[0].TempMin = 0; + canMem[0].TempMaxIndex = 0; + canMem[0].TempMinIndex = 0; + + //Wh版屏幕 + canMem[0].cumuliCap = 0; + canMem[0].cycleCnt = 0; + + //负值矫正 + canMem[0].cellVoltageMax = 0; + canMem[0].cellVoltageMin = 0; + + + canMem[1].status_byte1 = bmsMem.can_status_byte1; + canMem[1].status_byte2 = bmsMem.can_status_byte2; + canMem[1].status_byte3 = bmsMem.can_status_byte3; + canMem[1].status_byte4 = bmsMem.can_status_byte4; + canMem[1].soc = bmsMem.can_soc; + canMem[1].soh = bmsMem.can_soh; + canMem[1].cur = (int16_t)bmsMem.can_cur; + canMem[1].temp = (int16_t)bmsMem.can_temp; + canMem[1].VolMax = bmsMem.can_VolMax; + canMem[1].VolMin = bmsMem.can_VolMin; + canMem[1].VolMaxIndex = bmsMem.can_VolMaxIndex; + canMem[1].VolMinIndex = bmsMem.can_VolMinIndex; + canMem[1].TempMax = bmsMem.can_TempMax; + canMem[1].TempMin = bmsMem.can_TempMin; + canMem[1].TempMaxIndex = bmsMem.can_TempMaxIndex; + canMem[1].TempMinIndex = bmsMem.can_TempMinIndex; + + //Wh版屏幕 + canMem[1].cumuliCap = bmsMem.can_cumuliCap; + canMem[1].cycleCnt = bmsMem.can_cycleCnt; + + //负值矫正 + canMem[1].cellVoltageMax = (int16_t)(canMem[1].VolMax*32/5)*5/32; + canMem[1].cellVoltageMin = (int16_t)(canMem[1].VolMin*32/5)*5/32; + + #if Addr_SetAuto + if((paraMem.addr_FREE_Flg == 0) && (assignAddr_random != 0)) + { + canMem[1].com = assignAddr_random; //赋值主机自身生成的队列标志位 + } + else + #endif + { + canMem[1].com = 1; //就算此时没有生成好的队列标志位，也要置1不能是0（按逻辑其实这里一定有队列标志位） + } + + //2.统计当前通讯正常从机数量 + bmsMem.E2_485Snum = 1; + for(i=2;i<=paraMem.PACK_NUM;i++) + { + if(canMem[i].com != 0) //引入队列标志位后的改动 + { + bmsMem.E2_485Snum++; + } + } + + //3.计算并机总值 + //报警记录的并机值 + for(i=1;i<=paraMem.PACK_NUM;i++) + { + if(canMem[i].com != 0) + { + canMem[0].status_byte1 |= canMem[i].status_byte1; + canMem[0].status_byte2 |= canMem[i].status_byte2; + canMem[0].status_byte3 |= canMem[i].status_byte3; + canMem[0].status_byte4 |= canMem[i].status_byte4; + } + } + //参数的并机值 + //当处于并机模式，只纳入在线正常工作的BMS的数据 + if(bmsMem.E2_485Snum >= 2) + { + /*统计工作正常的数量，addr=1也要检测*/ + OnlineNum = 0; + OnlineFirstAddr = 0; + for(i=1;i<=paraMem.PACK_NUM;i++) + { + if(canMem[i].com != 0) //引入队列标志位后的改动 + { + //没有任何报警的BMS才认为是在线的(不考虑总体/单体过压) + if( ((canMem[i].status_byte1 & 0x067e) == 0) && ((canMem[i].status_byte2 & 0x00ff) == 0) && ((canMem[i].status_byte3 & 0x0008) == 0) && ((canMem[i].status_byte4 & 0x0f7f) == 0) ) + { + canMem[0].soc += canMem[i].soc; + canMem[0].soh += canMem[i].soh; + canMem[0].cur += canMem[i].cur; + canMem[0].temp += canMem[i].temp; + + //Wh版屏幕 + canMem[0].cumuliCap += canMem[i].cumuliCap; + canMem[0].cycleCnt += canMem[i].cycleCnt; + + if(OnlineFirstAddr == 0) OnlineFirstAddr = i; + OnlineNum++; + } + } + } + + if(OnlineNum != 0) //存在才能进行除计算 + { + //计算平均值 + canMem[0].soc = canMem[0].soc / OnlineNum; + canMem[0].soh = canMem[0].soh / OnlineNum; + canMem[0].temp = canMem[0].temp / OnlineNum; + + //计算最大最小值 + canMem[0].VolMax = canMem[OnlineFirstAddr].VolMax; + canMem[0].VolMin = canMem[OnlineFirstAddr].VolMin; + canMem[0].cellVoltageMax = canMem[OnlineFirstAddr].cellVoltageMax; //负值矫正 + canMem[0].cellVoltageMin = canMem[OnlineFirstAddr].cellVoltageMin; //负值矫正 + canMem[0].VolMaxIndex = canMem[OnlineFirstAddr].VolMaxIndex; + canMem[0].VolMinIndex = canMem[OnlineFirstAddr].VolMinIndex; + canMem[0].TempMax = canMem[OnlineFirstAddr].TempMax; + canMem[0].TempMin = canMem[OnlineFirstAddr].TempMin; + canMem[0].TempMaxIndex = canMem[OnlineFirstAddr].TempMaxIndex; + canMem[0].TempMinIndex = canMem[OnlineFirstAddr].TempMinIndex; + for(i=OnlineFirstAddr+1;i<=paraMem.PACK_NUM;i++) + { + if(canMem[i].com != 0) //只比较在线的 + { + //没有执行任何保护的BMS才认为是在线的(不考虑总体/单体过压) + if( ((canMem[i].status_byte1 & 0x067e) == 0) && ((canMem[i].status_byte2 & 0x00ff) == 0) && ((canMem[i].status_byte3 & 0x0008) == 0) && ((canMem[i].status_byte4 & 0x0f7f) == 0) ) + { + //if(canMem[i].VolMax > canMem[0].VolMax) + if(canMem[i].cellVoltageMax > canMem[0].cellVoltageMax) + { + canMem[0].cellVoltageMax = canMem[i].cellVoltageMax; //负值矫正 + + canMem[0].VolMax = canMem[i].VolMax; + canMem[0].VolMaxIndex = canMem[i].VolMaxIndex+bmsMem.ucCellNum*(i-1); + } + //if(canMem[i].VolMin < canMem[0].VolMin) + if(canMem[i].cellVoltageMin < canMem[0].cellVoltageMin) + { + canMem[0].cellVoltageMin = canMem[i].cellVoltageMin; //负值矫正 + + canMem[0].VolMin = canMem[i].VolMin; + canMem[0].VolMinIndex = canMem[i].VolMinIndex+bmsMem.ucCellNum*(i-1); + } + + if(canMem[i].TempMax > canMem[0].TempMax) + { + canMem[0].TempMax = canMem[i].TempMax; + canMem[0].TempMaxIndex = canMem[i].TempMaxIndex+4*(i-1); + } + if(canMem[i].TempMin < canMem[0].TempMin) + { + canMem[0].TempMin = canMem[i].TempMin; + canMem[0].TempMinIndex = canMem[i].TempMinIndex+4*(i-1); + } + } + } + } + } + } + //只连一台，只显示主机自身 + else + { + //赋值1，不影响协议显示 + OnlineNum = 1; + + //单板直接等于主机值 + canMem[0].soc = canMem[1].soc; + canMem[0].soh = canMem[1].soh; + canMem[0].cur = canMem[1].cur; + canMem[0].temp = canMem[1].temp; + + canMem[0].VolMax = canMem[1].VolMax; + canMem[0].VolMin = canMem[1].VolMin; + canMem[0].VolMaxIndex = canMem[1].VolMaxIndex; + canMem[0].VolMinIndex = canMem[1].VolMinIndex; + canMem[0].TempMax = canMem[1].TempMax; + canMem[0].TempMin = canMem[1].TempMin; + canMem[0].TempMaxIndex = canMem[1].TempMaxIndex; + canMem[0].TempMinIndex = canMem[1].TempMinIndex; + + //Wh版屏幕 + canMem[0].cumuliCap = canMem[1].cumuliCap; + canMem[0].cycleCnt = canMem[1].cycleCnt; + + //负值矫正 + canMem[0].cellVoltageMax = (int16_t)(canMem[0].VolMax*32/5)*5/32; + canMem[0].cellVoltageMin = (int16_t)(canMem[0].VolMin*32/5)*5/32; + } + + //额外补丁：超过600A的异常电流值不显示 + if( (canMem[0].cur >= 60000) || (canMem[0].cur <= (-60000)) ) //600A = 60000*0.01A + { + canMem[0].cur = oldcur; + } + + + //4.数据分析判断 + //逆变器通信：充到100%,启用禁充标志，低于99%释放 + if((paraMem.requestFlg_enable & 0x0080) != 0) + { + if(canMem[0].soc >= paraMem.chg_forbid_Soc) + { + chg_forbidFlg = 1; + } + else if(canMem[0].soc <= paraMem.chg_forbid_rSoc) + { + chg_forbidFlg = 0; + } + } + else + { + chg_forbidFlg = 0; + } + //逆变器通信：小于10%,启用禁放标志;超过20%后释放 + if((paraMem.requestFlg_enable & 0x0040) != 0) + { + if(canMem[0].soc <= paraMem.dsg_forbid_Soc) + { + dsg_forbidFlg = 1; + } + else if(canMem[0].soc >= paraMem.dsg_forbid_rSoc) + { + dsg_forbidFlg = 0; + } + + //当PACK电压=放电请求电压时，BMS发送禁放指令 + if(bmsMem.packVoltage <= bmsMem.inverter_dsgVolLimit*100) + { + dsg_forbidFlg = 1; + } + } + else + { + dsg_forbidFlg = 0; + } + //逆变器通信：小于10%,启用强充标志;超过20%后释放 + if((paraMem.requestFlg_enable & 0x0020) != 0) + { + if(canMem[0].soc <= paraMem.chg_force_Soc) + { + chg_forceFlg = 1; + } + else if(canMem[0].soc >= paraMem.chg_force_rSoc) + { + chg_forceFlg = 0; + } + } + else + { + chg_forceFlg = 0; + } + //逆变器通信：出现充电单体/总体过压告警后，逆变器充电限流固定40A + if((canMem[0].status_byte3 & 0x0500) != 0) + { + chg_curlimitFlg = 1; + } + else + { + chg_curlimitFlg = 0; + } + + + //对于正常在线的PACK，若满足条件则计数，以在未完全禁充禁放时，更改限压限流值 + chg_curLimitNum = 0; + dsg_curLimitNum = 0; + chg_cur0Num = 0; + for(i=1;i<=paraMem.PACK_NUM;i++) + { + if(canMem[i].com != 0) //引入队列标志位后的改动 + { + //没有任何报警的BMS才认为是在线的(不考虑总体/单体过压) + if( ((canMem[i].status_byte1 & 0x067e) == 0) && ((canMem[i].status_byte2 & 0x00ff) == 0) && ((canMem[i].status_byte3 & 0x0008) == 0) && ((canMem[i].status_byte4 & 0x0f7f) == 0) ) + { + if((canMem[i].soc >= paraMem.chg_forbid_Soc) && ((paraMem.requestFlg_enable & 0x0080) != 0)) //禁充个数 + { + chg_curLimitNum++; + } + if((canMem[i].soc < paraMem.dsg_forbid_Soc) && ((paraMem.requestFlg_enable & 0x0040) != 0)) //禁放个数 + { + dsg_curLimitNum++; + } + if((canMem[i].status_byte1 & 0x0101) != 0) //出现过压保护的个数 + { + chg_cur0Num++; + } + } + } + } +} + +//更新回复上位机对并机信息的请求所需的数据，1s执行1次 +void onlineMem_refresh(void) +{ + uint8_t i; + + /**上位机读信息的处理**/ + //上位机询问并机情况的回复 + onlineMem.Online[0] = 0; //3.11 表示工作正常的并机个数 + for(i=1; i<=paraMem.PACK_NUM; i++) + { + if(canMem[i].com != 0) + { + if( ((canMem[i].status_byte1 & 0x067e) ==0) && ((canMem[i].status_byte2 & 0x00ff) ==0) && ((canMem[i].status_byte3 & 0x0008) ==0) && ((canMem[i].status_byte4 & 0x0f7f) ==0) ) + { + onlineMem.Online[0]++; //该从机的(不管总体/单体过压报警的其他)报警都没有，就认为在线数量+1 + + if((canMem[i].status_byte1 & 0x01) ==0) //若不存在过压报警，确认正常 + { + onlineMem.Online[i] = 0xAA; //正常 + } + else + { + onlineMem.Online[i] = 0xBB; //存在报警 + } + } + else + { + onlineMem.Online[i] = 0xBB; //存在报警 + } + } + else + { + onlineMem.Online[i] = 0x00; + } + } + //若实际不在并机，则固定1个 + if(bmsMem.E2_485Snum == 1) + { + onlineMem.Online[0] = 1; + } +} + +//参数改动函数，1s执行1次 +uint8_t Addr_SetCount;//改虚地址后等待10s +void ParaChange(void) +{ + uint8_t tempWr[2]; + + + #if Addr_SetAuto + uint8_t tmpRd; + + //分配地址-从机：虚地址10s自恢复 + if((bmsMem.E2_485Addr == 0) || (bmsMem.E2_485Addr > AddrMax)) //若地址长时间保持为虚地址，自动恢复原地址 + { + Addr_SetCount++; + if(Addr_SetCount > 10) //10s + { + Addr_SetCount=0; + + EEPROM_RdMulByte(EE_ADDR,&tmpRd); + if((tmpRd>=1) && (tmpRd<=AddrMax)) + { + bmsMem.E2_485Addr = tmpRd; + } + else + { + bmsMem.E2_485Addr = 2; + } + scr_RdData_Index = bmsMem.E2_485Addr; + } + } + else + { + Addr_SetCount=0; + } + #endif + + + #if LTE_Conn + if((sleep_flag == 0) && (LTE_sleep_flag == 2)) + { + LTE_sleep_flag = 0xAA; //4G执行退出休眠 + } + #endif + + + /**上位机写参数的处理**/ + //上位机修改容量 + if(bmsMem.write_Capacity !=0) + { + if((bmsMem.write_Capacity>0) && (bmsMem.write_Capacity<=1000)) //范围1~1000Ah + { + tempWr[0] = (bmsMem.write_Capacity >> 8) & 0xff; + tempWr[1] = (bmsMem.write_Capacity >> 0) & 0xff; + EEPROM_WrMulByte(EE_NCC,tempWr); + delay_ms(5); + + //赋值额定容量 + bmsMem.ncc = 3600 * 1000 * bmsMem.write_Capacity; + ncc_Ah = bmsMem.write_Capacity; + + //赋值满充容量=额定容量 + fcc = bmsMem.ncc; + fcc_Ah = ncc_Ah; + tmpWrFCC[0] = (fcc>>24) & 0xff; + tmpWrFCC[1] = (fcc>>16) & 0xff; + tmpWrFCC[2] = (fcc>> 8) & 0xff; + tmpWrFCC[3] = (fcc>> 0) & 0xff; + tmpWrFCC[4] = tmpWrFCC[0] ^ 0xff; + tmpWrFCC[5] = tmpWrFCC[1] ^ 0xff; + tmpWrFCC[6] = tmpWrFCC[2] ^ 0xff; + tmpWrFCC[7] = tmpWrFCC[3] ^ 0xff; + EEPROM_WrMulByte(EE_FCC,tmpWrFCC); + delay_ms(20); + + //赋值剩余容量=新的满充容量*SOC + bmsMem.rcc = fcc/100 * bmsMem.soc; + rcc_Ah = fcc_Ah * bmsMem.soc / 100; + oldrcc_Ah = rcc_Ah; + + //改额定容量不影响此前的满放满充过程 + + bmsMem.write_Capacity = 0; + } + else + { + bmsMem.write_Capacity = 0; + } + } + //上位机修改SOC + if(bmsMem.write_Soc !=0) + { + if(bmsMem.write_Soc <= 100) //范围判断 + { + EEPROM_WrMulByte(EE_SOC,&bmsMem.write_Soc); + delay_ms(5); + + //赋值SOC + bmsMem.soc = bmsMem.write_Soc; + + //赋值剩余容量=满充容量*新的SOC + bmsMem.rcc = fcc/100 * bmsMem.soc; + rcc_Ah = fcc_Ah * bmsMem.soc / 100; + oldrcc_Ah = rcc_Ah; + + //在满放满充过程中，修改SOC会影响效果，不再执行 + if(fcc_CaliStartFlag == 1) + { + fcc_CaliStartFlag = 0; + if(LSEErrFlag == 0) + { + EEPROM_WrMulByte(EE_FCC_TIME,ClearEE); + delay_ms(5); + } + } + + bmsMem.write_Soc = 0; + } + else if(bmsMem.write_Soc == 0xAA) + { + bmsMem.write_Soc = 0; + EEPROM_WrMulByte(EE_SOC,&bmsMem.write_Soc); + delay_ms(5); + + //赋值SOC + bmsMem.soc = bmsMem.write_Soc; + + //赋值剩余容量=满充容量*新的SOC + bmsMem.rcc = fcc/100 * bmsMem.soc; + rcc_Ah = fcc_Ah * bmsMem.soc /100; + oldrcc_Ah = rcc_Ah; + + //在满放满充过程中，修改SOC会影响效果，不再执行 + if(fcc_CaliStartFlag == 1) + { + fcc_CaliStartFlag = 0; + if(LSEErrFlag == 0) + { + EEPROM_WrMulByte(EE_FCC_TIME,ClearEE); + delay_ms(5); + } + } + } + else + { + bmsMem.write_Soc = 0; + } + } + + //上位机修改休眠是否启用的标志位 + if((paraMem.sleep_min_disable & 0x8000) == 0) //现在启用休眠1 + { + if((sleep_enableflag & 0x01) == 0) //之前不执行休眠1 + { + //在第一次发现不同后更新sleep + sleep_enableflag |= 0x01; + SLEEP_Refresh(); + } + } + else + { + //保持清零 + sleep_enableflag &= 0xfe; + sleeptimecount=0; + //若休眠模式都已关闭，退出休眠 + if(sleep_enableflag == 0) sleep_flag = 0; + } + if((paraMem.sleep2_min_disable & 0x8000) == 0) //现在启用休眠2 + { + if((sleep_enableflag & 0x02) == 0) //之前不执行休眠2 + { + //在第一次发现不同后更新sleep + sleep_enableflag |= 0x02; + SLEEP2_Refresh(); + } + } + else + { + //保持清零 + sleep_enableflag &= 0xfd; + sleep2timecount=0; + //若休眠模式都已关闭，退出休眠 + if(sleep_enableflag == 0) sleep_flag = 0; + } + + //上位机解锁电流保护次数超限锁定 + if((CTRL_Order & 0x10) != 0) + { + CTRL_Order &= 0xef; //用完恢复 + bmsMem.balanceStatus &= 0xf8ff; //~0x0700 可解除3种锁定，短路保护不可解除 + } + + + //更新了充电过流告警电流 + if(alarm_occ_old != paraMem.alarm_occ) + { + alarm_occ_old = paraMem.alarm_occ; + chgCurLimit_changeFlg = 1; + } + //更新了放电过流1告警电流 + if(alarm_ocd1_old != paraMem.alarm_ocd1) + { + alarm_ocd1_old = paraMem.alarm_ocd1; + dsgCurLimit_changeFlg = 1; + } + //更新了总体欠压告警电压 + if(alarm_puv_old != paraMem.alarm_puv) + { + alarm_puv_old = paraMem.alarm_puv; + dsgVolLimit_changeFlg = 1; + } + //充放电过流告警，影响逆变器充放电限流 + if((chgCurLimit_changeFlg == 1) || (dsgCurLimit_changeFlg == 1) || (dsgVolLimit_changeFlg == 1)) + { + //修改充电过流告警电流后，逆变器充电限流值=该值-10A + if(chgCurLimit_changeFlg == 1) + { + chgCurLimit_changeFlg = 0; + bmsMem.inverter_chgCurLimit = paraMem.alarm_occ * 10 - 100; + } + //修改放电过流1告警电流后，逆变器放电限流值=该值-10A + if(dsgCurLimit_changeFlg == 1) + { + dsgCurLimit_changeFlg = 0; + bmsMem.inverter_dsgCurLimit = paraMem.alarm_ocd1 * 10 - 100; + } + //修改总体欠压告警电压后，逆变器放电限压值=该值 + if(dsgVolLimit_changeFlg == 1) + { + dsgVolLimit_changeFlg = 0; + bmsMem.inverter_dsgVolLimit = paraMem.alarm_puv; + } + + //bmsMem中数据更新到FLASH A区和B区和AFE EEPORM + if((MEMORY_UpdateFlash(FLASH_DATA_A_BASE) == 0) && (MEMORY_UpdateFlash(FLASH_DATA_B_BASE) == 0)) + { + staPack.bits.flashUpdate = 0; + } + else + { + staPack.bits.flashUpdate = 1; + } + bmsMem.packStatus = staPack.byte; + } +} + +//分配地址过程中，地址变动很快，故单独拎出直接放while循环里 +void Addr_Set(void) +{ + if(bmsMem.write_Addr !=0) + { + if(bmsMem.write_Addr <= AddrMax) //范围判断 + { + EEPROM_WrMulByte(EE_ADDR,&bmsMem.write_Addr); + delay_ms(5); + + bmsMem.E2_485Addr = bmsMem.write_Addr; + bmsMem.write_Addr = 0; + + #if Addr_SetAuto + if(paraMem.addr_FREE_Flg == 0) + { + uint8_t tmp[2]={0,0}; + + //分配地址的状态(此时可接收队列标志位) + assignAddr_State = 2; + bmsMem.can_ArrayIndex = 0; + EEPROM_WrMulByte(EE_ASSIGN,tmp); + delay_ms(5); + } + #endif + + //改地址后，屏幕显示也对应修改 + scr_RdData_Index = bmsMem.E2_485Addr; + } + else + { + bmsMem.write_Addr = 0; + } + } + + //因IO3变动而清空队列标志 + if(ClearArray_Flag == 1) + { + uint8_t tmp[2]={0,0}; + + ClearArray_Flag = 0; + + EEPROM_WrMulByte(EE_ASSIGN,tmp); + delay_ms(5); + } + + #if Addr_SetAuto + if(paraMem.addr_FREE_Flg == 0) + { + //从机根据自身地址，决定IO2输出给下一从机的电平 + if((bmsMem.E2_485Addr >= 2) && (bmsMem.E2_485Addr <= AddrMax)) + { + IO2_OUTReset(); //正常地址的OUT引脚置低 + } + else if(bmsMem.E2_485Addr > AddrMax) + { + IO2_OUTSet(); //OUT引脚置高，让下一个从机进入等待 + } + } + else + { + IO2_OUTReset(); //所有地址保持置低 + } + #endif +} + +//休眠1的计时起点更新 +void SLEEP_Refresh(void) +{ + if(LSEErrFlag!=1) + sleeptimecount=RTC_GetCounter(); + else + sleep_Moni_Count=SLEEP_MON_CNT; +} + +//休眠2的计时起点更新 +void SLEEP2_Refresh(void) +{ + //满足休眠电压，无均衡，无电流 + if((cellVoltageMin <= sleep2Vol) && ((bmsMem.balanceStatus & 0x0001) == 0) && (bmsMem.packCurrent > (-200)) && (bmsMem.packCurrent < 200)) + { + //无除过压以外的保护 + if(((bmsMem.bStatus1 & 0x067e) == 0) && ((bmsMem.bStatus2 & 0x00ff) == 0) && ((bmsMem.bStatus3 & 0x0008) == 0) && ((bmsMem.temperaStatus & 0x0f7f) == 0)) + { + if(LSEErrFlag!=1) + sleep2timecount=RTC_GetCounter(); + else + sleep2_Moni_Count=SLEEP2_MON_CNT; + } + } +} + +//启动休眠1的定时 +#define SLEEP_MON_CNT 6000*(paraMem.sleep_min_disable&0x7FFF) //60*100个10ms=1min +uint32_t sleep_Moni_Count; +void SLEEP_TIM_Moni(void) +{ + //当没触发休眠 + if(sleep_flag == 0) + { + if((paraMem.sleep_min_disable & 0x8000) == 0) //0代表启用休眠 + { + sleep_Moni_Count--; + if(sleep_Moni_Count == 0) + { + sleep_Moni_Count = SLEEP_MON_CNT; + sleep_flag = 1; + + #if LTE_Conn + pre_sleep_flag = 2; + pre_sleep_waitCnt = 0; + sleepOn_time=timecount; + #endif + } + } + } +} + +//启动休眠2的定时 +#define SLEEP2_MON_CNT 6000*(paraMem.sleep2_min_disable&0x7FFF) //60*100个10ms=1min +uint32_t sleep2_Moni_Count; +void SLEEP2_TIM_Moni(void) +{ + //当没触发休眠 + if(sleep_flag == 0) + { + if((paraMem.sleep2_min_disable & 0x8000) == 0) //0代表启用休眠 + { + //满足休眠电压，无均衡，无电流 + if((cellVoltageMin <= sleep2Vol) && ((bmsMem.balanceStatus & 0x0001) == 0) && (bmsMem.packCurrent > (-200)) && (bmsMem.packCurrent < 200)) + { + //无除过压以外的保护 + if(((bmsMem.bStatus1 & 0x067e) == 0) && ((bmsMem.bStatus2 & 0x00ff) == 0) && ((bmsMem.bStatus3 & 0x0008) == 0) && ((bmsMem.temperaStatus & 0x0f7f) == 0)) + { + sleep2_Moni_Count--; + if(sleep2_Moni_Count == 0) + { + sleep2_Moni_Count = SLEEP2_MON_CNT; + sleep_flag = 1; + + #if LTE_Conn + pre_sleep_flag = 2; + pre_sleep_waitCnt = 0; + sleepOn_time=timecount; + #endif + } + } + } + } + } +} + +//欠压强制复位的定时 +#define UVOff_MON_CNT 30000 //5*60*100个10ms=5分钟 +uint16_t uvoff_Moni_Count; +void UVOff_TIM_Moni(void) +{ + //屏幕手动关欠压启动了 + if((bmsMem.balanceStatus & 0x20) != 0) + { + uvoff_Moni_Count--; + if(uvoff_Moni_Count == 0) + { + uvoff_Moni_Count = UVOff_MON_CNT; + bmsMem.balanceStatus &= 0xffdf; + } + } + else + { + uvoff_Moni_Count = UVOff_MON_CNT; + } +} + +//校准满充容量的倒计时(中间开关机，会关闭。但这是重要功能，需在晶振故障时仍有计时) +#define FCCCALI_MON_CNT 6000*(paraMem.cali_min_disable&0x7FFF) //60*100个10ms=1min +uint32_t fcc_Cali_Moni_Count; +void FCCCali_TIM_Moni(void) +{ + //倒计时12h + if(fcc_CaliStartFlag == 1) + { + fcc_Cali_Moni_Count--; + if(fcc_Cali_Moni_Count == 0) + { + fcc_Cali_Moni_Count = FCCCALI_MON_CNT; + fcc_CaliStartFlag = 0; + } + } + else + { + fcc_Cali_Moni_Count = FCCCALI_MON_CNT; + } +} + +//更新软件版本 +void Refresh_FirmwareVersion(void) +{ + if(VersionMem.Software[2] < 0xA0) + { + sprintf(FirmwareVersion, "%u.%u.%u.%u", VersionMem.Software[0], VersionMem.Software[1], VersionMem.Software[2], VersionMem.Software[3]); + } + else + { + sprintf(FirmwareVersion, "%u.%u.%02X.%u",VersionMem.Software[0], VersionMem.Software[1],VersionMem.Software[2], VersionMem.Software[3]); + } +} + +//更新硬件版本 +void Refresh_HardwareVersion(void) +{ + if(VersionMem.Hardware[2] < 'A') + { + sprintf(HardwareVersion, "%u.%u.%u", VersionMem.Hardware[0], VersionMem.Hardware[1], VersionMem.Hardware[2]); //最后1位是数字 + } + else + { + sprintf(HardwareVersion, "%u.%u.%c", VersionMem.Hardware[0], VersionMem.Hardware[1], VersionMem.Hardware[2]); //最后1位是字符 + } +} + +//更新屏幕版本 +void Refresh_ScreenVersion(void) +{ + if(VersionMem.Screen == 0) + { + memset(ScreenVersion, 0, 6); //清空 + } + else + { + uint8_t data = VersionMem.Screen; + uint8_t list1=0,list2=0; + + //最高两位_00对应028，01对应035，10对应042，11对应070 + if((data>>6 == 0x00) && (data >= 0x04)) + { + list1 = 28; + list2 = (data & 0x3f) +1-4; + } + else if(data>>6 == 0x01) + { + list1 = 35; + list2 = (data & 0x3f) +1; + } + else if(data>>6 == 0x02) + { + list1 = 43; + list2 = (data & 0x3f) +1; + } + else if(data>>6 == 0x03) + { + list1 = 70; + list2 = (data & 0x3f) +1; + } + + if(list2 < 10) + { + sprintf(ScreenVersion, "0%u0%u", list1, list2); + } + else + { + sprintf(ScreenVersion, "0%u%u", list1, list2); + } + } +} + +//更新BMS_SN +void Refresh_BMS_SN(void) +{ + uint8_t i; + + //固定9位数字 + for(i=0;i<9;i++) + { + sprintf(&BMS_SN[i], "%c", VersionMem.BMS_SN[i]); + } +} + +//更新PACK_SN +void Refresh_PACK_SN(void) +{ + uint8_t i; + + //最大共15字节，不足填充0xff + for(i=0;i<15;i++) + { + if(VersionMem.PACK_SN[i] == 0xff) break; + sprintf(&PACK_SN[i], "%c", VersionMem.PACK_SN[i]); + } +} + +#if LTE_Conn +//默认值 +#define DOMAIN domain_TianChu +#define PORT 1883 +#define USERNAME username +#define PASSWORD password + +char domain_TianChu[] = "tcp://mqtt.ricnsmart.com"; //天储平台 +char username[] = "device"; +char password[] = "E6Mk2Rj6uhFU4Zgy3kWCbghvaDYka8Dz"; +//char clientId[] = "jdg0bcu4RMG!rmt0ubv"; //任意长度，所以改为和SN号一致 + +//4G通信凭证跟随SN号变动，更新到Flash +void LTE_4G_Domain_ChangeSN(void) +{ + uint8_t i; + + //清空原值 + memset(&VersionMem.ClientID[0], 0, 23); + + //改动ClientID=SN号 + for(i=0;i<9;i++) + { + VersionMem.ClientID[i] = VersionMem.BMS_SN[i]; + } + + //计算CRC校验值 + static uint8_t temp[HOSTMEM_LEN]; + memcpy(temp, &VersionMem.host[0], HOSTMEM_LEN); + + VersionMem.hostAll_crc = CRC8_Cal(&temp[0], 153); + + //更新Flash + if((MEMORY_UpdateFlash(FLASH_DATA_A_BASE) == 0) && (MEMORY_UpdateFlash(FLASH_DATA_B_BASE) == 0)) + { + staPack.bits.flashUpdate = 0; + } + else + { + staPack.bits.flashUpdate = 1; + } + bmsMem.packStatus = staPack.byte; +} + +//4G通信凭证开机初始化 +uint8_t Host_Def_Flag; //用默认值填充Host的标志 +uint8_t Port_Def_Flag; //用默认值填充Port的标志 +uint8_t UserName_Def_Flag; //用默认值填充UserName的标志 +uint8_t Password_Def_Flag; //用默认值填充Password的标志 +uint8_t ClientID_Def_Flag; //用SN号填充ClientID的标志 +void LTE_4G_Domain_Init(void) +{ + uint8_t i; + + //若发现Host的内容为空，将默认值填充 + Host_Def_Flag = 1; + for(i=0;i<40;i++) + { + if(VersionMem.host[i] != 0x00) + { + Host_Def_Flag = 0; + break; + } + } + if(Host_Def_Flag == 1) + { + uint8_t *data = (uint8_t *)DOMAIN; + + i = 0; + while(data[i] != (uint8_t)'\0') + { + VersionMem.host[i] = data[i]; + i++; + } + } + + //若发现Port的内容为空，将默认值填充 + if(VersionMem.port == 0x0000) + { + Port_Def_Flag = 1; + VersionMem.port = PORT; + } + + //若发现UserName的内容为空，将默认值填充 + UserName_Def_Flag = 1; + for(i=0;i<40;i++) + { + if(VersionMem.UserName[i] != 0x00) + { + UserName_Def_Flag = 0; + break; + } + } + if(UserName_Def_Flag == 1) + { + uint8_t *data = (uint8_t *)USERNAME; + + i = 0; + while(data[i] != (uint8_t)'\0') + { + VersionMem.UserName[i] = data[i]; + i++; + } + } + + //若发现Password的内容为空，将默认值填充 + Password_Def_Flag = 1; + for(i=0;i<40;i++) + { + if(VersionMem.PassWord[i] != 0x00) + { + Password_Def_Flag = 0; + break; + } + } + if(Password_Def_Flag == 1) + { + uint8_t *data = (uint8_t *)PASSWORD; + + i = 0; + while(data[i] != (uint8_t)'\0') + { + VersionMem.PassWord[i] = data[i]; + i++; + } + } + + //若发现ClientID的内容为空，直接填充SN号 + ClientID_Def_Flag = 1; + for(i=0;i<23;i++) + { + if(VersionMem.ClientID[i] != 0x00) + { + ClientID_Def_Flag = 0; + break; + } + } + if(ClientID_Def_Flag == 1) + { + for(i=0;i<9;i++) + { + VersionMem.ClientID[i] = VersionMem.BMS_SN[i]; + } + } + + //任意一个改动，写入Flash + if((Host_Def_Flag == 1) || (Port_Def_Flag == 1) || (UserName_Def_Flag == 1) || (Password_Def_Flag == 1) || (ClientID_Def_Flag == 1)) + { + //计算CRC校验值 + static uint8_t temp[HOSTMEM_LEN]; + memcpy(temp, &VersionMem.host[0], HOSTMEM_LEN); + + VersionMem.hostAll_crc = CRC8_Cal(&temp[0], 153); + + //更新Flash + if((MEMORY_UpdateFlash(FLASH_DATA_A_BASE) == 0) && (MEMORY_UpdateFlash(FLASH_DATA_B_BASE) == 0)) + { + staPack.bits.flashUpdate = 0; + } + else + { + staPack.bits.flashUpdate = 1; + } + bmsMem.packStatus = staPack.byte; + } +} +#endif + +//各种初始默认值 +void uf_GLOBAL_Init(void) +{ + uint8_t i; + uint8_t tmpRd[16]; //用于读SN号 + + //初始值，之后会刷新 + bmsMem.ucCellNum = 16; + bmsMem.cycleCount = 0; + bmsMem.soh = 99; + + + //根据配置读取 + fcc = 10000; + bmsMem.ncc = 10000; + bmsMem.rcc = 5000; + bmsMem.soc = 50; + //bmsMem.E2uiDsgEndVol = 2500;//4.21修改 + //for(i=0;i<10;i++) + //{ + // bmsMem.E2uiVOC[i] = bmsMem.E2uiDsgEndVol+100*(i+1); + //} + + bmsMem.temperaStatus = 0; + bmsMem.balanceStatus = 0; + bmsMem.packStatus = 0; + bmsMem.bStatus1 = 0; + bmsMem.bStatus2 = 0; + bmsMem.bStatus3 = 0; + + + //校准数据初始化 + cali.current = 100000; //用于计算增益参数 + + cali.cmdZero = 0; + cali.cmdGain = 0; + cali.flagWrZeroToEE = 0; + cali.flagWrGainToEE = 0; + + cali.cadcZero = 0; + cali.cadcGain = 0; + cali.cadcZero = EEPROM_CALI_RdZero(); + delay_ms(20); + cali.cadcGain = EEPROM_CALI_RdGain(); + delay_ms(20); + + bmsMem.cadcZero = cali.cadcZero; + bmsMem.cadcGain = cali.cadcGain; + + + //[宁化]参数更新同步 + alarm_occ_old = paraMem.alarm_occ; + alarm_ocd1_old = paraMem.alarm_ocd1; + alarm_puv_old = paraMem.alarm_puv; + + + #if Addr_SetAuto + //延时2s进行485通信 + assignAddr_relay = 2; + #endif + + + //上位机求取数据的地址，只对主机有效默认是自身1 + ConfigData_Index = 1; + //屏幕显示数据地址，每块BMS的屏幕都显示 + scr_RdData_Index = bmsMem.E2_485Addr; + + //开机初始化，屏幕记录要读数据并显示出来 + scr_RdRecord_Flg = 1; + + + //该程序的软件版本号 + VersionMem.Software[0] = 4; //大版本，有硬件不兼容项才变 + VersionMem.Software[1] = 0; //客户对应出货单号 + VersionMem.Software[2] = 0; //程序更新次数 A表示4G B表示蓝牙 C表示WIFI + VersionMem.Software[3] = 0; //程序后续小修改 + //软件版本以当前程序的为准 + EEPROM_RdMulByte(EE_Software,tmpRd); + if((tmpRd[0] != VersionMem.Software[0]) || (tmpRd[1] != VersionMem.Software[1]) || (tmpRd[2] != VersionMem.Software[2]) || (tmpRd[3] != VersionMem.Software[3])) //软件不是当前值，就进行写入 + { + EEPROM_WrMulByte(EE_Software,VersionMem.Software); + delay_ms(5); + } + //填充FirmwareVersion + Refresh_FirmwareVersion(); + + //该程序的硬件版本号 + VersionMem.Hardware[0] = 1; + VersionMem.Hardware[1] = 0; + VersionMem.Hardware[2] = 0; + //硬件版本号以EEPROM里面的为准，上面这个只做参考 + EEPROM_RdMulByte(EE_Hardware,tmpRd); + if(tmpRd[0] == 0xff) //硬件的第1位不存在 + { + EEPROM_WrMulByte(EE_Hardware,VersionMem.Hardware); + delay_ms(5); + } + else + { + VersionMem.Hardware[0] = tmpRd[0]; + VersionMem.Hardware[1] = tmpRd[1]; + VersionMem.Hardware[2] = tmpRd[2]; + } + //填充HardwareVersion + Refresh_HardwareVersion(); + + + //显示屏幕版本号 + //最高两位表示型号，01对应035，10对应043，11对应070 + //剩下6位表示序号Index，范围0~63，显示为1~64 + EEPROM_RdMulByte(EE_Screen,tmpRd); + if(tmpRd[0] != 0xff) + { + VersionMem.Screen = tmpRd[0]; + } + else + { + VersionMem.Screen = 0x00+37; //对应02834，也即2.8寸陶晶驰版 + } + //填充ScreenVersion + Refresh_ScreenVersion(); + + //显示BMS_SN号 + EEPROM_RdMulByte(EE_BMS_SN,tmpRd); + VersionMem.BMS_crc8 = CRC8_Cal(&tmpRd[0],9); + if(tmpRd[9] == VersionMem.BMS_crc8) //crc校验正确 + { + for(i=0;i<9;i++) + { + VersionMem.BMS_SN[i] = tmpRd[i]; + } + //填充BMS_SN + Refresh_BMS_SN(); + } + else + { + //清零 + memset(VersionMem.BMS_SN, 0, 9); + VersionMem.BMS_crc8 = 0; + + memset(BMS_SN, 0, 9); + } + + //显示PACK_SN号 + EEPROM_RdMulByte(EE_PACK_SN,tmpRd); + VersionMem.PACK_crc8 = CRC8_Cal(&tmpRd[0],15); + if(tmpRd[15] == VersionMem.PACK_crc8) //crc校验正确 + { + //最大共15字节，不足填充0xff + for(i=0;i<15;i++) + { + VersionMem.PACK_SN[i] = tmpRd[i]; + } + //填充PACK_SN + Refresh_PACK_SN(); + } + else + { + //清零 + memset(VersionMem.PACK_SN, 0, 15); + VersionMem.PACK_crc8 = 0; + + memset(PACK_SN, 0, 15); + } + + #if LTE_Conn + //显示4G凭证 + LTE_4G_Domain_Init(); + #endif +} + diff --git a/USER/global.h b/USER/global.h new file mode 100644 index 0000000..2a4126d --- /dev/null +++ b/USER/global.h @@ -0,0 +1,1699 @@ +/** + ****************************************************************************** + * @file global.h + * @author Jerry Cai + * @version V2.1 + * @date 19-April-2022 + * @brief This file contains all the functions prototypes for the GPIO + * firmware library. + ****************************************************************************** + * @attention + * + + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __GLOBAL_H +#define __GLOBAL_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" +#include "AFE_SH3673520.h" + +//特殊功能选择 +#define Key_PressLong 0 //按钮 0:短按模式 1:长按模式 +#define Key_PressRST 0 //按钮复位 0:禁用 1:启用 +#define Addr_SetAuto 1 //地址 0:手动分配 1:全自动分配地址 +#define DO2_Warm 0 //充电低温触发打开加热继电器 0:禁用 1:启用 +//三选一小板 +#define BLE_Conn 1 +#define WIFI_Conn 0 +#define LTE_Conn 0 + + +//6.3.LW的100A/150A版，AFE采样电阻是9个1mΩ，对应9倍 +//6.3.LW的200A版，AFE采样电阻是18个1mΩ，对应18倍 +//20020SF_V1.0采样电阻是18个1mΩ，对应18倍 +//同步修改的有AFE电流保护参数，还有默认增益系数 +#define AFE_Multiple 18 + +//参数改动涉及①Flash存储参数、②AFE写入参数、③SDWA默认参数、④特殊限流值 +//达到充电过压报警后，发逆变器的充电限流(*个数)：100A对应20A，150A对应30A，200A对应40A +#define Inv_curlimit 400 + + +//在Flash占用地址长度 +#define AFE_MCU_LEN 52 //bmsMem参数 +#define PARAMEM_LEN 32*6 //paraMem参数 485地址:0x00-0x6F +#define HOSTMEM_LEN 32*5 //4G连接参数 485地址:0x20-0x8F + + +//EEPROM数据_IAP标志 +#define EE_IAP 0x00,0x01,1 //IAP定位标志用的值(在用户程序里不启用) +#define EE_IAP_NEW1 0x02,0xFF,1 //IAP新位置1 +#define EE_IAP_NEW2 0x03,0xFF,1 //IAP新位置2 +#define EE_OTA_FINE 0x00,0xFF,1 //4G远程升级完成标志 + +//EEPROM数据_OTA升级标志 +#define EE_OTA_FINE 0x00,0xFF,1 //4G远程升级完成标志 + +//EEPROM数据_不可初始化 +#define EE_ADDR 0x00,0x00,1 //485通信地址 +#define EE_IAP 0x00,0x01,1 //IAP定位标志用的值(在用户程序里不启用) +#define EE_LANG 0x00,0x02,1 //屏幕语言 0：英文 1：中文 +#define EE_NO_UV 0x00,0x03,1 //在“欠压复位”前的欠压保护值 +#define EE_ASSIGN 0x00,0x04,2 //自动分配的随机队列标志 +#define EE_CALI_ZERO 0x00,0x08,4 //零点校准 +#define EE_CALI_GAIN 0x00,0x0C,4 //增益校准 +#define EE_Screen 0x00,0x10,1 //屏幕号 +#define EE_Hardware 0x00,0x12,3 //硬件版本号 +#define EE_Software 0x00,0x18,4 //软件版本号 +#define EE_BMS_SN 0x00,0x20,10 //BMS SN号，外加一个crc8校验码 9字节+1CRC +#define EE_PACK_SN 0x00,0x30,16 //PACK SN号，外加一个crc8校验码 15字节(开放到最大)+1CRC +#define EE_OTA_FINE 0x00,0xFF,1 //4G远程升级完成标志 +//EEPROM数据_备用数据 +#define EE_TIME_BACKUP 0x01,0x00,6 //每次开机，若时间异常则录入该备份时间 +#define EE_TIME_OCV 0x01,0x10,4 //每次开机，读取该值判断是否该执行OCV校准 +//EEPROM数据_特殊按钮初始化 +#define EE_NCC 0x02,0x00,2 //额定容量 +#define EE_SOC 0x02,0x02,1 //电量SOC +#define EE_PROTOCOL 0x02,0x03,1 //协议 +#define EE_CUMULI 0x02,0x04,2 //累积容量 +#define EE_CYCLE 0x02,0x06,2 //循环次数 +#define EE_SOH 0x02,0x08,1 //健康系数 +#define EE_CUMULI_2 0x02,0x14,2 //累积容量(备份) +#define EE_CYCLE_2 0x02,0x16,2 //循环次数(备份) +#define EE_IAP_NEW1 0x02,0xFF,1 //IAP新位置1 +//EEPROM数据_特殊功能需要 +#define EE_FCC 0x03,0x00,8 //满充容量，单位mAS +#define EE_FCC_TIME 0x03,0x08,4 //校准满充容量的起始时间 +#define EE_UNSUB 0x03,0x0F,1 //取消绑定原主题标志 +#define EE_IAP_NEW2 0x03,0xFF,1 //IAP新位置2 +//EEPROM数据_ParaMem有效数据_升级初始化 +#define EE_PARA_ALL 0x04,0x00,PARAMEM_LEN //ParaMem当前范围 +//EEPROM数据_报警记录相关 +#define EE_SOE_INF 0x08,0x00,8 //报警记录信息(总)：当前序号、当前记录地址、当前记录总数 +#define EE_SOE_NUM 0x08,0x04,4 //当前序号 +//EEPROM数据_报警记录,位置根据变量adrh,adrl决定 +#define EE_SOE adrh,adrl,64 +//EEPROM def - SOE extend cell17~20 voltage(6 bytes per record, addr=0x2900+index*6) +#define EE_SOE_EXT adrh,adrl,6 +//EEPROM数据处理_清空扇区 +#define EE_CLEAR adrh,adrl,64 +//EEPROM clear - SOE extend cell17~20 voltage +#define EE_CLEAR_EXT adrh,adrl,6 + + +#define BIT0 (0x1<<0) +#define BIT1 (0x1<<1) +#define BIT2 (0x1<<2) +#define BIT3 (0x1<<3) +#define BIT4 (0x1<<4) +#define BIT5 (0x1<<5) +#define BIT6 (0x1<<6) +#define BIT7 (0x1<<7) +#define BIT8 (0x1<<8) +#define BIT9 (0x1<<9) +#define BIT10 (0x1<<10) +#define BIT11 (0x1<<11) +#define BIT12 (0x1<<12) +#define BIT13 (0x1<<13) +#define BIT14 (0x1<<14) +#define BIT15 (0x1<<15) + + +#define CAN_TIMEOUT_COUNT 5000 +#define SLEEP_MON_CNT 6000*(paraMem.sleep_min_disable&0x7FFF) //60*100个10ms=1min +#define SLEEP2_MON_CNT 6000*(paraMem.sleep2_min_disable&0x7FFF) //60*100个10ms=1min +#define UVOff_MON_CNT 30000 //5*60*100个10ms=5分钟 +#define FCCCALI_MON_CNT 6000*(paraMem.cali_min_disable&0x7FFF) //60*100个10ms=1min + +#define sleep2Vol paraMem.sleep2_vol //休眠方案2对应休眠电压，单位1mV + +#define AddrMax 20 +#define ProtocolSum 24 //实际存储协议数量 +#define ProtocolIdxSum 40 //协议对应序号范围 + + +/*三选一小板，状态/保护/报警的标志位*/ +//状态 +#define ChargeStatus ((bmsMem.bStatus3 & BIT7) != 0) +#define DischargeStatus ((bmsMem.bStatus3 & BIT6) != 0) +#define PreChargeStatus ((bmsMem.bStatus3 & BIT5) != 0) +#define ChgMosStatus ((bmsMem.bStatus3 & BIT1) != 0) +#define DsgMosStatus ((bmsMem.bStatus3 & BIT0) != 0) +#define PchgMosStatus ((bmsMem.bStatus3 & BIT2) != 0) +#define ChgLimitStatus ((bmsMem.balanceStatus & BIT4) != 0) +#define BalanceStatus ((bmsMem.balanceStatus & BIT0) != 0) +//特殊状态 +#define LockOCC ((bmsMem.balanceStatus & BIT10) != 0) +#define LockOCD1 ((bmsMem.balanceStatus & BIT9) != 0) +#define LockOCD2 ((bmsMem.balanceStatus & BIT8) != 0) +#define LockSP ((bmsMem.balanceStatus & BIT6) != 0) +#define LockSC ((bmsMem.balanceStatus & BIT7) != 0) +#define ChgMosFault ((bmsMem.bStatus2 & BIT7) != 0) +#define DsgMosFault ((bmsMem.bStatus2 & BIT6) != 0) +#define DOStatus ((bmsMem.temperaStatus & BIT7) != 0) +#define ForceOffUV ((bmsMem.balanceStatus & BIT5) != 0) + +//电压保护 +#define PackOV ((bmsMem.bStatus1 & BIT8) != 0) +#define PackUV ((bmsMem.bStatus1 & BIT9) != 0) +#define CellOV ((bmsMem.bStatus1 & BIT0) != 0) +#define CellUV ((bmsMem.bStatus1 & BIT1) != 0) +#define PF ((bmsMem.bStatus1 & BIT6) != 0) +#define L0V ((bmsMem.bStatus3 & BIT3) != 0) +//电流保护 +#define OCC ((bmsMem.bStatus1 & BIT4) != 0) || ((bmsMem.temperaStatus & BIT4) != 0) +#define OCD1 ((bmsMem.bStatus1 & BIT2) != 0) || ((bmsMem.temperaStatus & BIT5) != 0) +#define OCD2 ((bmsMem.bStatus1 & BIT3) != 0) || ((bmsMem.bStatus1 & BIT10) != 0) +#define SP ((bmsMem.bStatus1 & BIT5) != 0) +#define SC ((bmsMem.bStatus2 & BIT4) != 0) +//温度保护 +#define McuOTC ((bmsMem.temperaStatus & BIT0) != 0) +#define McuOTD ((bmsMem.temperaStatus & BIT1) != 0) +#define McuUTC ((bmsMem.temperaStatus & BIT2) != 0) +#define McuUTD ((bmsMem.temperaStatus & BIT3) != 0) +#define AmbientOTC ((bmsMem.temperaStatus & BIT8) != 0) +#define AmbientOTD ((bmsMem.temperaStatus & BIT9) != 0) +#define AmbientUTC ((bmsMem.temperaStatus & BIT10) != 0) +#define AmbientUTD ((bmsMem.temperaStatus & BIT11) != 0) +#define MosOTC ((bmsMem.bStatus2 & BIT1) != 0) +#define MosOTD ((bmsMem.bStatus2 & BIT3) != 0) +#define MosUTC ((bmsMem.bStatus2 & BIT0) != 0) +#define MosUTD ((bmsMem.bStatus2 & BIT2) != 0) + +//电压报警 +#define PackOVWarning ((bmsMem.bStatus3 & BIT10) != 0) +#define PackUVWarning ((bmsMem.bStatus3 & BIT11) != 0) +#define CellOVWarning ((bmsMem.bStatus3 & BIT8) != 0) +#define CellUVWarning ((bmsMem.bStatus3 & BIT9) != 0) +//电流报警 +#define OCCWarning ((bmsMem.bStatus3 & BIT12) != 0) +#define OCDWarning ((bmsMem.bStatus3 & BIT13) != 0) +//温度报警 +#define McuOTCWarning ((bmsMem.bStatus2 & BIT12) != 0) +#define McuOTDWarning ((bmsMem.bStatus2 & BIT13) != 0) +#define McuUTCWarning ((bmsMem.bStatus2 & BIT14) != 0) +#define McuUTDWarning ((bmsMem.bStatus2 & BIT15) != 0) +#define AmbientOTCWarning ((bmsMem.temperaStatus & BIT12) != 0) +#define AmbientOTDWarning ((bmsMem.temperaStatus & BIT13) != 0) +#define AmbientUTCWarning ((bmsMem.temperaStatus & BIT14) != 0) +#define AmbientUTDWarning ((bmsMem.temperaStatus & BIT15) != 0) +#define MosOTCWarning ((bmsMem.bStatus2 & BIT8) != 0) +#define MosOTDWarning ((bmsMem.bStatus2 & BIT9) != 0) +#define MosUTCWarning ((bmsMem.bStatus2 & BIT10) != 0) +#define MosUTDWarning ((bmsMem.bStatus2 & BIT11) != 0) + + +/*三选一小板，公共常量*/ +#define SETPARA_SUM 34 //可写参数总个数 +#define GETPARA_SUM 34 //可读参数总个数 + + +/*三选一小板，公共变量*/ +extern char BMS_SN[10]; //9Byte +extern char PACK_SN[16]; //1~15Byte +extern char FirmwareVersion[11];//"4.00.00.00" 7~10Byte +extern char HardwareVersion[6]; //"6.3.L" 5Byte +extern char ScreenVersion[6]; //"03513" 5Byte + +extern const char* Status[2]; //0对应false, 1对应true + +extern char params_str[600]; //原始数据字符串 + +extern const char* putSrvc_reply_namestr; //写服务的名字字符串 +extern const char* putSrvc_reply_str; //写服务的字符串格式 +extern uint8_t putSrvc_reply_flg; //写服务回复标志 接收到ID号，就要以ID号的格式返回 + +extern const char* setPara_reply_name[SETPARA_SUM]; //写属性的名字字符串 +extern uint16_t setPara_reply_temp[SETPARA_SUM]; //写属性的数值 +extern uint8_t setPara_reply_pm[SETPARA_SUM]; //数值的正负 0：正数 1：负数 2：true 3：false +extern uint8_t setPara_reply_flg; //写属性回复标志 1:回复成功 0xAA:设备无所有要写的属性 0xBB:值不在范围，设备拒绝执行 +extern uint8_t setPara_reply_num; //写属性回复个数 + +extern const char* getPara_reply_name[GETPARA_SUM]; //读属性的名字字符串 +extern uint16_t getPara_reply_temp[GETPARA_SUM]; //读属性的数值 +extern uint8_t getPara_reply_pm[GETPARA_SUM]; //数值的正负 0：正数 1：负数 2：true 3：false +extern uint8_t getPara_reply_flg; //读属性回复标志 1:回复成功 0xAA:设备无所有要读的属性 +extern uint8_t getPara_reply_num; //读属性回复个数 + +extern uint8_t protocol_reply_flg; //协议在回复内容里的标志 +extern uint8_t protocol_reply_index; //协议在回复内容里的位置 + +extern uint8_t RTC_UpdateFlag; //起始点刷新标志位，用以刷新休眠和欠压强制复位的时间 + +extern uint8_t LTE_WarmDelay; //4G模块开机等待时间 + +#define ResendTime 2 +extern uint8_t LTE_ResendDelay; //4G模块对当前指令无回复，重试等待倒计时 + +#define WaitRxTime 2 +extern uint8_t LTE_WaitRxDelay; //4G模块对当前指令无回复，重新发送等待倒计时 +extern uint8_t LTE_WaitRxFlg; //已执行过的标志 + +extern uint8_t incident_flag; //4G上报_要执行上报事件的标志 +extern uint8_t incident_DataFlg; //4G上报_要上报发生事件时的数据的标志 2:保护 1:其他 0:不用记录 + +extern const char* incident_str; +extern uint8_t incident_len; +extern uint32_t incident_time; + + +/*变量*/ +extern uint8_t curLimitFlag; + +extern uint8_t bDSGING; //放电状态标记 +extern uint8_t bCHGING; //充电状态标记 +extern uint8_t bSTANDBY; //待机状态标记 +extern uint8_t modbusFaaRxFlg; //CADC零点校准数据接收正确标记 +extern uint8_t modbusFbbRxFlg; //CADC增益校准数据接收正确标记 +extern uint8_t modbus1FaaRxFlg; //CADC零点校准数据接收正确标记 +extern uint8_t modbus1FbbRxFlg; //CADC增益校准数据接收正确标记 + +extern uint8_t protocol; //逆变器通信协议 + +extern CanTxMsg TxMessage[20]; +extern CanRxMsg RxMessage; +extern uint8_t TxMailBox[20]; +extern uint8_t CAN_SendCount; + +extern int16_t TemperatureAverage; // 平均温度 +extern int16_t TemperatureMax; // 最高温度 +extern int16_t TemperatureMin; // 最低温度 +extern uint16_t TemperatureMaxIndex; // 最高温度序号 +extern uint16_t TemperatureMinIndex; // 最低温度序号 + +extern uint16_t ncc_Ah; //额定容量，单位1Ah +extern uint16_t fcc_Ah; //满充容量，单位1Ah +extern uint16_t rcc_Ah; //剩余容量，单位1Ah +extern uint16_t oldrcc_Ah;//用于比较得出增长的值，单位1Ah + +extern uint8_t dsg_forbidFlg; //禁放标志，SOC小于10%的时候启用 +extern uint8_t chg_forbidFlg; //禁充标志，SOC大于100%的时候启用 +extern uint8_t chg_forceFlg; //强充标志，SOC小于10%的时候启用 +extern uint16_t RequestFlag; //充放电允许位 + +extern uint32_t timecount; //当前计时s + +extern uint8_t sleep_flag; //休眠执行标志位 +extern uint8_t sleep_enableflag;//开启休眠功能标志位 +extern uint32_t sleeptimecount; //休眠计时起点s +extern uint32_t sleep2timecount; //休眠2计时起点s + +extern uint32_t uvofftimecount; //关闭欠压功能后的计时起点 +extern uint16_t uvofftime; //关闭欠压功能的倒计时数 + +extern uint32_t ocvtimecount; //开路电压法的计时起点 +extern uint32_t ocvtime; //开路电压法的倒计时数 +extern uint8_t OCV_Wait_flag; //允许OCV校准走倒计时的标志 +extern uint8_t OCV_CaliSOC_flag;//允许执行OCV校准获取当前电压对应soc的标志 + +extern uint8_t Cali_Soc_Flag; +extern uint16_t CaliSocMoniCount; + +extern uint8_t TSC_Flag; //判断是真短路，要关闭预充的标志，显示“真短路保护” +extern uint8_t tscTimeCount; + +extern uint8_t PCHG_Flag; //开启预充功能的标志，不会随短路保护消失而恢复 +extern uint8_t pchgTimeCount; +extern uint32_t loadvol; + +extern uint8_t LSEErrFlag; //外部低频晶振有问题的标志，需要让屏幕的时间不再显示 + +extern uint32_t sleep_Moni_Count; +extern uint32_t sleep2_Moni_Count; +extern uint16_t uvoff_Moni_Count; + +extern uint16_t CTRL_Order; //上位机[临时]控制MOS关闭指令 + +extern uint8_t modbusCurDev; //主机当前的轮询对象，这里用来给屏幕轮询有个断点 + +extern uint8_t ConfigData_Index; //上位机求取数据对应地址 +extern uint8_t Online_Flag; //上位机求某从机数据，主机代发后收到回复的标志，=1才对上位机进行回复 + +extern uint8_t scr_WrZero_Flg; //屏幕写零点校准 +extern uint8_t scr_WrGain_Flg; //屏幕写增益校准 + +//extern uint8_t language; //屏幕语言 + +extern uint8_t scr_RdData_Index;//屏幕显示数据的地址，默认是自身addr，只有addr=1可以变化为其他地址 +extern uint8_t scr_RdRecord_Flg;//屏幕只可以查看自身记录；当记录更新/清空/收到清空指令/进记录页面/上下翻动时，才会读EEPROM更新一次屏幕记录内容 + +extern uint8_t sdwa_WrAddr; //屏幕通过主机写从机地址的值 +extern uint8_t sdwa_WrAddr_Flg; //屏幕通过主机写从机地址的标志 0不在写 1尝试中 2成功 3失败 + +#if Addr_SetAuto +extern uint8_t assignAddr_State; //按钮分配地址的状态 0未开始 1进行中 2结束 +extern uint8_t assignAddr_Step; //自动分配地址当前步骤 + +extern uint8_t assignAddr_relay; //主机开机后延时2s再开始通信，等待地址变化 +extern uint8_t assignAddr_485num; //分配地址后的在线个数，若存在从机才进行下发队列标志 +extern uint16_t assignAddr_random; //主机完成分配后生成的随机数(AddrMax+1~65535),用来识别队列 +extern uint8_t assignAddr_WrIndex_Flg; //主机执行下发队列标志数的标志 +#endif + +extern uint8_t cumuliCapClear_flag; //当上位机写入循环次数时，会清空累积容量 + +extern uint8_t OnlineNum; //BMS正常工作数量 + +extern uint8_t chg_curLimitNum; //充电限流置0的个数，SOC大于100%的时候启用 +extern uint8_t dsg_curLimitNum; //放电限流置0的个数，SOC小于10%的时候启用 +extern uint8_t chg_cur0Num; //因报警触发充电限流40A时，出现保护限流0A的个数 + +extern uint16_t cell_OV; //单体过压值 +extern uint16_t cell_UV; //单体欠压值 +extern uint16_t cell_OVR; //单体过压释放值 +extern uint16_t cell_UVR; //单体欠压释放值 + +extern uint8_t chg_curlimitFlg; //充电限流(固定40A)的标志，出现总体过压或单体过压的时候启用 + +extern uint8_t ClearEE[4]; //用于清空存在EEPROM的计时起点 +extern uint8_t tmpWrFCC[8]; //用于写入满充容量值 + +extern uint32_t fcc; //满充容量，单位mAS +extern uint8_t fcc_CaliStartFlag; //当开始充电时，如果此时SOC=0/1%，开始计时 + +extern uint32_t fcc_Calitimecount; //校准满充容量的计时起点 +extern uint32_t fcc_Calitime; //校准满充容量的倒计时数，超过则不可更新 + +extern uint32_t fcc_Cali_Moni_Count;//在晶振异常时，也能在中间不关机时进行校准 + +extern uint8_t PollStop_flag; //主机暂停发送轮询的标志位 +extern uint8_t PollStop_count; //主机暂停发送轮询的倒计时，再次收到则清零，30s + +extern uint8_t protocolSwitchFail; //选择的协议不存在的标志 +extern uint8_t protocolNum; +extern char protocolStrings[ProtocolSum][16]; + +extern uint8_t PCHG_startFlag; //开机预充标志 0:没执行 1:已完成 + +extern uint8_t TSC_detectFlag; //不开启预充时，AFE短路发生后，判断是否是真短路的标志 +extern uint8_t sc_OccurFlag; //浪涌短路出现过的标志 + +extern int16_t cellVol[20]; //20串电压 +extern int16_t cellVoltageMax; +extern int16_t cellVoltageMin; + +extern uint8_t MOS_Close_Flg; //需要控制MOS全关的标志 + +extern uint8_t sc_close_flag; //控制浪涌短路保护关闭的标志 + +//Wh版屏幕需要 +extern uint16_t cumuliCapacity; //累积容量，单位0.1Ah + +/*IAP_V3.0*/ +extern uint8_t IAP_Run; //执行程序时是否正常的标志 +/*IAP_V3.0*/ + +extern char BMS_SN[10]; //9Byte +extern char PACK_SN[16]; //1~15Byte +extern char FirmwareVersion[11];//"4.00.00.00" 7~10Byte +extern char HardwareVersion[6]; //"6.3.L" 5Byte +extern char ScreenVersion[6]; //"03513" 5Byte + +#if Key_PressLong +extern uint8_t ON_confirm_flg; //程序运行后，先确认开机 1:按键按下2s确认开机 2：确认开机后按键松开，可以监测下一次按键按下以判断复位和重启 +extern uint8_t RST_confirm_flg; //按钮按下后，通过时长判断执行复位 +extern uint8_t OFF_confirm_flg; //按钮按下后，通过时长判断确认断开电源维持，等按钮松开就关机 + +extern uint8_t power_old; //如果是正常工作时重启，保持开机 +extern uint8_t power_state; //电源脚输出 0：应输出低，1：应输出高 +#endif + +extern uint8_t curLimit_ctrlFlag; //执行限流开/关的标志 0:关限流 1:开限流 + +extern uint8_t ClearArray_Flag; //在定时器函数中，执行清空队列标志的标志 + +extern uint8_t Screen_RevFlg; +extern uint8_t Screen_RevCount; +extern uint8_t Screen_RevHandlerFlg; //在主函数执行分析处理 + +extern uint8_t MODBUS_RevFlg; +extern uint8_t MODBUS_RevCount; + +extern uint8_t MODBUS1_RevFlg; +extern uint8_t MODBUS1_RevCount; + +/*三选一模块*/ +#if BLE_Conn +extern uint8_t BLE_RevFlg; +extern uint8_t BLE_RevCount; +#endif +#if WIFI_Conn +extern uint8_t WIFI_RevFlg; +extern uint8_t WIFI_RevCount; +#endif +#if LTE_Conn +#define event_pub 0xA0 +#define srvc_pub 0xA1 +#define setPara_pub 0xA2 +#define getPara_pub 0xA3 + +extern uint8_t LTE_RevFlg; +extern uint8_t LTE_RevCount; + +extern uint8_t LTE_PinRST_Flag; + +extern uint8_t MQTT_RST_flag; //重启MQTT服务 0xAA:多次重启失败 +extern uint8_t MQTT_RST_step; //执行步骤 0~2:退出MQTT服务 + +extern uint8_t LTE_LINK_flag; //已连接到服务器的标志 + +extern uint8_t LTE_UNSUB_Flag;//需要先取消绑定的标志 + +extern uint8_t MQTT_START_flag; //执行连接MQTT服务器的标志 +extern uint8_t MQTT_READY_flag; //MQTT执行正常通信流程的标志 +extern uint8_t MQTT_timed_count; //定时上报[属性]的倒计时 +extern uint8_t LTE_status; //执行内容 +extern uint8_t LTE_step; //执行步骤 + +extern uint8_t LTE_sleep_flag; //4G也进入休眠标志 +extern uint8_t pre_sleep_flag; //休眠前置标志 +extern uint8_t pre_sleep_waitCnt; //休眠前置操作等待完成计数，若持续1min未执行结束，也直接跳到休眠最后一步：关闭4G + +extern uint32_t sleepOn_time; //启动休眠时间 +extern uint32_t sleepOff_time; //退出休眠时间 + +//屏幕显示对应特殊 +extern uint8_t LTE_rssi; //信号强度 +extern uint8_t LTE_Onlineflag; //4G模块联网标志 0:未联网 1:已联网 0xAA:错误，尝试重新联网解决 + +extern uint8_t LTEStatus_flg; //要传状态的标志 +extern char LTEStatus_str[41]; //4G状态文本 + +//OTA升级所需调用 +#define ERR_timeEnd2 60/2 //持续ERR后重启计数，因遇到ERR会2s后再发报文，所以/2 1min + +#define LTE_Send LTE_printf + +#define LTE_RX_BUF_LEN 1000 //接收的最大长度 +#define LTE_TX_BUF_LEN 2000 //发送的最大长度 + +extern char LTE_Rx_Buf[LTE_RX_BUF_LEN]; +extern char LTE_Tx_Buf[LTE_TX_BUF_LEN]; + +extern uint16_t LTE_Rx_BufIndex; + +extern uint8_t CRESET_flag; //重启 0xAA:多次重启失败 +extern uint8_t CRESET_step; //执行步骤 0~2:退出MQTT服务 3:重启 + +#define ask_lbs 0 +#define ask_lbs_step1 0 + +//OTA升级 +extern uint8_t LTE_OTA_Flag; //4G升级标志 1：收到升级相关报文 +extern uint8_t LTE_OTA_fineFlag; //4G升级完成上报标志(上线后先上报升级完成) 0xAA:升级成功 0xBB:维持原程序 + +extern uint8_t OTAfine_WrFlg; //更新OTA升级成功/失败标志的标志 0xAA:更新到0 0xBB:更新到0xBB +#endif + + +//global +typedef union +{ + uint8_t b8[2]; + uint16_t b16; +}BYTE2; + + +//because false can be 1 2 3..., so true =0 +typedef enum +{ + FALSE = 1, + TRUE = 0, +} BOOL_STATE; + +// +typedef struct +{ + uint8_t l0v :1; //低压禁止充电 + uint8_t deltavol:1; //压差保护 + uint8_t packuvp :1; //电池组欠压保护 + uint8_t packuvw :1; // + uint8_t pakcovp :1; + uint8_t pakcovw :1; + uint8_t celluvp :1; + uint8_t celluvw :1; + uint8_t cellovp :1; + uint8_t cellovw :1; + uint8_t rsvd :6; +}VOLTAGE_STATUS; + +typedef union +{ + VOLTAGE_STATUS bits; + uint16_t halfword; +}UNION_VOLTAGE_STATUS; + +// +typedef struct +{ + uint8_t sc :1; // + uint8_t ocd2p :1; // + uint8_t ocd1p :1; // + uint8_t ocdw :1; // + uint8_t occp :1; + uint8_t occw :1; + uint8_t dhg :1; + uint8_t chg :1; + uint8_t rsvd :8; +}CURRENT_STATUS; + +typedef union +{ + CURRENT_STATUS bits; + uint16_t halfword; +}UNION_CURRENT_STATUS; + +// +typedef struct +{ + uint8_t utdp :1; //放电低温保护 + uint8_t utdw :1; //放电低温报警 + uint8_t otdp :1; //放电高温保护 + uint8_t otdw :1; //放电高温报警 + uint8_t utcp :1; //充电低温保护 + uint8_t utcw :1; //充电低温报警 + uint8_t otcp :1; //充电高温保护 + uint8_t otcw :1; //充电高温报警 + uint8_t rsvd :8; +}TEMPERA_STATUS1; + +typedef union +{ + TEMPERA_STATUS1 bits; + uint16_t halfword; +}UNION_TEMPERA_STATUS1; + +// +typedef struct +{ + uint8_t T6_utp :1; //T6低温保护 + uint8_t T6_utw :1; //T6低温报警 + uint8_t T6_otp :1; //T6高温保护 + uint8_t T6_otw :1; //T6高温报警 + + uint8_t T5_utp :1; //T5低温保护 + uint8_t T5_utw :1; //T5低温报警 + uint8_t T5_otp :1; //T5高温保护 + uint8_t T5_otw :1; //T5高温报警 + + uint8_t T4_utp :1; //T4低温保护 + uint8_t T4_utw :1; //T4低温报警 + uint8_t T4_otp :1; //T4高温保护 + uint8_t T4_otw :1; //T4高温报警 + + uint8_t rsvd :4; +}TEMPERA_STATUS2; + +typedef union +{ + TEMPERA_STATUS1 bits; + uint16_t halfword; +}UNION_TEMPERA_STATUS2; + +// +typedef struct +{ + uint8_t dsg :1; // + uint8_t chg :1; // + uint8_t pchg :1; // + uint8_t rsvd0 :5; + uint8_t rsvd1 :8; +}MOSFET_STATUS; + +typedef union +{ + MOSFET_STATUS bits; + uint16_t halfword; +}UNION_MOSFET_STATUS; + +// +typedef struct +{ + uint8_t flashUpdate :1; //flash更新标志 + uint8_t eepromUpdate :1; //eeprom更新标志 + uint8_t rsvd0 :6; +}PACK_STATUS; + +typedef union +{ + PACK_STATUS bits; + uint8_t byte; +}UNION_PACK_STATUS; + +extern UNION_VOLTAGE_STATUS staVol; +extern UNION_CURRENT_STATUS staCur; +extern UNION_TEMPERA_STATUS1 staTemp1; +extern UNION_TEMPERA_STATUS2 staTemp2; +extern UNION_MOSFET_STATUS staMos; +extern UNION_PACK_STATUS staPack; + + +//OCV曲线数据结构体 +typedef struct +{ + uint8_t soc; // SOC百分比 + uint16_t ocv_dp; // DP模式静置电压(放电) + uint16_t ocv_cp; // CP模式静置电压(充电) +}OCV_Data; + +extern OCV_Data ocv_data[15]; + + +//注意结构体数据对齐，否则会莫名奇妙问题 +typedef struct +{ + //数据及状态采集 + uint16_t vCell[16]; // 电芯单体电压 mv + uint32_t packVoltage; // 电芯总电压 mv + int32_t packCurrent; // 实时电流 mA + uint16_t cellVoltageMax; // 电芯单体最高电压 mv + uint16_t cellVoltageMin; // 电芯单体最低电压 mv + uint16_t cellVoltageMaxIndex; // 电芯单体最高电压序号 + uint16_t cellVoltageMinIndex; // 电芯单体最低电压序号 + uint16_t afe_T1; // AFE测量温度 .c + uint16_t afe_T2; // AFE测量温度 .c + uint16_t afe_T3; // AFE测量温度 .c + uint16_t mcu_T1; // MCU测量温度 .c + uint16_t mcu_T2; // MCU测量温度 .c + uint16_t mcu_T3; // MCU测量温度 .c + uint16_t mcu_T4; // MCU测量温度 .c + int16_t cadcAveVal; // AFE电流初始值,用于电流零点校准 + uint32_t ncc; // 系统额定容量 mAS + uint32_t rcc; // 电池包当前剩余电量 mAS + uint16_t soc; // 电池包的剩余电量百分比 % + uint16_t cycleCount; // 累计放电次数 + uint16_t bStatus1; // + uint16_t bStatus2; // + uint16_t bStatus3; // + int16_t cadcZero; // 零点校准系数 + int16_t cadcGain; // 增益校准系数 + uint16_t temperaStatus; // 温度保护状态, BIT0-充电高温; BIT1-放电高温; BIT2-充电低温; BIT3放电低温 + uint16_t balanceStatus; // 主动均衡状态, BTI0-均衡开启; BIT1-均衡失败 + uint8_t packStatus; // + uint8_t soh; // *8.22新加：电池健康系数(原本的位置显示循环次数了，而原本的packStatus没真正启用过) + + //AFE 内部EEPROM 26bytes，数据同时备份到内部FLASH A B + uint8_t ee_sconf1; // 002EH + uint8_t ee_sconf2; + uint8_t ee_ovt_ldrt_ovh; // 002CH + uint8_t ee_ovl; + uint8_t ee_uvt_ovrh; + uint8_t ee_ovrl; + uint8_t ee_uv; + uint8_t ee_uvr; + uint8_t ee_balv; + uint8_t ee_prev; + uint8_t ee_l0v; + uint8_t ee_pfv; + uint8_t ee_ocd1v_ocd1t; + uint8_t ee_ocd2v_ocd2t; + uint8_t ee_scv_sct; + uint8_t ee_occv_occt; + uint8_t ee_most_ocrt_pft; + int8_t otc; + int8_t otcr; + int8_t utc; + int8_t utcr; + int8_t otd; + int8_t otdr; + int8_t utd; + int8_t utdr; + uint8_t ee_tr; //TR是温度内部参考电阻系数 + + //20230221------------------ + int8_t mcu_otc; + int8_t mcu_otcr; + int8_t mcu_utc; + int8_t mcu_utcr; + + int8_t mcu_otd; + int8_t mcu_otdr; + int8_t mcu_utd; + int8_t mcu_utdr; + + uint8_t mcu_occ; //charging over current + uint8_t mcu_ocd; //discharging over current + uint8_t mcu_occ_t; + uint8_t mcu_ocd_t; + uint8_t mcu_ocr_t; //过流保护恢复事件，255 - 不自动恢复 + uint8_t mcu_crc; + //20230221--------------- + + //20230614--------------- + uint8_t CHGLimit_Value; //通过上位机改变限流板保护电流 A //0x42 + uint8_t CHGLimit_Count; //通过上位机改变限流板保护时间 S + uint16_t CHGLimit_ReleaseCount; //通过上位机改变限流板保护恢复时间 S + //20230614--------------- + + //20230705--------------- + uint16_t inverter_chgVolLimit; //通过上位机修改通信给逆变器的限压限流值 + uint16_t inverter_dsgVolLimit; //单位0.1V + uint16_t inverter_chgCurLimit; + uint16_t inverter_dsgCurLimit; //单位0.1A + //20230705--------------- + + /**** 下面是写入过程数据,不需要上位机可读取 ****/ + //20230411--------------- + uint8_t write_Addr; //通过上位机改变板子的通信地址 + uint8_t addr_crc; + //20230411--------------- + + //20230523--------------- + uint16_t write_Capacity; //通过上位机改变电池容量显示 //10.12改成u16,范围上限65535 + //20230523--------------- + + //20231109--------------- + uint8_t write_Soc; //通过上位机改变板子的通信地址 + uint8_t soc_crc; + //20231109--------------- + + + //并机时主机通过485采集下面数据处理 + //保护字节和报警字节取或 + //SOC和SOH取平均 + //电流取累加 + //温度取MCU最大值 + uint16_t can_status_byte1; //0x4B 3.4 + uint16_t can_status_byte2; //5.6 + uint16_t can_status_byte3; //7.8 + uint16_t can_status_byte4; //9.10 + uint8_t can_soc; //12 + uint8_t can_soh; //11 + int16_t can_cur; //13.14 + int16_t can_temp; //15.16 + uint16_t can_VolMax; //17.18 电芯单体最高电压 mv + uint16_t can_VolMin; //19.20 电芯单体最低电压 mv + uint16_t can_VolMaxIndex; //21.22 电芯单体最高电压序号 + uint16_t can_VolMinIndex; //23.24 电芯单体最低电压序号 + int16_t can_TempMax; //25.26 最高温度 + int16_t can_TempMin; //27.28 最低温度 + uint16_t can_TempMaxIndex; //29.30 最高温度序号 + uint16_t can_TempMinIndex; //31.32 最低温度序号 + + uint16_t can_ArrayIndex; //33.34 主机下发队列序号，与自动分配地址相关 + + //Wh版屏幕，显示功率总耗 + uint16_t can_cumuliCap; //35.36 累计容量 + uint16_t can_cycleCnt; //37.38 循环次数 + + + //EEPROM AT24CXX数据 + uint16_t E2_485Addr; //485通讯地址 主机地址一般为1,从机地址顺序 + uint16_t E2_485Baud; //485通讯波特率，保留 + uint16_t E2_485Snum; //485从机数量 + + uint16_t E2uiChgEndVol; //充电截止电压 + uint16_t E2uiDsgEndVol; //放电截止电压 + uint16_t E2uiVOC[10]; //SOC标定电压值 + uint8_t ucCellNum; //BMS当前电池节数 + + //SH36735XX系列扩展电芯17~20电压 + uint16_t vCell2[4]; //电芯17~20电压 mv（仅SH36735XX使用） +}BMS_MEMORY ; + +//专门存储配置参数，对应功能码f3 f4 +typedef struct +{ + /** 读写地址0x00-0x0F EEPROM地址0x0400-0x041F **/ + //20240419 主动均衡参数(单读写) + uint8_t act_bal_startV; //0x00 开启压差 + uint8_t act_bal_stopV; // 释放压差 + uint16_t act_bal_stopT; //0x01 释放延时 + + //20240821 SOH计算参数(单) + uint8_t sohcali_transCent; //0x02 累积容量/循环次数的转换百分比 1~100 + uint8_t sohcali_minSOH; // 最低健康系数 + uint16_t sohcali_startTime; //0x03 100%对应的最大循环次数 + uint16_t sohcali_stopTime; //0x04 最大循环次数 + + //20241023 浪涌短路锁定参数(暂不读写) + uint8_t scWait_T; //0x05 浪涌短路消失后，对下一次浪涌短路的等待时间 单位1s + uint8_t scWaitNum; // 浪涌短路的持续次数，次数溢出显示“浪涌短路锁定” + + //20241023 预充参数(暂不读写) + uint8_t pchg_startTime; //0x06 开机预充延时 + uint8_t pchg_Time; // 开放电MOS前预充延时 + uint8_t pchg_scVol; //0x07 预充时的真短路判断电压 + uint8_t sp_scVol; // 浪涌短路时的真短路判断电压 + + //20250313 禁充/禁放/强充(单) + uint16_t requestFlg_enable; //0x08 启用请求标志的标志 bit7:充电允许 bit6:放电允许 bit5:强充 + uint8_t chg_forbid_Soc; //0x09 禁充开启SOC + uint8_t chg_forbid_rSoc; // 禁充释放SOC + uint8_t dsg_forbid_Soc; //0x0A 禁放开启SOC + uint8_t dsg_forbid_rSoc; // 禁放释放SOC + uint8_t chg_force_Soc; //0x0B 强充开启SOC + uint8_t chg_force_rSoc; // 强充释放SOC + + //20250402 满充方式和方式4参数(单) + uint8_t soc100_methods; //0x0C 满充方式使能 bit0:单芯过压 bit1:总体过压 bit2:逆变器限压+2A小电流 bit3:满充电压+截止电流 + uint8_t soc100_cur; // 截止电流默认5A，单位0.1A + uint16_t soc100_vol; //0x0D 满充电压默认56V，单位0.1V + + uint8_t rsvd0[4]; //0x0E-0x0F + + + /** 读写地址0x10-0x1F EEPROM地址0x0420-0x043F **/ + //20240513 长时间待机定时休眠(单) + uint16_t sleep_min_disable; //0x10 纯定时休眠 bit15:休眠禁用 bit0~14:休眠时间min + + //20240924 地址控制(暂不读写) + uint16_t addr_FREE_Flg; //0x11 地址手动控制标志，默认0 + + //20241023 充放启用[长期]控制，重启不可初始化(暂不读写) + uint16_t ctrl_disable; //0x12 bit0:关放电MOS bit1:关充电MOS bit2:关预充 [驻启使用bit3] + + //20250519 满充容量校准 + uint16_t cali_min_disable; //0x13 bit15:满充容量校准禁用 bit0-14:等待时间 + + //20250402 低电压待机定时休眠(单) + uint16_t sleep2_min_disable;//0x14 bit15:休眠2禁用 bit0~14:休眠时间min + uint16_t sleep2_vol; //0x15 低电压休眠电压 + + //20250410 定时校准SOC-开路电压法(单) + uint16_t ocv_min_disable; //0x16 bit15:定时校准禁用 bit0~14:定时时间min + uint8_t ocv_soc_Range; //0x17 定时校准的赋值SOC范围 + uint8_t ocv_T_Range; // 定时校准的赋值温度范围 + + uint16_t temp_disable; //0x18 bit0~4:电池温度1~4的失效开/关控制 + + uint8_t rsvd1[14]; //0x19-0x1F [0x18~0x1C驻启有参数] + + + /** 读写地址0x20-0x2F EEPROM地址0x0440-0x045F **/ + //20250404 总体过压欠压保护(总读写) + uint16_t pack_ovv; //0x20 总体过压保护 单位0.1V + uint16_t pack_ovrv; //0x21 总体过压保护释放 单位0.1V + uint16_t pack_uvv; //0x22 总体欠压保护 单位0.1V + uint16_t pack_uvrv; //0x23 总体欠压保护释放 单位0.1V + uint8_t pack_ovt; //0x24 总体过压保护延时 单位1s + uint8_t pack_uvt; // 总体过压保护延时 单位1s + + //20250405 放电过流2保护(总读写) + uint16_t mcu_ocd2; //0x25 放电过流2保护电流 单位A + uint16_t mcu_ocd2_t; //0x26 放电过流2保护延时 单位10ms + + //20250405 环境温度保护(总读写) + int8_t am_otc; //0x27 环境充电高温 + int8_t am_otcr; // 环境充电高温释放 + int8_t am_utc; //0x28 环境充电低温 + int8_t am_utcr; // 环境充电低温释放 + int8_t am_otd; //0x29 环境放电高温 + int8_t am_otdr; // 环境放电高温释放 + int8_t am_utd; //0x2A 环境放电低温 + int8_t am_utdr; // 环境放电低温释放 + + uint8_t cellovr_soc; //0x2B 单体过压释放SOC + uint8_t packovr_soc; // 总体过压释放SOC + + uint8_t PACK_NUM; //0x2C 并机最大个数 + + uint8_t rsvd2_0[1]; //0x2C [驻启有参数] + uint8_t rsvd2_1[3]; //0x2D + + //20260722 + uint8_t ee_sconf4; //0x2E SH36735XX系列SCONF4寄存器串数配置 + + //20260716 + uint16_t sc_mode; //0x2F AFE芯片+短路倍数 + + /** 读写地址0x30-0x3F EEPROM地址0x0460-0x047F **/ + //20250408 报警参数(总读写) + uint16_t alarm_cov; //0x30 单体过压告警 + uint16_t alarm_cuv; //0x31 单体欠压告警 + uint16_t alarm_pov; //0x32 总体过压告警 + uint16_t alarm_puv; //0x33 总体欠压告警 + + uint8_t alarm_occ; //0x34 充电过流告警 + uint8_t alarm_ocd1; // 放电过流1告警 + + int8_t alarm_mcu_otc; //0x35 电芯充电高温告警 + int8_t alarm_mcu_utc; // 电芯充电低温告警 + int8_t alarm_mcu_otd; //0x36 电芯放电高温告警 + int8_t alarm_mcu_utd; // 电芯放电低温告警 + + int8_t alarm_am_otc; //0x37 环境充电高温告警 + int8_t alarm_am_utc; // 环境充电低温告警 + int8_t alarm_am_otd; //0x38 环境放电高温告警 + int8_t alarm_am_utd; // 环境放电低温告警 + + int8_t alarm_afe_otc; //0x39 MOS充电高温告警 + int8_t alarm_afe_utc; // MOS充电低温告警 + int8_t alarm_afe_otd; //0x3A MOS放电高温告警 + int8_t alarm_afe_utd; // MOS放电低温告警 + + uint8_t rsvd3[10]; //0x3B-0x3F [驻启有参数] + + + /** 读写地址0x40-0x4F EEPROM地址0x0480-0x049F **/ + //20250410 开路电压法-OCV放电曲线(单) + uint16_t ocv_dpBuf[15]; //0x40-0x4E 放电曲线 + + uint8_t rsvd4[2]; //0x4F + + + /** 读写地址0x50-0x5F EEPROM地址0x04A0-0x04BF **/ + //20250410 开路电压法-OCV充电曲线(单) + uint16_t ocv_cpBuf[15]; //0x50-0x5E 充电曲线 + + uint8_t rsvd5[2]; //0x5F + + + /** 读写地址0x50-0x5F EEPROM地址0x04A0-0x04BF **/ + //0x60-0x6F [驻启有参数] + + +}PARA_MEMORY ; + +//逆变器通信SRNE 结构体 +typedef struct +{ + //数据及状态采集 + int16_t packCurrent; // 实时电流 mA + uint16_t packVoltage; // 电芯总电压 mv + uint8_t soc; // 电池包的剩余电量百分比 % + uint8_t socH; + uint8_t soh; // 电池健康系数 % + uint8_t sohH; + uint16_t rcc; // 电池包当前剩余电量 mAH + uint16_t fcc; // 系统满充容量 mAH + uint16_t dcc; // 设计容量 mAH + uint16_t cyc; // 蓄电池循环计数 mAH + uint16_t rsvd1; + + uint16_t alarm_byte; //报警 + uint16_t protect_byte; //保护 + uint16_t status_byte; //状态/故障标志 + uint16_t balanceStatus; //平衡状态 + uint16_t rsvd2; + uint16_t rsvd3; + + uint16_t vCell[16]; // 电池电压 mv + int16_t Tcell[4]; // 电池温度 .c + int16_t afe_MOS; // MOS温度 .c 赋值两个MOS温度的平均值 + int16_t afe_MCU; // 环境温度 .c 赋值芯片温度 + int16_t chgVolLimit; // + int16_t chgCurLimit; // + int16_t dsgCurLimit; // + +}PROTOCOL_SRNE_MEMORY ; + +//逆变器通信Voltronic 结构体 +typedef struct +{ + uint16_t rsvd1; //协议地址从0x0001开始 + uint16_t protocolType; //协议类型 + uint16_t protocolVer; //协议版本 + uint16_t SoftwareH; //BMS软件版本 + uint16_t SoftwareL; + uint16_t HardwareH; //BMS硬件版本 + uint16_t HardwareL; + uint16_t rsvd2[9]; + + uint16_t cellNum; // 串联电芯数量 + uint16_t cellVol[20]; // 电芯电压1-16 (17~20暂无) + + uint16_t tempNum; // 温度传感器数量 + uint16_t T[10]; // 1-4电池温度 5芯片温度 6MOS温度平均值 (7-10暂无) + + uint16_t chg_packCurrent; // 模块充电电流 + uint16_t dsg_packCurrent; // 模块放电电流 + uint16_t packVoltage; // 模块电压 + uint16_t soc; // soc + uint16_t fccH; // 模块总容量 + uint16_t fccL; + + uint16_t packNum; // 并联电池包数量 + uint16_t chg_alarm_byte; // 充电报警 + uint16_t dsg_alarm_byte; // 放电报警 + uint16_t chg_protect1_byte; // 充电保护 + uint16_t chg_protect2_byte; // 充电保护2 + uint16_t dsg_protect1_byte; // 放电保护 + uint16_t dsg_protect2_byte; // 放电保护2 + uint16_t packstatus; // BMS状态 + uint16_t dccH; // 设计容量 + uint16_t dccL; + + uint16_t cellNum2; // 串联电芯数量 + uint16_t Vol_status[10]; // 电芯电压状态1/2,3/4…… + uint16_t rsvd3[5]; + + uint16_t tempNum2; // 温度传感器数量 + uint16_t T_status[5]; // BMS温度状态1/2,3/4…… + uint16_t rsvd4[10]; + + uint16_t other_status[10]; + uint16_t rsvd5[6]; + + uint16_t chgVolLimit; // 充电电压限制 + uint16_t dsgVolLimit; // 放电电压限制 + uint16_t chgCurLimit; // 充电电流限制 + uint16_t dsgCurLimit; // 放电电流限制 + uint16_t status_byte; // 充放电允许 + uint16_t runtime; // 剩余运行时间 + uint16_t rccH; // 电池包当前剩余电量 mAH + uint16_t rccL; + +}PROTOCOL_VOLTRONIC_MEMORY ; + +//逆变器通信SMK 结构体 +typedef struct +{ + uint16_t rsvd[19]; //00~18 + + uint16_t status_byte; //19 状态位 + uint16_t rsvd2; //20 预留 + int16_t soc; //21 soc % + int16_t packVoltage; //22 模块电压 10mV + int16_t packCurrent; //23 模块电流 10mA + uint16_t rsvd3; //24 预留 + int16_t chgCurLimit; //25 最大充电电流 10mA + int16_t rcc; //26 电池包当前剩余电量 10mAH + int16_t fcc; //27 系统满充容量 10mAH + uint16_t rsvd4[5]; //28~32 预留 + int16_t chgVolLimit; //33 最大充电电压 10mV + uint16_t rsvd5; //34 预留 + int16_t dcsCurLimit; //35 最大放电电流 10mA + +}PROTOCOL_SMK_MEMORY ; + +//逆变器通信Growatt 结构体 +typedef struct +{ + uint16_t rsvd1; //00 起始位(占位) + uint16_t MCU_softV; //01 MCU软件版本 + uint16_t Gauge_V; //02 Gauge版本 + uint16_t Gauge_FR_VL; //03 Gauge FR版本L + uint16_t Gauge_FR_VH; //04 Gauge FR版本H + uint16_t D_T1; //05 Date&Time1 + uint16_t D_T2; //06 Date&Time2 + uint16_t D_T3; //07 Date&Time3 + uint16_t D_T4; //08 Date&Time4 + uint16_t Bar_C1L; //09 条形码1L + uint16_t Bar_C1H; //0A 条形码1H + uint16_t Bar_C2; //0B 条形码2 + uint16_t Bar_C3; //0C 条形码3 + uint16_t companyL; //0D 公司信息L + uint16_t companyH; //0E 公司信息H + uint16_t Using_C; //0F 型号(大写) + uint16_t Gau_IC; //10 IC电流 + uint16_t Date1_TimeL; //11 日期、时间L + uint16_t Date1_TimeH; //12 日期、时间H + + uint16_t status_byte; //13 状态位 + uint16_t protect_byte; //14 保护 + uint16_t soc; //15 soc % + uint16_t packVoltage; //16 模块电压 10mV + uint16_t packCurrent; //17 模块电流 10mA + int16_t T_Average; //18 电芯温度 ℃ + uint16_t chgCurLimit; //19 充电电流限制 10mA + uint16_t rcc; //1A 电池包当前剩余电量 10mAH + uint16_t fcc; //1B 系统满充容量 10mAH + + uint16_t FW; //1C YW/FW + + uint16_t Delta; //1D 压差 mV + + uint16_t cyc; //1E 循环次数 + uint16_t Master_Box; //1F + + uint16_t soh; //20 电池健康系数 % + uint16_t CV_Vol; //21 CV电压 10mV + uint16_t alarm_byte; //22 报警 + uint16_t dsgCurLimit; //23 放电电流限制 10mA + + uint16_t Ext_Err; //24 扩展错误 + + uint16_t cellVolMax; //25 电芯单体最高电压 mV + uint16_t cellVolMin; //26 电芯单体最低电压 mV + uint16_t cellVolMaxIndex; //27 电芯单体最高电压序号，范围0-15 + uint16_t cellVolMinIndex; //28 电芯单体最低电压序号，范围0-15 + uint16_t cellNum; //29 串联电芯数量(单模块电池串联数量) + uint16_t UpdateFlg; //2A 升级标志 + uint16_t rsvd2[6]; //2B~30 + +//Box并联时上报第2组电池规格和状态查询信息 + uint16_t MCU2_softV; //31 软件版本 + uint16_t Gau2_Ver; //32 Gauge版本 + uint16_t Gau2_FR_VerL; //33 Gauge FR 版本L + uint16_t Gau2_FR_VerH; //34 Gauge FR 版本H + uint16_t Date2_Time1; //35 日期、时间1 + uint16_t Date2_Time2; //36 日期、时间2 + uint16_t Date2_Time3; //37 日期、时间3 + uint16_t Date2_Time4; //38 日期、时间4 + uint16_t Bar2_codeL; //39 条形码1L + uint16_t Bar2_codeH; //3A 条形码1H + uint16_t Bar2_code2; //3B 条形码2 + uint16_t Bar2_code3; //3C 条形码3 + + uint16_t company2L; //3D 公司名称L + uint16_t company2H; //3E 公司名称H + + uint16_t Mod2_num; //3F 产品型号 + uint16_t Gau2_IC_Cur; //40 Gauge IC 电流 10mA + uint16_t Date2_Time5L; //41 日期、时间L + uint16_t Date2_Time5H; //42 日期、时间H + + uint16_t status2_byte; //43 状态位 + uint16_t protect2_byte; //44 保护 + uint16_t soc2; //45 soc % + uint16_t packVoltage2; //46 模块电压 10mV + uint16_t packCurrent2; //47 模块电流 10mA + int16_t T_Average2; //48 温度(平均) -127~127℃ + uint16_t chg2_CurLimit; //49 充电电流限制 + uint16_t rcc2; //4A 电池包当前剩余电量 10mAH + uint16_t fcc2; //4B 系统满充容量 10mAH + uint16_t YW_FW2; //4C 软硬件版本号 范围1~9 + uint16_t Delta2; //4D 压差 V + uint16_t cyc2; //4E 蓄电池循环计数 mAH + uint16_t Mas2_Box; //4F 主机回复 + uint16_t soh2; //50 电池健康系数 % + uint16_t CV2_Vol; //51 CV电压 + uint16_t alarm2_byte; //52 报警1 + uint16_t rsvd3[29]; //53~6F + + uint16_t Bar_ID; //70 电池组ID + uint16_t cellVol[16]; //71~80 电芯电压1-16 + +//Box 并联时上报第 2 组电池单体电压信息： + uint16_t cellVol2[16]; //81~90 电芯电压1-16 + +}PROTOCOL_Growatt_MEMORY ; + + +//电流校准结构体 +typedef struct +{ + int32_t current; //校准电流点电流 + int16_t cadcZero; //零点校准值 + int16_t cadcGain; //增益校准值 + uint16_t cmdZero; //零点校准标记 + uint16_t cmdGain; //增益校准标记 + uint16_t flagWrZeroToEE; + uint16_t flagWrGainToEE; + uint16_t flagZeroCaliFail; + uint16_t flagGainCaliFail; + int16_t tempCur; + int16_t rsvd; +}CALI_STRUCT; + +extern CALI_STRUCT cali; + + +typedef struct +{ + uint16_t status_byte1; + uint16_t status_byte2; + uint16_t status_byte3; + uint16_t status_byte4; + uint16_t soc; + uint16_t soh; + int32_t cur; + int32_t temp; + + uint16_t VolMax; + uint16_t VolMin; + uint16_t VolMaxIndex; + uint16_t VolMinIndex; + uint16_t TempMax; + uint16_t TempMin; + uint16_t TempMaxIndex; + uint16_t TempMinIndex; + + //Wh版屏幕，显示功率总耗 + uint16_t cumuliCap; + uint32_t cycleCnt; + + //负值矫正后的最高最低电压 + int16_t cellVoltageMax; + int16_t cellVoltageMin; + + int16_t com; + +}CAN_MEMORY; + +//版本号结构体 +typedef struct +{ + uint8_t Hardware[3]; + uint8_t Screen; + uint8_t Software[4]; + + uint8_t BMS_SN[9]; //BMS生产批次 + uint8_t BMS_crc8; + uint8_t PACK_SN[15]; //PACK产品序列号，最大15字节 + uint8_t PACK_crc8; + + uint8_t rsvd1[30]; //驻启SN号位置，预留以区分 + + //存在Flash中，升级可更改的 + /** 读写地址0x20-0x5F **/ + char host[40+2]; //4G平台_域名 + uint16_t port; //4G平台_端口 + char UserName[40+2]; //4G平台_用户名 + char PassWord[40+2]; //4G平台_密码 + + /** 读写地址0x60-0x6F **/ + char ClientID[23+2]; //4G平台_设备唯一标识符 + + uint8_t hostAll_crc; //4G平台信息的CRC校验码 + + uint8_t rsvd4[6]; //预留 + +}VERSION_MEMORY ; + +//在线总数据结构体 +typedef struct +{ + uint8_t Online[AddrMax+2]; //轮询中的从机在线情况，Online[0]代表在线个数，Online[i]=0xAA说明地址i在线 + + uint16_t vol; //同步地址1当前电压 单位0.01V + int16_t cur; //同步canMem[0]数据 单位0.01A + int16_t temp; //单位0.1℃ + uint8_t soc; //单位1% + uint8_t soh; //单位1% + + uint8_t status_byte1; // + uint8_t status_byte2; // + uint8_t status_byte3; // + uint8_t status_byte4; // + + uint16_t VolMax; // 电芯单体最高电压 单位1mv + uint16_t VolMin; // 电芯单体最低电压 单位1mv + uint16_t VolMaxIndex; // 电芯单体最高电压序号 + uint16_t VolMinIndex; // 电芯单体最低电压序号 + uint16_t TempMax; // 最高温度 单位0.1℃ + uint16_t TempMin; // 最低温度 单位0.1℃ + uint16_t TempMaxIndex; // 最高温度序号 + uint16_t TempMinIndex; // 最低温度序号 + +}ONLINE_MEMORY ; + + +//Global +extern BMS_MEMORY bmsMem; +extern BMS_MEMORY bmsMem_slave; +extern PARA_MEMORY paraMem; + +extern CAN_MEMORY canMem[AddrMax+2]; + +extern VERSION_MEMORY VersionMem; +extern ONLINE_MEMORY onlineMem; + +extern PROTOCOL_SRNE_MEMORY SRNEMem; +extern PROTOCOL_VOLTRONIC_MEMORY VoltronicMem; +extern PROTOCOL_SMK_MEMORY SMKMem; +extern PROTOCOL_Growatt_MEMORY GrowattMem; + +extern void canMem_refresh(void); +extern void onlineMem_refresh(void); +extern void ParaChange(void); +extern void Addr_Set(void); +extern void SLEEP_Refresh(void); +extern void SLEEP2_Refresh(void); +extern void SLEEP_TIM_Moni(void); +extern void SLEEP2_TIM_Moni(void); +extern void UVOff_TIM_Moni(void); +extern void FCCCali_TIM_Moni(void); +extern void uf_GLOBAL_Init(void); + +extern uint8_t CRC8_Cal(uint8_t *p, uint8_t Length); +extern BYTE2 CRC16_Cal(uint8_t *pdata, uint16_t len); +extern uint16_t CRC16_FirmtoEE(uint8_t *data, uint16_t len); + +extern uint8_t toASCII(uint8_t data); +extern uint16_t get_random(void); +extern uint8_t GetStr(const char* dataKey, char End1, char End2, char* InStr, char* OutStr); +extern uint8_t GetID(char* InStr, char* OutStr); +extern uint8_t GetStrFromJson(const char* dataKey, char* InStr, char* OutStr); +extern uint8_t uint_str_len(uint32_t value); +extern uint8_t int_str_len(int32_t value); + +extern void Refresh_FirmwareVersion(void); +extern void Refresh_HardwareVersion(void); +extern void Refresh_ScreenVersion(void); +extern void Refresh_BMS_SN(void); +extern void Refresh_PACK_SN(void); + +//Systick +extern void delay_ms(uint16_t ms); +extern void delay_us(uint16_t us); + +//Gpio +extern void uf_GPIO_Init(void); +extern void uf_EXTI_Init(void); +extern void LED_RUN_On(void); +extern void LED_RUN_Off(void); +extern void LED1_On(void); +extern void LED1_Off(void); +extern void LED2_On(void); +extern void LED2_Off(void); +extern void LED3_On(void); +extern void LED3_Off(void); +extern void LED4_On(void); +extern void LED4_Off(void); +extern void LED_ALARM_On(void); +extern void LED_ALARM_Off(void); +extern void LED_ALARM_Toggle(void); +extern void LED_RUN_Toggle(void); +extern void LED_RST_Toggle(void); +extern void LED_ALL_ON(void); +extern void LED_ALL_OFF(void); +extern void VPRO_On(void); +extern void VPRO_Off(void); +extern void CTRL_On(void); +extern void CTRL_Off(void); +extern void PCHG_On(void); +extern void PCHG_Off(void); +extern void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); + +//电源控制 +extern void POWER_Check(void); +extern void POWER_Ctrl(void); +extern void KEY_TIM_Moni(void); + +//均衡控制 +extern void BAL_On(void); +extern void BAL_Off(void); +extern void MCU_BalanceProcess(void); + +//加热控制 +extern void WARM_Ctrl(void); + +//限流控制 +extern void TIM4_PWM_Init(uint16_t arr, uint16_t psc); +extern void PWM_Set_Duty_Percent(float duty_per); +extern void CHG_LIMIT_PWM_Adjust(void); +extern void CHG_LIMIT_Init(void); +extern void CHG_LIMIT_On(void); +extern void CHG_LIMIT_Off(void); +extern void CHG_LIMIT_Ctrl(void); + +//放电过流2 +extern void OCC2_TIM_Moni(void); +extern void OCC2_Ctrl(void); + +//DO +extern void DO_On(void); +extern void DO_Off(void); + +#if Addr_SetAuto +//分配地址 +extern uint8_t IO3_IN(void); //检测输入电平 +extern void IO2_OUTSet(void); //分配中先置高让下一个变99，再置低变AddrMax+1 +extern void IO2_OUTReset(void);//正常置低 +extern uint8_t IO1_IN(void); //检测输入电平 +extern void ADDR_Assign_Moni(void);//根据不同的原地址和输入电平，选择要修改的特定地址 +extern void ADDR_Rank_Moni(void); //根据IO3的不同电平，确定自身是主机/从机 +#endif + +//PCHG +extern void PCHG_StartCtrl(void); +extern void PCHG_Ctrl(void); +//浪涌短路时的TSC判断 +extern void TSC_Detect(void); +//AFE +extern void AFE_Ctrl(void); + +//Timer +extern uint32_t tmrSys; +extern uint32_t tmrTemp[20]; +extern void uf_TIM3_Init(void); +extern uint32_t TIMER_Update(void); +extern uint32_t TIMER_IsOut(uint32_t cnt, uint32_t tmr); +extern uint32_t TIMER_IsOther(uint32_t cnt, uint32_t tmr); + +//i2c +extern void uf_I2C1_Init(void); +extern uint8_t EEPROM_WrMulByte(uint8_t addrH, uint8_t addrL, uint8_t lenth, uint8_t *data); +extern uint8_t EEPROM_RdMulByte(uint8_t addrH, uint8_t addrL, uint8_t lenth, uint8_t *data); +extern uint8_t EEPROM_CALI_WrZero(int16_t data); +extern int16_t EEPROM_CALI_RdZero(void); +extern uint8_t EEPROM_CALI_WrGain(int16_t data); +extern int16_t EEPROM_CALI_RdGain(void); + +//spi +extern void uf_SPI2_Init(void); +extern void SPI2_Error(void); +extern uint8_t AFE_WriteOneByte(uint8_t addr, uint8_t *data); +extern uint8_t AFE_ReadMulByte(uint8_t addr, uint8_t lenth, uint8_t *data); +extern uint8_t AFE_Reset(void); + +//flash +#define FLASH_DATA_A_BASE 0X0800A000 +#define FLASH_DATA_B_BASE 0X0800C000 +extern uint8_t MEMORY_UpdateFlash(uint32_t addr); +extern uint8_t FLASH_UpdateMemory(void); +extern void uf_FLASH_Init(void); +extern void FLASH_RdWord(uint32_t addr, uint32_t *data, uint16_t len); +extern void FLASH_WrData(uint32_t addr, uint16_t *data, uint16_t num); + +//wdg +extern void uf_IWDG_Init(u8 prer,u16 rlr); +extern void IWDG_Feed(void); + +//Modbus - 主从机/旧上位机 +extern void uf_UART1_Init( u32 bound ); +extern void USART1_SendOneByte(uint8_t data); +extern void USART1_SendMulByte(uint8_t *bufPT, uint8_t size); +extern void MODBUS_Init(void); //串口初始化 +extern void MODBUS_IT_Receive(void); +extern void MODBUS_IQ_Transmit(void); +extern void MODBUS_IT_TIMUpdate(void); +extern void MODBUS_TIM_Moni(void); +//旧上位机相关 +extern void UART1_ReadRecord(void); +extern void UART1_ClearRecord(void); +extern void MODBUS_F03_Rx(uint8_t *mem); +extern void MODBUS_F10_Rx(uint8_t *mem); +extern void MODBUS_Faa_Rx(uint8_t *mem); +extern void MODBUS_Fbb_Rx(uint8_t *mem); +//主机相关 +extern void MODBUS_Poll_Init(void); //轮询汇总初始化，只有主机数据 +extern void MODBUS_MASTER_F03_Rx(void); //处理从机对读指令的回复 +extern void MODBUS_MASTER_F10_Rx(void); //处理从机对写指令的回复 +extern void MODBUS_MASTER_Polling_Tx(void);//主机轮询获总数据 +#if Addr_SetAuto +//分配地址 +extern void MODBUS_AddrAssign_Tx(void); //主机自动分配地址 +extern void MODBUS_WrIndex_Tx(void); //主机广播下发队列标志 +extern void MODBUS_WrIndex_Rx(void); //从机接收该次分配地址的队列标志 +#endif +//屏幕看从机 +extern void MODBUS_Screen_RdSlave_Tx(void); //主机因屏幕读从机数据 +extern void MODBUS_Screen_WrSlaveAddr_Tx(void);//主机因屏幕写从机地址 +//上位机看从机 +extern void MODBUS_Config_RdSlave_Tx(void); //主机因上位机读从机数据 + +//Modbus1 - 485逆变器/新上位机 +extern void uf_UART3_Init( u32 bound ); +extern void USART3_SendMulByte(uint8_t *bufPT, uint8_t size); +extern void MODBUS1_Init(void); +extern void MODBUS1_IT_Receive(void); +extern void MODBUS1_IQ_Transmit(void); +extern void MODBUS1_IT_TIMUpdate(void); +extern void MODBUS1_TIM_Moni(void); +//新上位机相关 +extern void UART3_EraseIAP(void); +extern void UART3_ReadRecord(void); +extern void UART3_ClearRecord(void); +extern void UART3_ProtocolSwitch(void); +extern void MODBUS1_F03_Rx(uint8_t *mem); +extern void MODBUS1_F10_Rx(uint8_t *mem); +extern void MODBUS1_Faa_Rx(uint8_t *mem); +extern void MODBUS1_Fbb_Rx(uint8_t *mem); +//广播 +extern void MODBUS1_CtrlMOS_Rx(uint8_t *mem); //ff f2 +//485逆变器 +extern void MODBUS1_UpdateData(void); +extern void YDN(void); + +//三选一分板串口 +extern void uf_UART4_Init( u32 bound ); + +//蓝牙模块 - 透传模式，通信小程序 +extern void BLE_IO_Init(void); +extern void BLE_Open(void); +extern void BLE_Close(void); +extern void BLE_Reset(void); +extern void BLE_Init(void); +extern void BLE_TIM_Moni(void); +extern void BLE_IT_Receive(void); //接收 +extern void BLE_IT_Update(void); //接收分析 +extern void BLE_IQ_Update(void); //发送分析 +extern void BLE_IQ_Transmit(void); //发送 +//功能 +extern void BLE_WriteName(void); +extern void BLE_CheckName(void); + +//WIFI模块 - 模块询问才回复 +extern void WIFI_IO_Init(void); +extern void WIFI_Open(void); +extern void WIFI_Close(void); +extern void WIFI_Reset(void); +extern void WIFI_Init(void); +extern void WIFI_TIM_Moni(void); +extern void WIFI_IT_Receive(void); //接收 +extern void WIFI_IT_Update(void); //接收分析 +extern void WIFI_IQ_Update(void); //发送分析 +extern void WIFI_IQ_Transmit(void); //发送 + +//4G模块 - AT指令通信 +extern int LTE_printf(const char *fmt, ...); +extern void LTE_4G_IO_Init(void); +extern void LTE_4G_Open(void); +extern void LTE_4G_Close(void); +extern void LTE_4G_Reset(void); +extern void LTE_4G_Init(void); +extern void LTE_TIM_Moni(void); +extern void LTE_4G_IT_Receive(void); //接收 +extern void LTE_4G_IT_Update(void); //接收分析 +extern void LTE_4G_IQ_Update(void); //发送分析 +extern void LTE_4G_IQ_Transmit(void); //发送 +//填充4G上报属性 +extern void LTE_Record_pubData(void); +//OTA升级相关 +extern void LTE_OTA_Info(void); +extern void LTE_OTA_IT_Update(void); +extern void LTE_OTA_IQ_Update(void); +extern void LTE_OTA_IQ_Transmit(void); +//功能 +extern void LTE_4G_Domain_ChangeSN(void); +extern void gcj02_to_wgs84(double gcj_lon, double gcj_lat, double *wgs_lon, double *wgs_lat); + +//ADC +extern void uf_ADC_Init(void); +extern void LOAD_VOL(void); +extern void MCU_TemperaProcess(void); + +//CAN +extern void uf_CAN1_Init(void); +extern void CAN_TIM_Moni(void); +extern void CAN_UpdateData(void); +extern void CAN1_SendData(uint32_t Id, uint8_t *data); + +//逆变器通信协议 +//第1页 +extern void CAN_Protocol_SolArk(void); +extern void CAN_Protocol_GoodWe(void); +extern void CAN_Protocol_Megarevo(void); +extern void CAN_Protocol_Pylon(void); +extern void CAN_Protocol_Deye(void); +extern void CAN_Protocol_MUST(void); +extern void CAN_Protocol_solis(void); +extern void CAN_Protocol_Growatt(void); +extern void CAN_Protocol_Aiswei(void); +extern void CAN_Protocol_Afore(void); +extern void CAN_Protocol_Victron(void); +extern void CAN_Protocol_Sorotec(void); +extern void MOD_Protocol_Growatt(void); //同时准备通信 +extern void MOD_Protocol_Sorotec(void); //同时准备通信 +extern void YDN_Protocol_Pylon(void); +//第2页 +extern void CAN_Protocol_SMA(void); +extern void CAN_Protocol_Sunways(void); +extern void CAN_Protocol_Luxpower(void); +extern void CAN_Protocol_Schneider(void); +extern void CAN_Protocol_AlpSolarr(void); +extern void MOD_Protocol_SRNE(void); +extern void MOD_Protocol_Voltronic(void); +extern void MOD_Protocol_COSUPER(void); +extern void MOD_Protocol_SMK(void); +extern void MOD_Protocol_SAKO(void); +extern void MOD_Protocol_SNADI(void); +extern void MOD_Protocol_invt(void); + +//NTC +extern uint16_t const NTC_103AT_CMFA[166]; +extern uint16_t TEMP_Cal(uint16_t ntcR); +extern uint16_t TEMP_Cal_CMFA(uint16_t ntcR); + +//AFE +extern uint8_t bAlarmFlag; +extern uint8_t bAlarmFlagOld; +extern uint8_t balancing; +extern int16_t AFE_CADC_GetVal(void); +extern void AFE_ReadAlarmFlag(void); +extern uint8_t AFE_Read(uint8_t addr, uint8_t lenth, uint8_t *data); +extern uint8_t AFE_WriteRAM(uint8_t addr, uint8_t lenth, uint8_t *data); +extern uint8_t TwiRead(uint8_t SlaveID,uint16_t RdAddr, uint8_t Length, uint8_t *RdBuf); +extern void CALI_CurrentProcess(void); + +//电量 +extern void GaugeManage(void); +extern void Cali_SOC_Moni(void); +extern void Cali_FCC_Moni(void); + +//Screen +extern void uf_UART2_Init( u32 bound ); +extern void Screen_Init(void); +extern void Screen_TIM_Moni(void); +extern void Screen_IT_Receive(void); //接收 +extern void Screen_IT_Update(void); //接收分析 +extern void Screen_IQ_Transmit(void); //发送 +extern void SCR_KeepLight0(void); +extern void SCR_DispProcotol(void); + +//SDWA +extern void SDWA_JumpToHome(void); +extern void SDWA_ChangeLight(uint8_t light); +extern void SDWA_KeepLight0(void); +extern void SDWA_UpdateData(void); +extern void SDWA_RecvData(void); +extern void SDWA_TIM_Moni(void); +extern void SDWA_IT_Receive(void); + +//OCV开路电压矫正SOC +extern uint8_t OCV_CaliSoc_dp(void); +extern void OCV_CaliSOC(void); +extern void OCV_CaliSOC_DataWr(void); + +//Status +extern void Trigger_OVAlarm(void); +extern void Trigger_UVAlarm(void); +extern void Release_OVAlarm(void); +extern void Release_UVAlarm(void); +extern void Trigger_OVProtect(void); +extern void Trigger_UVProtect(void); +extern void Release_OVProtect(void); +extern void Release_UVProtect(void); + +extern void Trigger_CurAlarm(void); +extern void Release_CurAlarm(void); +extern void Trigger_CurProtect(void); +extern void Release_CurProtect(void); +extern void Trigger_CurProtectLock(void); + +extern void Trigger_mcuTAlarm(void); +extern void Release_mcuTAlarm(void); +extern void Trigger_mcuTProtect(void); +extern void Release_mcuTProtect(void); + +extern void Trigger_amTAlarm(void); +extern void Release_amTAlarm(void); +extern void Trigger_amTProtect(void); +extern void Release_amTProtect(void); + +extern void Trigger_afeTAlarm(void); +extern void Release_afeTAlarm(void); +extern void Trigger_afeTProtect(void); +extern void Release_afeTProtect(void); + +extern void Check_eventChange(void); +extern void Transmit_incident(void); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/USER/main.c b/USER/main.c new file mode 100644 index 0000000..13c274e --- /dev/null +++ b/USER/main.c @@ -0,0 +1,545 @@ + /** + ****************************************************************************** + * @file main.c + * @author BMS + * @version V1.0.0 + * @date 20-5-2022 + * @brief Main program body. + ****************************************************************************** + * @attention + * + * Copyright (c) 2011 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" +#include "global.h" +#include "rtc.h" +#include "soe.h" + +/** @addtogroup STM32F10x_StdPeriph_Examples + * @{ + */ + +/** @addtogroup GPIO_IOToggle + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program. + * @param None + * @retval None + */ +int main(void) +{ + #if Key_PressLong + POWER_Check(); + #endif + + delay_ms(1000); //上电之后加1S延时，防止WK唤醒误动 + + //SCB->VTOR = FLASH_BASE | 0x1800; + + uf_GPIO_Init(); + uf_EXTI_Init(); + uf_TIM3_Init(); //10MS + uf_I2C1_Init(); + uf_SPI2_Init(); + uf_CAN1_Init(); + + uf_ADC_Init(); + + uf_IWDG_Init(7,1250); //分频数=7,重载值=1250,溢出时间=((4*2^7)*1250)/40=16000ms=16s + + #if Key_PressLong + LED_ALL_ON(); //按钮长按模式，需要先灭再常亮 + #endif + + uf_FLASH_Init(); + uf_GLOBAL_Init(); + + /*三选一模块*/ + #if BLE_Conn + BLE_Init(); //蓝牙初始化 + BLE_IO_Init(); + BLE_Open(); + #endif + #if WIFI_Conn + WIFI_Init(); //WIFI初始化 + WIFI_IO_Init(); + WIFI_Open(); + #endif + #if LTE_Conn + LTE_4G_Init(); //4G初始化 + LTE_4G_IO_Init(); + LTE_4G_Open(); + #endif + +// BAL_Off(); //默认关闭外置主动均衡(钰泰) + + MODBUS_Init(); + MODBUS1_Init(); + + AFE_VoltageProcess(); + InitGasGauge(); + + MCU_TemperaProcess(); + MODBUS_Poll_Init(); + + Screen_Init(); //[陶晶驰] + + if(uf_RTC_Init()==1) //RTC时钟初始化，超时说明晶振有问题 + { + LSEErrFlag=1; + sleep_Moni_Count=SLEEP_MON_CNT; + } + else + { + RTC_Get(); + } + + while (1) + { + //5*10ms + if(TIMER_IsOut(tmrTemp[0],5)) + { + tmrTemp[0] = TIMER_Update(); + + /*三选一模块：蓝牙*/ + #if BLE_Conn + BLE_IQ_Update(); //更新数据 + BLE_IQ_Transmit(); //发送数据，每0.05s执行一次 + #endif + } + + //10*10ms + if(TIMER_IsOut(tmrTemp[1],10)) + { + tmrTemp[1] = TIMER_Update(); + + /*三选一模块：WIFI*/ + #if WIFI_Conn + WIFI_IQ_Update(); //更新数据 + WIFI_IQ_Transmit(); //发送数据，每0.1s执行一次 + #endif + } + + //25*10ms + if(TIMER_IsOut(tmrTemp[2],25)) + { + tmrTemp[2] = TIMER_Update(); + AFE_CurrentProcess(); //1s读4次电流后取平均值 + + #if Key_PressLong + if(OFF_confirm_flg == 1) //若确认关机，此时把所有灯灭掉，提醒松开就会关机 + { + LED_ALL_OFF(); + } + else if(RST_confirm_flg == 1) //若按键摁下执行复位，灯被接管闪烁 + { + LED_RST_Toggle(); + } + else if(ON_confirm_flg != 0) //虚地址运行灯快速闪烁 + { + if(sleep_flag == 0) + { + if(curLimitFlag == 0) + { + if(bmsMem.E2_485Addr > AddrMax) + { + LED_RUN_Toggle(); + } + } + } + } + #endif + + /*三选一模块：4G*/ + #if LTE_Conn + if((LTE_WarmDelay == 0) && (LTE_ResendDelay == 0) && (LTE_WaitRxDelay == 0) && (LTE_PinRST_Flag == 0) && (LTE_sleep_flag == 0)) //不在等候+不在引脚重启+不在休眠 + { + if(MQTT_READY_flag == 0) //未通信MQTT + { + if(LTE_LINK_flag == 1) + { + LTE_4G_IQ_Update(); //更新数据 + LTE_4G_IQ_Transmit(); //发送数据，每0.25s执行一次 + } + } + else //已通信MQTT + { + if((pre_sleep_flag == 4) || (LTE_status == event_pub) || (LTE_status == srvc_pub) || (LTE_status == setPara_pub) || (LTE_status == getPara_pub)) + { + LTE_4G_IQ_Update(); //更新数据 + LTE_4G_IQ_Transmit(); //发送数据，每0.25s执行一次 + } + else if(LTE_OTA_Flag == 1) + { + LTE_OTA_IQ_Update(); //更新数据 + LTE_OTA_IQ_Transmit(); //发送数据，每0.25s执行一次 + } + } + } + #endif + } + + CALI_CurrentProcess(); //收到校准指令后进行更新，并回复 + + //50*10ms + if(TIMER_IsOut(tmrTemp[3],50)) + { + tmrTemp[3] = TIMER_Update(); + + //LED 运行灯 + #if Key_PressLong + if((ON_confirm_flg != 0) && (RST_confirm_flg != 1) && (OFF_confirm_flg != 1)) + #endif + { + if(sleep_flag == 0) + { + if(curLimitFlag == 0) + { + if((bmsMem.E2_485Addr >= 1) && (bmsMem.E2_485Addr <= AddrMax)) + { + LED_RUN_Toggle(); //正常地址运行灯正常闪烁 + } + } + else + { + LED_RUN_On(); //限流常亮灯 + } + } + else + { + LED_RUN_Off(); //休眠不亮灯 + } + } + + //LED报警灯 + #if Key_PressLong + if((ON_confirm_flg != 0) && (RST_confirm_flg != 1) && (OFF_confirm_flg != 1)) + #endif + { + if((bAlarmFlag == 0) && (((bmsMem.bStatus2 & 0x00e0) ==0) && ((bmsMem.temperaStatus & 0x0040) ==0))) //无保护 + { + if(((bmsMem.bStatus2 & 0xff00) != 0) || ((bmsMem.bStatus3 & 0x3A00) != 0) || ((bmsMem.temperaStatus & 0xf000) != 0)) //有报警(除了单体过压告警和总体过压告警) + { + if(sleep_flag == 0) LED_ALARM_Toggle(); + else LED_ALARM_Off(); + } + else if((bmsMem.bStatus3 & 0x0500) != 0) //单体过压告警和总体过压告警 + { + if(bmsMem.soc<99) //在正常工作时，发生[过压保护]，正常显示 + { + if(sleep_flag == 0) LED_ALARM_Toggle(); + else LED_ALARM_Off(); + } + else + { + LED_ALARM_Off(); + } + } + } + } + + //主机轮询从机 + #if Key_PressLong + if(OFF_confirm_flg != 1) + #endif + { + if(sleep_flag == 0) //休眠时，主从通信禁用 //确认关机后，停止通信 + { + //主机在3.4口向下通讯 + if((bmsMem.E2_485Addr == 1) && (paraMem.PACK_NUM >= 2) && (PollStop_flag == 0)) + { + #if Addr_SetAuto + //开机后地址可能从1变2，先等待2s + if((paraMem.addr_FREE_Flg == 0) && (assignAddr_relay > 0)) + { + assignAddr_relay--; + } + + else if((paraMem.addr_FREE_Flg == 0) && ((assignAddr_State == 0) || (assignAddr_State == 1))) + { + MODBUS_AddrAssign_Tx(); //(主机自动分配从机地址，结束了再进行下一操作) + } + else if((paraMem.addr_FREE_Flg == 0) && ((assignAddr_State == 2) && (assignAddr_WrIndex_Flg == 1))) + { + assignAddr_WrIndex_Flg = 0; + MODBUS_WrIndex_Tx(); //主机广播队列标志数 + } + + else + #endif + { + if(sdwa_WrAddr_Flg == 1)//(主机屏幕写从机地址，结束了再进行下一操作) + { + MODBUS_Screen_WrSlaveAddr_Tx(); + } + + else if((ConfigData_Index>=2) && (ConfigData_Index<=paraMem.PACK_NUM)) + { + MODBUS_Config_RdSlave_Tx();//(上位机持续读单一从机，上位机比屏幕优先级高) + } + else if((scr_RdData_Index>=2) && (scr_RdData_Index<=paraMem.PACK_NUM)) + { + MODBUS_Screen_RdSlave_Tx();//(屏幕持续读单一从机) + } + else + { + MODBUS_MASTER_Polling_Tx();//(轮询,是默认状态) + } + } + } + //主机暂停轮询在收不到之后的30s恢复 + else if(PollStop_flag == 1) + { + PollStop_count++; + if(PollStop_count > 30) + { + PollStop_count = 0; + PollStop_flag = 0; + } + } + } + } + } + + //100*10ms + if(TIMER_IsOut(tmrTemp[4],100)) + { + tmrTemp[4] = TIMER_Update(); + AFE_VoltageProcess(); + AFE_TemperaProcess(); + MCU_TemperaProcess(); + AFE_ProtectProcess(); + + IWDG_Feed(); //程序运行正常,进行喂狗 + + #if Key_PressLong + POWER_Ctrl(); + #endif + + #if Key_PressLong + if(OFF_confirm_flg == 1) + { + CTRL_Off(); //关闭充放MOS + delay_ms(2); + + CHG_LIMIT_Off(); //关闭限流 + curLimitFlag = 0; + delay_ms(2); + + PCHG_Off(); //关闭预充 + TSC_detectFlag = 0; + PCHG_startFlag = 0; + PCHG_Flag = 0; + delay_ms(2); + +// BAL_Off(); //关闭均衡 +// balancing = 0; + } + else + #endif + { +// MCU_BalanceProcess(); + CHG_LIMIT_Ctrl(); + + if(TSC_detectFlag == 1) + { + TSC_Detect(); //充接口开路或短路检测，开路检测 + } + else if(PCHG_startFlag == 0) + { + PCHG_StartCtrl(); //启动预充(约1s检测开短路) + } + else if(MOS_Close_Flg == 0) + { + AFE_Ctrl(); //正常(开放电MOS前开预充，并检测真短路) + } + } + + OCV_CaliSOC(); + ParaChange(); + + GaugeManage(); + + canMem_refresh(); + onlineMem_refresh(); + + #if Key_PressLong + if(OFF_confirm_flg != 1) + #endif + { + //当屏亮，而上位机在通过主机看从机，屏幕查看地址返回原值 + if(ConfigData_Index != 1) + { + scr_RdData_Index = bmsMem.E2_485Addr; + } + + //更新屏幕信息(息屏由[陶晶驰]自己做) + if(sleep_flag == 0) Screen_IQ_Transmit(); //每1s更新1次屏幕数据 + } + + //逆变器协议数据更新 + if(bmsMem.E2_485Addr == 1) + { + #if Key_PressLong + if(OFF_confirm_flg != 1) + #endif + { + if(sleep_flag == 0) CAN_UpdateData(); + if(sleep_flag == 0) MODBUS1_UpdateData(); + } + } + + if(LSEErrFlag!=1) + { + uf_RTC_Update(); //写时间或需要等待长时间，可能返回1，所以就不用这里来判断晶振了 + RTC_Get(); //时间更新每1s执行1次，若时钟持续10次都不走，可以认为晶振有问题 + } + + /*三选一模块：4G*/ + #if LTE_Conn + Check_eventChange(); //因为要加上时间，所以放在读时间后面 + + //开机等待or引脚重启等待 + if(LTE_WarmDelay > 0) + { + LTE_WarmDelay--; + } + //延迟下次发送等待 + else if(LTE_ResendDelay > 0) + { + LTE_ResendDelay--; + } + else if(LTE_WaitRxDelay > 0) + { + LTE_WaitRxDelay--; + } + //引脚重启 + else if(LTE_PinRST_Flag != 0) + { + if(LTE_PinRST_Flag == 1) + { + LTE_PinRST_Flag = 2; + LTE_4G_Close(); + } + else + { + LTE_PinRST_Flag = 0; + LTE_4G_Init(); + LTE_4G_Open(); + } + } + //休眠 + else if(LTE_sleep_flag != 0) + { + if(LTE_sleep_flag == 1) //1:准备休眠 + { + LTE_sleep_flag = 2; //2:正在休眠 + LTE_4G_Close(); //关闭4G模块 + } + else if(LTE_sleep_flag == 0xAA) //0xAA:退出休眠，执行1次开机4G模块 + { + LTE_sleep_flag = 0; + LTE_4G_Init(); + LTE_4G_Open(); //启动4G模块 + + pre_sleep_flag = 0xA0; //上线后，上报退出休眠事件 + sleepOff_time=timecount; + } + } + //正常通信or休眠前置步骤 + else + { + //休眠前置步骤执行倒计时 + if((pre_sleep_flag >=2) && (pre_sleep_flag <= 5)) + { + pre_sleep_waitCnt++; + if(pre_sleep_waitCnt > 60) + { + pre_sleep_waitCnt = 0; + pre_sleep_flag = 0; + LTE_sleep_flag = 1; //1min内前置一直卡住，直接执行休眠 + } + } + else + { + pre_sleep_waitCnt = 0; + } + + if(MQTT_READY_flag == 0) //未通信MQTT + { + if(LTE_LINK_flag == 0) + { + LTE_4G_IQ_Update(); //更新数据 + LTE_4G_IQ_Transmit(); //发送数据，每1s执行一次 + } + } + else //已通信MQTT + { + if((pre_sleep_flag != 4) && (LTE_OTA_Flag != 1) && (LTE_status != event_pub) && (LTE_status != srvc_pub) && (LTE_status != setPara_pub) && (LTE_status != getPara_pub)) + { + LTE_4G_IQ_Update(); //更新数据 + LTE_4G_IQ_Transmit(); //发送数据，每1s执行一次 + } + } + } + #endif + } + + + //需要及时响应的动作，直接放入while主循环里 + Addr_Set(); //地址写入 + RTC_BackUp(); //因各种情况触发的时间备份 + + //屏幕接收 + #if Key_PressLong + if(OFF_confirm_flg != 1) + { + if(Screen_RevHandlerFlg == 1) + { + Screen_RevHandlerFlg = 0; + Screen_IT_Update(); + } + } + else + { + SCR_KeepLight0(); //判断关机时收到数据屏幕也不能维持灯0 + } + #else + if(Screen_RevHandlerFlg == 1) + { + Screen_RevHandlerFlg = 0; + Screen_IT_Update(); + } + #endif + + //485发送回复 + #if Key_PressLong + if(OFF_confirm_flg != 1) MODBUS_IQ_Transmit(); + if(OFF_confirm_flg != 1) MODBUS1_IQ_Transmit(); + #else + MODBUS_IQ_Transmit(); + MODBUS1_IQ_Transmit(); + #endif + } +} + diff --git a/USER/stm32f10x.h b/USER/stm32f10x.h new file mode 100644 index 0000000..1cb1f09 --- /dev/null +++ b/USER/stm32f10x.h @@ -0,0 +1,8380 @@ +/** + ****************************************************************************** + * @file stm32f10x.h + * @author MCD Application Team + * @version V3.5.1 + * @date 08-September-2021 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for STM32F10x Connectivity line, + * High density, High density value line, Medium density, + * Medium density Value line, Low density, Low density Value line + * and XL-density devices. + * + * The file is the unique include file that the application programmer + * is using in the C source code, usually in main.c. This file contains: + * - Configuration section that allows to select: + * - The device used in the target application + * - To use or not the peripheral抯 drivers in application code(i.e. + * code will be based on direct access to peripheral抯 registers + * rather than drivers API), this option is controlled by + * "#define USE_STDPERIPH_DRIVER" + * - To change few application-specific parameters such as the HSE + * crystal frequency + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral抯 registers hardware + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2011 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f10x + * @{ + */ + +#ifndef __STM32F10x_H +#define __STM32F10x_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/* Uncomment the line below according to the target STM32 device used in your + application + */ + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) + /* #define STM32F10X_LD */ /*!< STM32F10X_LD: STM32 Low density devices */ + /* #define STM32F10X_LD_VL */ /*!< STM32F10X_LD_VL: STM32 Low density Value Line devices */ + /* #define STM32F10X_MD */ /*!< STM32F10X_MD: STM32 Medium density devices */ + /* #define STM32F10X_MD_VL */ /*!< STM32F10X_MD_VL: STM32 Medium density Value Line devices */ + /* #define STM32F10X_HD */ /*!< STM32F10X_HD: STM32 High density devices */ + /* #define STM32F10X_HD_VL */ /*!< STM32F10X_HD_VL: STM32 High density value line devices */ + /* #define STM32F10X_XL */ /*!< STM32F10X_XL: STM32 XL-density devices */ + /* #define STM32F10X_CL */ /*!< STM32F10X_CL: STM32 Connectivity line devices */ +#endif +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + + - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers + where the Flash memory density ranges between 16 and 32 Kbytes. + - Low-density value line devices are STM32F100xx microcontrollers where the Flash + memory density ranges between 16 and 32 Kbytes. + - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers + where the Flash memory density ranges between 64 and 128 Kbytes. + - Medium-density value line devices are STM32F100xx microcontrollers where the + Flash memory density ranges between 64 and 128 Kbytes. + - High-density devices are STM32F101xx and STM32F103xx microcontrollers where + the Flash memory density ranges between 256 and 512 Kbytes. + - High-density value line devices are STM32F100xx microcontrollers where the + Flash memory density ranges between 256 and 512 Kbytes. + - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where + the Flash memory density ranges between 512 and 1024 Kbytes. + - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. + */ + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) + #error "Please select first the target STM32F10x device used in your application (in stm32f10x.h file)" +#endif + +#if !defined (USE_STDPERIPH_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_STDPERIPH_DRIVER*/ +#endif /* USE_STDPERIPH_DRIVER */ + +/** + * @brief In the following line adjust the value of External High Speed oscillator (HSE) + used in your application + + Tip: To avoid modifying this file each time you need to use different HSE, you + can define the HSE value in your toolchain compiler preprocessor. + */ +#if !defined HSE_VALUE + #ifdef STM32F10X_CL + #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ + #else + #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ + #endif /* STM32F10X_CL */ +#endif /* HSE_VALUE */ + +/** + * @brief In the following line adjust the External High Speed oscillator (HSE) Startup + Timeout value + */ +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ +#endif /* HSE_STARTUP_TIMEOUT */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief STM32F10x Standard Peripheral Library version number V3.6.4 + */ +#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:24] main version */ +#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x06) /*!< [23:16] sub1 version */ +#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x04) /*!< [15:8] sub2 version */ +#define __STM32F10X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F10X_STDPERIPH_VERSION ((__STM32F10X_STDPERIPH_VERSION_MAIN << 24)\ + |(__STM32F10X_STDPERIPH_VERSION_SUB1 << 16)\ + |(__STM32F10X_STDPERIPH_VERSION_SUB2 << 8)\ + |(__STM32F10X_STDPERIPH_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M3 Processor and Core Peripherals + */ +#ifdef STM32F10X_XL + #define __MPU_PRESENT 1 /*!< STM32 XL-density devices provide an MPU */ +#else + #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */ +#endif /* STM32F10X_XL */ +#define __CM3_REV 0x0200 /*!< Core Revision r2p0 */ +#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * @brief STM32F10x Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** STM32 specific Interrupt Numbers *********************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMPER_IRQn = 2, /*!< Tamper Interrupt */ + RTC_IRQn = 3, /*!< RTC global Interrupt */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + +#ifdef STM32F10X_LD + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ +#endif /* STM32F10X_LD */ + +#ifdef STM32F10X_LD_VL + ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ + TIM7_IRQn = 55 /*!< TIM7 Interrupt */ +#endif /* STM32F10X_LD_VL */ + +#ifdef STM32F10X_MD + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ +#endif /* STM32F10X_MD */ + +#ifdef STM32F10X_MD_VL + ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ + TIM7_IRQn = 55 /*!< TIM7 Interrupt */ +#endif /* STM32F10X_MD_VL */ + +#ifdef STM32F10X_HD + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ + FSMC_IRQn = 48, /*!< FSMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ + TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ +#endif /* STM32F10X_HD */ + +#ifdef STM32F10X_HD_VL + ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ + TIM12_IRQn = 43, /*!< TIM12 global Interrupt */ + TIM13_IRQn = 44, /*!< TIM13 global Interrupt */ + TIM14_IRQn = 45, /*!< TIM14 global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ + TIM7_IRQn = 55, /*!< TIM7 Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ + DMA2_Channel5_IRQn = 60 /*!< DMA2 Channel 5 global Interrupt (DMA2 Channel 5 is + mapped at position 60 only if the MISC_REMAP bit in + the AFIO_MAPR2 register is set) */ +#endif /* STM32F10X_HD_VL */ + +#ifdef STM32F10X_XL + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break Interrupt and TIM9 global Interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global Interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global Interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global Interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ + FSMC_IRQn = 48, /*!< FSMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ + TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ +#endif /* STM32F10X_XL */ + +#ifdef STM32F10X_CL + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ + TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ + CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ + CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ + OTG_FS_IRQn = 67 /*!< USB OTG FS global Interrupt */ +#endif /* STM32F10X_CL */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm3.h" +#include "system_stm32f10x.h" +#include + +/** @addtogroup Exported_types + * @{ + */ + +/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef const int32_t sc32; /*!< Read Only */ +typedef const int16_t sc16; /*!< Read Only */ +typedef const int8_t sc8; /*!< Read Only */ + +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef __I int32_t vsc32; /*!< Read Only */ +typedef __I int16_t vsc16; /*!< Read Only */ +typedef __I int8_t vsc8; /*!< Read Only */ + +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef const uint32_t uc32; /*!< Read Only */ +typedef const uint16_t uc16; /*!< Read Only */ +typedef const uint8_t uc8; /*!< Read Only */ + +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +typedef __I uint32_t vuc32; /*!< Read Only */ +typedef __I uint16_t vuc16; /*!< Read Only */ +typedef __I uint8_t vuc8; /*!< Read Only */ + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +/*!< STM32F10x Standard Peripheral Library old definitions (maintained for legacy purpose) */ +#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT +#define HSE_Value HSE_VALUE +#define HSI_Value HSI_VALUE +/** + * @} + */ + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t SMPR1; + __IO uint32_t SMPR2; + __IO uint32_t JOFR1; + __IO uint32_t JOFR2; + __IO uint32_t JOFR3; + __IO uint32_t JOFR4; + __IO uint32_t HTR; + __IO uint32_t LTR; + __IO uint32_t SQR1; + __IO uint32_t SQR2; + __IO uint32_t SQR3; + __IO uint32_t JSQR; + __IO uint32_t JDR1; + __IO uint32_t JDR2; + __IO uint32_t JDR3; + __IO uint32_t JDR4; + __IO uint32_t DR; +} ADC_TypeDef; + +/** + * @brief Backup Registers + */ + +typedef struct +{ + uint32_t RESERVED0; + __IO uint16_t DR1; + uint16_t RESERVED1; + __IO uint16_t DR2; + uint16_t RESERVED2; + __IO uint16_t DR3; + uint16_t RESERVED3; + __IO uint16_t DR4; + uint16_t RESERVED4; + __IO uint16_t DR5; + uint16_t RESERVED5; + __IO uint16_t DR6; + uint16_t RESERVED6; + __IO uint16_t DR7; + uint16_t RESERVED7; + __IO uint16_t DR8; + uint16_t RESERVED8; + __IO uint16_t DR9; + uint16_t RESERVED9; + __IO uint16_t DR10; + uint16_t RESERVED10; + __IO uint16_t RTCCR; + uint16_t RESERVED11; + __IO uint16_t CR; + uint16_t RESERVED12; + __IO uint16_t CSR; + uint16_t RESERVED13[5]; + __IO uint16_t DR11; + uint16_t RESERVED14; + __IO uint16_t DR12; + uint16_t RESERVED15; + __IO uint16_t DR13; + uint16_t RESERVED16; + __IO uint16_t DR14; + uint16_t RESERVED17; + __IO uint16_t DR15; + uint16_t RESERVED18; + __IO uint16_t DR16; + uint16_t RESERVED19; + __IO uint16_t DR17; + uint16_t RESERVED20; + __IO uint16_t DR18; + uint16_t RESERVED21; + __IO uint16_t DR19; + uint16_t RESERVED22; + __IO uint16_t DR20; + uint16_t RESERVED23; + __IO uint16_t DR21; + uint16_t RESERVED24; + __IO uint16_t DR22; + uint16_t RESERVED25; + __IO uint16_t DR23; + uint16_t RESERVED26; + __IO uint16_t DR24; + uint16_t RESERVED27; + __IO uint16_t DR25; + uint16_t RESERVED28; + __IO uint16_t DR26; + uint16_t RESERVED29; + __IO uint16_t DR27; + uint16_t RESERVED30; + __IO uint16_t DR28; + uint16_t RESERVED31; + __IO uint16_t DR29; + uint16_t RESERVED32; + __IO uint16_t DR30; + uint16_t RESERVED33; + __IO uint16_t DR31; + uint16_t RESERVED34; + __IO uint16_t DR32; + uint16_t RESERVED35; + __IO uint16_t DR33; + uint16_t RESERVED36; + __IO uint16_t DR34; + uint16_t RESERVED37; + __IO uint16_t DR35; + uint16_t RESERVED38; + __IO uint16_t DR36; + uint16_t RESERVED39; + __IO uint16_t DR37; + uint16_t RESERVED40; + __IO uint16_t DR38; + uint16_t RESERVED41; + __IO uint16_t DR39; + uint16_t RESERVED42; + __IO uint16_t DR40; + uint16_t RESERVED43; + __IO uint16_t DR41; + uint16_t RESERVED44; + __IO uint16_t DR42; + uint16_t RESERVED45; +} BKP_TypeDef; + +/** + * @brief Controller Area Network TxMailBox + */ + +typedef struct +{ + __IO uint32_t TIR; + __IO uint32_t TDTR; + __IO uint32_t TDLR; + __IO uint32_t TDHR; +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ + +typedef struct +{ + __IO uint32_t RIR; + __IO uint32_t RDTR; + __IO uint32_t RDLR; + __IO uint32_t RDHR; +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ + +typedef struct +{ + __IO uint32_t FR1; + __IO uint32_t FR2; +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCR; + __IO uint32_t MSR; + __IO uint32_t TSR; + __IO uint32_t RF0R; + __IO uint32_t RF1R; + __IO uint32_t IER; + __IO uint32_t ESR; + __IO uint32_t BTR; + uint32_t RESERVED0[88]; + CAN_TxMailBox_TypeDef sTxMailBox[3]; + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; + uint32_t RESERVED1[12]; + __IO uint32_t FMR; + __IO uint32_t FM1R; + uint32_t RESERVED2; + __IO uint32_t FS1R; + uint32_t RESERVED3; + __IO uint32_t FFA1R; + uint32_t RESERVED4; + __IO uint32_t FA1R; + uint32_t RESERVED5[8]; +#ifndef STM32F10X_CL + CAN_FilterRegister_TypeDef sFilterRegister[14]; +#else + CAN_FilterRegister_TypeDef sFilterRegister[28]; +#endif /* STM32F10X_CL */ +} CAN_TypeDef; + +/** + * @brief Consumer Electronics Control (CEC) + */ +typedef struct +{ + __IO uint32_t CFGR; + __IO uint32_t OAR; + __IO uint32_t PRES; + __IO uint32_t ESR; + __IO uint32_t CSR; + __IO uint32_t TXD; + __IO uint32_t RXD; +} CEC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; + __IO uint8_t IDR; + uint8_t RESERVED0; + uint16_t RESERVED1; + __IO uint32_t CR; +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t SWTRIGR; + __IO uint32_t DHR12R1; + __IO uint32_t DHR12L1; + __IO uint32_t DHR8R1; + __IO uint32_t DHR12R2; + __IO uint32_t DHR12L2; + __IO uint32_t DHR8R2; + __IO uint32_t DHR12RD; + __IO uint32_t DHR12LD; + __IO uint32_t DHR8RD; + __IO uint32_t DOR1; + __IO uint32_t DOR2; +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + __IO uint32_t SR; +#endif +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; + __IO uint32_t CR; +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; + __IO uint32_t CNDTR; + __IO uint32_t CPAR; + __IO uint32_t CMAR; +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; + __IO uint32_t IFCR; +} DMA_TypeDef; + +/** + * @brief Ethernet MAC + */ + +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACFFR; + __IO uint32_t MACHTHR; + __IO uint32_t MACHTLR; + __IO uint32_t MACMIIAR; + __IO uint32_t MACMIIDR; + __IO uint32_t MACFCR; + __IO uint32_t MACVLANTR; /* 8 */ + uint32_t RESERVED0[2]; + __IO uint32_t MACRWUFFR; /* 11 */ + __IO uint32_t MACPMTCSR; + uint32_t RESERVED1[2]; + __IO uint32_t MACSR; /* 15 */ + __IO uint32_t MACIMR; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; /* 24 */ + uint32_t RESERVED2[40]; + __IO uint32_t MMCCR; /* 65 */ + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; /* 69 */ + uint32_t RESERVED3[14]; + __IO uint32_t MMCTGFSCCR; /* 84 */ + __IO uint32_t MMCTGFMSCCR; + uint32_t RESERVED4[5]; + __IO uint32_t MMCTGFCR; + uint32_t RESERVED5[10]; + __IO uint32_t MMCRFCECR; + __IO uint32_t MMCRFAECR; + uint32_t RESERVED6[10]; + __IO uint32_t MMCRGUFCR; + uint32_t RESERVED7[334]; + __IO uint32_t PTPTSCR; + __IO uint32_t PTPSSIR; + __IO uint32_t PTPTSHR; + __IO uint32_t PTPTSLR; + __IO uint32_t PTPTSHUR; + __IO uint32_t PTPTSLUR; + __IO uint32_t PTPTSAR; + __IO uint32_t PTPTTHR; + __IO uint32_t PTPTTLR; + uint32_t RESERVED8[567]; + __IO uint32_t DMABMR; + __IO uint32_t DMATPDR; + __IO uint32_t DMARPDR; + __IO uint32_t DMARDLAR; + __IO uint32_t DMATDLAR; + __IO uint32_t DMASR; + __IO uint32_t DMAOMR; + __IO uint32_t DMAIER; + __IO uint32_t DMAMFBOCR; + uint32_t RESERVED9[9]; + __IO uint32_t DMACHTDR; + __IO uint32_t DMACHRDR; + __IO uint32_t DMACHTBAR; + __IO uint32_t DMACHRBAR; +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; + __IO uint32_t EMR; + __IO uint32_t RTSR; + __IO uint32_t FTSR; + __IO uint32_t SWIER; + __IO uint32_t PR; +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; + __IO uint32_t KEYR; + __IO uint32_t OPTKEYR; + __IO uint32_t SR; + __IO uint32_t CR; + __IO uint32_t AR; + __IO uint32_t RESERVED; + __IO uint32_t OBR; + __IO uint32_t WRPR; +#ifdef STM32F10X_XL + uint32_t RESERVED1[8]; + __IO uint32_t KEYR2; + uint32_t RESERVED2; + __IO uint32_t SR2; + __IO uint32_t CR2; + __IO uint32_t AR2; +#endif /* STM32F10X_XL */ +} FLASH_TypeDef; + +/** + * @brief Option Bytes Registers + */ + +typedef struct +{ + __IO uint16_t RDP; + __IO uint16_t USER; + __IO uint16_t Data0; + __IO uint16_t Data1; + __IO uint16_t WRP0; + __IO uint16_t WRP1; + __IO uint16_t WRP2; + __IO uint16_t WRP3; +} OB_TypeDef; + +/** + * @brief Flexible Static Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; +} FSMC_Bank1_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; +} FSMC_Bank1E_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank2 + */ + +typedef struct +{ + __IO uint32_t PCR2; + __IO uint32_t SR2; + __IO uint32_t PMEM2; + __IO uint32_t PATT2; + uint32_t RESERVED0; + __IO uint32_t ECCR2; +} FSMC_Bank2_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR3; + __IO uint32_t SR3; + __IO uint32_t PMEM3; + __IO uint32_t PATT3; + uint32_t RESERVED0; + __IO uint32_t ECCR3; +} FSMC_Bank3_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank4 + */ + +typedef struct +{ + __IO uint32_t PCR4; + __IO uint32_t SR4; + __IO uint32_t PMEM4; + __IO uint32_t PATT4; + __IO uint32_t PIO4; +} FSMC_Bank4_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t CRL; + __IO uint32_t CRH; + __IO uint32_t IDR; + __IO uint32_t ODR; + __IO uint32_t BSRR; + __IO uint32_t BRR; + __IO uint32_t LCKR; +} GPIO_TypeDef; + +/** + * @brief Alternate Function I/O + */ + +typedef struct +{ + __IO uint32_t EVCR; + __IO uint32_t MAPR; + __IO uint32_t EXTICR[4]; + uint32_t RESERVED0; + __IO uint32_t MAPR2; +} AFIO_TypeDef; +/** + * @brief Inter Integrated Circuit Interface + */ + +typedef struct +{ + __IO uint16_t CR1; + uint16_t RESERVED0; + __IO uint16_t CR2; + uint16_t RESERVED1; + __IO uint16_t OAR1; + uint16_t RESERVED2; + __IO uint16_t OAR2; + uint16_t RESERVED3; + __IO uint16_t DR; + uint16_t RESERVED4; + __IO uint16_t SR1; + uint16_t RESERVED5; + __IO uint16_t SR2; + uint16_t RESERVED6; + __IO uint16_t CCR; + uint16_t RESERVED7; + __IO uint16_t TRISE; + uint16_t RESERVED8; +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; + __IO uint32_t PR; + __IO uint32_t RLR; + __IO uint32_t SR; +} IWDG_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CSR; +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CFGR; + __IO uint32_t CIR; + __IO uint32_t APB2RSTR; + __IO uint32_t APB1RSTR; + __IO uint32_t AHBENR; + __IO uint32_t APB2ENR; + __IO uint32_t APB1ENR; + __IO uint32_t BDCR; + __IO uint32_t CSR; + +#ifdef STM32F10X_CL + __IO uint32_t AHBRSTR; + __IO uint32_t CFGR2; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + uint32_t RESERVED0; + __IO uint32_t CFGR2; +#endif /* STM32F10X_LD_VL || STM32F10X_MD_VL || STM32F10X_HD_VL */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint16_t CRH; + uint16_t RESERVED0; + __IO uint16_t CRL; + uint16_t RESERVED1; + __IO uint16_t PRLH; + uint16_t RESERVED2; + __IO uint16_t PRLL; + uint16_t RESERVED3; + __IO uint16_t DIVH; + uint16_t RESERVED4; + __IO uint16_t DIVL; + uint16_t RESERVED5; + __IO uint16_t CNTH; + uint16_t RESERVED6; + __IO uint16_t CNTL; + uint16_t RESERVED7; + __IO uint16_t ALRH; + uint16_t RESERVED8; + __IO uint16_t ALRL; + uint16_t RESERVED9; +} RTC_TypeDef; + +/** + * @brief SD host Interface + */ + +typedef struct +{ + __IO uint32_t POWER; + __IO uint32_t CLKCR; + __IO uint32_t ARG; + __IO uint32_t CMD; + __I uint32_t RESPCMD; + __I uint32_t RESP1; + __I uint32_t RESP2; + __I uint32_t RESP3; + __I uint32_t RESP4; + __IO uint32_t DTIMER; + __IO uint32_t DLEN; + __IO uint32_t DCTRL; + __I uint32_t DCOUNT; + __I uint32_t STA; + __IO uint32_t ICR; + __IO uint32_t MASK; + uint32_t RESERVED0[2]; + __I uint32_t FIFOCNT; + uint32_t RESERVED1[13]; + __IO uint32_t FIFO; +} SDIO_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint16_t CR1; + uint16_t RESERVED0; + __IO uint16_t CR2; + uint16_t RESERVED1; + __IO uint16_t SR; + uint16_t RESERVED2; + __IO uint16_t DR; + uint16_t RESERVED3; + __IO uint16_t CRCPR; + uint16_t RESERVED4; + __IO uint16_t RXCRCR; + uint16_t RESERVED5; + __IO uint16_t TXCRCR; + uint16_t RESERVED6; + __IO uint16_t I2SCFGR; + uint16_t RESERVED7; + __IO uint16_t I2SPR; + uint16_t RESERVED8; +} SPI_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint16_t CR1; + uint16_t RESERVED0; + __IO uint16_t CR2; + uint16_t RESERVED1; + __IO uint16_t SMCR; + uint16_t RESERVED2; + __IO uint16_t DIER; + uint16_t RESERVED3; + __IO uint16_t SR; + uint16_t RESERVED4; + __IO uint16_t EGR; + uint16_t RESERVED5; + __IO uint16_t CCMR1; + uint16_t RESERVED6; + __IO uint16_t CCMR2; + uint16_t RESERVED7; + __IO uint16_t CCER; + uint16_t RESERVED8; + __IO uint16_t CNT; + uint16_t RESERVED9; + __IO uint16_t PSC; + uint16_t RESERVED10; + __IO uint16_t ARR; + uint16_t RESERVED11; + __IO uint16_t RCR; + uint16_t RESERVED12; + __IO uint16_t CCR1; + uint16_t RESERVED13; + __IO uint16_t CCR2; + uint16_t RESERVED14; + __IO uint16_t CCR3; + uint16_t RESERVED15; + __IO uint16_t CCR4; + uint16_t RESERVED16; + __IO uint16_t BDTR; + uint16_t RESERVED17; + __IO uint16_t DCR; + uint16_t RESERVED18; + __IO uint16_t DMAR; + uint16_t RESERVED19; +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint16_t SR; + uint16_t RESERVED0; + __IO uint16_t DR; + uint16_t RESERVED1; + __IO uint16_t BRR; + uint16_t RESERVED2; + __IO uint16_t CR1; + uint16_t RESERVED3; + __IO uint16_t CR2; + uint16_t RESERVED4; + __IO uint16_t CR3; + uint16_t RESERVED5; + __IO uint16_t GTPR; + uint16_t RESERVED6; +} USART_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CFR; + __IO uint32_t SR; +} WWDG_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ + + +#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ + +#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ + +#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) + +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) +#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) +#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) +#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) +#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400) +#define CEC_BASE (APB1PERIPH_BASE + 0x7800) + +#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) +#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) +#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) +#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) +#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) +#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) +#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) +#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800) +#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00) +#define TIM10_BASE (APB2PERIPH_BASE + 0x5000) +#define TIM11_BASE (APB2PERIPH_BASE + 0x5400) + +#define SDIO_BASE (PERIPH_BASE + 0x18000) + +#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) +#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) +#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) +#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) +#define DMA2_BASE (AHBPERIPH_BASE + 0x0400) +#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) +#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) +#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) +#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) +#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) +#define RCC_BASE (AHBPERIPH_BASE + 0x1000) +#define CRC_BASE (AHBPERIPH_BASE + 0x3000) + +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */ +#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */ + +#define ETH_BASE (AHBPERIPH_BASE + 0x8000) +#define ETH_MAC_BASE (ETH_BASE) +#define ETH_MMC_BASE (ETH_BASE + 0x0100) +#define ETH_PTP_BASE (ETH_BASE + 0x0700) +#define ETH_DMA_BASE (ETH_BASE + 0x1000) + +#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */ +#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */ +#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2 registers base address */ +#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) /*!< FSMC Bank3 registers base address */ +#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */ + +#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ + +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) +#define CAN2 ((CAN_TypeDef *) CAN2_BASE) +#define BKP ((BKP_TypeDef *) BKP_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define CEC ((CEC_TypeDef *) CEC_BASE) +#define AFIO ((AFIO_TypeDef *) AFIO_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define OB ((OB_TypeDef *) OB_BASE) +#define ETH ((ETH_TypeDef *) ETH_BASE) +#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) +#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) +#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) +#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) +#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ + + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ + + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */ + +/******************************************************************************/ +/* */ +/* Power Control */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for PWR_CR register ********************/ +#define PWR_CR_LPDS ((uint16_t)0x0001) /*!< Low-Power Deepsleep */ +#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */ +#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */ +#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */ +#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */ + +#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */ +#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */ +#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */ + +/*!< PVD level configuration */ +#define PWR_CR_PLS_2V2 ((uint16_t)0x0000) /*!< PVD level 2.2V */ +#define PWR_CR_PLS_2V3 ((uint16_t)0x0020) /*!< PVD level 2.3V */ +#define PWR_CR_PLS_2V4 ((uint16_t)0x0040) /*!< PVD level 2.4V */ +#define PWR_CR_PLS_2V5 ((uint16_t)0x0060) /*!< PVD level 2.5V */ +#define PWR_CR_PLS_2V6 ((uint16_t)0x0080) /*!< PVD level 2.6V */ +#define PWR_CR_PLS_2V7 ((uint16_t)0x00A0) /*!< PVD level 2.7V */ +#define PWR_CR_PLS_2V8 ((uint16_t)0x00C0) /*!< PVD level 2.8V */ +#define PWR_CR_PLS_2V9 ((uint16_t)0x00E0) /*!< PVD level 2.9V */ + +#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */ + + +/******************* Bit definition for PWR_CSR register ********************/ +#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */ +#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */ +#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */ +#define PWR_CSR_EWUP ((uint16_t)0x0100) /*!< Enable WKUP pin */ + +/******************************************************************************/ +/* */ +/* Backup registers */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for BKP_DR1 register ********************/ +#define BKP_DR1_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR2 register ********************/ +#define BKP_DR2_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR3 register ********************/ +#define BKP_DR3_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR4 register ********************/ +#define BKP_DR4_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR5 register ********************/ +#define BKP_DR5_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR6 register ********************/ +#define BKP_DR6_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR7 register ********************/ +#define BKP_DR7_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR8 register ********************/ +#define BKP_DR8_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR9 register ********************/ +#define BKP_DR9_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR10 register *******************/ +#define BKP_DR10_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR11 register *******************/ +#define BKP_DR11_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR12 register *******************/ +#define BKP_DR12_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR13 register *******************/ +#define BKP_DR13_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR14 register *******************/ +#define BKP_DR14_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR15 register *******************/ +#define BKP_DR15_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR16 register *******************/ +#define BKP_DR16_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR17 register *******************/ +#define BKP_DR17_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/****************** Bit definition for BKP_DR18 register ********************/ +#define BKP_DR18_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR19 register *******************/ +#define BKP_DR19_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR20 register *******************/ +#define BKP_DR20_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR21 register *******************/ +#define BKP_DR21_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR22 register *******************/ +#define BKP_DR22_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR23 register *******************/ +#define BKP_DR23_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR24 register *******************/ +#define BKP_DR24_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR25 register *******************/ +#define BKP_DR25_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR26 register *******************/ +#define BKP_DR26_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR27 register *******************/ +#define BKP_DR27_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR28 register *******************/ +#define BKP_DR28_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR29 register *******************/ +#define BKP_DR29_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR30 register *******************/ +#define BKP_DR30_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR31 register *******************/ +#define BKP_DR31_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR32 register *******************/ +#define BKP_DR32_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR33 register *******************/ +#define BKP_DR33_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR34 register *******************/ +#define BKP_DR34_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR35 register *******************/ +#define BKP_DR35_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR36 register *******************/ +#define BKP_DR36_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR37 register *******************/ +#define BKP_DR37_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR38 register *******************/ +#define BKP_DR38_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR39 register *******************/ +#define BKP_DR39_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR40 register *******************/ +#define BKP_DR40_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR41 register *******************/ +#define BKP_DR41_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR42 register *******************/ +#define BKP_DR42_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/****************** Bit definition for BKP_RTCCR register *******************/ +#define BKP_RTCCR_CAL ((uint16_t)0x007F) /*!< Calibration value */ +#define BKP_RTCCR_CCO ((uint16_t)0x0080) /*!< Calibration Clock Output */ +#define BKP_RTCCR_ASOE ((uint16_t)0x0100) /*!< Alarm or Second Output Enable */ +#define BKP_RTCCR_ASOS ((uint16_t)0x0200) /*!< Alarm or Second Output Selection */ + +/******************** Bit definition for BKP_CR register ********************/ +#define BKP_CR_TPE ((uint8_t)0x01) /*!< TAMPER pin enable */ +#define BKP_CR_TPAL ((uint8_t)0x02) /*!< TAMPER pin active level */ + +/******************* Bit definition for BKP_CSR register ********************/ +#define BKP_CSR_CTE ((uint16_t)0x0001) /*!< Clear Tamper event */ +#define BKP_CSR_CTI ((uint16_t)0x0002) /*!< Clear Tamper Interrupt */ +#define BKP_CSR_TPIE ((uint16_t)0x0004) /*!< TAMPER Pin interrupt enable */ +#define BKP_CSR_TEF ((uint16_t)0x0100) /*!< Tamper Event Flag */ +#define BKP_CSR_TIF ((uint16_t)0x0200) /*!< Tamper Interrupt Flag */ + +/******************************************************************************/ +/* */ +/* Reset and Clock Control */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for RCC_CR register ********************/ +#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */ +#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */ +#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */ +#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */ +#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */ +#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */ +#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */ +#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */ +#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */ +#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */ + +#ifdef STM32F10X_CL + #define RCC_CR_PLL2ON ((uint32_t)0x04000000) /*!< PLL2 enable */ + #define RCC_CR_PLL2RDY ((uint32_t)0x08000000) /*!< PLL2 clock ready flag */ + #define RCC_CR_PLL3ON ((uint32_t)0x10000000) /*!< PLL3 enable */ + #define RCC_CR_PLL3RDY ((uint32_t)0x20000000) /*!< PLL3 clock ready flag */ +#endif /* STM32F10X_CL */ + +/******************* Bit definition for RCC_CFGR register *******************/ +/*!< SW configuration */ +#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */ +#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + +#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */ +#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */ +#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */ + +/*!< SWS configuration */ +#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */ +#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */ +#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */ + +/*!< HPRE configuration */ +#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */ +#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ +#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ +#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ +#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ +#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ +#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ +#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ +#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ +#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ + +/*!< PPRE1 configuration */ +#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */ +#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ + +#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ +#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */ + +/*!< PPRE2 configuration */ +#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */ +#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */ +#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */ +#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */ + +#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ +#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */ + +/*!< ADCPPRE configuration */ +#define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /*!< ADCPRE[1:0] bits (ADC prescaler) */ +#define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /*!< Bit 0 */ +#define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /*!< Bit 1 */ + +#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */ +#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */ +#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */ +#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */ + +#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */ + +#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */ + +/*!< PLLMUL configuration */ +#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ +#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */ +#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */ + +#ifdef STM32F10X_CL + #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ + #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ + + #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ + #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ + + #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock * 4 */ + #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock * 5 */ + #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock * 6 */ + #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock * 7 */ + #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock * 8 */ + #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock * 9 */ + #define RCC_CFGR_PLLMULL6_5 ((uint32_t)0x00340000) /*!< PLL input clock * 6.5 */ + + #define RCC_CFGR_OTGFSPRE ((uint32_t)0x00400000) /*!< USB OTG FS prescaler */ + +/*!< MCO configuration */ + #define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */ + #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ + #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + #define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + + #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ + #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ + #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ + #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ + #define RCC_CFGR_MCO_PLLCLK_Div2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ + #define RCC_CFGR_MCO_PLL2CLK ((uint32_t)0x08000000) /*!< PLL2 clock selected as MCO source*/ + #define RCC_CFGR_MCO_PLL3CLK_Div2 ((uint32_t)0x09000000) /*!< PLL3 clock divided by 2 selected as MCO source*/ + #define RCC_CFGR_MCO_Ext_HSE ((uint32_t)0x0A000000) /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */ + #define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) /*!< PLL3 clock selected as MCO source */ +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ + #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ + + #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ + #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ + + #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ + #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ + #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ + #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ + #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ + #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ + #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ + #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ + #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ + #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ + #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ + #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ + #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ + #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ + #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ + +/*!< MCO configuration */ + #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ + #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ + #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + + #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ + #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ + #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ + #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ + #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ +#else + #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ + #define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */ + + #define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */ + #define RCC_CFGR_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */ + + #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ + #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ + #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ + #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ + #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ + #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ + #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ + #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ + #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ + #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ + #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ + #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ + #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ + #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ + #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ + #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB Device prescaler */ + +/*!< MCO configuration */ + #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ + #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ + #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + + #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ + #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ + #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ + #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ + #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ +#endif /* STM32F10X_CL */ + +/*!<****************** Bit definition for RCC_CIR register ********************/ +#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */ +#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */ +#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */ +#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */ +#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */ +#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */ +#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */ +#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */ +#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */ +#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */ +#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */ +#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */ +#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */ +#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */ +#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */ +#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */ +#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */ + +#ifdef STM32F10X_CL + #define RCC_CIR_PLL2RDYF ((uint32_t)0x00000020) /*!< PLL2 Ready Interrupt flag */ + #define RCC_CIR_PLL3RDYF ((uint32_t)0x00000040) /*!< PLL3 Ready Interrupt flag */ + #define RCC_CIR_PLL2RDYIE ((uint32_t)0x00002000) /*!< PLL2 Ready Interrupt Enable */ + #define RCC_CIR_PLL3RDYIE ((uint32_t)0x00004000) /*!< PLL3 Ready Interrupt Enable */ + #define RCC_CIR_PLL2RDYC ((uint32_t)0x00200000) /*!< PLL2 Ready Interrupt Clear */ + #define RCC_CIR_PLL3RDYC ((uint32_t)0x00400000) /*!< PLL3 Ready Interrupt Clear */ +#endif /* STM32F10X_CL */ + +/***************** Bit definition for RCC_APB2RSTR register *****************/ +#define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */ +#define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */ +#define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) /*!< I/O port B reset */ +#define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) /*!< I/O port C reset */ +#define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) /*!< I/O port D reset */ +#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC 1 interface reset */ + +#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) +#define RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) /*!< ADC 2 interface reset */ +#endif + +#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */ +#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */ +#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 Timer reset */ +#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 Timer reset */ +#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 Timer reset */ +#endif + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) + #define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) /*!< I/O port E reset */ +#endif /* STM32F10X_LD && STM32F10X_LD_VL */ + +#if defined (STM32F10X_HD) || defined (STM32F10X_XL) + #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */ + #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */ + #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000) /*!< TIM8 Timer reset */ + #define RCC_APB2RSTR_ADC3RST ((uint32_t)0x00008000) /*!< ADC3 interface reset */ +#endif + +#if defined (STM32F10X_HD_VL) + #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */ + #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */ +#endif + +#ifdef STM32F10X_XL + #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00080000) /*!< TIM9 Timer reset */ + #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00100000) /*!< TIM10 Timer reset */ + #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00200000) /*!< TIM11 Timer reset */ +#endif /* STM32F10X_XL */ + +/***************** Bit definition for RCC_APB1RSTR register *****************/ +#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */ +#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */ +#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */ +#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */ +#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */ + +#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) +#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /*!< CAN1 reset */ +#endif + +#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */ +#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */ + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) + #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */ + #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */ + #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */ + #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */ +#endif /* STM32F10X_LD && STM32F10X_LD_VL */ + +#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) || defined (STM32F10X_XL) + #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */ +#endif + +#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_XL) + #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */ + #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ + #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ + #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */ + #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */ + #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */ + #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ +#endif + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ + #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ + #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ + #define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC interface reset */ +#endif + +#if defined (STM32F10X_HD_VL) + #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */ + #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */ + #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */ + #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */ + #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */ + #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */ + #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */ +#endif + +#ifdef STM32F10X_CL + #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000) /*!< CAN2 reset */ +#endif /* STM32F10X_CL */ + +#ifdef STM32F10X_XL + #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */ + #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */ + #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */ +#endif /* STM32F10X_XL */ + +/****************** Bit definition for RCC_AHBENR register ******************/ +#define RCC_AHBENR_DMA1EN ((uint16_t)0x0001) /*!< DMA1 clock enable */ +#define RCC_AHBENR_SRAMEN ((uint16_t)0x0004) /*!< SRAM interface clock enable */ +#define RCC_AHBENR_FLITFEN ((uint16_t)0x0010) /*!< FLITF clock enable */ +#define RCC_AHBENR_CRCEN ((uint16_t)0x0040) /*!< CRC clock enable */ + +#if defined (STM32F10X_HD) || defined (STM32F10X_XL) || defined (STM32F10X_CL) || defined (STM32F10X_HD_VL) + #define RCC_AHBENR_DMA2EN ((uint16_t)0x0002) /*!< DMA2 clock enable */ +#endif + +#if defined (STM32F10X_HD) || defined (STM32F10X_XL) + #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */ + #define RCC_AHBENR_SDIOEN ((uint16_t)0x0400) /*!< SDIO clock enable */ +#endif + +#if defined (STM32F10X_HD_VL) + #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */ +#endif + +#ifdef STM32F10X_CL + #define RCC_AHBENR_OTGFSEN ((uint32_t)0x00001000) /*!< USB OTG FS clock enable */ + #define RCC_AHBENR_ETHMACEN ((uint32_t)0x00004000) /*!< ETHERNET MAC clock enable */ + #define RCC_AHBENR_ETHMACTXEN ((uint32_t)0x00008000) /*!< ETHERNET MAC Tx clock enable */ + #define RCC_AHBENR_ETHMACRXEN ((uint32_t)0x00010000) /*!< ETHERNET MAC Rx clock enable */ +#endif /* STM32F10X_CL */ + +/****************** Bit definition for RCC_APB2ENR register *****************/ +#define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */ +#define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */ +#define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */ +#define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */ +#define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */ +#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC 1 interface clock enable */ + +#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) +#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) /*!< ADC 2 interface clock enable */ +#endif + +#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */ +#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI 1 clock enable */ +#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 Timer clock enable */ +#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 Timer clock enable */ +#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 Timer clock enable */ +#endif + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) + #define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) /*!< I/O port E clock enable */ +#endif /* STM32F10X_LD && STM32F10X_LD_VL */ + +#if defined (STM32F10X_HD) || defined (STM32F10X_XL) + #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */ + #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */ + #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 Timer clock enable */ + #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00008000) /*!< DMA1 clock enable */ +#endif + +#if defined (STM32F10X_HD_VL) + #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */ + #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */ +#endif + +#ifdef STM32F10X_XL + #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00080000) /*!< TIM9 Timer clock enable */ + #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00100000) /*!< TIM10 Timer clock enable */ + #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00200000) /*!< TIM11 Timer clock enable */ +#endif + +/***************** Bit definition for RCC_APB1ENR register ******************/ +#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/ +#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */ +#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */ +#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */ +#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */ + +#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) +#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /*!< CAN1 clock enable */ +#endif + +#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */ +#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */ + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) + #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */ + #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */ + #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */ + #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */ +#endif /* STM32F10X_LD && STM32F10X_LD_VL */ + +#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) + #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */ +#endif + +#if defined (STM32F10X_HD) || defined (STM32F10X_CL) + #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */ + #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ + #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ + #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */ + #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */ + #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */ + #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ +#endif + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ + #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ + #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ + #define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC interface clock enable */ +#endif + +#ifdef STM32F10X_HD_VL + #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */ + #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */ + #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */ + #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */ + #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */ + #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */ + #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */ +#endif /* STM32F10X_HD_VL */ + +#ifdef STM32F10X_CL + #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000) /*!< CAN2 clock enable */ +#endif /* STM32F10X_CL */ + +#ifdef STM32F10X_XL + #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */ + #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */ + #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */ +#endif /* STM32F10X_XL */ + +/******************* Bit definition for RCC_BDCR register *******************/ +#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */ +#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */ +#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */ + +#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */ +#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +/*!< RTC congiguration */ +#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ +#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */ +#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */ +#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */ + +#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */ +#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */ + +/******************* Bit definition for RCC_CSR register ********************/ +#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */ +#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */ +#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */ +#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */ +#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */ +#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */ +#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */ +#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */ +#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */ + +#ifdef STM32F10X_CL +/******************* Bit definition for RCC_AHBRSTR register ****************/ + #define RCC_AHBRSTR_OTGFSRST ((uint32_t)0x00001000) /*!< USB OTG FS reset */ + #define RCC_AHBRSTR_ETHMACRST ((uint32_t)0x00004000) /*!< ETHERNET MAC reset */ + +/******************* Bit definition for RCC_CFGR2 register ******************/ +/*!< PREDIV1 configuration */ + #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ + #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ + #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + + #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ + #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ + #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ + #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ + #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ + #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ + #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ + #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ + #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ + #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ + #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ + #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ + #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ + #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ + #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ + #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ + +/*!< PREDIV2 configuration */ + #define RCC_CFGR2_PREDIV2 ((uint32_t)0x000000F0) /*!< PREDIV2[3:0] bits */ + #define RCC_CFGR2_PREDIV2_0 ((uint32_t)0x00000010) /*!< Bit 0 */ + #define RCC_CFGR2_PREDIV2_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + #define RCC_CFGR2_PREDIV2_2 ((uint32_t)0x00000040) /*!< Bit 2 */ + #define RCC_CFGR2_PREDIV2_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + + #define RCC_CFGR2_PREDIV2_DIV1 ((uint32_t)0x00000000) /*!< PREDIV2 input clock not divided */ + #define RCC_CFGR2_PREDIV2_DIV2 ((uint32_t)0x00000010) /*!< PREDIV2 input clock divided by 2 */ + #define RCC_CFGR2_PREDIV2_DIV3 ((uint32_t)0x00000020) /*!< PREDIV2 input clock divided by 3 */ + #define RCC_CFGR2_PREDIV2_DIV4 ((uint32_t)0x00000030) /*!< PREDIV2 input clock divided by 4 */ + #define RCC_CFGR2_PREDIV2_DIV5 ((uint32_t)0x00000040) /*!< PREDIV2 input clock divided by 5 */ + #define RCC_CFGR2_PREDIV2_DIV6 ((uint32_t)0x00000050) /*!< PREDIV2 input clock divided by 6 */ + #define RCC_CFGR2_PREDIV2_DIV7 ((uint32_t)0x00000060) /*!< PREDIV2 input clock divided by 7 */ + #define RCC_CFGR2_PREDIV2_DIV8 ((uint32_t)0x00000070) /*!< PREDIV2 input clock divided by 8 */ + #define RCC_CFGR2_PREDIV2_DIV9 ((uint32_t)0x00000080) /*!< PREDIV2 input clock divided by 9 */ + #define RCC_CFGR2_PREDIV2_DIV10 ((uint32_t)0x00000090) /*!< PREDIV2 input clock divided by 10 */ + #define RCC_CFGR2_PREDIV2_DIV11 ((uint32_t)0x000000A0) /*!< PREDIV2 input clock divided by 11 */ + #define RCC_CFGR2_PREDIV2_DIV12 ((uint32_t)0x000000B0) /*!< PREDIV2 input clock divided by 12 */ + #define RCC_CFGR2_PREDIV2_DIV13 ((uint32_t)0x000000C0) /*!< PREDIV2 input clock divided by 13 */ + #define RCC_CFGR2_PREDIV2_DIV14 ((uint32_t)0x000000D0) /*!< PREDIV2 input clock divided by 14 */ + #define RCC_CFGR2_PREDIV2_DIV15 ((uint32_t)0x000000E0) /*!< PREDIV2 input clock divided by 15 */ + #define RCC_CFGR2_PREDIV2_DIV16 ((uint32_t)0x000000F0) /*!< PREDIV2 input clock divided by 16 */ + +/*!< PLL2MUL configuration */ + #define RCC_CFGR2_PLL2MUL ((uint32_t)0x00000F00) /*!< PLL2MUL[3:0] bits */ + #define RCC_CFGR2_PLL2MUL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ + #define RCC_CFGR2_PLL2MUL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + #define RCC_CFGR2_PLL2MUL_2 ((uint32_t)0x00000400) /*!< Bit 2 */ + #define RCC_CFGR2_PLL2MUL_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + + #define RCC_CFGR2_PLL2MUL8 ((uint32_t)0x00000600) /*!< PLL2 input clock * 8 */ + #define RCC_CFGR2_PLL2MUL9 ((uint32_t)0x00000700) /*!< PLL2 input clock * 9 */ + #define RCC_CFGR2_PLL2MUL10 ((uint32_t)0x00000800) /*!< PLL2 input clock * 10 */ + #define RCC_CFGR2_PLL2MUL11 ((uint32_t)0x00000900) /*!< PLL2 input clock * 11 */ + #define RCC_CFGR2_PLL2MUL12 ((uint32_t)0x00000A00) /*!< PLL2 input clock * 12 */ + #define RCC_CFGR2_PLL2MUL13 ((uint32_t)0x00000B00) /*!< PLL2 input clock * 13 */ + #define RCC_CFGR2_PLL2MUL14 ((uint32_t)0x00000C00) /*!< PLL2 input clock * 14 */ + #define RCC_CFGR2_PLL2MUL16 ((uint32_t)0x00000E00) /*!< PLL2 input clock * 16 */ + #define RCC_CFGR2_PLL2MUL20 ((uint32_t)0x00000F00) /*!< PLL2 input clock * 20 */ + +/*!< PLL3MUL configuration */ + #define RCC_CFGR2_PLL3MUL ((uint32_t)0x0000F000) /*!< PLL3MUL[3:0] bits */ + #define RCC_CFGR2_PLL3MUL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ + #define RCC_CFGR2_PLL3MUL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ + #define RCC_CFGR2_PLL3MUL_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + #define RCC_CFGR2_PLL3MUL_3 ((uint32_t)0x00008000) /*!< Bit 3 */ + + #define RCC_CFGR2_PLL3MUL8 ((uint32_t)0x00006000) /*!< PLL3 input clock * 8 */ + #define RCC_CFGR2_PLL3MUL9 ((uint32_t)0x00007000) /*!< PLL3 input clock * 9 */ + #define RCC_CFGR2_PLL3MUL10 ((uint32_t)0x00008000) /*!< PLL3 input clock * 10 */ + #define RCC_CFGR2_PLL3MUL11 ((uint32_t)0x00009000) /*!< PLL3 input clock * 11 */ + #define RCC_CFGR2_PLL3MUL12 ((uint32_t)0x0000A000) /*!< PLL3 input clock * 12 */ + #define RCC_CFGR2_PLL3MUL13 ((uint32_t)0x0000B000) /*!< PLL3 input clock * 13 */ + #define RCC_CFGR2_PLL3MUL14 ((uint32_t)0x0000C000) /*!< PLL3 input clock * 14 */ + #define RCC_CFGR2_PLL3MUL16 ((uint32_t)0x0000E000) /*!< PLL3 input clock * 16 */ + #define RCC_CFGR2_PLL3MUL20 ((uint32_t)0x0000F000) /*!< PLL3 input clock * 20 */ + + #define RCC_CFGR2_PREDIV1SRC ((uint32_t)0x00010000) /*!< PREDIV1 entry clock source */ + #define RCC_CFGR2_PREDIV1SRC_PLL2 ((uint32_t)0x00010000) /*!< PLL2 selected as PREDIV1 entry clock source */ + #define RCC_CFGR2_PREDIV1SRC_HSE ((uint32_t)0x00000000) /*!< HSE selected as PREDIV1 entry clock source */ + #define RCC_CFGR2_I2S2SRC ((uint32_t)0x00020000) /*!< I2S2 entry clock source */ + #define RCC_CFGR2_I2S3SRC ((uint32_t)0x00040000) /*!< I2S3 clock source */ +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +/******************* Bit definition for RCC_CFGR2 register ******************/ +/*!< PREDIV1 configuration */ + #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ + #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ + #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + + #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ + #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ + #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ + #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ + #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ + #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ + #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ + #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ + #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ + #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ + #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ + #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ + #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ + #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ + #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ + #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ +#endif + +/******************************************************************************/ +/* */ +/* General Purpose and Alternate Function I/O */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for GPIO_CRL register *******************/ +#define GPIO_CRL_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ + +#define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ +#define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + +#define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ +#define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ +#define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +#define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ +#define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ +#define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ +#define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ +#define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ +#define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ + +#define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ +#define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ +#define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +#define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ +#define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /*!< Bit 1 */ + +#define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ +#define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /*!< Bit 0 */ +#define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ +#define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ +#define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /*!< Bit 0 */ +#define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ +#define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ +#define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /*!< Bit 0 */ +#define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /*!< Bit 1 */ + +/******************* Bit definition for GPIO_CRH register *******************/ +#define GPIO_CRH_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ + +#define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ +#define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + +#define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ +#define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ +#define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +#define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ +#define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ +#define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ +#define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ +#define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ +#define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ + +#define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ +#define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ +#define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +#define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ +#define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /*!< Bit 1 */ + +#define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ +#define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /*!< Bit 0 */ +#define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ +#define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ +#define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /*!< Bit 0 */ +#define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ +#define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ +#define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /*!< Bit 0 */ +#define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /*!< Bit 1 */ + +/*!<****************** Bit definition for GPIO_IDR register *******************/ +#define GPIO_IDR_IDR0 ((uint16_t)0x0001) /*!< Port input data, bit 0 */ +#define GPIO_IDR_IDR1 ((uint16_t)0x0002) /*!< Port input data, bit 1 */ +#define GPIO_IDR_IDR2 ((uint16_t)0x0004) /*!< Port input data, bit 2 */ +#define GPIO_IDR_IDR3 ((uint16_t)0x0008) /*!< Port input data, bit 3 */ +#define GPIO_IDR_IDR4 ((uint16_t)0x0010) /*!< Port input data, bit 4 */ +#define GPIO_IDR_IDR5 ((uint16_t)0x0020) /*!< Port input data, bit 5 */ +#define GPIO_IDR_IDR6 ((uint16_t)0x0040) /*!< Port input data, bit 6 */ +#define GPIO_IDR_IDR7 ((uint16_t)0x0080) /*!< Port input data, bit 7 */ +#define GPIO_IDR_IDR8 ((uint16_t)0x0100) /*!< Port input data, bit 8 */ +#define GPIO_IDR_IDR9 ((uint16_t)0x0200) /*!< Port input data, bit 9 */ +#define GPIO_IDR_IDR10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */ +#define GPIO_IDR_IDR11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */ +#define GPIO_IDR_IDR12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */ +#define GPIO_IDR_IDR13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */ +#define GPIO_IDR_IDR14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */ +#define GPIO_IDR_IDR15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */ + +/******************* Bit definition for GPIO_ODR register *******************/ +#define GPIO_ODR_ODR0 ((uint16_t)0x0001) /*!< Port output data, bit 0 */ +#define GPIO_ODR_ODR1 ((uint16_t)0x0002) /*!< Port output data, bit 1 */ +#define GPIO_ODR_ODR2 ((uint16_t)0x0004) /*!< Port output data, bit 2 */ +#define GPIO_ODR_ODR3 ((uint16_t)0x0008) /*!< Port output data, bit 3 */ +#define GPIO_ODR_ODR4 ((uint16_t)0x0010) /*!< Port output data, bit 4 */ +#define GPIO_ODR_ODR5 ((uint16_t)0x0020) /*!< Port output data, bit 5 */ +#define GPIO_ODR_ODR6 ((uint16_t)0x0040) /*!< Port output data, bit 6 */ +#define GPIO_ODR_ODR7 ((uint16_t)0x0080) /*!< Port output data, bit 7 */ +#define GPIO_ODR_ODR8 ((uint16_t)0x0100) /*!< Port output data, bit 8 */ +#define GPIO_ODR_ODR9 ((uint16_t)0x0200) /*!< Port output data, bit 9 */ +#define GPIO_ODR_ODR10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */ +#define GPIO_ODR_ODR11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */ +#define GPIO_ODR_ODR12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */ +#define GPIO_ODR_ODR13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */ +#define GPIO_ODR_ODR14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */ +#define GPIO_ODR_ODR15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */ + +/****************** Bit definition for GPIO_BSRR register *******************/ +#define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */ +#define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */ +#define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */ +#define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */ +#define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */ +#define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */ +#define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */ +#define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */ +#define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */ +#define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */ +#define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */ +#define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */ +#define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */ +#define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */ +#define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */ +#define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */ + +#define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */ +#define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */ +#define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */ +#define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */ +#define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */ +#define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */ +#define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */ +#define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */ +#define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */ +#define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */ +#define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */ +#define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */ +#define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */ +#define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */ +#define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */ +#define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */ + +/******************* Bit definition for GPIO_BRR register *******************/ +#define GPIO_BRR_BR0 ((uint16_t)0x0001) /*!< Port x Reset bit 0 */ +#define GPIO_BRR_BR1 ((uint16_t)0x0002) /*!< Port x Reset bit 1 */ +#define GPIO_BRR_BR2 ((uint16_t)0x0004) /*!< Port x Reset bit 2 */ +#define GPIO_BRR_BR3 ((uint16_t)0x0008) /*!< Port x Reset bit 3 */ +#define GPIO_BRR_BR4 ((uint16_t)0x0010) /*!< Port x Reset bit 4 */ +#define GPIO_BRR_BR5 ((uint16_t)0x0020) /*!< Port x Reset bit 5 */ +#define GPIO_BRR_BR6 ((uint16_t)0x0040) /*!< Port x Reset bit 6 */ +#define GPIO_BRR_BR7 ((uint16_t)0x0080) /*!< Port x Reset bit 7 */ +#define GPIO_BRR_BR8 ((uint16_t)0x0100) /*!< Port x Reset bit 8 */ +#define GPIO_BRR_BR9 ((uint16_t)0x0200) /*!< Port x Reset bit 9 */ +#define GPIO_BRR_BR10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */ +#define GPIO_BRR_BR11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */ +#define GPIO_BRR_BR12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */ +#define GPIO_BRR_BR13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */ +#define GPIO_BRR_BR14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */ +#define GPIO_BRR_BR15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */ + +/****************** Bit definition for GPIO_LCKR register *******************/ +#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */ +#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */ +#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */ +#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */ +#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */ +#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */ +#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */ +#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */ +#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */ +#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */ +#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */ +#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */ +#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */ +#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */ +#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */ +#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */ +#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /*!< Lock key */ + +/*----------------------------------------------------------------------------*/ + +/****************** Bit definition for AFIO_EVCR register *******************/ +#define AFIO_EVCR_PIN ((uint8_t)0x0F) /*!< PIN[3:0] bits (Pin selection) */ +#define AFIO_EVCR_PIN_0 ((uint8_t)0x01) /*!< Bit 0 */ +#define AFIO_EVCR_PIN_1 ((uint8_t)0x02) /*!< Bit 1 */ +#define AFIO_EVCR_PIN_2 ((uint8_t)0x04) /*!< Bit 2 */ +#define AFIO_EVCR_PIN_3 ((uint8_t)0x08) /*!< Bit 3 */ + +/*!< PIN configuration */ +#define AFIO_EVCR_PIN_PX0 ((uint8_t)0x00) /*!< Pin 0 selected */ +#define AFIO_EVCR_PIN_PX1 ((uint8_t)0x01) /*!< Pin 1 selected */ +#define AFIO_EVCR_PIN_PX2 ((uint8_t)0x02) /*!< Pin 2 selected */ +#define AFIO_EVCR_PIN_PX3 ((uint8_t)0x03) /*!< Pin 3 selected */ +#define AFIO_EVCR_PIN_PX4 ((uint8_t)0x04) /*!< Pin 4 selected */ +#define AFIO_EVCR_PIN_PX5 ((uint8_t)0x05) /*!< Pin 5 selected */ +#define AFIO_EVCR_PIN_PX6 ((uint8_t)0x06) /*!< Pin 6 selected */ +#define AFIO_EVCR_PIN_PX7 ((uint8_t)0x07) /*!< Pin 7 selected */ +#define AFIO_EVCR_PIN_PX8 ((uint8_t)0x08) /*!< Pin 8 selected */ +#define AFIO_EVCR_PIN_PX9 ((uint8_t)0x09) /*!< Pin 9 selected */ +#define AFIO_EVCR_PIN_PX10 ((uint8_t)0x0A) /*!< Pin 10 selected */ +#define AFIO_EVCR_PIN_PX11 ((uint8_t)0x0B) /*!< Pin 11 selected */ +#define AFIO_EVCR_PIN_PX12 ((uint8_t)0x0C) /*!< Pin 12 selected */ +#define AFIO_EVCR_PIN_PX13 ((uint8_t)0x0D) /*!< Pin 13 selected */ +#define AFIO_EVCR_PIN_PX14 ((uint8_t)0x0E) /*!< Pin 14 selected */ +#define AFIO_EVCR_PIN_PX15 ((uint8_t)0x0F) /*!< Pin 15 selected */ + +#define AFIO_EVCR_PORT ((uint8_t)0x70) /*!< PORT[2:0] bits (Port selection) */ +#define AFIO_EVCR_PORT_0 ((uint8_t)0x10) /*!< Bit 0 */ +#define AFIO_EVCR_PORT_1 ((uint8_t)0x20) /*!< Bit 1 */ +#define AFIO_EVCR_PORT_2 ((uint8_t)0x40) /*!< Bit 2 */ + +/*!< PORT configuration */ +#define AFIO_EVCR_PORT_PA ((uint8_t)0x00) /*!< Port A selected */ +#define AFIO_EVCR_PORT_PB ((uint8_t)0x10) /*!< Port B selected */ +#define AFIO_EVCR_PORT_PC ((uint8_t)0x20) /*!< Port C selected */ +#define AFIO_EVCR_PORT_PD ((uint8_t)0x30) /*!< Port D selected */ +#define AFIO_EVCR_PORT_PE ((uint8_t)0x40) /*!< Port E selected */ + +#define AFIO_EVCR_EVOE ((uint8_t)0x80) /*!< Event Output Enable */ + +/****************** Bit definition for AFIO_MAPR register *******************/ +#define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /*!< SPI1 remapping */ +#define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /*!< I2C1 remapping */ +#define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /*!< USART1 remapping */ +#define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /*!< USART2 remapping */ + +#define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /*!< USART3_REMAP[1:0] bits (USART3 remapping) */ +#define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +/* USART3_REMAP configuration */ +#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ +#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ +#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ + +#define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ +#define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +/*!< TIM1_REMAP configuration */ +#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ +#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ +#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ + +#define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ +#define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +/*!< TIM2_REMAP configuration */ +#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ +#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ + +#define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ +#define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /*!< Bit 1 */ + +/*!< TIM3_REMAP configuration */ +#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ +#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ +#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ + +#define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /*!< TIM4_REMAP bit (TIM4 remapping) */ + +#define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ +#define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) /*!< Bit 1 */ + +/*!< CAN_REMAP configuration */ +#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */ +#define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /*!< CANRX mapped to PB8, CANTX mapped to PB9 */ +#define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /*!< CANRX mapped to PD0, CANTX mapped to PD1 */ + +#define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ +#define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) /*!< TIM5 Channel4 Internal Remap */ +#define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /*!< ADC 1 External Trigger Injected Conversion remapping */ +#define AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /*!< ADC 1 External Trigger Regular Conversion remapping */ +#define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /*!< ADC 2 External Trigger Injected Conversion remapping */ +#define AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /*!< ADC 2 External Trigger Regular Conversion remapping */ + +/*!< SWJ_CFG configuration */ +#define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ +#define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + +#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ +#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ +#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /*!< JTAG-DP Disabled and SW-DP Enabled */ +#define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /*!< JTAG-DP Disabled and SW-DP Disabled */ + +#ifdef STM32F10X_CL +/*!< ETH_REMAP configuration */ + #define AFIO_MAPR_ETH_REMAP ((uint32_t)0x00200000) /*!< SPI3_REMAP bit (Ethernet MAC I/O remapping) */ + +/*!< CAN2_REMAP configuration */ + #define AFIO_MAPR_CAN2_REMAP ((uint32_t)0x00400000) /*!< CAN2_REMAP bit (CAN2 I/O remapping) */ + +/*!< MII_RMII_SEL configuration */ + #define AFIO_MAPR_MII_RMII_SEL ((uint32_t)0x00800000) /*!< MII_RMII_SEL bit (Ethernet MII or RMII selection) */ + +/*!< SPI3_REMAP configuration */ + #define AFIO_MAPR_SPI3_REMAP ((uint32_t)0x10000000) /*!< SPI3_REMAP bit (SPI3 remapping) */ + +/*!< TIM2ITR1_IREMAP configuration */ + #define AFIO_MAPR_TIM2ITR1_IREMAP ((uint32_t)0x20000000) /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */ + +/*!< PTP_PPS_REMAP configuration */ + #define AFIO_MAPR_PTP_PPS_REMAP ((uint32_t)0x40000000) /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */ +#endif + +/***************** Bit definition for AFIO_EXTICR1 register *****************/ +#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */ +#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */ +#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */ +#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */ + +/*!< EXTI0 configuration */ +#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */ +#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */ +#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */ +#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */ +#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */ +#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */ +#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!< PG[0] pin */ + +/*!< EXTI1 configuration */ +#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */ +#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */ +#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */ +#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */ +#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */ +#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */ +#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!< PG[1] pin */ + +/*!< EXTI2 configuration */ +#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */ +#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */ +#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */ +#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */ +#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */ +#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */ +#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!< PG[2] pin */ + +/*!< EXTI3 configuration */ +#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */ +#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */ +#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */ +#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */ +#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */ +#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */ +#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!< PG[3] pin */ + +/***************** Bit definition for AFIO_EXTICR2 register *****************/ +#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */ +#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */ +#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */ +#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */ + +/*!< EXTI4 configuration */ +#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */ +#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */ +#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */ +#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */ +#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */ +#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */ +#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!< PG[4] pin */ + +/* EXTI5 configuration */ +#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */ +#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */ +#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */ +#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */ +#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */ +#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */ +#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!< PG[5] pin */ + +/*!< EXTI6 configuration */ +#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */ +#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */ +#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */ +#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */ +#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */ +#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */ +#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!< PG[6] pin */ + +/*!< EXTI7 configuration */ +#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */ +#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */ +#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */ +#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */ +#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */ +#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */ +#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!< PG[7] pin */ + +/***************** Bit definition for AFIO_EXTICR3 register *****************/ +#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */ +#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */ +#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */ +#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */ + +/*!< EXTI8 configuration */ +#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */ +#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */ +#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */ +#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */ +#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */ +#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */ +#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!< PG[8] pin */ + +/*!< EXTI9 configuration */ +#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */ +#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */ +#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */ +#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */ +#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */ +#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */ +#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!< PG[9] pin */ + +/*!< EXTI10 configuration */ +#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */ +#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */ +#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */ +#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */ +#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */ +#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */ +#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!< PG[10] pin */ + +/*!< EXTI11 configuration */ +#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */ +#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */ +#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */ +#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */ +#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */ +#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */ +#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!< PG[11] pin */ + +/***************** Bit definition for AFIO_EXTICR4 register *****************/ +#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */ +#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */ +#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */ +#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */ + +/* EXTI12 configuration */ +#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */ +#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */ +#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */ +#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */ +#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */ +#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */ +#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!< PG[12] pin */ + +/* EXTI13 configuration */ +#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */ +#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */ +#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */ +#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */ +#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */ +#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */ +#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!< PG[13] pin */ + +/*!< EXTI14 configuration */ +#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */ +#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */ +#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */ +#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */ +#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */ +#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */ +#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!< PG[14] pin */ + +/*!< EXTI15 configuration */ +#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */ +#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */ +#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */ +#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */ +#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */ +#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */ +#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!< PG[15] pin */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) +/****************** Bit definition for AFIO_MAPR2 register ******************/ +#define AFIO_MAPR2_TIM15_REMAP ((uint32_t)0x00000001) /*!< TIM15 remapping */ +#define AFIO_MAPR2_TIM16_REMAP ((uint32_t)0x00000002) /*!< TIM16 remapping */ +#define AFIO_MAPR2_TIM17_REMAP ((uint32_t)0x00000004) /*!< TIM17 remapping */ +#define AFIO_MAPR2_CEC_REMAP ((uint32_t)0x00000008) /*!< CEC remapping */ +#define AFIO_MAPR2_TIM1_DMA_REMAP ((uint32_t)0x00000010) /*!< TIM1_DMA remapping */ +#endif + +#ifdef STM32F10X_HD_VL +#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */ +#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */ +#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */ +#define AFIO_MAPR2_TIM67_DAC_DMA_REMAP ((uint32_t)0x00000800) /*!< TIM6/TIM7 and DAC DMA remapping */ +#define AFIO_MAPR2_TIM12_REMAP ((uint32_t)0x00001000) /*!< TIM12 remapping */ +#define AFIO_MAPR2_MISC_REMAP ((uint32_t)0x00002000) /*!< Miscellaneous remapping */ +#endif + +#ifdef STM32F10X_XL +/****************** Bit definition for AFIO_MAPR2 register ******************/ +#define AFIO_MAPR2_TIM9_REMAP ((uint32_t)0x00000020) /*!< TIM9 remapping */ +#define AFIO_MAPR2_TIM10_REMAP ((uint32_t)0x00000040) /*!< TIM10 remapping */ +#define AFIO_MAPR2_TIM11_REMAP ((uint32_t)0x00000080) /*!< TIM11 remapping */ +#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */ +#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */ +#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */ +#endif + +/******************************************************************************/ +/* */ +/* SystemTick */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for SysTick_CTRL register *****************/ +#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */ +#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */ +#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */ +#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */ + +/***************** Bit definition for SysTick_LOAD register *****************/ +#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ + +/***************** Bit definition for SysTick_VAL register ******************/ +#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */ + +/***************** Bit definition for SysTick_CALIB register ****************/ +#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */ +#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */ +#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */ + +/******************************************************************************/ +/* */ +/* Nested Vectored Interrupt Controller */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for NVIC_ISER register *******************/ +#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */ +#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_ICER register *******************/ +#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */ +#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_ISPR register *******************/ +#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */ +#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_ICPR register *******************/ +#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */ +#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_IABR register *******************/ +#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */ +#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_PRI0 register *******************/ +#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */ +#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */ +#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */ +#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */ + +/****************** Bit definition for NVIC_PRI1 register *******************/ +#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */ +#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */ +#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */ +#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */ + +/****************** Bit definition for NVIC_PRI2 register *******************/ +#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */ +#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */ +#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */ +#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */ + +/****************** Bit definition for NVIC_PRI3 register *******************/ +#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */ +#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */ +#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */ +#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */ + +/****************** Bit definition for NVIC_PRI4 register *******************/ +#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */ +#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */ +#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */ +#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */ + +/****************** Bit definition for NVIC_PRI5 register *******************/ +#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */ +#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */ +#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */ +#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */ + +/****************** Bit definition for NVIC_PRI6 register *******************/ +#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */ +#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */ +#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */ +#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */ + +/****************** Bit definition for NVIC_PRI7 register *******************/ +#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */ +#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */ +#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */ +#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */ + +/****************** Bit definition for SCB_CPUID register *******************/ +#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */ +#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */ +#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */ +#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */ +#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */ + +/******************* Bit definition for SCB_ICSR register *******************/ +#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */ +#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ +#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */ +#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */ +#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ +#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */ +#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */ +#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */ +#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */ +#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */ + +/******************* Bit definition for SCB_VTOR register *******************/ +#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */ +#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */ + +/*!<***************** Bit definition for SCB_AIRCR register *******************/ +#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */ +#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */ +#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */ + +#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */ +#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */ + +/* prority group configuration */ +#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ +#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ + +#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */ +#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ + +/******************* Bit definition for SCB_SCR register ********************/ +#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */ +#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */ +#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */ + +/******************** Bit definition for SCB_CCR register *******************/ +#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ +#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ +#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */ +#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */ +#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */ +#define SCB_CCR_STKALIGN ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ + +/******************* Bit definition for SCB_SHPR register ********************/ +#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ +#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ +#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ +#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ + +/****************** Bit definition for SCB_SHCSR register *******************/ +#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */ +#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */ +#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */ +#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */ +#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */ +#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */ +#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */ +#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */ +#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */ +#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */ +#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */ +#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */ +#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */ +#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */ + +/******************* Bit definition for SCB_CFSR register *******************/ +/*!< MFSR */ +#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */ +#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */ +#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */ +#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */ +#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */ +/*!< BFSR */ +#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */ +#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */ +#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */ +#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */ +#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */ +#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */ +/*!< UFSR */ +#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to execute an undefined instruction */ +#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */ +#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */ +#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */ +#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */ +#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ + +/******************* Bit definition for SCB_HFSR register *******************/ +#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */ +#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ +#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */ + +/******************* Bit definition for SCB_DFSR register *******************/ +#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */ +#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */ +#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */ +#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */ +#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */ + +/******************* Bit definition for SCB_MMFAR register ******************/ +#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */ + +/******************* Bit definition for SCB_BFAR register *******************/ +#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */ + +/******************* Bit definition for SCB_afsr register *******************/ +#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */ + +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for EXTI_IMR register *******************/ +#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */ +#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */ +#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */ +#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */ +#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */ +#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */ +#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */ +#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */ +#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */ +#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */ +#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */ +#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */ +#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */ +#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */ +#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */ +#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */ +#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */ +#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ +#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ +#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ + +/******************* Bit definition for EXTI_EMR register *******************/ +#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ +#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */ +#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */ +#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */ +#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */ +#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */ +#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */ +#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */ +#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */ +#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */ +#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */ +#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */ +#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */ +#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */ +#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */ +#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */ +#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */ +#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ +#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ +#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ + +/****************** Bit definition for EXTI_RTSR register *******************/ +#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ +#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */ +#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */ +#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */ +#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */ +#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */ +#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */ +#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */ +#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */ +#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */ +#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */ +#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */ +#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */ +#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */ +#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */ +#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */ +#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */ +#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ +#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ +#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ + +/****************** Bit definition for EXTI_FTSR register *******************/ +#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ +#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */ +#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */ +#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */ +#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */ +#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */ +#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */ +#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */ +#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */ +#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */ +#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */ +#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */ +#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */ +#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */ +#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */ +#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */ +#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */ +#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ +#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ +#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ + +/****************** Bit definition for EXTI_SWIER register ******************/ +#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */ +#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */ +#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ +#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ +#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ + +/******************* Bit definition for EXTI_PR register ********************/ +#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */ +#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */ +#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */ +#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */ +#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */ +#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */ +#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */ +#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */ +#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */ +#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */ +#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */ +#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */ +#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */ +#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */ +#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */ +#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */ +#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */ +#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */ +#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */ +#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */ + +/******************************************************************************/ +/* */ +/* DMA Controller */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_ISR register ********************/ +#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */ +#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */ +#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */ +#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */ +#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */ +#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */ +#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */ +#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */ +#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */ +#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */ +#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */ +#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */ +#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */ +#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */ +#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */ +#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */ +#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */ +#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */ +#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */ +#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */ +#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */ +#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */ +#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */ +#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */ +#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */ +#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */ +#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */ +#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */ + +/******************* Bit definition for DMA_IFCR register *******************/ +#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */ +#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */ +#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */ +#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */ +#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */ +#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */ +#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */ +#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */ +#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */ +#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */ +#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */ +#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */ +#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */ +#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */ +#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */ +#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */ +#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */ +#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */ +#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */ +#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */ +#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */ +#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */ +#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */ +#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */ +#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */ +#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */ +#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */ +#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */ + +/******************* Bit definition for DMA_CCR1 register *******************/ +#define DMA_CCR1_EN ((uint16_t)0x0001) /*!< Channel enable*/ +#define DMA_CCR1_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR1_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR1_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR1_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR1_PL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */ +#define DMA_CCR1_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR1_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/******************* Bit definition for DMA_CCR2 register *******************/ +#define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR2_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR2_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR2_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR2_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/******************* Bit definition for DMA_CCR3 register *******************/ +#define DMA_CCR3_EN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CCR3_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR3_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR3_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR3_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR3_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR3_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR3_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/*!<****************** Bit definition for DMA_CCR4 register *******************/ +#define DMA_CCR4_EN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CCR4_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR4_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR4_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR4_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR4_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR4_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR4_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR4_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR4_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR4_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR4_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR4_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR4_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR4_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR4_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR4_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR4_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/****************** Bit definition for DMA_CCR5 register *******************/ +#define DMA_CCR5_EN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CCR5_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR5_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR5_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR5_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR5_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR5_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR5_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR5_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR5_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR5_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR5_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR5_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR5_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR5_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR5_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR5_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR5_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */ + +/******************* Bit definition for DMA_CCR6 register *******************/ +#define DMA_CCR6_EN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CCR6_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR6_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR6_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR6_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR6_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR6_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR6_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR6_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR6_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR6_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR6_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR6_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR6_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR6_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR6_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR6_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR6_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/******************* Bit definition for DMA_CCR7 register *******************/ +#define DMA_CCR7_EN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CCR7_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR7_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR7_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR7_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR7_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR7_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR7_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR7_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR7_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR7_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR7_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR7_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR7_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR7_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR7_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */ + +/****************** Bit definition for DMA_CNDTR1 register ******************/ +#define DMA_CNDTR1_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CNDTR2 register ******************/ +#define DMA_CNDTR2_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CNDTR3 register ******************/ +#define DMA_CNDTR3_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CNDTR4 register ******************/ +#define DMA_CNDTR4_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CNDTR5 register ******************/ +#define DMA_CNDTR5_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CNDTR6 register ******************/ +#define DMA_CNDTR6_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CNDTR7 register ******************/ +#define DMA_CNDTR7_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CPAR1 register *******************/ +#define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CPAR2 register *******************/ +#define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CPAR3 register *******************/ +#define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + + +/****************** Bit definition for DMA_CPAR4 register *******************/ +#define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CPAR5 register *******************/ +#define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CPAR6 register *******************/ +#define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + + +/****************** Bit definition for DMA_CPAR7 register *******************/ +#define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CMAR1 register *******************/ +#define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/****************** Bit definition for DMA_CMAR2 register *******************/ +#define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/****************** Bit definition for DMA_CMAR3 register *******************/ +#define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + + +/****************** Bit definition for DMA_CMAR4 register *******************/ +#define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/****************** Bit definition for DMA_CMAR5 register *******************/ +#define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/****************** Bit definition for DMA_CMAR6 register *******************/ +#define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/****************** Bit definition for DMA_CMAR7 register *******************/ +#define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for ADC_SR register ********************/ +#define ADC_SR_AWD ((uint8_t)0x01) /*!< Analog watchdog flag */ +#define ADC_SR_EOC ((uint8_t)0x02) /*!< End of conversion */ +#define ADC_SR_JEOC ((uint8_t)0x04) /*!< Injected channel end of conversion */ +#define ADC_SR_JSTRT ((uint8_t)0x08) /*!< Injected channel Start flag */ +#define ADC_SR_STRT ((uint8_t)0x10) /*!< Regular channel Start flag */ + +/******************* Bit definition for ADC_CR1 register ********************/ +#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */ +#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */ +#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */ +#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */ +#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */ +#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */ +#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */ +#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */ +#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */ + +#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */ +#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */ +#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */ + +#define ADC_CR1_DUALMOD ((uint32_t)0x000F0000) /*!< DUALMOD[3:0] bits (Dual mode selection) */ +#define ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) /*!< Bit 3 */ + +#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */ +#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */ + + +/******************* Bit definition for ADC_CR2 register ********************/ +#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */ +#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */ +#define ADC_CR2_CAL ((uint32_t)0x00000004) /*!< A/D Calibration */ +#define ADC_CR2_RSTCAL ((uint32_t)0x00000008) /*!< Reset Calibration */ +#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */ +#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */ + +#define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) /*!< JEXTSEL[2:0] bits (External event select for injected group) */ +#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + +#define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) /*!< External Trigger Conversion mode for injected channels */ + +#define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */ +#define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) /*!< Bit 0 */ +#define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) /*!< Bit 1 */ +#define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) /*!< Bit 2 */ + +#define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) /*!< External Trigger Conversion mode for regular channels */ +#define ADC_CR2_JSWSTART ((uint32_t)0x00200000) /*!< Start Conversion of injected channels */ +#define ADC_CR2_SWSTART ((uint32_t)0x00400000) /*!< Start Conversion of regular channels */ +#define ADC_CR2_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */ + +/****************** Bit definition for ADC_SMPR1 register *******************/ +#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */ +#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */ +#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */ +#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */ +#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */ +#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */ +#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 15 Sample time selection) */ +#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */ +#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */ +#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */ + +/****************** Bit definition for ADC_SMPR2 register *******************/ +#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */ +#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */ +#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */ +#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */ +#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */ +#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */ +#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */ +#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */ +#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */ +#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */ +#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */ +#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */ + +/****************** Bit definition for ADC_JOFR1 register *******************/ +#define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 1 */ + +/****************** Bit definition for ADC_JOFR2 register *******************/ +#define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 2 */ + +/****************** Bit definition for ADC_JOFR3 register *******************/ +#define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 3 */ + +/****************** Bit definition for ADC_JOFR4 register *******************/ +#define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /*!< Data offset for injected channel 4 */ + +/******************* Bit definition for ADC_HTR register ********************/ +#define ADC_HTR_HT ((uint16_t)0x0FFF) /*!< Analog watchdog high threshold */ + +/******************* Bit definition for ADC_LTR register ********************/ +#define ADC_LTR_LT ((uint16_t)0x0FFF) /*!< Analog watchdog low threshold */ + +/******************* Bit definition for ADC_SQR1 register *******************/ +#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */ +#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */ +#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */ +#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */ +#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */ +#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +/******************* Bit definition for ADC_SQR2 register *******************/ +#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */ +#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */ +#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */ +#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */ +#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */ +#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */ +#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */ + +#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */ +#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */ +#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */ +#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */ +#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */ + +/******************* Bit definition for ADC_SQR3 register *******************/ +#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */ +#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */ +#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */ +#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */ +#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */ +#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */ +#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */ + +#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */ +#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */ +#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */ +#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */ +#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */ + +/******************* Bit definition for ADC_JSQR register *******************/ +#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */ +#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */ +#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */ +#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */ +#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */ +#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */ + +/******************* Bit definition for ADC_JDR1 register *******************/ +#define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ + +/******************* Bit definition for ADC_JDR2 register *******************/ +#define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ + +/******************* Bit definition for ADC_JDR3 register *******************/ +#define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ + +/******************* Bit definition for ADC_JDR4 register *******************/ +#define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /*!< Injected data */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */ +#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!< ADC2 data */ + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */ +#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */ +#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */ + +#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */ +#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ +#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ +#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + +#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */ +#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */ +#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */ +#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */ + +#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */ +#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */ +#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */ +#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */ + +#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ +#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */ +#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */ + +#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ +#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + #define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun interrupt enable */ + #define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun interrupt enable */ +#endif + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!< DAC channel1 software trigger */ +#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!< DAC channel2 software trigger */ + +/***************** Bit definition for DAC_DHR12R1 register ******************/ +#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!< DAC channel1 12-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12L1 register ******************/ +#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!< DAC channel1 12-bit Left aligned data */ + +/****************** Bit definition for DAC_DHR8R1 register ******************/ +#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!< DAC channel1 8-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12R2 register ******************/ +#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!< DAC channel2 12-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12L2 register ******************/ +#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!< DAC channel2 12-bit Left aligned data */ + +/****************** Bit definition for DAC_DHR8R2 register ******************/ +#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!< DAC channel2 8-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12RD register ******************/ +#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */ +#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */ + +/***************** Bit definition for DAC_DHR12LD register ******************/ +#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */ +#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */ + +/****************** Bit definition for DAC_DHR8RD register ******************/ +#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!< DAC channel1 8-bit Right aligned data */ +#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!< DAC channel2 8-bit Right aligned data */ + +/******************* Bit definition for DAC_DOR1 register *******************/ +#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!< DAC channel1 data output */ + +/******************* Bit definition for DAC_DOR2 register *******************/ +#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!< DAC channel2 data output */ + +/******************** Bit definition for DAC_SR register ********************/ +#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */ +#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */ + +/******************************************************************************/ +/* */ +/* CEC */ +/* */ +/******************************************************************************/ +/******************** Bit definition for CEC_CFGR register ******************/ +#define CEC_CFGR_PE ((uint16_t)0x0001) /*!< Peripheral Enable */ +#define CEC_CFGR_IE ((uint16_t)0x0002) /*!< Interrupt Enable */ +#define CEC_CFGR_BTEM ((uint16_t)0x0004) /*!< Bit Timing Error Mode */ +#define CEC_CFGR_BPEM ((uint16_t)0x0008) /*!< Bit Period Error Mode */ + +/******************** Bit definition for CEC_OAR register ******************/ +#define CEC_OAR_OA ((uint16_t)0x000F) /*!< OA[3:0]: Own Address */ +#define CEC_OAR_OA_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define CEC_OAR_OA_1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define CEC_OAR_OA_2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define CEC_OAR_OA_3 ((uint16_t)0x0008) /*!< Bit 3 */ + +/******************** Bit definition for CEC_PRES register ******************/ +#define CEC_PRES_PRES ((uint16_t)0x3FFF) /*!< Prescaler Counter Value */ + +/******************** Bit definition for CEC_ESR register ******************/ +#define CEC_ESR_BTE ((uint16_t)0x0001) /*!< Bit Timing Error */ +#define CEC_ESR_BPE ((uint16_t)0x0002) /*!< Bit Period Error */ +#define CEC_ESR_RBTFE ((uint16_t)0x0004) /*!< Rx Block Transfer Finished Error */ +#define CEC_ESR_SBE ((uint16_t)0x0008) /*!< Start Bit Error */ +#define CEC_ESR_ACKE ((uint16_t)0x0010) /*!< Block Acknowledge Error */ +#define CEC_ESR_LINE ((uint16_t)0x0020) /*!< Line Error */ +#define CEC_ESR_TBTFE ((uint16_t)0x0040) /*!< Tx Block Transfer Finished Error */ + +/******************** Bit definition for CEC_CSR register ******************/ +#define CEC_CSR_TSOM ((uint16_t)0x0001) /*!< Tx Start Of Message */ +#define CEC_CSR_TEOM ((uint16_t)0x0002) /*!< Tx End Of Message */ +#define CEC_CSR_TERR ((uint16_t)0x0004) /*!< Tx Error */ +#define CEC_CSR_TBTRF ((uint16_t)0x0008) /*!< Tx Byte Transfer Request or Block Transfer Finished */ +#define CEC_CSR_RSOM ((uint16_t)0x0010) /*!< Rx Start Of Message */ +#define CEC_CSR_REOM ((uint16_t)0x0020) /*!< Rx End Of Message */ +#define CEC_CSR_RERR ((uint16_t)0x0040) /*!< Rx Error */ +#define CEC_CSR_RBTF ((uint16_t)0x0080) /*!< Rx Block Transfer Finished */ + +/******************** Bit definition for CEC_TXD register ******************/ +#define CEC_TXD_TXD ((uint16_t)0x00FF) /*!< Tx Data register */ + +/******************** Bit definition for CEC_RXD register ******************/ +#define CEC_RXD_RXD ((uint16_t)0x00FF) /*!< Rx Data register */ + +/******************************************************************************/ +/* */ +/* TIM */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for TIM_CR1 register ********************/ +#define TIM_CR1_CEN ((uint16_t)0x0001) /*!< Counter enable */ +#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!< Update disable */ +#define TIM_CR1_URS ((uint16_t)0x0004) /*!< Update request source */ +#define TIM_CR1_OPM ((uint16_t)0x0008) /*!< One pulse mode */ +#define TIM_CR1_DIR ((uint16_t)0x0010) /*!< Direction */ + +#define TIM_CR1_CMS ((uint16_t)0x0060) /*!< CMS[1:0] bits (Center-aligned mode selection) */ +#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!< Bit 0 */ +#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!< Bit 1 */ + +#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!< Auto-reload preload enable */ + +#define TIM_CR1_CKD ((uint16_t)0x0300) /*!< CKD[1:0] bits (clock division) */ +#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +/******************* Bit definition for TIM_CR2 register ********************/ +#define TIM_CR2_CCPC ((uint16_t)0x0001) /*!< Capture/Compare Preloaded Control */ +#define TIM_CR2_CCUS ((uint16_t)0x0004) /*!< Capture/Compare Control Update Selection */ +#define TIM_CR2_CCDS ((uint16_t)0x0008) /*!< Capture/Compare DMA Selection */ + +#define TIM_CR2_MMS ((uint16_t)0x0070) /*!< MMS[2:0] bits (Master Mode Selection) */ +#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!< Bit 2 */ + +#define TIM_CR2_TI1S ((uint16_t)0x0080) /*!< TI1 Selection */ +#define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!< Output Idle state 1 (OC1 output) */ +#define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!< Output Idle state 1 (OC1N output) */ +#define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!< Output Idle state 2 (OC2 output) */ +#define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!< Output Idle state 2 (OC2N output) */ +#define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!< Output Idle state 3 (OC3 output) */ +#define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!< Output Idle state 3 (OC3N output) */ +#define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!< Output Idle state 4 (OC4 output) */ + +/******************* Bit definition for TIM_SMCR register *******************/ +#define TIM_SMCR_SMS ((uint16_t)0x0007) /*!< SMS[2:0] bits (Slave mode selection) */ +#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!< Bit 2 */ + +#define TIM_SMCR_TS ((uint16_t)0x0070) /*!< TS[2:0] bits (Trigger selection) */ +#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!< Bit 2 */ + +#define TIM_SMCR_MSM ((uint16_t)0x0080) /*!< Master/slave mode */ + +#define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!< ETF[3:0] bits (External trigger filter) */ +#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!< Bit 1 */ +#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!< Bit 2 */ +#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!< Bit 3 */ + +#define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!< ETPS[1:0] bits (External trigger prescaler) */ +#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define TIM_SMCR_ECE ((uint16_t)0x4000) /*!< External clock enable */ +#define TIM_SMCR_ETP ((uint16_t)0x8000) /*!< External trigger polarity */ + +/******************* Bit definition for TIM_DIER register *******************/ +#define TIM_DIER_UIE ((uint16_t)0x0001) /*!< Update interrupt enable */ +#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!< Capture/Compare 1 interrupt enable */ +#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!< Capture/Compare 2 interrupt enable */ +#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!< Capture/Compare 3 interrupt enable */ +#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!< Capture/Compare 4 interrupt enable */ +#define TIM_DIER_COMIE ((uint16_t)0x0020) /*!< COM interrupt enable */ +#define TIM_DIER_TIE ((uint16_t)0x0040) /*!< Trigger interrupt enable */ +#define TIM_DIER_BIE ((uint16_t)0x0080) /*!< Break interrupt enable */ +#define TIM_DIER_UDE ((uint16_t)0x0100) /*!< Update DMA request enable */ +#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!< Capture/Compare 1 DMA request enable */ +#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!< Capture/Compare 2 DMA request enable */ +#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!< Capture/Compare 3 DMA request enable */ +#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!< Capture/Compare 4 DMA request enable */ +#define TIM_DIER_COMDE ((uint16_t)0x2000) /*!< COM DMA request enable */ +#define TIM_DIER_TDE ((uint16_t)0x4000) /*!< Trigger DMA request enable */ + +/******************** Bit definition for TIM_SR register ********************/ +#define TIM_SR_UIF ((uint16_t)0x0001) /*!< Update interrupt Flag */ +#define TIM_SR_CC1IF ((uint16_t)0x0002) /*!< Capture/Compare 1 interrupt Flag */ +#define TIM_SR_CC2IF ((uint16_t)0x0004) /*!< Capture/Compare 2 interrupt Flag */ +#define TIM_SR_CC3IF ((uint16_t)0x0008) /*!< Capture/Compare 3 interrupt Flag */ +#define TIM_SR_CC4IF ((uint16_t)0x0010) /*!< Capture/Compare 4 interrupt Flag */ +#define TIM_SR_COMIF ((uint16_t)0x0020) /*!< COM interrupt Flag */ +#define TIM_SR_TIF ((uint16_t)0x0040) /*!< Trigger interrupt Flag */ +#define TIM_SR_BIF ((uint16_t)0x0080) /*!< Break interrupt Flag */ +#define TIM_SR_CC1OF ((uint16_t)0x0200) /*!< Capture/Compare 1 Overcapture Flag */ +#define TIM_SR_CC2OF ((uint16_t)0x0400) /*!< Capture/Compare 2 Overcapture Flag */ +#define TIM_SR_CC3OF ((uint16_t)0x0800) /*!< Capture/Compare 3 Overcapture Flag */ +#define TIM_SR_CC4OF ((uint16_t)0x1000) /*!< Capture/Compare 4 Overcapture Flag */ + +/******************* Bit definition for TIM_EGR register ********************/ +#define TIM_EGR_UG ((uint8_t)0x01) /*!< Update Generation */ +#define TIM_EGR_CC1G ((uint8_t)0x02) /*!< Capture/Compare 1 Generation */ +#define TIM_EGR_CC2G ((uint8_t)0x04) /*!< Capture/Compare 2 Generation */ +#define TIM_EGR_CC3G ((uint8_t)0x08) /*!< Capture/Compare 3 Generation */ +#define TIM_EGR_CC4G ((uint8_t)0x10) /*!< Capture/Compare 4 Generation */ +#define TIM_EGR_COMG ((uint8_t)0x20) /*!< Capture/Compare Control Update Generation */ +#define TIM_EGR_TG ((uint8_t)0x40) /*!< Trigger Generation */ +#define TIM_EGR_BG ((uint8_t)0x80) /*!< Break Generation */ + +/****************** Bit definition for TIM_CCMR1 register *******************/ +#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!< CC1S[1:0] bits (Capture/Compare 1 Selection) */ +#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!< Bit 1 */ + +#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!< Output Compare 1 Fast enable */ +#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!< Output Compare 1 Preload enable */ + +#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!< OC1M[2:0] bits (Output Compare 1 Mode) */ +#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!< Bit 2 */ + +#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!< Output Compare 1Clear Enable */ + +#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!< CC2S[1:0] bits (Capture/Compare 2 Selection) */ +#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!< Output Compare 2 Fast enable */ +#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!< Output Compare 2 Preload enable */ + +#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!< OC2M[2:0] bits (Output Compare 2 Mode) */ +#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!< Bit 1 */ +#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!< Bit 2 */ + +#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!< Output Compare 2 Clear Enable */ + +/*----------------------------------------------------------------------------*/ + +#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!< IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ +#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */ +#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */ + +#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!< IC1F[3:0] bits (Input Capture 1 Filter) */ +#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!< Bit 2 */ +#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!< Bit 3 */ + +#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!< IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ +#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!< IC2F[3:0] bits (Input Capture 2 Filter) */ +#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!< Bit 1 */ +#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!< Bit 2 */ +#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!< Bit 3 */ + +/****************** Bit definition for TIM_CCMR2 register *******************/ +#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!< CC3S[1:0] bits (Capture/Compare 3 Selection) */ +#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!< Bit 1 */ + +#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!< Output Compare 3 Fast enable */ +#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!< Output Compare 3 Preload enable */ + +#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!< OC3M[2:0] bits (Output Compare 3 Mode) */ +#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!< Bit 2 */ + +#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!< Output Compare 3 Clear Enable */ + +#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!< CC4S[1:0] bits (Capture/Compare 4 Selection) */ +#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!< Output Compare 4 Fast enable */ +#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!< Output Compare 4 Preload enable */ + +#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!< OC4M[2:0] bits (Output Compare 4 Mode) */ +#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!< Bit 1 */ +#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!< Bit 2 */ + +#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!< Output Compare 4 Clear Enable */ + +/*----------------------------------------------------------------------------*/ + +#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!< IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ +#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!< Bit 0 */ +#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!< Bit 1 */ + +#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!< IC3F[3:0] bits (Input Capture 3 Filter) */ +#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!< Bit 2 */ +#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!< Bit 3 */ + +#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!< IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ +#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!< IC4F[3:0] bits (Input Capture 4 Filter) */ +#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!< Bit 1 */ +#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!< Bit 2 */ +#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!< Bit 3 */ + +/******************* Bit definition for TIM_CCER register *******************/ +#define TIM_CCER_CC1E ((uint16_t)0x0001) /*!< Capture/Compare 1 output enable */ +#define TIM_CCER_CC1P ((uint16_t)0x0002) /*!< Capture/Compare 1 output Polarity */ +#define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!< Capture/Compare 1 Complementary output enable */ +#define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!< Capture/Compare 1 Complementary output Polarity */ +#define TIM_CCER_CC2E ((uint16_t)0x0010) /*!< Capture/Compare 2 output enable */ +#define TIM_CCER_CC2P ((uint16_t)0x0020) /*!< Capture/Compare 2 output Polarity */ +#define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!< Capture/Compare 2 Complementary output enable */ +#define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!< Capture/Compare 2 Complementary output Polarity */ +#define TIM_CCER_CC3E ((uint16_t)0x0100) /*!< Capture/Compare 3 output enable */ +#define TIM_CCER_CC3P ((uint16_t)0x0200) /*!< Capture/Compare 3 output Polarity */ +#define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!< Capture/Compare 3 Complementary output enable */ +#define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!< Capture/Compare 3 Complementary output Polarity */ +#define TIM_CCER_CC4E ((uint16_t)0x1000) /*!< Capture/Compare 4 output enable */ +#define TIM_CCER_CC4P ((uint16_t)0x2000) /*!< Capture/Compare 4 output Polarity */ +#define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!< Capture/Compare 4 Complementary output Polarity */ + +/******************* Bit definition for TIM_CNT register ********************/ +#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!< Counter Value */ + +/******************* Bit definition for TIM_PSC register ********************/ +#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!< Prescaler Value */ + +/******************* Bit definition for TIM_ARR register ********************/ +#define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!< actual auto-reload Value */ + +/******************* Bit definition for TIM_RCR register ********************/ +#define TIM_RCR_REP ((uint8_t)0xFF) /*!< Repetition Counter Value */ + +/******************* Bit definition for TIM_CCR1 register *******************/ +#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!< Capture/Compare 1 Value */ + +/******************* Bit definition for TIM_CCR2 register *******************/ +#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!< Capture/Compare 2 Value */ + +/******************* Bit definition for TIM_CCR3 register *******************/ +#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!< Capture/Compare 3 Value */ + +/******************* Bit definition for TIM_CCR4 register *******************/ +#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!< Capture/Compare 4 Value */ + +/******************* Bit definition for TIM_BDTR register *******************/ +#define TIM_BDTR_DTG ((uint16_t)0x00FF) /*!< DTG[0:7] bits (Dead-Time Generator set-up) */ +#define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /*!< Bit 4 */ +#define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /*!< Bit 5 */ +#define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /*!< Bit 6 */ +#define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /*!< Bit 7 */ + +#define TIM_BDTR_LOCK ((uint16_t)0x0300) /*!< LOCK[1:0] bits (Lock Configuration) */ +#define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define TIM_BDTR_OSSI ((uint16_t)0x0400) /*!< Off-State Selection for Idle mode */ +#define TIM_BDTR_OSSR ((uint16_t)0x0800) /*!< Off-State Selection for Run mode */ +#define TIM_BDTR_BKE ((uint16_t)0x1000) /*!< Break enable */ +#define TIM_BDTR_BKP ((uint16_t)0x2000) /*!< Break Polarity */ +#define TIM_BDTR_AOE ((uint16_t)0x4000) /*!< Automatic Output enable */ +#define TIM_BDTR_MOE ((uint16_t)0x8000) /*!< Main Output enable */ + +/******************* Bit definition for TIM_DCR register ********************/ +#define TIM_DCR_DBA ((uint16_t)0x001F) /*!< DBA[4:0] bits (DMA Base Address) */ +#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!< Bit 4 */ + +#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!< DBL[4:0] bits (DMA Burst Length) */ +#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!< Bit 1 */ +#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!< Bit 2 */ +#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!< Bit 3 */ +#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!< Bit 4 */ + +/******************* Bit definition for TIM_DMAR register *******************/ +#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!< DMA register for burst accesses */ + +/******************************************************************************/ +/* */ +/* Real-Time Clock */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for RTC_CRH register ********************/ +#define RTC_CRH_SECIE ((uint8_t)0x01) /*!< Second Interrupt Enable */ +#define RTC_CRH_ALRIE ((uint8_t)0x02) /*!< Alarm Interrupt Enable */ +#define RTC_CRH_OWIE ((uint8_t)0x04) /*!< OverfloW Interrupt Enable */ + +/******************* Bit definition for RTC_CRL register ********************/ +#define RTC_CRL_SECF ((uint8_t)0x01) /*!< Second Flag */ +#define RTC_CRL_ALRF ((uint8_t)0x02) /*!< Alarm Flag */ +#define RTC_CRL_OWF ((uint8_t)0x04) /*!< OverfloW Flag */ +#define RTC_CRL_RSF ((uint8_t)0x08) /*!< Registers Synchronized Flag */ +#define RTC_CRL_CNF ((uint8_t)0x10) /*!< Configuration Flag */ +#define RTC_CRL_RTOFF ((uint8_t)0x20) /*!< RTC operation OFF */ + +/******************* Bit definition for RTC_PRLH register *******************/ +#define RTC_PRLH_PRL ((uint16_t)0x000F) /*!< RTC Prescaler Reload Value High */ + +/******************* Bit definition for RTC_PRLL register *******************/ +#define RTC_PRLL_PRL ((uint16_t)0xFFFF) /*!< RTC Prescaler Reload Value Low */ + +/******************* Bit definition for RTC_DIVH register *******************/ +#define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) /*!< RTC Clock Divider High */ + +/******************* Bit definition for RTC_DIVL register *******************/ +#define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) /*!< RTC Clock Divider Low */ + +/******************* Bit definition for RTC_CNTH register *******************/ +#define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) /*!< RTC Counter High */ + +/******************* Bit definition for RTC_CNTL register *******************/ +#define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) /*!< RTC Counter Low */ + +/******************* Bit definition for RTC_ALRH register *******************/ +#define RTC_ALRH_RTC_ALR ((uint16_t)0xFFFF) /*!< RTC Alarm High */ + +/******************* Bit definition for RTC_ALRL register *******************/ +#define RTC_ALRL_RTC_ALR ((uint16_t)0xFFFF) /*!< RTC Alarm Low */ + +/******************************************************************************/ +/* */ +/* Independent WATCHDOG */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for IWDG_KR register ********************/ +#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!< Key value (write only, read 0000h) */ + +/******************* Bit definition for IWDG_PR register ********************/ +#define IWDG_PR_PR ((uint8_t)0x07) /*!< PR[2:0] (Prescaler divider) */ +#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!< Bit 0 */ +#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!< Bit 1 */ +#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!< Bit 2 */ + +/******************* Bit definition for IWDG_RLR register *******************/ +#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!< Watchdog counter reload value */ + +/******************* Bit definition for IWDG_SR register ********************/ +#define IWDG_SR_PVU ((uint8_t)0x01) /*!< Watchdog prescaler value update */ +#define IWDG_SR_RVU ((uint8_t)0x02) /*!< Watchdog counter reload value update */ + +/******************************************************************************/ +/* */ +/* Window WATCHDOG */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for WWDG_CR register ********************/ +#define WWDG_CR_T ((uint8_t)0x7F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */ +#define WWDG_CR_T0 ((uint8_t)0x01) /*!< Bit 0 */ +#define WWDG_CR_T1 ((uint8_t)0x02) /*!< Bit 1 */ +#define WWDG_CR_T2 ((uint8_t)0x04) /*!< Bit 2 */ +#define WWDG_CR_T3 ((uint8_t)0x08) /*!< Bit 3 */ +#define WWDG_CR_T4 ((uint8_t)0x10) /*!< Bit 4 */ +#define WWDG_CR_T5 ((uint8_t)0x20) /*!< Bit 5 */ +#define WWDG_CR_T6 ((uint8_t)0x40) /*!< Bit 6 */ + +#define WWDG_CR_WDGA ((uint8_t)0x80) /*!< Activation bit */ + +/******************* Bit definition for WWDG_CFR register *******************/ +#define WWDG_CFR_W ((uint16_t)0x007F) /*!< W[6:0] bits (7-bit window value) */ +#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!< Bit 4 */ +#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!< Bit 5 */ +#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!< Bit 6 */ + +#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!< WDGTB[1:0] bits (Timer Base) */ +#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!< Bit 0 */ +#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!< Bit 1 */ + +#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!< Early Wakeup Interrupt */ + +/******************* Bit definition for WWDG_SR register ********************/ +#define WWDG_SR_EWIF ((uint8_t)0x01) /*!< Early Wakeup Interrupt Flag */ + +/******************************************************************************/ +/* */ +/* Flexible Static Memory Controller */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for FSMC_BCR1 register *******************/ +#define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ +#define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ + +#define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ +#define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ +#define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ +#define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ +#define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ +#define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ +#define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ +#define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ +#define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ +#define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ +#define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ +#define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ + +/****************** Bit definition for FSMC_BCR2 register *******************/ +#define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ +#define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ + +#define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ +#define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ +#define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ +#define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ +#define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ +#define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ +#define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ +#define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ +#define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ +#define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ +#define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ +#define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ + +/****************** Bit definition for FSMC_BCR3 register *******************/ +#define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ +#define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ + +#define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ +#define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ +#define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ +#define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ +#define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit. */ +#define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ +#define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ +#define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ +#define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ +#define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ +#define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ +#define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ + +/****************** Bit definition for FSMC_BCR4 register *******************/ +#define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */ +#define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */ + +#define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */ +#define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */ +#define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */ +#define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */ +#define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */ +#define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */ +#define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */ +#define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!< Write enable bit */ +#define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */ +#define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */ +#define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */ +#define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */ + +/****************** Bit definition for FSMC_BTR1 register ******************/ +#define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ + +#define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for FSMC_BTR2 register *******************/ +#define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ + +#define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/******************* Bit definition for FSMC_BTR3 register *******************/ +#define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ + +#define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for FSMC_BTR4 register *******************/ +#define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */ +#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */ + +#define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for FSMC_BWTR1 register ******************/ +#define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for FSMC_BWTR2 register ******************/ +#define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1*/ +#define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for FSMC_BWTR3 register ******************/ +#define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for FSMC_BWTR4 register ******************/ +#define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */ +#define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + +#define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */ +#define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */ +#define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */ +#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */ +#define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */ +#define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +/****************** Bit definition for FSMC_PCR2 register *******************/ +#define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ +#define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ +#define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!< Memory type */ + +#define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ +#define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ + +#define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ +#define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */ +#define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */ + +#define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ +#define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */ +#define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */ +#define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */ + +#define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[1:0] bits (ECC page size) */ +#define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ +#define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ +#define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ + +/****************** Bit definition for FSMC_PCR3 register *******************/ +#define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ +#define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ +#define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!< Memory type */ + +#define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ +#define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ + +#define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ +#define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */ +#define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */ + +#define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ +#define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */ +#define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */ +#define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */ + +#define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[2:0] bits (ECC page size) */ +#define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ +#define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ +#define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ + +/****************** Bit definition for FSMC_PCR4 register *******************/ +#define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!< Wait feature enable bit */ +#define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!< PC Card/NAND Flash memory bank enable bit */ +#define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!< Memory type */ + +#define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!< PWID[1:0] bits (NAND Flash databus width) */ +#define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!< ECC computation logic enable bit */ + +#define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!< TCLR[3:0] bits (CLE to RE delay) */ +#define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!< Bit 2 */ +#define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!< Bit 3 */ + +#define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!< TAR[3:0] bits (ALE to RE delay) */ +#define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!< Bit 1 */ +#define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!< Bit 2 */ +#define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!< Bit 3 */ + +#define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!< ECCPS[2:0] bits (ECC page size) */ +#define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!< Bit 0 */ +#define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!< Bit 1 */ +#define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!< Bit 2 */ + +/******************* Bit definition for FSMC_SR2 register *******************/ +#define FSMC_SR2_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */ +#define FSMC_SR2_ILS ((uint8_t)0x02) /*!< Interrupt Level status */ +#define FSMC_SR2_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */ +#define FSMC_SR2_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */ +#define FSMC_SR2_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */ +#define FSMC_SR2_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */ +#define FSMC_SR2_FEMPT ((uint8_t)0x40) /*!< FIFO empty */ + +/******************* Bit definition for FSMC_SR3 register *******************/ +#define FSMC_SR3_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */ +#define FSMC_SR3_ILS ((uint8_t)0x02) /*!< Interrupt Level status */ +#define FSMC_SR3_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */ +#define FSMC_SR3_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */ +#define FSMC_SR3_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */ +#define FSMC_SR3_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */ +#define FSMC_SR3_FEMPT ((uint8_t)0x40) /*!< FIFO empty */ + +/******************* Bit definition for FSMC_SR4 register *******************/ +#define FSMC_SR4_IRS ((uint8_t)0x01) /*!< Interrupt Rising Edge status */ +#define FSMC_SR4_ILS ((uint8_t)0x02) /*!< Interrupt Level status */ +#define FSMC_SR4_IFS ((uint8_t)0x04) /*!< Interrupt Falling Edge status */ +#define FSMC_SR4_IREN ((uint8_t)0x08) /*!< Interrupt Rising Edge detection Enable bit */ +#define FSMC_SR4_ILEN ((uint8_t)0x10) /*!< Interrupt Level detection Enable bit */ +#define FSMC_SR4_IFEN ((uint8_t)0x20) /*!< Interrupt Falling Edge detection Enable bit */ +#define FSMC_SR4_FEMPT ((uint8_t)0x40) /*!< FIFO empty */ + +/****************** Bit definition for FSMC_PMEM2 register ******************/ +#define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!< MEMSET2[7:0] bits (Common memory 2 setup time) */ +#define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!< MEMWAIT2[7:0] bits (Common memory 2 wait time) */ +#define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!< MEMHOLD2[7:0] bits (Common memory 2 hold time) */ +#define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!< MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */ +#define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for FSMC_PMEM3 register ******************/ +#define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!< MEMSET3[7:0] bits (Common memory 3 setup time) */ +#define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!< MEMWAIT3[7:0] bits (Common memory 3 wait time) */ +#define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!< MEMHOLD3[7:0] bits (Common memory 3 hold time) */ +#define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!< MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */ +#define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for FSMC_PMEM4 register ******************/ +#define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!< MEMSET4[7:0] bits (Common memory 4 setup time) */ +#define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!< MEMWAIT4[7:0] bits (Common memory 4 wait time) */ +#define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!< MEMHOLD4[7:0] bits (Common memory 4 hold time) */ +#define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!< MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */ +#define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for FSMC_PATT2 register ******************/ +#define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!< ATTSET2[7:0] bits (Attribute memory 2 setup time) */ +#define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!< ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */ +#define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!< ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */ +#define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!< ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */ +#define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for FSMC_PATT3 register ******************/ +#define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!< ATTSET3[7:0] bits (Attribute memory 3 setup time) */ +#define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!< ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */ +#define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!< ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */ +#define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!< ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */ +#define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for FSMC_PATT4 register ******************/ +#define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!< ATTSET4[7:0] bits (Attribute memory 4 setup time) */ +#define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!< ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */ +#define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!< ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */ +#define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!< ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */ +#define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for FSMC_PIO4 register *******************/ +#define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!< IOSET4[7:0] bits (I/O 4 setup time) */ +#define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!< Bit 4 */ +#define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!< Bit 5 */ +#define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!< Bit 6 */ +#define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!< Bit 7 */ + +#define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!< IOWAIT4[7:0] bits (I/O 4 wait time) */ +#define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!< Bit 2 */ +#define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!< Bit 3 */ +#define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!< Bit 4 */ +#define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!< Bit 5 */ +#define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!< Bit 6 */ +#define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!< Bit 7 */ + +#define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!< IOHOLD4[7:0] bits (I/O 4 hold time) */ +#define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!< Bit 7 */ + +#define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!< IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */ +#define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!< Bit 3 */ +#define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!< Bit 4 */ +#define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!< Bit 5 */ +#define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!< Bit 6 */ +#define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!< Bit 7 */ + +/****************** Bit definition for FSMC_ECCR2 register ******************/ +#define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!< ECC result */ + +/****************** Bit definition for FSMC_ECCR3 register ******************/ +#define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!< ECC result */ + +/******************************************************************************/ +/* */ +/* SD host Interface */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for SDIO_POWER register ******************/ +#define SDIO_POWER_PWRCTRL ((uint8_t)0x03) /*!< PWRCTRL[1:0] bits (Power supply control bits) */ +#define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) /*!< Bit 0 */ +#define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) /*!< Bit 1 */ + +/****************** Bit definition for SDIO_CLKCR register ******************/ +#define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) /*!< Clock divide factor */ +#define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) /*!< Clock enable bit */ +#define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) /*!< Power saving configuration bit */ +#define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) /*!< Clock divider bypass enable bit */ + +#define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */ +#define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /*!< Bit 0 */ +#define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /*!< Bit 1 */ + +#define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) /*!< SDIO_CK dephasing selection bit */ +#define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) /*!< HW Flow Control enable */ + +/******************* Bit definition for SDIO_ARG register *******************/ +#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!< Command argument */ + +/******************* Bit definition for SDIO_CMD register *******************/ +#define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) /*!< Command Index */ + +#define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) /*!< WAITRESP[1:0] bits (Wait for response bits) */ +#define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) /*!< Bit 0 */ +#define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) /*!< Bit 1 */ + +#define SDIO_CMD_WAITINT ((uint16_t)0x0100) /*!< CPSM Waits for Interrupt Request */ +#define SDIO_CMD_WAITPEND ((uint16_t)0x0200) /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */ +#define SDIO_CMD_CPSMEN ((uint16_t)0x0400) /*!< Command path state machine (CPSM) Enable bit */ +#define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) /*!< SD I/O suspend command */ +#define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) /*!< Enable CMD completion */ +#define SDIO_CMD_NIEN ((uint16_t)0x2000) /*!< Not Interrupt Enable */ +#define SDIO_CMD_CEATACMD ((uint16_t)0x4000) /*!< CE-ATA command */ + +/***************** Bit definition for SDIO_RESPCMD register *****************/ +#define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) /*!< Response command index */ + +/****************** Bit definition for SDIO_RESP0 register ******************/ +#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ + +/****************** Bit definition for SDIO_RESP1 register ******************/ +#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ + +/****************** Bit definition for SDIO_RESP2 register ******************/ +#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ + +/****************** Bit definition for SDIO_RESP3 register ******************/ +#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ + +/****************** Bit definition for SDIO_RESP4 register ******************/ +#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!< Card Status */ + +/****************** Bit definition for SDIO_DTIMER register *****************/ +#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!< Data timeout period. */ + +/****************** Bit definition for SDIO_DLEN register *******************/ +#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!< Data length value */ + +/****************** Bit definition for SDIO_DCTRL register ******************/ +#define SDIO_DCTRL_DTEN ((uint16_t)0x0001) /*!< Data transfer enabled bit */ +#define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) /*!< Data transfer direction selection */ +#define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) /*!< Data transfer mode selection */ +#define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) /*!< DMA enabled bit */ + +#define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /*!< DBLOCKSIZE[3:0] bits (Data block size) */ +#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /*!< Bit 1 */ +#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /*!< Bit 2 */ +#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /*!< Bit 3 */ + +#define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) /*!< Read wait start */ +#define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) /*!< Read wait stop */ +#define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) /*!< Read wait mode */ +#define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) /*!< SD I/O enable functions */ + +/****************** Bit definition for SDIO_DCOUNT register *****************/ +#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!< Data count value */ + +/****************** Bit definition for SDIO_STA register ********************/ +#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!< Command response received (CRC check failed) */ +#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!< Data block sent/received (CRC check failed) */ +#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!< Command response timeout */ +#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!< Data timeout */ +#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!< Transmit FIFO underrun error */ +#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!< Received FIFO overrun error */ +#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!< Command response received (CRC check passed) */ +#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!< Command sent (no response required) */ +#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!< Data end (data counter, SDIDCOUNT, is zero) */ +#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!< Start bit not detected on all data signals in wide bus mode */ +#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!< Data block sent/received (CRC check passed) */ +#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!< Command transfer in progress */ +#define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!< Data transmit in progress */ +#define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!< Data receive in progress */ +#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */ +#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */ +#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!< Transmit FIFO full */ +#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!< Receive FIFO full */ +#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!< Transmit FIFO empty */ +#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!< Receive FIFO empty */ +#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!< Data available in transmit FIFO */ +#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!< Data available in receive FIFO */ +#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!< SDIO interrupt received */ +#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received for CMD61 */ + +/******************* Bit definition for SDIO_ICR register *******************/ +#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!< CCRCFAIL flag clear bit */ +#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!< DCRCFAIL flag clear bit */ +#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!< CTIMEOUT flag clear bit */ +#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!< DTIMEOUT flag clear bit */ +#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!< TXUNDERR flag clear bit */ +#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!< RXOVERR flag clear bit */ +#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!< CMDREND flag clear bit */ +#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!< CMDSENT flag clear bit */ +#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!< DATAEND flag clear bit */ +#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!< STBITERR flag clear bit */ +#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!< DBCKEND flag clear bit */ +#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!< SDIOIT flag clear bit */ +#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!< CEATAEND flag clear bit */ + +/****************** Bit definition for SDIO_MASK register *******************/ +#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!< Command CRC Fail Interrupt Enable */ +#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!< Data CRC Fail Interrupt Enable */ +#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!< Command TimeOut Interrupt Enable */ +#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!< Data TimeOut Interrupt Enable */ +#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!< Tx FIFO UnderRun Error Interrupt Enable */ +#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!< Rx FIFO OverRun Error Interrupt Enable */ +#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!< Command Response Received Interrupt Enable */ +#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!< Command Sent Interrupt Enable */ +#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!< Data End Interrupt Enable */ +#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!< Start Bit Error Interrupt Enable */ +#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!< Data Block End Interrupt Enable */ +#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!< Command Acting Interrupt Enable */ +#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!< Data Transmit Acting Interrupt Enable */ +#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!< Data receive acting interrupt enabled */ +#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!< Tx FIFO Half Empty interrupt Enable */ +#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!< Rx FIFO Half Full interrupt Enable */ +#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!< Tx FIFO Full interrupt Enable */ +#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!< Rx FIFO Full interrupt Enable */ +#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!< Tx FIFO Empty interrupt Enable */ +#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!< Rx FIFO Empty interrupt Enable */ +#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!< Data available in Tx FIFO interrupt Enable */ +#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!< Data available in Rx FIFO interrupt Enable */ +#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!< SDIO Mode Interrupt Received interrupt Enable */ +#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received Interrupt Enable */ + +/***************** Bit definition for SDIO_FIFOCNT register *****************/ +#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!< Remaining number of words to be written to or read from the FIFO */ + +/****************** Bit definition for SDIO_FIFO register *******************/ +#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!< Receive and transmit FIFO data */ + +/******************************************************************************/ +/* */ +/* USB Device FS */ +/* */ +/******************************************************************************/ + +/*!< Endpoint-specific registers */ +/******************* Bit definition for USB_EP0R register *******************/ +#define USB_EP0R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP0R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP0R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP0R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP0R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP0R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP0R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP0R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP0R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP0R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP0R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP0R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP0R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP0R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP1R register *******************/ +#define USB_EP1R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP1R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP1R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP1R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP1R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP1R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP1R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP1R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP1R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP1R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP1R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP1R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP1R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP1R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP2R register *******************/ +#define USB_EP2R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP2R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP2R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP2R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP2R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP2R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP2R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP2R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP2R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP2R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP2R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP2R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP2R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP2R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP3R register *******************/ +#define USB_EP3R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP3R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP3R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP3R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP3R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP3R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP3R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP3R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP3R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP3R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP3R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP3R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP3R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP3R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP4R register *******************/ +#define USB_EP4R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP4R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP4R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP4R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP4R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP4R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP4R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP4R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP4R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP4R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP4R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP4R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP4R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP4R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP5R register *******************/ +#define USB_EP5R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP5R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP5R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP5R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP5R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP5R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP5R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP5R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP5R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP5R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP5R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP5R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP5R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP5R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP6R register *******************/ +#define USB_EP6R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP6R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP6R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP6R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP6R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP6R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP6R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP6R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP6R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP6R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP6R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP6R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP6R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP6R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP7R register *******************/ +#define USB_EP7R_EA ((uint16_t)0x000F) /*!< Endpoint Address */ + +#define USB_EP7R_STAT_TX ((uint16_t)0x0030) /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP7R_STAT_TX_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define USB_EP7R_STAT_TX_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define USB_EP7R_DTOG_TX ((uint16_t)0x0040) /*!< Data Toggle, for transmission transfers */ +#define USB_EP7R_CTR_TX ((uint16_t)0x0080) /*!< Correct Transfer for transmission */ +#define USB_EP7R_EP_KIND ((uint16_t)0x0100) /*!< Endpoint Kind */ + +#define USB_EP7R_EP_TYPE ((uint16_t)0x0600) /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200) /*!< Bit 0 */ +#define USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400) /*!< Bit 1 */ + +#define USB_EP7R_SETUP ((uint16_t)0x0800) /*!< Setup transaction completed */ + +#define USB_EP7R_STAT_RX ((uint16_t)0x3000) /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP7R_STAT_RX_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USB_EP7R_STAT_RX_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USB_EP7R_DTOG_RX ((uint16_t)0x4000) /*!< Data Toggle, for reception transfers */ +#define USB_EP7R_CTR_RX ((uint16_t)0x8000) /*!< Correct Transfer for reception */ + +/*!< Common registers */ +/******************* Bit definition for USB_CNTR register *******************/ +#define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB Reset */ +#define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power down */ +#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!< Low-power mode */ +#define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force suspend */ +#define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< Resume request */ +#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Interrupt Mask */ +#define USB_CNTR_SOFM ((uint16_t)0x0200) /*!< Start Of Frame Interrupt Mask */ +#define USB_CNTR_RESETM ((uint16_t)0x0400) /*!< RESET Interrupt Mask */ +#define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< Suspend mode Interrupt Mask */ +#define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< Wakeup Interrupt Mask */ +#define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< Error Interrupt Mask */ +#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun Interrupt Mask */ +#define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct Transfer Interrupt Mask */ + +/******************* Bit definition for USB_ISTR register *******************/ +#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< Endpoint Identifier */ +#define USB_ISTR_DIR ((uint16_t)0x0010) /*!< Direction of transaction */ +#define USB_ISTR_ESOF ((uint16_t)0x0100) /*!< Expected Start Of Frame */ +#define USB_ISTR_SOF ((uint16_t)0x0200) /*!< Start Of Frame */ +#define USB_ISTR_RESET ((uint16_t)0x0400) /*!< USB RESET request */ +#define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< Suspend mode request */ +#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< Wake up */ +#define USB_ISTR_ERR ((uint16_t)0x2000) /*!< Error */ +#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!< Packet Memory Area Over / Underrun */ +#define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct Transfer */ + +/******************* Bit definition for USB_FNR register ********************/ +#define USB_FNR_FN ((uint16_t)0x07FF) /*!< Frame Number */ +#define USB_FNR_LSOF ((uint16_t)0x1800) /*!< Lost SOF */ +#define USB_FNR_LCK ((uint16_t)0x2000) /*!< Locked */ +#define USB_FNR_RXDM ((uint16_t)0x4000) /*!< Receive Data - Line Status */ +#define USB_FNR_RXDP ((uint16_t)0x8000) /*!< Receive Data + Line Status */ + +/****************** Bit definition for USB_DADDR register *******************/ +#define USB_DADDR_ADD ((uint8_t)0x7F) /*!< ADD[6:0] bits (Device Address) */ +#define USB_DADDR_ADD0 ((uint8_t)0x01) /*!< Bit 0 */ +#define USB_DADDR_ADD1 ((uint8_t)0x02) /*!< Bit 1 */ +#define USB_DADDR_ADD2 ((uint8_t)0x04) /*!< Bit 2 */ +#define USB_DADDR_ADD3 ((uint8_t)0x08) /*!< Bit 3 */ +#define USB_DADDR_ADD4 ((uint8_t)0x10) /*!< Bit 4 */ +#define USB_DADDR_ADD5 ((uint8_t)0x20) /*!< Bit 5 */ +#define USB_DADDR_ADD6 ((uint8_t)0x40) /*!< Bit 6 */ + +#define USB_DADDR_EF ((uint8_t)0x80) /*!< Enable Function */ + +/****************** Bit definition for USB_BTABLE register ******************/ +#define USB_BTABLE_BTABLE ((uint16_t)0xFFF8) /*!< Buffer Table */ + +/*!< Buffer descriptor table */ +/***************** Bit definition for USB_ADDR0_TX register *****************/ +#define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 0 */ + +/***************** Bit definition for USB_ADDR1_TX register *****************/ +#define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 1 */ + +/***************** Bit definition for USB_ADDR2_TX register *****************/ +#define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 2 */ + +/***************** Bit definition for USB_ADDR3_TX register *****************/ +#define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 3 */ + +/***************** Bit definition for USB_ADDR4_TX register *****************/ +#define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 4 */ + +/***************** Bit definition for USB_ADDR5_TX register *****************/ +#define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 5 */ + +/***************** Bit definition for USB_ADDR6_TX register *****************/ +#define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 6 */ + +/***************** Bit definition for USB_ADDR7_TX register *****************/ +#define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 7 */ + +/*----------------------------------------------------------------------------*/ + +/***************** Bit definition for USB_COUNT0_TX register ****************/ +#define USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 0 */ + +/***************** Bit definition for USB_COUNT1_TX register ****************/ +#define USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 1 */ + +/***************** Bit definition for USB_COUNT2_TX register ****************/ +#define USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 2 */ + +/***************** Bit definition for USB_COUNT3_TX register ****************/ +#define USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 3 */ + +/***************** Bit definition for USB_COUNT4_TX register ****************/ +#define USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 4 */ + +/***************** Bit definition for USB_COUNT5_TX register ****************/ +#define USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 5 */ + +/***************** Bit definition for USB_COUNT6_TX register ****************/ +#define USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 6 */ + +/***************** Bit definition for USB_COUNT7_TX register ****************/ +#define USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 7 */ + +/*----------------------------------------------------------------------------*/ + +/**************** Bit definition for USB_COUNT0_TX_0 register ***************/ +#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */ + +/**************** Bit definition for USB_COUNT0_TX_1 register ***************/ +#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */ + +/**************** Bit definition for USB_COUNT1_TX_0 register ***************/ +#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */ + +/**************** Bit definition for USB_COUNT1_TX_1 register ***************/ +#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */ + +/**************** Bit definition for USB_COUNT2_TX_0 register ***************/ +#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */ + +/**************** Bit definition for USB_COUNT2_TX_1 register ***************/ +#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */ + +/**************** Bit definition for USB_COUNT3_TX_0 register ***************/ +#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */ + +/**************** Bit definition for USB_COUNT3_TX_1 register ***************/ +#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */ + +/**************** Bit definition for USB_COUNT4_TX_0 register ***************/ +#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */ + +/**************** Bit definition for USB_COUNT4_TX_1 register ***************/ +#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */ + +/**************** Bit definition for USB_COUNT5_TX_0 register ***************/ +#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */ + +/**************** Bit definition for USB_COUNT5_TX_1 register ***************/ +#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */ + +/**************** Bit definition for USB_COUNT6_TX_0 register ***************/ +#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */ + +/**************** Bit definition for USB_COUNT6_TX_1 register ***************/ +#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */ + +/**************** Bit definition for USB_COUNT7_TX_0 register ***************/ +#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */ + +/**************** Bit definition for USB_COUNT7_TX_1 register ***************/ +#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */ + +/*----------------------------------------------------------------------------*/ + +/***************** Bit definition for USB_ADDR0_RX register *****************/ +#define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 0 */ + +/***************** Bit definition for USB_ADDR1_RX register *****************/ +#define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 1 */ + +/***************** Bit definition for USB_ADDR2_RX register *****************/ +#define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 2 */ + +/***************** Bit definition for USB_ADDR3_RX register *****************/ +#define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 3 */ + +/***************** Bit definition for USB_ADDR4_RX register *****************/ +#define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 4 */ + +/***************** Bit definition for USB_ADDR5_RX register *****************/ +#define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 5 */ + +/***************** Bit definition for USB_ADDR6_RX register *****************/ +#define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 6 */ + +/***************** Bit definition for USB_ADDR7_RX register *****************/ +#define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 7 */ + +/*----------------------------------------------------------------------------*/ + +/***************** Bit definition for USB_COUNT0_RX register ****************/ +#define USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT1_RX register ****************/ +#define USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT2_RX register ****************/ +#define USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT3_RX register ****************/ +#define USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT4_RX register ****************/ +#define USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT5_RX register ****************/ +#define USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT6_RX register ****************/ +#define USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT7_RX register ****************/ +#define USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */ + +#define USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */ +#define USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */ +#define USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */ +#define USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */ + +#define USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */ + +/*----------------------------------------------------------------------------*/ + +/**************** Bit definition for USB_COUNT0_RX_0 register ***************/ +#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT0_RX_1 register ***************/ +#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT1_RX_0 register ***************/ +#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT1_RX_1 register ***************/ +#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT2_RX_0 register ***************/ +#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT2_RX_1 register ***************/ +#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT3_RX_0 register ***************/ +#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT3_RX_1 register ***************/ +#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT4_RX_0 register ***************/ +#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT4_RX_1 register ***************/ +#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT5_RX_0 register ***************/ +#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT5_RX_1 register ***************/ +#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/*************** Bit definition for USB_COUNT6_RX_0 register ***************/ +#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT6_RX_1 register ***************/ +#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/*************** Bit definition for USB_COUNT7_RX_0 register ****************/ +#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ + +#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ + +/*************** Bit definition for USB_COUNT7_RX_1 register ****************/ +#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ + +#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ + +#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ + +/******************************************************************************/ +/* */ +/* Controller Area Network */ +/* */ +/******************************************************************************/ + +/*!< CAN control and status registers */ +/******************* Bit definition for CAN_MCR register ********************/ +#define CAN_MCR_INRQ ((uint16_t)0x0001) /*!< Initialization Request */ +#define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!< Sleep Mode Request */ +#define CAN_MCR_TXFP ((uint16_t)0x0004) /*!< Transmit FIFO Priority */ +#define CAN_MCR_RFLM ((uint16_t)0x0008) /*!< Receive FIFO Locked Mode */ +#define CAN_MCR_NART ((uint16_t)0x0010) /*!< No Automatic Retransmission */ +#define CAN_MCR_AWUM ((uint16_t)0x0020) /*!< Automatic Wakeup Mode */ +#define CAN_MCR_ABOM ((uint16_t)0x0040) /*!< Automatic Bus-Off Management */ +#define CAN_MCR_TTCM ((uint16_t)0x0080) /*!< Time Triggered Communication Mode */ +#define CAN_MCR_RESET ((uint16_t)0x8000) /*!< CAN software master reset */ + +/******************* Bit definition for CAN_MSR register ********************/ +#define CAN_MSR_INAK ((uint16_t)0x0001) /*!< Initialization Acknowledge */ +#define CAN_MSR_SLAK ((uint16_t)0x0002) /*!< Sleep Acknowledge */ +#define CAN_MSR_ERRI ((uint16_t)0x0004) /*!< Error Interrupt */ +#define CAN_MSR_WKUI ((uint16_t)0x0008) /*!< Wakeup Interrupt */ +#define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!< Sleep Acknowledge Interrupt */ +#define CAN_MSR_TXM ((uint16_t)0x0100) /*!< Transmit Mode */ +#define CAN_MSR_RXM ((uint16_t)0x0200) /*!< Receive Mode */ +#define CAN_MSR_SAMP ((uint16_t)0x0400) /*!< Last Sample Point */ +#define CAN_MSR_RX ((uint16_t)0x0800) /*!< CAN Rx Signal */ + +/******************* Bit definition for CAN_TSR register ********************/ +#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!< Request Completed Mailbox0 */ +#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!< Transmission OK of Mailbox0 */ +#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!< Arbitration Lost for Mailbox0 */ +#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!< Transmission Error of Mailbox0 */ +#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!< Abort Request for Mailbox0 */ +#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!< Request Completed Mailbox1 */ +#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!< Transmission OK of Mailbox1 */ +#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!< Arbitration Lost for Mailbox1 */ +#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!< Transmission Error of Mailbox1 */ +#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!< Abort Request for Mailbox 1 */ +#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!< Request Completed Mailbox2 */ +#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!< Transmission OK of Mailbox 2 */ +#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!< Arbitration Lost for mailbox 2 */ +#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!< Transmission Error of Mailbox 2 */ +#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!< Abort Request for Mailbox 2 */ +#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!< Mailbox Code */ + +#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!< TME[2:0] bits */ +#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!< Transmit Mailbox 0 Empty */ +#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!< Transmit Mailbox 1 Empty */ +#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!< Transmit Mailbox 2 Empty */ + +#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!< LOW[2:0] bits */ +#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!< Lowest Priority Flag for Mailbox 0 */ +#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!< Lowest Priority Flag for Mailbox 1 */ +#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!< Lowest Priority Flag for Mailbox 2 */ + +/******************* Bit definition for CAN_RF0R register *******************/ +#define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!< FIFO 0 Message Pending */ +#define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!< FIFO 0 Full */ +#define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!< FIFO 0 Overrun */ +#define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!< Release FIFO 0 Output Mailbox */ + +/******************* Bit definition for CAN_RF1R register *******************/ +#define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!< FIFO 1 Message Pending */ +#define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!< FIFO 1 Full */ +#define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!< FIFO 1 Overrun */ +#define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!< Release FIFO 1 Output Mailbox */ + +/******************** Bit definition for CAN_IER register *******************/ +#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!< Transmit Mailbox Empty Interrupt Enable */ +#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!< FIFO Message Pending Interrupt Enable */ +#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!< FIFO Full Interrupt Enable */ +#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!< FIFO Overrun Interrupt Enable */ +#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!< FIFO Message Pending Interrupt Enable */ +#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!< FIFO Full Interrupt Enable */ +#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!< FIFO Overrun Interrupt Enable */ +#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!< Error Warning Interrupt Enable */ +#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!< Error Passive Interrupt Enable */ +#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!< Bus-Off Interrupt Enable */ +#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!< Last Error Code Interrupt Enable */ +#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!< Error Interrupt Enable */ +#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!< Wakeup Interrupt Enable */ +#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!< Sleep Interrupt Enable */ + +/******************** Bit definition for CAN_ESR register *******************/ +#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!< Error Warning Flag */ +#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!< Error Passive Flag */ +#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!< Bus-Off Flag */ + +#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!< LEC[2:0] bits (Last Error Code) */ +#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!< Bit 2 */ + +#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!< Least significant byte of the 9-bit Transmit Error Counter */ +#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!< Receive Error Counter */ + +/******************* Bit definition for CAN_BTR register ********************/ +#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!< Baud Rate Prescaler */ +#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!< Time Segment 1 */ +#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!< Time Segment 2 */ +#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!< Resynchronization Jump Width */ +#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!< Loop Back Mode (Debug) */ +#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!< Silent Mode */ + +/*!< Mailbox registers */ +/****************** Bit definition for CAN_TI0R register ********************/ +#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ +#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ +#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ +#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ +#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ + +/****************** Bit definition for CAN_TDT0R register *******************/ +#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ +#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ +#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ + +/****************** Bit definition for CAN_TDL0R register *******************/ +#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ +#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ +#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ +#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ + +/****************** Bit definition for CAN_TDH0R register *******************/ +#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ +#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ +#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ +#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ + +/******************* Bit definition for CAN_TI1R register *******************/ +#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ +#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ +#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ +#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ +#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_TDT1R register ******************/ +#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ +#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ +#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ + +/******************* Bit definition for CAN_TDL1R register ******************/ +#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ +#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ +#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ +#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ + +/******************* Bit definition for CAN_TDH1R register ******************/ +#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ +#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ +#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ +#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ + +/******************* Bit definition for CAN_TI2R register *******************/ +#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!< Transmit Mailbox Request */ +#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ +#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ +#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!< Extended identifier */ +#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_TDT2R register ******************/ +#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ +#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!< Transmit Global Time */ +#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ + +/******************* Bit definition for CAN_TDL2R register ******************/ +#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ +#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ +#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ +#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ + +/******************* Bit definition for CAN_TDH2R register ******************/ +#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ +#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ +#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ +#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ + +/******************* Bit definition for CAN_RI0R register *******************/ +#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ +#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ +#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!< Extended Identifier */ +#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_RDT0R register ******************/ +#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ +#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */ +#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ + +/******************* Bit definition for CAN_RDL0R register ******************/ +#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ +#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ +#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ +#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ + +/******************* Bit definition for CAN_RDH0R register ******************/ +#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ +#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ +#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ +#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ + +/******************* Bit definition for CAN_RI1R register *******************/ +#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!< Remote Transmission Request */ +#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!< Identifier Extension */ +#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!< Extended identifier */ +#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!< Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_RDT1R register ******************/ +#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!< Data Length Code */ +#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!< Filter Match Index */ +#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!< Message Time Stamp */ + +/******************* Bit definition for CAN_RDL1R register ******************/ +#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!< Data byte 0 */ +#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!< Data byte 1 */ +#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!< Data byte 2 */ +#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!< Data byte 3 */ + +/******************* Bit definition for CAN_RDH1R register ******************/ +#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!< Data byte 4 */ +#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!< Data byte 5 */ +#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!< Data byte 6 */ +#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!< Data byte 7 */ + +/*!< CAN filter registers */ +/******************* Bit definition for CAN_FMR register ********************/ +#define CAN_FMR_FINIT ((uint8_t)0x01) /*!< Filter Init Mode */ + +/******************* Bit definition for CAN_FM1R register *******************/ +#define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!< Filter Mode */ +#define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!< Filter Init Mode bit 0 */ +#define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!< Filter Init Mode bit 1 */ +#define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!< Filter Init Mode bit 2 */ +#define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!< Filter Init Mode bit 3 */ +#define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!< Filter Init Mode bit 4 */ +#define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!< Filter Init Mode bit 5 */ +#define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!< Filter Init Mode bit 6 */ +#define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!< Filter Init Mode bit 7 */ +#define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!< Filter Init Mode bit 8 */ +#define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!< Filter Init Mode bit 9 */ +#define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!< Filter Init Mode bit 10 */ +#define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!< Filter Init Mode bit 11 */ +#define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!< Filter Init Mode bit 12 */ +#define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!< Filter Init Mode bit 13 */ + +/******************* Bit definition for CAN_FS1R register *******************/ +#define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!< Filter Scale Configuration */ +#define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!< Filter Scale Configuration bit 0 */ +#define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!< Filter Scale Configuration bit 1 */ +#define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!< Filter Scale Configuration bit 2 */ +#define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!< Filter Scale Configuration bit 3 */ +#define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!< Filter Scale Configuration bit 4 */ +#define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!< Filter Scale Configuration bit 5 */ +#define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!< Filter Scale Configuration bit 6 */ +#define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!< Filter Scale Configuration bit 7 */ +#define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!< Filter Scale Configuration bit 8 */ +#define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!< Filter Scale Configuration bit 9 */ +#define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!< Filter Scale Configuration bit 10 */ +#define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!< Filter Scale Configuration bit 11 */ +#define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!< Filter Scale Configuration bit 12 */ +#define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!< Filter Scale Configuration bit 13 */ + +/****************** Bit definition for CAN_FFA1R register *******************/ +#define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!< Filter FIFO Assignment */ +#define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!< Filter FIFO Assignment for Filter 0 */ +#define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!< Filter FIFO Assignment for Filter 1 */ +#define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!< Filter FIFO Assignment for Filter 2 */ +#define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!< Filter FIFO Assignment for Filter 3 */ +#define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!< Filter FIFO Assignment for Filter 4 */ +#define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!< Filter FIFO Assignment for Filter 5 */ +#define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!< Filter FIFO Assignment for Filter 6 */ +#define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!< Filter FIFO Assignment for Filter 7 */ +#define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!< Filter FIFO Assignment for Filter 8 */ +#define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!< Filter FIFO Assignment for Filter 9 */ +#define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!< Filter FIFO Assignment for Filter 10 */ +#define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!< Filter FIFO Assignment for Filter 11 */ +#define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!< Filter FIFO Assignment for Filter 12 */ +#define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!< Filter FIFO Assignment for Filter 13 */ + +/******************* Bit definition for CAN_FA1R register *******************/ +#define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!< Filter Active */ +#define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!< Filter 0 Active */ +#define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!< Filter 1 Active */ +#define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!< Filter 2 Active */ +#define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!< Filter 3 Active */ +#define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!< Filter 4 Active */ +#define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!< Filter 5 Active */ +#define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!< Filter 6 Active */ +#define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!< Filter 7 Active */ +#define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!< Filter 8 Active */ +#define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!< Filter 9 Active */ +#define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!< Filter 10 Active */ +#define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!< Filter 11 Active */ +#define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!< Filter 12 Active */ +#define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!< Filter 13 Active */ + +/******************* Bit definition for CAN_F0R1 register *******************/ +#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F1R1 register *******************/ +#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F2R1 register *******************/ +#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F3R1 register *******************/ +#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F4R1 register *******************/ +#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F5R1 register *******************/ +#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F6R1 register *******************/ +#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F7R1 register *******************/ +#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F8R1 register *******************/ +#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F9R1 register *******************/ +#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F10R1 register ******************/ +#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F11R1 register ******************/ +#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F12R1 register ******************/ +#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F13R1 register ******************/ +#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F0R2 register *******************/ +#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F1R2 register *******************/ +#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F2R2 register *******************/ +#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F3R2 register *******************/ +#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F4R2 register *******************/ +#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F5R2 register *******************/ +#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F6R2 register *******************/ +#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F7R2 register *******************/ +#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F8R2 register *******************/ +#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F9R2 register *******************/ +#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F10R2 register ******************/ +#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F11R2 register ******************/ +#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F12R2 register ******************/ +#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************* Bit definition for CAN_F13R2 register ******************/ +#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!< Filter bit 0 */ +#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!< Filter bit 1 */ +#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!< Filter bit 2 */ +#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!< Filter bit 3 */ +#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!< Filter bit 4 */ +#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!< Filter bit 5 */ +#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!< Filter bit 6 */ +#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!< Filter bit 7 */ +#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!< Filter bit 8 */ +#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!< Filter bit 9 */ +#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!< Filter bit 10 */ +#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!< Filter bit 11 */ +#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!< Filter bit 12 */ +#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!< Filter bit 13 */ +#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!< Filter bit 14 */ +#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!< Filter bit 15 */ +#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!< Filter bit 16 */ +#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!< Filter bit 17 */ +#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!< Filter bit 18 */ +#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!< Filter bit 19 */ +#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!< Filter bit 20 */ +#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!< Filter bit 21 */ +#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!< Filter bit 22 */ +#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!< Filter bit 23 */ +#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!< Filter bit 24 */ +#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!< Filter bit 25 */ +#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!< Filter bit 26 */ +#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!< Filter bit 27 */ +#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!< Filter bit 28 */ +#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!< Filter bit 29 */ +#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!< Filter bit 30 */ +#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!< Filter bit 31 */ + +/******************************************************************************/ +/* */ +/* Serial Peripheral Interface */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for SPI_CR1 register ********************/ +#define SPI_CR1_CPHA ((uint16_t)0x0001) /*!< Clock Phase */ +#define SPI_CR1_CPOL ((uint16_t)0x0002) /*!< Clock Polarity */ +#define SPI_CR1_MSTR ((uint16_t)0x0004) /*!< Master Selection */ + +#define SPI_CR1_BR ((uint16_t)0x0038) /*!< BR[2:0] bits (Baud Rate Control) */ +#define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!< Bit 0 */ +#define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!< Bit 1 */ +#define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!< Bit 2 */ + +#define SPI_CR1_SPE ((uint16_t)0x0040) /*!< SPI Enable */ +#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!< Frame Format */ +#define SPI_CR1_SSI ((uint16_t)0x0100) /*!< Internal slave select */ +#define SPI_CR1_SSM ((uint16_t)0x0200) /*!< Software slave management */ +#define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!< Receive only */ +#define SPI_CR1_DFF ((uint16_t)0x0800) /*!< Data Frame Format */ +#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!< Transmit CRC next */ +#define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!< Hardware CRC calculation enable */ +#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!< Output enable in bidirectional mode */ +#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!< Bidirectional data mode enable */ + +/******************* Bit definition for SPI_CR2 register ********************/ +#define SPI_CR2_RXDMAEN ((uint8_t)0x01) /*!< Rx Buffer DMA Enable */ +#define SPI_CR2_TXDMAEN ((uint8_t)0x02) /*!< Tx Buffer DMA Enable */ +#define SPI_CR2_SSOE ((uint8_t)0x04) /*!< SS Output Enable */ +#define SPI_CR2_ERRIE ((uint8_t)0x20) /*!< Error Interrupt Enable */ +#define SPI_CR2_RXNEIE ((uint8_t)0x40) /*!< RX buffer Not Empty Interrupt Enable */ +#define SPI_CR2_TXEIE ((uint8_t)0x80) /*!< Tx buffer Empty Interrupt Enable */ + +/******************** Bit definition for SPI_SR register ********************/ +#define SPI_SR_RXNE ((uint8_t)0x01) /*!< Receive buffer Not Empty */ +#define SPI_SR_TXE ((uint8_t)0x02) /*!< Transmit buffer Empty */ +#define SPI_SR_CHSIDE ((uint8_t)0x04) /*!< Channel side */ +#define SPI_SR_UDR ((uint8_t)0x08) /*!< Underrun flag */ +#define SPI_SR_CRCERR ((uint8_t)0x10) /*!< CRC Error flag */ +#define SPI_SR_MODF ((uint8_t)0x20) /*!< Mode fault */ +#define SPI_SR_OVR ((uint8_t)0x40) /*!< Overrun flag */ +#define SPI_SR_BSY ((uint8_t)0x80) /*!< Busy flag */ + +/******************** Bit definition for SPI_DR register ********************/ +#define SPI_DR_DR ((uint16_t)0xFFFF) /*!< Data Register */ + +/******************* Bit definition for SPI_CRCPR register ******************/ +#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!< CRC polynomial register */ + +/****************** Bit definition for SPI_RXCRCR register ******************/ +#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!< Rx CRC Register */ + +/****************** Bit definition for SPI_TXCRCR register ******************/ +#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!< Tx CRC Register */ + +/****************** Bit definition for SPI_I2SCFGR register *****************/ +#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!< Channel length (number of bits per audio channel) */ + +#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!< DATLEN[1:0] bits (Data length to be transferred) */ +#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!< Bit 0 */ +#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!< Bit 1 */ + +#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!< steady state clock polarity */ + +#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!< I2SSTD[1:0] bits (I2S standard selection) */ +#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!< Bit 0 */ +#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!< Bit 1 */ + +#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!< PCM frame synchronization */ + +#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!< I2SCFG[1:0] bits (I2S configuration mode) */ +#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!< I2S Enable */ +#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!< I2S mode selection */ + +/****************** Bit definition for SPI_I2SPR register *******************/ +#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!< I2S Linear prescaler */ +#define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!< Odd factor for the prescaler */ +#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!< Master Clock Output Enable */ + +/******************************************************************************/ +/* */ +/* Inter-integrated Circuit Interface */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for I2C_CR1 register ********************/ +#define I2C_CR1_PE ((uint16_t)0x0001) /*!< Peripheral Enable */ +#define I2C_CR1_SMBUS ((uint16_t)0x0002) /*!< SMBus Mode */ +#define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /*!< SMBus Type */ +#define I2C_CR1_ENARP ((uint16_t)0x0010) /*!< ARP Enable */ +#define I2C_CR1_ENPEC ((uint16_t)0x0020) /*!< PEC Enable */ +#define I2C_CR1_ENGC ((uint16_t)0x0040) /*!< General Call Enable */ +#define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /*!< Clock Stretching Disable (Slave mode) */ +#define I2C_CR1_START ((uint16_t)0x0100) /*!< Start Generation */ +#define I2C_CR1_STOP ((uint16_t)0x0200) /*!< Stop Generation */ +#define I2C_CR1_ACK ((uint16_t)0x0400) /*!< Acknowledge Enable */ +#define I2C_CR1_POS ((uint16_t)0x0800) /*!< Acknowledge/PEC Position (for data reception) */ +#define I2C_CR1_PEC ((uint16_t)0x1000) /*!< Packet Error Checking */ +#define I2C_CR1_ALERT ((uint16_t)0x2000) /*!< SMBus Alert */ +#define I2C_CR1_SWRST ((uint16_t)0x8000) /*!< Software Reset */ + +/******************* Bit definition for I2C_CR2 register ********************/ +#define I2C_CR2_FREQ ((uint16_t)0x003F) /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */ +#define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /*!< Bit 4 */ +#define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /*!< Bit 5 */ + +#define I2C_CR2_ITERREN ((uint16_t)0x0100) /*!< Error Interrupt Enable */ +#define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /*!< Event Interrupt Enable */ +#define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /*!< Buffer Interrupt Enable */ +#define I2C_CR2_DMAEN ((uint16_t)0x0800) /*!< DMA Requests Enable */ +#define I2C_CR2_LAST ((uint16_t)0x1000) /*!< DMA Last Transfer */ + +/******************* Bit definition for I2C_OAR1 register *******************/ +#define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /*!< Interface Address */ +#define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /*!< Interface Address */ + +#define I2C_OAR1_ADD0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define I2C_OAR1_ADD1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define I2C_OAR1_ADD2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define I2C_OAR1_ADD3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define I2C_OAR1_ADD4 ((uint16_t)0x0010) /*!< Bit 4 */ +#define I2C_OAR1_ADD5 ((uint16_t)0x0020) /*!< Bit 5 */ +#define I2C_OAR1_ADD6 ((uint16_t)0x0040) /*!< Bit 6 */ +#define I2C_OAR1_ADD7 ((uint16_t)0x0080) /*!< Bit 7 */ +#define I2C_OAR1_ADD8 ((uint16_t)0x0100) /*!< Bit 8 */ +#define I2C_OAR1_ADD9 ((uint16_t)0x0200) /*!< Bit 9 */ + +#define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /*!< Addressing Mode (Slave mode) */ + +/******************* Bit definition for I2C_OAR2 register *******************/ +#define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!< Dual addressing mode enable */ +#define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!< Interface address */ + +/******************** Bit definition for I2C_DR register ********************/ +#define I2C_DR_DR ((uint8_t)0xFF) /*!< 8-bit Data Register */ + +/******************* Bit definition for I2C_SR1 register ********************/ +#define I2C_SR1_SB ((uint16_t)0x0001) /*!< Start Bit (Master mode) */ +#define I2C_SR1_ADDR ((uint16_t)0x0002) /*!< Address sent (master mode)/matched (slave mode) */ +#define I2C_SR1_BTF ((uint16_t)0x0004) /*!< Byte Transfer Finished */ +#define I2C_SR1_ADD10 ((uint16_t)0x0008) /*!< 10-bit header sent (Master mode) */ +#define I2C_SR1_STOPF ((uint16_t)0x0010) /*!< Stop detection (Slave mode) */ +#define I2C_SR1_RXNE ((uint16_t)0x0040) /*!< Data Register not Empty (receivers) */ +#define I2C_SR1_TXE ((uint16_t)0x0080) /*!< Data Register Empty (transmitters) */ +#define I2C_SR1_BERR ((uint16_t)0x0100) /*!< Bus Error */ +#define I2C_SR1_ARLO ((uint16_t)0x0200) /*!< Arbitration Lost (master mode) */ +#define I2C_SR1_AF ((uint16_t)0x0400) /*!< Acknowledge Failure */ +#define I2C_SR1_OVR ((uint16_t)0x0800) /*!< Overrun/Underrun */ +#define I2C_SR1_PECERR ((uint16_t)0x1000) /*!< PEC Error in reception */ +#define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /*!< Timeout or Tlow Error */ +#define I2C_SR1_SMBALERT ((uint16_t)0x8000) /*!< SMBus Alert */ + +/******************* Bit definition for I2C_SR2 register ********************/ +#define I2C_SR2_MSL ((uint16_t)0x0001) /*!< Master/Slave */ +#define I2C_SR2_BUSY ((uint16_t)0x0002) /*!< Bus Busy */ +#define I2C_SR2_TRA ((uint16_t)0x0004) /*!< Transmitter/Receiver */ +#define I2C_SR2_GENCALL ((uint16_t)0x0010) /*!< General Call Address (Slave mode) */ +#define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /*!< SMBus Device Default Address (Slave mode) */ +#define I2C_SR2_SMBHOST ((uint16_t)0x0040) /*!< SMBus Host Header (Slave mode) */ +#define I2C_SR2_DUALF ((uint16_t)0x0080) /*!< Dual Flag (Slave mode) */ +#define I2C_SR2_PEC ((uint16_t)0xFF00) /*!< Packet Error Checking Register */ + +/******************* Bit definition for I2C_CCR register ********************/ +#define I2C_CCR_CCR ((uint16_t)0x0FFF) /*!< Clock Control Register in Fast/Standard mode (Master mode) */ +#define I2C_CCR_DUTY ((uint16_t)0x4000) /*!< Fast Mode Duty Cycle */ +#define I2C_CCR_FS ((uint16_t)0x8000) /*!< I2C Master Mode Selection */ + +/****************** Bit definition for I2C_TRISE register *******************/ +#define I2C_TRISE_TRISE ((uint8_t)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */ + +/******************************************************************************/ +/* */ +/* Universal Synchronous Asynchronous Receiver Transmitter */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for USART_SR register *******************/ +#define USART_SR_PE ((uint16_t)0x0001) /*!< Parity Error */ +#define USART_SR_FE ((uint16_t)0x0002) /*!< Framing Error */ +#define USART_SR_NE ((uint16_t)0x0004) /*!< Noise Error Flag */ +#define USART_SR_ORE ((uint16_t)0x0008) /*!< OverRun Error */ +#define USART_SR_IDLE ((uint16_t)0x0010) /*!< IDLE line detected */ +#define USART_SR_RXNE ((uint16_t)0x0020) /*!< Read Data Register Not Empty */ +#define USART_SR_TC ((uint16_t)0x0040) /*!< Transmission Complete */ +#define USART_SR_TXE ((uint16_t)0x0080) /*!< Transmit Data Register Empty */ +#define USART_SR_LBD ((uint16_t)0x0100) /*!< LIN Break Detection Flag */ +#define USART_SR_CTS ((uint16_t)0x0200) /*!< CTS Flag */ + +/******************* Bit definition for USART_DR register *******************/ +#define USART_DR_DR ((uint16_t)0x01FF) /*!< Data value */ + +/****************** Bit definition for USART_BRR register *******************/ +#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /*!< Fraction of USARTDIV */ +#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /*!< Mantissa of USARTDIV */ + +/****************** Bit definition for USART_CR1 register *******************/ +#define USART_CR1_SBK ((uint16_t)0x0001) /*!< Send Break */ +#define USART_CR1_RWU ((uint16_t)0x0002) /*!< Receiver wakeup */ +#define USART_CR1_RE ((uint16_t)0x0004) /*!< Receiver Enable */ +#define USART_CR1_TE ((uint16_t)0x0008) /*!< Transmitter Enable */ +#define USART_CR1_IDLEIE ((uint16_t)0x0010) /*!< IDLE Interrupt Enable */ +#define USART_CR1_RXNEIE ((uint16_t)0x0020) /*!< RXNE Interrupt Enable */ +#define USART_CR1_TCIE ((uint16_t)0x0040) /*!< Transmission Complete Interrupt Enable */ +#define USART_CR1_TXEIE ((uint16_t)0x0080) /*!< PE Interrupt Enable */ +#define USART_CR1_PEIE ((uint16_t)0x0100) /*!< PE Interrupt Enable */ +#define USART_CR1_PS ((uint16_t)0x0200) /*!< Parity Selection */ +#define USART_CR1_PCE ((uint16_t)0x0400) /*!< Parity Control Enable */ +#define USART_CR1_WAKE ((uint16_t)0x0800) /*!< Wakeup method */ +#define USART_CR1_M ((uint16_t)0x1000) /*!< Word length */ +#define USART_CR1_UE ((uint16_t)0x2000) /*!< USART Enable */ +#define USART_CR1_OVER8 ((uint16_t)0x8000) /*!< USART Oversmapling 8-bits */ + +/****************** Bit definition for USART_CR2 register *******************/ +#define USART_CR2_ADD ((uint16_t)0x000F) /*!< Address of the USART node */ +#define USART_CR2_LBDL ((uint16_t)0x0020) /*!< LIN Break Detection Length */ +#define USART_CR2_LBDIE ((uint16_t)0x0040) /*!< LIN Break Detection Interrupt Enable */ +#define USART_CR2_LBCL ((uint16_t)0x0100) /*!< Last Bit Clock pulse */ +#define USART_CR2_CPHA ((uint16_t)0x0200) /*!< Clock Phase */ +#define USART_CR2_CPOL ((uint16_t)0x0400) /*!< Clock Polarity */ +#define USART_CR2_CLKEN ((uint16_t)0x0800) /*!< Clock Enable */ + +#define USART_CR2_STOP ((uint16_t)0x3000) /*!< STOP[1:0] bits (STOP bits) */ +#define USART_CR2_STOP_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define USART_CR2_STOP_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define USART_CR2_LINEN ((uint16_t)0x4000) /*!< LIN mode enable */ + +/****************** Bit definition for USART_CR3 register *******************/ +#define USART_CR3_EIE ((uint16_t)0x0001) /*!< Error Interrupt Enable */ +#define USART_CR3_IREN ((uint16_t)0x0002) /*!< IrDA mode Enable */ +#define USART_CR3_IRLP ((uint16_t)0x0004) /*!< IrDA Low-Power */ +#define USART_CR3_HDSEL ((uint16_t)0x0008) /*!< Half-Duplex Selection */ +#define USART_CR3_NACK ((uint16_t)0x0010) /*!< Smartcard NACK enable */ +#define USART_CR3_SCEN ((uint16_t)0x0020) /*!< Smartcard mode enable */ +#define USART_CR3_DMAR ((uint16_t)0x0040) /*!< DMA Enable Receiver */ +#define USART_CR3_DMAT ((uint16_t)0x0080) /*!< DMA Enable Transmitter */ +#define USART_CR3_RTSE ((uint16_t)0x0100) /*!< RTS Enable */ +#define USART_CR3_CTSE ((uint16_t)0x0200) /*!< CTS Enable */ +#define USART_CR3_CTSIE ((uint16_t)0x0400) /*!< CTS Interrupt Enable */ +#define USART_CR3_ONEBIT ((uint16_t)0x0800) /*!< One Bit method */ + +/****************** Bit definition for USART_GTPR register ******************/ +#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */ +#define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*!< Bit 4 */ +#define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*!< Bit 5 */ +#define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*!< Bit 6 */ +#define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*!< Bit 7 */ + +#define USART_GTPR_GT ((uint16_t)0xFF00) /*!< Guard time value */ + +/******************************************************************************/ +/* */ +/* Debug MCU */ +/* */ +/******************************************************************************/ + +/**************** Bit definition for DBGMCU_IDCODE register *****************/ +#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */ + +#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */ +#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */ +#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */ +#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */ +#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */ +#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */ +#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */ +#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */ +#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */ +#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */ +#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */ +#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */ +#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */ +#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */ + +/****************** Bit definition for DBGMCU_CR register *******************/ +#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */ +#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */ +#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */ +#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /*!< Trace Pin Assignment Control */ + +#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */ +#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +#define DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) /*!< Debug Independent Watchdog stopped when Core is halted */ +#define DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) /*!< Debug Window Watchdog stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) /*!< TIM1 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) /*!< TIM2 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) /*!< TIM3 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) /*!< TIM4 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000) /*!< Debug CAN1 stopped when Core is halted */ +#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) /*!< SMBUS timeout mode stopped when Core is halted */ +#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) /*!< SMBUS timeout mode stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM8_STOP ((uint32_t)0x00020000) /*!< TIM8 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM5_STOP ((uint32_t)0x00040000) /*!< TIM5 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) /*!< TIM6 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) /*!< TIM7 counter stopped when core is halted */ +#define DBGMCU_CR_DBG_CAN2_STOP ((uint32_t)0x00200000) /*!< Debug CAN2 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM15_STOP ((uint32_t)0x00400000) /*!< Debug TIM15 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM16_STOP ((uint32_t)0x00800000) /*!< Debug TIM16 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM17_STOP ((uint32_t)0x01000000) /*!< Debug TIM17 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM12_STOP ((uint32_t)0x02000000) /*!< Debug TIM12 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM13_STOP ((uint32_t)0x04000000) /*!< Debug TIM13 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM14_STOP ((uint32_t)0x08000000) /*!< Debug TIM14 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM9_STOP ((uint32_t)0x10000000) /*!< Debug TIM9 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM10_STOP ((uint32_t)0x20000000) /*!< Debug TIM10 stopped when Core is halted */ +#define DBGMCU_CR_DBG_TIM11_STOP ((uint32_t)0x40000000) /*!< Debug TIM11 stopped when Core is halted */ + +/******************************************************************************/ +/* */ +/* FLASH and Option Bytes Registers */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for FLASH_ACR register ******************/ +#define FLASH_ACR_LATENCY ((uint8_t)0x07) /*!< LATENCY[2:0] bits (Latency) */ +#define FLASH_ACR_LATENCY_0 ((uint8_t)0x00) /*!< Bit 0 */ +#define FLASH_ACR_LATENCY_1 ((uint8_t)0x01) /*!< Bit 0 */ +#define FLASH_ACR_LATENCY_2 ((uint8_t)0x02) /*!< Bit 1 */ + +#define FLASH_ACR_HLFCYA ((uint8_t)0x08) /*!< Flash Half Cycle Access Enable */ +#define FLASH_ACR_PRFTBE ((uint8_t)0x10) /*!< Prefetch Buffer Enable */ +#define FLASH_ACR_PRFTBS ((uint8_t)0x20) /*!< Prefetch Buffer Status */ + +/****************** Bit definition for FLASH_KEYR register ******************/ +#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */ + +/****************** FLASH Keys **********************************************/ +#define RDP_Key ((uint16_t)0x00A5) +#define FLASH_KEY1 ((uint32_t)0x45670123) +#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) + +/***************** Bit definition for FLASH_OPTKEYR register ****************/ +#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */ + +/****************** Bit definition for FLASH_SR register *******************/ +#define FLASH_SR_BSY ((uint8_t)0x01) /*!< Busy */ +#define FLASH_SR_PGERR ((uint8_t)0x04) /*!< Programming Error */ +#define FLASH_SR_WRPRTERR ((uint8_t)0x10) /*!< Write Protection Error */ +#define FLASH_SR_EOP ((uint8_t)0x20) /*!< End of operation */ + +/******************* Bit definition for FLASH_CR register *******************/ +#define FLASH_CR_PG ((uint16_t)0x0001) /*!< Programming */ +#define FLASH_CR_PER ((uint16_t)0x0002) /*!< Page Erase */ +#define FLASH_CR_MER ((uint16_t)0x0004) /*!< Mass Erase */ +#define FLASH_CR_OPTPG ((uint16_t)0x0010) /*!< Option Byte Programming */ +#define FLASH_CR_OPTER ((uint16_t)0x0020) /*!< Option Byte Erase */ +#define FLASH_CR_STRT ((uint16_t)0x0040) /*!< Start */ +#define FLASH_CR_LOCK ((uint16_t)0x0080) /*!< Lock */ +#define FLASH_CR_OPTWRE ((uint16_t)0x0200) /*!< Option Bytes Write Enable */ +#define FLASH_CR_ERRIE ((uint16_t)0x0400) /*!< Error Interrupt Enable */ +#define FLASH_CR_EOPIE ((uint16_t)0x1000) /*!< End of operation interrupt enable */ + +/******************* Bit definition for FLASH_AR register *******************/ +#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */ + +/****************** Bit definition for FLASH_OBR register *******************/ +#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /*!< Option Byte Error */ +#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /*!< Read protection */ + +#define FLASH_OBR_USER ((uint16_t)0x03FC) /*!< User Option Bytes */ +#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /*!< WDG_SW */ +#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /*!< nRST_STOP */ +#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /*!< nRST_STDBY */ +#define FLASH_OBR_BFB2 ((uint16_t)0x0020) /*!< BFB2 */ + +/****************** Bit definition for FLASH_WRPR register ******************/ +#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */ + +/*----------------------------------------------------------------------------*/ + +/****************** Bit definition for FLASH_RDP register *******************/ +#define FLASH_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */ +#define FLASH_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */ + +/****************** Bit definition for FLASH_USER register ******************/ +#define FLASH_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */ +#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */ + +/****************** Bit definition for FLASH_Data0 register *****************/ +#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /*!< User data storage option byte */ +#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /*!< User data storage complemented option byte */ + +/****************** Bit definition for FLASH_Data1 register *****************/ +#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /*!< User data storage option byte */ +#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /*!< User data storage complemented option byte */ + +/****************** Bit definition for FLASH_WRP0 register ******************/ +#define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ +#define FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRP1 register ******************/ +#define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ +#define FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRP2 register ******************/ +#define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ +#define FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRP3 register ******************/ +#define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ +#define FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ + +#ifdef STM32F10X_CL +/******************************************************************************/ +/* Ethernet MAC Registers bits definitions */ +/******************************************************************************/ +/* Bit definition for Ethernet MAC Control Register register */ +#define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */ +#define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */ +#define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */ + #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */ + #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */ + #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */ + #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */ + #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */ + #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */ + #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */ + #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */ +#define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */ +#define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */ +#define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */ +#define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */ +#define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */ +#define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */ +#define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */ +#define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */ +#define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling + a transmission attempt during retries after a collision: 0 =< r <2^k */ + #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */ + #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */ + #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */ + #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */ +#define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */ +#define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */ +#define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */ + +/* Bit definition for Ethernet MAC Frame Filter Register */ +#define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */ +#define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */ +#define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */ +#define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */ +#define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */ + #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */ + #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ + #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ +#define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */ +#define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */ +#define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */ +#define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */ +#define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */ +#define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */ + +/* Bit definition for Ethernet MAC Hash Table High Register */ +#define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */ + +/* Bit definition for Ethernet MAC Hash Table Low Register */ +#define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */ + +/* Bit definition for Ethernet MAC MII Address Register */ +#define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */ +#define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */ +#define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */ + #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-72 MHz; MDC clock= HCLK/42 */ + #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ + #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */ +#define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */ +#define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */ + +/* Bit definition for Ethernet MAC MII Data Register */ +#define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */ + +/* Bit definition for Ethernet MAC Flow Control Register */ +#define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */ +#define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */ +#define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */ + #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ + #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */ + #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */ + #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */ +#define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */ +#define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */ +#define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */ +#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */ + +/* Bit definition for Ethernet MAC VLAN Tag Register */ +#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */ +#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */ + +/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ +#define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */ +/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers. + Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */ +/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask + Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask + Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask + Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask + Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - + RSVD - Filter1 Command - RSVD - Filter0 Command + Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset + Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16 + Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */ + +/* Bit definition for Ethernet MAC PMT Control and Status Register */ +#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */ +#define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */ +#define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */ +#define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */ +#define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */ +#define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */ +#define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */ + +/* Bit definition for Ethernet MAC Status Register */ +#define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */ +#define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */ +#define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */ +#define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */ +#define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */ + +/* Bit definition for Ethernet MAC Interrupt Mask Register */ +#define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */ +#define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */ + +/* Bit definition for Ethernet MAC Address0 High Register */ +#define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */ + +/* Bit definition for Ethernet MAC Address0 Low Register */ +#define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */ + +/* Bit definition for Ethernet MAC Address1 High Register */ +#define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */ +#define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */ +#define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ + #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ + #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ + #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ + #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ + #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ + #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ +#define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */ + +/* Bit definition for Ethernet MAC Address1 Low Register */ +#define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */ + +/* Bit definition for Ethernet MAC Address2 High Register */ +#define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */ +#define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */ +#define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ + #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ + #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ + #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ + #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ + #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ + #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ +#define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */ + +/* Bit definition for Ethernet MAC Address2 Low Register */ +#define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */ + +/* Bit definition for Ethernet MAC Address3 High Register */ +#define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */ +#define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */ +#define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ + #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ + #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ + #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ + #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ + #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ + #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ +#define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */ + +/* Bit definition for Ethernet MAC Address3 Low Register */ +#define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */ + +/******************************************************************************/ +/* Ethernet MMC Registers bits definition */ +/******************************************************************************/ + +/* Bit definition for Ethernet MMC Contol Register */ +#define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */ +#define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */ +#define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */ +#define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */ + +/* Bit definition for Ethernet MMC Receive Interrupt Register */ +#define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */ +#define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */ +#define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */ + +/* Bit definition for Ethernet MMC Transmit Interrupt Register */ +#define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */ +#define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */ +#define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */ + +/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */ +#define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */ +#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */ +#define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */ + +/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */ +#define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */ +#define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */ +#define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */ + +/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */ +#define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */ + +/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */ +#define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */ + +/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */ +#define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */ + +/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */ +#define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */ + +/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */ +#define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */ + +/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */ +#define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */ + +/******************************************************************************/ +/* Ethernet PTP Registers bits definition */ +/******************************************************************************/ + +/* Bit definition for Ethernet PTP Time Stamp Contol Register */ +#define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */ +#define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */ +#define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */ +#define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */ +#define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */ +#define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */ + +/* Bit definition for Ethernet PTP Sub-Second Increment Register */ +#define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */ + +/* Bit definition for Ethernet PTP Time Stamp High Register */ +#define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */ + +/* Bit definition for Ethernet PTP Time Stamp Low Register */ +#define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */ +#define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */ + +/* Bit definition for Ethernet PTP Time Stamp High Update Register */ +#define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */ + +/* Bit definition for Ethernet PTP Time Stamp Low Update Register */ +#define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */ +#define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */ + +/* Bit definition for Ethernet PTP Time Stamp Addend Register */ +#define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */ + +/* Bit definition for Ethernet PTP Target Time High Register */ +#define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */ + +/* Bit definition for Ethernet PTP Target Time Low Register */ +#define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */ + +/******************************************************************************/ +/* Ethernet DMA Registers bits definition */ +/******************************************************************************/ + +/* Bit definition for Ethernet DMA Bus Mode Register */ +#define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */ +#define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */ +#define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */ +#define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */ + #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ + #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ + #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ + #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ + #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ + #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ + #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ + #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ + #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ + #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ + #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ + #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ +#define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */ +#define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ +#define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */ + #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ + #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ + #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ + #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ + #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ + #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ + #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ + #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ + #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ + #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ + #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ + #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ +#define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */ +#define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */ +#define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */ + +/* Bit definition for Ethernet DMA Transmit Poll Demand Register */ +#define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */ + +/* Bit definition for Ethernet DMA Receive Poll Demand Register */ +#define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */ + +/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */ +#define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */ + +/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */ +#define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */ + +/* Bit definition for Ethernet DMA Status Register */ +#define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */ +#define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */ +#define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */ +#define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */ + /* combination with EBS[2:0] for GetFlagStatus function */ + #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ + #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ + #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ +#define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */ + #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ + #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */ + #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */ + #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */ + #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */ + #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */ +#define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */ + #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ + #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */ + #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */ + #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */ + #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */ + #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */ +#define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */ +#define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */ +#define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */ +#define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */ +#define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */ +#define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */ +#define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */ +#define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */ +#define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */ +#define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */ +#define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */ +#define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */ +#define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */ +#define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */ +#define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */ + +/* Bit definition for Ethernet DMA Operation Mode Register */ +#define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */ +#define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */ +#define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */ +#define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */ +#define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */ +#define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */ + #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ + #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ + #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ + #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ + #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ + #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ + #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ + #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ +#define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */ +#define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */ +#define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */ +#define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */ + #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ + #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ + #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ + #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ +#define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */ +#define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */ + +/* Bit definition for Ethernet DMA Interrupt Enable Register */ +#define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */ +#define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */ +#define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */ +#define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */ +#define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */ +#define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */ +#define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */ +#define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */ +#define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */ +#define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */ +#define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */ +#define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */ +#define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */ +#define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */ +#define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */ + +/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */ +#define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */ +#define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */ +#define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */ +#define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */ + +/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */ +#define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */ + +/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */ +#define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */ + +/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */ +#define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */ + +/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */ +#define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */ +#endif /* STM32F10X_CL */ + +/** + * @} + */ + + /** + * @} + */ + +#ifdef USE_STDPERIPH_DRIVER + #include "stm32f10x_conf.h" +#endif + +/** @addtogroup Exported_macro + * @{ + */ + +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32F10x_H */ + +/** + * @} + */ + + /** + * @} + */ + diff --git a/USER/stm32f10x_conf.h b/USER/stm32f10x_conf.h new file mode 100644 index 0000000..a95acc4 --- /dev/null +++ b/USER/stm32f10x_conf.h @@ -0,0 +1,75 @@ +/** + ****************************************************************************** + * @file Project/STM32F10x_StdPeriph_Template/stm32f10x_conf.h + * @author MCD Application Team + * @version V3.6.0 + * @date 20-September-2021 + * @brief Library configuration file. + ****************************************************************************** + * @attention + * + * Copyright (c) 2011 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_CONF_H +#define __STM32F10x_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */ +#include "stm32f10x_adc.h" +#include "stm32f10x_bkp.h" +#include "stm32f10x_can.h" +#include "stm32f10x_cec.h" +#include "stm32f10x_crc.h" +#include "stm32f10x_dac.h" +#include "stm32f10x_dbgmcu.h" +#include "stm32f10x_dma.h" +#include "stm32f10x_exti.h" +#include "stm32f10x_flash.h" +#include "stm32f10x_fsmc.h" +#include "stm32f10x_gpio.h" +#include "stm32f10x_i2c.h" +#include "stm32f10x_iwdg.h" +#include "stm32f10x_pwr.h" +#include "stm32f10x_rcc.h" +#include "stm32f10x_rtc.h" +#include "stm32f10x_sdio.h" +#include "stm32f10x_spi.h" +#include "stm32f10x_tim.h" +#include "stm32f10x_usart.h" +#include "stm32f10x_wwdg.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function which reports + * the name of the source file and the source line number of the call + * that failed. If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F10x_CONF_H */ + diff --git a/USER/stm32f10x_it.c b/USER/stm32f10x_it.c new file mode 100644 index 0000000..8208294 --- /dev/null +++ b/USER/stm32f10x_it.c @@ -0,0 +1,166 @@ +/** + ****************************************************************************** + * @file Project/STM32F10x_StdPeriph_Template/stm32f10x_it.c + * @author MCD Application Team + * @version V3.6.0 + * @date 20-September-2021 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and + * peripherals interrupt service routine. + ****************************************************************************** + * @attention + * + * Copyright (c) 2011 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_it.h" + +/** @addtogroup STM32F10x_StdPeriph_Template + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + //执行软件重启 + NVIC_SystemReset(); + + //备用：软件复位失效时，触发IWDG复位 + IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable); // 解锁写访问 + IWDG_SetReload(1); // 重载值设为1 + IWDG_ReloadCounter(); // 喂狗，计数器重置为1 + + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* STM32F10x Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f10x_xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + + diff --git a/USER/stm32f10x_it.h b/USER/stm32f10x_it.h new file mode 100644 index 0000000..cb075d7 --- /dev/null +++ b/USER/stm32f10x_it.h @@ -0,0 +1,52 @@ +/** + ****************************************************************************** + * @file Project/STM32F10x_StdPeriph_Template/stm32f10x_it.h + * @author MCD Application Team + * @version V3.6.0 + * @date 20-September-2021 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + * Copyright (c) 2011 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_IT_H +#define __STM32F10x_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_IT_H */ + diff --git a/USER/system_stm32f10x.c b/USER/system_stm32f10x.c new file mode 100644 index 0000000..6c98c01 --- /dev/null +++ b/USER/system_stm32f10x.c @@ -0,0 +1,1149 @@ +/** + ****************************************************************************** + * @file system_stm32f10x.c + * @author MCD Application Team + * @version V3.5.1 + * @date 08-September-2021 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * factors, AHB/APBx prescalers and Flash settings). + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f10x_xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (8 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on + * the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. + * When HSE is used as system clock source, directly or through PLL, and you + * are using different crystal you have to adapt the HSE value to your own + * configuration. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2011 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f10x_system + * @{ + */ + +/** @addtogroup STM32F10x_System_Private_Includes + * @{ + */ + +#include "stm32f10x.h" + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Defines + * @{ + */ + +/*!< Uncomment the line corresponding to the desired System clock (SYSCLK) + frequency (after reset the HSI is used as SYSCLK source) + + IMPORTANT NOTE: + ============== + 1. After each device reset the HSI is used as System clock source. + + 2. Please make sure that the selected System clock doesn't exceed your device's + maximum frequency. + + 3. If none of the define below is enabled, the HSI is used as System clock + source. + + 4. The System clock configuration functions provided within this file assume that: + - For Low, Medium and High density Value line devices an external 8MHz + crystal is used to drive the System clock. + - For Low, Medium and High density devices an external 8MHz crystal is + used to drive the System clock. + - For Connectivity line devices an external 25MHz crystal is used to drive + the System clock. + If you are using different crystal you have to adapt those functions accordingly. + */ + +#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ + #define SYSCLK_FREQ_24MHz 24000000 +#else +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ +/* #define SYSCLK_FREQ_24MHz 24000000 */ +/* #define SYSCLK_FREQ_36MHz 36000000 */ +/* #define SYSCLK_FREQ_48MHz 48000000 */ +/* #define SYSCLK_FREQ_56MHz 56000000 */ + #define SYSCLK_FREQ_72MHz 72000000 +/*#define SYSCLK_FREQ_36MHz_HSI 36000000*/ +#endif + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM3210E-EVAL board (STM32 High density and XL-density devices) or on + STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) +/* #define DATA_IN_ExtSRAM */ +#endif + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Variables + * @{ + */ + +/******************************************************************************* +* Clock Definitions +*******************************************************************************/ +#ifdef SYSCLK_FREQ_HSE + uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_24MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_36MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_36MHz_HSI + uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz_HSI; /*!< System Clock Frequency (Core Clock) */ +#else /*!< HSI Selected as System Clock source */ + uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */ +#endif + +__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); + +#ifdef SYSCLK_FREQ_HSE + static void SetSysClockToHSE(void); +#elif defined SYSCLK_FREQ_24MHz + static void SetSysClockTo24(void); +#elif defined SYSCLK_FREQ_36MHz + static void SetSysClockTo36(void); +#elif defined SYSCLK_FREQ_48MHz + static void SetSysClockTo48(void); +#elif defined SYSCLK_FREQ_56MHz + static void SetSysClockTo56(void); +#elif defined SYSCLK_FREQ_72MHz + static void SetSysClockTo72(void); +#elif defined SYSCLK_FREQ_36MHz_HSI + static void SetSysClockTo36_HSI(void); +#endif + +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemCoreClock variable. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +void SystemInit (void) +{ + /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ +#ifndef STM32F10X_CL + RCC->CFGR &= (uint32_t)0xF8FF0000; +#else + RCC->CFGR &= (uint32_t)0xF0FF0000; +#endif /* STM32F10X_CL */ + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ + RCC->CFGR &= (uint32_t)0xFF80FFFF; + +#ifdef STM32F10X_CL + /* Reset PLL2ON and PLL3ON bits */ + RCC->CR &= (uint32_t)0xEBFFFFFF; + + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x00FF0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#else + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) + #ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); + #endif /* DATA_IN_ExtSRAM */ +#endif + + /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ + /* Configure the Flash Latency cycles and enable prefetch buffer */ + SetSysClock(); + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz or 25 MHz, depending on the product used), user has to ensure + * that HSE_VALUE is same as the real frequency of the crystal used. + * Otherwise, this function may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0; + +#ifdef STM32F10X_CL + uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + uint32_t prediv1factor = 0; +#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */ + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock */ + + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + +#ifndef STM32F10X_CL + pllmull = ( pllmull >> 18) + 2; + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + { + #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + #else + /* HSE selected as PLL clock entry */ + if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) + {/* HSE oscillator clock divided by 2 */ + SystemCoreClock = (HSE_VALUE >> 1) * pllmull; + } + else + { + SystemCoreClock = HSE_VALUE * pllmull; + } + #endif + } +#else + pllmull = pllmull >> 18; + + if (pllmull != 0x0D) + { + pllmull += 2; + } + else + { /* PLL multiplication factor = PLL input clock * 6.5 */ + pllmull = 13 / 2; + } + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + {/* PREDIV1 selected as PLL clock entry */ + + /* Get PREDIV1 clock source and division factor */ + prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + + if (prediv1source == 0) + { + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + } + else + {/* PLL2 clock selected as PREDIV1 clock entry */ + + /* Get PREDIV2 division factor and PLL2 multiplication factor */ + prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1; + pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; + SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; + } + } +#endif /* STM32F10X_CL */ + break; + + default: + SystemCoreClock = HSI_VALUE; + break; + } + + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +#ifdef SYSCLK_FREQ_HSE + SetSysClockToHSE(); +#elif defined SYSCLK_FREQ_24MHz + SetSysClockTo24(); +#elif defined SYSCLK_FREQ_36MHz + SetSysClockTo36(); +#elif defined SYSCLK_FREQ_48MHz + SetSysClockTo48(); +#elif defined SYSCLK_FREQ_56MHz + SetSysClockTo56(); +#elif defined SYSCLK_FREQ_72MHz + SetSysClockTo72(); +#elif defined SYSCLK_FREQ_36MHz_HSI + SetSysClockTo36_HSI(); +#endif + + /* If none of the define above is enabled, the HSI is used as System clock + source (default after reset) */ +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f10x.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f10x_xx.s/.c before jump to main. + * This function configures the external SRAM mounted on STM3210E-EVAL + * board (STM32 High density devices). This SRAM will be used as program + * data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is + required, then adjust the Register Addresses */ + + /* Enable FSMC clock */ + RCC->AHBENR = 0x00000114; + + /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ + RCC->APB2ENR = 0x000001E0; + +/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ +/*---------------- SRAM Address lines configuration -------------------------*/ +/*---------------- NOE and NWE configuration --------------------------------*/ +/*---------------- NE3 configuration ----------------------------------------*/ +/*---------------- NBL0, NBL1 configuration ---------------------------------*/ + + GPIOD->CRL = 0x44BB44BB; + GPIOD->CRH = 0xBBBBBBBB; + + GPIOE->CRL = 0xB44444BB; + GPIOE->CRH = 0xBBBBBBBB; + + GPIOF->CRL = 0x44BBBBBB; + GPIOF->CRH = 0xBBBB4444; + + GPIOG->CRL = 0x44BBBBBB; + GPIOG->CRH = 0x44444B44; + +/*---------------- FSMC Configuration ---------------------------------------*/ +/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ + + FSMC_Bank1->BTCR[4] = 0x00001011; + FSMC_Bank1->BTCR[5] = 0x00000200; +} +#endif /* DATA_IN_ExtSRAM */ + +#ifdef SYSCLK_FREQ_HSE +/** + * @brief Selects HSE as System clock source and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockToHSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + +#ifndef STM32F10X_CL + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#else + if (HSE_VALUE <= 24000000) + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; + } + else + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + } +#endif /* STM32F10X_CL */ +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + + /* Select HSE as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; + + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_24MHz +/** + * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo24(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); + + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_36MHz +/** + * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo36(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); + + /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + +#else + /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_48MHz +/** + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo48(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_56MHz +/** + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo56(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL7); +#else + /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7); + +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_72MHz +/** + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo72(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); +#else + /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | + RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_36MHz_HSI +/** + * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo36_HSI(void) +{ + __IO uint32_t HSIStartUpStatus = 0; + + HSIStartUpStatus = RCC->CR & RCC_CR_HSIRDY; + + if (HSIStartUpStatus == RCC_CR_HSIRDY) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + RCC_HCLKConfig(RCC_SYSCLK_Div1); + + RCC_PCLK2Config(RCC_HCLK_Div1); + + RCC_PCLK1Config(RCC_HCLK_Div2); + + RCC_PLLConfig(RCC_PLLSource_HSI_Div2, RCC_PLLMul_9); + + RCC_PLLCmd(ENABLE); + + while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) + {} + + RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); + + while (RCC_GetSYSCLKSource() != 0x08){ + } + } + else + { + while (1) + { + } + } +} + +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/USER/system_stm32f10x.h b/USER/system_stm32f10x.h new file mode 100644 index 0000000..4665723 --- /dev/null +++ b/USER/system_stm32f10x.h @@ -0,0 +1,96 @@ +/** + ****************************************************************************** + * @file system_stm32f10x.h + * @author MCD Application Team + * @version V3.5.1 + * @date 08-September-2021 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. + ****************************************************************************** + * @attention + * + * Copyright (c) 2011 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f10x_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32F10X_H +#define __SYSTEM_STM32F10X_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32F10x_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32F10x_System_Exported_types + * @{ + */ + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32F10X_H */ + +/** + * @} + */ + +/** + * @} + */