247 lines
5.6 KiB
C
247 lines
5.6 KiB
C
/**
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******************************************************************************
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* @file global.h
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* @author Jerry Cai
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* @version V2.1
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* @date 19-April-2022
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* @brief This file contains all the functions prototypes for the GPIO
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* firmware library.
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******************************************************************************
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* @attention
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*
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __AFE_SH3673520_H
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#define __AFE_SH3673520_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f10x.h"
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//#define CALICUR 1000
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//#define CALICUR 30700 //16个4m欧电阻并联
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//#define CALICUR 28000 //16个5m欧电阻并联
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#define REG_ADDR_SCONF1 0x40
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#define REG_ADDR_SCONF2 0x41
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#define REG_ADDR_SCONF3 0x42
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#define REG_ADDR_SCONF4 0x43
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#define REG_ADDR_SCONF5 0x44
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#define REG_ADDR_SCONF6 0x45
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#define REG_ADDR_SCONF7 0x46
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#define REG_ADDR_OWV_ALARMH 0x47
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#define REG_ADDR_ALARML 0x48
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#define REG_ADDR_OVT_OVH 0x49
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#define REG_ADDR_OVL 0x4A
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#define REG_ADDR_UVT_UVL 0x4B
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#define REG_ADDR_UVL 0x4C
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#define REG_ADDR_OCD1V_OCD1T 0x4D
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#define REG_ADDR_OCD2V_OCD2T 0x4E
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#define REG_ADDR_SCV_SCT 0x4F
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#define REG_ADDR_OCCV_OCCT 0x50
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#define REG_ADDR_OTC 0x51
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#define REG_ADDR_OTD 0x52
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#define REG_ADDR_UTC 0x53
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#define REG_ADDR_UTD 0x54
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#define REG_ADDR_BALANCEH 0x55
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#define REG_ADDR_BALANCEM 0x56
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#define REG_ADDR_BALANCEL 0x57
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#define REG_ADDR_FLAG1 0x58
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#define REG_ADDR_FLAG2 0x59
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#define REG_ADDR_FLAG3 0x5A
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#define REG_ADDR_BSTATUS1 0x5B
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#define REG_ADDR_BSTATUS2 0x5C
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#define REG_ADDR_TEMP1H 0x5D
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#define REG_ADDR_TEMP1L 0x5E
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#define REG_ADDR_TEMP2H 0x5F
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#define REG_ADDR_TEMP2L 0x60
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#define REG_ADDR_TEMP3H 0x61
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#define REG_ADDR_TEMP3L 0x62
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#define REG_ADDR_TEMP4H 0x63
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#define REG_ADDR_TEMP4L 0x64
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#define REG_ADDR_TEMPIH 0x65
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#define REG_ADDR_TEMPIL 0x66
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#define REG_ADDR_CURH 0x67
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#define REG_ADDR_CURL 0x68
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#define REG_ADDR_CELL1H 0x69
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#define REG_ADDR_CELL1L 0x6A
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#define REG_ADDR_CELL2H 0x6B
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#define REG_ADDR_CELL2L 0x6C
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#define REG_ADDR_CELL3H 0x6D
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#define REG_ADDR_CELL3L 0x6E
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#define REG_ADDR_CELL4H 0x6F
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#define REG_ADDR_CELL4L 0x70
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#define REG_ADDR_CELL5H 0x71
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#define REG_ADDR_CELL5L 0x72
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#define REG_ADDR_CELL6H 0x73
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#define REG_ADDR_CELL6L 0x74
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#define REG_ADDR_CELL7H 0x75
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#define REG_ADDR_CELL7L 0x76
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#define REG_ADDR_CELL8H 0x77
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#define REG_ADDR_CELL8L 0x78
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#define REG_ADDR_CELL9H 0x79
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#define REG_ADDR_CELL9L 0x7A
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#define REG_ADDR_CELL10H 0X7B
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#define REG_ADDR_CELL10L 0X7C
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#define REG_ADDR_CELL11H 0X7D
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#define REG_ADDR_CELL11L 0X7E
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#define REG_ADDR_CELL12H 0X7F
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#define REG_ADDR_CELL12L 0X80
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#define REG_ADDR_CELL13H 0X81
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#define REG_ADDR_CELL13L 0X82
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#define REG_ADDR_CELL14H 0X83
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#define REG_ADDR_CELL14L 0X84
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#define REG_ADDR_CELL15H 0X85
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#define REG_ADDR_CELL15L 0X86
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#define REG_ADDR_CELL16H 0X87
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#define REG_ADDR_CELL16L 0X88
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#define REG_ADDR_CELL17H 0X89
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#define REG_ADDR_CELL17L 0X8A
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#define REG_ADDR_CELL18H 0X8B
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#define REG_ADDR_CELL18L 0X8C
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#define REG_ADDR_CELL19H 0X8D
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#define REG_ADDR_CELL19L 0X8E
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#define REG_ADDR_CELL20H 0X8F
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#define REG_ADDR_CELL20L 0X90
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#define REG_ADDR_CADCDH 0x91
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#define REG_ADDR_CADCDL 0x92
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#define REG_ADDR_VTOPH 0x93
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#define REG_ADDR_VTOPL 0x94
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#define REG_ADDR_VCHGRH 0x95
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#define REG_ADDR_VCHGRL 0x96
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#define REG_ADDR_OWDH 0x97
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#define REG_ADDR_OWDM 0x98
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#define REG_ADDR_OWDL 0x99
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//AFE RAM Register
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typedef struct
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{
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uint8_t sconf1;
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uint8_t sconf2;
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uint8_t sconf3;
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uint8_t sconf4;
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uint8_t sconf5;
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uint8_t sconf6;
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uint8_t sconf7;
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uint8_t owv_alarmh;
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uint8_t alarml;
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uint8_t ovt_ovh;
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uint8_t ovl;
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uint8_t uvt_uvh;
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uint8_t uvl;
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uint8_t ocd1v_ocd1t;
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uint8_t ocd2v_ocd2t;
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uint8_t scv_sct;
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uint8_t occv_occt;
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uint8_t otc;
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uint8_t otd;
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uint8_t utc;
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uint8_t utd;
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uint8_t balanceh;
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uint8_t balancem;
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uint8_t balancel;
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uint8_t flag1;
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uint8_t flag2;
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uint8_t flag3;
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uint8_t bstatus1;
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uint8_t bstatus2;
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uint8_t temp1h;
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uint8_t temp1l;
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uint8_t temp2h;
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uint8_t temp2l;
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uint8_t temp3h;
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uint8_t temp3l;
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uint8_t temp4h;
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uint8_t temp4l;
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uint8_t tempih;
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uint8_t tempil;
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uint8_t curh;
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uint8_t curl;
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uint8_t cell1h;
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uint8_t cell1l;
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uint8_t cell2h;
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uint8_t cell2l;
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uint8_t cell3h;
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uint8_t cell3l;
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uint8_t cell4h;
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uint8_t cell4l;
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uint8_t cell5h;
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uint8_t cell5l;
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uint8_t cell6h;
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uint8_t cell6l;
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uint8_t cell7h;
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uint8_t cell7l;
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uint8_t cell8h;
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uint8_t cell8l;
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uint8_t cell9h;
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uint8_t cell9l;
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uint8_t cell10h;
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uint8_t cell10l;
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uint8_t cell11h;
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uint8_t cell11l;
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uint8_t cell12h;
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uint8_t cell12l;
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uint8_t cell13h;
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uint8_t cell13l;
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uint8_t cell14h;
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uint8_t cell14l;
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uint8_t cell15h;
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uint8_t cell15l;
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uint8_t cell16h;
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uint8_t cell16l;
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uint8_t cell17h;
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uint8_t cell17l;
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uint8_t cell18h;
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uint8_t cell18l;
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uint8_t cell19h;
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uint8_t cell19l;
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uint8_t cell20h;
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uint8_t cell20l;
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uint8_t cadcdh;
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uint8_t cadcdl;
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uint8_t vtoph;
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uint8_t vtopl;
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uint8_t vchgrh;
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uint8_t vchgrl;
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uint8_t owdh;
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uint8_t owdm;
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uint8_t owdl;
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} AFE_RAM;
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//AFE FLG Register
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typedef struct
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{
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uint16_t temp1;
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uint16_t temp2;
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uint16_t temp3;
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uint16_t temp4;
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} AFE_FLG;
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extern AFE_RAM afeRam;
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extern AFE_FLG afeFlg;
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extern void AFE_VoltageProcess(void);
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extern void AFE_CurrentProcess(void);
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extern void AFE_TemperaProcess(void);
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extern void AFE_ProtectProcess(void);
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extern uint8_t MEMORY_UpdateAFE(void);
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extern void InitGasGauge(void);
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#ifdef __cplusplus
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}
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#endif
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#endif
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