/**
  ******************************************************************************
  * @file    global.h
  * @author  Jerry Cai
  * @version V2.1
  * @date    19-April-2022
  * @brief   This file contains all the functions prototypes for the GPIO 
  *          firmware library.
  ******************************************************************************
  * @attention
  *

  *
  ******************************************************************************
  */

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AFE_SH3673520_H
#define __AFE_SH3673520_H

#ifdef __cplusplus
 extern "C" {
#endif

/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"
	 
//#define CALICUR				1000
//#define CALICUR				30700  //16个4m欧电阻并联
//#define CALICUR				28000  //16个5m欧电阻并联
	 
#define REG_ADDR_SCONF1				0x40
#define REG_ADDR_SCONF2				0x41
#define REG_ADDR_SCONF3				0x42
#define REG_ADDR_SCONF4				0x43
#define REG_ADDR_SCONF5				0x44
#define REG_ADDR_SCONF6				0x45
#define REG_ADDR_SCONF7				0x46
#define REG_ADDR_OWV_ALARMH		0x47
#define REG_ADDR_ALARML				0x48
#define REG_ADDR_OVT_OVH			0x49
#define REG_ADDR_OVL					0x4A
#define REG_ADDR_UVT_UVL			0x4B
#define REG_ADDR_UVL					0x4C
#define REG_ADDR_OCD1V_OCD1T	0x4D
#define REG_ADDR_OCD2V_OCD2T	0x4E
#define REG_ADDR_SCV_SCT			0x4F
#define REG_ADDR_OCCV_OCCT		0x50
#define REG_ADDR_OTC					0x51
#define REG_ADDR_OTD					0x52
#define REG_ADDR_UTC					0x53
#define REG_ADDR_UTD					0x54
#define REG_ADDR_BALANCEH			0x55
#define REG_ADDR_BALANCEM			0x56
#define REG_ADDR_BALANCEL			0x57
#define REG_ADDR_FLAG1				0x58
#define REG_ADDR_FLAG2				0x59
#define REG_ADDR_FLAG3				0x5A
#define REG_ADDR_BSTATUS1			0x5B
#define REG_ADDR_BSTATUS2			0x5C
#define REG_ADDR_TEMP1H				0x5D
#define REG_ADDR_TEMP1L				0x5E
#define REG_ADDR_TEMP2H				0x5F
#define REG_ADDR_TEMP2L				0x60
#define REG_ADDR_TEMP3H				0x61
#define REG_ADDR_TEMP3L				0x62
#define REG_ADDR_TEMP4H				0x63
#define REG_ADDR_TEMP4L				0x64
#define REG_ADDR_TEMPIH				0x65
#define REG_ADDR_TEMPIL				0x66
#define REG_ADDR_CURH					0x67
#define REG_ADDR_CURL					0x68
#define REG_ADDR_CELL1H				0x69
#define REG_ADDR_CELL1L				0x6A
#define REG_ADDR_CELL2H				0x6B
#define REG_ADDR_CELL2L				0x6C
#define REG_ADDR_CELL3H				0x6D
#define REG_ADDR_CELL3L				0x6E
#define REG_ADDR_CELL4H				0x6F
#define REG_ADDR_CELL4L				0x70
#define REG_ADDR_CELL5H				0x71
#define REG_ADDR_CELL5L				0x72
#define REG_ADDR_CELL6H				0x73
#define REG_ADDR_CELL6L				0x74
#define REG_ADDR_CELL7H				0x75
#define REG_ADDR_CELL7L				0x76
#define REG_ADDR_CELL8H				0x77
#define REG_ADDR_CELL8L				0x78
#define REG_ADDR_CELL9H				0x79
#define REG_ADDR_CELL9L				0x7A
#define REG_ADDR_CELL10H			0X7B
#define REG_ADDR_CELL10L			0X7C
#define REG_ADDR_CELL11H			0X7D
#define REG_ADDR_CELL11L			0X7E
#define REG_ADDR_CELL12H			0X7F
#define REG_ADDR_CELL12L			0X80
#define REG_ADDR_CELL13H			0X81
#define REG_ADDR_CELL13L			0X82
#define REG_ADDR_CELL14H			0X83
#define REG_ADDR_CELL14L			0X84
#define REG_ADDR_CELL15H			0X85
#define REG_ADDR_CELL15L			0X86
#define REG_ADDR_CELL16H			0X87
#define REG_ADDR_CELL16L			0X88
#define REG_ADDR_CELL17H			0X89
#define REG_ADDR_CELL17L			0X8A
#define REG_ADDR_CELL18H			0X8B
#define REG_ADDR_CELL18L			0X8C
#define REG_ADDR_CELL19H			0X8D
#define REG_ADDR_CELL19L			0X8E
#define REG_ADDR_CELL20H			0X8F
#define REG_ADDR_CELL20L			0X90
#define REG_ADDR_CADCDH				0x91
#define REG_ADDR_CADCDL				0x92
#define REG_ADDR_VTOPH				0x93
#define REG_ADDR_VTOPL				0x94
#define REG_ADDR_VCHGRH				0x95
#define REG_ADDR_VCHGRL				0x96
#define REG_ADDR_OWDH					0x97
#define REG_ADDR_OWDM					0x98
#define REG_ADDR_OWDL					0x99


//AFE RAM Register
typedef struct
{
	uint8_t sconf1;
	uint8_t sconf2;
	uint8_t sconf3;
	uint8_t sconf4;
	uint8_t sconf5;
	uint8_t sconf6;
	uint8_t sconf7;
	uint8_t owv_alarmh;
	uint8_t alarml;
	uint8_t ovt_ovh;
	uint8_t ovl;
	uint8_t uvt_uvh;
	uint8_t uvl;
	uint8_t ocd1v_ocd1t;
	uint8_t ocd2v_ocd2t;
	uint8_t scv_sct;
	uint8_t occv_occt;
	uint8_t otc;
	uint8_t otd;
	uint8_t utc;
	uint8_t utd;
	uint8_t balanceh;
	uint8_t balancem;
	uint8_t balancel;
	uint8_t flag1;
	uint8_t flag2;
	uint8_t flag3;
	uint8_t bstatus1;
	uint8_t bstatus2;
	uint8_t temp1h;
	uint8_t temp1l;
	uint8_t temp2h;
	uint8_t temp2l;
	uint8_t temp3h;
	uint8_t temp3l;
	uint8_t temp4h;
	uint8_t temp4l;
	uint8_t tempih;
	uint8_t tempil;
	uint8_t curh;
	uint8_t curl;
	uint8_t cell1h;
	uint8_t cell1l;
	uint8_t cell2h;
	uint8_t cell2l;
	uint8_t cell3h;
	uint8_t cell3l;
	uint8_t cell4h;
	uint8_t cell4l;
	uint8_t cell5h;
	uint8_t cell5l;
	uint8_t cell6h;
	uint8_t cell6l;
	uint8_t cell7h;
	uint8_t cell7l;
	uint8_t cell8h;
	uint8_t cell8l;
	uint8_t cell9h;
	uint8_t cell9l;
	uint8_t cell10h;
	uint8_t cell10l;
	uint8_t cell11h;
	uint8_t cell11l;
	uint8_t cell12h;
	uint8_t cell12l;
	uint8_t cell13h;
	uint8_t cell13l;
	uint8_t cell14h;
	uint8_t cell14l;
	uint8_t cell15h;
	uint8_t cell15l;
	uint8_t cell16h;
	uint8_t cell16l;
	uint8_t cell17h;
	uint8_t cell17l;
	uint8_t cell18h;
	uint8_t cell18l;
	uint8_t cell19h;
	uint8_t cell19l;
	uint8_t cell20h;
	uint8_t cell20l;
	uint8_t cadcdh;
	uint8_t cadcdl;
	uint8_t vtoph;
	uint8_t vtopl;
	uint8_t vchgrh;
	uint8_t vchgrl;
	uint8_t owdh;
	uint8_t owdm;
	uint8_t owdl;
} AFE_RAM;

//AFE FLG Register
typedef struct
{
	uint16_t temp1;
	uint16_t temp2;
	uint16_t temp3;
	uint16_t temp4;
} AFE_FLG;

extern AFE_RAM afeRam;
extern AFE_FLG afeFlg;


extern void AFE_VoltageProcess(void);
extern void AFE_CurrentProcess(void);
extern void AFE_TemperaProcess(void);
extern void AFE_ProtectProcess(void);
extern uint8_t MEMORY_UpdateAFE(void);

extern void InitGasGauge(void);
	 

#ifdef __cplusplus
}
#endif

#endif